ra6m2_pac/
iic0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.2, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:11:44 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Inter-Integrated Circuit 0"]
28unsafe impl ::core::marker::Send for super::Iic0 {}
29unsafe impl ::core::marker::Sync for super::Iic0 {}
30impl super::Iic0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "I2C Bus Control Register 1"]
38    #[inline(always)]
39    pub const fn iccr1(&self) -> &'static crate::common::Reg<self::Iccr1_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Iccr1_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "I2C Bus Control Register 2"]
48    #[inline(always)]
49    pub const fn iccr2(&self) -> &'static crate::common::Reg<self::Iccr2_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Iccr2_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "I2C Bus Mode Register 1"]
58    #[inline(always)]
59    pub const fn icmr1(&self) -> &'static crate::common::Reg<self::Icmr1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Icmr1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "I2C Bus Mode Register 2"]
68    #[inline(always)]
69    pub const fn icmr2(&self) -> &'static crate::common::Reg<self::Icmr2_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Icmr2_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(3usize),
73            )
74        }
75    }
76
77    #[doc = "I2C Bus Mode Register 3"]
78    #[inline(always)]
79    pub const fn icmr3(&self) -> &'static crate::common::Reg<self::Icmr3_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Icmr3_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(4usize),
83            )
84        }
85    }
86
87    #[doc = "I2C Bus Function Enable Register"]
88    #[inline(always)]
89    pub const fn icfer(&self) -> &'static crate::common::Reg<self::Icfer_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Icfer_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(5usize),
93            )
94        }
95    }
96
97    #[doc = "I2C Bus Status Enable Register"]
98    #[inline(always)]
99    pub const fn icser(&self) -> &'static crate::common::Reg<self::Icser_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Icser_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(6usize),
103            )
104        }
105    }
106
107    #[doc = "I2C Bus Interrupt Enable Register"]
108    #[inline(always)]
109    pub const fn icier(&self) -> &'static crate::common::Reg<self::Icier_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Icier_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(7usize),
113            )
114        }
115    }
116
117    #[doc = "I2C Bus Status Register 1"]
118    #[inline(always)]
119    pub const fn icsr1(&self) -> &'static crate::common::Reg<self::Icsr1_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Icsr1_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(8usize),
123            )
124        }
125    }
126
127    #[doc = "I2C Bus Status Register 2"]
128    #[inline(always)]
129    pub const fn icsr2(&self) -> &'static crate::common::Reg<self::Icsr2_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Icsr2_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(9usize),
133            )
134        }
135    }
136
137    #[doc = "Slave Address Register L%s"]
138    #[inline(always)]
139    pub const fn sarl(
140        &self,
141    ) -> &'static crate::common::ClusterRegisterArray<
142        crate::common::Reg<self::Sarl_SPEC, crate::common::RW>,
143        3,
144        0x2,
145    > {
146        unsafe {
147            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xausize))
148        }
149    }
150    #[inline(always)]
151    pub const fn sarl0(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0xausize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn sarl1(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(0xcusize),
163            )
164        }
165    }
166    #[inline(always)]
167    pub const fn sarl2(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
168        unsafe {
169            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
170                self._svd2pac_as_ptr().add(0xeusize),
171            )
172        }
173    }
174
175    #[doc = "Slave Address Register U%s"]
176    #[inline(always)]
177    pub const fn saru(
178        &self,
179    ) -> &'static crate::common::ClusterRegisterArray<
180        crate::common::Reg<self::Saru_SPEC, crate::common::RW>,
181        3,
182        0x2,
183    > {
184        unsafe {
185            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xbusize))
186        }
187    }
188    #[inline(always)]
189    pub const fn saru0(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
190        unsafe {
191            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
192                self._svd2pac_as_ptr().add(0xbusize),
193            )
194        }
195    }
196    #[inline(always)]
197    pub const fn saru1(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(0xdusize),
201            )
202        }
203    }
204    #[inline(always)]
205    pub const fn saru2(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0xfusize),
209            )
210        }
211    }
212
213    #[doc = "I2C Bus Bit Rate Low-Level Register"]
214    #[inline(always)]
215    pub const fn icbrl(&self) -> &'static crate::common::Reg<self::Icbrl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Icbrl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(16usize),
219            )
220        }
221    }
222
223    #[doc = "I2C Bus Bit Rate High-Level Register"]
224    #[inline(always)]
225    pub const fn icbrh(&self) -> &'static crate::common::Reg<self::Icbrh_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Icbrh_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(17usize),
229            )
230        }
231    }
232
233    #[doc = "I2C Bus Transmit Data Register"]
234    #[inline(always)]
235    pub const fn icdrt(&self) -> &'static crate::common::Reg<self::Icdrt_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Icdrt_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "I2C Bus Receive Data Register"]
244    #[inline(always)]
245    pub const fn icdrr(&self) -> &'static crate::common::Reg<self::Icdrr_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Icdrr_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252
253    #[doc = "I2C Bus Wake Up Unit Register"]
254    #[inline(always)]
255    pub const fn icwur(&self) -> &'static crate::common::Reg<self::Icwur_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Icwur_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(22usize),
259            )
260        }
261    }
262
263    #[doc = "I2C Bus Wake Up Unit Register 2"]
264    #[inline(always)]
265    pub const fn icwur2(&self) -> &'static crate::common::Reg<self::Icwur2_SPEC, crate::common::R> {
266        unsafe {
267            crate::common::Reg::<self::Icwur2_SPEC, crate::common::R>::from_ptr(
268                self._svd2pac_as_ptr().add(23usize),
269            )
270        }
271    }
272}
273#[doc(hidden)]
274#[derive(Copy, Clone, Eq, PartialEq)]
275pub struct Iccr1_SPEC;
276impl crate::sealed::RegSpec for Iccr1_SPEC {
277    type DataType = u8;
278}
279
280#[doc = "I2C Bus Control Register 1"]
281pub type Iccr1 = crate::RegValueT<Iccr1_SPEC>;
282
283impl Iccr1 {
284    #[doc = "I2C Bus Interface Enable"]
285    #[inline(always)]
286    pub fn ice(
287        self,
288    ) -> crate::common::RegisterField<
289        7,
290        0x1,
291        1,
292        0,
293        iccr1::Ice,
294        iccr1::Ice,
295        Iccr1_SPEC,
296        crate::common::RW,
297    > {
298        crate::common::RegisterField::<
299            7,
300            0x1,
301            1,
302            0,
303            iccr1::Ice,
304            iccr1::Ice,
305            Iccr1_SPEC,
306            crate::common::RW,
307        >::from_register(self, 0)
308    }
309
310    #[doc = "I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
311    #[inline(always)]
312    pub fn iicrst(
313        self,
314    ) -> crate::common::RegisterField<
315        6,
316        0x1,
317        1,
318        0,
319        iccr1::Iicrst,
320        iccr1::Iicrst,
321        Iccr1_SPEC,
322        crate::common::RW,
323    > {
324        crate::common::RegisterField::<
325            6,
326            0x1,
327            1,
328            0,
329            iccr1::Iicrst,
330            iccr1::Iicrst,
331            Iccr1_SPEC,
332            crate::common::RW,
333        >::from_register(self, 0)
334    }
335
336    #[doc = "Extra SCL Clock Cycle Output"]
337    #[inline(always)]
338    pub fn clo(
339        self,
340    ) -> crate::common::RegisterField<
341        5,
342        0x1,
343        1,
344        0,
345        iccr1::Clo,
346        iccr1::Clo,
347        Iccr1_SPEC,
348        crate::common::RW,
349    > {
350        crate::common::RegisterField::<
351            5,
352            0x1,
353            1,
354            0,
355            iccr1::Clo,
356            iccr1::Clo,
357            Iccr1_SPEC,
358            crate::common::RW,
359        >::from_register(self, 0)
360    }
361
362    #[doc = "SCLO/SDAO Write Protect"]
363    #[inline(always)]
364    pub fn sowp(
365        self,
366    ) -> crate::common::RegisterField<
367        4,
368        0x1,
369        1,
370        0,
371        iccr1::Sowp,
372        iccr1::Sowp,
373        Iccr1_SPEC,
374        crate::common::W,
375    > {
376        crate::common::RegisterField::<
377            4,
378            0x1,
379            1,
380            0,
381            iccr1::Sowp,
382            iccr1::Sowp,
383            Iccr1_SPEC,
384            crate::common::W,
385        >::from_register(self, 0)
386    }
387
388    #[doc = "SCL Output Control/Monitor"]
389    #[inline(always)]
390    pub fn sclo(
391        self,
392    ) -> crate::common::RegisterField<
393        3,
394        0x1,
395        1,
396        0,
397        iccr1::Sclo,
398        iccr1::Sclo,
399        Iccr1_SPEC,
400        crate::common::RW,
401    > {
402        crate::common::RegisterField::<
403            3,
404            0x1,
405            1,
406            0,
407            iccr1::Sclo,
408            iccr1::Sclo,
409            Iccr1_SPEC,
410            crate::common::RW,
411        >::from_register(self, 0)
412    }
413
414    #[doc = "SDA Output Control/Monitor"]
415    #[inline(always)]
416    pub fn sdao(
417        self,
418    ) -> crate::common::RegisterField<
419        2,
420        0x1,
421        1,
422        0,
423        iccr1::Sdao,
424        iccr1::Sdao,
425        Iccr1_SPEC,
426        crate::common::RW,
427    > {
428        crate::common::RegisterField::<
429            2,
430            0x1,
431            1,
432            0,
433            iccr1::Sdao,
434            iccr1::Sdao,
435            Iccr1_SPEC,
436            crate::common::RW,
437        >::from_register(self, 0)
438    }
439
440    #[doc = "SCL Line Monitor"]
441    #[inline(always)]
442    pub fn scli(
443        self,
444    ) -> crate::common::RegisterField<
445        1,
446        0x1,
447        1,
448        0,
449        iccr1::Scli,
450        iccr1::Scli,
451        Iccr1_SPEC,
452        crate::common::R,
453    > {
454        crate::common::RegisterField::<
455            1,
456            0x1,
457            1,
458            0,
459            iccr1::Scli,
460            iccr1::Scli,
461            Iccr1_SPEC,
462            crate::common::R,
463        >::from_register(self, 0)
464    }
465
466    #[doc = "SDA Line Monitor"]
467    #[inline(always)]
468    pub fn sdai(
469        self,
470    ) -> crate::common::RegisterField<
471        0,
472        0x1,
473        1,
474        0,
475        iccr1::Sdai,
476        iccr1::Sdai,
477        Iccr1_SPEC,
478        crate::common::R,
479    > {
480        crate::common::RegisterField::<
481            0,
482            0x1,
483            1,
484            0,
485            iccr1::Sdai,
486            iccr1::Sdai,
487            Iccr1_SPEC,
488            crate::common::R,
489        >::from_register(self, 0)
490    }
491}
492impl ::core::default::Default for Iccr1 {
493    #[inline(always)]
494    fn default() -> Iccr1 {
495        <crate::RegValueT<Iccr1_SPEC> as RegisterValue<_>>::new(31)
496    }
497}
498pub mod iccr1 {
499
500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
501    pub struct Ice_SPEC;
502    pub type Ice = crate::EnumBitfieldStruct<u8, Ice_SPEC>;
503    impl Ice {
504        #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
505        pub const _0: Self = Self::new(0);
506
507        #[doc = "Enable (SCLn and SDAn pins in active state)"]
508        pub const _1: Self = Self::new(1);
509    }
510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
511    pub struct Iicrst_SPEC;
512    pub type Iicrst = crate::EnumBitfieldStruct<u8, Iicrst_SPEC>;
513    impl Iicrst {
514        #[doc = "Releases the RIIC reset or internal reset."]
515        pub const _0: Self = Self::new(0);
516
517        #[doc = "Initiates the RIIC reset or internal reset."]
518        pub const _1: Self = Self::new(1);
519    }
520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
521    pub struct Clo_SPEC;
522    pub type Clo = crate::EnumBitfieldStruct<u8, Clo_SPEC>;
523    impl Clo {
524        #[doc = "Does not output an extra SCL clock cycle."]
525        pub const _0: Self = Self::new(0);
526
527        #[doc = "Outputs an extra SCL clock cycle."]
528        pub const _1: Self = Self::new(1);
529    }
530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
531    pub struct Sowp_SPEC;
532    pub type Sowp = crate::EnumBitfieldStruct<u8, Sowp_SPEC>;
533    impl Sowp {
534        #[doc = "Enables a value to be written in SCLO bit and SDAO bit."]
535        pub const _0: Self = Self::new(0);
536
537        #[doc = "Disables a value to be written in SCLO bit and SDAO bit."]
538        pub const _1: Self = Self::new(1);
539    }
540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
541    pub struct Sclo_SPEC;
542    pub type Sclo = crate::EnumBitfieldStruct<u8, Sclo_SPEC>;
543    impl Sclo {
544        #[doc = "(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
545        pub const _0: Self = Self::new(0);
546
547        #[doc = "(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
548        pub const _1: Self = Self::new(1);
549    }
550    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
551    pub struct Sdao_SPEC;
552    pub type Sdao = crate::EnumBitfieldStruct<u8, Sdao_SPEC>;
553    impl Sdao {
554        #[doc = "(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
555        pub const _0: Self = Self::new(0);
556
557        #[doc = "(Read)The RIIC has released the SDAn pin./  (Write)The RIIC releases the SDAn pin."]
558        pub const _1: Self = Self::new(1);
559    }
560    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
561    pub struct Scli_SPEC;
562    pub type Scli = crate::EnumBitfieldStruct<u8, Scli_SPEC>;
563    impl Scli {
564        #[doc = "SCLn line is low."]
565        pub const _0: Self = Self::new(0);
566
567        #[doc = "SCLn line is high."]
568        pub const _1: Self = Self::new(1);
569    }
570    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
571    pub struct Sdai_SPEC;
572    pub type Sdai = crate::EnumBitfieldStruct<u8, Sdai_SPEC>;
573    impl Sdai {
574        #[doc = "SDAn line is low."]
575        pub const _0: Self = Self::new(0);
576
577        #[doc = "SDAn line is high."]
578        pub const _1: Self = Self::new(1);
579    }
580}
581#[doc(hidden)]
582#[derive(Copy, Clone, Eq, PartialEq)]
583pub struct Iccr2_SPEC;
584impl crate::sealed::RegSpec for Iccr2_SPEC {
585    type DataType = u8;
586}
587
588#[doc = "I2C Bus Control Register 2"]
589pub type Iccr2 = crate::RegValueT<Iccr2_SPEC>;
590
591impl Iccr2 {
592    #[doc = "Bus Busy Detection Flag"]
593    #[inline(always)]
594    pub fn bbsy(
595        self,
596    ) -> crate::common::RegisterField<
597        7,
598        0x1,
599        1,
600        0,
601        iccr2::Bbsy,
602        iccr2::Bbsy,
603        Iccr2_SPEC,
604        crate::common::R,
605    > {
606        crate::common::RegisterField::<
607            7,
608            0x1,
609            1,
610            0,
611            iccr2::Bbsy,
612            iccr2::Bbsy,
613            Iccr2_SPEC,
614            crate::common::R,
615        >::from_register(self, 0)
616    }
617
618    #[doc = "Master/Slave Mode"]
619    #[inline(always)]
620    pub fn mst(
621        self,
622    ) -> crate::common::RegisterField<
623        6,
624        0x1,
625        1,
626        0,
627        iccr2::Mst,
628        iccr2::Mst,
629        Iccr2_SPEC,
630        crate::common::RW,
631    > {
632        crate::common::RegisterField::<
633            6,
634            0x1,
635            1,
636            0,
637            iccr2::Mst,
638            iccr2::Mst,
639            Iccr2_SPEC,
640            crate::common::RW,
641        >::from_register(self, 0)
642    }
643
644    #[doc = "Transmit/Receive Mode"]
645    #[inline(always)]
646    pub fn trs(
647        self,
648    ) -> crate::common::RegisterField<
649        5,
650        0x1,
651        1,
652        0,
653        iccr2::Trs,
654        iccr2::Trs,
655        Iccr2_SPEC,
656        crate::common::RW,
657    > {
658        crate::common::RegisterField::<
659            5,
660            0x1,
661            1,
662            0,
663            iccr2::Trs,
664            iccr2::Trs,
665            Iccr2_SPEC,
666            crate::common::RW,
667        >::from_register(self, 0)
668    }
669
670    #[doc = "Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued."]
671    #[inline(always)]
672    pub fn sp(
673        self,
674    ) -> crate::common::RegisterField<
675        3,
676        0x1,
677        1,
678        0,
679        iccr2::Sp,
680        iccr2::Sp,
681        Iccr2_SPEC,
682        crate::common::RW,
683    > {
684        crate::common::RegisterField::<
685            3,
686            0x1,
687            1,
688            0,
689            iccr2::Sp,
690            iccr2::Sp,
691            Iccr2_SPEC,
692            crate::common::RW,
693        >::from_register(self, 0)
694    }
695
696    #[doc = "Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition."]
697    #[inline(always)]
698    pub fn rs(
699        self,
700    ) -> crate::common::RegisterField<
701        2,
702        0x1,
703        1,
704        0,
705        iccr2::Rs,
706        iccr2::Rs,
707        Iccr2_SPEC,
708        crate::common::RW,
709    > {
710        crate::common::RegisterField::<
711            2,
712            0x1,
713            1,
714            0,
715            iccr2::Rs,
716            iccr2::Rs,
717            Iccr2_SPEC,
718            crate::common::RW,
719        >::from_register(self, 0)
720    }
721
722    #[doc = "Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)."]
723    #[inline(always)]
724    pub fn st(
725        self,
726    ) -> crate::common::RegisterField<
727        1,
728        0x1,
729        1,
730        0,
731        iccr2::St,
732        iccr2::St,
733        Iccr2_SPEC,
734        crate::common::RW,
735    > {
736        crate::common::RegisterField::<
737            1,
738            0x1,
739            1,
740            0,
741            iccr2::St,
742            iccr2::St,
743            Iccr2_SPEC,
744            crate::common::RW,
745        >::from_register(self, 0)
746    }
747}
748impl ::core::default::Default for Iccr2 {
749    #[inline(always)]
750    fn default() -> Iccr2 {
751        <crate::RegValueT<Iccr2_SPEC> as RegisterValue<_>>::new(0)
752    }
753}
754pub mod iccr2 {
755
756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
757    pub struct Bbsy_SPEC;
758    pub type Bbsy = crate::EnumBitfieldStruct<u8, Bbsy_SPEC>;
759    impl Bbsy {
760        #[doc = "The I2C bus is released (bus free state)."]
761        pub const _0: Self = Self::new(0);
762
763        #[doc = "The I2C bus is occupied (bus busy state)."]
764        pub const _1: Self = Self::new(1);
765    }
766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767    pub struct Mst_SPEC;
768    pub type Mst = crate::EnumBitfieldStruct<u8, Mst_SPEC>;
769    impl Mst {
770        #[doc = "Slave mode"]
771        pub const _0: Self = Self::new(0);
772
773        #[doc = "Master mode"]
774        pub const _1: Self = Self::new(1);
775    }
776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
777    pub struct Trs_SPEC;
778    pub type Trs = crate::EnumBitfieldStruct<u8, Trs_SPEC>;
779    impl Trs {
780        #[doc = "Receive mode"]
781        pub const _0: Self = Self::new(0);
782
783        #[doc = "Transmit mode"]
784        pub const _1: Self = Self::new(1);
785    }
786    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
787    pub struct Sp_SPEC;
788    pub type Sp = crate::EnumBitfieldStruct<u8, Sp_SPEC>;
789    impl Sp {
790        #[doc = "Does not request to issue a stop condition."]
791        pub const _0: Self = Self::new(0);
792
793        #[doc = "Requests to issue a stop condition."]
794        pub const _1: Self = Self::new(1);
795    }
796    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
797    pub struct Rs_SPEC;
798    pub type Rs = crate::EnumBitfieldStruct<u8, Rs_SPEC>;
799    impl Rs {
800        #[doc = "Does not request to issue a restart condition."]
801        pub const _0: Self = Self::new(0);
802
803        #[doc = "Requests to issue a restart condition."]
804        pub const _1: Self = Self::new(1);
805    }
806    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
807    pub struct St_SPEC;
808    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
809    impl St {
810        #[doc = "Does not request to issue a start condition."]
811        pub const _0: Self = Self::new(0);
812
813        #[doc = "Requests to issue a start condition."]
814        pub const _1: Self = Self::new(1);
815    }
816}
817#[doc(hidden)]
818#[derive(Copy, Clone, Eq, PartialEq)]
819pub struct Icmr1_SPEC;
820impl crate::sealed::RegSpec for Icmr1_SPEC {
821    type DataType = u8;
822}
823
824#[doc = "I2C Bus Mode Register 1"]
825pub type Icmr1 = crate::RegValueT<Icmr1_SPEC>;
826
827impl Icmr1 {
828    #[doc = "MST/TRS Write Protect"]
829    #[inline(always)]
830    pub fn mtwp(
831        self,
832    ) -> crate::common::RegisterField<
833        7,
834        0x1,
835        1,
836        0,
837        icmr1::Mtwp,
838        icmr1::Mtwp,
839        Icmr1_SPEC,
840        crate::common::RW,
841    > {
842        crate::common::RegisterField::<
843            7,
844            0x1,
845            1,
846            0,
847            icmr1::Mtwp,
848            icmr1::Mtwp,
849            Icmr1_SPEC,
850            crate::common::RW,
851        >::from_register(self, 0)
852    }
853
854    #[doc = "Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )"]
855    #[inline(always)]
856    pub fn cks(
857        self,
858    ) -> crate::common::RegisterField<
859        4,
860        0x7,
861        1,
862        0,
863        icmr1::Cks,
864        icmr1::Cks,
865        Icmr1_SPEC,
866        crate::common::RW,
867    > {
868        crate::common::RegisterField::<
869            4,
870            0x7,
871            1,
872            0,
873            icmr1::Cks,
874            icmr1::Cks,
875            Icmr1_SPEC,
876            crate::common::RW,
877        >::from_register(self, 0)
878    }
879
880    #[doc = "BC Write Protect(This bit is read as 1.)"]
881    #[inline(always)]
882    pub fn bcwp(
883        self,
884    ) -> crate::common::RegisterField<
885        3,
886        0x1,
887        1,
888        0,
889        icmr1::Bcwp,
890        icmr1::Bcwp,
891        Icmr1_SPEC,
892        crate::common::W,
893    > {
894        crate::common::RegisterField::<
895            3,
896            0x1,
897            1,
898            0,
899            icmr1::Bcwp,
900            icmr1::Bcwp,
901            Icmr1_SPEC,
902            crate::common::W,
903        >::from_register(self, 0)
904    }
905
906    #[doc = "Bit Counter"]
907    #[inline(always)]
908    pub fn bc(
909        self,
910    ) -> crate::common::RegisterField<
911        0,
912        0x7,
913        1,
914        0,
915        icmr1::Bc,
916        icmr1::Bc,
917        Icmr1_SPEC,
918        crate::common::RW,
919    > {
920        crate::common::RegisterField::<
921            0,
922            0x7,
923            1,
924            0,
925            icmr1::Bc,
926            icmr1::Bc,
927            Icmr1_SPEC,
928            crate::common::RW,
929        >::from_register(self, 0)
930    }
931}
932impl ::core::default::Default for Icmr1 {
933    #[inline(always)]
934    fn default() -> Icmr1 {
935        <crate::RegValueT<Icmr1_SPEC> as RegisterValue<_>>::new(8)
936    }
937}
938pub mod icmr1 {
939
940    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
941    pub struct Mtwp_SPEC;
942    pub type Mtwp = crate::EnumBitfieldStruct<u8, Mtwp_SPEC>;
943    impl Mtwp {
944        #[doc = "Disables writing to the MST and TRS bits in ICCR2."]
945        pub const _0: Self = Self::new(0);
946
947        #[doc = "Enables writing to the MST and TRS bits in ICCR2."]
948        pub const _1: Self = Self::new(1);
949    }
950    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
951    pub struct Cks_SPEC;
952    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
953    impl Cks {
954        #[doc = "PCLKB/1 clock"]
955        pub const _000: Self = Self::new(0);
956
957        #[doc = "PCLKB/2 clock"]
958        pub const _001: Self = Self::new(1);
959
960        #[doc = "PCLKB/4 clock"]
961        pub const _010: Self = Self::new(2);
962
963        #[doc = "PCLKB/8 clock"]
964        pub const _011: Self = Self::new(3);
965
966        #[doc = "PCLKB/16 clock"]
967        pub const _100: Self = Self::new(4);
968
969        #[doc = "PCLKB/32 clock"]
970        pub const _101: Self = Self::new(5);
971
972        #[doc = "PCLKB/64 clock"]
973        pub const _110: Self = Self::new(6);
974
975        #[doc = "PCLKB/128 clock"]
976        pub const _111: Self = Self::new(7);
977    }
978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
979    pub struct Bcwp_SPEC;
980    pub type Bcwp = crate::EnumBitfieldStruct<u8, Bcwp_SPEC>;
981    impl Bcwp {
982        #[doc = "Enables a value to be written in the BC\\[2:0\\] bits."]
983        pub const _0: Self = Self::new(0);
984
985        #[doc = "Disables a value to be written in the BC\\[2:0\\] bits."]
986        pub const _1: Self = Self::new(1);
987    }
988    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
989    pub struct Bc_SPEC;
990    pub type Bc = crate::EnumBitfieldStruct<u8, Bc_SPEC>;
991    impl Bc {
992        #[doc = "9 bits"]
993        pub const _000: Self = Self::new(0);
994
995        #[doc = "2 bits"]
996        pub const _001: Self = Self::new(1);
997
998        #[doc = "3 bits"]
999        pub const _010: Self = Self::new(2);
1000
1001        #[doc = "4 bits"]
1002        pub const _011: Self = Self::new(3);
1003
1004        #[doc = "5 bits"]
1005        pub const _100: Self = Self::new(4);
1006
1007        #[doc = "6 bits"]
1008        pub const _101: Self = Self::new(5);
1009
1010        #[doc = "7 bits"]
1011        pub const _110: Self = Self::new(6);
1012
1013        #[doc = "8 bits"]
1014        pub const _111: Self = Self::new(7);
1015    }
1016}
1017#[doc(hidden)]
1018#[derive(Copy, Clone, Eq, PartialEq)]
1019pub struct Icmr2_SPEC;
1020impl crate::sealed::RegSpec for Icmr2_SPEC {
1021    type DataType = u8;
1022}
1023
1024#[doc = "I2C Bus Mode Register 2"]
1025pub type Icmr2 = crate::RegValueT<Icmr2_SPEC>;
1026
1027impl Icmr2 {
1028    #[doc = "SDA Output Delay Clock Source Selection"]
1029    #[inline(always)]
1030    pub fn dlcs(
1031        self,
1032    ) -> crate::common::RegisterField<
1033        7,
1034        0x1,
1035        1,
1036        0,
1037        icmr2::Dlcs,
1038        icmr2::Dlcs,
1039        Icmr2_SPEC,
1040        crate::common::RW,
1041    > {
1042        crate::common::RegisterField::<
1043            7,
1044            0x1,
1045            1,
1046            0,
1047            icmr2::Dlcs,
1048            icmr2::Dlcs,
1049            Icmr2_SPEC,
1050            crate::common::RW,
1051        >::from_register(self, 0)
1052    }
1053
1054    #[doc = "SDA Output Delay Counter"]
1055    #[inline(always)]
1056    pub fn sddl(
1057        self,
1058    ) -> crate::common::RegisterField<
1059        4,
1060        0x7,
1061        1,
1062        0,
1063        icmr2::Sddl,
1064        icmr2::Sddl,
1065        Icmr2_SPEC,
1066        crate::common::RW,
1067    > {
1068        crate::common::RegisterField::<
1069            4,
1070            0x7,
1071            1,
1072            0,
1073            icmr2::Sddl,
1074            icmr2::Sddl,
1075            Icmr2_SPEC,
1076            crate::common::RW,
1077        >::from_register(self, 0)
1078    }
1079
1080    #[doc = "Timeout H Count Control"]
1081    #[inline(always)]
1082    pub fn tmoh(
1083        self,
1084    ) -> crate::common::RegisterField<
1085        2,
1086        0x1,
1087        1,
1088        0,
1089        icmr2::Tmoh,
1090        icmr2::Tmoh,
1091        Icmr2_SPEC,
1092        crate::common::RW,
1093    > {
1094        crate::common::RegisterField::<
1095            2,
1096            0x1,
1097            1,
1098            0,
1099            icmr2::Tmoh,
1100            icmr2::Tmoh,
1101            Icmr2_SPEC,
1102            crate::common::RW,
1103        >::from_register(self, 0)
1104    }
1105
1106    #[doc = "Timeout L Count Control"]
1107    #[inline(always)]
1108    pub fn tmol(
1109        self,
1110    ) -> crate::common::RegisterField<
1111        1,
1112        0x1,
1113        1,
1114        0,
1115        icmr2::Tmol,
1116        icmr2::Tmol,
1117        Icmr2_SPEC,
1118        crate::common::RW,
1119    > {
1120        crate::common::RegisterField::<
1121            1,
1122            0x1,
1123            1,
1124            0,
1125            icmr2::Tmol,
1126            icmr2::Tmol,
1127            Icmr2_SPEC,
1128            crate::common::RW,
1129        >::from_register(self, 0)
1130    }
1131
1132    #[doc = "Timeout Detection Time Selection"]
1133    #[inline(always)]
1134    pub fn tmos(
1135        self,
1136    ) -> crate::common::RegisterField<
1137        0,
1138        0x1,
1139        1,
1140        0,
1141        icmr2::Tmos,
1142        icmr2::Tmos,
1143        Icmr2_SPEC,
1144        crate::common::RW,
1145    > {
1146        crate::common::RegisterField::<
1147            0,
1148            0x1,
1149            1,
1150            0,
1151            icmr2::Tmos,
1152            icmr2::Tmos,
1153            Icmr2_SPEC,
1154            crate::common::RW,
1155        >::from_register(self, 0)
1156    }
1157}
1158impl ::core::default::Default for Icmr2 {
1159    #[inline(always)]
1160    fn default() -> Icmr2 {
1161        <crate::RegValueT<Icmr2_SPEC> as RegisterValue<_>>::new(6)
1162    }
1163}
1164pub mod icmr2 {
1165
1166    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1167    pub struct Dlcs_SPEC;
1168    pub type Dlcs = crate::EnumBitfieldStruct<u8, Dlcs_SPEC>;
1169    impl Dlcs {
1170        #[doc = "The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
1171        pub const _0: Self = Self::new(0);
1172
1173        #[doc = "The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
1174        pub const _1: Self = Self::new(1);
1175    }
1176    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1177    pub struct Sddl_SPEC;
1178    pub type Sddl = crate::EnumBitfieldStruct<u8, Sddl_SPEC>;
1179    impl Sddl {
1180        #[doc = "No output delay"]
1181        pub const _000: Self = Self::new(0);
1182
1183        #[doc = "1 fIIC cycle  (ICMR2.DLCS=0) / 1  or 2 fIIC cycles (ICMR2.DLCS=1)"]
1184        pub const _001: Self = Self::new(1);
1185
1186        #[doc = "2 fIIC cycles (ICMR2.DLCS=0) /  3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
1187        pub const _010: Self = Self::new(2);
1188
1189        #[doc = "3 fIIC cycles (ICMR2.DLCS=0) /  5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
1190        pub const _011: Self = Self::new(3);
1191
1192        #[doc = "4 fIIC cycles (ICMR2.DLCS=0) /  7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
1193        pub const _100: Self = Self::new(4);
1194
1195        #[doc = "5 fIIC cycles (ICMR2.DLCS=0) /  9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
1196        pub const _101: Self = Self::new(5);
1197
1198        #[doc = "6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
1199        pub const _110: Self = Self::new(6);
1200
1201        #[doc = "7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
1202        pub const _111: Self = Self::new(7);
1203    }
1204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1205    pub struct Tmoh_SPEC;
1206    pub type Tmoh = crate::EnumBitfieldStruct<u8, Tmoh_SPEC>;
1207    impl Tmoh {
1208        #[doc = "Count is disabled while the SCLn line is at a high level."]
1209        pub const _0: Self = Self::new(0);
1210
1211        #[doc = "Count is enabled while the SCLn line is at a high level."]
1212        pub const _1: Self = Self::new(1);
1213    }
1214    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1215    pub struct Tmol_SPEC;
1216    pub type Tmol = crate::EnumBitfieldStruct<u8, Tmol_SPEC>;
1217    impl Tmol {
1218        #[doc = "Count is disabled while the SCLn line is at a low level."]
1219        pub const _0: Self = Self::new(0);
1220
1221        #[doc = "Count is enabled while the SCLn line is at a low level."]
1222        pub const _1: Self = Self::new(1);
1223    }
1224    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1225    pub struct Tmos_SPEC;
1226    pub type Tmos = crate::EnumBitfieldStruct<u8, Tmos_SPEC>;
1227    impl Tmos {
1228        #[doc = "Long mode is selected."]
1229        pub const _0: Self = Self::new(0);
1230
1231        #[doc = "Short mode is selected."]
1232        pub const _1: Self = Self::new(1);
1233    }
1234}
1235#[doc(hidden)]
1236#[derive(Copy, Clone, Eq, PartialEq)]
1237pub struct Icmr3_SPEC;
1238impl crate::sealed::RegSpec for Icmr3_SPEC {
1239    type DataType = u8;
1240}
1241
1242#[doc = "I2C Bus Mode Register 3"]
1243pub type Icmr3 = crate::RegValueT<Icmr3_SPEC>;
1244
1245impl Icmr3 {
1246    #[doc = "SMBus/I2C Bus Selection"]
1247    #[inline(always)]
1248    pub fn smbs(
1249        self,
1250    ) -> crate::common::RegisterField<
1251        7,
1252        0x1,
1253        1,
1254        0,
1255        icmr3::Smbs,
1256        icmr3::Smbs,
1257        Icmr3_SPEC,
1258        crate::common::RW,
1259    > {
1260        crate::common::RegisterField::<
1261            7,
1262            0x1,
1263            1,
1264            0,
1265            icmr3::Smbs,
1266            icmr3::Smbs,
1267            Icmr3_SPEC,
1268            crate::common::RW,
1269        >::from_register(self, 0)
1270    }
1271
1272    #[doc = "WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand."]
1273    #[inline(always)]
1274    pub fn wait(
1275        self,
1276    ) -> crate::common::RegisterField<
1277        6,
1278        0x1,
1279        1,
1280        0,
1281        icmr3::Wait,
1282        icmr3::Wait,
1283        Icmr3_SPEC,
1284        crate::common::RW,
1285    > {
1286        crate::common::RegisterField::<
1287            6,
1288            0x1,
1289            1,
1290            0,
1291            icmr3::Wait,
1292            icmr3::Wait,
1293            Icmr3_SPEC,
1294            crate::common::RW,
1295        >::from_register(self, 0)
1296    }
1297
1298    #[doc = "RDRF Flag Set Timing Selection"]
1299    #[inline(always)]
1300    pub fn rdrfs(
1301        self,
1302    ) -> crate::common::RegisterField<
1303        5,
1304        0x1,
1305        1,
1306        0,
1307        icmr3::Rdrfs,
1308        icmr3::Rdrfs,
1309        Icmr3_SPEC,
1310        crate::common::RW,
1311    > {
1312        crate::common::RegisterField::<
1313            5,
1314            0x1,
1315            1,
1316            0,
1317            icmr3::Rdrfs,
1318            icmr3::Rdrfs,
1319            Icmr3_SPEC,
1320            crate::common::RW,
1321        >::from_register(self, 0)
1322    }
1323
1324    #[doc = "ACKBT Write Protect"]
1325    #[inline(always)]
1326    pub fn ackwp(
1327        self,
1328    ) -> crate::common::RegisterField<
1329        4,
1330        0x1,
1331        1,
1332        0,
1333        icmr3::Ackwp,
1334        icmr3::Ackwp,
1335        Icmr3_SPEC,
1336        crate::common::RW,
1337    > {
1338        crate::common::RegisterField::<
1339            4,
1340            0x1,
1341            1,
1342            0,
1343            icmr3::Ackwp,
1344            icmr3::Ackwp,
1345            Icmr3_SPEC,
1346            crate::common::RW,
1347        >::from_register(self, 0)
1348    }
1349
1350    #[doc = "Transmit Acknowledge"]
1351    #[inline(always)]
1352    pub fn ackbt(
1353        self,
1354    ) -> crate::common::RegisterField<
1355        3,
1356        0x1,
1357        1,
1358        0,
1359        icmr3::Ackbt,
1360        icmr3::Ackbt,
1361        Icmr3_SPEC,
1362        crate::common::RW,
1363    > {
1364        crate::common::RegisterField::<
1365            3,
1366            0x1,
1367            1,
1368            0,
1369            icmr3::Ackbt,
1370            icmr3::Ackbt,
1371            Icmr3_SPEC,
1372            crate::common::RW,
1373        >::from_register(self, 0)
1374    }
1375
1376    #[doc = "Receive Acknowledge"]
1377    #[inline(always)]
1378    pub fn ackbr(
1379        self,
1380    ) -> crate::common::RegisterField<
1381        2,
1382        0x1,
1383        1,
1384        0,
1385        icmr3::Ackbr,
1386        icmr3::Ackbr,
1387        Icmr3_SPEC,
1388        crate::common::R,
1389    > {
1390        crate::common::RegisterField::<
1391            2,
1392            0x1,
1393            1,
1394            0,
1395            icmr3::Ackbr,
1396            icmr3::Ackbr,
1397            Icmr3_SPEC,
1398            crate::common::R,
1399        >::from_register(self, 0)
1400    }
1401
1402    #[doc = "Noise Filter Stage Selection"]
1403    #[inline(always)]
1404    pub fn nf(
1405        self,
1406    ) -> crate::common::RegisterField<
1407        0,
1408        0x3,
1409        1,
1410        0,
1411        icmr3::Nf,
1412        icmr3::Nf,
1413        Icmr3_SPEC,
1414        crate::common::RW,
1415    > {
1416        crate::common::RegisterField::<
1417            0,
1418            0x3,
1419            1,
1420            0,
1421            icmr3::Nf,
1422            icmr3::Nf,
1423            Icmr3_SPEC,
1424            crate::common::RW,
1425        >::from_register(self, 0)
1426    }
1427}
1428impl ::core::default::Default for Icmr3 {
1429    #[inline(always)]
1430    fn default() -> Icmr3 {
1431        <crate::RegValueT<Icmr3_SPEC> as RegisterValue<_>>::new(0)
1432    }
1433}
1434pub mod icmr3 {
1435
1436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1437    pub struct Smbs_SPEC;
1438    pub type Smbs = crate::EnumBitfieldStruct<u8, Smbs_SPEC>;
1439    impl Smbs {
1440        #[doc = "The I2C bus is selected."]
1441        pub const _0: Self = Self::new(0);
1442
1443        #[doc = "The SMBus is selected."]
1444        pub const _1: Self = Self::new(1);
1445    }
1446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1447    pub struct Wait_SPEC;
1448    pub type Wait = crate::EnumBitfieldStruct<u8, Wait_SPEC>;
1449    impl Wait {
1450        #[doc = "No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)"]
1451        pub const _0: Self = Self::new(0);
1452
1453        #[doc = "WAIT (The period between ninth clock cycle and first clock cycle is held low.)"]
1454        pub const _1: Self = Self::new(1);
1455    }
1456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1457    pub struct Rdrfs_SPEC;
1458    pub type Rdrfs = crate::EnumBitfieldStruct<u8, Rdrfs_SPEC>;
1459    impl Rdrfs {
1460        #[doc = "The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)"]
1461        pub const _0: Self = Self::new(0);
1462
1463        #[doc = "The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)"]
1464        pub const _1: Self = Self::new(1);
1465    }
1466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1467    pub struct Ackwp_SPEC;
1468    pub type Ackwp = crate::EnumBitfieldStruct<u8, Ackwp_SPEC>;
1469    impl Ackwp {
1470        #[doc = "Modification of the ACKBT bit is disabled."]
1471        pub const _0: Self = Self::new(0);
1472
1473        #[doc = "Modification of the ACKBT bit is enabled."]
1474        pub const _1: Self = Self::new(1);
1475    }
1476    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1477    pub struct Ackbt_SPEC;
1478    pub type Ackbt = crate::EnumBitfieldStruct<u8, Ackbt_SPEC>;
1479    impl Ackbt {
1480        #[doc = "A 0 is sent as the acknowledge bit (ACK transmission)."]
1481        pub const _0: Self = Self::new(0);
1482
1483        #[doc = "A 1 is sent as the acknowledge bit (NACK transmission)."]
1484        pub const _1: Self = Self::new(1);
1485    }
1486    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1487    pub struct Ackbr_SPEC;
1488    pub type Ackbr = crate::EnumBitfieldStruct<u8, Ackbr_SPEC>;
1489    impl Ackbr {
1490        #[doc = "A 0 is received as the acknowledge bit (ACK reception)."]
1491        pub const _0: Self = Self::new(0);
1492
1493        #[doc = "A 1 is received as the acknowledge bit (NACK reception)."]
1494        pub const _1: Self = Self::new(1);
1495    }
1496    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1497    pub struct Nf_SPEC;
1498    pub type Nf = crate::EnumBitfieldStruct<u8, Nf_SPEC>;
1499    impl Nf {
1500        #[doc = "Noise of up to one fIIC cycle is filtered out (single-stage filter)."]
1501        pub const _00: Self = Self::new(0);
1502
1503        #[doc = "Noise of up to two fIIC cycles is filtered out (2-stage filter)."]
1504        pub const _01: Self = Self::new(1);
1505
1506        #[doc = "Noise of up to three fIIC cycles is filtered out (3-stage filter)."]
1507        pub const _10: Self = Self::new(2);
1508
1509        #[doc = "Noise of up to four fIIC cycles is filtered out (4-stage filter)"]
1510        pub const _11: Self = Self::new(3);
1511    }
1512}
1513#[doc(hidden)]
1514#[derive(Copy, Clone, Eq, PartialEq)]
1515pub struct Icfer_SPEC;
1516impl crate::sealed::RegSpec for Icfer_SPEC {
1517    type DataType = u8;
1518}
1519
1520#[doc = "I2C Bus Function Enable Register"]
1521pub type Icfer = crate::RegValueT<Icfer_SPEC>;
1522
1523impl Icfer {
1524    #[doc = "Fast-mode Plus Enable"]
1525    #[inline(always)]
1526    pub fn fmpe(
1527        self,
1528    ) -> crate::common::RegisterField<
1529        7,
1530        0x1,
1531        1,
1532        0,
1533        icfer::Fmpe,
1534        icfer::Fmpe,
1535        Icfer_SPEC,
1536        crate::common::RW,
1537    > {
1538        crate::common::RegisterField::<
1539            7,
1540            0x1,
1541            1,
1542            0,
1543            icfer::Fmpe,
1544            icfer::Fmpe,
1545            Icfer_SPEC,
1546            crate::common::RW,
1547        >::from_register(self, 0)
1548    }
1549
1550    #[doc = "SCL Synchronous Circuit Enable"]
1551    #[inline(always)]
1552    pub fn scle(
1553        self,
1554    ) -> crate::common::RegisterField<
1555        6,
1556        0x1,
1557        1,
1558        0,
1559        icfer::Scle,
1560        icfer::Scle,
1561        Icfer_SPEC,
1562        crate::common::RW,
1563    > {
1564        crate::common::RegisterField::<
1565            6,
1566            0x1,
1567            1,
1568            0,
1569            icfer::Scle,
1570            icfer::Scle,
1571            Icfer_SPEC,
1572            crate::common::RW,
1573        >::from_register(self, 0)
1574    }
1575
1576    #[doc = "Digital Noise Filter Circuit Enable"]
1577    #[inline(always)]
1578    pub fn nfe(
1579        self,
1580    ) -> crate::common::RegisterField<
1581        5,
1582        0x1,
1583        1,
1584        0,
1585        icfer::Nfe,
1586        icfer::Nfe,
1587        Icfer_SPEC,
1588        crate::common::RW,
1589    > {
1590        crate::common::RegisterField::<
1591            5,
1592            0x1,
1593            1,
1594            0,
1595            icfer::Nfe,
1596            icfer::Nfe,
1597            Icfer_SPEC,
1598            crate::common::RW,
1599        >::from_register(self, 0)
1600    }
1601
1602    #[doc = "NACK Reception Transfer Suspension Enable"]
1603    #[inline(always)]
1604    pub fn nacke(
1605        self,
1606    ) -> crate::common::RegisterField<
1607        4,
1608        0x1,
1609        1,
1610        0,
1611        icfer::Nacke,
1612        icfer::Nacke,
1613        Icfer_SPEC,
1614        crate::common::RW,
1615    > {
1616        crate::common::RegisterField::<
1617            4,
1618            0x1,
1619            1,
1620            0,
1621            icfer::Nacke,
1622            icfer::Nacke,
1623            Icfer_SPEC,
1624            crate::common::RW,
1625        >::from_register(self, 0)
1626    }
1627
1628    #[doc = "Slave Arbitration-Lost Detection Enable"]
1629    #[inline(always)]
1630    pub fn sale(
1631        self,
1632    ) -> crate::common::RegisterField<
1633        3,
1634        0x1,
1635        1,
1636        0,
1637        icfer::Sale,
1638        icfer::Sale,
1639        Icfer_SPEC,
1640        crate::common::RW,
1641    > {
1642        crate::common::RegisterField::<
1643            3,
1644            0x1,
1645            1,
1646            0,
1647            icfer::Sale,
1648            icfer::Sale,
1649            Icfer_SPEC,
1650            crate::common::RW,
1651        >::from_register(self, 0)
1652    }
1653
1654    #[doc = "NACK Transmission Arbitration-Lost Detection Enable"]
1655    #[inline(always)]
1656    pub fn nale(
1657        self,
1658    ) -> crate::common::RegisterField<
1659        2,
1660        0x1,
1661        1,
1662        0,
1663        icfer::Nale,
1664        icfer::Nale,
1665        Icfer_SPEC,
1666        crate::common::RW,
1667    > {
1668        crate::common::RegisterField::<
1669            2,
1670            0x1,
1671            1,
1672            0,
1673            icfer::Nale,
1674            icfer::Nale,
1675            Icfer_SPEC,
1676            crate::common::RW,
1677        >::from_register(self, 0)
1678    }
1679
1680    #[doc = "Master Arbitration-Lost Detection Enable"]
1681    #[inline(always)]
1682    pub fn male(
1683        self,
1684    ) -> crate::common::RegisterField<
1685        1,
1686        0x1,
1687        1,
1688        0,
1689        icfer::Male,
1690        icfer::Male,
1691        Icfer_SPEC,
1692        crate::common::RW,
1693    > {
1694        crate::common::RegisterField::<
1695            1,
1696            0x1,
1697            1,
1698            0,
1699            icfer::Male,
1700            icfer::Male,
1701            Icfer_SPEC,
1702            crate::common::RW,
1703        >::from_register(self, 0)
1704    }
1705
1706    #[doc = "Timeout Function Enable"]
1707    #[inline(always)]
1708    pub fn tmoe(
1709        self,
1710    ) -> crate::common::RegisterField<
1711        0,
1712        0x1,
1713        1,
1714        0,
1715        icfer::Tmoe,
1716        icfer::Tmoe,
1717        Icfer_SPEC,
1718        crate::common::RW,
1719    > {
1720        crate::common::RegisterField::<
1721            0,
1722            0x1,
1723            1,
1724            0,
1725            icfer::Tmoe,
1726            icfer::Tmoe,
1727            Icfer_SPEC,
1728            crate::common::RW,
1729        >::from_register(self, 0)
1730    }
1731}
1732impl ::core::default::Default for Icfer {
1733    #[inline(always)]
1734    fn default() -> Icfer {
1735        <crate::RegValueT<Icfer_SPEC> as RegisterValue<_>>::new(114)
1736    }
1737}
1738pub mod icfer {
1739
1740    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1741    pub struct Fmpe_SPEC;
1742    pub type Fmpe = crate::EnumBitfieldStruct<u8, Fmpe_SPEC>;
1743    impl Fmpe {
1744        #[doc = "No Fm+ slope control circuit is used for the SCLn pin and SDAn pin."]
1745        pub const _0: Self = Self::new(0);
1746
1747        #[doc = "An Fm+ slope control circuit is used for the SCLn pin and SDAn pin."]
1748        pub const _1: Self = Self::new(1);
1749    }
1750    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1751    pub struct Scle_SPEC;
1752    pub type Scle = crate::EnumBitfieldStruct<u8, Scle_SPEC>;
1753    impl Scle {
1754        #[doc = "No SCL synchronous circuit is used."]
1755        pub const _0: Self = Self::new(0);
1756
1757        #[doc = "An SCL synchronous circuit is used."]
1758        pub const _1: Self = Self::new(1);
1759    }
1760    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1761    pub struct Nfe_SPEC;
1762    pub type Nfe = crate::EnumBitfieldStruct<u8, Nfe_SPEC>;
1763    impl Nfe {
1764        #[doc = "No digital noise filter circuit is used."]
1765        pub const _0: Self = Self::new(0);
1766
1767        #[doc = "A digital noise filter circuit is used."]
1768        pub const _1: Self = Self::new(1);
1769    }
1770    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1771    pub struct Nacke_SPEC;
1772    pub type Nacke = crate::EnumBitfieldStruct<u8, Nacke_SPEC>;
1773    impl Nacke {
1774        #[doc = "Transfer operation is not suspended during NACK reception (transfer suspension disabled)."]
1775        pub const _0: Self = Self::new(0);
1776
1777        #[doc = "Transfer operation is suspended during NACK reception (transfer suspension enabled)."]
1778        pub const _1: Self = Self::new(1);
1779    }
1780    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1781    pub struct Sale_SPEC;
1782    pub type Sale = crate::EnumBitfieldStruct<u8, Sale_SPEC>;
1783    impl Sale {
1784        #[doc = "Slave arbitration-lost detection is disabled."]
1785        pub const _0: Self = Self::new(0);
1786
1787        #[doc = "Slave arbitration-lost detection is enabled."]
1788        pub const _1: Self = Self::new(1);
1789    }
1790    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1791    pub struct Nale_SPEC;
1792    pub type Nale = crate::EnumBitfieldStruct<u8, Nale_SPEC>;
1793    impl Nale {
1794        #[doc = "NACK transmission arbitration-lost detection is disabled."]
1795        pub const _0: Self = Self::new(0);
1796
1797        #[doc = "NACK transmission arbitration-lost detection is enabled."]
1798        pub const _1: Self = Self::new(1);
1799    }
1800    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1801    pub struct Male_SPEC;
1802    pub type Male = crate::EnumBitfieldStruct<u8, Male_SPEC>;
1803    impl Male {
1804        #[doc = "Master arbitration-lost detection is disabled."]
1805        pub const _0: Self = Self::new(0);
1806
1807        #[doc = "Master arbitration-lost detection is enabled."]
1808        pub const _1: Self = Self::new(1);
1809    }
1810    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1811    pub struct Tmoe_SPEC;
1812    pub type Tmoe = crate::EnumBitfieldStruct<u8, Tmoe_SPEC>;
1813    impl Tmoe {
1814        #[doc = "The timeout function is disabled."]
1815        pub const _0: Self = Self::new(0);
1816
1817        #[doc = "The timeout function is enabled."]
1818        pub const _1: Self = Self::new(1);
1819    }
1820}
1821#[doc(hidden)]
1822#[derive(Copy, Clone, Eq, PartialEq)]
1823pub struct Icser_SPEC;
1824impl crate::sealed::RegSpec for Icser_SPEC {
1825    type DataType = u8;
1826}
1827
1828#[doc = "I2C Bus Status Enable Register"]
1829pub type Icser = crate::RegValueT<Icser_SPEC>;
1830
1831impl Icser {
1832    #[doc = "Host Address Enable"]
1833    #[inline(always)]
1834    pub fn hoae(
1835        self,
1836    ) -> crate::common::RegisterField<
1837        7,
1838        0x1,
1839        1,
1840        0,
1841        icser::Hoae,
1842        icser::Hoae,
1843        Icser_SPEC,
1844        crate::common::RW,
1845    > {
1846        crate::common::RegisterField::<
1847            7,
1848            0x1,
1849            1,
1850            0,
1851            icser::Hoae,
1852            icser::Hoae,
1853            Icser_SPEC,
1854            crate::common::RW,
1855        >::from_register(self, 0)
1856    }
1857
1858    #[doc = "Device-ID Address Detection Enable"]
1859    #[inline(always)]
1860    pub fn dide(
1861        self,
1862    ) -> crate::common::RegisterField<
1863        5,
1864        0x1,
1865        1,
1866        0,
1867        icser::Dide,
1868        icser::Dide,
1869        Icser_SPEC,
1870        crate::common::RW,
1871    > {
1872        crate::common::RegisterField::<
1873            5,
1874            0x1,
1875            1,
1876            0,
1877            icser::Dide,
1878            icser::Dide,
1879            Icser_SPEC,
1880            crate::common::RW,
1881        >::from_register(self, 0)
1882    }
1883
1884    #[doc = "General Call Address Enable"]
1885    #[inline(always)]
1886    pub fn gcae(
1887        self,
1888    ) -> crate::common::RegisterField<
1889        3,
1890        0x1,
1891        1,
1892        0,
1893        icser::Gcae,
1894        icser::Gcae,
1895        Icser_SPEC,
1896        crate::common::RW,
1897    > {
1898        crate::common::RegisterField::<
1899            3,
1900            0x1,
1901            1,
1902            0,
1903            icser::Gcae,
1904            icser::Gcae,
1905            Icser_SPEC,
1906            crate::common::RW,
1907        >::from_register(self, 0)
1908    }
1909
1910    #[doc = "Slave Address Register 2 Enable"]
1911    #[inline(always)]
1912    pub fn sar2e(
1913        self,
1914    ) -> crate::common::RegisterField<
1915        2,
1916        0x1,
1917        1,
1918        0,
1919        icser::Sar2E,
1920        icser::Sar2E,
1921        Icser_SPEC,
1922        crate::common::RW,
1923    > {
1924        crate::common::RegisterField::<
1925            2,
1926            0x1,
1927            1,
1928            0,
1929            icser::Sar2E,
1930            icser::Sar2E,
1931            Icser_SPEC,
1932            crate::common::RW,
1933        >::from_register(self, 0)
1934    }
1935
1936    #[doc = "Slave Address Register 1 Enable"]
1937    #[inline(always)]
1938    pub fn sar1e(
1939        self,
1940    ) -> crate::common::RegisterField<
1941        1,
1942        0x1,
1943        1,
1944        0,
1945        icser::Sar1E,
1946        icser::Sar1E,
1947        Icser_SPEC,
1948        crate::common::RW,
1949    > {
1950        crate::common::RegisterField::<
1951            1,
1952            0x1,
1953            1,
1954            0,
1955            icser::Sar1E,
1956            icser::Sar1E,
1957            Icser_SPEC,
1958            crate::common::RW,
1959        >::from_register(self, 0)
1960    }
1961
1962    #[doc = "Slave Address Register 0 Enable"]
1963    #[inline(always)]
1964    pub fn sar0e(
1965        self,
1966    ) -> crate::common::RegisterField<
1967        0,
1968        0x1,
1969        1,
1970        0,
1971        icser::Sar0E,
1972        icser::Sar0E,
1973        Icser_SPEC,
1974        crate::common::RW,
1975    > {
1976        crate::common::RegisterField::<
1977            0,
1978            0x1,
1979            1,
1980            0,
1981            icser::Sar0E,
1982            icser::Sar0E,
1983            Icser_SPEC,
1984            crate::common::RW,
1985        >::from_register(self, 0)
1986    }
1987}
1988impl ::core::default::Default for Icser {
1989    #[inline(always)]
1990    fn default() -> Icser {
1991        <crate::RegValueT<Icser_SPEC> as RegisterValue<_>>::new(9)
1992    }
1993}
1994pub mod icser {
1995
1996    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1997    pub struct Hoae_SPEC;
1998    pub type Hoae = crate::EnumBitfieldStruct<u8, Hoae_SPEC>;
1999    impl Hoae {
2000        #[doc = "Host address detection is disabled."]
2001        pub const _0: Self = Self::new(0);
2002
2003        #[doc = "Host address detection is enabled."]
2004        pub const _1: Self = Self::new(1);
2005    }
2006    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2007    pub struct Dide_SPEC;
2008    pub type Dide = crate::EnumBitfieldStruct<u8, Dide_SPEC>;
2009    impl Dide {
2010        #[doc = "Device-ID address detection is disabled."]
2011        pub const _0: Self = Self::new(0);
2012
2013        #[doc = "Device-ID address detection is enabled."]
2014        pub const _1: Self = Self::new(1);
2015    }
2016    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2017    pub struct Gcae_SPEC;
2018    pub type Gcae = crate::EnumBitfieldStruct<u8, Gcae_SPEC>;
2019    impl Gcae {
2020        #[doc = "General call address detection is disabled."]
2021        pub const _0: Self = Self::new(0);
2022
2023        #[doc = "General call address detection is enabled."]
2024        pub const _1: Self = Self::new(1);
2025    }
2026    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2027    pub struct Sar2E_SPEC;
2028    pub type Sar2E = crate::EnumBitfieldStruct<u8, Sar2E_SPEC>;
2029    impl Sar2E {
2030        #[doc = "Slave address in SARL2 and SARU2 is disabled."]
2031        pub const _0: Self = Self::new(0);
2032
2033        #[doc = "Slave address in SARL2 and SARU2 is enabled"]
2034        pub const _1: Self = Self::new(1);
2035    }
2036    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2037    pub struct Sar1E_SPEC;
2038    pub type Sar1E = crate::EnumBitfieldStruct<u8, Sar1E_SPEC>;
2039    impl Sar1E {
2040        #[doc = "Slave address in SARL1 and SARU1 is disabled."]
2041        pub const _0: Self = Self::new(0);
2042
2043        #[doc = "Slave address in SARL1 and SARU1 is enabled."]
2044        pub const _1: Self = Self::new(1);
2045    }
2046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2047    pub struct Sar0E_SPEC;
2048    pub type Sar0E = crate::EnumBitfieldStruct<u8, Sar0E_SPEC>;
2049    impl Sar0E {
2050        #[doc = "Slave address in SARL0 and SARU0 is disabled."]
2051        pub const _0: Self = Self::new(0);
2052
2053        #[doc = "Slave address in SARL0 and SARU0 is enabled."]
2054        pub const _1: Self = Self::new(1);
2055    }
2056}
2057#[doc(hidden)]
2058#[derive(Copy, Clone, Eq, PartialEq)]
2059pub struct Icier_SPEC;
2060impl crate::sealed::RegSpec for Icier_SPEC {
2061    type DataType = u8;
2062}
2063
2064#[doc = "I2C Bus Interrupt Enable Register"]
2065pub type Icier = crate::RegValueT<Icier_SPEC>;
2066
2067impl Icier {
2068    #[doc = "Transmit Data Empty Interrupt Request Enable"]
2069    #[inline(always)]
2070    pub fn tie(
2071        self,
2072    ) -> crate::common::RegisterField<
2073        7,
2074        0x1,
2075        1,
2076        0,
2077        icier::Tie,
2078        icier::Tie,
2079        Icier_SPEC,
2080        crate::common::RW,
2081    > {
2082        crate::common::RegisterField::<
2083            7,
2084            0x1,
2085            1,
2086            0,
2087            icier::Tie,
2088            icier::Tie,
2089            Icier_SPEC,
2090            crate::common::RW,
2091        >::from_register(self, 0)
2092    }
2093
2094    #[doc = "Transmit End Interrupt Request  Enable"]
2095    #[inline(always)]
2096    pub fn teie(
2097        self,
2098    ) -> crate::common::RegisterField<
2099        6,
2100        0x1,
2101        1,
2102        0,
2103        icier::Teie,
2104        icier::Teie,
2105        Icier_SPEC,
2106        crate::common::RW,
2107    > {
2108        crate::common::RegisterField::<
2109            6,
2110            0x1,
2111            1,
2112            0,
2113            icier::Teie,
2114            icier::Teie,
2115            Icier_SPEC,
2116            crate::common::RW,
2117        >::from_register(self, 0)
2118    }
2119
2120    #[doc = "Receive Data Full Interrupt Request Enable"]
2121    #[inline(always)]
2122    pub fn rie(
2123        self,
2124    ) -> crate::common::RegisterField<
2125        5,
2126        0x1,
2127        1,
2128        0,
2129        icier::Rie,
2130        icier::Rie,
2131        Icier_SPEC,
2132        crate::common::RW,
2133    > {
2134        crate::common::RegisterField::<
2135            5,
2136            0x1,
2137            1,
2138            0,
2139            icier::Rie,
2140            icier::Rie,
2141            Icier_SPEC,
2142            crate::common::RW,
2143        >::from_register(self, 0)
2144    }
2145
2146    #[doc = "NACK Reception Interrupt Request Enable"]
2147    #[inline(always)]
2148    pub fn nakie(
2149        self,
2150    ) -> crate::common::RegisterField<
2151        4,
2152        0x1,
2153        1,
2154        0,
2155        icier::Nakie,
2156        icier::Nakie,
2157        Icier_SPEC,
2158        crate::common::RW,
2159    > {
2160        crate::common::RegisterField::<
2161            4,
2162            0x1,
2163            1,
2164            0,
2165            icier::Nakie,
2166            icier::Nakie,
2167            Icier_SPEC,
2168            crate::common::RW,
2169        >::from_register(self, 0)
2170    }
2171
2172    #[doc = "Stop Condition Detection Interrupt Request Enable"]
2173    #[inline(always)]
2174    pub fn spie(
2175        self,
2176    ) -> crate::common::RegisterField<
2177        3,
2178        0x1,
2179        1,
2180        0,
2181        icier::Spie,
2182        icier::Spie,
2183        Icier_SPEC,
2184        crate::common::RW,
2185    > {
2186        crate::common::RegisterField::<
2187            3,
2188            0x1,
2189            1,
2190            0,
2191            icier::Spie,
2192            icier::Spie,
2193            Icier_SPEC,
2194            crate::common::RW,
2195        >::from_register(self, 0)
2196    }
2197
2198    #[doc = "Start Condition Detection Interrupt Request Enable"]
2199    #[inline(always)]
2200    pub fn stie(
2201        self,
2202    ) -> crate::common::RegisterField<
2203        2,
2204        0x1,
2205        1,
2206        0,
2207        icier::Stie,
2208        icier::Stie,
2209        Icier_SPEC,
2210        crate::common::RW,
2211    > {
2212        crate::common::RegisterField::<
2213            2,
2214            0x1,
2215            1,
2216            0,
2217            icier::Stie,
2218            icier::Stie,
2219            Icier_SPEC,
2220            crate::common::RW,
2221        >::from_register(self, 0)
2222    }
2223
2224    #[doc = "Arbitration-Lost Interrupt Request Enable"]
2225    #[inline(always)]
2226    pub fn alie(
2227        self,
2228    ) -> crate::common::RegisterField<
2229        1,
2230        0x1,
2231        1,
2232        0,
2233        icier::Alie,
2234        icier::Alie,
2235        Icier_SPEC,
2236        crate::common::RW,
2237    > {
2238        crate::common::RegisterField::<
2239            1,
2240            0x1,
2241            1,
2242            0,
2243            icier::Alie,
2244            icier::Alie,
2245            Icier_SPEC,
2246            crate::common::RW,
2247        >::from_register(self, 0)
2248    }
2249
2250    #[doc = "Timeout Interrupt Request Enable"]
2251    #[inline(always)]
2252    pub fn tmoie(
2253        self,
2254    ) -> crate::common::RegisterField<
2255        0,
2256        0x1,
2257        1,
2258        0,
2259        icier::Tmoie,
2260        icier::Tmoie,
2261        Icier_SPEC,
2262        crate::common::RW,
2263    > {
2264        crate::common::RegisterField::<
2265            0,
2266            0x1,
2267            1,
2268            0,
2269            icier::Tmoie,
2270            icier::Tmoie,
2271            Icier_SPEC,
2272            crate::common::RW,
2273        >::from_register(self, 0)
2274    }
2275}
2276impl ::core::default::Default for Icier {
2277    #[inline(always)]
2278    fn default() -> Icier {
2279        <crate::RegValueT<Icier_SPEC> as RegisterValue<_>>::new(0)
2280    }
2281}
2282pub mod icier {
2283
2284    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2285    pub struct Tie_SPEC;
2286    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
2287    impl Tie {
2288        #[doc = "Transmit data empty interrupt request (TXI) is disabled."]
2289        pub const _0: Self = Self::new(0);
2290
2291        #[doc = "Transmit data empty interrupt request (TXI) is enabled."]
2292        pub const _1: Self = Self::new(1);
2293    }
2294    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2295    pub struct Teie_SPEC;
2296    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
2297    impl Teie {
2298        #[doc = "Transmit end interrupt request (TEI) is disabled."]
2299        pub const _0: Self = Self::new(0);
2300
2301        #[doc = "Transmit end interrupt request (TEI) is enabled."]
2302        pub const _1: Self = Self::new(1);
2303    }
2304    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2305    pub struct Rie_SPEC;
2306    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
2307    impl Rie {
2308        #[doc = "Receive data full interrupt request (RXI) is disabled."]
2309        pub const _0: Self = Self::new(0);
2310
2311        #[doc = "Receive data full interrupt request (RXI) is enabled."]
2312        pub const _1: Self = Self::new(1);
2313    }
2314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2315    pub struct Nakie_SPEC;
2316    pub type Nakie = crate::EnumBitfieldStruct<u8, Nakie_SPEC>;
2317    impl Nakie {
2318        #[doc = "NACK reception interrupt request (NAKI) is disabled."]
2319        pub const _0: Self = Self::new(0);
2320
2321        #[doc = "NACK reception interrupt request (NAKI) is enabled."]
2322        pub const _1: Self = Self::new(1);
2323    }
2324    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2325    pub struct Spie_SPEC;
2326    pub type Spie = crate::EnumBitfieldStruct<u8, Spie_SPEC>;
2327    impl Spie {
2328        #[doc = "Stop condition detection interrupt request (SPI) is disabled."]
2329        pub const _0: Self = Self::new(0);
2330
2331        #[doc = "Stop condition detection interrupt request (SPI) is enabled."]
2332        pub const _1: Self = Self::new(1);
2333    }
2334    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2335    pub struct Stie_SPEC;
2336    pub type Stie = crate::EnumBitfieldStruct<u8, Stie_SPEC>;
2337    impl Stie {
2338        #[doc = "Start condition detection interrupt request (STI) is disabled."]
2339        pub const _0: Self = Self::new(0);
2340
2341        #[doc = "Start condition detection interrupt request (STI) is enabled."]
2342        pub const _1: Self = Self::new(1);
2343    }
2344    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2345    pub struct Alie_SPEC;
2346    pub type Alie = crate::EnumBitfieldStruct<u8, Alie_SPEC>;
2347    impl Alie {
2348        #[doc = "Arbitration-lost interrupt request (ALI) is disabled."]
2349        pub const _0: Self = Self::new(0);
2350
2351        #[doc = "Arbitration-lost interrupt request (ALI) is enabled."]
2352        pub const _1: Self = Self::new(1);
2353    }
2354    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2355    pub struct Tmoie_SPEC;
2356    pub type Tmoie = crate::EnumBitfieldStruct<u8, Tmoie_SPEC>;
2357    impl Tmoie {
2358        #[doc = "Timeout interrupt request (TMOI) is disabled."]
2359        pub const _0: Self = Self::new(0);
2360
2361        #[doc = "Timeout interrupt request (TMOI) is enabled."]
2362        pub const _1: Self = Self::new(1);
2363    }
2364}
2365#[doc(hidden)]
2366#[derive(Copy, Clone, Eq, PartialEq)]
2367pub struct Icsr1_SPEC;
2368impl crate::sealed::RegSpec for Icsr1_SPEC {
2369    type DataType = u8;
2370}
2371
2372#[doc = "I2C Bus Status Register 1"]
2373pub type Icsr1 = crate::RegValueT<Icsr1_SPEC>;
2374
2375impl Icsr1 {
2376    #[doc = "Host Address Detection Flag"]
2377    #[inline(always)]
2378    pub fn hoa(
2379        self,
2380    ) -> crate::common::RegisterField<
2381        7,
2382        0x1,
2383        1,
2384        0,
2385        icsr1::Hoa,
2386        icsr1::Hoa,
2387        Icsr1_SPEC,
2388        crate::common::RW,
2389    > {
2390        crate::common::RegisterField::<
2391            7,
2392            0x1,
2393            1,
2394            0,
2395            icsr1::Hoa,
2396            icsr1::Hoa,
2397            Icsr1_SPEC,
2398            crate::common::RW,
2399        >::from_register(self, 0)
2400    }
2401
2402    #[doc = "Device-ID Address Detection Flag"]
2403    #[inline(always)]
2404    pub fn did(
2405        self,
2406    ) -> crate::common::RegisterField<
2407        5,
2408        0x1,
2409        1,
2410        0,
2411        icsr1::Did,
2412        icsr1::Did,
2413        Icsr1_SPEC,
2414        crate::common::RW,
2415    > {
2416        crate::common::RegisterField::<
2417            5,
2418            0x1,
2419            1,
2420            0,
2421            icsr1::Did,
2422            icsr1::Did,
2423            Icsr1_SPEC,
2424            crate::common::RW,
2425        >::from_register(self, 0)
2426    }
2427
2428    #[doc = "General Call Address Detection Flag"]
2429    #[inline(always)]
2430    pub fn gca(
2431        self,
2432    ) -> crate::common::RegisterField<
2433        3,
2434        0x1,
2435        1,
2436        0,
2437        icsr1::Gca,
2438        icsr1::Gca,
2439        Icsr1_SPEC,
2440        crate::common::RW,
2441    > {
2442        crate::common::RegisterField::<
2443            3,
2444            0x1,
2445            1,
2446            0,
2447            icsr1::Gca,
2448            icsr1::Gca,
2449            Icsr1_SPEC,
2450            crate::common::RW,
2451        >::from_register(self, 0)
2452    }
2453
2454    #[doc = "Slave Address 2 Detection Flag"]
2455    #[inline(always)]
2456    pub fn aas2(
2457        self,
2458    ) -> crate::common::RegisterField<
2459        2,
2460        0x1,
2461        1,
2462        0,
2463        icsr1::Aas2,
2464        icsr1::Aas2,
2465        Icsr1_SPEC,
2466        crate::common::RW,
2467    > {
2468        crate::common::RegisterField::<
2469            2,
2470            0x1,
2471            1,
2472            0,
2473            icsr1::Aas2,
2474            icsr1::Aas2,
2475            Icsr1_SPEC,
2476            crate::common::RW,
2477        >::from_register(self, 0)
2478    }
2479
2480    #[doc = "Slave Address 1 Detection Flag"]
2481    #[inline(always)]
2482    pub fn aas1(
2483        self,
2484    ) -> crate::common::RegisterField<
2485        1,
2486        0x1,
2487        1,
2488        0,
2489        icsr1::Aas1,
2490        icsr1::Aas1,
2491        Icsr1_SPEC,
2492        crate::common::RW,
2493    > {
2494        crate::common::RegisterField::<
2495            1,
2496            0x1,
2497            1,
2498            0,
2499            icsr1::Aas1,
2500            icsr1::Aas1,
2501            Icsr1_SPEC,
2502            crate::common::RW,
2503        >::from_register(self, 0)
2504    }
2505
2506    #[doc = "Slave Address 0 Detection Flag"]
2507    #[inline(always)]
2508    pub fn aas0(
2509        self,
2510    ) -> crate::common::RegisterField<
2511        0,
2512        0x1,
2513        1,
2514        0,
2515        icsr1::Aas0,
2516        icsr1::Aas0,
2517        Icsr1_SPEC,
2518        crate::common::RW,
2519    > {
2520        crate::common::RegisterField::<
2521            0,
2522            0x1,
2523            1,
2524            0,
2525            icsr1::Aas0,
2526            icsr1::Aas0,
2527            Icsr1_SPEC,
2528            crate::common::RW,
2529        >::from_register(self, 0)
2530    }
2531}
2532impl ::core::default::Default for Icsr1 {
2533    #[inline(always)]
2534    fn default() -> Icsr1 {
2535        <crate::RegValueT<Icsr1_SPEC> as RegisterValue<_>>::new(0)
2536    }
2537}
2538pub mod icsr1 {
2539
2540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2541    pub struct Hoa_SPEC;
2542    pub type Hoa = crate::EnumBitfieldStruct<u8, Hoa_SPEC>;
2543    impl Hoa {
2544        #[doc = "Host address is not detected."]
2545        pub const _0: Self = Self::new(0);
2546
2547        #[doc = "Host address is detected."]
2548        pub const _1: Self = Self::new(1);
2549    }
2550    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2551    pub struct Did_SPEC;
2552    pub type Did = crate::EnumBitfieldStruct<u8, Did_SPEC>;
2553    impl Did {
2554        #[doc = "Device-ID command is not detected."]
2555        pub const _0: Self = Self::new(0);
2556
2557        #[doc = "Device-ID command is detected."]
2558        pub const _1: Self = Self::new(1);
2559    }
2560    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2561    pub struct Gca_SPEC;
2562    pub type Gca = crate::EnumBitfieldStruct<u8, Gca_SPEC>;
2563    impl Gca {
2564        #[doc = "General call address is not detected."]
2565        pub const _0: Self = Self::new(0);
2566
2567        #[doc = "General call address is detected."]
2568        pub const _1: Self = Self::new(1);
2569    }
2570    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2571    pub struct Aas2_SPEC;
2572    pub type Aas2 = crate::EnumBitfieldStruct<u8, Aas2_SPEC>;
2573    impl Aas2 {
2574        #[doc = "Slave address 2 is not detected."]
2575        pub const _0: Self = Self::new(0);
2576
2577        #[doc = "Slave address 2 is detected"]
2578        pub const _1: Self = Self::new(1);
2579    }
2580    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2581    pub struct Aas1_SPEC;
2582    pub type Aas1 = crate::EnumBitfieldStruct<u8, Aas1_SPEC>;
2583    impl Aas1 {
2584        #[doc = "Slave address 1 is not detected."]
2585        pub const _0: Self = Self::new(0);
2586
2587        #[doc = "Slave address 1 is detected."]
2588        pub const _1: Self = Self::new(1);
2589    }
2590    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2591    pub struct Aas0_SPEC;
2592    pub type Aas0 = crate::EnumBitfieldStruct<u8, Aas0_SPEC>;
2593    impl Aas0 {
2594        #[doc = "Slave address 0 is not detected."]
2595        pub const _0: Self = Self::new(0);
2596
2597        #[doc = "Slave address 0 is detected."]
2598        pub const _1: Self = Self::new(1);
2599    }
2600}
2601#[doc(hidden)]
2602#[derive(Copy, Clone, Eq, PartialEq)]
2603pub struct Icsr2_SPEC;
2604impl crate::sealed::RegSpec for Icsr2_SPEC {
2605    type DataType = u8;
2606}
2607
2608#[doc = "I2C Bus Status Register 2"]
2609pub type Icsr2 = crate::RegValueT<Icsr2_SPEC>;
2610
2611impl Icsr2 {
2612    #[doc = "Transmit Data Empty Flag"]
2613    #[inline(always)]
2614    pub fn tdre(
2615        self,
2616    ) -> crate::common::RegisterField<
2617        7,
2618        0x1,
2619        1,
2620        0,
2621        icsr2::Tdre,
2622        icsr2::Tdre,
2623        Icsr2_SPEC,
2624        crate::common::R,
2625    > {
2626        crate::common::RegisterField::<
2627            7,
2628            0x1,
2629            1,
2630            0,
2631            icsr2::Tdre,
2632            icsr2::Tdre,
2633            Icsr2_SPEC,
2634            crate::common::R,
2635        >::from_register(self, 0)
2636    }
2637
2638    #[doc = "Transmit End Flag"]
2639    #[inline(always)]
2640    pub fn tend(
2641        self,
2642    ) -> crate::common::RegisterField<
2643        6,
2644        0x1,
2645        1,
2646        0,
2647        icsr2::Tend,
2648        icsr2::Tend,
2649        Icsr2_SPEC,
2650        crate::common::RW,
2651    > {
2652        crate::common::RegisterField::<
2653            6,
2654            0x1,
2655            1,
2656            0,
2657            icsr2::Tend,
2658            icsr2::Tend,
2659            Icsr2_SPEC,
2660            crate::common::RW,
2661        >::from_register(self, 0)
2662    }
2663
2664    #[doc = "Receive Data Full Flag"]
2665    #[inline(always)]
2666    pub fn rdrf(
2667        self,
2668    ) -> crate::common::RegisterField<
2669        5,
2670        0x1,
2671        1,
2672        0,
2673        icsr2::Rdrf,
2674        icsr2::Rdrf,
2675        Icsr2_SPEC,
2676        crate::common::RW,
2677    > {
2678        crate::common::RegisterField::<
2679            5,
2680            0x1,
2681            1,
2682            0,
2683            icsr2::Rdrf,
2684            icsr2::Rdrf,
2685            Icsr2_SPEC,
2686            crate::common::RW,
2687        >::from_register(self, 0)
2688    }
2689
2690    #[doc = "NACK Detection Flag"]
2691    #[inline(always)]
2692    pub fn nackf(
2693        self,
2694    ) -> crate::common::RegisterField<
2695        4,
2696        0x1,
2697        1,
2698        0,
2699        icsr2::Nackf,
2700        icsr2::Nackf,
2701        Icsr2_SPEC,
2702        crate::common::RW,
2703    > {
2704        crate::common::RegisterField::<
2705            4,
2706            0x1,
2707            1,
2708            0,
2709            icsr2::Nackf,
2710            icsr2::Nackf,
2711            Icsr2_SPEC,
2712            crate::common::RW,
2713        >::from_register(self, 0)
2714    }
2715
2716    #[doc = "Stop Condition Detection Flag"]
2717    #[inline(always)]
2718    pub fn stop(
2719        self,
2720    ) -> crate::common::RegisterField<
2721        3,
2722        0x1,
2723        1,
2724        0,
2725        icsr2::Stop,
2726        icsr2::Stop,
2727        Icsr2_SPEC,
2728        crate::common::RW,
2729    > {
2730        crate::common::RegisterField::<
2731            3,
2732            0x1,
2733            1,
2734            0,
2735            icsr2::Stop,
2736            icsr2::Stop,
2737            Icsr2_SPEC,
2738            crate::common::RW,
2739        >::from_register(self, 0)
2740    }
2741
2742    #[doc = "Start Condition Detection Flag"]
2743    #[inline(always)]
2744    pub fn start(
2745        self,
2746    ) -> crate::common::RegisterField<
2747        2,
2748        0x1,
2749        1,
2750        0,
2751        icsr2::Start,
2752        icsr2::Start,
2753        Icsr2_SPEC,
2754        crate::common::RW,
2755    > {
2756        crate::common::RegisterField::<
2757            2,
2758            0x1,
2759            1,
2760            0,
2761            icsr2::Start,
2762            icsr2::Start,
2763            Icsr2_SPEC,
2764            crate::common::RW,
2765        >::from_register(self, 0)
2766    }
2767
2768    #[doc = "Arbitration-Lost Flag"]
2769    #[inline(always)]
2770    pub fn al(
2771        self,
2772    ) -> crate::common::RegisterField<
2773        1,
2774        0x1,
2775        1,
2776        0,
2777        icsr2::Al,
2778        icsr2::Al,
2779        Icsr2_SPEC,
2780        crate::common::RW,
2781    > {
2782        crate::common::RegisterField::<
2783            1,
2784            0x1,
2785            1,
2786            0,
2787            icsr2::Al,
2788            icsr2::Al,
2789            Icsr2_SPEC,
2790            crate::common::RW,
2791        >::from_register(self, 0)
2792    }
2793
2794    #[doc = "Timeout Detection Flag"]
2795    #[inline(always)]
2796    pub fn tmof(
2797        self,
2798    ) -> crate::common::RegisterField<
2799        0,
2800        0x1,
2801        1,
2802        0,
2803        icsr2::Tmof,
2804        icsr2::Tmof,
2805        Icsr2_SPEC,
2806        crate::common::RW,
2807    > {
2808        crate::common::RegisterField::<
2809            0,
2810            0x1,
2811            1,
2812            0,
2813            icsr2::Tmof,
2814            icsr2::Tmof,
2815            Icsr2_SPEC,
2816            crate::common::RW,
2817        >::from_register(self, 0)
2818    }
2819}
2820impl ::core::default::Default for Icsr2 {
2821    #[inline(always)]
2822    fn default() -> Icsr2 {
2823        <crate::RegValueT<Icsr2_SPEC> as RegisterValue<_>>::new(0)
2824    }
2825}
2826pub mod icsr2 {
2827
2828    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2829    pub struct Tdre_SPEC;
2830    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
2831    impl Tdre {
2832        #[doc = "ICDRT contains transmit data."]
2833        pub const _0: Self = Self::new(0);
2834
2835        #[doc = "ICDRT contains no transmit data."]
2836        pub const _1: Self = Self::new(1);
2837    }
2838    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2839    pub struct Tend_SPEC;
2840    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
2841    impl Tend {
2842        #[doc = "Data is being transmitted."]
2843        pub const _0: Self = Self::new(0);
2844
2845        #[doc = "Data has been transmitted."]
2846        pub const _1: Self = Self::new(1);
2847    }
2848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2849    pub struct Rdrf_SPEC;
2850    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
2851    impl Rdrf {
2852        #[doc = "ICDRR contains no receive data."]
2853        pub const _0: Self = Self::new(0);
2854
2855        #[doc = "ICDRR contains receive data."]
2856        pub const _1: Self = Self::new(1);
2857    }
2858    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2859    pub struct Nackf_SPEC;
2860    pub type Nackf = crate::EnumBitfieldStruct<u8, Nackf_SPEC>;
2861    impl Nackf {
2862        #[doc = "NACK is not detected."]
2863        pub const _0: Self = Self::new(0);
2864
2865        #[doc = "NACK is detected."]
2866        pub const _1: Self = Self::new(1);
2867    }
2868    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2869    pub struct Stop_SPEC;
2870    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
2871    impl Stop {
2872        #[doc = "Stop condition is not detected."]
2873        pub const _0: Self = Self::new(0);
2874
2875        #[doc = "Stop condition is detected."]
2876        pub const _1: Self = Self::new(1);
2877    }
2878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2879    pub struct Start_SPEC;
2880    pub type Start = crate::EnumBitfieldStruct<u8, Start_SPEC>;
2881    impl Start {
2882        #[doc = "Start condition is not detected."]
2883        pub const _0: Self = Self::new(0);
2884
2885        #[doc = "Start condition is detected."]
2886        pub const _1: Self = Self::new(1);
2887    }
2888    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2889    pub struct Al_SPEC;
2890    pub type Al = crate::EnumBitfieldStruct<u8, Al_SPEC>;
2891    impl Al {
2892        #[doc = "Arbitration is not lost."]
2893        pub const _0: Self = Self::new(0);
2894
2895        #[doc = "Arbitration is lost."]
2896        pub const _1: Self = Self::new(1);
2897    }
2898    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2899    pub struct Tmof_SPEC;
2900    pub type Tmof = crate::EnumBitfieldStruct<u8, Tmof_SPEC>;
2901    impl Tmof {
2902        #[doc = "Timeout is not detected."]
2903        pub const _0: Self = Self::new(0);
2904
2905        #[doc = "Timeout is detected."]
2906        pub const _1: Self = Self::new(1);
2907    }
2908}
2909#[doc(hidden)]
2910#[derive(Copy, Clone, Eq, PartialEq)]
2911pub struct Sarl_SPEC;
2912impl crate::sealed::RegSpec for Sarl_SPEC {
2913    type DataType = u8;
2914}
2915
2916#[doc = "Slave Address Register L%s"]
2917pub type Sarl = crate::RegValueT<Sarl_SPEC>;
2918
2919impl Sarl {
2920    #[doc = "A slave address is set.7-Bit Address = SVA\\[7:1\\] 10-Bit Address = { SVA9,SVA8,SVA\\[7:0\\] }"]
2921    #[inline(always)]
2922    pub fn sva(
2923        self,
2924    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sarl_SPEC, crate::common::RW> {
2925        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sarl_SPEC,crate::common::RW>::from_register(self,0)
2926    }
2927}
2928impl ::core::default::Default for Sarl {
2929    #[inline(always)]
2930    fn default() -> Sarl {
2931        <crate::RegValueT<Sarl_SPEC> as RegisterValue<_>>::new(0)
2932    }
2933}
2934
2935#[doc(hidden)]
2936#[derive(Copy, Clone, Eq, PartialEq)]
2937pub struct Saru_SPEC;
2938impl crate::sealed::RegSpec for Saru_SPEC {
2939    type DataType = u8;
2940}
2941
2942#[doc = "Slave Address Register U%s"]
2943pub type Saru = crate::RegValueT<Saru_SPEC>;
2944
2945impl Saru {
2946    #[doc = "10-Bit Address(bit9)"]
2947    #[inline(always)]
2948    pub fn sva9(self) -> crate::common::RegisterFieldBool<2, 1, 0, Saru_SPEC, crate::common::RW> {
2949        crate::common::RegisterFieldBool::<2, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2950            self, 0,
2951        )
2952    }
2953
2954    #[doc = "10-Bit Address(bit8)"]
2955    #[inline(always)]
2956    pub fn sva8(self) -> crate::common::RegisterFieldBool<1, 1, 0, Saru_SPEC, crate::common::RW> {
2957        crate::common::RegisterFieldBool::<1, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2958            self, 0,
2959        )
2960    }
2961
2962    #[doc = "7-Bit/10-Bit Address Format Selection"]
2963    #[inline(always)]
2964    pub fn fs(
2965        self,
2966    ) -> crate::common::RegisterField<0, 0x1, 1, 0, saru::Fs, saru::Fs, Saru_SPEC, crate::common::RW>
2967    {
2968        crate::common::RegisterField::<0,0x1,1,0,saru::Fs,saru::Fs,Saru_SPEC,crate::common::RW>::from_register(self,0)
2969    }
2970}
2971impl ::core::default::Default for Saru {
2972    #[inline(always)]
2973    fn default() -> Saru {
2974        <crate::RegValueT<Saru_SPEC> as RegisterValue<_>>::new(0)
2975    }
2976}
2977pub mod saru {
2978
2979    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2980    pub struct Fs_SPEC;
2981    pub type Fs = crate::EnumBitfieldStruct<u8, Fs_SPEC>;
2982    impl Fs {
2983        #[doc = "The 7-bit address format is selected."]
2984        pub const _0: Self = Self::new(0);
2985
2986        #[doc = "The 10-bit address format is selected."]
2987        pub const _1: Self = Self::new(1);
2988    }
2989}
2990#[doc(hidden)]
2991#[derive(Copy, Clone, Eq, PartialEq)]
2992pub struct Icbrl_SPEC;
2993impl crate::sealed::RegSpec for Icbrl_SPEC {
2994    type DataType = u8;
2995}
2996
2997#[doc = "I2C Bus Bit Rate Low-Level Register"]
2998pub type Icbrl = crate::RegValueT<Icbrl_SPEC>;
2999
3000impl Icbrl {
3001    #[doc = "Bit Rate Low-Level Period(Low-level period of SCL clock)"]
3002    #[inline(always)]
3003    pub fn brl(
3004        self,
3005    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
3006        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
3007    }
3008}
3009impl ::core::default::Default for Icbrl {
3010    #[inline(always)]
3011    fn default() -> Icbrl {
3012        <crate::RegValueT<Icbrl_SPEC> as RegisterValue<_>>::new(255)
3013    }
3014}
3015
3016#[doc(hidden)]
3017#[derive(Copy, Clone, Eq, PartialEq)]
3018pub struct Icbrh_SPEC;
3019impl crate::sealed::RegSpec for Icbrh_SPEC {
3020    type DataType = u8;
3021}
3022
3023#[doc = "I2C Bus Bit Rate High-Level Register"]
3024pub type Icbrh = crate::RegValueT<Icbrh_SPEC>;
3025
3026impl Icbrh {
3027    #[doc = "Bit Rate High-Level Period(High-level period of SCL clock)"]
3028    #[inline(always)]
3029    pub fn brh(
3030        self,
3031    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3032        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3033    }
3034}
3035impl ::core::default::Default for Icbrh {
3036    #[inline(always)]
3037    fn default() -> Icbrh {
3038        <crate::RegValueT<Icbrh_SPEC> as RegisterValue<_>>::new(255)
3039    }
3040}
3041
3042#[doc(hidden)]
3043#[derive(Copy, Clone, Eq, PartialEq)]
3044pub struct Icdrt_SPEC;
3045impl crate::sealed::RegSpec for Icdrt_SPEC {
3046    type DataType = u8;
3047}
3048
3049#[doc = "I2C Bus Transmit Data Register"]
3050pub type Icdrt = crate::RegValueT<Icdrt_SPEC>;
3051
3052impl Icdrt {
3053    #[doc = "8-bit read-write register that stores transmit data."]
3054    #[inline(always)]
3055    pub fn icdrt(
3056        self,
3057    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrt_SPEC, crate::common::RW> {
3058        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrt_SPEC,crate::common::RW>::from_register(self,0)
3059    }
3060}
3061impl ::core::default::Default for Icdrt {
3062    #[inline(always)]
3063    fn default() -> Icdrt {
3064        <crate::RegValueT<Icdrt_SPEC> as RegisterValue<_>>::new(255)
3065    }
3066}
3067
3068#[doc(hidden)]
3069#[derive(Copy, Clone, Eq, PartialEq)]
3070pub struct Icdrr_SPEC;
3071impl crate::sealed::RegSpec for Icdrr_SPEC {
3072    type DataType = u8;
3073}
3074
3075#[doc = "I2C Bus Receive Data Register"]
3076pub type Icdrr = crate::RegValueT<Icdrr_SPEC>;
3077
3078impl Icdrr {
3079    #[doc = "8-bit register that stores the received data"]
3080    #[inline(always)]
3081    pub fn icdrr(
3082        self,
3083    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrr_SPEC, crate::common::R> {
3084        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrr_SPEC,crate::common::R>::from_register(self,0)
3085    }
3086}
3087impl ::core::default::Default for Icdrr {
3088    #[inline(always)]
3089    fn default() -> Icdrr {
3090        <crate::RegValueT<Icdrr_SPEC> as RegisterValue<_>>::new(0)
3091    }
3092}
3093
3094#[doc(hidden)]
3095#[derive(Copy, Clone, Eq, PartialEq)]
3096pub struct Icwur_SPEC;
3097impl crate::sealed::RegSpec for Icwur_SPEC {
3098    type DataType = u8;
3099}
3100
3101#[doc = "I2C Bus Wake Up Unit Register"]
3102pub type Icwur = crate::RegValueT<Icwur_SPEC>;
3103
3104impl Icwur {
3105    #[doc = "Wake Up function Enable"]
3106    #[inline(always)]
3107    pub fn wue(
3108        self,
3109    ) -> crate::common::RegisterField<
3110        7,
3111        0x1,
3112        1,
3113        0,
3114        icwur::Wue,
3115        icwur::Wue,
3116        Icwur_SPEC,
3117        crate::common::RW,
3118    > {
3119        crate::common::RegisterField::<
3120            7,
3121            0x1,
3122            1,
3123            0,
3124            icwur::Wue,
3125            icwur::Wue,
3126            Icwur_SPEC,
3127            crate::common::RW,
3128        >::from_register(self, 0)
3129    }
3130
3131    #[doc = "Wake Up Interrupt Request Enable"]
3132    #[inline(always)]
3133    pub fn wuie(
3134        self,
3135    ) -> crate::common::RegisterField<
3136        6,
3137        0x1,
3138        1,
3139        0,
3140        icwur::Wuie,
3141        icwur::Wuie,
3142        Icwur_SPEC,
3143        crate::common::RW,
3144    > {
3145        crate::common::RegisterField::<
3146            6,
3147            0x1,
3148            1,
3149            0,
3150            icwur::Wuie,
3151            icwur::Wuie,
3152            Icwur_SPEC,
3153            crate::common::RW,
3154        >::from_register(self, 0)
3155    }
3156
3157    #[doc = "Wake-Up Event Occurrence Flag"]
3158    #[inline(always)]
3159    pub fn wuf(
3160        self,
3161    ) -> crate::common::RegisterField<
3162        5,
3163        0x1,
3164        1,
3165        0,
3166        icwur::Wuf,
3167        icwur::Wuf,
3168        Icwur_SPEC,
3169        crate::common::RW,
3170    > {
3171        crate::common::RegisterField::<
3172            5,
3173            0x1,
3174            1,
3175            0,
3176            icwur::Wuf,
3177            icwur::Wuf,
3178            Icwur_SPEC,
3179            crate::common::RW,
3180        >::from_register(self, 0)
3181    }
3182
3183    #[doc = "Asynchronous/Synchronous Operation State Flag"]
3184    #[inline(always)]
3185    pub fn wuack(
3186        self,
3187    ) -> crate::common::RegisterField<
3188        4,
3189        0x1,
3190        1,
3191        0,
3192        icwur::Wuack,
3193        icwur::Wuack,
3194        Icwur_SPEC,
3195        crate::common::RW,
3196    > {
3197        crate::common::RegisterField::<
3198            4,
3199            0x1,
3200            1,
3201            0,
3202            icwur::Wuack,
3203            icwur::Wuack,
3204            Icwur_SPEC,
3205            crate::common::RW,
3206        >::from_register(self, 0)
3207    }
3208
3209    #[doc = "Wake-Up Analog Filter Additional Selection"]
3210    #[inline(always)]
3211    pub fn wuafa(
3212        self,
3213    ) -> crate::common::RegisterField<
3214        0,
3215        0x1,
3216        1,
3217        0,
3218        icwur::Wuafa,
3219        icwur::Wuafa,
3220        Icwur_SPEC,
3221        crate::common::RW,
3222    > {
3223        crate::common::RegisterField::<
3224            0,
3225            0x1,
3226            1,
3227            0,
3228            icwur::Wuafa,
3229            icwur::Wuafa,
3230            Icwur_SPEC,
3231            crate::common::RW,
3232        >::from_register(self, 0)
3233    }
3234}
3235impl ::core::default::Default for Icwur {
3236    #[inline(always)]
3237    fn default() -> Icwur {
3238        <crate::RegValueT<Icwur_SPEC> as RegisterValue<_>>::new(0)
3239    }
3240}
3241pub mod icwur {
3242
3243    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3244    pub struct Wue_SPEC;
3245    pub type Wue = crate::EnumBitfieldStruct<u8, Wue_SPEC>;
3246    impl Wue {
3247        #[doc = "Wake-up function is disabled"]
3248        pub const _0: Self = Self::new(0);
3249
3250        #[doc = "Wake-up function is enabled."]
3251        pub const _1: Self = Self::new(1);
3252    }
3253    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3254    pub struct Wuie_SPEC;
3255    pub type Wuie = crate::EnumBitfieldStruct<u8, Wuie_SPEC>;
3256    impl Wuie {
3257        #[doc = "Wake Up Interrupt Request (WUI) is disabled."]
3258        pub const _0: Self = Self::new(0);
3259
3260        #[doc = "Wake Up Interrupt Request (WUI) is enabled."]
3261        pub const _1: Self = Self::new(1);
3262    }
3263    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3264    pub struct Wuf_SPEC;
3265    pub type Wuf = crate::EnumBitfieldStruct<u8, Wuf_SPEC>;
3266    impl Wuf {
3267        #[doc = "Slave address match during Wake-Up function."]
3268        pub const _0: Self = Self::new(0);
3269
3270        #[doc = "Slave address not match during Wake-Up function."]
3271        pub const _1: Self = Self::new(1);
3272    }
3273    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3274    pub struct Wuack_SPEC;
3275    pub type Wuack = crate::EnumBitfieldStruct<u8, Wuack_SPEC>;
3276    impl Wuack {
3277        #[doc = "State of synchronous operation"]
3278        pub const _0: Self = Self::new(0);
3279
3280        #[doc = "State of asynchronous operation"]
3281        pub const _1: Self = Self::new(1);
3282    }
3283    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3284    pub struct Wuafa_SPEC;
3285    pub type Wuafa = crate::EnumBitfieldStruct<u8, Wuafa_SPEC>;
3286    impl Wuafa {
3287        #[doc = "Do not add the Wake Up analog filter."]
3288        pub const _0: Self = Self::new(0);
3289
3290        #[doc = "Add the Wake Up analog filter."]
3291        pub const _1: Self = Self::new(1);
3292    }
3293}
3294#[doc(hidden)]
3295#[derive(Copy, Clone, Eq, PartialEq)]
3296pub struct Icwur2_SPEC;
3297impl crate::sealed::RegSpec for Icwur2_SPEC {
3298    type DataType = u8;
3299}
3300
3301#[doc = "I2C Bus Wake Up Unit Register 2"]
3302pub type Icwur2 = crate::RegValueT<Icwur2_SPEC>;
3303
3304impl Icwur2 {
3305    #[doc = "Wake-Up function synchronous operation status flag"]
3306    #[inline(always)]
3307    pub fn wusyf(
3308        self,
3309    ) -> crate::common::RegisterField<
3310        2,
3311        0x1,
3312        1,
3313        0,
3314        icwur2::Wusyf,
3315        icwur2::Wusyf,
3316        Icwur2_SPEC,
3317        crate::common::R,
3318    > {
3319        crate::common::RegisterField::<
3320            2,
3321            0x1,
3322            1,
3323            0,
3324            icwur2::Wusyf,
3325            icwur2::Wusyf,
3326            Icwur2_SPEC,
3327            crate::common::R,
3328        >::from_register(self, 0)
3329    }
3330
3331    #[doc = "Wake-Up function asynchronous operation status flag"]
3332    #[inline(always)]
3333    pub fn wuasyf(
3334        self,
3335    ) -> crate::common::RegisterField<
3336        1,
3337        0x1,
3338        1,
3339        0,
3340        icwur2::Wuasyf,
3341        icwur2::Wuasyf,
3342        Icwur2_SPEC,
3343        crate::common::R,
3344    > {
3345        crate::common::RegisterField::<
3346            1,
3347            0x1,
3348            1,
3349            0,
3350            icwur2::Wuasyf,
3351            icwur2::Wuasyf,
3352            Icwur2_SPEC,
3353            crate::common::R,
3354        >::from_register(self, 0)
3355    }
3356
3357    #[doc = "Wake-Up function synchronous enable"]
3358    #[inline(always)]
3359    pub fn wusen(
3360        self,
3361    ) -> crate::common::RegisterField<
3362        0,
3363        0x1,
3364        1,
3365        0,
3366        icwur2::Wusen,
3367        icwur2::Wusen,
3368        Icwur2_SPEC,
3369        crate::common::RW,
3370    > {
3371        crate::common::RegisterField::<
3372            0,
3373            0x1,
3374            1,
3375            0,
3376            icwur2::Wusen,
3377            icwur2::Wusen,
3378            Icwur2_SPEC,
3379            crate::common::RW,
3380        >::from_register(self, 0)
3381    }
3382}
3383impl ::core::default::Default for Icwur2 {
3384    #[inline(always)]
3385    fn default() -> Icwur2 {
3386        <crate::RegValueT<Icwur2_SPEC> as RegisterValue<_>>::new(3)
3387    }
3388}
3389pub mod icwur2 {
3390
3391    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3392    pub struct Wusyf_SPEC;
3393    pub type Wusyf = crate::EnumBitfieldStruct<u8, Wusyf_SPEC>;
3394    impl Wusyf {
3395        #[doc = "IIC asynchronous circuit enable condition"]
3396        pub const _0: Self = Self::new(0);
3397
3398        #[doc = "IIC synchronous circuit enable condition"]
3399        pub const _1: Self = Self::new(1);
3400    }
3401    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3402    pub struct Wuasyf_SPEC;
3403    pub type Wuasyf = crate::EnumBitfieldStruct<u8, Wuasyf_SPEC>;
3404    impl Wuasyf {
3405        #[doc = "IIC synchronous circuit enable condition"]
3406        pub const _0: Self = Self::new(0);
3407
3408        #[doc = "IIC asynchronous circuit enable condition"]
3409        pub const _1: Self = Self::new(1);
3410    }
3411    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3412    pub struct Wusen_SPEC;
3413    pub type Wusen = crate::EnumBitfieldStruct<u8, Wusen_SPEC>;
3414    impl Wusen {
3415        #[doc = "IIC asynchronous circuit enable"]
3416        pub const _0: Self = Self::new(0);
3417
3418        #[doc = "IIC synchronous circuit enable"]
3419        pub const _1: Self = Self::new(1);
3420    }
3421}
ra6m2_pac/iic0.rs

ra6m2_pac/
iic0.rs
