1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Direct memory access controller 0"]
28unsafe impl ::core::marker::Send for super::Dmac0 {}
29unsafe impl ::core::marker::Sync for super::Dmac0 {}
30impl super::Dmac0 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "DMA Source Address Register"]
38 #[inline(always)]
39 pub const fn dmsar(&self) -> &'static crate::common::Reg<self::Dmsar_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Dmsar_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "DMA Destination Address Register"]
48 #[inline(always)]
49 pub const fn dmdar(&self) -> &'static crate::common::Reg<self::Dmdar_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Dmdar_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "DMA Transfer Count Register"]
58 #[inline(always)]
59 pub const fn dmcra(&self) -> &'static crate::common::Reg<self::Dmcra_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Dmcra_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(8usize),
63 )
64 }
65 }
66
67 #[doc = "DMA Block Transfer Count Register"]
68 #[inline(always)]
69 pub const fn dmcrb(&self) -> &'static crate::common::Reg<self::Dmcrb_SPEC, crate::common::RW> {
70 unsafe {
71 crate::common::Reg::<self::Dmcrb_SPEC, crate::common::RW>::from_ptr(
72 self._svd2pac_as_ptr().add(12usize),
73 )
74 }
75 }
76
77 #[doc = "DMA Transfer Mode Register"]
78 #[inline(always)]
79 pub const fn dmtmd(&self) -> &'static crate::common::Reg<self::Dmtmd_SPEC, crate::common::RW> {
80 unsafe {
81 crate::common::Reg::<self::Dmtmd_SPEC, crate::common::RW>::from_ptr(
82 self._svd2pac_as_ptr().add(16usize),
83 )
84 }
85 }
86
87 #[doc = "DMA Interrupt Setting Register"]
88 #[inline(always)]
89 pub const fn dmint(&self) -> &'static crate::common::Reg<self::Dmint_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Dmint_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(19usize),
93 )
94 }
95 }
96
97 #[doc = "DMA Address Mode Register"]
98 #[inline(always)]
99 pub const fn dmamd(&self) -> &'static crate::common::Reg<self::Dmamd_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Dmamd_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(20usize),
103 )
104 }
105 }
106
107 #[doc = "DMA Offset Register"]
108 #[inline(always)]
109 pub const fn dmofr(&self) -> &'static crate::common::Reg<self::Dmofr_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::Dmofr_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(24usize),
113 )
114 }
115 }
116
117 #[doc = "DMA Transfer Enable Register"]
118 #[inline(always)]
119 pub const fn dmcnt(&self) -> &'static crate::common::Reg<self::Dmcnt_SPEC, crate::common::RW> {
120 unsafe {
121 crate::common::Reg::<self::Dmcnt_SPEC, crate::common::RW>::from_ptr(
122 self._svd2pac_as_ptr().add(28usize),
123 )
124 }
125 }
126
127 #[doc = "DMA Software Start Register"]
128 #[inline(always)]
129 pub const fn dmreq(&self) -> &'static crate::common::Reg<self::Dmreq_SPEC, crate::common::RW> {
130 unsafe {
131 crate::common::Reg::<self::Dmreq_SPEC, crate::common::RW>::from_ptr(
132 self._svd2pac_as_ptr().add(29usize),
133 )
134 }
135 }
136
137 #[doc = "DMAC Module Activation Register"]
138 #[inline(always)]
139 pub const fn dmsts(&self) -> &'static crate::common::Reg<self::Dmsts_SPEC, crate::common::RW> {
140 unsafe {
141 crate::common::Reg::<self::Dmsts_SPEC, crate::common::RW>::from_ptr(
142 self._svd2pac_as_ptr().add(30usize),
143 )
144 }
145 }
146}
147#[doc(hidden)]
148#[derive(Copy, Clone, Eq, PartialEq)]
149pub struct Dmsar_SPEC;
150impl crate::sealed::RegSpec for Dmsar_SPEC {
151 type DataType = u32;
152}
153
154#[doc = "DMA Source Address Register"]
155pub type Dmsar = crate::RegValueT<Dmsar_SPEC>;
156
157impl Dmsar {
158 #[doc = "Specifies the transfer source start address."]
159 #[inline(always)]
160 pub fn dmsar(
161 self,
162 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Dmsar_SPEC, crate::common::RW>
163 {
164 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Dmsar_SPEC,crate::common::RW>::from_register(self,0)
165 }
166}
167impl ::core::default::Default for Dmsar {
168 #[inline(always)]
169 fn default() -> Dmsar {
170 <crate::RegValueT<Dmsar_SPEC> as RegisterValue<_>>::new(0)
171 }
172}
173
174#[doc(hidden)]
175#[derive(Copy, Clone, Eq, PartialEq)]
176pub struct Dmdar_SPEC;
177impl crate::sealed::RegSpec for Dmdar_SPEC {
178 type DataType = u32;
179}
180
181#[doc = "DMA Destination Address Register"]
182pub type Dmdar = crate::RegValueT<Dmdar_SPEC>;
183
184impl Dmdar {
185 #[doc = "Specifies the transfer destination start address."]
186 #[inline(always)]
187 pub fn dmdar(
188 self,
189 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Dmdar_SPEC, crate::common::RW>
190 {
191 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Dmdar_SPEC,crate::common::RW>::from_register(self,0)
192 }
193}
194impl ::core::default::Default for Dmdar {
195 #[inline(always)]
196 fn default() -> Dmdar {
197 <crate::RegValueT<Dmdar_SPEC> as RegisterValue<_>>::new(0)
198 }
199}
200
201#[doc(hidden)]
202#[derive(Copy, Clone, Eq, PartialEq)]
203pub struct Dmcra_SPEC;
204impl crate::sealed::RegSpec for Dmcra_SPEC {
205 type DataType = u32;
206}
207
208#[doc = "DMA Transfer Count Register"]
209pub type Dmcra = crate::RegValueT<Dmcra_SPEC>;
210
211impl Dmcra {
212 #[doc = "Upper bits of transfer count"]
213 #[inline(always)]
214 pub fn dmcrah(
215 self,
216 ) -> crate::common::RegisterField<16, 0x3ff, 1, 0, u16, u16, Dmcra_SPEC, crate::common::RW>
217 {
218 crate::common::RegisterField::<16,0x3ff,1,0,u16,u16,Dmcra_SPEC,crate::common::RW>::from_register(self,0)
219 }
220
221 #[doc = "Lower bits of transfer count"]
222 #[inline(always)]
223 pub fn dmcral(
224 self,
225 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Dmcra_SPEC, crate::common::RW>
226 {
227 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Dmcra_SPEC,crate::common::RW>::from_register(self,0)
228 }
229}
230impl ::core::default::Default for Dmcra {
231 #[inline(always)]
232 fn default() -> Dmcra {
233 <crate::RegValueT<Dmcra_SPEC> as RegisterValue<_>>::new(0)
234 }
235}
236
237#[doc(hidden)]
238#[derive(Copy, Clone, Eq, PartialEq)]
239pub struct Dmcrb_SPEC;
240impl crate::sealed::RegSpec for Dmcrb_SPEC {
241 type DataType = u16;
242}
243
244#[doc = "DMA Block Transfer Count Register"]
245pub type Dmcrb = crate::RegValueT<Dmcrb_SPEC>;
246
247impl Dmcrb {
248 #[doc = "Specifies the number of block transfer operations or repeat transfer operations."]
249 #[inline(always)]
250 pub fn dmcrb(
251 self,
252 ) -> crate::common::RegisterField<
253 0,
254 0xffff,
255 1,
256 0,
257 dmcrb::Dmcrb,
258 dmcrb::Dmcrb,
259 Dmcrb_SPEC,
260 crate::common::RW,
261 > {
262 crate::common::RegisterField::<
263 0,
264 0xffff,
265 1,
266 0,
267 dmcrb::Dmcrb,
268 dmcrb::Dmcrb,
269 Dmcrb_SPEC,
270 crate::common::RW,
271 >::from_register(self, 0)
272 }
273}
274impl ::core::default::Default for Dmcrb {
275 #[inline(always)]
276 fn default() -> Dmcrb {
277 <crate::RegValueT<Dmcrb_SPEC> as RegisterValue<_>>::new(0)
278 }
279}
280pub mod dmcrb {
281
282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
283 pub struct Dmcrb_SPEC;
284 pub type Dmcrb = crate::EnumBitfieldStruct<u8, Dmcrb_SPEC>;
285 impl Dmcrb {
286 #[doc = "65,536 blocks"]
287 pub const _0000: Self = Self::new(0);
288 }
289}
290#[doc(hidden)]
291#[derive(Copy, Clone, Eq, PartialEq)]
292pub struct Dmtmd_SPEC;
293impl crate::sealed::RegSpec for Dmtmd_SPEC {
294 type DataType = u16;
295}
296
297#[doc = "DMA Transfer Mode Register"]
298pub type Dmtmd = crate::RegValueT<Dmtmd_SPEC>;
299
300impl Dmtmd {
301 #[doc = "Transfer Mode Select"]
302 #[inline(always)]
303 pub fn md(
304 self,
305 ) -> crate::common::RegisterField<
306 14,
307 0x3,
308 1,
309 0,
310 dmtmd::Md,
311 dmtmd::Md,
312 Dmtmd_SPEC,
313 crate::common::RW,
314 > {
315 crate::common::RegisterField::<
316 14,
317 0x3,
318 1,
319 0,
320 dmtmd::Md,
321 dmtmd::Md,
322 Dmtmd_SPEC,
323 crate::common::RW,
324 >::from_register(self, 0)
325 }
326
327 #[doc = "Repeat Area Select"]
328 #[inline(always)]
329 pub fn dts(
330 self,
331 ) -> crate::common::RegisterField<
332 12,
333 0x3,
334 1,
335 0,
336 dmtmd::Dts,
337 dmtmd::Dts,
338 Dmtmd_SPEC,
339 crate::common::RW,
340 > {
341 crate::common::RegisterField::<
342 12,
343 0x3,
344 1,
345 0,
346 dmtmd::Dts,
347 dmtmd::Dts,
348 Dmtmd_SPEC,
349 crate::common::RW,
350 >::from_register(self, 0)
351 }
352
353 #[doc = "Transfer Data Size Select"]
354 #[inline(always)]
355 pub fn sz(
356 self,
357 ) -> crate::common::RegisterField<
358 8,
359 0x3,
360 1,
361 0,
362 dmtmd::Sz,
363 dmtmd::Sz,
364 Dmtmd_SPEC,
365 crate::common::RW,
366 > {
367 crate::common::RegisterField::<
368 8,
369 0x3,
370 1,
371 0,
372 dmtmd::Sz,
373 dmtmd::Sz,
374 Dmtmd_SPEC,
375 crate::common::RW,
376 >::from_register(self, 0)
377 }
378
379 #[doc = "Transfer Request Source Select"]
380 #[inline(always)]
381 pub fn dctg(
382 self,
383 ) -> crate::common::RegisterField<
384 0,
385 0x3,
386 1,
387 0,
388 dmtmd::Dctg,
389 dmtmd::Dctg,
390 Dmtmd_SPEC,
391 crate::common::RW,
392 > {
393 crate::common::RegisterField::<
394 0,
395 0x3,
396 1,
397 0,
398 dmtmd::Dctg,
399 dmtmd::Dctg,
400 Dmtmd_SPEC,
401 crate::common::RW,
402 >::from_register(self, 0)
403 }
404}
405impl ::core::default::Default for Dmtmd {
406 #[inline(always)]
407 fn default() -> Dmtmd {
408 <crate::RegValueT<Dmtmd_SPEC> as RegisterValue<_>>::new(0)
409 }
410}
411pub mod dmtmd {
412
413 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
414 pub struct Md_SPEC;
415 pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
416 impl Md {
417 #[doc = "Normal transfer"]
418 pub const _00: Self = Self::new(0);
419
420 #[doc = "Repeat transfer"]
421 pub const _01: Self = Self::new(1);
422
423 #[doc = "Block transfer"]
424 pub const _10: Self = Self::new(2);
425
426 #[doc = "Setting prohibited"]
427 pub const _11: Self = Self::new(3);
428 }
429 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
430 pub struct Dts_SPEC;
431 pub type Dts = crate::EnumBitfieldStruct<u8, Dts_SPEC>;
432 impl Dts {
433 #[doc = "Specify destination as the repeat area or block area"]
434 pub const _00: Self = Self::new(0);
435
436 #[doc = "Specify source as the repeat area or block area"]
437 pub const _01: Self = Self::new(1);
438
439 #[doc = "Do not specify repeat area or block area"]
440 pub const _10: Self = Self::new(2);
441
442 #[doc = "Setting prohibited"]
443 pub const _11: Self = Self::new(3);
444 }
445 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
446 pub struct Sz_SPEC;
447 pub type Sz = crate::EnumBitfieldStruct<u8, Sz_SPEC>;
448 impl Sz {
449 #[doc = "8 bits"]
450 pub const _00: Self = Self::new(0);
451
452 #[doc = "16 bits"]
453 pub const _01: Self = Self::new(1);
454
455 #[doc = "32 bits"]
456 pub const _10: Self = Self::new(2);
457
458 #[doc = "Setting prohibited"]
459 pub const _11: Self = Self::new(3);
460 }
461 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
462 pub struct Dctg_SPEC;
463 pub type Dctg = crate::EnumBitfieldStruct<u8, Dctg_SPEC>;
464 impl Dctg {
465 #[doc = "Software"]
466 pub const _00: Self = Self::new(0);
467
468 #[doc = "Interrupts from peripheral modules or external interrupt input pins"]
469 pub const _01: Self = Self::new(1);
470 }
471}
472#[doc(hidden)]
473#[derive(Copy, Clone, Eq, PartialEq)]
474pub struct Dmint_SPEC;
475impl crate::sealed::RegSpec for Dmint_SPEC {
476 type DataType = u8;
477}
478
479#[doc = "DMA Interrupt Setting Register"]
480pub type Dmint = crate::RegValueT<Dmint_SPEC>;
481
482impl Dmint {
483 #[doc = "Transfer End Interrupt Enable"]
484 #[inline(always)]
485 pub fn dtie(
486 self,
487 ) -> crate::common::RegisterField<
488 4,
489 0x1,
490 1,
491 0,
492 dmint::Dtie,
493 dmint::Dtie,
494 Dmint_SPEC,
495 crate::common::RW,
496 > {
497 crate::common::RegisterField::<
498 4,
499 0x1,
500 1,
501 0,
502 dmint::Dtie,
503 dmint::Dtie,
504 Dmint_SPEC,
505 crate::common::RW,
506 >::from_register(self, 0)
507 }
508
509 #[doc = "Transfer Escape End Interrupt Enable"]
510 #[inline(always)]
511 pub fn esie(
512 self,
513 ) -> crate::common::RegisterField<
514 3,
515 0x1,
516 1,
517 0,
518 dmint::Esie,
519 dmint::Esie,
520 Dmint_SPEC,
521 crate::common::RW,
522 > {
523 crate::common::RegisterField::<
524 3,
525 0x1,
526 1,
527 0,
528 dmint::Esie,
529 dmint::Esie,
530 Dmint_SPEC,
531 crate::common::RW,
532 >::from_register(self, 0)
533 }
534
535 #[doc = "Repeat Size End Interrupt Enable"]
536 #[inline(always)]
537 pub fn rptie(
538 self,
539 ) -> crate::common::RegisterField<
540 2,
541 0x1,
542 1,
543 0,
544 dmint::Rptie,
545 dmint::Rptie,
546 Dmint_SPEC,
547 crate::common::RW,
548 > {
549 crate::common::RegisterField::<
550 2,
551 0x1,
552 1,
553 0,
554 dmint::Rptie,
555 dmint::Rptie,
556 Dmint_SPEC,
557 crate::common::RW,
558 >::from_register(self, 0)
559 }
560
561 #[doc = "Source Address Extended Repeat Area Overflow Interrupt Enable"]
562 #[inline(always)]
563 pub fn sarie(
564 self,
565 ) -> crate::common::RegisterField<
566 1,
567 0x1,
568 1,
569 0,
570 dmint::Sarie,
571 dmint::Sarie,
572 Dmint_SPEC,
573 crate::common::RW,
574 > {
575 crate::common::RegisterField::<
576 1,
577 0x1,
578 1,
579 0,
580 dmint::Sarie,
581 dmint::Sarie,
582 Dmint_SPEC,
583 crate::common::RW,
584 >::from_register(self, 0)
585 }
586
587 #[doc = "Destination Address Extended Repeat Area Overflow Interrupt Enable"]
588 #[inline(always)]
589 pub fn darie(
590 self,
591 ) -> crate::common::RegisterField<
592 0,
593 0x1,
594 1,
595 0,
596 dmint::Darie,
597 dmint::Darie,
598 Dmint_SPEC,
599 crate::common::RW,
600 > {
601 crate::common::RegisterField::<
602 0,
603 0x1,
604 1,
605 0,
606 dmint::Darie,
607 dmint::Darie,
608 Dmint_SPEC,
609 crate::common::RW,
610 >::from_register(self, 0)
611 }
612}
613impl ::core::default::Default for Dmint {
614 #[inline(always)]
615 fn default() -> Dmint {
616 <crate::RegValueT<Dmint_SPEC> as RegisterValue<_>>::new(0)
617 }
618}
619pub mod dmint {
620
621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
622 pub struct Dtie_SPEC;
623 pub type Dtie = crate::EnumBitfieldStruct<u8, Dtie_SPEC>;
624 impl Dtie {
625 #[doc = "Disable"]
626 pub const _0: Self = Self::new(0);
627
628 #[doc = "Enable."]
629 pub const _1: Self = Self::new(1);
630 }
631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
632 pub struct Esie_SPEC;
633 pub type Esie = crate::EnumBitfieldStruct<u8, Esie_SPEC>;
634 impl Esie {
635 #[doc = "Disable"]
636 pub const _0: Self = Self::new(0);
637
638 #[doc = "Enable."]
639 pub const _1: Self = Self::new(1);
640 }
641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
642 pub struct Rptie_SPEC;
643 pub type Rptie = crate::EnumBitfieldStruct<u8, Rptie_SPEC>;
644 impl Rptie {
645 #[doc = "Disable"]
646 pub const _0: Self = Self::new(0);
647
648 #[doc = "Enable."]
649 pub const _1: Self = Self::new(1);
650 }
651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
652 pub struct Sarie_SPEC;
653 pub type Sarie = crate::EnumBitfieldStruct<u8, Sarie_SPEC>;
654 impl Sarie {
655 #[doc = "Disable"]
656 pub const _0: Self = Self::new(0);
657
658 #[doc = "Enable."]
659 pub const _1: Self = Self::new(1);
660 }
661 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
662 pub struct Darie_SPEC;
663 pub type Darie = crate::EnumBitfieldStruct<u8, Darie_SPEC>;
664 impl Darie {
665 #[doc = "Disable"]
666 pub const _0: Self = Self::new(0);
667
668 #[doc = "Enable."]
669 pub const _1: Self = Self::new(1);
670 }
671}
672#[doc(hidden)]
673#[derive(Copy, Clone, Eq, PartialEq)]
674pub struct Dmamd_SPEC;
675impl crate::sealed::RegSpec for Dmamd_SPEC {
676 type DataType = u16;
677}
678
679#[doc = "DMA Address Mode Register"]
680pub type Dmamd = crate::RegValueT<Dmamd_SPEC>;
681
682impl Dmamd {
683 #[doc = "Source Address Update Mode"]
684 #[inline(always)]
685 pub fn sm(
686 self,
687 ) -> crate::common::RegisterField<
688 14,
689 0x3,
690 1,
691 0,
692 dmamd::Sm,
693 dmamd::Sm,
694 Dmamd_SPEC,
695 crate::common::RW,
696 > {
697 crate::common::RegisterField::<
698 14,
699 0x3,
700 1,
701 0,
702 dmamd::Sm,
703 dmamd::Sm,
704 Dmamd_SPEC,
705 crate::common::RW,
706 >::from_register(self, 0)
707 }
708
709 #[doc = "Source Address Extended Repeat Area Specifies the extended repeat area on the source address. For details on the settings."]
710 #[inline(always)]
711 pub fn sara(
712 self,
713 ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, Dmamd_SPEC, crate::common::RW> {
714 crate::common::RegisterField::<8,0x1f,1,0,u8,u8,Dmamd_SPEC,crate::common::RW>::from_register(self,0)
715 }
716
717 #[doc = "Destination Address Update Mode"]
718 #[inline(always)]
719 pub fn dm(
720 self,
721 ) -> crate::common::RegisterField<
722 6,
723 0x3,
724 1,
725 0,
726 dmamd::Dm,
727 dmamd::Dm,
728 Dmamd_SPEC,
729 crate::common::RW,
730 > {
731 crate::common::RegisterField::<
732 6,
733 0x3,
734 1,
735 0,
736 dmamd::Dm,
737 dmamd::Dm,
738 Dmamd_SPEC,
739 crate::common::RW,
740 >::from_register(self, 0)
741 }
742
743 #[doc = "Destination Address Extended Repeat Area Specifies the extended repeat area on the destination address. For details on the settings."]
744 #[inline(always)]
745 pub fn dara(
746 self,
747 ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Dmamd_SPEC, crate::common::RW> {
748 crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Dmamd_SPEC,crate::common::RW>::from_register(self,0)
749 }
750}
751impl ::core::default::Default for Dmamd {
752 #[inline(always)]
753 fn default() -> Dmamd {
754 <crate::RegValueT<Dmamd_SPEC> as RegisterValue<_>>::new(0)
755 }
756}
757pub mod dmamd {
758
759 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
760 pub struct Sm_SPEC;
761 pub type Sm = crate::EnumBitfieldStruct<u8, Sm_SPEC>;
762 impl Sm {
763 #[doc = "Fixed address"]
764 pub const _00: Self = Self::new(0);
765
766 #[doc = "Offset addition"]
767 pub const _01: Self = Self::new(1);
768
769 #[doc = "Incremented address"]
770 pub const _10: Self = Self::new(2);
771
772 #[doc = "Decremented address."]
773 pub const _11: Self = Self::new(3);
774 }
775 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
776 pub struct Dm_SPEC;
777 pub type Dm = crate::EnumBitfieldStruct<u8, Dm_SPEC>;
778 impl Dm {
779 #[doc = "Fixed address"]
780 pub const _00: Self = Self::new(0);
781
782 #[doc = "Offset addition"]
783 pub const _01: Self = Self::new(1);
784
785 #[doc = "Incremented address"]
786 pub const _10: Self = Self::new(2);
787
788 #[doc = "Decremented address."]
789 pub const _11: Self = Self::new(3);
790 }
791}
792#[doc(hidden)]
793#[derive(Copy, Clone, Eq, PartialEq)]
794pub struct Dmofr_SPEC;
795impl crate::sealed::RegSpec for Dmofr_SPEC {
796 type DataType = u32;
797}
798
799#[doc = "DMA Offset Register"]
800pub type Dmofr = crate::RegValueT<Dmofr_SPEC>;
801
802impl Dmofr {
803 #[doc = "Specifies the offset when offset addition is selected as the address update mode for transfer source or destination."]
804 #[inline(always)]
805 pub fn dmofr(
806 self,
807 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Dmofr_SPEC, crate::common::RW>
808 {
809 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Dmofr_SPEC,crate::common::RW>::from_register(self,0)
810 }
811}
812impl ::core::default::Default for Dmofr {
813 #[inline(always)]
814 fn default() -> Dmofr {
815 <crate::RegValueT<Dmofr_SPEC> as RegisterValue<_>>::new(0)
816 }
817}
818
819#[doc(hidden)]
820#[derive(Copy, Clone, Eq, PartialEq)]
821pub struct Dmcnt_SPEC;
822impl crate::sealed::RegSpec for Dmcnt_SPEC {
823 type DataType = u8;
824}
825
826#[doc = "DMA Transfer Enable Register"]
827pub type Dmcnt = crate::RegValueT<Dmcnt_SPEC>;
828
829impl Dmcnt {
830 #[doc = "DMA Transfer Enable"]
831 #[inline(always)]
832 pub fn dte(
833 self,
834 ) -> crate::common::RegisterField<
835 0,
836 0x1,
837 1,
838 0,
839 dmcnt::Dte,
840 dmcnt::Dte,
841 Dmcnt_SPEC,
842 crate::common::RW,
843 > {
844 crate::common::RegisterField::<
845 0,
846 0x1,
847 1,
848 0,
849 dmcnt::Dte,
850 dmcnt::Dte,
851 Dmcnt_SPEC,
852 crate::common::RW,
853 >::from_register(self, 0)
854 }
855}
856impl ::core::default::Default for Dmcnt {
857 #[inline(always)]
858 fn default() -> Dmcnt {
859 <crate::RegValueT<Dmcnt_SPEC> as RegisterValue<_>>::new(0)
860 }
861}
862pub mod dmcnt {
863
864 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
865 pub struct Dte_SPEC;
866 pub type Dte = crate::EnumBitfieldStruct<u8, Dte_SPEC>;
867 impl Dte {
868 #[doc = "Disable"]
869 pub const _0: Self = Self::new(0);
870
871 #[doc = "Enable"]
872 pub const _1: Self = Self::new(1);
873 }
874}
875#[doc(hidden)]
876#[derive(Copy, Clone, Eq, PartialEq)]
877pub struct Dmreq_SPEC;
878impl crate::sealed::RegSpec for Dmreq_SPEC {
879 type DataType = u8;
880}
881
882#[doc = "DMA Software Start Register"]
883pub type Dmreq = crate::RegValueT<Dmreq_SPEC>;
884
885impl Dmreq {
886 #[doc = "DMA Software Start Bit Auto Clear Select"]
887 #[inline(always)]
888 pub fn clrs(
889 self,
890 ) -> crate::common::RegisterField<
891 4,
892 0x1,
893 1,
894 0,
895 dmreq::Clrs,
896 dmreq::Clrs,
897 Dmreq_SPEC,
898 crate::common::RW,
899 > {
900 crate::common::RegisterField::<
901 4,
902 0x1,
903 1,
904 0,
905 dmreq::Clrs,
906 dmreq::Clrs,
907 Dmreq_SPEC,
908 crate::common::RW,
909 >::from_register(self, 0)
910 }
911
912 #[doc = "DMA Software Start"]
913 #[inline(always)]
914 pub fn swreq(
915 self,
916 ) -> crate::common::RegisterField<
917 0,
918 0x1,
919 1,
920 0,
921 dmreq::Swreq,
922 dmreq::Swreq,
923 Dmreq_SPEC,
924 crate::common::RW,
925 > {
926 crate::common::RegisterField::<
927 0,
928 0x1,
929 1,
930 0,
931 dmreq::Swreq,
932 dmreq::Swreq,
933 Dmreq_SPEC,
934 crate::common::RW,
935 >::from_register(self, 0)
936 }
937}
938impl ::core::default::Default for Dmreq {
939 #[inline(always)]
940 fn default() -> Dmreq {
941 <crate::RegValueT<Dmreq_SPEC> as RegisterValue<_>>::new(0)
942 }
943}
944pub mod dmreq {
945
946 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
947 pub struct Clrs_SPEC;
948 pub type Clrs = crate::EnumBitfieldStruct<u8, Clrs_SPEC>;
949 impl Clrs {
950 #[doc = "Clear SWREQ bit after DMA transfer is started by software"]
951 pub const _0: Self = Self::new(0);
952
953 #[doc = "Do not clear SWREQ bit after DMA transfer is started by software"]
954 pub const _1: Self = Self::new(1);
955 }
956 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
957 pub struct Swreq_SPEC;
958 pub type Swreq = crate::EnumBitfieldStruct<u8, Swreq_SPEC>;
959 impl Swreq {
960 #[doc = "Do not request DMA transfer"]
961 pub const _0: Self = Self::new(0);
962
963 #[doc = "Request DMA transfer."]
964 pub const _1: Self = Self::new(1);
965 }
966}
967#[doc(hidden)]
968#[derive(Copy, Clone, Eq, PartialEq)]
969pub struct Dmsts_SPEC;
970impl crate::sealed::RegSpec for Dmsts_SPEC {
971 type DataType = u8;
972}
973
974#[doc = "DMAC Module Activation Register"]
975pub type Dmsts = crate::RegValueT<Dmsts_SPEC>;
976
977impl Dmsts {
978 #[doc = "DMA Active Flag"]
979 #[inline(always)]
980 pub fn act(
981 self,
982 ) -> crate::common::RegisterField<
983 7,
984 0x1,
985 1,
986 0,
987 dmsts::Act,
988 dmsts::Act,
989 Dmsts_SPEC,
990 crate::common::R,
991 > {
992 crate::common::RegisterField::<
993 7,
994 0x1,
995 1,
996 0,
997 dmsts::Act,
998 dmsts::Act,
999 Dmsts_SPEC,
1000 crate::common::R,
1001 >::from_register(self, 0)
1002 }
1003
1004 #[doc = "Transfer End Interrupt Flag"]
1005 #[inline(always)]
1006 pub fn dtif(
1007 self,
1008 ) -> crate::common::RegisterField<
1009 4,
1010 0x1,
1011 1,
1012 0,
1013 dmsts::Dtif,
1014 dmsts::Dtif,
1015 Dmsts_SPEC,
1016 crate::common::RW,
1017 > {
1018 crate::common::RegisterField::<
1019 4,
1020 0x1,
1021 1,
1022 0,
1023 dmsts::Dtif,
1024 dmsts::Dtif,
1025 Dmsts_SPEC,
1026 crate::common::RW,
1027 >::from_register(self, 0)
1028 }
1029
1030 #[doc = "Transfer Escape End Interrupt Flag"]
1031 #[inline(always)]
1032 pub fn esif(
1033 self,
1034 ) -> crate::common::RegisterField<
1035 0,
1036 0x1,
1037 1,
1038 0,
1039 dmsts::Esif,
1040 dmsts::Esif,
1041 Dmsts_SPEC,
1042 crate::common::RW,
1043 > {
1044 crate::common::RegisterField::<
1045 0,
1046 0x1,
1047 1,
1048 0,
1049 dmsts::Esif,
1050 dmsts::Esif,
1051 Dmsts_SPEC,
1052 crate::common::RW,
1053 >::from_register(self, 0)
1054 }
1055}
1056impl ::core::default::Default for Dmsts {
1057 #[inline(always)]
1058 fn default() -> Dmsts {
1059 <crate::RegValueT<Dmsts_SPEC> as RegisterValue<_>>::new(0)
1060 }
1061}
1062pub mod dmsts {
1063
1064 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1065 pub struct Act_SPEC;
1066 pub type Act = crate::EnumBitfieldStruct<u8, Act_SPEC>;
1067 impl Act {
1068 #[doc = "DMAC operation is suspended."]
1069 pub const _0: Self = Self::new(0);
1070
1071 #[doc = "DMAC is operating."]
1072 pub const _1: Self = Self::new(1);
1073 }
1074 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1075 pub struct Dtif_SPEC;
1076 pub type Dtif = crate::EnumBitfieldStruct<u8, Dtif_SPEC>;
1077 impl Dtif {
1078 #[doc = "No interrupt occurred"]
1079 pub const _0: Self = Self::new(0);
1080
1081 #[doc = "Interrupt occurred."]
1082 pub const _1: Self = Self::new(1);
1083 }
1084 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1085 pub struct Esif_SPEC;
1086 pub type Esif = crate::EnumBitfieldStruct<u8, Esif_SPEC>;
1087 impl Esif {
1088 #[doc = "A transfer escape end interrupt has not been generated."]
1089 pub const _0: Self = Self::new(0);
1090
1091 #[doc = "A transfer escape end interrupt has been generated."]
1092 pub const _1: Self = Self::new(1);
1093 }
1094}