1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Peripheral Interface 0"]
28unsafe impl ::core::marker::Send for super::Spi0 {}
29unsafe impl ::core::marker::Sync for super::Spi0 {}
30impl super::Spi0 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "SPI Control Register"]
38 #[inline(always)]
39 pub const fn spcr(&self) -> &'static crate::common::Reg<self::Spcr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Spcr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "SPI Slave Select Polarity Register"]
48 #[inline(always)]
49 pub const fn sslp(&self) -> &'static crate::common::Reg<self::Sslp_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Sslp_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(1usize),
53 )
54 }
55 }
56
57 #[doc = "RSPI Pin Control Register"]
58 #[inline(always)]
59 pub const fn sppcr(&self) -> &'static crate::common::Reg<self::Sppcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Sppcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(2usize),
63 )
64 }
65 }
66
67 #[doc = "SPI Status Register"]
68 #[inline(always)]
69 pub const fn spsr(&self) -> &'static crate::common::Reg<self::Spsr_SPEC, crate::common::RW> {
70 unsafe {
71 crate::common::Reg::<self::Spsr_SPEC, crate::common::RW>::from_ptr(
72 self._svd2pac_as_ptr().add(3usize),
73 )
74 }
75 }
76
77 #[doc = "SPI Data Register"]
78 #[inline(always)]
79 pub const fn spdr(&self) -> &'static crate::common::Reg<self::Spdr_SPEC, crate::common::RW> {
80 unsafe {
81 crate::common::Reg::<self::Spdr_SPEC, crate::common::RW>::from_ptr(
82 self._svd2pac_as_ptr().add(4usize),
83 )
84 }
85 }
86
87 #[doc = "SPI Data Register ( halfword access )"]
88 #[inline(always)]
89 pub const fn spdr_ha(
90 &self,
91 ) -> &'static crate::common::Reg<self::SpdrHa_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::SpdrHa_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(4usize),
95 )
96 }
97 }
98
99 #[doc = "SPI Sequence Control Register"]
100 #[inline(always)]
101 pub const fn spscr(&self) -> &'static crate::common::Reg<self::Spscr_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::Spscr_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(8usize),
105 )
106 }
107 }
108
109 #[doc = "SPI Sequence Status Register"]
110 #[inline(always)]
111 pub const fn spssr(&self) -> &'static crate::common::Reg<self::Spssr_SPEC, crate::common::R> {
112 unsafe {
113 crate::common::Reg::<self::Spssr_SPEC, crate::common::R>::from_ptr(
114 self._svd2pac_as_ptr().add(9usize),
115 )
116 }
117 }
118
119 #[doc = "SPI Bit Rate Register"]
120 #[inline(always)]
121 pub const fn spbr(&self) -> &'static crate::common::Reg<self::Spbr_SPEC, crate::common::RW> {
122 unsafe {
123 crate::common::Reg::<self::Spbr_SPEC, crate::common::RW>::from_ptr(
124 self._svd2pac_as_ptr().add(10usize),
125 )
126 }
127 }
128
129 #[doc = "SPI Data Control Register"]
130 #[inline(always)]
131 pub const fn spdcr(&self) -> &'static crate::common::Reg<self::Spdcr_SPEC, crate::common::RW> {
132 unsafe {
133 crate::common::Reg::<self::Spdcr_SPEC, crate::common::RW>::from_ptr(
134 self._svd2pac_as_ptr().add(11usize),
135 )
136 }
137 }
138
139 #[doc = "SPI Clock Delay Register"]
140 #[inline(always)]
141 pub const fn spckd(&self) -> &'static crate::common::Reg<self::Spckd_SPEC, crate::common::RW> {
142 unsafe {
143 crate::common::Reg::<self::Spckd_SPEC, crate::common::RW>::from_ptr(
144 self._svd2pac_as_ptr().add(12usize),
145 )
146 }
147 }
148
149 #[doc = "SPI Slave Select Negation Delay Register"]
150 #[inline(always)]
151 pub const fn sslnd(&self) -> &'static crate::common::Reg<self::Sslnd_SPEC, crate::common::RW> {
152 unsafe {
153 crate::common::Reg::<self::Sslnd_SPEC, crate::common::RW>::from_ptr(
154 self._svd2pac_as_ptr().add(13usize),
155 )
156 }
157 }
158
159 #[doc = "SPI Next-Access Delay Register"]
160 #[inline(always)]
161 pub const fn spnd(&self) -> &'static crate::common::Reg<self::Spnd_SPEC, crate::common::RW> {
162 unsafe {
163 crate::common::Reg::<self::Spnd_SPEC, crate::common::RW>::from_ptr(
164 self._svd2pac_as_ptr().add(14usize),
165 )
166 }
167 }
168
169 #[doc = "SPI Control Register 2"]
170 #[inline(always)]
171 pub const fn spcr2(&self) -> &'static crate::common::Reg<self::Spcr2_SPEC, crate::common::RW> {
172 unsafe {
173 crate::common::Reg::<self::Spcr2_SPEC, crate::common::RW>::from_ptr(
174 self._svd2pac_as_ptr().add(15usize),
175 )
176 }
177 }
178
179 #[doc = "SPI Command Register %s"]
180 #[inline(always)]
181 pub const fn spcmd(
182 &self,
183 ) -> &'static crate::common::ClusterRegisterArray<
184 crate::common::Reg<self::Spcmd_SPEC, crate::common::RW>,
185 8,
186 0x2,
187 > {
188 unsafe {
189 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x10usize))
190 }
191 }
192 #[inline(always)]
193 pub const fn spcmd0(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
194 unsafe {
195 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
196 self._svd2pac_as_ptr().add(0x10usize),
197 )
198 }
199 }
200 #[inline(always)]
201 pub const fn spcmd1(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(0x12usize),
205 )
206 }
207 }
208 #[inline(always)]
209 pub const fn spcmd2(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
210 unsafe {
211 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
212 self._svd2pac_as_ptr().add(0x14usize),
213 )
214 }
215 }
216 #[inline(always)]
217 pub const fn spcmd3(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
218 unsafe {
219 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
220 self._svd2pac_as_ptr().add(0x16usize),
221 )
222 }
223 }
224 #[inline(always)]
225 pub const fn spcmd4(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
226 unsafe {
227 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
228 self._svd2pac_as_ptr().add(0x18usize),
229 )
230 }
231 }
232 #[inline(always)]
233 pub const fn spcmd5(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(0x1ausize),
237 )
238 }
239 }
240 #[inline(always)]
241 pub const fn spcmd6(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
242 unsafe {
243 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
244 self._svd2pac_as_ptr().add(0x1cusize),
245 )
246 }
247 }
248 #[inline(always)]
249 pub const fn spcmd7(&self) -> &'static crate::common::Reg<self::Spcmd_SPEC, crate::common::RW> {
250 unsafe {
251 crate::common::Reg::<self::Spcmd_SPEC, crate::common::RW>::from_ptr(
252 self._svd2pac_as_ptr().add(0x1eusize),
253 )
254 }
255 }
256
257 #[doc = "SPI Data Control Register 2"]
258 #[inline(always)]
259 pub const fn spdcr2(
260 &self,
261 ) -> &'static crate::common::Reg<self::Spdcr2_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Spdcr2_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(32usize),
265 )
266 }
267 }
268}
269#[doc(hidden)]
270#[derive(Copy, Clone, Eq, PartialEq)]
271pub struct Spcr_SPEC;
272impl crate::sealed::RegSpec for Spcr_SPEC {
273 type DataType = u8;
274}
275
276#[doc = "SPI Control Register"]
277pub type Spcr = crate::RegValueT<Spcr_SPEC>;
278
279impl Spcr {
280 #[doc = "SPI Receive Buffer Full Interrupt Enable"]
281 #[inline(always)]
282 pub fn sprie(
283 self,
284 ) -> crate::common::RegisterField<
285 7,
286 0x1,
287 1,
288 0,
289 spcr::Sprie,
290 spcr::Sprie,
291 Spcr_SPEC,
292 crate::common::RW,
293 > {
294 crate::common::RegisterField::<
295 7,
296 0x1,
297 1,
298 0,
299 spcr::Sprie,
300 spcr::Sprie,
301 Spcr_SPEC,
302 crate::common::RW,
303 >::from_register(self, 0)
304 }
305
306 #[doc = "SPI Function Enable"]
307 #[inline(always)]
308 pub fn spe(
309 self,
310 ) -> crate::common::RegisterField<
311 6,
312 0x1,
313 1,
314 0,
315 spcr::Spe,
316 spcr::Spe,
317 Spcr_SPEC,
318 crate::common::RW,
319 > {
320 crate::common::RegisterField::<
321 6,
322 0x1,
323 1,
324 0,
325 spcr::Spe,
326 spcr::Spe,
327 Spcr_SPEC,
328 crate::common::RW,
329 >::from_register(self, 0)
330 }
331
332 #[doc = "Transmit Buffer Empty Interrupt Enable"]
333 #[inline(always)]
334 pub fn sptie(
335 self,
336 ) -> crate::common::RegisterField<
337 5,
338 0x1,
339 1,
340 0,
341 spcr::Sptie,
342 spcr::Sptie,
343 Spcr_SPEC,
344 crate::common::RW,
345 > {
346 crate::common::RegisterField::<
347 5,
348 0x1,
349 1,
350 0,
351 spcr::Sptie,
352 spcr::Sptie,
353 Spcr_SPEC,
354 crate::common::RW,
355 >::from_register(self, 0)
356 }
357
358 #[doc = "SPI Error Interrupt Enable"]
359 #[inline(always)]
360 pub fn speie(
361 self,
362 ) -> crate::common::RegisterField<
363 4,
364 0x1,
365 1,
366 0,
367 spcr::Speie,
368 spcr::Speie,
369 Spcr_SPEC,
370 crate::common::RW,
371 > {
372 crate::common::RegisterField::<
373 4,
374 0x1,
375 1,
376 0,
377 spcr::Speie,
378 spcr::Speie,
379 Spcr_SPEC,
380 crate::common::RW,
381 >::from_register(self, 0)
382 }
383
384 #[doc = "SPI Master/Slave Mode Select"]
385 #[inline(always)]
386 pub fn mstr(
387 self,
388 ) -> crate::common::RegisterField<
389 3,
390 0x1,
391 1,
392 0,
393 spcr::Mstr,
394 spcr::Mstr,
395 Spcr_SPEC,
396 crate::common::RW,
397 > {
398 crate::common::RegisterField::<
399 3,
400 0x1,
401 1,
402 0,
403 spcr::Mstr,
404 spcr::Mstr,
405 Spcr_SPEC,
406 crate::common::RW,
407 >::from_register(self, 0)
408 }
409
410 #[doc = "Mode Fault Error Detection Enable"]
411 #[inline(always)]
412 pub fn modfen(
413 self,
414 ) -> crate::common::RegisterField<
415 2,
416 0x1,
417 1,
418 0,
419 spcr::Modfen,
420 spcr::Modfen,
421 Spcr_SPEC,
422 crate::common::RW,
423 > {
424 crate::common::RegisterField::<
425 2,
426 0x1,
427 1,
428 0,
429 spcr::Modfen,
430 spcr::Modfen,
431 Spcr_SPEC,
432 crate::common::RW,
433 >::from_register(self, 0)
434 }
435
436 #[doc = "Communications Operating Mode Select"]
437 #[inline(always)]
438 pub fn txmd(
439 self,
440 ) -> crate::common::RegisterField<
441 1,
442 0x1,
443 1,
444 0,
445 spcr::Txmd,
446 spcr::Txmd,
447 Spcr_SPEC,
448 crate::common::RW,
449 > {
450 crate::common::RegisterField::<
451 1,
452 0x1,
453 1,
454 0,
455 spcr::Txmd,
456 spcr::Txmd,
457 Spcr_SPEC,
458 crate::common::RW,
459 >::from_register(self, 0)
460 }
461
462 #[doc = "SPI Mode Select"]
463 #[inline(always)]
464 pub fn spms(
465 self,
466 ) -> crate::common::RegisterField<
467 0,
468 0x1,
469 1,
470 0,
471 spcr::Spms,
472 spcr::Spms,
473 Spcr_SPEC,
474 crate::common::RW,
475 > {
476 crate::common::RegisterField::<
477 0,
478 0x1,
479 1,
480 0,
481 spcr::Spms,
482 spcr::Spms,
483 Spcr_SPEC,
484 crate::common::RW,
485 >::from_register(self, 0)
486 }
487}
488impl ::core::default::Default for Spcr {
489 #[inline(always)]
490 fn default() -> Spcr {
491 <crate::RegValueT<Spcr_SPEC> as RegisterValue<_>>::new(0)
492 }
493}
494pub mod spcr {
495
496 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
497 pub struct Sprie_SPEC;
498 pub type Sprie = crate::EnumBitfieldStruct<u8, Sprie_SPEC>;
499 impl Sprie {
500 #[doc = "Disables the generation of SPI receive buffer full interrupt requests"]
501 pub const _0: Self = Self::new(0);
502
503 #[doc = "Enables the generation of SPI receive buffer full interrupt requests"]
504 pub const _1: Self = Self::new(1);
505 }
506 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
507 pub struct Spe_SPEC;
508 pub type Spe = crate::EnumBitfieldStruct<u8, Spe_SPEC>;
509 impl Spe {
510 #[doc = "Disables the SPI function"]
511 pub const _0: Self = Self::new(0);
512
513 #[doc = "Enables the SPI function"]
514 pub const _1: Self = Self::new(1);
515 }
516 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
517 pub struct Sptie_SPEC;
518 pub type Sptie = crate::EnumBitfieldStruct<u8, Sptie_SPEC>;
519 impl Sptie {
520 #[doc = "Disables the generation of transmit buffer empty interrupt requests"]
521 pub const _0: Self = Self::new(0);
522
523 #[doc = "Enables the generation of transmit buffer empty interrupt requests"]
524 pub const _1: Self = Self::new(1);
525 }
526 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
527 pub struct Speie_SPEC;
528 pub type Speie = crate::EnumBitfieldStruct<u8, Speie_SPEC>;
529 impl Speie {
530 #[doc = "Disables the generation of SPI error interrupt requests"]
531 pub const _0: Self = Self::new(0);
532
533 #[doc = "Enables the generation of SPI error interrupt requests"]
534 pub const _1: Self = Self::new(1);
535 }
536 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
537 pub struct Mstr_SPEC;
538 pub type Mstr = crate::EnumBitfieldStruct<u8, Mstr_SPEC>;
539 impl Mstr {
540 #[doc = "Slave mode"]
541 pub const _0: Self = Self::new(0);
542
543 #[doc = "Master mode"]
544 pub const _1: Self = Self::new(1);
545 }
546 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
547 pub struct Modfen_SPEC;
548 pub type Modfen = crate::EnumBitfieldStruct<u8, Modfen_SPEC>;
549 impl Modfen {
550 #[doc = "Disables the detection of mode fault error"]
551 pub const _0: Self = Self::new(0);
552
553 #[doc = "Enables the detection of mode fault error"]
554 pub const _1: Self = Self::new(1);
555 }
556 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
557 pub struct Txmd_SPEC;
558 pub type Txmd = crate::EnumBitfieldStruct<u8, Txmd_SPEC>;
559 impl Txmd {
560 #[doc = "Full-duplex synchronous serial communications"]
561 pub const _0: Self = Self::new(0);
562
563 #[doc = "Serial communications consisting of only transmit operations"]
564 pub const _1: Self = Self::new(1);
565 }
566 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
567 pub struct Spms_SPEC;
568 pub type Spms = crate::EnumBitfieldStruct<u8, Spms_SPEC>;
569 impl Spms {
570 #[doc = "SPI operation (4-wire method)"]
571 pub const _0: Self = Self::new(0);
572
573 #[doc = "Clock synchronous operation (3-wire method)"]
574 pub const _1: Self = Self::new(1);
575 }
576}
577#[doc(hidden)]
578#[derive(Copy, Clone, Eq, PartialEq)]
579pub struct Sslp_SPEC;
580impl crate::sealed::RegSpec for Sslp_SPEC {
581 type DataType = u8;
582}
583
584#[doc = "SPI Slave Select Polarity Register"]
585pub type Sslp = crate::RegValueT<Sslp_SPEC>;
586
587impl Sslp {
588 #[doc = "SSL3 Signal Polarity Setting"]
589 #[inline(always)]
590 pub fn ssl3p(
591 self,
592 ) -> crate::common::RegisterField<
593 3,
594 0x1,
595 1,
596 0,
597 sslp::Ssl3P,
598 sslp::Ssl3P,
599 Sslp_SPEC,
600 crate::common::RW,
601 > {
602 crate::common::RegisterField::<
603 3,
604 0x1,
605 1,
606 0,
607 sslp::Ssl3P,
608 sslp::Ssl3P,
609 Sslp_SPEC,
610 crate::common::RW,
611 >::from_register(self, 0)
612 }
613
614 #[doc = "SSL2 Signal Polarity Setting"]
615 #[inline(always)]
616 pub fn ssl2p(
617 self,
618 ) -> crate::common::RegisterField<
619 2,
620 0x1,
621 1,
622 0,
623 sslp::Ssl2P,
624 sslp::Ssl2P,
625 Sslp_SPEC,
626 crate::common::RW,
627 > {
628 crate::common::RegisterField::<
629 2,
630 0x1,
631 1,
632 0,
633 sslp::Ssl2P,
634 sslp::Ssl2P,
635 Sslp_SPEC,
636 crate::common::RW,
637 >::from_register(self, 0)
638 }
639
640 #[doc = "SSL1 Signal Polarity Setting"]
641 #[inline(always)]
642 pub fn ssl1p(
643 self,
644 ) -> crate::common::RegisterField<
645 1,
646 0x1,
647 1,
648 0,
649 sslp::Ssl1P,
650 sslp::Ssl1P,
651 Sslp_SPEC,
652 crate::common::RW,
653 > {
654 crate::common::RegisterField::<
655 1,
656 0x1,
657 1,
658 0,
659 sslp::Ssl1P,
660 sslp::Ssl1P,
661 Sslp_SPEC,
662 crate::common::RW,
663 >::from_register(self, 0)
664 }
665
666 #[doc = "SSL0 Signal Polarity Setting"]
667 #[inline(always)]
668 pub fn ssl0p(
669 self,
670 ) -> crate::common::RegisterField<
671 0,
672 0x1,
673 1,
674 0,
675 sslp::Ssl0P,
676 sslp::Ssl0P,
677 Sslp_SPEC,
678 crate::common::RW,
679 > {
680 crate::common::RegisterField::<
681 0,
682 0x1,
683 1,
684 0,
685 sslp::Ssl0P,
686 sslp::Ssl0P,
687 Sslp_SPEC,
688 crate::common::RW,
689 >::from_register(self, 0)
690 }
691}
692impl ::core::default::Default for Sslp {
693 #[inline(always)]
694 fn default() -> Sslp {
695 <crate::RegValueT<Sslp_SPEC> as RegisterValue<_>>::new(0)
696 }
697}
698pub mod sslp {
699
700 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
701 pub struct Ssl3P_SPEC;
702 pub type Ssl3P = crate::EnumBitfieldStruct<u8, Ssl3P_SPEC>;
703 impl Ssl3P {
704 #[doc = "SSL3 signal is active low"]
705 pub const _0: Self = Self::new(0);
706
707 #[doc = "SSL3 signal is active high"]
708 pub const _1: Self = Self::new(1);
709 }
710 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
711 pub struct Ssl2P_SPEC;
712 pub type Ssl2P = crate::EnumBitfieldStruct<u8, Ssl2P_SPEC>;
713 impl Ssl2P {
714 #[doc = "SSL2 signal is active low"]
715 pub const _0: Self = Self::new(0);
716
717 #[doc = "SSL2 signal is active high"]
718 pub const _1: Self = Self::new(1);
719 }
720 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
721 pub struct Ssl1P_SPEC;
722 pub type Ssl1P = crate::EnumBitfieldStruct<u8, Ssl1P_SPEC>;
723 impl Ssl1P {
724 #[doc = "SSL1 signal is active low"]
725 pub const _0: Self = Self::new(0);
726
727 #[doc = "SSL1 signal is active high"]
728 pub const _1: Self = Self::new(1);
729 }
730 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
731 pub struct Ssl0P_SPEC;
732 pub type Ssl0P = crate::EnumBitfieldStruct<u8, Ssl0P_SPEC>;
733 impl Ssl0P {
734 #[doc = "SSL0 signal is active low"]
735 pub const _0: Self = Self::new(0);
736
737 #[doc = "SSL0 signal is active high"]
738 pub const _1: Self = Self::new(1);
739 }
740}
741#[doc(hidden)]
742#[derive(Copy, Clone, Eq, PartialEq)]
743pub struct Sppcr_SPEC;
744impl crate::sealed::RegSpec for Sppcr_SPEC {
745 type DataType = u8;
746}
747
748#[doc = "RSPI Pin Control Register"]
749pub type Sppcr = crate::RegValueT<Sppcr_SPEC>;
750
751impl Sppcr {
752 #[doc = "MOSI Idle Value Fixing Enable"]
753 #[inline(always)]
754 pub fn moife(
755 self,
756 ) -> crate::common::RegisterField<
757 5,
758 0x1,
759 1,
760 0,
761 sppcr::Moife,
762 sppcr::Moife,
763 Sppcr_SPEC,
764 crate::common::RW,
765 > {
766 crate::common::RegisterField::<
767 5,
768 0x1,
769 1,
770 0,
771 sppcr::Moife,
772 sppcr::Moife,
773 Sppcr_SPEC,
774 crate::common::RW,
775 >::from_register(self, 0)
776 }
777
778 #[doc = "MOSI Idle Fixed Value"]
779 #[inline(always)]
780 pub fn moifv(
781 self,
782 ) -> crate::common::RegisterField<
783 4,
784 0x1,
785 1,
786 0,
787 sppcr::Moifv,
788 sppcr::Moifv,
789 Sppcr_SPEC,
790 crate::common::RW,
791 > {
792 crate::common::RegisterField::<
793 4,
794 0x1,
795 1,
796 0,
797 sppcr::Moifv,
798 sppcr::Moifv,
799 Sppcr_SPEC,
800 crate::common::RW,
801 >::from_register(self, 0)
802 }
803
804 #[doc = "RSPI Loopback 2"]
805 #[inline(always)]
806 pub fn splp2(
807 self,
808 ) -> crate::common::RegisterField<
809 1,
810 0x1,
811 1,
812 0,
813 sppcr::Splp2,
814 sppcr::Splp2,
815 Sppcr_SPEC,
816 crate::common::RW,
817 > {
818 crate::common::RegisterField::<
819 1,
820 0x1,
821 1,
822 0,
823 sppcr::Splp2,
824 sppcr::Splp2,
825 Sppcr_SPEC,
826 crate::common::RW,
827 >::from_register(self, 0)
828 }
829
830 #[doc = "RSPI Loopback"]
831 #[inline(always)]
832 pub fn splp(
833 self,
834 ) -> crate::common::RegisterField<
835 0,
836 0x1,
837 1,
838 0,
839 sppcr::Splp,
840 sppcr::Splp,
841 Sppcr_SPEC,
842 crate::common::RW,
843 > {
844 crate::common::RegisterField::<
845 0,
846 0x1,
847 1,
848 0,
849 sppcr::Splp,
850 sppcr::Splp,
851 Sppcr_SPEC,
852 crate::common::RW,
853 >::from_register(self, 0)
854 }
855}
856impl ::core::default::Default for Sppcr {
857 #[inline(always)]
858 fn default() -> Sppcr {
859 <crate::RegValueT<Sppcr_SPEC> as RegisterValue<_>>::new(0)
860 }
861}
862pub mod sppcr {
863
864 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
865 pub struct Moife_SPEC;
866 pub type Moife = crate::EnumBitfieldStruct<u8, Moife_SPEC>;
867 impl Moife {
868 #[doc = "MOSI output value equals final data from previous transfer"]
869 pub const _0: Self = Self::new(0);
870
871 #[doc = "MOSI output value equals the value set in the MOIFV bit"]
872 pub const _1: Self = Self::new(1);
873 }
874 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
875 pub struct Moifv_SPEC;
876 pub type Moifv = crate::EnumBitfieldStruct<u8, Moifv_SPEC>;
877 impl Moifv {
878 #[doc = "The level output on the MOSIn pin during MOSI idling corresponds to low."]
879 pub const _0: Self = Self::new(0);
880
881 #[doc = "The level output on the MOSIn pin during MOSI idling corresponds to high."]
882 pub const _1: Self = Self::new(1);
883 }
884 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
885 pub struct Splp2_SPEC;
886 pub type Splp2 = crate::EnumBitfieldStruct<u8, Splp2_SPEC>;
887 impl Splp2 {
888 #[doc = "Normal mode"]
889 pub const _0: Self = Self::new(0);
890
891 #[doc = "Loopback mode (data is not inverted for transmission)"]
892 pub const _1: Self = Self::new(1);
893 }
894 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
895 pub struct Splp_SPEC;
896 pub type Splp = crate::EnumBitfieldStruct<u8, Splp_SPEC>;
897 impl Splp {
898 #[doc = "Normal mode"]
899 pub const _0: Self = Self::new(0);
900
901 #[doc = "Loopback mode (data is inverted for transmission)"]
902 pub const _1: Self = Self::new(1);
903 }
904}
905#[doc(hidden)]
906#[derive(Copy, Clone, Eq, PartialEq)]
907pub struct Spsr_SPEC;
908impl crate::sealed::RegSpec for Spsr_SPEC {
909 type DataType = u8;
910}
911
912#[doc = "SPI Status Register"]
913pub type Spsr = crate::RegValueT<Spsr_SPEC>;
914
915impl Spsr {
916 #[doc = "SPI Receive Buffer Full Flag"]
917 #[inline(always)]
918 pub fn sprf(
919 self,
920 ) -> crate::common::RegisterField<
921 7,
922 0x1,
923 1,
924 0,
925 spsr::Sprf,
926 spsr::Sprf,
927 Spsr_SPEC,
928 crate::common::RW,
929 > {
930 crate::common::RegisterField::<
931 7,
932 0x1,
933 1,
934 0,
935 spsr::Sprf,
936 spsr::Sprf,
937 Spsr_SPEC,
938 crate::common::RW,
939 >::from_register(self, 0)
940 }
941
942 #[doc = "SPI Transmit Buffer Empty Flag"]
943 #[inline(always)]
944 pub fn sptef(
945 self,
946 ) -> crate::common::RegisterField<
947 5,
948 0x1,
949 1,
950 0,
951 spsr::Sptef,
952 spsr::Sptef,
953 Spsr_SPEC,
954 crate::common::RW,
955 > {
956 crate::common::RegisterField::<
957 5,
958 0x1,
959 1,
960 0,
961 spsr::Sptef,
962 spsr::Sptef,
963 Spsr_SPEC,
964 crate::common::RW,
965 >::from_register(self, 0)
966 }
967
968 #[doc = "Underrun Error Flag(When MODF is 0, This bit is invalid.)"]
969 #[inline(always)]
970 pub fn udrf(
971 self,
972 ) -> crate::common::RegisterField<
973 4,
974 0x1,
975 1,
976 0,
977 spsr::Udrf,
978 spsr::Udrf,
979 Spsr_SPEC,
980 crate::common::RW,
981 > {
982 crate::common::RegisterField::<
983 4,
984 0x1,
985 1,
986 0,
987 spsr::Udrf,
988 spsr::Udrf,
989 Spsr_SPEC,
990 crate::common::RW,
991 >::from_register(self, 0)
992 }
993
994 #[doc = "Parity Error Flag"]
995 #[inline(always)]
996 pub fn perf(
997 self,
998 ) -> crate::common::RegisterField<
999 3,
1000 0x1,
1001 1,
1002 0,
1003 spsr::Perf,
1004 spsr::Perf,
1005 Spsr_SPEC,
1006 crate::common::RW,
1007 > {
1008 crate::common::RegisterField::<
1009 3,
1010 0x1,
1011 1,
1012 0,
1013 spsr::Perf,
1014 spsr::Perf,
1015 Spsr_SPEC,
1016 crate::common::RW,
1017 >::from_register(self, 0)
1018 }
1019
1020 #[doc = "Mode Fault Error Flag"]
1021 #[inline(always)]
1022 pub fn modf(
1023 self,
1024 ) -> crate::common::RegisterField<
1025 2,
1026 0x1,
1027 1,
1028 0,
1029 spsr::Modf,
1030 spsr::Modf,
1031 Spsr_SPEC,
1032 crate::common::RW,
1033 > {
1034 crate::common::RegisterField::<
1035 2,
1036 0x1,
1037 1,
1038 0,
1039 spsr::Modf,
1040 spsr::Modf,
1041 Spsr_SPEC,
1042 crate::common::RW,
1043 >::from_register(self, 0)
1044 }
1045
1046 #[doc = "SPI Idle Flag"]
1047 #[inline(always)]
1048 pub fn idlnf(
1049 self,
1050 ) -> crate::common::RegisterField<
1051 1,
1052 0x1,
1053 1,
1054 0,
1055 spsr::Idlnf,
1056 spsr::Idlnf,
1057 Spsr_SPEC,
1058 crate::common::R,
1059 > {
1060 crate::common::RegisterField::<
1061 1,
1062 0x1,
1063 1,
1064 0,
1065 spsr::Idlnf,
1066 spsr::Idlnf,
1067 Spsr_SPEC,
1068 crate::common::R,
1069 >::from_register(self, 0)
1070 }
1071
1072 #[doc = "Overrun Error Flag"]
1073 #[inline(always)]
1074 pub fn ovrf(
1075 self,
1076 ) -> crate::common::RegisterField<
1077 0,
1078 0x1,
1079 1,
1080 0,
1081 spsr::Ovrf,
1082 spsr::Ovrf,
1083 Spsr_SPEC,
1084 crate::common::RW,
1085 > {
1086 crate::common::RegisterField::<
1087 0,
1088 0x1,
1089 1,
1090 0,
1091 spsr::Ovrf,
1092 spsr::Ovrf,
1093 Spsr_SPEC,
1094 crate::common::RW,
1095 >::from_register(self, 0)
1096 }
1097}
1098impl ::core::default::Default for Spsr {
1099 #[inline(always)]
1100 fn default() -> Spsr {
1101 <crate::RegValueT<Spsr_SPEC> as RegisterValue<_>>::new(32)
1102 }
1103}
1104pub mod spsr {
1105
1106 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1107 pub struct Sprf_SPEC;
1108 pub type Sprf = crate::EnumBitfieldStruct<u8, Sprf_SPEC>;
1109 impl Sprf {
1110 #[doc = "No valid data in SPDR"]
1111 pub const _0: Self = Self::new(0);
1112
1113 #[doc = "Valid data found in SPDR"]
1114 pub const _1: Self = Self::new(1);
1115 }
1116 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1117 pub struct Sptef_SPEC;
1118 pub type Sptef = crate::EnumBitfieldStruct<u8, Sptef_SPEC>;
1119 impl Sptef {
1120 #[doc = "Data found in the transmit buffer"]
1121 pub const _0: Self = Self::new(0);
1122
1123 #[doc = "No data in the transmit buffer"]
1124 pub const _1: Self = Self::new(1);
1125 }
1126 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1127 pub struct Udrf_SPEC;
1128 pub type Udrf = crate::EnumBitfieldStruct<u8, Udrf_SPEC>;
1129 impl Udrf {
1130 #[doc = "A mode fault error occurs (MODF=1)"]
1131 pub const _0: Self = Self::new(0);
1132
1133 #[doc = "An underrun error occurs (MODF=1)"]
1134 pub const _1: Self = Self::new(1);
1135 }
1136 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1137 pub struct Perf_SPEC;
1138 pub type Perf = crate::EnumBitfieldStruct<u8, Perf_SPEC>;
1139 impl Perf {
1140 #[doc = "No parity error occurs"]
1141 pub const _0: Self = Self::new(0);
1142
1143 #[doc = "A parity error occurs"]
1144 pub const _1: Self = Self::new(1);
1145 }
1146 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1147 pub struct Modf_SPEC;
1148 pub type Modf = crate::EnumBitfieldStruct<u8, Modf_SPEC>;
1149 impl Modf {
1150 #[doc = "Neither mode fault error nor underrun error occurs"]
1151 pub const _0: Self = Self::new(0);
1152
1153 #[doc = "A mode fault error or an underrun error occurs."]
1154 pub const _1: Self = Self::new(1);
1155 }
1156 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1157 pub struct Idlnf_SPEC;
1158 pub type Idlnf = crate::EnumBitfieldStruct<u8, Idlnf_SPEC>;
1159 impl Idlnf {
1160 #[doc = "SPI is in the idle state"]
1161 pub const _0: Self = Self::new(0);
1162
1163 #[doc = "SPI is in the transfer state"]
1164 pub const _1: Self = Self::new(1);
1165 }
1166 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1167 pub struct Ovrf_SPEC;
1168 pub type Ovrf = crate::EnumBitfieldStruct<u8, Ovrf_SPEC>;
1169 impl Ovrf {
1170 #[doc = "No overrun error occurs"]
1171 pub const _0: Self = Self::new(0);
1172
1173 #[doc = "An overrun error occurs"]
1174 pub const _1: Self = Self::new(1);
1175 }
1176}
1177#[doc(hidden)]
1178#[derive(Copy, Clone, Eq, PartialEq)]
1179pub struct Spdr_SPEC;
1180impl crate::sealed::RegSpec for Spdr_SPEC {
1181 type DataType = u32;
1182}
1183
1184#[doc = "SPI Data Register"]
1185pub type Spdr = crate::RegValueT<Spdr_SPEC>;
1186
1187impl Spdr {
1188 #[doc = "SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in word (SPDCR.SPLW=1), access SPDR."]
1189 #[inline(always)]
1190 pub fn spdr(
1191 self,
1192 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Spdr_SPEC, crate::common::RW>
1193 {
1194 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Spdr_SPEC,crate::common::RW>::from_register(self,0)
1195 }
1196}
1197impl ::core::default::Default for Spdr {
1198 #[inline(always)]
1199 fn default() -> Spdr {
1200 <crate::RegValueT<Spdr_SPEC> as RegisterValue<_>>::new(0)
1201 }
1202}
1203
1204#[doc(hidden)]
1205#[derive(Copy, Clone, Eq, PartialEq)]
1206pub struct SpdrHa_SPEC;
1207impl crate::sealed::RegSpec for SpdrHa_SPEC {
1208 type DataType = u16;
1209}
1210
1211#[doc = "SPI Data Register ( halfword access )"]
1212pub type SpdrHa = crate::RegValueT<SpdrHa_SPEC>;
1213
1214impl SpdrHa {
1215 #[doc = "SPDR is the interface with the buffers that hold data for transmission and reception by the RSPI.When accessing in halfword (SPDCR.SPLW=0), access SPDR_HA."]
1216 #[inline(always)]
1217 pub fn spdr_ha(
1218 self,
1219 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, SpdrHa_SPEC, crate::common::RW>
1220 {
1221 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,SpdrHa_SPEC,crate::common::RW>::from_register(self,0)
1222 }
1223}
1224impl ::core::default::Default for SpdrHa {
1225 #[inline(always)]
1226 fn default() -> SpdrHa {
1227 <crate::RegValueT<SpdrHa_SPEC> as RegisterValue<_>>::new(0)
1228 }
1229}
1230
1231#[doc(hidden)]
1232#[derive(Copy, Clone, Eq, PartialEq)]
1233pub struct Spscr_SPEC;
1234impl crate::sealed::RegSpec for Spscr_SPEC {
1235 type DataType = u8;
1236}
1237
1238#[doc = "SPI Sequence Control Register"]
1239pub type Spscr = crate::RegValueT<Spscr_SPEC>;
1240
1241impl Spscr {
1242 #[doc = "RSPI Sequence Length SpecificationThe order in which the SPCMD0 to SPCMD07 registers are to be referenced is changed in accordance with the sequence length that is set in these bits. The relationship among the setting of these bits, sequence length, and SPCMD0 to SPCMD7 registers referenced by the RSPI is shown above. However, the RSPI in slave mode always references SPCMD0."]
1243 #[inline(always)]
1244 pub fn spsln(
1245 self,
1246 ) -> crate::common::RegisterField<
1247 0,
1248 0x7,
1249 1,
1250 0,
1251 spscr::Spsln,
1252 spscr::Spsln,
1253 Spscr_SPEC,
1254 crate::common::RW,
1255 > {
1256 crate::common::RegisterField::<
1257 0,
1258 0x7,
1259 1,
1260 0,
1261 spscr::Spsln,
1262 spscr::Spsln,
1263 Spscr_SPEC,
1264 crate::common::RW,
1265 >::from_register(self, 0)
1266 }
1267}
1268impl ::core::default::Default for Spscr {
1269 #[inline(always)]
1270 fn default() -> Spscr {
1271 <crate::RegValueT<Spscr_SPEC> as RegisterValue<_>>::new(0)
1272 }
1273}
1274pub mod spscr {
1275
1276 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1277 pub struct Spsln_SPEC;
1278 pub type Spsln = crate::EnumBitfieldStruct<u8, Spsln_SPEC>;
1279 impl Spsln {
1280 #[doc = "Length 1 SPDMDx x = 0->0->..."]
1281 pub const _000: Self = Self::new(0);
1282
1283 #[doc = "Length 2 SPDMDx x = 0->1->0->..."]
1284 pub const _001: Self = Self::new(1);
1285
1286 #[doc = "Length 3 SPDMDx x = 0->1->2->0->..."]
1287 pub const _010: Self = Self::new(2);
1288
1289 #[doc = "Length 4 SPDMDx x = 0->1->2->3->0->..."]
1290 pub const _011: Self = Self::new(3);
1291
1292 #[doc = "Length 5 SPDMDx x = 0->1->2->3->4->0->..."]
1293 pub const _100: Self = Self::new(4);
1294
1295 #[doc = "Length 6 SPDMDx x = 0->1->2->3->4->5->0->..."]
1296 pub const _101: Self = Self::new(5);
1297
1298 #[doc = "Length 7 SPDMDx x = 0->1->2->3->4->5->6->0->..."]
1299 pub const _110: Self = Self::new(6);
1300
1301 #[doc = "Length 8 SPDMDx x = 0->1->2->3->4->5->6->7->0->..."]
1302 pub const _111: Self = Self::new(7);
1303 }
1304}
1305#[doc(hidden)]
1306#[derive(Copy, Clone, Eq, PartialEq)]
1307pub struct Spssr_SPEC;
1308impl crate::sealed::RegSpec for Spssr_SPEC {
1309 type DataType = u8;
1310}
1311
1312#[doc = "SPI Sequence Status Register"]
1313pub type Spssr = crate::RegValueT<Spssr_SPEC>;
1314
1315impl Spssr {
1316 #[doc = "RSPI Error Command"]
1317 #[inline(always)]
1318 pub fn specm(
1319 self,
1320 ) -> crate::common::RegisterField<
1321 4,
1322 0x7,
1323 1,
1324 0,
1325 spssr::Specm,
1326 spssr::Specm,
1327 Spssr_SPEC,
1328 crate::common::R,
1329 > {
1330 crate::common::RegisterField::<
1331 4,
1332 0x7,
1333 1,
1334 0,
1335 spssr::Specm,
1336 spssr::Specm,
1337 Spssr_SPEC,
1338 crate::common::R,
1339 >::from_register(self, 0)
1340 }
1341
1342 #[doc = "RSPI Command Pointer"]
1343 #[inline(always)]
1344 pub fn spcp(
1345 self,
1346 ) -> crate::common::RegisterField<
1347 0,
1348 0x7,
1349 1,
1350 0,
1351 spssr::Spcp,
1352 spssr::Spcp,
1353 Spssr_SPEC,
1354 crate::common::R,
1355 > {
1356 crate::common::RegisterField::<
1357 0,
1358 0x7,
1359 1,
1360 0,
1361 spssr::Spcp,
1362 spssr::Spcp,
1363 Spssr_SPEC,
1364 crate::common::R,
1365 >::from_register(self, 0)
1366 }
1367}
1368impl ::core::default::Default for Spssr {
1369 #[inline(always)]
1370 fn default() -> Spssr {
1371 <crate::RegValueT<Spssr_SPEC> as RegisterValue<_>>::new(0)
1372 }
1373}
1374pub mod spssr {
1375
1376 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1377 pub struct Specm_SPEC;
1378 pub type Specm = crate::EnumBitfieldStruct<u8, Specm_SPEC>;
1379 impl Specm {
1380 #[doc = "SPCMD0"]
1381 pub const _000: Self = Self::new(0);
1382
1383 #[doc = "SPCMD1"]
1384 pub const _001: Self = Self::new(1);
1385
1386 #[doc = "SPCMD2"]
1387 pub const _010: Self = Self::new(2);
1388
1389 #[doc = "SPCMD3"]
1390 pub const _011: Self = Self::new(3);
1391
1392 #[doc = "SPCMD4"]
1393 pub const _100: Self = Self::new(4);
1394
1395 #[doc = "SPCMD5"]
1396 pub const _101: Self = Self::new(5);
1397
1398 #[doc = "SPCMD6"]
1399 pub const _110: Self = Self::new(6);
1400
1401 #[doc = "SPCMD7"]
1402 pub const _111: Self = Self::new(7);
1403 }
1404 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1405 pub struct Spcp_SPEC;
1406 pub type Spcp = crate::EnumBitfieldStruct<u8, Spcp_SPEC>;
1407 impl Spcp {
1408 #[doc = "SPCMD0"]
1409 pub const _000: Self = Self::new(0);
1410
1411 #[doc = "SPCMD1"]
1412 pub const _001: Self = Self::new(1);
1413
1414 #[doc = "SPCMD2"]
1415 pub const _010: Self = Self::new(2);
1416
1417 #[doc = "SPCMD3"]
1418 pub const _011: Self = Self::new(3);
1419
1420 #[doc = "SPCMD4"]
1421 pub const _100: Self = Self::new(4);
1422
1423 #[doc = "SPCMD5"]
1424 pub const _101: Self = Self::new(5);
1425
1426 #[doc = "SPCMD6"]
1427 pub const _110: Self = Self::new(6);
1428
1429 #[doc = "SPCMD7"]
1430 pub const _111: Self = Self::new(7);
1431 }
1432}
1433#[doc(hidden)]
1434#[derive(Copy, Clone, Eq, PartialEq)]
1435pub struct Spbr_SPEC;
1436impl crate::sealed::RegSpec for Spbr_SPEC {
1437 type DataType = u8;
1438}
1439
1440#[doc = "SPI Bit Rate Register"]
1441pub type Spbr = crate::RegValueT<Spbr_SPEC>;
1442
1443impl Spbr {
1444 #[doc = "SPBR sets the bit rate in master mode."]
1445 #[inline(always)]
1446 pub fn spr(
1447 self,
1448 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Spbr_SPEC, crate::common::RW> {
1449 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Spbr_SPEC,crate::common::RW>::from_register(self,0)
1450 }
1451}
1452impl ::core::default::Default for Spbr {
1453 #[inline(always)]
1454 fn default() -> Spbr {
1455 <crate::RegValueT<Spbr_SPEC> as RegisterValue<_>>::new(255)
1456 }
1457}
1458
1459#[doc(hidden)]
1460#[derive(Copy, Clone, Eq, PartialEq)]
1461pub struct Spdcr_SPEC;
1462impl crate::sealed::RegSpec for Spdcr_SPEC {
1463 type DataType = u8;
1464}
1465
1466#[doc = "SPI Data Control Register"]
1467pub type Spdcr = crate::RegValueT<Spdcr_SPEC>;
1468
1469impl Spdcr {
1470 #[doc = "SPI Byte Access Specification"]
1471 #[inline(always)]
1472 pub fn spbyt(
1473 self,
1474 ) -> crate::common::RegisterField<
1475 6,
1476 0x1,
1477 1,
1478 0,
1479 spdcr::Spbyt,
1480 spdcr::Spbyt,
1481 Spdcr_SPEC,
1482 crate::common::RW,
1483 > {
1484 crate::common::RegisterField::<
1485 6,
1486 0x1,
1487 1,
1488 0,
1489 spdcr::Spbyt,
1490 spdcr::Spbyt,
1491 Spdcr_SPEC,
1492 crate::common::RW,
1493 >::from_register(self, 0)
1494 }
1495
1496 #[doc = "SPI Word Access/Halfword Access Specification"]
1497 #[inline(always)]
1498 pub fn splw(
1499 self,
1500 ) -> crate::common::RegisterField<
1501 5,
1502 0x1,
1503 1,
1504 0,
1505 spdcr::Splw,
1506 spdcr::Splw,
1507 Spdcr_SPEC,
1508 crate::common::RW,
1509 > {
1510 crate::common::RegisterField::<
1511 5,
1512 0x1,
1513 1,
1514 0,
1515 spdcr::Splw,
1516 spdcr::Splw,
1517 Spdcr_SPEC,
1518 crate::common::RW,
1519 >::from_register(self, 0)
1520 }
1521
1522 #[doc = "RSPI Receive/Transmit Data Selection"]
1523 #[inline(always)]
1524 pub fn sprdtd(
1525 self,
1526 ) -> crate::common::RegisterField<
1527 4,
1528 0x1,
1529 1,
1530 0,
1531 spdcr::Sprdtd,
1532 spdcr::Sprdtd,
1533 Spdcr_SPEC,
1534 crate::common::RW,
1535 > {
1536 crate::common::RegisterField::<
1537 4,
1538 0x1,
1539 1,
1540 0,
1541 spdcr::Sprdtd,
1542 spdcr::Sprdtd,
1543 Spdcr_SPEC,
1544 crate::common::RW,
1545 >::from_register(self, 0)
1546 }
1547
1548 #[doc = "Number of Frames Specification"]
1549 #[inline(always)]
1550 pub fn spfc(
1551 self,
1552 ) -> crate::common::RegisterField<
1553 0,
1554 0x3,
1555 1,
1556 0,
1557 spdcr::Spfc,
1558 spdcr::Spfc,
1559 Spdcr_SPEC,
1560 crate::common::RW,
1561 > {
1562 crate::common::RegisterField::<
1563 0,
1564 0x3,
1565 1,
1566 0,
1567 spdcr::Spfc,
1568 spdcr::Spfc,
1569 Spdcr_SPEC,
1570 crate::common::RW,
1571 >::from_register(self, 0)
1572 }
1573}
1574impl ::core::default::Default for Spdcr {
1575 #[inline(always)]
1576 fn default() -> Spdcr {
1577 <crate::RegValueT<Spdcr_SPEC> as RegisterValue<_>>::new(0)
1578 }
1579}
1580pub mod spdcr {
1581
1582 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1583 pub struct Spbyt_SPEC;
1584 pub type Spbyt = crate::EnumBitfieldStruct<u8, Spbyt_SPEC>;
1585 impl Spbyt {
1586 #[doc = "SPDR is accessed in word or longword (SPLW is valid)"]
1587 pub const _0: Self = Self::new(0);
1588
1589 #[doc = "SPDR is accessed in byte (SPLW is invalid)"]
1590 pub const _1: Self = Self::new(1);
1591 }
1592 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1593 pub struct Splw_SPEC;
1594 pub type Splw = crate::EnumBitfieldStruct<u8, Splw_SPEC>;
1595 impl Splw {
1596 #[doc = "SPDR_HA is valid to access in halfwords"]
1597 pub const _0: Self = Self::new(0);
1598
1599 #[doc = "SPDR is valid (to access in words)."]
1600 pub const _1: Self = Self::new(1);
1601 }
1602 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1603 pub struct Sprdtd_SPEC;
1604 pub type Sprdtd = crate::EnumBitfieldStruct<u8, Sprdtd_SPEC>;
1605 impl Sprdtd {
1606 #[doc = "SPDR values are read from the receive buffer"]
1607 pub const _0: Self = Self::new(0);
1608
1609 #[doc = "SPDR values are read from the transmit buffer (but only if the transmit buffer is empty)"]
1610 pub const _1: Self = Self::new(1);
1611 }
1612 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1613 pub struct Spfc_SPEC;
1614 pub type Spfc = crate::EnumBitfieldStruct<u8, Spfc_SPEC>;
1615 impl Spfc {
1616 #[doc = "1 frame"]
1617 pub const _00: Self = Self::new(0);
1618
1619 #[doc = "2 frames"]
1620 pub const _01: Self = Self::new(1);
1621
1622 #[doc = "3 frames"]
1623 pub const _10: Self = Self::new(2);
1624
1625 #[doc = "4 frames."]
1626 pub const _11: Self = Self::new(3);
1627 }
1628}
1629#[doc(hidden)]
1630#[derive(Copy, Clone, Eq, PartialEq)]
1631pub struct Spckd_SPEC;
1632impl crate::sealed::RegSpec for Spckd_SPEC {
1633 type DataType = u8;
1634}
1635
1636#[doc = "SPI Clock Delay Register"]
1637pub type Spckd = crate::RegValueT<Spckd_SPEC>;
1638
1639impl Spckd {
1640 #[doc = "RSPCK Delay Setting"]
1641 #[inline(always)]
1642 pub fn sckdl(
1643 self,
1644 ) -> crate::common::RegisterField<
1645 0,
1646 0x7,
1647 1,
1648 0,
1649 spckd::Sckdl,
1650 spckd::Sckdl,
1651 Spckd_SPEC,
1652 crate::common::RW,
1653 > {
1654 crate::common::RegisterField::<
1655 0,
1656 0x7,
1657 1,
1658 0,
1659 spckd::Sckdl,
1660 spckd::Sckdl,
1661 Spckd_SPEC,
1662 crate::common::RW,
1663 >::from_register(self, 0)
1664 }
1665}
1666impl ::core::default::Default for Spckd {
1667 #[inline(always)]
1668 fn default() -> Spckd {
1669 <crate::RegValueT<Spckd_SPEC> as RegisterValue<_>>::new(0)
1670 }
1671}
1672pub mod spckd {
1673
1674 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1675 pub struct Sckdl_SPEC;
1676 pub type Sckdl = crate::EnumBitfieldStruct<u8, Sckdl_SPEC>;
1677 impl Sckdl {
1678 #[doc = "1 RSPCK"]
1679 pub const _000: Self = Self::new(0);
1680
1681 #[doc = "2 RSPCK"]
1682 pub const _001: Self = Self::new(1);
1683
1684 #[doc = "3 RSPCK"]
1685 pub const _010: Self = Self::new(2);
1686
1687 #[doc = "4 RSPCK"]
1688 pub const _011: Self = Self::new(3);
1689
1690 #[doc = "5 RSPCK"]
1691 pub const _100: Self = Self::new(4);
1692
1693 #[doc = "6 RSPCK"]
1694 pub const _101: Self = Self::new(5);
1695
1696 #[doc = "7 RSPCK"]
1697 pub const _110: Self = Self::new(6);
1698
1699 #[doc = "8 RSPCK"]
1700 pub const _111: Self = Self::new(7);
1701 }
1702}
1703#[doc(hidden)]
1704#[derive(Copy, Clone, Eq, PartialEq)]
1705pub struct Sslnd_SPEC;
1706impl crate::sealed::RegSpec for Sslnd_SPEC {
1707 type DataType = u8;
1708}
1709
1710#[doc = "SPI Slave Select Negation Delay Register"]
1711pub type Sslnd = crate::RegValueT<Sslnd_SPEC>;
1712
1713impl Sslnd {
1714 #[doc = "SSL Negation Delay Setting"]
1715 #[inline(always)]
1716 pub fn slndl(
1717 self,
1718 ) -> crate::common::RegisterField<
1719 0,
1720 0x7,
1721 1,
1722 0,
1723 sslnd::Slndl,
1724 sslnd::Slndl,
1725 Sslnd_SPEC,
1726 crate::common::RW,
1727 > {
1728 crate::common::RegisterField::<
1729 0,
1730 0x7,
1731 1,
1732 0,
1733 sslnd::Slndl,
1734 sslnd::Slndl,
1735 Sslnd_SPEC,
1736 crate::common::RW,
1737 >::from_register(self, 0)
1738 }
1739}
1740impl ::core::default::Default for Sslnd {
1741 #[inline(always)]
1742 fn default() -> Sslnd {
1743 <crate::RegValueT<Sslnd_SPEC> as RegisterValue<_>>::new(0)
1744 }
1745}
1746pub mod sslnd {
1747
1748 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1749 pub struct Slndl_SPEC;
1750 pub type Slndl = crate::EnumBitfieldStruct<u8, Slndl_SPEC>;
1751 impl Slndl {
1752 #[doc = "1 RSPCK"]
1753 pub const _000: Self = Self::new(0);
1754
1755 #[doc = "2 RSPCK"]
1756 pub const _001: Self = Self::new(1);
1757
1758 #[doc = "3 RSPCK"]
1759 pub const _010: Self = Self::new(2);
1760
1761 #[doc = "4 RSPCK"]
1762 pub const _011: Self = Self::new(3);
1763
1764 #[doc = "5 RSPCK"]
1765 pub const _100: Self = Self::new(4);
1766
1767 #[doc = "6 RSPCK"]
1768 pub const _101: Self = Self::new(5);
1769
1770 #[doc = "7 RSPCK"]
1771 pub const _110: Self = Self::new(6);
1772
1773 #[doc = "8 RSPCK"]
1774 pub const _111: Self = Self::new(7);
1775 }
1776}
1777#[doc(hidden)]
1778#[derive(Copy, Clone, Eq, PartialEq)]
1779pub struct Spnd_SPEC;
1780impl crate::sealed::RegSpec for Spnd_SPEC {
1781 type DataType = u8;
1782}
1783
1784#[doc = "SPI Next-Access Delay Register"]
1785pub type Spnd = crate::RegValueT<Spnd_SPEC>;
1786
1787impl Spnd {
1788 #[doc = "SPI Next-Access Delay Setting"]
1789 #[inline(always)]
1790 pub fn spndl(
1791 self,
1792 ) -> crate::common::RegisterField<
1793 0,
1794 0x7,
1795 1,
1796 0,
1797 spnd::Spndl,
1798 spnd::Spndl,
1799 Spnd_SPEC,
1800 crate::common::RW,
1801 > {
1802 crate::common::RegisterField::<
1803 0,
1804 0x7,
1805 1,
1806 0,
1807 spnd::Spndl,
1808 spnd::Spndl,
1809 Spnd_SPEC,
1810 crate::common::RW,
1811 >::from_register(self, 0)
1812 }
1813}
1814impl ::core::default::Default for Spnd {
1815 #[inline(always)]
1816 fn default() -> Spnd {
1817 <crate::RegValueT<Spnd_SPEC> as RegisterValue<_>>::new(0)
1818 }
1819}
1820pub mod spnd {
1821
1822 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1823 pub struct Spndl_SPEC;
1824 pub type Spndl = crate::EnumBitfieldStruct<u8, Spndl_SPEC>;
1825 impl Spndl {
1826 #[doc = "1 RSPCK + 2 PCLK"]
1827 pub const _000: Self = Self::new(0);
1828
1829 #[doc = "2 RSPCK + 2 PCLK"]
1830 pub const _001: Self = Self::new(1);
1831
1832 #[doc = "3 RSPCK + 2 PCLK"]
1833 pub const _010: Self = Self::new(2);
1834
1835 #[doc = "4 RSPCK + 2 PCLK"]
1836 pub const _011: Self = Self::new(3);
1837
1838 #[doc = "5 RSPCK + 2 PCLK"]
1839 pub const _100: Self = Self::new(4);
1840
1841 #[doc = "6 RSPCK + 2 PCLK"]
1842 pub const _101: Self = Self::new(5);
1843
1844 #[doc = "7 RSPCK + 2 PCLK"]
1845 pub const _110: Self = Self::new(6);
1846
1847 #[doc = "8 RSPCK + 2 PCLK"]
1848 pub const _111: Self = Self::new(7);
1849 }
1850}
1851#[doc(hidden)]
1852#[derive(Copy, Clone, Eq, PartialEq)]
1853pub struct Spcr2_SPEC;
1854impl crate::sealed::RegSpec for Spcr2_SPEC {
1855 type DataType = u8;
1856}
1857
1858#[doc = "SPI Control Register 2"]
1859pub type Spcr2 = crate::RegValueT<Spcr2_SPEC>;
1860
1861impl Spcr2 {
1862 #[doc = "RSPCK Auto-Stop Function Enable"]
1863 #[inline(always)]
1864 pub fn sckase(
1865 self,
1866 ) -> crate::common::RegisterField<
1867 4,
1868 0x1,
1869 1,
1870 0,
1871 spcr2::Sckase,
1872 spcr2::Sckase,
1873 Spcr2_SPEC,
1874 crate::common::RW,
1875 > {
1876 crate::common::RegisterField::<
1877 4,
1878 0x1,
1879 1,
1880 0,
1881 spcr2::Sckase,
1882 spcr2::Sckase,
1883 Spcr2_SPEC,
1884 crate::common::RW,
1885 >::from_register(self, 0)
1886 }
1887
1888 #[doc = "Parity Self-Testing"]
1889 #[inline(always)]
1890 pub fn pte(
1891 self,
1892 ) -> crate::common::RegisterField<
1893 3,
1894 0x1,
1895 1,
1896 0,
1897 spcr2::Pte,
1898 spcr2::Pte,
1899 Spcr2_SPEC,
1900 crate::common::RW,
1901 > {
1902 crate::common::RegisterField::<
1903 3,
1904 0x1,
1905 1,
1906 0,
1907 spcr2::Pte,
1908 spcr2::Pte,
1909 Spcr2_SPEC,
1910 crate::common::RW,
1911 >::from_register(self, 0)
1912 }
1913
1914 #[doc = "SPI Idle Interrupt Enable"]
1915 #[inline(always)]
1916 pub fn spiie(
1917 self,
1918 ) -> crate::common::RegisterField<
1919 2,
1920 0x1,
1921 1,
1922 0,
1923 spcr2::Spiie,
1924 spcr2::Spiie,
1925 Spcr2_SPEC,
1926 crate::common::RW,
1927 > {
1928 crate::common::RegisterField::<
1929 2,
1930 0x1,
1931 1,
1932 0,
1933 spcr2::Spiie,
1934 spcr2::Spiie,
1935 Spcr2_SPEC,
1936 crate::common::RW,
1937 >::from_register(self, 0)
1938 }
1939
1940 #[doc = "Parity Mode"]
1941 #[inline(always)]
1942 pub fn spoe(
1943 self,
1944 ) -> crate::common::RegisterField<
1945 1,
1946 0x1,
1947 1,
1948 0,
1949 spcr2::Spoe,
1950 spcr2::Spoe,
1951 Spcr2_SPEC,
1952 crate::common::RW,
1953 > {
1954 crate::common::RegisterField::<
1955 1,
1956 0x1,
1957 1,
1958 0,
1959 spcr2::Spoe,
1960 spcr2::Spoe,
1961 Spcr2_SPEC,
1962 crate::common::RW,
1963 >::from_register(self, 0)
1964 }
1965
1966 #[doc = "Parity Enable"]
1967 #[inline(always)]
1968 pub fn sppe(
1969 self,
1970 ) -> crate::common::RegisterField<
1971 0,
1972 0x1,
1973 1,
1974 0,
1975 spcr2::Sppe,
1976 spcr2::Sppe,
1977 Spcr2_SPEC,
1978 crate::common::RW,
1979 > {
1980 crate::common::RegisterField::<
1981 0,
1982 0x1,
1983 1,
1984 0,
1985 spcr2::Sppe,
1986 spcr2::Sppe,
1987 Spcr2_SPEC,
1988 crate::common::RW,
1989 >::from_register(self, 0)
1990 }
1991}
1992impl ::core::default::Default for Spcr2 {
1993 #[inline(always)]
1994 fn default() -> Spcr2 {
1995 <crate::RegValueT<Spcr2_SPEC> as RegisterValue<_>>::new(0)
1996 }
1997}
1998pub mod spcr2 {
1999
2000 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2001 pub struct Sckase_SPEC;
2002 pub type Sckase = crate::EnumBitfieldStruct<u8, Sckase_SPEC>;
2003 impl Sckase {
2004 #[doc = "Disables the RSPCK auto-stop function"]
2005 pub const _0: Self = Self::new(0);
2006
2007 #[doc = "Enables the RSPCK auto-stop function"]
2008 pub const _1: Self = Self::new(1);
2009 }
2010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2011 pub struct Pte_SPEC;
2012 pub type Pte = crate::EnumBitfieldStruct<u8, Pte_SPEC>;
2013 impl Pte {
2014 #[doc = "Disables the self-diagnosis function of the parity circuit"]
2015 pub const _0: Self = Self::new(0);
2016
2017 #[doc = "Enables the self-diagnosis function of the parity circuit"]
2018 pub const _1: Self = Self::new(1);
2019 }
2020 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2021 pub struct Spiie_SPEC;
2022 pub type Spiie = crate::EnumBitfieldStruct<u8, Spiie_SPEC>;
2023 impl Spiie {
2024 #[doc = "Disables the generation of idle interrupt requests"]
2025 pub const _0: Self = Self::new(0);
2026
2027 #[doc = "Enables the generation of idle interrupt requests"]
2028 pub const _1: Self = Self::new(1);
2029 }
2030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2031 pub struct Spoe_SPEC;
2032 pub type Spoe = crate::EnumBitfieldStruct<u8, Spoe_SPEC>;
2033 impl Spoe {
2034 #[doc = "Selects even parity for use in transmission and reception"]
2035 pub const _0: Self = Self::new(0);
2036
2037 #[doc = "Selects odd parity for use in transmission and reception"]
2038 pub const _1: Self = Self::new(1);
2039 }
2040 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2041 pub struct Sppe_SPEC;
2042 pub type Sppe = crate::EnumBitfieldStruct<u8, Sppe_SPEC>;
2043 impl Sppe {
2044 #[doc = "Does not add the parity bit to transmit data and does not check the parity bit of receive data"]
2045 pub const _0: Self = Self::new(0);
2046
2047 #[doc = "Adds the parity bit to transmit data and checks the parity bit of receive data (when SPCR.TXMD = 0) / Adds the parity bit to transmit data but does not check the parity bit of receive data (when SPCR.TXMD = 1)"]
2048 pub const _1: Self = Self::new(1);
2049 }
2050}
2051#[doc(hidden)]
2052#[derive(Copy, Clone, Eq, PartialEq)]
2053pub struct Spcmd_SPEC;
2054impl crate::sealed::RegSpec for Spcmd_SPEC {
2055 type DataType = u16;
2056}
2057
2058#[doc = "SPI Command Register %s"]
2059pub type Spcmd = crate::RegValueT<Spcmd_SPEC>;
2060
2061impl Spcmd {
2062 #[doc = "RSPCK Delay Setting Enable"]
2063 #[inline(always)]
2064 pub fn sckden(
2065 self,
2066 ) -> crate::common::RegisterField<
2067 15,
2068 0x1,
2069 1,
2070 0,
2071 spcmd::Sckden,
2072 spcmd::Sckden,
2073 Spcmd_SPEC,
2074 crate::common::RW,
2075 > {
2076 crate::common::RegisterField::<
2077 15,
2078 0x1,
2079 1,
2080 0,
2081 spcmd::Sckden,
2082 spcmd::Sckden,
2083 Spcmd_SPEC,
2084 crate::common::RW,
2085 >::from_register(self, 0)
2086 }
2087
2088 #[doc = "SSL Negation Delay Setting Enable"]
2089 #[inline(always)]
2090 pub fn slnden(
2091 self,
2092 ) -> crate::common::RegisterField<
2093 14,
2094 0x1,
2095 1,
2096 0,
2097 spcmd::Slnden,
2098 spcmd::Slnden,
2099 Spcmd_SPEC,
2100 crate::common::RW,
2101 > {
2102 crate::common::RegisterField::<
2103 14,
2104 0x1,
2105 1,
2106 0,
2107 spcmd::Slnden,
2108 spcmd::Slnden,
2109 Spcmd_SPEC,
2110 crate::common::RW,
2111 >::from_register(self, 0)
2112 }
2113
2114 #[doc = "RSPI Next-Access Delay Enable"]
2115 #[inline(always)]
2116 pub fn spnden(
2117 self,
2118 ) -> crate::common::RegisterField<
2119 13,
2120 0x1,
2121 1,
2122 0,
2123 spcmd::Spnden,
2124 spcmd::Spnden,
2125 Spcmd_SPEC,
2126 crate::common::RW,
2127 > {
2128 crate::common::RegisterField::<
2129 13,
2130 0x1,
2131 1,
2132 0,
2133 spcmd::Spnden,
2134 spcmd::Spnden,
2135 Spcmd_SPEC,
2136 crate::common::RW,
2137 >::from_register(self, 0)
2138 }
2139
2140 #[doc = "RSPI LSB First"]
2141 #[inline(always)]
2142 pub fn lsbf(
2143 self,
2144 ) -> crate::common::RegisterField<
2145 12,
2146 0x1,
2147 1,
2148 0,
2149 spcmd::Lsbf,
2150 spcmd::Lsbf,
2151 Spcmd_SPEC,
2152 crate::common::RW,
2153 > {
2154 crate::common::RegisterField::<
2155 12,
2156 0x1,
2157 1,
2158 0,
2159 spcmd::Lsbf,
2160 spcmd::Lsbf,
2161 Spcmd_SPEC,
2162 crate::common::RW,
2163 >::from_register(self, 0)
2164 }
2165
2166 #[doc = "RSPI Data Length Setting"]
2167 #[inline(always)]
2168 pub fn spb(
2169 self,
2170 ) -> crate::common::RegisterField<
2171 8,
2172 0xf,
2173 1,
2174 0,
2175 spcmd::Spb,
2176 spcmd::Spb,
2177 Spcmd_SPEC,
2178 crate::common::RW,
2179 > {
2180 crate::common::RegisterField::<
2181 8,
2182 0xf,
2183 1,
2184 0,
2185 spcmd::Spb,
2186 spcmd::Spb,
2187 Spcmd_SPEC,
2188 crate::common::RW,
2189 >::from_register(self, 0)
2190 }
2191
2192 #[doc = "SSL Signal Level Keeping"]
2193 #[inline(always)]
2194 pub fn sslkp(
2195 self,
2196 ) -> crate::common::RegisterField<
2197 7,
2198 0x1,
2199 1,
2200 0,
2201 spcmd::Sslkp,
2202 spcmd::Sslkp,
2203 Spcmd_SPEC,
2204 crate::common::RW,
2205 > {
2206 crate::common::RegisterField::<
2207 7,
2208 0x1,
2209 1,
2210 0,
2211 spcmd::Sslkp,
2212 spcmd::Sslkp,
2213 Spcmd_SPEC,
2214 crate::common::RW,
2215 >::from_register(self, 0)
2216 }
2217
2218 #[doc = "SSL Signal Assertion Setting"]
2219 #[inline(always)]
2220 pub fn ssla(
2221 self,
2222 ) -> crate::common::RegisterField<
2223 4,
2224 0x7,
2225 1,
2226 0,
2227 spcmd::Ssla,
2228 spcmd::Ssla,
2229 Spcmd_SPEC,
2230 crate::common::RW,
2231 > {
2232 crate::common::RegisterField::<
2233 4,
2234 0x7,
2235 1,
2236 0,
2237 spcmd::Ssla,
2238 spcmd::Ssla,
2239 Spcmd_SPEC,
2240 crate::common::RW,
2241 >::from_register(self, 0)
2242 }
2243
2244 #[doc = "Bit Rate Division Setting"]
2245 #[inline(always)]
2246 pub fn brdv(
2247 self,
2248 ) -> crate::common::RegisterField<
2249 2,
2250 0x3,
2251 1,
2252 0,
2253 spcmd::Brdv,
2254 spcmd::Brdv,
2255 Spcmd_SPEC,
2256 crate::common::RW,
2257 > {
2258 crate::common::RegisterField::<
2259 2,
2260 0x3,
2261 1,
2262 0,
2263 spcmd::Brdv,
2264 spcmd::Brdv,
2265 Spcmd_SPEC,
2266 crate::common::RW,
2267 >::from_register(self, 0)
2268 }
2269
2270 #[doc = "RSPCK Polarity Setting"]
2271 #[inline(always)]
2272 pub fn cpol(
2273 self,
2274 ) -> crate::common::RegisterField<
2275 1,
2276 0x1,
2277 1,
2278 0,
2279 spcmd::Cpol,
2280 spcmd::Cpol,
2281 Spcmd_SPEC,
2282 crate::common::RW,
2283 > {
2284 crate::common::RegisterField::<
2285 1,
2286 0x1,
2287 1,
2288 0,
2289 spcmd::Cpol,
2290 spcmd::Cpol,
2291 Spcmd_SPEC,
2292 crate::common::RW,
2293 >::from_register(self, 0)
2294 }
2295
2296 #[doc = "RSPCK Phase Setting"]
2297 #[inline(always)]
2298 pub fn cpha(
2299 self,
2300 ) -> crate::common::RegisterField<
2301 0,
2302 0x1,
2303 1,
2304 0,
2305 spcmd::Cpha,
2306 spcmd::Cpha,
2307 Spcmd_SPEC,
2308 crate::common::RW,
2309 > {
2310 crate::common::RegisterField::<
2311 0,
2312 0x1,
2313 1,
2314 0,
2315 spcmd::Cpha,
2316 spcmd::Cpha,
2317 Spcmd_SPEC,
2318 crate::common::RW,
2319 >::from_register(self, 0)
2320 }
2321}
2322impl ::core::default::Default for Spcmd {
2323 #[inline(always)]
2324 fn default() -> Spcmd {
2325 <crate::RegValueT<Spcmd_SPEC> as RegisterValue<_>>::new(1805)
2326 }
2327}
2328pub mod spcmd {
2329
2330 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2331 pub struct Sckden_SPEC;
2332 pub type Sckden = crate::EnumBitfieldStruct<u8, Sckden_SPEC>;
2333 impl Sckden {
2334 #[doc = "An RSPCK delay of 1 RSPCK"]
2335 pub const _0: Self = Self::new(0);
2336
2337 #[doc = "An RSPCK delay is equal to the setting of the RSPI clock delay register (SPCKD)"]
2338 pub const _1: Self = Self::new(1);
2339 }
2340 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2341 pub struct Slnden_SPEC;
2342 pub type Slnden = crate::EnumBitfieldStruct<u8, Slnden_SPEC>;
2343 impl Slnden {
2344 #[doc = "An SSL negation delay of 1 RSPCK"]
2345 pub const _0: Self = Self::new(0);
2346
2347 #[doc = "An SSL negation delay is equal to the setting of the RSPI slave select negation delay register (SSLND)"]
2348 pub const _1: Self = Self::new(1);
2349 }
2350 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2351 pub struct Spnden_SPEC;
2352 pub type Spnden = crate::EnumBitfieldStruct<u8, Spnden_SPEC>;
2353 impl Spnden {
2354 #[doc = "A next-access delay of 1 RSPCK + 2 PCLK"]
2355 pub const _0: Self = Self::new(0);
2356
2357 #[doc = "A next-access delay is equal to the setting of the RSPI next-access delay register (SPND)"]
2358 pub const _1: Self = Self::new(1);
2359 }
2360 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2361 pub struct Lsbf_SPEC;
2362 pub type Lsbf = crate::EnumBitfieldStruct<u8, Lsbf_SPEC>;
2363 impl Lsbf {
2364 #[doc = "MSB first"]
2365 pub const _0: Self = Self::new(0);
2366
2367 #[doc = "LSB first"]
2368 pub const _1: Self = Self::new(1);
2369 }
2370 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2371 pub struct Spb_SPEC;
2372 pub type Spb = crate::EnumBitfieldStruct<u8, Spb_SPEC>;
2373 impl Spb {
2374 #[doc = "20 bits"]
2375 pub const _0000: Self = Self::new(0);
2376
2377 #[doc = "24 bits"]
2378 pub const _0001: Self = Self::new(1);
2379
2380 #[doc = "32 bits"]
2381 pub const _0010: Self = Self::new(2);
2382
2383 #[doc = "32 bits"]
2384 pub const _0011: Self = Self::new(3);
2385
2386 #[doc = "9 bits"]
2387 pub const _1000: Self = Self::new(8);
2388
2389 #[doc = "10 bits"]
2390 pub const _1001: Self = Self::new(9);
2391
2392 #[doc = "11 bits"]
2393 pub const _1010: Self = Self::new(10);
2394
2395 #[doc = "12 bits"]
2396 pub const _1011: Self = Self::new(11);
2397
2398 #[doc = "13 bits"]
2399 pub const _1100: Self = Self::new(12);
2400
2401 #[doc = "14 bits"]
2402 pub const _1101: Self = Self::new(13);
2403
2404 #[doc = "15 bits"]
2405 pub const _1110: Self = Self::new(14);
2406
2407 #[doc = "16 bits"]
2408 pub const _1111: Self = Self::new(15);
2409 }
2410 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2411 pub struct Sslkp_SPEC;
2412 pub type Sslkp = crate::EnumBitfieldStruct<u8, Sslkp_SPEC>;
2413 impl Sslkp {
2414 #[doc = "Negate all SSL signals on completion of transfer"]
2415 pub const _0: Self = Self::new(0);
2416
2417 #[doc = "Keep SSL signal level from the end of transfer until the beginning"]
2418 pub const _1: Self = Self::new(1);
2419 }
2420 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2421 pub struct Ssla_SPEC;
2422 pub type Ssla = crate::EnumBitfieldStruct<u8, Ssla_SPEC>;
2423 impl Ssla {
2424 #[doc = "SSL0"]
2425 pub const _000: Self = Self::new(0);
2426
2427 #[doc = "SSL1"]
2428 pub const _001: Self = Self::new(1);
2429
2430 #[doc = "SSL2"]
2431 pub const _010: Self = Self::new(2);
2432
2433 #[doc = "SSL3"]
2434 pub const _011: Self = Self::new(3);
2435 }
2436 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2437 pub struct Brdv_SPEC;
2438 pub type Brdv = crate::EnumBitfieldStruct<u8, Brdv_SPEC>;
2439 impl Brdv {
2440 #[doc = "These bits select the base bit rate"]
2441 pub const _00: Self = Self::new(0);
2442
2443 #[doc = "These bits select the base bit rate divided by 2"]
2444 pub const _01: Self = Self::new(1);
2445
2446 #[doc = "These bits select the base bit rate divided by 4"]
2447 pub const _10: Self = Self::new(2);
2448
2449 #[doc = "These bits select the base bit rate divided by 8"]
2450 pub const _11: Self = Self::new(3);
2451 }
2452 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2453 pub struct Cpol_SPEC;
2454 pub type Cpol = crate::EnumBitfieldStruct<u8, Cpol_SPEC>;
2455 impl Cpol {
2456 #[doc = "RSPCK is low when idle"]
2457 pub const _0: Self = Self::new(0);
2458
2459 #[doc = "RSPCK is high when idle"]
2460 pub const _1: Self = Self::new(1);
2461 }
2462 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2463 pub struct Cpha_SPEC;
2464 pub type Cpha = crate::EnumBitfieldStruct<u8, Cpha_SPEC>;
2465 impl Cpha {
2466 #[doc = "Data sampling on odd edge, data variation on even edge"]
2467 pub const _0: Self = Self::new(0);
2468
2469 #[doc = "Data variation on odd edge, data sampling on even edge"]
2470 pub const _1: Self = Self::new(1);
2471 }
2472}
2473#[doc(hidden)]
2474#[derive(Copy, Clone, Eq, PartialEq)]
2475pub struct Spdcr2_SPEC;
2476impl crate::sealed::RegSpec for Spdcr2_SPEC {
2477 type DataType = u8;
2478}
2479
2480#[doc = "SPI Data Control Register 2"]
2481pub type Spdcr2 = crate::RegValueT<Spdcr2_SPEC>;
2482
2483impl Spdcr2 {
2484 #[doc = "Byte Swap Operating Mode Select"]
2485 #[inline(always)]
2486 pub fn bysw(
2487 self,
2488 ) -> crate::common::RegisterField<
2489 0,
2490 0x1,
2491 1,
2492 0,
2493 spdcr2::Bysw,
2494 spdcr2::Bysw,
2495 Spdcr2_SPEC,
2496 crate::common::RW,
2497 > {
2498 crate::common::RegisterField::<
2499 0,
2500 0x1,
2501 1,
2502 0,
2503 spdcr2::Bysw,
2504 spdcr2::Bysw,
2505 Spdcr2_SPEC,
2506 crate::common::RW,
2507 >::from_register(self, 0)
2508 }
2509}
2510impl ::core::default::Default for Spdcr2 {
2511 #[inline(always)]
2512 fn default() -> Spdcr2 {
2513 <crate::RegValueT<Spdcr2_SPEC> as RegisterValue<_>>::new(0)
2514 }
2515}
2516pub mod spdcr2 {
2517
2518 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2519 pub struct Bysw_SPEC;
2520 pub type Bysw = crate::EnumBitfieldStruct<u8, Bysw_SPEC>;
2521 impl Bysw {
2522 #[doc = "Byte Swap Operating Mode disabled"]
2523 pub const _0: Self = Self::new(0);
2524
2525 #[doc = "Byte Swap Operating Mode enabled"]
2526 pub const _1: Self = Self::new(1);
2527 }
2528}