ra6m1/port1/
pdr.rs

1#[doc = "Register `PDR` reader"]
2pub struct R(crate::R<PDR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<PDR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<PDR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<PDR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `PDR` writer"]
17pub struct W(crate::W<PDR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<PDR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<PDR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<PDR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `PDR` reader - Pmn Direction"]
38pub type PDR_R = crate::FieldReader<u16, PDR_A>;
39#[doc = "Pmn Direction\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u16)]
42pub enum PDR_A {
43    #[doc = "0: Input (functions as an input pin)"]
44    _0 = 0,
45    #[doc = "1: Output (functions as an output pin)."]
46    _1 = 1,
47}
48impl From<PDR_A> for u16 {
49    #[inline(always)]
50    fn from(variant: PDR_A) -> Self {
51        variant as _
52    }
53}
54impl PDR_R {
55    #[doc = "Get enumerated values variant"]
56    #[inline(always)]
57    pub fn variant(&self) -> Option<PDR_A> {
58        match self.bits {
59            0 => Some(PDR_A::_0),
60            1 => Some(PDR_A::_1),
61            _ => None,
62        }
63    }
64    #[doc = "Checks if the value of the field is `_0`"]
65    #[inline(always)]
66    pub fn is_0(&self) -> bool {
67        *self == PDR_A::_0
68    }
69    #[doc = "Checks if the value of the field is `_1`"]
70    #[inline(always)]
71    pub fn is_1(&self) -> bool {
72        *self == PDR_A::_1
73    }
74}
75#[doc = "Field `PDR` writer - Pmn Direction"]
76pub type PDR_W<'a, const O: u8> = crate::FieldWriter<'a, u16, PDR_SPEC, u16, PDR_A, 16, O>;
77impl<'a, const O: u8> PDR_W<'a, O> {
78    #[doc = "Input (functions as an input pin)"]
79    #[inline(always)]
80    pub fn _0(self) -> &'a mut W {
81        self.variant(PDR_A::_0)
82    }
83    #[doc = "Output (functions as an output pin)."]
84    #[inline(always)]
85    pub fn _1(self) -> &'a mut W {
86        self.variant(PDR_A::_1)
87    }
88}
89impl R {
90    #[doc = "Bits 0:15 - Pmn Direction"]
91    #[inline(always)]
92    pub fn pdr(&self) -> PDR_R {
93        PDR_R::new(self.bits)
94    }
95}
96impl W {
97    #[doc = "Bits 0:15 - Pmn Direction"]
98    #[inline(always)]
99    #[must_use]
100    pub fn pdr(&mut self) -> PDR_W<0> {
101        PDR_W::new(self)
102    }
103    #[doc = "Writes raw bits to the register."]
104    #[inline(always)]
105    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
106        self.0.bits(bits);
107        self
108    }
109}
110#[doc = "Data direction register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [pdr](index.html) module"]
111pub struct PDR_SPEC;
112impl crate::RegisterSpec for PDR_SPEC {
113    type Ux = u16;
114}
115#[doc = "`read()` method returns [pdr::R](R) reader structure"]
116impl crate::Readable for PDR_SPEC {
117    type Reader = R;
118}
119#[doc = "`write(|w| ..)` method takes [pdr::W](W) writer structure"]
120impl crate::Writable for PDR_SPEC {
121    type Writer = W;
122    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
123    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
124}
125#[doc = "`reset()` method sets PDR to value 0"]
126impl crate::Resettable for PDR_SPEC {
127    const RESET_VALUE: Self::Ux = 0;
128}
ra6m1/port1/pdr.rs

ra6m1/port1/
pdr.rs
