ra6e1/sci2/
sptr.rs

1#[doc = "Register `SPTR` reader"]
2pub struct R(crate::R<SPTR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPTR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPTR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPTR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SPTR` writer"]
17pub struct W(crate::W<SPTR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPTR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPTR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPTR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `RXDMON` reader - Serial Input Data Monitor"]
38pub type RXDMON_R = crate::BitReader<bool>;
39#[doc = "Field `SPB2DT` reader - Serial Port Break Data Select"]
40pub type SPB2DT_R = crate::BitReader<bool>;
41#[doc = "Field `SPB2DT` writer - Serial Port Break Data Select"]
42pub type SPB2DT_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, bool, O>;
43#[doc = "Field `SPB2IO` reader - Serial Port Break I/O"]
44pub type SPB2IO_R = crate::BitReader<SPB2IO_A>;
45#[doc = "Serial Port Break I/O\n\nValue on reset: 0"]
46#[derive(Clone, Copy, Debug, PartialEq, Eq)]
47pub enum SPB2IO_A {
48    #[doc = "0: Do not output value of SPB2DT bit on TXDn pin"]
49    _0 = 0,
50    #[doc = "1: Output value of SPB2DT bit on TXDn pin"]
51    _1 = 1,
52}
53impl From<SPB2IO_A> for bool {
54    #[inline(always)]
55    fn from(variant: SPB2IO_A) -> Self {
56        variant as u8 != 0
57    }
58}
59impl SPB2IO_R {
60    #[doc = "Get enumerated values variant"]
61    #[inline(always)]
62    pub fn variant(&self) -> SPB2IO_A {
63        match self.bits {
64            false => SPB2IO_A::_0,
65            true => SPB2IO_A::_1,
66        }
67    }
68    #[doc = "Checks if the value of the field is `_0`"]
69    #[inline(always)]
70    pub fn is_0(&self) -> bool {
71        *self == SPB2IO_A::_0
72    }
73    #[doc = "Checks if the value of the field is `_1`"]
74    #[inline(always)]
75    pub fn is_1(&self) -> bool {
76        *self == SPB2IO_A::_1
77    }
78}
79#[doc = "Field `SPB2IO` writer - Serial Port Break I/O"]
80pub type SPB2IO_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, SPB2IO_A, O>;
81impl<'a, const O: u8> SPB2IO_W<'a, O> {
82    #[doc = "Do not output value of SPB2DT bit on TXDn pin"]
83    #[inline(always)]
84    pub fn _0(self) -> &'a mut W {
85        self.variant(SPB2IO_A::_0)
86    }
87    #[doc = "Output value of SPB2DT bit on TXDn pin"]
88    #[inline(always)]
89    pub fn _1(self) -> &'a mut W {
90        self.variant(SPB2IO_A::_1)
91    }
92}
93#[doc = "Field `RINV` reader - RXD invert bit"]
94pub type RINV_R = crate::BitReader<RINV_A>;
95#[doc = "RXD invert bit\n\nValue on reset: 0"]
96#[derive(Clone, Copy, Debug, PartialEq, Eq)]
97pub enum RINV_A {
98    #[doc = "0: Received data from RXDn is not inverted and input."]
99    _0 = 0,
100    #[doc = "1: Received data from RXDn is inverted and input."]
101    _1 = 1,
102}
103impl From<RINV_A> for bool {
104    #[inline(always)]
105    fn from(variant: RINV_A) -> Self {
106        variant as u8 != 0
107    }
108}
109impl RINV_R {
110    #[doc = "Get enumerated values variant"]
111    #[inline(always)]
112    pub fn variant(&self) -> RINV_A {
113        match self.bits {
114            false => RINV_A::_0,
115            true => RINV_A::_1,
116        }
117    }
118    #[doc = "Checks if the value of the field is `_0`"]
119    #[inline(always)]
120    pub fn is_0(&self) -> bool {
121        *self == RINV_A::_0
122    }
123    #[doc = "Checks if the value of the field is `_1`"]
124    #[inline(always)]
125    pub fn is_1(&self) -> bool {
126        *self == RINV_A::_1
127    }
128}
129#[doc = "Field `RINV` writer - RXD invert bit"]
130pub type RINV_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, RINV_A, O>;
131impl<'a, const O: u8> RINV_W<'a, O> {
132    #[doc = "Received data from RXDn is not inverted and input."]
133    #[inline(always)]
134    pub fn _0(self) -> &'a mut W {
135        self.variant(RINV_A::_0)
136    }
137    #[doc = "Received data from RXDn is inverted and input."]
138    #[inline(always)]
139    pub fn _1(self) -> &'a mut W {
140        self.variant(RINV_A::_1)
141    }
142}
143#[doc = "Field `TINV` reader - TXD invert bit"]
144pub type TINV_R = crate::BitReader<TINV_A>;
145#[doc = "TXD invert bit\n\nValue on reset: 0"]
146#[derive(Clone, Copy, Debug, PartialEq, Eq)]
147pub enum TINV_A {
148    #[doc = "0: Transmit data is not inverted and output to TXDn."]
149    _0 = 0,
150    #[doc = "1: Transmit data is inverted and output to TXDn."]
151    _1 = 1,
152}
153impl From<TINV_A> for bool {
154    #[inline(always)]
155    fn from(variant: TINV_A) -> Self {
156        variant as u8 != 0
157    }
158}
159impl TINV_R {
160    #[doc = "Get enumerated values variant"]
161    #[inline(always)]
162    pub fn variant(&self) -> TINV_A {
163        match self.bits {
164            false => TINV_A::_0,
165            true => TINV_A::_1,
166        }
167    }
168    #[doc = "Checks if the value of the field is `_0`"]
169    #[inline(always)]
170    pub fn is_0(&self) -> bool {
171        *self == TINV_A::_0
172    }
173    #[doc = "Checks if the value of the field is `_1`"]
174    #[inline(always)]
175    pub fn is_1(&self) -> bool {
176        *self == TINV_A::_1
177    }
178}
179#[doc = "Field `TINV` writer - TXD invert bit"]
180pub type TINV_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, TINV_A, O>;
181impl<'a, const O: u8> TINV_W<'a, O> {
182    #[doc = "Transmit data is not inverted and output to TXDn."]
183    #[inline(always)]
184    pub fn _0(self) -> &'a mut W {
185        self.variant(TINV_A::_0)
186    }
187    #[doc = "Transmit data is inverted and output to TXDn."]
188    #[inline(always)]
189    pub fn _1(self) -> &'a mut W {
190        self.variant(TINV_A::_1)
191    }
192}
193#[doc = "Field `ASEN` reader - Adjust receive sampling timing enable"]
194pub type ASEN_R = crate::BitReader<ASEN_A>;
195#[doc = "Adjust receive sampling timing enable\n\nValue on reset: 0"]
196#[derive(Clone, Copy, Debug, PartialEq, Eq)]
197pub enum ASEN_A {
198    #[doc = "0: Adjust sampling timing disable."]
199    _0 = 0,
200    #[doc = "1: Adjust sampling timing enable."]
201    _1 = 1,
202}
203impl From<ASEN_A> for bool {
204    #[inline(always)]
205    fn from(variant: ASEN_A) -> Self {
206        variant as u8 != 0
207    }
208}
209impl ASEN_R {
210    #[doc = "Get enumerated values variant"]
211    #[inline(always)]
212    pub fn variant(&self) -> ASEN_A {
213        match self.bits {
214            false => ASEN_A::_0,
215            true => ASEN_A::_1,
216        }
217    }
218    #[doc = "Checks if the value of the field is `_0`"]
219    #[inline(always)]
220    pub fn is_0(&self) -> bool {
221        *self == ASEN_A::_0
222    }
223    #[doc = "Checks if the value of the field is `_1`"]
224    #[inline(always)]
225    pub fn is_1(&self) -> bool {
226        *self == ASEN_A::_1
227    }
228}
229#[doc = "Field `ASEN` writer - Adjust receive sampling timing enable"]
230pub type ASEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, ASEN_A, O>;
231impl<'a, const O: u8> ASEN_W<'a, O> {
232    #[doc = "Adjust sampling timing disable."]
233    #[inline(always)]
234    pub fn _0(self) -> &'a mut W {
235        self.variant(ASEN_A::_0)
236    }
237    #[doc = "Adjust sampling timing enable."]
238    #[inline(always)]
239    pub fn _1(self) -> &'a mut W {
240        self.variant(ASEN_A::_1)
241    }
242}
243#[doc = "Field `ATEN` reader - Adjust transmit timing enable"]
244pub type ATEN_R = crate::BitReader<ATEN_A>;
245#[doc = "Adjust transmit timing enable\n\nValue on reset: 0"]
246#[derive(Clone, Copy, Debug, PartialEq, Eq)]
247pub enum ATEN_A {
248    #[doc = "0: Adjust transmit timing disable."]
249    _0 = 0,
250    #[doc = "1: Adjust transmit timing enable."]
251    _1 = 1,
252}
253impl From<ATEN_A> for bool {
254    #[inline(always)]
255    fn from(variant: ATEN_A) -> Self {
256        variant as u8 != 0
257    }
258}
259impl ATEN_R {
260    #[doc = "Get enumerated values variant"]
261    #[inline(always)]
262    pub fn variant(&self) -> ATEN_A {
263        match self.bits {
264            false => ATEN_A::_0,
265            true => ATEN_A::_1,
266        }
267    }
268    #[doc = "Checks if the value of the field is `_0`"]
269    #[inline(always)]
270    pub fn is_0(&self) -> bool {
271        *self == ATEN_A::_0
272    }
273    #[doc = "Checks if the value of the field is `_1`"]
274    #[inline(always)]
275    pub fn is_1(&self) -> bool {
276        *self == ATEN_A::_1
277    }
278}
279#[doc = "Field `ATEN` writer - Adjust transmit timing enable"]
280pub type ATEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPTR_SPEC, ATEN_A, O>;
281impl<'a, const O: u8> ATEN_W<'a, O> {
282    #[doc = "Adjust transmit timing disable."]
283    #[inline(always)]
284    pub fn _0(self) -> &'a mut W {
285        self.variant(ATEN_A::_0)
286    }
287    #[doc = "Adjust transmit timing enable."]
288    #[inline(always)]
289    pub fn _1(self) -> &'a mut W {
290        self.variant(ATEN_A::_1)
291    }
292}
293impl R {
294    #[doc = "Bit 0 - Serial Input Data Monitor"]
295    #[inline(always)]
296    pub fn rxdmon(&self) -> RXDMON_R {
297        RXDMON_R::new((self.bits & 1) != 0)
298    }
299    #[doc = "Bit 1 - Serial Port Break Data Select"]
300    #[inline(always)]
301    pub fn spb2dt(&self) -> SPB2DT_R {
302        SPB2DT_R::new(((self.bits >> 1) & 1) != 0)
303    }
304    #[doc = "Bit 2 - Serial Port Break I/O"]
305    #[inline(always)]
306    pub fn spb2io(&self) -> SPB2IO_R {
307        SPB2IO_R::new(((self.bits >> 2) & 1) != 0)
308    }
309    #[doc = "Bit 4 - RXD invert bit"]
310    #[inline(always)]
311    pub fn rinv(&self) -> RINV_R {
312        RINV_R::new(((self.bits >> 4) & 1) != 0)
313    }
314    #[doc = "Bit 5 - TXD invert bit"]
315    #[inline(always)]
316    pub fn tinv(&self) -> TINV_R {
317        TINV_R::new(((self.bits >> 5) & 1) != 0)
318    }
319    #[doc = "Bit 6 - Adjust receive sampling timing enable"]
320    #[inline(always)]
321    pub fn asen(&self) -> ASEN_R {
322        ASEN_R::new(((self.bits >> 6) & 1) != 0)
323    }
324    #[doc = "Bit 7 - Adjust transmit timing enable"]
325    #[inline(always)]
326    pub fn aten(&self) -> ATEN_R {
327        ATEN_R::new(((self.bits >> 7) & 1) != 0)
328    }
329}
330impl W {
331    #[doc = "Bit 1 - Serial Port Break Data Select"]
332    #[inline(always)]
333    #[must_use]
334    pub fn spb2dt(&mut self) -> SPB2DT_W<1> {
335        SPB2DT_W::new(self)
336    }
337    #[doc = "Bit 2 - Serial Port Break I/O"]
338    #[inline(always)]
339    #[must_use]
340    pub fn spb2io(&mut self) -> SPB2IO_W<2> {
341        SPB2IO_W::new(self)
342    }
343    #[doc = "Bit 4 - RXD invert bit"]
344    #[inline(always)]
345    #[must_use]
346    pub fn rinv(&mut self) -> RINV_W<4> {
347        RINV_W::new(self)
348    }
349    #[doc = "Bit 5 - TXD invert bit"]
350    #[inline(always)]
351    #[must_use]
352    pub fn tinv(&mut self) -> TINV_W<5> {
353        TINV_W::new(self)
354    }
355    #[doc = "Bit 6 - Adjust receive sampling timing enable"]
356    #[inline(always)]
357    #[must_use]
358    pub fn asen(&mut self) -> ASEN_W<6> {
359        ASEN_W::new(self)
360    }
361    #[doc = "Bit 7 - Adjust transmit timing enable"]
362    #[inline(always)]
363    #[must_use]
364    pub fn aten(&mut self) -> ATEN_W<7> {
365        ATEN_W::new(self)
366    }
367    #[doc = "Writes raw bits to the register."]
368    #[inline(always)]
369    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
370        self.0.bits(bits);
371        self
372    }
373}
374#[doc = "Serial Port Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sptr](index.html) module"]
375pub struct SPTR_SPEC;
376impl crate::RegisterSpec for SPTR_SPEC {
377    type Ux = u8;
378}
379#[doc = "`read()` method returns [sptr::R](R) reader structure"]
380impl crate::Readable for SPTR_SPEC {
381    type Reader = R;
382}
383#[doc = "`write(|w| ..)` method takes [sptr::W](W) writer structure"]
384impl crate::Writable for SPTR_SPEC {
385    type Writer = W;
386    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
387    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
388}
389#[doc = "`reset()` method sets SPTR to value 0x03"]
390impl crate::Resettable for SPTR_SPEC {
391    const RESET_VALUE: Self::Ux = 0x03;
392}
ra6e1/sci2/sptr.rs

ra6e1/sci2/
sptr.rs
