1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Quad Serial Peripheral Interface"]
28unsafe impl ::core::marker::Send for super::Qspi {}
29unsafe impl ::core::marker::Sync for super::Qspi {}
30impl super::Qspi {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Transfer Mode Control Register"]
38 #[inline(always)]
39 pub const fn sfmsmd(
40 &self,
41 ) -> &'static crate::common::Reg<self::Sfmsmd_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Sfmsmd_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "Chip Selection Control Register"]
50 #[inline(always)]
51 pub const fn sfmssc(
52 &self,
53 ) -> &'static crate::common::Reg<self::Sfmssc_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Sfmssc_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(4usize),
57 )
58 }
59 }
60
61 #[doc = "Clock Control Register"]
62 #[inline(always)]
63 pub const fn sfmskc(
64 &self,
65 ) -> &'static crate::common::Reg<self::Sfmskc_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Sfmskc_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(8usize),
69 )
70 }
71 }
72
73 #[doc = "Status Register"]
74 #[inline(always)]
75 pub const fn sfmsst(&self) -> &'static crate::common::Reg<self::Sfmsst_SPEC, crate::common::R> {
76 unsafe {
77 crate::common::Reg::<self::Sfmsst_SPEC, crate::common::R>::from_ptr(
78 self._svd2pac_as_ptr().add(12usize),
79 )
80 }
81 }
82
83 #[doc = "Communication Port Register"]
84 #[inline(always)]
85 pub const fn sfmcom(
86 &self,
87 ) -> &'static crate::common::Reg<self::Sfmcom_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Sfmcom_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(16usize),
91 )
92 }
93 }
94
95 #[doc = "Communication Mode Control Register"]
96 #[inline(always)]
97 pub const fn sfmcmd(
98 &self,
99 ) -> &'static crate::common::Reg<self::Sfmcmd_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Sfmcmd_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(20usize),
103 )
104 }
105 }
106
107 #[doc = "Communication Status Register"]
108 #[inline(always)]
109 pub const fn sfmcst(
110 &self,
111 ) -> &'static crate::common::Reg<self::Sfmcst_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Sfmcst_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(24usize),
115 )
116 }
117 }
118
119 #[doc = "Instruction Code Register"]
120 #[inline(always)]
121 pub const fn sfmsic(
122 &self,
123 ) -> &'static crate::common::Reg<self::Sfmsic_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Sfmsic_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(32usize),
127 )
128 }
129 }
130
131 #[doc = "Address Mode Control Register"]
132 #[inline(always)]
133 pub const fn sfmsac(
134 &self,
135 ) -> &'static crate::common::Reg<self::Sfmsac_SPEC, crate::common::RW> {
136 unsafe {
137 crate::common::Reg::<self::Sfmsac_SPEC, crate::common::RW>::from_ptr(
138 self._svd2pac_as_ptr().add(36usize),
139 )
140 }
141 }
142
143 #[doc = "Dummy Cycle Control Register"]
144 #[inline(always)]
145 pub const fn sfmsdc(
146 &self,
147 ) -> &'static crate::common::Reg<self::Sfmsdc_SPEC, crate::common::RW> {
148 unsafe {
149 crate::common::Reg::<self::Sfmsdc_SPEC, crate::common::RW>::from_ptr(
150 self._svd2pac_as_ptr().add(40usize),
151 )
152 }
153 }
154
155 #[doc = "SPI Protocol Control Register"]
156 #[inline(always)]
157 pub const fn sfmspc(
158 &self,
159 ) -> &'static crate::common::Reg<self::Sfmspc_SPEC, crate::common::RW> {
160 unsafe {
161 crate::common::Reg::<self::Sfmspc_SPEC, crate::common::RW>::from_ptr(
162 self._svd2pac_as_ptr().add(48usize),
163 )
164 }
165 }
166
167 #[doc = "Port Control Register"]
168 #[inline(always)]
169 pub const fn sfmpmd(
170 &self,
171 ) -> &'static crate::common::Reg<self::Sfmpmd_SPEC, crate::common::RW> {
172 unsafe {
173 crate::common::Reg::<self::Sfmpmd_SPEC, crate::common::RW>::from_ptr(
174 self._svd2pac_as_ptr().add(52usize),
175 )
176 }
177 }
178
179 #[doc = "External QSPI Address Register"]
180 #[inline(always)]
181 pub const fn sfmcnt1(
182 &self,
183 ) -> &'static crate::common::Reg<self::Sfmcnt1_SPEC, crate::common::RW> {
184 unsafe {
185 crate::common::Reg::<self::Sfmcnt1_SPEC, crate::common::RW>::from_ptr(
186 self._svd2pac_as_ptr().add(2052usize),
187 )
188 }
189 }
190}
191#[doc(hidden)]
192#[derive(Copy, Clone, Eq, PartialEq)]
193pub struct Sfmsmd_SPEC;
194impl crate::sealed::RegSpec for Sfmsmd_SPEC {
195 type DataType = u32;
196}
197
198#[doc = "Transfer Mode Control Register"]
199pub type Sfmsmd = crate::RegValueT<Sfmsmd_SPEC>;
200
201impl Sfmsmd {
202 #[doc = "Serial interface read mode select"]
203 #[inline(always)]
204 pub fn sfmrm(
205 self,
206 ) -> crate::common::RegisterField<
207 0,
208 0x7,
209 1,
210 0,
211 sfmsmd::Sfmrm,
212 sfmsmd::Sfmrm,
213 Sfmsmd_SPEC,
214 crate::common::RW,
215 > {
216 crate::common::RegisterField::<
217 0,
218 0x7,
219 1,
220 0,
221 sfmsmd::Sfmrm,
222 sfmsmd::Sfmrm,
223 Sfmsmd_SPEC,
224 crate::common::RW,
225 >::from_register(self, 0)
226 }
227
228 #[doc = "QSSL extension function select after SPI bus access"]
229 #[inline(always)]
230 pub fn sfmse(
231 self,
232 ) -> crate::common::RegisterField<
233 4,
234 0x3,
235 1,
236 0,
237 sfmsmd::Sfmse,
238 sfmsmd::Sfmse,
239 Sfmsmd_SPEC,
240 crate::common::RW,
241 > {
242 crate::common::RegisterField::<
243 4,
244 0x3,
245 1,
246 0,
247 sfmsmd::Sfmse,
248 sfmsmd::Sfmse,
249 Sfmsmd_SPEC,
250 crate::common::RW,
251 >::from_register(self, 0)
252 }
253
254 #[doc = "Prefetch function select"]
255 #[inline(always)]
256 pub fn sfmpfe(
257 self,
258 ) -> crate::common::RegisterField<
259 6,
260 0x1,
261 1,
262 0,
263 sfmsmd::Sfmpfe,
264 sfmsmd::Sfmpfe,
265 Sfmsmd_SPEC,
266 crate::common::RW,
267 > {
268 crate::common::RegisterField::<
269 6,
270 0x1,
271 1,
272 0,
273 sfmsmd::Sfmpfe,
274 sfmsmd::Sfmpfe,
275 Sfmsmd_SPEC,
276 crate::common::RW,
277 >::from_register(self, 0)
278 }
279
280 #[doc = "Function select for stopping prefetch at locations other than on byte boundaries"]
281 #[inline(always)]
282 pub fn sfmpae(
283 self,
284 ) -> crate::common::RegisterField<
285 7,
286 0x1,
287 1,
288 0,
289 sfmsmd::Sfmpae,
290 sfmsmd::Sfmpae,
291 Sfmsmd_SPEC,
292 crate::common::RW,
293 > {
294 crate::common::RegisterField::<
295 7,
296 0x1,
297 1,
298 0,
299 sfmsmd::Sfmpae,
300 sfmsmd::Sfmpae,
301 Sfmsmd_SPEC,
302 crate::common::RW,
303 >::from_register(self, 0)
304 }
305
306 #[doc = "SPI mode select."]
307 #[inline(always)]
308 pub fn sfmmd3(
309 self,
310 ) -> crate::common::RegisterField<
311 8,
312 0x1,
313 1,
314 0,
315 sfmsmd::Sfmmd3,
316 sfmsmd::Sfmmd3,
317 Sfmsmd_SPEC,
318 crate::common::RW,
319 > {
320 crate::common::RegisterField::<
321 8,
322 0x1,
323 1,
324 0,
325 sfmsmd::Sfmmd3,
326 sfmsmd::Sfmmd3,
327 Sfmsmd_SPEC,
328 crate::common::RW,
329 >::from_register(self, 0)
330 }
331
332 #[doc = "Extension select for the I/O buffer output enable signal for the serial interface"]
333 #[inline(always)]
334 pub fn sfmoex(
335 self,
336 ) -> crate::common::RegisterField<
337 9,
338 0x1,
339 1,
340 0,
341 sfmsmd::Sfmoex,
342 sfmsmd::Sfmoex,
343 Sfmsmd_SPEC,
344 crate::common::RW,
345 > {
346 crate::common::RegisterField::<
347 9,
348 0x1,
349 1,
350 0,
351 sfmsmd::Sfmoex,
352 sfmsmd::Sfmoex,
353 Sfmsmd_SPEC,
354 crate::common::RW,
355 >::from_register(self, 0)
356 }
357
358 #[doc = "Hold time adjustment for serial transmission"]
359 #[inline(always)]
360 pub fn sfmohw(
361 self,
362 ) -> crate::common::RegisterField<
363 10,
364 0x1,
365 1,
366 0,
367 sfmsmd::Sfmohw,
368 sfmsmd::Sfmohw,
369 Sfmsmd_SPEC,
370 crate::common::RW,
371 > {
372 crate::common::RegisterField::<
373 10,
374 0x1,
375 1,
376 0,
377 sfmsmd::Sfmohw,
378 sfmsmd::Sfmohw,
379 Sfmsmd_SPEC,
380 crate::common::RW,
381 >::from_register(self, 0)
382 }
383
384 #[doc = "Setup time adjustment for serial transmission"]
385 #[inline(always)]
386 pub fn sfmosw(
387 self,
388 ) -> crate::common::RegisterField<
389 11,
390 0x1,
391 1,
392 0,
393 sfmsmd::Sfmosw,
394 sfmsmd::Sfmosw,
395 Sfmsmd_SPEC,
396 crate::common::RW,
397 > {
398 crate::common::RegisterField::<
399 11,
400 0x1,
401 1,
402 0,
403 sfmsmd::Sfmosw,
404 sfmsmd::Sfmosw,
405 Sfmsmd_SPEC,
406 crate::common::RW,
407 >::from_register(self, 0)
408 }
409
410 #[doc = "Read instruction code select"]
411 #[inline(always)]
412 pub fn sfmcce(
413 self,
414 ) -> crate::common::RegisterField<
415 15,
416 0x1,
417 1,
418 0,
419 sfmsmd::Sfmcce,
420 sfmsmd::Sfmcce,
421 Sfmsmd_SPEC,
422 crate::common::RW,
423 > {
424 crate::common::RegisterField::<
425 15,
426 0x1,
427 1,
428 0,
429 sfmsmd::Sfmcce,
430 sfmsmd::Sfmcce,
431 Sfmsmd_SPEC,
432 crate::common::RW,
433 >::from_register(self, 0)
434 }
435}
436impl ::core::default::Default for Sfmsmd {
437 #[inline(always)]
438 fn default() -> Sfmsmd {
439 <crate::RegValueT<Sfmsmd_SPEC> as RegisterValue<_>>::new(0)
440 }
441}
442pub mod sfmsmd {
443
444 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
445 pub struct Sfmrm_SPEC;
446 pub type Sfmrm = crate::EnumBitfieldStruct<u8, Sfmrm_SPEC>;
447 impl Sfmrm {
448 #[doc = "Standard Read"]
449 pub const _000: Self = Self::new(0);
450
451 #[doc = "Fast Read"]
452 pub const _001: Self = Self::new(1);
453
454 #[doc = "Fast Read Dual Output"]
455 pub const _010: Self = Self::new(2);
456
457 #[doc = "Fast Read Dual I/O"]
458 pub const _011: Self = Self::new(3);
459
460 #[doc = "Fast Read Quad Output"]
461 pub const _100: Self = Self::new(4);
462
463 #[doc = "Fast Read Quad I/O"]
464 pub const _101: Self = Self::new(5);
465
466 #[doc = "Setting prohibited"]
467 pub const OTHERS: Self = Self::new(0);
468 }
469 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
470 pub struct Sfmse_SPEC;
471 pub type Sfmse = crate::EnumBitfieldStruct<u8, Sfmse_SPEC>;
472 impl Sfmse {
473 #[doc = "Do not extend QSSL"]
474 pub const _00: Self = Self::new(0);
475
476 #[doc = "Extend QSSL by 33 QSPCLK"]
477 pub const _01: Self = Self::new(1);
478
479 #[doc = "Extend QSSL by 129 QSPCLK"]
480 pub const _10: Self = Self::new(2);
481
482 #[doc = "Extend QSSL infinitely"]
483 pub const _11: Self = Self::new(3);
484 }
485 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
486 pub struct Sfmpfe_SPEC;
487 pub type Sfmpfe = crate::EnumBitfieldStruct<u8, Sfmpfe_SPEC>;
488 impl Sfmpfe {
489 #[doc = "Disable function"]
490 pub const _0: Self = Self::new(0);
491
492 #[doc = "Enable function"]
493 pub const _1: Self = Self::new(1);
494 }
495 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
496 pub struct Sfmpae_SPEC;
497 pub type Sfmpae = crate::EnumBitfieldStruct<u8, Sfmpae_SPEC>;
498 impl Sfmpae {
499 #[doc = "Disable function"]
500 pub const _0: Self = Self::new(0);
501
502 #[doc = "Enable function"]
503 pub const _1: Self = Self::new(1);
504 }
505 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
506 pub struct Sfmmd3_SPEC;
507 pub type Sfmmd3 = crate::EnumBitfieldStruct<u8, Sfmmd3_SPEC>;
508 impl Sfmmd3 {
509 #[doc = "SPI mode 0"]
510 pub const _0: Self = Self::new(0);
511
512 #[doc = "SPI mode 3"]
513 pub const _1: Self = Self::new(1);
514 }
515 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
516 pub struct Sfmoex_SPEC;
517 pub type Sfmoex = crate::EnumBitfieldStruct<u8, Sfmoex_SPEC>;
518 impl Sfmoex {
519 #[doc = "Do not extend"]
520 pub const _0: Self = Self::new(0);
521
522 #[doc = "Extend by 1 QSPCLK"]
523 pub const _1: Self = Self::new(1);
524 }
525 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
526 pub struct Sfmohw_SPEC;
527 pub type Sfmohw = crate::EnumBitfieldStruct<u8, Sfmohw_SPEC>;
528 impl Sfmohw {
529 #[doc = "Do not extend high-level width of QSPCLK during transmission"]
530 pub const _0: Self = Self::new(0);
531
532 #[doc = "Extend high-level width of QSPCLK by 1 PCLKA during transmission"]
533 pub const _1: Self = Self::new(1);
534 }
535 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
536 pub struct Sfmosw_SPEC;
537 pub type Sfmosw = crate::EnumBitfieldStruct<u8, Sfmosw_SPEC>;
538 impl Sfmosw {
539 #[doc = "Do not extend low-level width of QSPCLK during transmission"]
540 pub const _0: Self = Self::new(0);
541
542 #[doc = "Extend low-level width of QSPCLK by 1 PCLKA during transmission"]
543 pub const _1: Self = Self::new(1);
544 }
545 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
546 pub struct Sfmcce_SPEC;
547 pub type Sfmcce = crate::EnumBitfieldStruct<u8, Sfmcce_SPEC>;
548 impl Sfmcce {
549 #[doc = "Uses automatically generated SPI instruction code"]
550 pub const _0: Self = Self::new(0);
551
552 #[doc = "Use instruction code in the SFMSIC register"]
553 pub const _1: Self = Self::new(1);
554 }
555}
556#[doc(hidden)]
557#[derive(Copy, Clone, Eq, PartialEq)]
558pub struct Sfmssc_SPEC;
559impl crate::sealed::RegSpec for Sfmssc_SPEC {
560 type DataType = u32;
561}
562
563#[doc = "Chip Selection Control Register"]
564pub type Sfmssc = crate::RegValueT<Sfmssc_SPEC>;
565
566impl Sfmssc {
567 #[doc = "Minimum High-level Width Select for QSSL Signal"]
568 #[inline(always)]
569 pub fn sfmsw(
570 self,
571 ) -> crate::common::RegisterField<
572 0,
573 0xf,
574 1,
575 0,
576 sfmssc::Sfmsw,
577 sfmssc::Sfmsw,
578 Sfmssc_SPEC,
579 crate::common::RW,
580 > {
581 crate::common::RegisterField::<
582 0,
583 0xf,
584 1,
585 0,
586 sfmssc::Sfmsw,
587 sfmssc::Sfmsw,
588 Sfmssc_SPEC,
589 crate::common::RW,
590 >::from_register(self, 0)
591 }
592
593 #[doc = "QSSL Signal Hold Time"]
594 #[inline(always)]
595 pub fn sfmshd(
596 self,
597 ) -> crate::common::RegisterField<
598 4,
599 0x1,
600 1,
601 0,
602 sfmssc::Sfmshd,
603 sfmssc::Sfmshd,
604 Sfmssc_SPEC,
605 crate::common::RW,
606 > {
607 crate::common::RegisterField::<
608 4,
609 0x1,
610 1,
611 0,
612 sfmssc::Sfmshd,
613 sfmssc::Sfmshd,
614 Sfmssc_SPEC,
615 crate::common::RW,
616 >::from_register(self, 0)
617 }
618
619 #[doc = "QSSL Signal Setup Time"]
620 #[inline(always)]
621 pub fn sfmsld(
622 self,
623 ) -> crate::common::RegisterField<
624 5,
625 0x1,
626 1,
627 0,
628 sfmssc::Sfmsld,
629 sfmssc::Sfmsld,
630 Sfmssc_SPEC,
631 crate::common::RW,
632 > {
633 crate::common::RegisterField::<
634 5,
635 0x1,
636 1,
637 0,
638 sfmssc::Sfmsld,
639 sfmssc::Sfmsld,
640 Sfmssc_SPEC,
641 crate::common::RW,
642 >::from_register(self, 0)
643 }
644}
645impl ::core::default::Default for Sfmssc {
646 #[inline(always)]
647 fn default() -> Sfmssc {
648 <crate::RegValueT<Sfmssc_SPEC> as RegisterValue<_>>::new(55)
649 }
650}
651pub mod sfmssc {
652
653 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
654 pub struct Sfmsw_SPEC;
655 pub type Sfmsw = crate::EnumBitfieldStruct<u8, Sfmsw_SPEC>;
656 impl Sfmsw {
657 #[doc = "1 QSPCLK"]
658 pub const _0_X_0: Self = Self::new(0);
659
660 #[doc = "2 QSPCLK"]
661 pub const _0_X_1: Self = Self::new(1);
662
663 #[doc = "3 QSPCLK"]
664 pub const _0_X_2: Self = Self::new(2);
665
666 #[doc = "4 QSPCLK"]
667 pub const _0_X_3: Self = Self::new(3);
668
669 #[doc = "5 QSPCLK"]
670 pub const _0_X_4: Self = Self::new(4);
671
672 #[doc = "6 QSPCLK"]
673 pub const _0_X_5: Self = Self::new(5);
674
675 #[doc = "7 QSPCLK"]
676 pub const _0_X_6: Self = Self::new(6);
677
678 #[doc = "8 QSPCLK"]
679 pub const _0_X_7: Self = Self::new(7);
680
681 #[doc = "9 QSPCLK"]
682 pub const _0_X_8: Self = Self::new(8);
683
684 #[doc = "10 QSPCLK"]
685 pub const _0_X_9: Self = Self::new(9);
686
687 #[doc = "11 QSPCLK"]
688 pub const _0_X_A: Self = Self::new(10);
689
690 #[doc = "12 QSPCLK"]
691 pub const _0_X_B: Self = Self::new(11);
692
693 #[doc = "13 QSPCLK"]
694 pub const _0_X_C: Self = Self::new(12);
695
696 #[doc = "14 QSPCLK"]
697 pub const _0_X_D: Self = Self::new(13);
698
699 #[doc = "15 QSPCLK"]
700 pub const _0_X_E: Self = Self::new(14);
701
702 #[doc = "16 QSPCLK"]
703 pub const _0_X_F: Self = Self::new(15);
704 }
705 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
706 pub struct Sfmshd_SPEC;
707 pub type Sfmshd = crate::EnumBitfieldStruct<u8, Sfmshd_SPEC>;
708 impl Sfmshd {
709 #[doc = "QSSL outputs high after 0.5 QSPCLK cycles from the last rising edge of QSPCLK."]
710 pub const _0: Self = Self::new(0);
711
712 #[doc = "QSSL outputs high after 1.5 QSPCLK cycles from the last rising edge of QSPCLK."]
713 pub const _1: Self = Self::new(1);
714 }
715 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
716 pub struct Sfmsld_SPEC;
717 pub type Sfmsld = crate::EnumBitfieldStruct<u8, Sfmsld_SPEC>;
718 impl Sfmsld {
719 #[doc = "QSSL outputs low before 0.5 QSPCLK cycles from the first rising edge of QSPCLK."]
720 pub const _0: Self = Self::new(0);
721
722 #[doc = "QSSL outputs low before 1.5 QSPCLK cycles from the first rising edge of QSPCLK."]
723 pub const _1: Self = Self::new(1);
724 }
725}
726#[doc(hidden)]
727#[derive(Copy, Clone, Eq, PartialEq)]
728pub struct Sfmskc_SPEC;
729impl crate::sealed::RegSpec for Sfmskc_SPEC {
730 type DataType = u32;
731}
732
733#[doc = "Clock Control Register"]
734pub type Sfmskc = crate::RegValueT<Sfmskc_SPEC>;
735
736impl Sfmskc {
737 #[doc = "Serial interface reference cycle select. (Pay attention to irregularities.)"]
738 #[inline(always)]
739 pub fn sfmdv(
740 self,
741 ) -> crate::common::RegisterField<
742 0,
743 0x1f,
744 1,
745 0,
746 sfmskc::Sfmdv,
747 sfmskc::Sfmdv,
748 Sfmskc_SPEC,
749 crate::common::RW,
750 > {
751 crate::common::RegisterField::<
752 0,
753 0x1f,
754 1,
755 0,
756 sfmskc::Sfmdv,
757 sfmskc::Sfmdv,
758 Sfmskc_SPEC,
759 crate::common::RW,
760 >::from_register(self, 0)
761 }
762
763 #[doc = "Duty ratio correction function select for the QSPCLK signal when divided by an odd number"]
764 #[inline(always)]
765 pub fn sfmdty(
766 self,
767 ) -> crate::common::RegisterField<
768 5,
769 0x1,
770 1,
771 0,
772 sfmskc::Sfmdty,
773 sfmskc::Sfmdty,
774 Sfmskc_SPEC,
775 crate::common::RW,
776 > {
777 crate::common::RegisterField::<
778 5,
779 0x1,
780 1,
781 0,
782 sfmskc::Sfmdty,
783 sfmskc::Sfmdty,
784 Sfmskc_SPEC,
785 crate::common::RW,
786 >::from_register(self, 0)
787 }
788}
789impl ::core::default::Default for Sfmskc {
790 #[inline(always)]
791 fn default() -> Sfmskc {
792 <crate::RegValueT<Sfmskc_SPEC> as RegisterValue<_>>::new(8)
793 }
794}
795pub mod sfmskc {
796
797 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
798 pub struct Sfmdv_SPEC;
799 pub type Sfmdv = crate::EnumBitfieldStruct<u8, Sfmdv_SPEC>;
800 impl Sfmdv {
801 #[doc = "2 PCLKA"]
802 pub const _0_X_00: Self = Self::new(0);
803
804 #[doc = "3 PCLKA (divided by an odd number)"]
805 pub const _0_X_01: Self = Self::new(1);
806
807 #[doc = "4 PCLKA"]
808 pub const _0_X_02: Self = Self::new(2);
809
810 #[doc = "5 PCLKA (divided by an odd number)"]
811 pub const _0_X_03: Self = Self::new(3);
812
813 #[doc = "6 PCLKA"]
814 pub const _0_X_04: Self = Self::new(4);
815
816 #[doc = "7 PCLKA (divided by an odd number)"]
817 pub const _0_X_05: Self = Self::new(5);
818
819 #[doc = "8 PCLKA"]
820 pub const _0_X_06: Self = Self::new(6);
821
822 #[doc = "9 PCLKA (divided by an odd number)"]
823 pub const _0_X_07: Self = Self::new(7);
824
825 #[doc = "10 PCLKA"]
826 pub const _0_X_08: Self = Self::new(8);
827
828 #[doc = "11 PCLKA (divided by an odd number)"]
829 pub const _0_X_09: Self = Self::new(9);
830
831 #[doc = "12 PCLKA"]
832 pub const _0_X_0_A: Self = Self::new(10);
833
834 #[doc = "13 PCLKA (divided by an odd number)"]
835 pub const _0_X_0_B: Self = Self::new(11);
836
837 #[doc = "14 PCLKA"]
838 pub const _0_X_0_C: Self = Self::new(12);
839
840 #[doc = "15 PCLKA (divided by an odd number)"]
841 pub const _0_X_0_D: Self = Self::new(13);
842
843 #[doc = "16 PCLKA"]
844 pub const _0_X_0_E: Self = Self::new(14);
845
846 #[doc = "17 PCLKA (divided by an odd number)"]
847 pub const _0_X_0_F: Self = Self::new(15);
848
849 #[doc = "18 PCLKA"]
850 pub const _0_X_10: Self = Self::new(16);
851
852 #[doc = "20 PCLKA"]
853 pub const _0_X_11: Self = Self::new(17);
854
855 #[doc = "22 PCLKA"]
856 pub const _0_X_12: Self = Self::new(18);
857
858 #[doc = "24 PCLKA"]
859 pub const _0_X_13: Self = Self::new(19);
860
861 #[doc = "26 PCLKA"]
862 pub const _0_X_14: Self = Self::new(20);
863
864 #[doc = "28 PCLKA"]
865 pub const _0_X_15: Self = Self::new(21);
866
867 #[doc = "30 PCLKA"]
868 pub const _0_X_16: Self = Self::new(22);
869
870 #[doc = "32 PCLKA"]
871 pub const _0_X_17: Self = Self::new(23);
872
873 #[doc = "34 PCLKA"]
874 pub const _0_X_18: Self = Self::new(24);
875
876 #[doc = "36 PCLKA"]
877 pub const _0_X_19: Self = Self::new(25);
878
879 #[doc = "38 PCLKA"]
880 pub const _0_X_1_A: Self = Self::new(26);
881
882 #[doc = "40 PCLKA"]
883 pub const _0_X_1_B: Self = Self::new(27);
884
885 #[doc = "42 PCLKA"]
886 pub const _0_X_1_C: Self = Self::new(28);
887
888 #[doc = "44 PCLKA"]
889 pub const _0_X_1_D: Self = Self::new(29);
890
891 #[doc = "46 PCLKA"]
892 pub const _0_X_1_E: Self = Self::new(30);
893
894 #[doc = "48 PCLKA"]
895 pub const _0_X_1_F: Self = Self::new(31);
896 }
897 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
898 pub struct Sfmdty_SPEC;
899 pub type Sfmdty = crate::EnumBitfieldStruct<u8, Sfmdty_SPEC>;
900 impl Sfmdty {
901 #[doc = "Make no correction"]
902 pub const _0: Self = Self::new(0);
903
904 #[doc = "Make correction"]
905 pub const _1: Self = Self::new(1);
906 }
907}
908#[doc(hidden)]
909#[derive(Copy, Clone, Eq, PartialEq)]
910pub struct Sfmsst_SPEC;
911impl crate::sealed::RegSpec for Sfmsst_SPEC {
912 type DataType = u32;
913}
914
915#[doc = "Status Register"]
916pub type Sfmsst = crate::RegValueT<Sfmsst_SPEC>;
917
918impl Sfmsst {
919 #[doc = "Number of bytes of prefetched data"]
920 #[inline(always)]
921 pub fn pfcnt(
922 self,
923 ) -> crate::common::RegisterField<
924 0,
925 0x1f,
926 1,
927 0,
928 sfmsst::Pfcnt,
929 sfmsst::Pfcnt,
930 Sfmsst_SPEC,
931 crate::common::R,
932 > {
933 crate::common::RegisterField::<
934 0,
935 0x1f,
936 1,
937 0,
938 sfmsst::Pfcnt,
939 sfmsst::Pfcnt,
940 Sfmsst_SPEC,
941 crate::common::R,
942 >::from_register(self, 0)
943 }
944
945 #[doc = "Prefetch buffer state"]
946 #[inline(always)]
947 pub fn pfful(
948 self,
949 ) -> crate::common::RegisterField<
950 6,
951 0x1,
952 1,
953 0,
954 sfmsst::Pfful,
955 sfmsst::Pfful,
956 Sfmsst_SPEC,
957 crate::common::R,
958 > {
959 crate::common::RegisterField::<
960 6,
961 0x1,
962 1,
963 0,
964 sfmsst::Pfful,
965 sfmsst::Pfful,
966 Sfmsst_SPEC,
967 crate::common::R,
968 >::from_register(self, 0)
969 }
970
971 #[doc = "Prefetch function operating state"]
972 #[inline(always)]
973 pub fn pfoff(
974 self,
975 ) -> crate::common::RegisterField<
976 7,
977 0x1,
978 1,
979 0,
980 sfmsst::Pfoff,
981 sfmsst::Pfoff,
982 Sfmsst_SPEC,
983 crate::common::R,
984 > {
985 crate::common::RegisterField::<
986 7,
987 0x1,
988 1,
989 0,
990 sfmsst::Pfoff,
991 sfmsst::Pfoff,
992 Sfmsst_SPEC,
993 crate::common::R,
994 >::from_register(self, 0)
995 }
996}
997impl ::core::default::Default for Sfmsst {
998 #[inline(always)]
999 fn default() -> Sfmsst {
1000 <crate::RegValueT<Sfmsst_SPEC> as RegisterValue<_>>::new(128)
1001 }
1002}
1003pub mod sfmsst {
1004
1005 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1006 pub struct Pfcnt_SPEC;
1007 pub type Pfcnt = crate::EnumBitfieldStruct<u8, Pfcnt_SPEC>;
1008 impl Pfcnt {
1009 #[doc = "0 byte"]
1010 pub const _0_X_00: Self = Self::new(0);
1011
1012 #[doc = "1 byte"]
1013 pub const _0_X_01: Self = Self::new(1);
1014
1015 #[doc = "2 bytes"]
1016 pub const _0_X_02: Self = Self::new(2);
1017
1018 #[doc = "3 bytes"]
1019 pub const _0_X_03: Self = Self::new(3);
1020
1021 #[doc = "4 bytes"]
1022 pub const _0_X_04: Self = Self::new(4);
1023
1024 #[doc = "5 bytes"]
1025 pub const _0_X_05: Self = Self::new(5);
1026
1027 #[doc = "6 bytes"]
1028 pub const _0_X_06: Self = Self::new(6);
1029
1030 #[doc = "7 bytes"]
1031 pub const _0_X_07: Self = Self::new(7);
1032
1033 #[doc = "8 bytes"]
1034 pub const _0_X_08: Self = Self::new(8);
1035
1036 #[doc = "9 bytes"]
1037 pub const _0_X_09: Self = Self::new(9);
1038
1039 #[doc = "10 bytes"]
1040 pub const _0_X_0_A: Self = Self::new(10);
1041
1042 #[doc = "11 bytes"]
1043 pub const _0_X_0_B: Self = Self::new(11);
1044
1045 #[doc = "12 bytes"]
1046 pub const _0_X_0_C: Self = Self::new(12);
1047
1048 #[doc = "13 bytes"]
1049 pub const _0_X_0_D: Self = Self::new(13);
1050
1051 #[doc = "14 bytes"]
1052 pub const _0_X_0_E: Self = Self::new(14);
1053
1054 #[doc = "15 bytes"]
1055 pub const _0_X_0_F: Self = Self::new(15);
1056
1057 #[doc = "16 bytes"]
1058 pub const _0_X_10: Self = Self::new(16);
1059
1060 #[doc = "17 bytes"]
1061 pub const _0_X_11: Self = Self::new(17);
1062
1063 #[doc = "18 bytes"]
1064 pub const _0_X_12: Self = Self::new(18);
1065
1066 #[doc = "Reserved"]
1067 pub const OTHERS: Self = Self::new(0);
1068 }
1069 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1070 pub struct Pfful_SPEC;
1071 pub type Pfful = crate::EnumBitfieldStruct<u8, Pfful_SPEC>;
1072 impl Pfful {
1073 #[doc = "Prefetch buffer has free space"]
1074 pub const _0: Self = Self::new(0);
1075
1076 #[doc = "Prefetch buffer is full"]
1077 pub const _1: Self = Self::new(1);
1078 }
1079 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1080 pub struct Pfoff_SPEC;
1081 pub type Pfoff = crate::EnumBitfieldStruct<u8, Pfoff_SPEC>;
1082 impl Pfoff {
1083 #[doc = "Prefetch function operating"]
1084 pub const _0: Self = Self::new(0);
1085
1086 #[doc = "Prefetch function not enabled or not operating"]
1087 pub const _1: Self = Self::new(1);
1088 }
1089}
1090#[doc(hidden)]
1091#[derive(Copy, Clone, Eq, PartialEq)]
1092pub struct Sfmcom_SPEC;
1093impl crate::sealed::RegSpec for Sfmcom_SPEC {
1094 type DataType = u32;
1095}
1096
1097#[doc = "Communication Port Register"]
1098pub type Sfmcom = crate::RegValueT<Sfmcom_SPEC>;
1099
1100impl Sfmcom {
1101 #[doc = "Port for direct communication with the SPI bus"]
1102 #[inline(always)]
1103 pub fn sfmd(
1104 self,
1105 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmcom_SPEC, crate::common::RW> {
1106 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmcom_SPEC,crate::common::RW>::from_register(self,0)
1107 }
1108}
1109impl ::core::default::Default for Sfmcom {
1110 #[inline(always)]
1111 fn default() -> Sfmcom {
1112 <crate::RegValueT<Sfmcom_SPEC> as RegisterValue<_>>::new(0)
1113 }
1114}
1115
1116#[doc(hidden)]
1117#[derive(Copy, Clone, Eq, PartialEq)]
1118pub struct Sfmcmd_SPEC;
1119impl crate::sealed::RegSpec for Sfmcmd_SPEC {
1120 type DataType = u32;
1121}
1122
1123#[doc = "Communication Mode Control Register"]
1124pub type Sfmcmd = crate::RegValueT<Sfmcmd_SPEC>;
1125
1126impl Sfmcmd {
1127 #[doc = "Mode select for communication with the SPI bus"]
1128 #[inline(always)]
1129 pub fn dcom(
1130 self,
1131 ) -> crate::common::RegisterField<
1132 0,
1133 0x1,
1134 1,
1135 0,
1136 sfmcmd::Dcom,
1137 sfmcmd::Dcom,
1138 Sfmcmd_SPEC,
1139 crate::common::RW,
1140 > {
1141 crate::common::RegisterField::<
1142 0,
1143 0x1,
1144 1,
1145 0,
1146 sfmcmd::Dcom,
1147 sfmcmd::Dcom,
1148 Sfmcmd_SPEC,
1149 crate::common::RW,
1150 >::from_register(self, 0)
1151 }
1152}
1153impl ::core::default::Default for Sfmcmd {
1154 #[inline(always)]
1155 fn default() -> Sfmcmd {
1156 <crate::RegValueT<Sfmcmd_SPEC> as RegisterValue<_>>::new(0)
1157 }
1158}
1159pub mod sfmcmd {
1160
1161 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1162 pub struct Dcom_SPEC;
1163 pub type Dcom = crate::EnumBitfieldStruct<u8, Dcom_SPEC>;
1164 impl Dcom {
1165 #[doc = "ROM access mode"]
1166 pub const _0: Self = Self::new(0);
1167
1168 #[doc = "Direct communication mode"]
1169 pub const _1: Self = Self::new(1);
1170 }
1171}
1172#[doc(hidden)]
1173#[derive(Copy, Clone, Eq, PartialEq)]
1174pub struct Sfmcst_SPEC;
1175impl crate::sealed::RegSpec for Sfmcst_SPEC {
1176 type DataType = u32;
1177}
1178
1179#[doc = "Communication Status Register"]
1180pub type Sfmcst = crate::RegValueT<Sfmcst_SPEC>;
1181
1182impl Sfmcst {
1183 #[doc = "SPI bus cycle completion state in direct communication"]
1184 #[inline(always)]
1185 pub fn combsy(
1186 self,
1187 ) -> crate::common::RegisterField<
1188 0,
1189 0x1,
1190 1,
1191 0,
1192 sfmcst::Combsy,
1193 sfmcst::Combsy,
1194 Sfmcst_SPEC,
1195 crate::common::R,
1196 > {
1197 crate::common::RegisterField::<
1198 0,
1199 0x1,
1200 1,
1201 0,
1202 sfmcst::Combsy,
1203 sfmcst::Combsy,
1204 Sfmcst_SPEC,
1205 crate::common::R,
1206 >::from_register(self, 0)
1207 }
1208
1209 #[doc = "ROM access detection status in direct communication mode"]
1210 #[inline(always)]
1211 pub fn eromr(
1212 self,
1213 ) -> crate::common::RegisterField<
1214 7,
1215 0x1,
1216 1,
1217 0,
1218 sfmcst::Eromr,
1219 sfmcst::Eromr,
1220 Sfmcst_SPEC,
1221 crate::common::RW,
1222 > {
1223 crate::common::RegisterField::<
1224 7,
1225 0x1,
1226 1,
1227 0,
1228 sfmcst::Eromr,
1229 sfmcst::Eromr,
1230 Sfmcst_SPEC,
1231 crate::common::RW,
1232 >::from_register(self, 0)
1233 }
1234}
1235impl ::core::default::Default for Sfmcst {
1236 #[inline(always)]
1237 fn default() -> Sfmcst {
1238 <crate::RegValueT<Sfmcst_SPEC> as RegisterValue<_>>::new(0)
1239 }
1240}
1241pub mod sfmcst {
1242
1243 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1244 pub struct Combsy_SPEC;
1245 pub type Combsy = crate::EnumBitfieldStruct<u8, Combsy_SPEC>;
1246 impl Combsy {
1247 #[doc = "No serial transfer being processed"]
1248 pub const _0: Self = Self::new(0);
1249
1250 #[doc = "Serial transfer being processed"]
1251 pub const _1: Self = Self::new(1);
1252 }
1253 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1254 pub struct Eromr_SPEC;
1255 pub type Eromr = crate::EnumBitfieldStruct<u8, Eromr_SPEC>;
1256 impl Eromr {
1257 #[doc = "ROM access not detected"]
1258 pub const _0: Self = Self::new(0);
1259
1260 #[doc = "ROM access detected"]
1261 pub const _1: Self = Self::new(1);
1262 }
1263}
1264#[doc(hidden)]
1265#[derive(Copy, Clone, Eq, PartialEq)]
1266pub struct Sfmsic_SPEC;
1267impl crate::sealed::RegSpec for Sfmsic_SPEC {
1268 type DataType = u32;
1269}
1270
1271#[doc = "Instruction Code Register"]
1272pub type Sfmsic = crate::RegValueT<Sfmsic_SPEC>;
1273
1274impl Sfmsic {
1275 #[doc = "Serial flash instruction code to substitute"]
1276 #[inline(always)]
1277 pub fn sfmcic(
1278 self,
1279 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sfmsic_SPEC, crate::common::RW> {
1280 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sfmsic_SPEC,crate::common::RW>::from_register(self,0)
1281 }
1282}
1283impl ::core::default::Default for Sfmsic {
1284 #[inline(always)]
1285 fn default() -> Sfmsic {
1286 <crate::RegValueT<Sfmsic_SPEC> as RegisterValue<_>>::new(0)
1287 }
1288}
1289
1290#[doc(hidden)]
1291#[derive(Copy, Clone, Eq, PartialEq)]
1292pub struct Sfmsac_SPEC;
1293impl crate::sealed::RegSpec for Sfmsac_SPEC {
1294 type DataType = u32;
1295}
1296
1297#[doc = "Address Mode Control Register"]
1298pub type Sfmsac = crate::RegValueT<Sfmsac_SPEC>;
1299
1300impl Sfmsac {
1301 #[doc = "Number of address bytes select for the serial interface"]
1302 #[inline(always)]
1303 pub fn sfmas(
1304 self,
1305 ) -> crate::common::RegisterField<
1306 0,
1307 0x3,
1308 1,
1309 0,
1310 sfmsac::Sfmas,
1311 sfmsac::Sfmas,
1312 Sfmsac_SPEC,
1313 crate::common::RW,
1314 > {
1315 crate::common::RegisterField::<
1316 0,
1317 0x3,
1318 1,
1319 0,
1320 sfmsac::Sfmas,
1321 sfmsac::Sfmas,
1322 Sfmsac_SPEC,
1323 crate::common::RW,
1324 >::from_register(self, 0)
1325 }
1326
1327 #[doc = "Selection of instruction code automatically generated when the serial interface address width is 4 bytes"]
1328 #[inline(always)]
1329 pub fn sfm4bc(
1330 self,
1331 ) -> crate::common::RegisterField<
1332 4,
1333 0x1,
1334 1,
1335 0,
1336 sfmsac::Sfm4Bc,
1337 sfmsac::Sfm4Bc,
1338 Sfmsac_SPEC,
1339 crate::common::RW,
1340 > {
1341 crate::common::RegisterField::<
1342 4,
1343 0x1,
1344 1,
1345 0,
1346 sfmsac::Sfm4Bc,
1347 sfmsac::Sfm4Bc,
1348 Sfmsac_SPEC,
1349 crate::common::RW,
1350 >::from_register(self, 0)
1351 }
1352}
1353impl ::core::default::Default for Sfmsac {
1354 #[inline(always)]
1355 fn default() -> Sfmsac {
1356 <crate::RegValueT<Sfmsac_SPEC> as RegisterValue<_>>::new(2)
1357 }
1358}
1359pub mod sfmsac {
1360
1361 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1362 pub struct Sfmas_SPEC;
1363 pub type Sfmas = crate::EnumBitfieldStruct<u8, Sfmas_SPEC>;
1364 impl Sfmas {
1365 #[doc = "1 byte"]
1366 pub const _00: Self = Self::new(0);
1367
1368 #[doc = "2 bytes"]
1369 pub const _01: Self = Self::new(1);
1370
1371 #[doc = "3 bytes"]
1372 pub const _10: Self = Self::new(2);
1373
1374 #[doc = "4 bytes"]
1375 pub const _11: Self = Self::new(3);
1376 }
1377 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1378 pub struct Sfm4Bc_SPEC;
1379 pub type Sfm4Bc = crate::EnumBitfieldStruct<u8, Sfm4Bc_SPEC>;
1380 impl Sfm4Bc {
1381 #[doc = "Do not use 4-byte address read instruction code"]
1382 pub const _0: Self = Self::new(0);
1383
1384 #[doc = "Use 4-byte address read instruction code"]
1385 pub const _1: Self = Self::new(1);
1386 }
1387}
1388#[doc(hidden)]
1389#[derive(Copy, Clone, Eq, PartialEq)]
1390pub struct Sfmsdc_SPEC;
1391impl crate::sealed::RegSpec for Sfmsdc_SPEC {
1392 type DataType = u32;
1393}
1394
1395#[doc = "Dummy Cycle Control Register"]
1396pub type Sfmsdc = crate::RegValueT<Sfmsdc_SPEC>;
1397
1398impl Sfmsdc {
1399 #[doc = "Number of dummy cycles select for Fast Read instructions"]
1400 #[inline(always)]
1401 pub fn sfmdn(
1402 self,
1403 ) -> crate::common::RegisterField<
1404 0,
1405 0xf,
1406 1,
1407 0,
1408 sfmsdc::Sfmdn,
1409 sfmsdc::Sfmdn,
1410 Sfmsdc_SPEC,
1411 crate::common::RW,
1412 > {
1413 crate::common::RegisterField::<
1414 0,
1415 0xf,
1416 1,
1417 0,
1418 sfmsdc::Sfmdn,
1419 sfmsdc::Sfmdn,
1420 Sfmsdc_SPEC,
1421 crate::common::RW,
1422 >::from_register(self, 0)
1423 }
1424
1425 #[doc = "XIP mode status"]
1426 #[inline(always)]
1427 pub fn sfmxst(
1428 self,
1429 ) -> crate::common::RegisterField<
1430 6,
1431 0x1,
1432 1,
1433 0,
1434 sfmsdc::Sfmxst,
1435 sfmsdc::Sfmxst,
1436 Sfmsdc_SPEC,
1437 crate::common::R,
1438 > {
1439 crate::common::RegisterField::<
1440 6,
1441 0x1,
1442 1,
1443 0,
1444 sfmsdc::Sfmxst,
1445 sfmsdc::Sfmxst,
1446 Sfmsdc_SPEC,
1447 crate::common::R,
1448 >::from_register(self, 0)
1449 }
1450
1451 #[doc = "XIP mode permission"]
1452 #[inline(always)]
1453 pub fn sfmxen(
1454 self,
1455 ) -> crate::common::RegisterField<
1456 7,
1457 0x1,
1458 1,
1459 0,
1460 sfmsdc::Sfmxen,
1461 sfmsdc::Sfmxen,
1462 Sfmsdc_SPEC,
1463 crate::common::RW,
1464 > {
1465 crate::common::RegisterField::<
1466 7,
1467 0x1,
1468 1,
1469 0,
1470 sfmsdc::Sfmxen,
1471 sfmsdc::Sfmxen,
1472 Sfmsdc_SPEC,
1473 crate::common::RW,
1474 >::from_register(self, 0)
1475 }
1476
1477 #[doc = "Mode data for serial flash (Controls XIP mode.)"]
1478 #[inline(always)]
1479 pub fn sfmxd(
1480 self,
1481 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Sfmsdc_SPEC, crate::common::RW> {
1482 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Sfmsdc_SPEC,crate::common::RW>::from_register(self,0)
1483 }
1484}
1485impl ::core::default::Default for Sfmsdc {
1486 #[inline(always)]
1487 fn default() -> Sfmsdc {
1488 <crate::RegValueT<Sfmsdc_SPEC> as RegisterValue<_>>::new(65280)
1489 }
1490}
1491pub mod sfmsdc {
1492
1493 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1494 pub struct Sfmdn_SPEC;
1495 pub type Sfmdn = crate::EnumBitfieldStruct<u8, Sfmdn_SPEC>;
1496 impl Sfmdn {
1497 #[doc = "Default dummy cycles for each instruction: - Fast Read Quad I/O: 6 QSPCLK - Fast Read Quad Output: 8 QSPCLK - Fast Read Dual I/O: 4 QSPCLK - Fast Read Dual Output: 8 QSPCLK - Fast Read: 8 QSPCLK"]
1498 pub const _0_X_0: Self = Self::new(0);
1499
1500 #[doc = "3 QSPCLK"]
1501 pub const _0_X_1: Self = Self::new(1);
1502
1503 #[doc = "4 QSPCLK"]
1504 pub const _0_X_2: Self = Self::new(2);
1505
1506 #[doc = "5 QSPCLK"]
1507 pub const _0_X_3: Self = Self::new(3);
1508
1509 #[doc = "6 QSPCLK"]
1510 pub const _0_X_4: Self = Self::new(4);
1511
1512 #[doc = "7 QSPCLK"]
1513 pub const _0_X_5: Self = Self::new(5);
1514
1515 #[doc = "8 QSPCLK"]
1516 pub const _0_X_6: Self = Self::new(6);
1517
1518 #[doc = "9 QSPCLK"]
1519 pub const _0_X_7: Self = Self::new(7);
1520
1521 #[doc = "10 QSPCLK"]
1522 pub const _0_X_8: Self = Self::new(8);
1523
1524 #[doc = "11 QSPCLK"]
1525 pub const _0_X_9: Self = Self::new(9);
1526
1527 #[doc = "12 QSPCLK"]
1528 pub const _0_X_A: Self = Self::new(10);
1529
1530 #[doc = "13 QSPCLK"]
1531 pub const _0_X_B: Self = Self::new(11);
1532
1533 #[doc = "14 QSPCLK"]
1534 pub const _0_X_C: Self = Self::new(12);
1535
1536 #[doc = "15 QSPCLK"]
1537 pub const _0_X_D: Self = Self::new(13);
1538
1539 #[doc = "16 QSPCLK"]
1540 pub const _0_X_E: Self = Self::new(14);
1541
1542 #[doc = "17 QSPCLK"]
1543 pub const _0_X_F: Self = Self::new(15);
1544 }
1545 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1546 pub struct Sfmxst_SPEC;
1547 pub type Sfmxst = crate::EnumBitfieldStruct<u8, Sfmxst_SPEC>;
1548 impl Sfmxst {
1549 #[doc = "Normal (non-XIP) mode"]
1550 pub const _0: Self = Self::new(0);
1551
1552 #[doc = "XIP mode"]
1553 pub const _1: Self = Self::new(1);
1554 }
1555 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1556 pub struct Sfmxen_SPEC;
1557 pub type Sfmxen = crate::EnumBitfieldStruct<u8, Sfmxen_SPEC>;
1558 impl Sfmxen {
1559 #[doc = "Prohibit XIP mode"]
1560 pub const _0: Self = Self::new(0);
1561
1562 #[doc = "Permit XIP mode"]
1563 pub const _1: Self = Self::new(1);
1564 }
1565}
1566#[doc(hidden)]
1567#[derive(Copy, Clone, Eq, PartialEq)]
1568pub struct Sfmspc_SPEC;
1569impl crate::sealed::RegSpec for Sfmspc_SPEC {
1570 type DataType = u32;
1571}
1572
1573#[doc = "SPI Protocol Control Register"]
1574pub type Sfmspc = crate::RegValueT<Sfmspc_SPEC>;
1575
1576impl Sfmspc {
1577 #[doc = "SPI protocol select"]
1578 #[inline(always)]
1579 pub fn sfmspi(
1580 self,
1581 ) -> crate::common::RegisterField<
1582 0,
1583 0x3,
1584 1,
1585 0,
1586 sfmspc::Sfmspi,
1587 sfmspc::Sfmspi,
1588 Sfmspc_SPEC,
1589 crate::common::RW,
1590 > {
1591 crate::common::RegisterField::<
1592 0,
1593 0x3,
1594 1,
1595 0,
1596 sfmspc::Sfmspi,
1597 sfmspc::Sfmspi,
1598 Sfmspc_SPEC,
1599 crate::common::RW,
1600 >::from_register(self, 0)
1601 }
1602
1603 #[doc = "QSPCLK extended selection bit when switching I/O of QIOn pin"]
1604 #[inline(always)]
1605 pub fn sfmsde(
1606 self,
1607 ) -> crate::common::RegisterField<
1608 4,
1609 0x1,
1610 1,
1611 0,
1612 sfmspc::Sfmsde,
1613 sfmspc::Sfmsde,
1614 Sfmspc_SPEC,
1615 crate::common::RW,
1616 > {
1617 crate::common::RegisterField::<
1618 4,
1619 0x1,
1620 1,
1621 0,
1622 sfmspc::Sfmsde,
1623 sfmspc::Sfmsde,
1624 Sfmspc_SPEC,
1625 crate::common::RW,
1626 >::from_register(self, 0)
1627 }
1628}
1629impl ::core::default::Default for Sfmspc {
1630 #[inline(always)]
1631 fn default() -> Sfmspc {
1632 <crate::RegValueT<Sfmspc_SPEC> as RegisterValue<_>>::new(16)
1633 }
1634}
1635pub mod sfmspc {
1636
1637 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1638 pub struct Sfmspi_SPEC;
1639 pub type Sfmspi = crate::EnumBitfieldStruct<u8, Sfmspi_SPEC>;
1640 impl Sfmspi {
1641 #[doc = "Single SPI Protocol, Extended SPI protocol"]
1642 pub const _00: Self = Self::new(0);
1643
1644 #[doc = "Dual SPI protocol"]
1645 pub const _01: Self = Self::new(1);
1646
1647 #[doc = "Quad SPI protocol"]
1648 pub const _10: Self = Self::new(2);
1649
1650 #[doc = "Setting prohibited"]
1651 pub const _11: Self = Self::new(3);
1652 }
1653 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1654 pub struct Sfmsde_SPEC;
1655 pub type Sfmsde = crate::EnumBitfieldStruct<u8, Sfmsde_SPEC>;
1656 impl Sfmsde {
1657 #[doc = "No QSPCLK extension"]
1658 pub const _0: Self = Self::new(0);
1659
1660 #[doc = "QSPCLK expansion when switching I/O direction of QIOn pin"]
1661 pub const _1: Self = Self::new(1);
1662 }
1663}
1664#[doc(hidden)]
1665#[derive(Copy, Clone, Eq, PartialEq)]
1666pub struct Sfmpmd_SPEC;
1667impl crate::sealed::RegSpec for Sfmpmd_SPEC {
1668 type DataType = u32;
1669}
1670
1671#[doc = "Port Control Register"]
1672pub type Sfmpmd = crate::RegValueT<Sfmpmd_SPEC>;
1673
1674impl Sfmpmd {
1675 #[doc = "WP pin level specification"]
1676 #[inline(always)]
1677 pub fn sfmwpl(
1678 self,
1679 ) -> crate::common::RegisterField<
1680 2,
1681 0x1,
1682 1,
1683 0,
1684 sfmpmd::Sfmwpl,
1685 sfmpmd::Sfmwpl,
1686 Sfmpmd_SPEC,
1687 crate::common::RW,
1688 > {
1689 crate::common::RegisterField::<
1690 2,
1691 0x1,
1692 1,
1693 0,
1694 sfmpmd::Sfmwpl,
1695 sfmpmd::Sfmwpl,
1696 Sfmpmd_SPEC,
1697 crate::common::RW,
1698 >::from_register(self, 0)
1699 }
1700}
1701impl ::core::default::Default for Sfmpmd {
1702 #[inline(always)]
1703 fn default() -> Sfmpmd {
1704 <crate::RegValueT<Sfmpmd_SPEC> as RegisterValue<_>>::new(0)
1705 }
1706}
1707pub mod sfmpmd {
1708
1709 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1710 pub struct Sfmwpl_SPEC;
1711 pub type Sfmwpl = crate::EnumBitfieldStruct<u8, Sfmwpl_SPEC>;
1712 impl Sfmwpl {
1713 #[doc = "Low level"]
1714 pub const _0: Self = Self::new(0);
1715
1716 #[doc = "High level"]
1717 pub const _1: Self = Self::new(1);
1718 }
1719}
1720#[doc(hidden)]
1721#[derive(Copy, Clone, Eq, PartialEq)]
1722pub struct Sfmcnt1_SPEC;
1723impl crate::sealed::RegSpec for Sfmcnt1_SPEC {
1724 type DataType = u32;
1725}
1726
1727#[doc = "External QSPI Address Register"]
1728pub type Sfmcnt1 = crate::RegValueT<Sfmcnt1_SPEC>;
1729
1730impl Sfmcnt1 {
1731 #[doc = "Bank switching address"]
1732 #[inline(always)]
1733 pub fn qspi_ext(
1734 self,
1735 ) -> crate::common::RegisterField<26, 0x3f, 1, 0, u8, u8, Sfmcnt1_SPEC, crate::common::RW> {
1736 crate::common::RegisterField::<26,0x3f,1,0,u8,u8,Sfmcnt1_SPEC,crate::common::RW>::from_register(self,0)
1737 }
1738}
1739impl ::core::default::Default for Sfmcnt1 {
1740 #[inline(always)]
1741 fn default() -> Sfmcnt1 {
1742 <crate::RegValueT<Sfmcnt1_SPEC> as RegisterValue<_>>::new(0)
1743 }
1744}