ra6e1_pac/
agt0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.00, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:50:30 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Low Power Asynchronous General Purpose Timer 0"]
28unsafe impl ::core::marker::Send for super::Agt0 {}
29unsafe impl ::core::marker::Sync for super::Agt0 {}
30impl super::Agt0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "AGT Counter Register"]
38    #[inline(always)]
39    pub const fn agt(&self) -> &'static crate::common::Reg<self::Agt_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Agt_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "AGT Compare Match A Register"]
48    #[inline(always)]
49    pub const fn agtcma(
50        &self,
51    ) -> &'static crate::common::Reg<self::Agtcma_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Agtcma_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(2usize),
55            )
56        }
57    }
58
59    #[doc = "AGT Compare Match B Register"]
60    #[inline(always)]
61    pub const fn agtcmb(
62        &self,
63    ) -> &'static crate::common::Reg<self::Agtcmb_SPEC, crate::common::RW> {
64        unsafe {
65            crate::common::Reg::<self::Agtcmb_SPEC, crate::common::RW>::from_ptr(
66                self._svd2pac_as_ptr().add(4usize),
67            )
68        }
69    }
70
71    #[doc = "AGT Control Register"]
72    #[inline(always)]
73    pub const fn agtcr(&self) -> &'static crate::common::Reg<self::Agtcr_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::Agtcr_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(8usize),
77            )
78        }
79    }
80
81    #[doc = "AGT Mode Register 1"]
82    #[inline(always)]
83    pub const fn agtmr1(
84        &self,
85    ) -> &'static crate::common::Reg<self::Agtmr1_SPEC, crate::common::RW> {
86        unsafe {
87            crate::common::Reg::<self::Agtmr1_SPEC, crate::common::RW>::from_ptr(
88                self._svd2pac_as_ptr().add(9usize),
89            )
90        }
91    }
92
93    #[doc = "AGT Mode Register 2"]
94    #[inline(always)]
95    pub const fn agtmr2(
96        &self,
97    ) -> &'static crate::common::Reg<self::Agtmr2_SPEC, crate::common::RW> {
98        unsafe {
99            crate::common::Reg::<self::Agtmr2_SPEC, crate::common::RW>::from_ptr(
100                self._svd2pac_as_ptr().add(10usize),
101            )
102        }
103    }
104
105    #[doc = "AGT I/O Control Register"]
106    #[inline(always)]
107    pub const fn agtioc(
108        &self,
109    ) -> &'static crate::common::Reg<self::Agtioc_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Agtioc_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(12usize),
113            )
114        }
115    }
116
117    #[doc = "AGT Event Pin Select Register"]
118    #[inline(always)]
119    pub const fn agtisr(
120        &self,
121    ) -> &'static crate::common::Reg<self::Agtisr_SPEC, crate::common::RW> {
122        unsafe {
123            crate::common::Reg::<self::Agtisr_SPEC, crate::common::RW>::from_ptr(
124                self._svd2pac_as_ptr().add(13usize),
125            )
126        }
127    }
128
129    #[doc = "AGT Compare Match Function Select Register"]
130    #[inline(always)]
131    pub const fn agtcmsr(
132        &self,
133    ) -> &'static crate::common::Reg<self::Agtcmsr_SPEC, crate::common::RW> {
134        unsafe {
135            crate::common::Reg::<self::Agtcmsr_SPEC, crate::common::RW>::from_ptr(
136                self._svd2pac_as_ptr().add(14usize),
137            )
138        }
139    }
140
141    #[doc = "AGT Pin Select Register"]
142    #[inline(always)]
143    pub const fn agtiosel(
144        &self,
145    ) -> &'static crate::common::Reg<self::Agtiosel_SPEC, crate::common::RW> {
146        unsafe {
147            crate::common::Reg::<self::Agtiosel_SPEC, crate::common::RW>::from_ptr(
148                self._svd2pac_as_ptr().add(15usize),
149            )
150        }
151    }
152}
153#[doc(hidden)]
154#[derive(Copy, Clone, Eq, PartialEq)]
155pub struct Agt_SPEC;
156impl crate::sealed::RegSpec for Agt_SPEC {
157    type DataType = u16;
158}
159
160#[doc = "AGT Counter Register"]
161pub type Agt = crate::RegValueT<Agt_SPEC>;
162
163impl NoBitfieldReg<Agt_SPEC> for Agt {}
164impl ::core::default::Default for Agt {
165    #[inline(always)]
166    fn default() -> Agt {
167        <crate::RegValueT<Agt_SPEC> as RegisterValue<_>>::new(65535)
168    }
169}
170
171#[doc(hidden)]
172#[derive(Copy, Clone, Eq, PartialEq)]
173pub struct Agtcma_SPEC;
174impl crate::sealed::RegSpec for Agtcma_SPEC {
175    type DataType = u16;
176}
177
178#[doc = "AGT Compare Match A Register"]
179pub type Agtcma = crate::RegValueT<Agtcma_SPEC>;
180
181impl NoBitfieldReg<Agtcma_SPEC> for Agtcma {}
182impl ::core::default::Default for Agtcma {
183    #[inline(always)]
184    fn default() -> Agtcma {
185        <crate::RegValueT<Agtcma_SPEC> as RegisterValue<_>>::new(65535)
186    }
187}
188
189#[doc(hidden)]
190#[derive(Copy, Clone, Eq, PartialEq)]
191pub struct Agtcmb_SPEC;
192impl crate::sealed::RegSpec for Agtcmb_SPEC {
193    type DataType = u16;
194}
195
196#[doc = "AGT Compare Match B Register"]
197pub type Agtcmb = crate::RegValueT<Agtcmb_SPEC>;
198
199impl NoBitfieldReg<Agtcmb_SPEC> for Agtcmb {}
200impl ::core::default::Default for Agtcmb {
201    #[inline(always)]
202    fn default() -> Agtcmb {
203        <crate::RegValueT<Agtcmb_SPEC> as RegisterValue<_>>::new(65535)
204    }
205}
206
207#[doc(hidden)]
208#[derive(Copy, Clone, Eq, PartialEq)]
209pub struct Agtcr_SPEC;
210impl crate::sealed::RegSpec for Agtcr_SPEC {
211    type DataType = u8;
212}
213
214#[doc = "AGT Control Register"]
215pub type Agtcr = crate::RegValueT<Agtcr_SPEC>;
216
217impl Agtcr {
218    #[doc = "AGT Count Start"]
219    #[inline(always)]
220    pub fn tstart(
221        self,
222    ) -> crate::common::RegisterField<
223        0,
224        0x1,
225        1,
226        0,
227        agtcr::Tstart,
228        agtcr::Tstart,
229        Agtcr_SPEC,
230        crate::common::RW,
231    > {
232        crate::common::RegisterField::<
233            0,
234            0x1,
235            1,
236            0,
237            agtcr::Tstart,
238            agtcr::Tstart,
239            Agtcr_SPEC,
240            crate::common::RW,
241        >::from_register(self, 0)
242    }
243
244    #[doc = "AGT Count Status Flag"]
245    #[inline(always)]
246    pub fn tcstf(
247        self,
248    ) -> crate::common::RegisterField<
249        1,
250        0x1,
251        1,
252        0,
253        agtcr::Tcstf,
254        agtcr::Tcstf,
255        Agtcr_SPEC,
256        crate::common::R,
257    > {
258        crate::common::RegisterField::<
259            1,
260            0x1,
261            1,
262            0,
263            agtcr::Tcstf,
264            agtcr::Tcstf,
265            Agtcr_SPEC,
266            crate::common::R,
267        >::from_register(self, 0)
268    }
269
270    #[doc = "AGT Count Forced Stop"]
271    #[inline(always)]
272    pub fn tstop(
273        self,
274    ) -> crate::common::RegisterField<
275        2,
276        0x1,
277        1,
278        0,
279        agtcr::Tstop,
280        agtcr::Tstop,
281        Agtcr_SPEC,
282        crate::common::W,
283    > {
284        crate::common::RegisterField::<
285            2,
286            0x1,
287            1,
288            0,
289            agtcr::Tstop,
290            agtcr::Tstop,
291            Agtcr_SPEC,
292            crate::common::W,
293        >::from_register(self, 0)
294    }
295
296    #[doc = "Active Edge Judgment Flag"]
297    #[inline(always)]
298    pub fn tedgf(
299        self,
300    ) -> crate::common::RegisterField<
301        4,
302        0x1,
303        1,
304        0,
305        agtcr::Tedgf,
306        agtcr::Tedgf,
307        Agtcr_SPEC,
308        crate::common::RW,
309    > {
310        crate::common::RegisterField::<
311            4,
312            0x1,
313            1,
314            0,
315            agtcr::Tedgf,
316            agtcr::Tedgf,
317            Agtcr_SPEC,
318            crate::common::RW,
319        >::from_register(self, 0)
320    }
321
322    #[doc = "Underflow Flag"]
323    #[inline(always)]
324    pub fn tundf(
325        self,
326    ) -> crate::common::RegisterField<
327        5,
328        0x1,
329        1,
330        0,
331        agtcr::Tundf,
332        agtcr::Tundf,
333        Agtcr_SPEC,
334        crate::common::RW,
335    > {
336        crate::common::RegisterField::<
337            5,
338            0x1,
339            1,
340            0,
341            agtcr::Tundf,
342            agtcr::Tundf,
343            Agtcr_SPEC,
344            crate::common::RW,
345        >::from_register(self, 0)
346    }
347
348    #[doc = "Compare Match A Flag"]
349    #[inline(always)]
350    pub fn tcmaf(
351        self,
352    ) -> crate::common::RegisterField<
353        6,
354        0x1,
355        1,
356        0,
357        agtcr::Tcmaf,
358        agtcr::Tcmaf,
359        Agtcr_SPEC,
360        crate::common::RW,
361    > {
362        crate::common::RegisterField::<
363            6,
364            0x1,
365            1,
366            0,
367            agtcr::Tcmaf,
368            agtcr::Tcmaf,
369            Agtcr_SPEC,
370            crate::common::RW,
371        >::from_register(self, 0)
372    }
373
374    #[doc = "Compare Match B Flag"]
375    #[inline(always)]
376    pub fn tcmbf(
377        self,
378    ) -> crate::common::RegisterField<
379        7,
380        0x1,
381        1,
382        0,
383        agtcr::Tcmbf,
384        agtcr::Tcmbf,
385        Agtcr_SPEC,
386        crate::common::RW,
387    > {
388        crate::common::RegisterField::<
389            7,
390            0x1,
391            1,
392            0,
393            agtcr::Tcmbf,
394            agtcr::Tcmbf,
395            Agtcr_SPEC,
396            crate::common::RW,
397        >::from_register(self, 0)
398    }
399}
400impl ::core::default::Default for Agtcr {
401    #[inline(always)]
402    fn default() -> Agtcr {
403        <crate::RegValueT<Agtcr_SPEC> as RegisterValue<_>>::new(0)
404    }
405}
406pub mod agtcr {
407
408    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
409    pub struct Tstart_SPEC;
410    pub type Tstart = crate::EnumBitfieldStruct<u8, Tstart_SPEC>;
411    impl Tstart {
412        #[doc = "Count stops"]
413        pub const _0: Self = Self::new(0);
414
415        #[doc = "Count starts"]
416        pub const _1: Self = Self::new(1);
417    }
418    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
419    pub struct Tcstf_SPEC;
420    pub type Tcstf = crate::EnumBitfieldStruct<u8, Tcstf_SPEC>;
421    impl Tcstf {
422        #[doc = "Count stopped"]
423        pub const _0: Self = Self::new(0);
424
425        #[doc = "Count in progress"]
426        pub const _1: Self = Self::new(1);
427    }
428    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
429    pub struct Tstop_SPEC;
430    pub type Tstop = crate::EnumBitfieldStruct<u8, Tstop_SPEC>;
431    impl Tstop {
432        #[doc = "Writing is invalid"]
433        pub const _0: Self = Self::new(0);
434
435        #[doc = "The count is forcibly stopped"]
436        pub const _1: Self = Self::new(1);
437    }
438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
439    pub struct Tedgf_SPEC;
440    pub type Tedgf = crate::EnumBitfieldStruct<u8, Tedgf_SPEC>;
441    impl Tedgf {
442        #[doc = "No active edge received"]
443        pub const _0: Self = Self::new(0);
444
445        #[doc = "Active edge received"]
446        pub const _1: Self = Self::new(1);
447    }
448    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
449    pub struct Tundf_SPEC;
450    pub type Tundf = crate::EnumBitfieldStruct<u8, Tundf_SPEC>;
451    impl Tundf {
452        #[doc = "No underflow"]
453        pub const _0: Self = Self::new(0);
454
455        #[doc = "Underflow"]
456        pub const _1: Self = Self::new(1);
457    }
458    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
459    pub struct Tcmaf_SPEC;
460    pub type Tcmaf = crate::EnumBitfieldStruct<u8, Tcmaf_SPEC>;
461    impl Tcmaf {
462        #[doc = "No match"]
463        pub const _0: Self = Self::new(0);
464
465        #[doc = "Match"]
466        pub const _1: Self = Self::new(1);
467    }
468    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
469    pub struct Tcmbf_SPEC;
470    pub type Tcmbf = crate::EnumBitfieldStruct<u8, Tcmbf_SPEC>;
471    impl Tcmbf {
472        #[doc = "No match"]
473        pub const _0: Self = Self::new(0);
474
475        #[doc = "Match"]
476        pub const _1: Self = Self::new(1);
477    }
478}
479#[doc(hidden)]
480#[derive(Copy, Clone, Eq, PartialEq)]
481pub struct Agtmr1_SPEC;
482impl crate::sealed::RegSpec for Agtmr1_SPEC {
483    type DataType = u8;
484}
485
486#[doc = "AGT Mode Register 1"]
487pub type Agtmr1 = crate::RegValueT<Agtmr1_SPEC>;
488
489impl Agtmr1 {
490    #[doc = "Operating Mode"]
491    #[inline(always)]
492    pub fn tmod(
493        self,
494    ) -> crate::common::RegisterField<
495        0,
496        0x7,
497        1,
498        0,
499        agtmr1::Tmod,
500        agtmr1::Tmod,
501        Agtmr1_SPEC,
502        crate::common::RW,
503    > {
504        crate::common::RegisterField::<
505            0,
506            0x7,
507            1,
508            0,
509            agtmr1::Tmod,
510            agtmr1::Tmod,
511            Agtmr1_SPEC,
512            crate::common::RW,
513        >::from_register(self, 0)
514    }
515
516    #[doc = "Edge Polarity"]
517    #[inline(always)]
518    pub fn tedgpl(
519        self,
520    ) -> crate::common::RegisterField<
521        3,
522        0x1,
523        1,
524        0,
525        agtmr1::Tedgpl,
526        agtmr1::Tedgpl,
527        Agtmr1_SPEC,
528        crate::common::RW,
529    > {
530        crate::common::RegisterField::<
531            3,
532            0x1,
533            1,
534            0,
535            agtmr1::Tedgpl,
536            agtmr1::Tedgpl,
537            Agtmr1_SPEC,
538            crate::common::RW,
539        >::from_register(self, 0)
540    }
541
542    #[doc = "Count Source"]
543    #[inline(always)]
544    pub fn tck(
545        self,
546    ) -> crate::common::RegisterField<
547        4,
548        0x7,
549        1,
550        0,
551        agtmr1::Tck,
552        agtmr1::Tck,
553        Agtmr1_SPEC,
554        crate::common::RW,
555    > {
556        crate::common::RegisterField::<
557            4,
558            0x7,
559            1,
560            0,
561            agtmr1::Tck,
562            agtmr1::Tck,
563            Agtmr1_SPEC,
564            crate::common::RW,
565        >::from_register(self, 0)
566    }
567}
568impl ::core::default::Default for Agtmr1 {
569    #[inline(always)]
570    fn default() -> Agtmr1 {
571        <crate::RegValueT<Agtmr1_SPEC> as RegisterValue<_>>::new(0)
572    }
573}
574pub mod agtmr1 {
575
576    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
577    pub struct Tmod_SPEC;
578    pub type Tmod = crate::EnumBitfieldStruct<u8, Tmod_SPEC>;
579    impl Tmod {
580        #[doc = "Timer mode"]
581        pub const _000: Self = Self::new(0);
582
583        #[doc = "Pulse output mode"]
584        pub const _001: Self = Self::new(1);
585
586        #[doc = "Event counter mode"]
587        pub const _010: Self = Self::new(2);
588
589        #[doc = "Pulse width measurement mode"]
590        pub const _011: Self = Self::new(3);
591
592        #[doc = "Pulse period measurement mode"]
593        pub const _100: Self = Self::new(4);
594
595        #[doc = "Setting prohibited"]
596        pub const OTHERS: Self = Self::new(0);
597    }
598    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
599    pub struct Tedgpl_SPEC;
600    pub type Tedgpl = crate::EnumBitfieldStruct<u8, Tedgpl_SPEC>;
601    impl Tedgpl {
602        #[doc = "Single-edge"]
603        pub const _0: Self = Self::new(0);
604
605        #[doc = "Both-edge"]
606        pub const _1: Self = Self::new(1);
607    }
608    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
609    pub struct Tck_SPEC;
610    pub type Tck = crate::EnumBitfieldStruct<u8, Tck_SPEC>;
611    impl Tck {
612        #[doc = "PCLKB"]
613        pub const _000: Self = Self::new(0);
614
615        #[doc = "PCLKB/8"]
616        pub const _001: Self = Self::new(1);
617
618        #[doc = "PCLKB/2"]
619        pub const _011: Self = Self::new(3);
620
621        #[doc = "Divided clock AGTLCLK specified by CKS\\[2:0\\] bits in the AGTMR2 register"]
622        pub const _100: Self = Self::new(4);
623
624        #[doc = "Underflow event signal from AGTn (n = 0, 2, 4)"]
625        pub const _101: Self = Self::new(5);
626
627        #[doc = "Divided clock AGTSCLK specified by CKS\\[2:0\\] bits in the AGTMR2 register"]
628        pub const _110: Self = Self::new(6);
629
630        #[doc = "Setting prohibited"]
631        pub const OTHERS: Self = Self::new(0);
632    }
633}
634#[doc(hidden)]
635#[derive(Copy, Clone, Eq, PartialEq)]
636pub struct Agtmr2_SPEC;
637impl crate::sealed::RegSpec for Agtmr2_SPEC {
638    type DataType = u8;
639}
640
641#[doc = "AGT Mode Register 2"]
642pub type Agtmr2 = crate::RegValueT<Agtmr2_SPEC>;
643
644impl Agtmr2 {
645    #[doc = "AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio"]
646    #[inline(always)]
647    pub fn cks(
648        self,
649    ) -> crate::common::RegisterField<
650        0,
651        0x7,
652        1,
653        0,
654        agtmr2::Cks,
655        agtmr2::Cks,
656        Agtmr2_SPEC,
657        crate::common::RW,
658    > {
659        crate::common::RegisterField::<
660            0,
661            0x7,
662            1,
663            0,
664            agtmr2::Cks,
665            agtmr2::Cks,
666            Agtmr2_SPEC,
667            crate::common::RW,
668        >::from_register(self, 0)
669    }
670
671    #[doc = "Low Power Mode"]
672    #[inline(always)]
673    pub fn lpm(
674        self,
675    ) -> crate::common::RegisterField<
676        7,
677        0x1,
678        1,
679        0,
680        agtmr2::Lpm,
681        agtmr2::Lpm,
682        Agtmr2_SPEC,
683        crate::common::RW,
684    > {
685        crate::common::RegisterField::<
686            7,
687            0x1,
688            1,
689            0,
690            agtmr2::Lpm,
691            agtmr2::Lpm,
692            Agtmr2_SPEC,
693            crate::common::RW,
694        >::from_register(self, 0)
695    }
696}
697impl ::core::default::Default for Agtmr2 {
698    #[inline(always)]
699    fn default() -> Agtmr2 {
700        <crate::RegValueT<Agtmr2_SPEC> as RegisterValue<_>>::new(0)
701    }
702}
703pub mod agtmr2 {
704
705    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
706    pub struct Cks_SPEC;
707    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
708    impl Cks {
709        #[doc = "1/1"]
710        pub const _000: Self = Self::new(0);
711
712        #[doc = "1/2"]
713        pub const _001: Self = Self::new(1);
714
715        #[doc = "1/4"]
716        pub const _010: Self = Self::new(2);
717
718        #[doc = "1/8"]
719        pub const _011: Self = Self::new(3);
720
721        #[doc = "1/16"]
722        pub const _100: Self = Self::new(4);
723
724        #[doc = "1/32"]
725        pub const _101: Self = Self::new(5);
726
727        #[doc = "1/64"]
728        pub const _110: Self = Self::new(6);
729
730        #[doc = "1/128"]
731        pub const _111: Self = Self::new(7);
732    }
733    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
734    pub struct Lpm_SPEC;
735    pub type Lpm = crate::EnumBitfieldStruct<u8, Lpm_SPEC>;
736    impl Lpm {
737        #[doc = "Normal mode"]
738        pub const _0: Self = Self::new(0);
739
740        #[doc = "Low power mode"]
741        pub const _1: Self = Self::new(1);
742    }
743}
744#[doc(hidden)]
745#[derive(Copy, Clone, Eq, PartialEq)]
746pub struct Agtioc_SPEC;
747impl crate::sealed::RegSpec for Agtioc_SPEC {
748    type DataType = u8;
749}
750
751#[doc = "AGT I/O Control Register"]
752pub type Agtioc = crate::RegValueT<Agtioc_SPEC>;
753
754impl Agtioc {
755    #[doc = "I/O Polarity Switch"]
756    #[inline(always)]
757    pub fn tedgsel(
758        self,
759    ) -> crate::common::RegisterFieldBool<0, 1, 0, Agtioc_SPEC, crate::common::RW> {
760        crate::common::RegisterFieldBool::<0, 1, 0, Agtioc_SPEC, crate::common::RW>::from_register(
761            self, 0,
762        )
763    }
764
765    #[doc = "AGTOn pin Output Enable"]
766    #[inline(always)]
767    pub fn toe(
768        self,
769    ) -> crate::common::RegisterField<
770        2,
771        0x1,
772        1,
773        0,
774        agtioc::Toe,
775        agtioc::Toe,
776        Agtioc_SPEC,
777        crate::common::RW,
778    > {
779        crate::common::RegisterField::<
780            2,
781            0x1,
782            1,
783            0,
784            agtioc::Toe,
785            agtioc::Toe,
786            Agtioc_SPEC,
787            crate::common::RW,
788        >::from_register(self, 0)
789    }
790
791    #[doc = "Input Filter"]
792    #[inline(always)]
793    pub fn tipf(
794        self,
795    ) -> crate::common::RegisterField<
796        4,
797        0x3,
798        1,
799        0,
800        agtioc::Tipf,
801        agtioc::Tipf,
802        Agtioc_SPEC,
803        crate::common::RW,
804    > {
805        crate::common::RegisterField::<
806            4,
807            0x3,
808            1,
809            0,
810            agtioc::Tipf,
811            agtioc::Tipf,
812            Agtioc_SPEC,
813            crate::common::RW,
814        >::from_register(self, 0)
815    }
816
817    #[doc = "Count Control"]
818    #[inline(always)]
819    pub fn tiogt(
820        self,
821    ) -> crate::common::RegisterField<
822        6,
823        0x3,
824        1,
825        0,
826        agtioc::Tiogt,
827        agtioc::Tiogt,
828        Agtioc_SPEC,
829        crate::common::RW,
830    > {
831        crate::common::RegisterField::<
832            6,
833            0x3,
834            1,
835            0,
836            agtioc::Tiogt,
837            agtioc::Tiogt,
838            Agtioc_SPEC,
839            crate::common::RW,
840        >::from_register(self, 0)
841    }
842}
843impl ::core::default::Default for Agtioc {
844    #[inline(always)]
845    fn default() -> Agtioc {
846        <crate::RegValueT<Agtioc_SPEC> as RegisterValue<_>>::new(0)
847    }
848}
849pub mod agtioc {
850
851    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
852    pub struct Toe_SPEC;
853    pub type Toe = crate::EnumBitfieldStruct<u8, Toe_SPEC>;
854    impl Toe {
855        #[doc = "AGTOn pin output disabled"]
856        pub const _0: Self = Self::new(0);
857
858        #[doc = "AGTOn pin output enabled"]
859        pub const _1: Self = Self::new(1);
860    }
861    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
862    pub struct Tipf_SPEC;
863    pub type Tipf = crate::EnumBitfieldStruct<u8, Tipf_SPEC>;
864    impl Tipf {
865        #[doc = "No filter"]
866        pub const _00: Self = Self::new(0);
867
868        #[doc = "Filter sampled at PCLKB"]
869        pub const _01: Self = Self::new(1);
870
871        #[doc = "Filter sampled at PCLKB/8"]
872        pub const _10: Self = Self::new(2);
873
874        #[doc = "Filter sampled at PCLKB/32"]
875        pub const _11: Self = Self::new(3);
876    }
877    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
878    pub struct Tiogt_SPEC;
879    pub type Tiogt = crate::EnumBitfieldStruct<u8, Tiogt_SPEC>;
880    impl Tiogt {
881        #[doc = "Event is always counted"]
882        pub const _00: Self = Self::new(0);
883
884        #[doc = "Event is counted during polarity period specified for AGTEEn pin"]
885        pub const _01: Self = Self::new(1);
886
887        #[doc = "Setting prohibited"]
888        pub const OTHERS: Self = Self::new(0);
889    }
890}
891#[doc(hidden)]
892#[derive(Copy, Clone, Eq, PartialEq)]
893pub struct Agtisr_SPEC;
894impl crate::sealed::RegSpec for Agtisr_SPEC {
895    type DataType = u8;
896}
897
898#[doc = "AGT Event Pin Select Register"]
899pub type Agtisr = crate::RegValueT<Agtisr_SPEC>;
900
901impl Agtisr {
902    #[doc = "AGTEEn Polarity Selection"]
903    #[inline(always)]
904    pub fn eeps(
905        self,
906    ) -> crate::common::RegisterField<
907        2,
908        0x1,
909        1,
910        0,
911        agtisr::Eeps,
912        agtisr::Eeps,
913        Agtisr_SPEC,
914        crate::common::RW,
915    > {
916        crate::common::RegisterField::<
917            2,
918            0x1,
919            1,
920            0,
921            agtisr::Eeps,
922            agtisr::Eeps,
923            Agtisr_SPEC,
924            crate::common::RW,
925        >::from_register(self, 0)
926    }
927}
928impl ::core::default::Default for Agtisr {
929    #[inline(always)]
930    fn default() -> Agtisr {
931        <crate::RegValueT<Agtisr_SPEC> as RegisterValue<_>>::new(0)
932    }
933}
934pub mod agtisr {
935
936    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
937    pub struct Eeps_SPEC;
938    pub type Eeps = crate::EnumBitfieldStruct<u8, Eeps_SPEC>;
939    impl Eeps {
940        #[doc = "An event is counted during the low-level period"]
941        pub const _0: Self = Self::new(0);
942
943        #[doc = "An event is counted during the high-level period"]
944        pub const _1: Self = Self::new(1);
945    }
946}
947#[doc(hidden)]
948#[derive(Copy, Clone, Eq, PartialEq)]
949pub struct Agtcmsr_SPEC;
950impl crate::sealed::RegSpec for Agtcmsr_SPEC {
951    type DataType = u8;
952}
953
954#[doc = "AGT Compare Match Function Select Register"]
955pub type Agtcmsr = crate::RegValueT<Agtcmsr_SPEC>;
956
957impl Agtcmsr {
958    #[doc = "AGT Compare Match A Register Enable"]
959    #[inline(always)]
960    pub fn tcmea(
961        self,
962    ) -> crate::common::RegisterField<
963        0,
964        0x1,
965        1,
966        0,
967        agtcmsr::Tcmea,
968        agtcmsr::Tcmea,
969        Agtcmsr_SPEC,
970        crate::common::RW,
971    > {
972        crate::common::RegisterField::<
973            0,
974            0x1,
975            1,
976            0,
977            agtcmsr::Tcmea,
978            agtcmsr::Tcmea,
979            Agtcmsr_SPEC,
980            crate::common::RW,
981        >::from_register(self, 0)
982    }
983
984    #[doc = "AGTOAn Pin Output Enable"]
985    #[inline(always)]
986    pub fn toea(
987        self,
988    ) -> crate::common::RegisterField<
989        1,
990        0x1,
991        1,
992        0,
993        agtcmsr::Toea,
994        agtcmsr::Toea,
995        Agtcmsr_SPEC,
996        crate::common::RW,
997    > {
998        crate::common::RegisterField::<
999            1,
1000            0x1,
1001            1,
1002            0,
1003            agtcmsr::Toea,
1004            agtcmsr::Toea,
1005            Agtcmsr_SPEC,
1006            crate::common::RW,
1007        >::from_register(self, 0)
1008    }
1009
1010    #[doc = "AGTOAn Pin Polarity Select"]
1011    #[inline(always)]
1012    pub fn topola(
1013        self,
1014    ) -> crate::common::RegisterField<
1015        2,
1016        0x1,
1017        1,
1018        0,
1019        agtcmsr::Topola,
1020        agtcmsr::Topola,
1021        Agtcmsr_SPEC,
1022        crate::common::RW,
1023    > {
1024        crate::common::RegisterField::<
1025            2,
1026            0x1,
1027            1,
1028            0,
1029            agtcmsr::Topola,
1030            agtcmsr::Topola,
1031            Agtcmsr_SPEC,
1032            crate::common::RW,
1033        >::from_register(self, 0)
1034    }
1035
1036    #[doc = "AGT Compare Match B Register Enable"]
1037    #[inline(always)]
1038    pub fn tcmeb(
1039        self,
1040    ) -> crate::common::RegisterField<
1041        4,
1042        0x1,
1043        1,
1044        0,
1045        agtcmsr::Tcmeb,
1046        agtcmsr::Tcmeb,
1047        Agtcmsr_SPEC,
1048        crate::common::RW,
1049    > {
1050        crate::common::RegisterField::<
1051            4,
1052            0x1,
1053            1,
1054            0,
1055            agtcmsr::Tcmeb,
1056            agtcmsr::Tcmeb,
1057            Agtcmsr_SPEC,
1058            crate::common::RW,
1059        >::from_register(self, 0)
1060    }
1061
1062    #[doc = "AGTOBn Pin Output Enable"]
1063    #[inline(always)]
1064    pub fn toeb(
1065        self,
1066    ) -> crate::common::RegisterField<
1067        5,
1068        0x1,
1069        1,
1070        0,
1071        agtcmsr::Toeb,
1072        agtcmsr::Toeb,
1073        Agtcmsr_SPEC,
1074        crate::common::RW,
1075    > {
1076        crate::common::RegisterField::<
1077            5,
1078            0x1,
1079            1,
1080            0,
1081            agtcmsr::Toeb,
1082            agtcmsr::Toeb,
1083            Agtcmsr_SPEC,
1084            crate::common::RW,
1085        >::from_register(self, 0)
1086    }
1087
1088    #[doc = "AGTOBn Pin Polarity Select"]
1089    #[inline(always)]
1090    pub fn topolb(
1091        self,
1092    ) -> crate::common::RegisterField<
1093        6,
1094        0x1,
1095        1,
1096        0,
1097        agtcmsr::Topolb,
1098        agtcmsr::Topolb,
1099        Agtcmsr_SPEC,
1100        crate::common::RW,
1101    > {
1102        crate::common::RegisterField::<
1103            6,
1104            0x1,
1105            1,
1106            0,
1107            agtcmsr::Topolb,
1108            agtcmsr::Topolb,
1109            Agtcmsr_SPEC,
1110            crate::common::RW,
1111        >::from_register(self, 0)
1112    }
1113}
1114impl ::core::default::Default for Agtcmsr {
1115    #[inline(always)]
1116    fn default() -> Agtcmsr {
1117        <crate::RegValueT<Agtcmsr_SPEC> as RegisterValue<_>>::new(0)
1118    }
1119}
1120pub mod agtcmsr {
1121
1122    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1123    pub struct Tcmea_SPEC;
1124    pub type Tcmea = crate::EnumBitfieldStruct<u8, Tcmea_SPEC>;
1125    impl Tcmea {
1126        #[doc = "AGT Compare match A register disabled"]
1127        pub const _0: Self = Self::new(0);
1128
1129        #[doc = "AGT Compare match A register enabled"]
1130        pub const _1: Self = Self::new(1);
1131    }
1132    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1133    pub struct Toea_SPEC;
1134    pub type Toea = crate::EnumBitfieldStruct<u8, Toea_SPEC>;
1135    impl Toea {
1136        #[doc = "AGTOAn pin output disabled"]
1137        pub const _0: Self = Self::new(0);
1138
1139        #[doc = "AGTOAn pin output enabled"]
1140        pub const _1: Self = Self::new(1);
1141    }
1142    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1143    pub struct Topola_SPEC;
1144    pub type Topola = crate::EnumBitfieldStruct<u8, Topola_SPEC>;
1145    impl Topola {
1146        #[doc = "AGTOAn pin output is started on low. i.e. normal output"]
1147        pub const _0: Self = Self::new(0);
1148
1149        #[doc = "AGTOAn pin output is started on high. i.e. inverted output"]
1150        pub const _1: Self = Self::new(1);
1151    }
1152    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1153    pub struct Tcmeb_SPEC;
1154    pub type Tcmeb = crate::EnumBitfieldStruct<u8, Tcmeb_SPEC>;
1155    impl Tcmeb {
1156        #[doc = "Compare match B register disabled"]
1157        pub const _0: Self = Self::new(0);
1158
1159        #[doc = "Compare match B register enabled"]
1160        pub const _1: Self = Self::new(1);
1161    }
1162    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1163    pub struct Toeb_SPEC;
1164    pub type Toeb = crate::EnumBitfieldStruct<u8, Toeb_SPEC>;
1165    impl Toeb {
1166        #[doc = "AGTOBn pin output disabled"]
1167        pub const _0: Self = Self::new(0);
1168
1169        #[doc = "AGTOBn pin output enabled"]
1170        pub const _1: Self = Self::new(1);
1171    }
1172    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1173    pub struct Topolb_SPEC;
1174    pub type Topolb = crate::EnumBitfieldStruct<u8, Topolb_SPEC>;
1175    impl Topolb {
1176        #[doc = "AGTOBn pin output is started on low. i.e. normal output"]
1177        pub const _0: Self = Self::new(0);
1178
1179        #[doc = "AGTOBn pin output is started on high. i.e. inverted output"]
1180        pub const _1: Self = Self::new(1);
1181    }
1182}
1183#[doc(hidden)]
1184#[derive(Copy, Clone, Eq, PartialEq)]
1185pub struct Agtiosel_SPEC;
1186impl crate::sealed::RegSpec for Agtiosel_SPEC {
1187    type DataType = u8;
1188}
1189
1190#[doc = "AGT Pin Select Register"]
1191pub type Agtiosel = crate::RegValueT<Agtiosel_SPEC>;
1192
1193impl Agtiosel {
1194    #[doc = "AGTIOn Pin Select"]
1195    #[inline(always)]
1196    pub fn sel(
1197        self,
1198    ) -> crate::common::RegisterField<
1199        0,
1200        0x3,
1201        1,
1202        0,
1203        agtiosel::Sel,
1204        agtiosel::Sel,
1205        Agtiosel_SPEC,
1206        crate::common::RW,
1207    > {
1208        crate::common::RegisterField::<
1209            0,
1210            0x3,
1211            1,
1212            0,
1213            agtiosel::Sel,
1214            agtiosel::Sel,
1215            Agtiosel_SPEC,
1216            crate::common::RW,
1217        >::from_register(self, 0)
1218    }
1219
1220    #[doc = "AGTIOn Pin Input Enable"]
1221    #[inline(always)]
1222    pub fn ties(
1223        self,
1224    ) -> crate::common::RegisterField<
1225        4,
1226        0x1,
1227        1,
1228        0,
1229        agtiosel::Ties,
1230        agtiosel::Ties,
1231        Agtiosel_SPEC,
1232        crate::common::RW,
1233    > {
1234        crate::common::RegisterField::<
1235            4,
1236            0x1,
1237            1,
1238            0,
1239            agtiosel::Ties,
1240            agtiosel::Ties,
1241            Agtiosel_SPEC,
1242            crate::common::RW,
1243        >::from_register(self, 0)
1244    }
1245}
1246impl ::core::default::Default for Agtiosel {
1247    #[inline(always)]
1248    fn default() -> Agtiosel {
1249        <crate::RegValueT<Agtiosel_SPEC> as RegisterValue<_>>::new(0)
1250    }
1251}
1252pub mod agtiosel {
1253
1254    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1255    pub struct Sel_SPEC;
1256    pub type Sel = crate::EnumBitfieldStruct<u8, Sel_SPEC>;
1257    impl Sel {
1258        #[doc = "Select Pm/AGTIO as AGTIO. Pm/AGTIO can not be used as AGTIO input pin in Deep Software Standby mode. (m = 100, 301, 407, and 705 (AGT0), m = 204 and 400 (AGT1), m = 103 (AGT2), m = 600(AGT3).)"]
1259        pub const _00: Self = Self::new(0);
1260
1261        #[doc = "Select P404/AGTIO as AGTIO P404/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P404/AGTIOn is input only. It cannot be used for output."]
1262        pub const _01: Self = Self::new(1);
1263
1264        #[doc = "Select P402/AGTIO as AGTIO P402/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P402/AGTIOn is input only. It cannot be used for output."]
1265        pub const _10: Self = Self::new(2);
1266
1267        #[doc = "Select P403/AGTIO as AGTIO. P403/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P403/AGTIOn is input only. It cannot be used for output."]
1268        pub const _11: Self = Self::new(3);
1269    }
1270    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1271    pub struct Ties_SPEC;
1272    pub type Ties = crate::EnumBitfieldStruct<u8, Ties_SPEC>;
1273    impl Ties {
1274        #[doc = "External event input is disabled during Software Standby mode"]
1275        pub const _0: Self = Self::new(0);
1276
1277        #[doc = "External event input is enabled during Software Standby mode"]
1278        pub const _1: Self = Self::new(1);
1279    }
1280}
ra6e1_pac/agt0.rs

ra6e1_pac/
agt0.rs
