1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Interrupt Controller"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 16,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114 #[inline(always)]
115 pub const fn irqcr8(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
116 unsafe {
117 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
118 self._svd2pac_as_ptr().add(0x8usize),
119 )
120 }
121 }
122 #[inline(always)]
123 pub const fn irqcr9(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(0x9usize),
127 )
128 }
129 }
130 #[inline(always)]
131 pub const fn irqcr10(
132 &self,
133 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(0xausize),
137 )
138 }
139 }
140 #[inline(always)]
141 pub const fn irqcr11(
142 &self,
143 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(0xbusize),
147 )
148 }
149 }
150 #[inline(always)]
151 pub const fn irqcr12(
152 &self,
153 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
154 unsafe {
155 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
156 self._svd2pac_as_ptr().add(0xcusize),
157 )
158 }
159 }
160 #[inline(always)]
161 pub const fn irqcr13(
162 &self,
163 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(0xdusize),
167 )
168 }
169 }
170 #[inline(always)]
171 pub const fn irqcr14(
172 &self,
173 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(0xeusize),
177 )
178 }
179 }
180 #[inline(always)]
181 pub const fn irqcr15(
182 &self,
183 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
184 unsafe {
185 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
186 self._svd2pac_as_ptr().add(0xfusize),
187 )
188 }
189 }
190
191 #[doc = "NMI Pin Interrupt Control Register"]
192 #[inline(always)]
193 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
194 unsafe {
195 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
196 self._svd2pac_as_ptr().add(256usize),
197 )
198 }
199 }
200
201 #[doc = "Non-Maskable Interrupt Enable Register"]
202 #[inline(always)]
203 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
204 unsafe {
205 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
206 self._svd2pac_as_ptr().add(288usize),
207 )
208 }
209 }
210
211 #[doc = "Non-Maskable Interrupt Status Clear Register"]
212 #[inline(always)]
213 pub const fn nmiclr(
214 &self,
215 ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
216 unsafe {
217 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
218 self._svd2pac_as_ptr().add(304usize),
219 )
220 }
221 }
222
223 #[doc = "Non-Maskable Interrupt Status Register"]
224 #[inline(always)]
225 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
226 unsafe {
227 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
228 self._svd2pac_as_ptr().add(320usize),
229 )
230 }
231 }
232
233 #[doc = "Wake Up Interrupt Enable Register 0"]
234 #[inline(always)]
235 pub const fn wupen0(
236 &self,
237 ) -> &'static crate::common::Reg<self::Wupen0_SPEC, crate::common::RW> {
238 unsafe {
239 crate::common::Reg::<self::Wupen0_SPEC, crate::common::RW>::from_ptr(
240 self._svd2pac_as_ptr().add(416usize),
241 )
242 }
243 }
244
245 #[doc = "Wake Up interrupt enable register 1"]
246 #[inline(always)]
247 pub const fn wupen1(
248 &self,
249 ) -> &'static crate::common::Reg<self::Wupen1_SPEC, crate::common::RW> {
250 unsafe {
251 crate::common::Reg::<self::Wupen1_SPEC, crate::common::RW>::from_ptr(
252 self._svd2pac_as_ptr().add(420usize),
253 )
254 }
255 }
256
257 #[doc = "SYS Event Link Setting Register"]
258 #[inline(always)]
259 pub const fn selsr0(
260 &self,
261 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(512usize),
265 )
266 }
267 }
268
269 #[doc = "DMAC Event Link Setting Register %s"]
270 #[inline(always)]
271 pub const fn delsr(
272 &self,
273 ) -> &'static crate::common::ClusterRegisterArray<
274 crate::common::Reg<self::Delsr_SPEC, crate::common::RW>,
275 8,
276 0x4,
277 > {
278 unsafe {
279 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x280usize))
280 }
281 }
282 #[inline(always)]
283 pub const fn delsr0(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
284 unsafe {
285 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
286 self._svd2pac_as_ptr().add(0x280usize),
287 )
288 }
289 }
290 #[inline(always)]
291 pub const fn delsr1(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
292 unsafe {
293 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
294 self._svd2pac_as_ptr().add(0x284usize),
295 )
296 }
297 }
298 #[inline(always)]
299 pub const fn delsr2(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
300 unsafe {
301 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
302 self._svd2pac_as_ptr().add(0x288usize),
303 )
304 }
305 }
306 #[inline(always)]
307 pub const fn delsr3(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
308 unsafe {
309 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
310 self._svd2pac_as_ptr().add(0x28cusize),
311 )
312 }
313 }
314 #[inline(always)]
315 pub const fn delsr4(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(0x290usize),
319 )
320 }
321 }
322 #[inline(always)]
323 pub const fn delsr5(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
324 unsafe {
325 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
326 self._svd2pac_as_ptr().add(0x294usize),
327 )
328 }
329 }
330 #[inline(always)]
331 pub const fn delsr6(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
332 unsafe {
333 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
334 self._svd2pac_as_ptr().add(0x298usize),
335 )
336 }
337 }
338 #[inline(always)]
339 pub const fn delsr7(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(0x29cusize),
343 )
344 }
345 }
346
347 #[doc = "ICU Event Link Setting Register %s"]
348 #[inline(always)]
349 pub const fn ielsr(
350 &self,
351 ) -> &'static crate::common::ClusterRegisterArray<
352 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
353 96,
354 0x4,
355 > {
356 unsafe {
357 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
358 }
359 }
360 #[inline(always)]
361 pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
362 unsafe {
363 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
364 self._svd2pac_as_ptr().add(0x300usize),
365 )
366 }
367 }
368 #[inline(always)]
369 pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
370 unsafe {
371 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
372 self._svd2pac_as_ptr().add(0x304usize),
373 )
374 }
375 }
376 #[inline(always)]
377 pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
378 unsafe {
379 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
380 self._svd2pac_as_ptr().add(0x308usize),
381 )
382 }
383 }
384 #[inline(always)]
385 pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(0x30cusize),
389 )
390 }
391 }
392 #[inline(always)]
393 pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
394 unsafe {
395 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
396 self._svd2pac_as_ptr().add(0x310usize),
397 )
398 }
399 }
400 #[inline(always)]
401 pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
402 unsafe {
403 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
404 self._svd2pac_as_ptr().add(0x314usize),
405 )
406 }
407 }
408 #[inline(always)]
409 pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
410 unsafe {
411 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
412 self._svd2pac_as_ptr().add(0x318usize),
413 )
414 }
415 }
416 #[inline(always)]
417 pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
418 unsafe {
419 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
420 self._svd2pac_as_ptr().add(0x31cusize),
421 )
422 }
423 }
424 #[inline(always)]
425 pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x320usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
434 unsafe {
435 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
436 self._svd2pac_as_ptr().add(0x324usize),
437 )
438 }
439 }
440 #[inline(always)]
441 pub const fn ielsr10(
442 &self,
443 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
444 unsafe {
445 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
446 self._svd2pac_as_ptr().add(0x328usize),
447 )
448 }
449 }
450 #[inline(always)]
451 pub const fn ielsr11(
452 &self,
453 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
454 unsafe {
455 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
456 self._svd2pac_as_ptr().add(0x32cusize),
457 )
458 }
459 }
460 #[inline(always)]
461 pub const fn ielsr12(
462 &self,
463 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
464 unsafe {
465 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
466 self._svd2pac_as_ptr().add(0x330usize),
467 )
468 }
469 }
470 #[inline(always)]
471 pub const fn ielsr13(
472 &self,
473 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
474 unsafe {
475 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
476 self._svd2pac_as_ptr().add(0x334usize),
477 )
478 }
479 }
480 #[inline(always)]
481 pub const fn ielsr14(
482 &self,
483 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
484 unsafe {
485 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
486 self._svd2pac_as_ptr().add(0x338usize),
487 )
488 }
489 }
490 #[inline(always)]
491 pub const fn ielsr15(
492 &self,
493 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
494 unsafe {
495 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
496 self._svd2pac_as_ptr().add(0x33cusize),
497 )
498 }
499 }
500 #[inline(always)]
501 pub const fn ielsr16(
502 &self,
503 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
504 unsafe {
505 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
506 self._svd2pac_as_ptr().add(0x340usize),
507 )
508 }
509 }
510 #[inline(always)]
511 pub const fn ielsr17(
512 &self,
513 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
514 unsafe {
515 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
516 self._svd2pac_as_ptr().add(0x344usize),
517 )
518 }
519 }
520 #[inline(always)]
521 pub const fn ielsr18(
522 &self,
523 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
524 unsafe {
525 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
526 self._svd2pac_as_ptr().add(0x348usize),
527 )
528 }
529 }
530 #[inline(always)]
531 pub const fn ielsr19(
532 &self,
533 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
534 unsafe {
535 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
536 self._svd2pac_as_ptr().add(0x34cusize),
537 )
538 }
539 }
540 #[inline(always)]
541 pub const fn ielsr20(
542 &self,
543 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
544 unsafe {
545 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
546 self._svd2pac_as_ptr().add(0x350usize),
547 )
548 }
549 }
550 #[inline(always)]
551 pub const fn ielsr21(
552 &self,
553 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
554 unsafe {
555 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
556 self._svd2pac_as_ptr().add(0x354usize),
557 )
558 }
559 }
560 #[inline(always)]
561 pub const fn ielsr22(
562 &self,
563 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
564 unsafe {
565 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
566 self._svd2pac_as_ptr().add(0x358usize),
567 )
568 }
569 }
570 #[inline(always)]
571 pub const fn ielsr23(
572 &self,
573 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
574 unsafe {
575 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
576 self._svd2pac_as_ptr().add(0x35cusize),
577 )
578 }
579 }
580 #[inline(always)]
581 pub const fn ielsr24(
582 &self,
583 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
584 unsafe {
585 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
586 self._svd2pac_as_ptr().add(0x360usize),
587 )
588 }
589 }
590 #[inline(always)]
591 pub const fn ielsr25(
592 &self,
593 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
594 unsafe {
595 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
596 self._svd2pac_as_ptr().add(0x364usize),
597 )
598 }
599 }
600 #[inline(always)]
601 pub const fn ielsr26(
602 &self,
603 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
604 unsafe {
605 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
606 self._svd2pac_as_ptr().add(0x368usize),
607 )
608 }
609 }
610 #[inline(always)]
611 pub const fn ielsr27(
612 &self,
613 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
614 unsafe {
615 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
616 self._svd2pac_as_ptr().add(0x36cusize),
617 )
618 }
619 }
620 #[inline(always)]
621 pub const fn ielsr28(
622 &self,
623 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
624 unsafe {
625 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
626 self._svd2pac_as_ptr().add(0x370usize),
627 )
628 }
629 }
630 #[inline(always)]
631 pub const fn ielsr29(
632 &self,
633 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
634 unsafe {
635 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
636 self._svd2pac_as_ptr().add(0x374usize),
637 )
638 }
639 }
640 #[inline(always)]
641 pub const fn ielsr30(
642 &self,
643 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
644 unsafe {
645 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
646 self._svd2pac_as_ptr().add(0x378usize),
647 )
648 }
649 }
650 #[inline(always)]
651 pub const fn ielsr31(
652 &self,
653 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
654 unsafe {
655 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
656 self._svd2pac_as_ptr().add(0x37cusize),
657 )
658 }
659 }
660 #[inline(always)]
661 pub const fn ielsr32(
662 &self,
663 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
664 unsafe {
665 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
666 self._svd2pac_as_ptr().add(0x380usize),
667 )
668 }
669 }
670 #[inline(always)]
671 pub const fn ielsr33(
672 &self,
673 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
674 unsafe {
675 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
676 self._svd2pac_as_ptr().add(0x384usize),
677 )
678 }
679 }
680 #[inline(always)]
681 pub const fn ielsr34(
682 &self,
683 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
684 unsafe {
685 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
686 self._svd2pac_as_ptr().add(0x388usize),
687 )
688 }
689 }
690 #[inline(always)]
691 pub const fn ielsr35(
692 &self,
693 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
694 unsafe {
695 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
696 self._svd2pac_as_ptr().add(0x38cusize),
697 )
698 }
699 }
700 #[inline(always)]
701 pub const fn ielsr36(
702 &self,
703 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
704 unsafe {
705 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
706 self._svd2pac_as_ptr().add(0x390usize),
707 )
708 }
709 }
710 #[inline(always)]
711 pub const fn ielsr37(
712 &self,
713 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
714 unsafe {
715 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
716 self._svd2pac_as_ptr().add(0x394usize),
717 )
718 }
719 }
720 #[inline(always)]
721 pub const fn ielsr38(
722 &self,
723 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
724 unsafe {
725 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
726 self._svd2pac_as_ptr().add(0x398usize),
727 )
728 }
729 }
730 #[inline(always)]
731 pub const fn ielsr39(
732 &self,
733 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
734 unsafe {
735 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
736 self._svd2pac_as_ptr().add(0x39cusize),
737 )
738 }
739 }
740 #[inline(always)]
741 pub const fn ielsr40(
742 &self,
743 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
744 unsafe {
745 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
746 self._svd2pac_as_ptr().add(0x3a0usize),
747 )
748 }
749 }
750 #[inline(always)]
751 pub const fn ielsr41(
752 &self,
753 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
754 unsafe {
755 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
756 self._svd2pac_as_ptr().add(0x3a4usize),
757 )
758 }
759 }
760 #[inline(always)]
761 pub const fn ielsr42(
762 &self,
763 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
764 unsafe {
765 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
766 self._svd2pac_as_ptr().add(0x3a8usize),
767 )
768 }
769 }
770 #[inline(always)]
771 pub const fn ielsr43(
772 &self,
773 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
774 unsafe {
775 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
776 self._svd2pac_as_ptr().add(0x3acusize),
777 )
778 }
779 }
780 #[inline(always)]
781 pub const fn ielsr44(
782 &self,
783 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
784 unsafe {
785 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
786 self._svd2pac_as_ptr().add(0x3b0usize),
787 )
788 }
789 }
790 #[inline(always)]
791 pub const fn ielsr45(
792 &self,
793 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
794 unsafe {
795 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
796 self._svd2pac_as_ptr().add(0x3b4usize),
797 )
798 }
799 }
800 #[inline(always)]
801 pub const fn ielsr46(
802 &self,
803 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
804 unsafe {
805 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
806 self._svd2pac_as_ptr().add(0x3b8usize),
807 )
808 }
809 }
810 #[inline(always)]
811 pub const fn ielsr47(
812 &self,
813 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
814 unsafe {
815 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
816 self._svd2pac_as_ptr().add(0x3bcusize),
817 )
818 }
819 }
820 #[inline(always)]
821 pub const fn ielsr48(
822 &self,
823 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
824 unsafe {
825 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
826 self._svd2pac_as_ptr().add(0x3c0usize),
827 )
828 }
829 }
830 #[inline(always)]
831 pub const fn ielsr49(
832 &self,
833 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
834 unsafe {
835 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
836 self._svd2pac_as_ptr().add(0x3c4usize),
837 )
838 }
839 }
840 #[inline(always)]
841 pub const fn ielsr50(
842 &self,
843 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
844 unsafe {
845 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
846 self._svd2pac_as_ptr().add(0x3c8usize),
847 )
848 }
849 }
850 #[inline(always)]
851 pub const fn ielsr51(
852 &self,
853 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
854 unsafe {
855 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
856 self._svd2pac_as_ptr().add(0x3ccusize),
857 )
858 }
859 }
860 #[inline(always)]
861 pub const fn ielsr52(
862 &self,
863 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
864 unsafe {
865 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
866 self._svd2pac_as_ptr().add(0x3d0usize),
867 )
868 }
869 }
870 #[inline(always)]
871 pub const fn ielsr53(
872 &self,
873 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
874 unsafe {
875 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
876 self._svd2pac_as_ptr().add(0x3d4usize),
877 )
878 }
879 }
880 #[inline(always)]
881 pub const fn ielsr54(
882 &self,
883 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
884 unsafe {
885 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
886 self._svd2pac_as_ptr().add(0x3d8usize),
887 )
888 }
889 }
890 #[inline(always)]
891 pub const fn ielsr55(
892 &self,
893 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
894 unsafe {
895 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
896 self._svd2pac_as_ptr().add(0x3dcusize),
897 )
898 }
899 }
900 #[inline(always)]
901 pub const fn ielsr56(
902 &self,
903 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
904 unsafe {
905 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
906 self._svd2pac_as_ptr().add(0x3e0usize),
907 )
908 }
909 }
910 #[inline(always)]
911 pub const fn ielsr57(
912 &self,
913 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
914 unsafe {
915 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
916 self._svd2pac_as_ptr().add(0x3e4usize),
917 )
918 }
919 }
920 #[inline(always)]
921 pub const fn ielsr58(
922 &self,
923 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
924 unsafe {
925 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
926 self._svd2pac_as_ptr().add(0x3e8usize),
927 )
928 }
929 }
930 #[inline(always)]
931 pub const fn ielsr59(
932 &self,
933 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
934 unsafe {
935 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
936 self._svd2pac_as_ptr().add(0x3ecusize),
937 )
938 }
939 }
940 #[inline(always)]
941 pub const fn ielsr60(
942 &self,
943 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
944 unsafe {
945 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
946 self._svd2pac_as_ptr().add(0x3f0usize),
947 )
948 }
949 }
950 #[inline(always)]
951 pub const fn ielsr61(
952 &self,
953 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
954 unsafe {
955 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
956 self._svd2pac_as_ptr().add(0x3f4usize),
957 )
958 }
959 }
960 #[inline(always)]
961 pub const fn ielsr62(
962 &self,
963 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
964 unsafe {
965 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
966 self._svd2pac_as_ptr().add(0x3f8usize),
967 )
968 }
969 }
970 #[inline(always)]
971 pub const fn ielsr63(
972 &self,
973 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
974 unsafe {
975 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
976 self._svd2pac_as_ptr().add(0x3fcusize),
977 )
978 }
979 }
980 #[inline(always)]
981 pub const fn ielsr64(
982 &self,
983 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
984 unsafe {
985 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
986 self._svd2pac_as_ptr().add(0x400usize),
987 )
988 }
989 }
990 #[inline(always)]
991 pub const fn ielsr65(
992 &self,
993 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
994 unsafe {
995 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
996 self._svd2pac_as_ptr().add(0x404usize),
997 )
998 }
999 }
1000 #[inline(always)]
1001 pub const fn ielsr66(
1002 &self,
1003 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1004 unsafe {
1005 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1006 self._svd2pac_as_ptr().add(0x408usize),
1007 )
1008 }
1009 }
1010 #[inline(always)]
1011 pub const fn ielsr67(
1012 &self,
1013 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1014 unsafe {
1015 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1016 self._svd2pac_as_ptr().add(0x40cusize),
1017 )
1018 }
1019 }
1020 #[inline(always)]
1021 pub const fn ielsr68(
1022 &self,
1023 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1024 unsafe {
1025 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1026 self._svd2pac_as_ptr().add(0x410usize),
1027 )
1028 }
1029 }
1030 #[inline(always)]
1031 pub const fn ielsr69(
1032 &self,
1033 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1034 unsafe {
1035 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1036 self._svd2pac_as_ptr().add(0x414usize),
1037 )
1038 }
1039 }
1040 #[inline(always)]
1041 pub const fn ielsr70(
1042 &self,
1043 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1044 unsafe {
1045 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1046 self._svd2pac_as_ptr().add(0x418usize),
1047 )
1048 }
1049 }
1050 #[inline(always)]
1051 pub const fn ielsr71(
1052 &self,
1053 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1054 unsafe {
1055 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1056 self._svd2pac_as_ptr().add(0x41cusize),
1057 )
1058 }
1059 }
1060 #[inline(always)]
1061 pub const fn ielsr72(
1062 &self,
1063 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1064 unsafe {
1065 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1066 self._svd2pac_as_ptr().add(0x420usize),
1067 )
1068 }
1069 }
1070 #[inline(always)]
1071 pub const fn ielsr73(
1072 &self,
1073 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1074 unsafe {
1075 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1076 self._svd2pac_as_ptr().add(0x424usize),
1077 )
1078 }
1079 }
1080 #[inline(always)]
1081 pub const fn ielsr74(
1082 &self,
1083 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1084 unsafe {
1085 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1086 self._svd2pac_as_ptr().add(0x428usize),
1087 )
1088 }
1089 }
1090 #[inline(always)]
1091 pub const fn ielsr75(
1092 &self,
1093 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1094 unsafe {
1095 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1096 self._svd2pac_as_ptr().add(0x42cusize),
1097 )
1098 }
1099 }
1100 #[inline(always)]
1101 pub const fn ielsr76(
1102 &self,
1103 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1104 unsafe {
1105 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1106 self._svd2pac_as_ptr().add(0x430usize),
1107 )
1108 }
1109 }
1110 #[inline(always)]
1111 pub const fn ielsr77(
1112 &self,
1113 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1114 unsafe {
1115 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1116 self._svd2pac_as_ptr().add(0x434usize),
1117 )
1118 }
1119 }
1120 #[inline(always)]
1121 pub const fn ielsr78(
1122 &self,
1123 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1124 unsafe {
1125 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1126 self._svd2pac_as_ptr().add(0x438usize),
1127 )
1128 }
1129 }
1130 #[inline(always)]
1131 pub const fn ielsr79(
1132 &self,
1133 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1134 unsafe {
1135 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1136 self._svd2pac_as_ptr().add(0x43cusize),
1137 )
1138 }
1139 }
1140 #[inline(always)]
1141 pub const fn ielsr80(
1142 &self,
1143 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1144 unsafe {
1145 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1146 self._svd2pac_as_ptr().add(0x440usize),
1147 )
1148 }
1149 }
1150 #[inline(always)]
1151 pub const fn ielsr81(
1152 &self,
1153 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1154 unsafe {
1155 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1156 self._svd2pac_as_ptr().add(0x444usize),
1157 )
1158 }
1159 }
1160 #[inline(always)]
1161 pub const fn ielsr82(
1162 &self,
1163 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1164 unsafe {
1165 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1166 self._svd2pac_as_ptr().add(0x448usize),
1167 )
1168 }
1169 }
1170 #[inline(always)]
1171 pub const fn ielsr83(
1172 &self,
1173 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1174 unsafe {
1175 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1176 self._svd2pac_as_ptr().add(0x44cusize),
1177 )
1178 }
1179 }
1180 #[inline(always)]
1181 pub const fn ielsr84(
1182 &self,
1183 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1184 unsafe {
1185 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1186 self._svd2pac_as_ptr().add(0x450usize),
1187 )
1188 }
1189 }
1190 #[inline(always)]
1191 pub const fn ielsr85(
1192 &self,
1193 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1194 unsafe {
1195 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1196 self._svd2pac_as_ptr().add(0x454usize),
1197 )
1198 }
1199 }
1200 #[inline(always)]
1201 pub const fn ielsr86(
1202 &self,
1203 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1204 unsafe {
1205 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1206 self._svd2pac_as_ptr().add(0x458usize),
1207 )
1208 }
1209 }
1210 #[inline(always)]
1211 pub const fn ielsr87(
1212 &self,
1213 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1214 unsafe {
1215 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1216 self._svd2pac_as_ptr().add(0x45cusize),
1217 )
1218 }
1219 }
1220 #[inline(always)]
1221 pub const fn ielsr88(
1222 &self,
1223 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1224 unsafe {
1225 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1226 self._svd2pac_as_ptr().add(0x460usize),
1227 )
1228 }
1229 }
1230 #[inline(always)]
1231 pub const fn ielsr89(
1232 &self,
1233 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1234 unsafe {
1235 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1236 self._svd2pac_as_ptr().add(0x464usize),
1237 )
1238 }
1239 }
1240 #[inline(always)]
1241 pub const fn ielsr90(
1242 &self,
1243 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1244 unsafe {
1245 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1246 self._svd2pac_as_ptr().add(0x468usize),
1247 )
1248 }
1249 }
1250 #[inline(always)]
1251 pub const fn ielsr91(
1252 &self,
1253 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1254 unsafe {
1255 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1256 self._svd2pac_as_ptr().add(0x46cusize),
1257 )
1258 }
1259 }
1260 #[inline(always)]
1261 pub const fn ielsr92(
1262 &self,
1263 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1264 unsafe {
1265 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1266 self._svd2pac_as_ptr().add(0x470usize),
1267 )
1268 }
1269 }
1270 #[inline(always)]
1271 pub const fn ielsr93(
1272 &self,
1273 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1274 unsafe {
1275 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1276 self._svd2pac_as_ptr().add(0x474usize),
1277 )
1278 }
1279 }
1280 #[inline(always)]
1281 pub const fn ielsr94(
1282 &self,
1283 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1284 unsafe {
1285 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1286 self._svd2pac_as_ptr().add(0x478usize),
1287 )
1288 }
1289 }
1290 #[inline(always)]
1291 pub const fn ielsr95(
1292 &self,
1293 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1294 unsafe {
1295 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1296 self._svd2pac_as_ptr().add(0x47cusize),
1297 )
1298 }
1299 }
1300}
1301#[doc(hidden)]
1302#[derive(Copy, Clone, Eq, PartialEq)]
1303pub struct Irqcr_SPEC;
1304impl crate::sealed::RegSpec for Irqcr_SPEC {
1305 type DataType = u8;
1306}
1307
1308#[doc = "IRQ Control Register %s"]
1309pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
1310
1311impl Irqcr {
1312 #[doc = "IRQi Detection Sense Select"]
1313 #[inline(always)]
1314 pub fn irqmd(
1315 self,
1316 ) -> crate::common::RegisterField<
1317 0,
1318 0x3,
1319 1,
1320 0,
1321 irqcr::Irqmd,
1322 irqcr::Irqmd,
1323 Irqcr_SPEC,
1324 crate::common::RW,
1325 > {
1326 crate::common::RegisterField::<
1327 0,
1328 0x3,
1329 1,
1330 0,
1331 irqcr::Irqmd,
1332 irqcr::Irqmd,
1333 Irqcr_SPEC,
1334 crate::common::RW,
1335 >::from_register(self, 0)
1336 }
1337
1338 #[doc = "IRQi Digital Filter Sampling Clock Select"]
1339 #[inline(always)]
1340 pub fn fclksel(
1341 self,
1342 ) -> crate::common::RegisterField<
1343 4,
1344 0x3,
1345 1,
1346 0,
1347 irqcr::Fclksel,
1348 irqcr::Fclksel,
1349 Irqcr_SPEC,
1350 crate::common::RW,
1351 > {
1352 crate::common::RegisterField::<
1353 4,
1354 0x3,
1355 1,
1356 0,
1357 irqcr::Fclksel,
1358 irqcr::Fclksel,
1359 Irqcr_SPEC,
1360 crate::common::RW,
1361 >::from_register(self, 0)
1362 }
1363
1364 #[doc = "IRQi Digital Filter Enable"]
1365 #[inline(always)]
1366 pub fn flten(
1367 self,
1368 ) -> crate::common::RegisterField<
1369 7,
1370 0x1,
1371 1,
1372 0,
1373 irqcr::Flten,
1374 irqcr::Flten,
1375 Irqcr_SPEC,
1376 crate::common::RW,
1377 > {
1378 crate::common::RegisterField::<
1379 7,
1380 0x1,
1381 1,
1382 0,
1383 irqcr::Flten,
1384 irqcr::Flten,
1385 Irqcr_SPEC,
1386 crate::common::RW,
1387 >::from_register(self, 0)
1388 }
1389}
1390impl ::core::default::Default for Irqcr {
1391 #[inline(always)]
1392 fn default() -> Irqcr {
1393 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
1394 }
1395}
1396pub mod irqcr {
1397
1398 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1399 pub struct Irqmd_SPEC;
1400 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
1401 impl Irqmd {
1402 #[doc = "Falling edge"]
1403 pub const _00: Self = Self::new(0);
1404
1405 #[doc = "Rising edge"]
1406 pub const _01: Self = Self::new(1);
1407
1408 #[doc = "Rising and falling edges"]
1409 pub const _10: Self = Self::new(2);
1410
1411 #[doc = "Low level"]
1412 pub const _11: Self = Self::new(3);
1413 }
1414 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1415 pub struct Fclksel_SPEC;
1416 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
1417 impl Fclksel {
1418 #[doc = "PCLKB"]
1419 pub const _00: Self = Self::new(0);
1420
1421 #[doc = "PCLKB/8"]
1422 pub const _01: Self = Self::new(1);
1423
1424 #[doc = "PCLKB/32"]
1425 pub const _10: Self = Self::new(2);
1426
1427 #[doc = "PCLKB/64"]
1428 pub const _11: Self = Self::new(3);
1429 }
1430 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1431 pub struct Flten_SPEC;
1432 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
1433 impl Flten {
1434 #[doc = "Digital filter is disabled"]
1435 pub const _0: Self = Self::new(0);
1436
1437 #[doc = "Digital filter is enabled."]
1438 pub const _1: Self = Self::new(1);
1439 }
1440}
1441#[doc(hidden)]
1442#[derive(Copy, Clone, Eq, PartialEq)]
1443pub struct Nmicr_SPEC;
1444impl crate::sealed::RegSpec for Nmicr_SPEC {
1445 type DataType = u8;
1446}
1447
1448#[doc = "NMI Pin Interrupt Control Register"]
1449pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
1450
1451impl Nmicr {
1452 #[doc = "NMI Detection Set"]
1453 #[inline(always)]
1454 pub fn nmimd(
1455 self,
1456 ) -> crate::common::RegisterField<
1457 0,
1458 0x1,
1459 1,
1460 0,
1461 nmicr::Nmimd,
1462 nmicr::Nmimd,
1463 Nmicr_SPEC,
1464 crate::common::RW,
1465 > {
1466 crate::common::RegisterField::<
1467 0,
1468 0x1,
1469 1,
1470 0,
1471 nmicr::Nmimd,
1472 nmicr::Nmimd,
1473 Nmicr_SPEC,
1474 crate::common::RW,
1475 >::from_register(self, 0)
1476 }
1477
1478 #[doc = "NMI Digital Filter Sampling Clock Select"]
1479 #[inline(always)]
1480 pub fn nfclksel(
1481 self,
1482 ) -> crate::common::RegisterField<
1483 4,
1484 0x3,
1485 1,
1486 0,
1487 nmicr::Nfclksel,
1488 nmicr::Nfclksel,
1489 Nmicr_SPEC,
1490 crate::common::RW,
1491 > {
1492 crate::common::RegisterField::<
1493 4,
1494 0x3,
1495 1,
1496 0,
1497 nmicr::Nfclksel,
1498 nmicr::Nfclksel,
1499 Nmicr_SPEC,
1500 crate::common::RW,
1501 >::from_register(self, 0)
1502 }
1503
1504 #[doc = "NMI Digital Filter Enable"]
1505 #[inline(always)]
1506 pub fn nflten(
1507 self,
1508 ) -> crate::common::RegisterField<
1509 7,
1510 0x1,
1511 1,
1512 0,
1513 nmicr::Nflten,
1514 nmicr::Nflten,
1515 Nmicr_SPEC,
1516 crate::common::RW,
1517 > {
1518 crate::common::RegisterField::<
1519 7,
1520 0x1,
1521 1,
1522 0,
1523 nmicr::Nflten,
1524 nmicr::Nflten,
1525 Nmicr_SPEC,
1526 crate::common::RW,
1527 >::from_register(self, 0)
1528 }
1529}
1530impl ::core::default::Default for Nmicr {
1531 #[inline(always)]
1532 fn default() -> Nmicr {
1533 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
1534 }
1535}
1536pub mod nmicr {
1537
1538 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1539 pub struct Nmimd_SPEC;
1540 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
1541 impl Nmimd {
1542 #[doc = "Falling edge"]
1543 pub const _0: Self = Self::new(0);
1544
1545 #[doc = "Rising edge"]
1546 pub const _1: Self = Self::new(1);
1547 }
1548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1549 pub struct Nfclksel_SPEC;
1550 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
1551 impl Nfclksel {
1552 #[doc = "PCLKB"]
1553 pub const _00: Self = Self::new(0);
1554
1555 #[doc = "PCLKB/8"]
1556 pub const _01: Self = Self::new(1);
1557
1558 #[doc = "PCLKB/32"]
1559 pub const _10: Self = Self::new(2);
1560
1561 #[doc = "PCLKB/64"]
1562 pub const _11: Self = Self::new(3);
1563 }
1564 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1565 pub struct Nflten_SPEC;
1566 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
1567 impl Nflten {
1568 #[doc = "Disabled."]
1569 pub const _0: Self = Self::new(0);
1570
1571 #[doc = "Enabled."]
1572 pub const _1: Self = Self::new(1);
1573 }
1574}
1575#[doc(hidden)]
1576#[derive(Copy, Clone, Eq, PartialEq)]
1577pub struct Nmier_SPEC;
1578impl crate::sealed::RegSpec for Nmier_SPEC {
1579 type DataType = u16;
1580}
1581
1582#[doc = "Non-Maskable Interrupt Enable Register"]
1583pub type Nmier = crate::RegValueT<Nmier_SPEC>;
1584
1585impl Nmier {
1586 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
1587 #[inline(always)]
1588 pub fn iwdten(
1589 self,
1590 ) -> crate::common::RegisterField<
1591 0,
1592 0x1,
1593 1,
1594 0,
1595 nmier::Iwdten,
1596 nmier::Iwdten,
1597 Nmier_SPEC,
1598 crate::common::RW,
1599 > {
1600 crate::common::RegisterField::<
1601 0,
1602 0x1,
1603 1,
1604 0,
1605 nmier::Iwdten,
1606 nmier::Iwdten,
1607 Nmier_SPEC,
1608 crate::common::RW,
1609 >::from_register(self, 0)
1610 }
1611
1612 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
1613 #[inline(always)]
1614 pub fn wdten(
1615 self,
1616 ) -> crate::common::RegisterField<
1617 1,
1618 0x1,
1619 1,
1620 0,
1621 nmier::Wdten,
1622 nmier::Wdten,
1623 Nmier_SPEC,
1624 crate::common::RW,
1625 > {
1626 crate::common::RegisterField::<
1627 1,
1628 0x1,
1629 1,
1630 0,
1631 nmier::Wdten,
1632 nmier::Wdten,
1633 Nmier_SPEC,
1634 crate::common::RW,
1635 >::from_register(self, 0)
1636 }
1637
1638 #[doc = "Voltage monitor 1 Interrupt Enable"]
1639 #[inline(always)]
1640 pub fn lvd1en(
1641 self,
1642 ) -> crate::common::RegisterField<
1643 2,
1644 0x1,
1645 1,
1646 0,
1647 nmier::Lvd1En,
1648 nmier::Lvd1En,
1649 Nmier_SPEC,
1650 crate::common::RW,
1651 > {
1652 crate::common::RegisterField::<
1653 2,
1654 0x1,
1655 1,
1656 0,
1657 nmier::Lvd1En,
1658 nmier::Lvd1En,
1659 Nmier_SPEC,
1660 crate::common::RW,
1661 >::from_register(self, 0)
1662 }
1663
1664 #[doc = "Voltage monitor 2 Interrupt Enable"]
1665 #[inline(always)]
1666 pub fn lvd2en(
1667 self,
1668 ) -> crate::common::RegisterField<
1669 3,
1670 0x1,
1671 1,
1672 0,
1673 nmier::Lvd2En,
1674 nmier::Lvd2En,
1675 Nmier_SPEC,
1676 crate::common::RW,
1677 > {
1678 crate::common::RegisterField::<
1679 3,
1680 0x1,
1681 1,
1682 0,
1683 nmier::Lvd2En,
1684 nmier::Lvd2En,
1685 Nmier_SPEC,
1686 crate::common::RW,
1687 >::from_register(self, 0)
1688 }
1689
1690 #[doc = "Main Clock Oscillation Stop Detection Interrupt Enable"]
1691 #[inline(always)]
1692 pub fn osten(
1693 self,
1694 ) -> crate::common::RegisterField<
1695 6,
1696 0x1,
1697 1,
1698 0,
1699 nmier::Osten,
1700 nmier::Osten,
1701 Nmier_SPEC,
1702 crate::common::RW,
1703 > {
1704 crate::common::RegisterField::<
1705 6,
1706 0x1,
1707 1,
1708 0,
1709 nmier::Osten,
1710 nmier::Osten,
1711 Nmier_SPEC,
1712 crate::common::RW,
1713 >::from_register(self, 0)
1714 }
1715
1716 #[doc = "NMI Pin Interrupt Enable"]
1717 #[inline(always)]
1718 pub fn nmien(
1719 self,
1720 ) -> crate::common::RegisterField<
1721 7,
1722 0x1,
1723 1,
1724 0,
1725 nmier::Nmien,
1726 nmier::Nmien,
1727 Nmier_SPEC,
1728 crate::common::RW,
1729 > {
1730 crate::common::RegisterField::<
1731 7,
1732 0x1,
1733 1,
1734 0,
1735 nmier::Nmien,
1736 nmier::Nmien,
1737 Nmier_SPEC,
1738 crate::common::RW,
1739 >::from_register(self, 0)
1740 }
1741
1742 #[doc = "SRAM Parity Error Interrupt Enable"]
1743 #[inline(always)]
1744 pub fn rpeen(
1745 self,
1746 ) -> crate::common::RegisterField<
1747 8,
1748 0x1,
1749 1,
1750 0,
1751 nmier::Rpeen,
1752 nmier::Rpeen,
1753 Nmier_SPEC,
1754 crate::common::RW,
1755 > {
1756 crate::common::RegisterField::<
1757 8,
1758 0x1,
1759 1,
1760 0,
1761 nmier::Rpeen,
1762 nmier::Rpeen,
1763 Nmier_SPEC,
1764 crate::common::RW,
1765 >::from_register(self, 0)
1766 }
1767
1768 #[doc = "Bus Master MPU Error Interrupt Enable"]
1769 #[inline(always)]
1770 pub fn busmen(
1771 self,
1772 ) -> crate::common::RegisterField<
1773 11,
1774 0x1,
1775 1,
1776 0,
1777 nmier::Busmen,
1778 nmier::Busmen,
1779 Nmier_SPEC,
1780 crate::common::RW,
1781 > {
1782 crate::common::RegisterField::<
1783 11,
1784 0x1,
1785 1,
1786 0,
1787 nmier::Busmen,
1788 nmier::Busmen,
1789 Nmier_SPEC,
1790 crate::common::RW,
1791 >::from_register(self, 0)
1792 }
1793
1794 #[inline(always)]
1795 pub fn tzfen(
1796 self,
1797 ) -> crate::common::RegisterField<
1798 13,
1799 0x1,
1800 1,
1801 0,
1802 nmier::Tzfen,
1803 nmier::Tzfen,
1804 Nmier_SPEC,
1805 crate::common::RW,
1806 > {
1807 crate::common::RegisterField::<
1808 13,
1809 0x1,
1810 1,
1811 0,
1812 nmier::Tzfen,
1813 nmier::Tzfen,
1814 Nmier_SPEC,
1815 crate::common::RW,
1816 >::from_register(self, 0)
1817 }
1818
1819 #[inline(always)]
1820 pub fn cpeen(
1821 self,
1822 ) -> crate::common::RegisterField<
1823 15,
1824 0x1,
1825 1,
1826 0,
1827 nmier::Cpeen,
1828 nmier::Cpeen,
1829 Nmier_SPEC,
1830 crate::common::RW,
1831 > {
1832 crate::common::RegisterField::<
1833 15,
1834 0x1,
1835 1,
1836 0,
1837 nmier::Cpeen,
1838 nmier::Cpeen,
1839 Nmier_SPEC,
1840 crate::common::RW,
1841 >::from_register(self, 0)
1842 }
1843}
1844impl ::core::default::Default for Nmier {
1845 #[inline(always)]
1846 fn default() -> Nmier {
1847 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1848 }
1849}
1850pub mod nmier {
1851
1852 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1853 pub struct Iwdten_SPEC;
1854 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1855 impl Iwdten {
1856 #[doc = "Disabled"]
1857 pub const _0: Self = Self::new(0);
1858
1859 #[doc = "Enabled."]
1860 pub const _1: Self = Self::new(1);
1861 }
1862 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1863 pub struct Wdten_SPEC;
1864 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1865 impl Wdten {
1866 #[doc = "Disabled"]
1867 pub const _0: Self = Self::new(0);
1868
1869 #[doc = "Enabled"]
1870 pub const _1: Self = Self::new(1);
1871 }
1872 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1873 pub struct Lvd1En_SPEC;
1874 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1875 impl Lvd1En {
1876 #[doc = "Disabled"]
1877 pub const _0: Self = Self::new(0);
1878
1879 #[doc = "Enabled"]
1880 pub const _1: Self = Self::new(1);
1881 }
1882 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1883 pub struct Lvd2En_SPEC;
1884 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1885 impl Lvd2En {
1886 #[doc = "Disabled"]
1887 pub const _0: Self = Self::new(0);
1888
1889 #[doc = "Enabled"]
1890 pub const _1: Self = Self::new(1);
1891 }
1892 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1893 pub struct Osten_SPEC;
1894 pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
1895 impl Osten {
1896 #[doc = "Disabled"]
1897 pub const _0: Self = Self::new(0);
1898
1899 #[doc = "Enabled"]
1900 pub const _1: Self = Self::new(1);
1901 }
1902 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1903 pub struct Nmien_SPEC;
1904 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1905 impl Nmien {
1906 #[doc = "Disabled"]
1907 pub const _0: Self = Self::new(0);
1908
1909 #[doc = "Enabled"]
1910 pub const _1: Self = Self::new(1);
1911 }
1912 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1913 pub struct Rpeen_SPEC;
1914 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1915 impl Rpeen {
1916 #[doc = "Disabled"]
1917 pub const _0: Self = Self::new(0);
1918
1919 #[doc = "Enabled"]
1920 pub const _1: Self = Self::new(1);
1921 }
1922 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1923 pub struct Busmen_SPEC;
1924 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1925 impl Busmen {
1926 #[doc = "Disabled"]
1927 pub const _0: Self = Self::new(0);
1928
1929 #[doc = "Enabled"]
1930 pub const _1: Self = Self::new(1);
1931 }
1932 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1933 pub struct Tzfen_SPEC;
1934 pub type Tzfen = crate::EnumBitfieldStruct<u8, Tzfen_SPEC>;
1935 impl Tzfen {
1936 #[doc = "Disabled"]
1937 pub const _0: Self = Self::new(0);
1938
1939 #[doc = "Enabled"]
1940 pub const _1: Self = Self::new(1);
1941 }
1942 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1943 pub struct Cpeen_SPEC;
1944 pub type Cpeen = crate::EnumBitfieldStruct<u8, Cpeen_SPEC>;
1945 impl Cpeen {
1946 #[doc = "Disabled"]
1947 pub const _0: Self = Self::new(0);
1948
1949 #[doc = "Enabled"]
1950 pub const _1: Self = Self::new(1);
1951 }
1952}
1953#[doc(hidden)]
1954#[derive(Copy, Clone, Eq, PartialEq)]
1955pub struct Nmiclr_SPEC;
1956impl crate::sealed::RegSpec for Nmiclr_SPEC {
1957 type DataType = u16;
1958}
1959
1960#[doc = "Non-Maskable Interrupt Status Clear Register"]
1961pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1962
1963impl Nmiclr {
1964 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1965 #[inline(always)]
1966 pub fn iwdtclr(
1967 self,
1968 ) -> crate::common::RegisterField<
1969 0,
1970 0x1,
1971 1,
1972 0,
1973 nmiclr::Iwdtclr,
1974 nmiclr::Iwdtclr,
1975 Nmiclr_SPEC,
1976 crate::common::RW,
1977 > {
1978 crate::common::RegisterField::<
1979 0,
1980 0x1,
1981 1,
1982 0,
1983 nmiclr::Iwdtclr,
1984 nmiclr::Iwdtclr,
1985 Nmiclr_SPEC,
1986 crate::common::RW,
1987 >::from_register(self, 0)
1988 }
1989
1990 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1991 #[inline(always)]
1992 pub fn wdtclr(
1993 self,
1994 ) -> crate::common::RegisterField<
1995 1,
1996 0x1,
1997 1,
1998 0,
1999 nmiclr::Wdtclr,
2000 nmiclr::Wdtclr,
2001 Nmiclr_SPEC,
2002 crate::common::RW,
2003 > {
2004 crate::common::RegisterField::<
2005 1,
2006 0x1,
2007 1,
2008 0,
2009 nmiclr::Wdtclr,
2010 nmiclr::Wdtclr,
2011 Nmiclr_SPEC,
2012 crate::common::RW,
2013 >::from_register(self, 0)
2014 }
2015
2016 #[doc = "Voltage Monitor 1 Interrupt Status Flag Clear"]
2017 #[inline(always)]
2018 pub fn lvd1clr(
2019 self,
2020 ) -> crate::common::RegisterField<
2021 2,
2022 0x1,
2023 1,
2024 0,
2025 nmiclr::Lvd1Clr,
2026 nmiclr::Lvd1Clr,
2027 Nmiclr_SPEC,
2028 crate::common::RW,
2029 > {
2030 crate::common::RegisterField::<
2031 2,
2032 0x1,
2033 1,
2034 0,
2035 nmiclr::Lvd1Clr,
2036 nmiclr::Lvd1Clr,
2037 Nmiclr_SPEC,
2038 crate::common::RW,
2039 >::from_register(self, 0)
2040 }
2041
2042 #[doc = "Voltage Monitor 2 Interrupt Status Flag Clear"]
2043 #[inline(always)]
2044 pub fn lvd2clr(
2045 self,
2046 ) -> crate::common::RegisterField<
2047 3,
2048 0x1,
2049 1,
2050 0,
2051 nmiclr::Lvd2Clr,
2052 nmiclr::Lvd2Clr,
2053 Nmiclr_SPEC,
2054 crate::common::RW,
2055 > {
2056 crate::common::RegisterField::<
2057 3,
2058 0x1,
2059 1,
2060 0,
2061 nmiclr::Lvd2Clr,
2062 nmiclr::Lvd2Clr,
2063 Nmiclr_SPEC,
2064 crate::common::RW,
2065 >::from_register(self, 0)
2066 }
2067
2068 #[doc = "Oscillation Stop Detection Interrupt Status Flag Clear"]
2069 #[inline(always)]
2070 pub fn ostclr(
2071 self,
2072 ) -> crate::common::RegisterField<
2073 6,
2074 0x1,
2075 1,
2076 0,
2077 nmiclr::Ostclr,
2078 nmiclr::Ostclr,
2079 Nmiclr_SPEC,
2080 crate::common::RW,
2081 > {
2082 crate::common::RegisterField::<
2083 6,
2084 0x1,
2085 1,
2086 0,
2087 nmiclr::Ostclr,
2088 nmiclr::Ostclr,
2089 Nmiclr_SPEC,
2090 crate::common::RW,
2091 >::from_register(self, 0)
2092 }
2093
2094 #[doc = "NMI Pin Interrupt Status Flag Clear"]
2095 #[inline(always)]
2096 pub fn nmiclr(
2097 self,
2098 ) -> crate::common::RegisterField<
2099 7,
2100 0x1,
2101 1,
2102 0,
2103 nmiclr::Nmiclr,
2104 nmiclr::Nmiclr,
2105 Nmiclr_SPEC,
2106 crate::common::RW,
2107 > {
2108 crate::common::RegisterField::<
2109 7,
2110 0x1,
2111 1,
2112 0,
2113 nmiclr::Nmiclr,
2114 nmiclr::Nmiclr,
2115 Nmiclr_SPEC,
2116 crate::common::RW,
2117 >::from_register(self, 0)
2118 }
2119
2120 #[doc = "SRAM Parity Error Interrupt Status Flag Clear"]
2121 #[inline(always)]
2122 pub fn rpeclr(
2123 self,
2124 ) -> crate::common::RegisterField<
2125 8,
2126 0x1,
2127 1,
2128 0,
2129 nmiclr::Rpeclr,
2130 nmiclr::Rpeclr,
2131 Nmiclr_SPEC,
2132 crate::common::RW,
2133 > {
2134 crate::common::RegisterField::<
2135 8,
2136 0x1,
2137 1,
2138 0,
2139 nmiclr::Rpeclr,
2140 nmiclr::Rpeclr,
2141 Nmiclr_SPEC,
2142 crate::common::RW,
2143 >::from_register(self, 0)
2144 }
2145
2146 #[doc = "Bus Master MPU Error Interrupt Status Flag Clear"]
2147 #[inline(always)]
2148 pub fn busmclr(
2149 self,
2150 ) -> crate::common::RegisterField<
2151 11,
2152 0x1,
2153 1,
2154 0,
2155 nmiclr::Busmclr,
2156 nmiclr::Busmclr,
2157 Nmiclr_SPEC,
2158 crate::common::RW,
2159 > {
2160 crate::common::RegisterField::<
2161 11,
2162 0x1,
2163 1,
2164 0,
2165 nmiclr::Busmclr,
2166 nmiclr::Busmclr,
2167 Nmiclr_SPEC,
2168 crate::common::RW,
2169 >::from_register(self, 0)
2170 }
2171
2172 #[inline(always)]
2173 pub fn tzfclr(
2174 self,
2175 ) -> crate::common::RegisterField<
2176 13,
2177 0x1,
2178 1,
2179 0,
2180 nmiclr::Tzfclr,
2181 nmiclr::Tzfclr,
2182 Nmiclr_SPEC,
2183 crate::common::RW,
2184 > {
2185 crate::common::RegisterField::<
2186 13,
2187 0x1,
2188 1,
2189 0,
2190 nmiclr::Tzfclr,
2191 nmiclr::Tzfclr,
2192 Nmiclr_SPEC,
2193 crate::common::RW,
2194 >::from_register(self, 0)
2195 }
2196
2197 #[inline(always)]
2198 pub fn cpeclr(
2199 self,
2200 ) -> crate::common::RegisterField<
2201 15,
2202 0x1,
2203 1,
2204 0,
2205 nmiclr::Cpeclr,
2206 nmiclr::Cpeclr,
2207 Nmiclr_SPEC,
2208 crate::common::RW,
2209 > {
2210 crate::common::RegisterField::<
2211 15,
2212 0x1,
2213 1,
2214 0,
2215 nmiclr::Cpeclr,
2216 nmiclr::Cpeclr,
2217 Nmiclr_SPEC,
2218 crate::common::RW,
2219 >::from_register(self, 0)
2220 }
2221}
2222impl ::core::default::Default for Nmiclr {
2223 #[inline(always)]
2224 fn default() -> Nmiclr {
2225 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
2226 }
2227}
2228pub mod nmiclr {
2229
2230 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2231 pub struct Iwdtclr_SPEC;
2232 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
2233 impl Iwdtclr {
2234 #[doc = "No effect"]
2235 pub const _0: Self = Self::new(0);
2236
2237 #[doc = "Clear the NMISR.IWDTST flag"]
2238 pub const _1: Self = Self::new(1);
2239 }
2240 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2241 pub struct Wdtclr_SPEC;
2242 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
2243 impl Wdtclr {
2244 #[doc = "No effect"]
2245 pub const _0: Self = Self::new(0);
2246
2247 #[doc = "Clear the NMISR.WDTST flag"]
2248 pub const _1: Self = Self::new(1);
2249 }
2250 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2251 pub struct Lvd1Clr_SPEC;
2252 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
2253 impl Lvd1Clr {
2254 #[doc = "No effect"]
2255 pub const _0: Self = Self::new(0);
2256
2257 #[doc = "Clear the NMISR.LVD1ST flag"]
2258 pub const _1: Self = Self::new(1);
2259 }
2260 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2261 pub struct Lvd2Clr_SPEC;
2262 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
2263 impl Lvd2Clr {
2264 #[doc = "No effect"]
2265 pub const _0: Self = Self::new(0);
2266
2267 #[doc = "Clear the NMISR.LVD2ST flag."]
2268 pub const _1: Self = Self::new(1);
2269 }
2270 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2271 pub struct Ostclr_SPEC;
2272 pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
2273 impl Ostclr {
2274 #[doc = "No effect"]
2275 pub const _0: Self = Self::new(0);
2276
2277 #[doc = "Clear the NMISR.OSTST flag"]
2278 pub const _1: Self = Self::new(1);
2279 }
2280 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2281 pub struct Nmiclr_SPEC;
2282 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
2283 impl Nmiclr {
2284 #[doc = "No effect"]
2285 pub const _0: Self = Self::new(0);
2286
2287 #[doc = "Clear the NMISR.NMIST flag"]
2288 pub const _1: Self = Self::new(1);
2289 }
2290 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2291 pub struct Rpeclr_SPEC;
2292 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
2293 impl Rpeclr {
2294 #[doc = "No effect"]
2295 pub const _0: Self = Self::new(0);
2296
2297 #[doc = "Clear the NMISR.RPEST flag"]
2298 pub const _1: Self = Self::new(1);
2299 }
2300 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2301 pub struct Busmclr_SPEC;
2302 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
2303 impl Busmclr {
2304 #[doc = "No effect"]
2305 pub const _0: Self = Self::new(0);
2306
2307 #[doc = "Clear the NMISR.BUSMST flag"]
2308 pub const _1: Self = Self::new(1);
2309 }
2310 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2311 pub struct Tzfclr_SPEC;
2312 pub type Tzfclr = crate::EnumBitfieldStruct<u8, Tzfclr_SPEC>;
2313 impl Tzfclr {
2314 #[doc = "No effect"]
2315 pub const _0: Self = Self::new(0);
2316
2317 #[doc = "Clear the NMISR.TZFCLR flag"]
2318 pub const _1: Self = Self::new(1);
2319 }
2320 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2321 pub struct Cpeclr_SPEC;
2322 pub type Cpeclr = crate::EnumBitfieldStruct<u8, Cpeclr_SPEC>;
2323 impl Cpeclr {
2324 #[doc = "No effect"]
2325 pub const _0: Self = Self::new(0);
2326
2327 #[doc = "Clear the NMISR.CPECLR flag"]
2328 pub const _1: Self = Self::new(1);
2329 }
2330}
2331#[doc(hidden)]
2332#[derive(Copy, Clone, Eq, PartialEq)]
2333pub struct Nmisr_SPEC;
2334impl crate::sealed::RegSpec for Nmisr_SPEC {
2335 type DataType = u16;
2336}
2337
2338#[doc = "Non-Maskable Interrupt Status Register"]
2339pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
2340
2341impl Nmisr {
2342 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag"]
2343 #[inline(always)]
2344 pub fn iwdtst(
2345 self,
2346 ) -> crate::common::RegisterField<
2347 0,
2348 0x1,
2349 1,
2350 0,
2351 nmisr::Iwdtst,
2352 nmisr::Iwdtst,
2353 Nmisr_SPEC,
2354 crate::common::R,
2355 > {
2356 crate::common::RegisterField::<
2357 0,
2358 0x1,
2359 1,
2360 0,
2361 nmisr::Iwdtst,
2362 nmisr::Iwdtst,
2363 Nmisr_SPEC,
2364 crate::common::R,
2365 >::from_register(self, 0)
2366 }
2367
2368 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag"]
2369 #[inline(always)]
2370 pub fn wdtst(
2371 self,
2372 ) -> crate::common::RegisterField<
2373 1,
2374 0x1,
2375 1,
2376 0,
2377 nmisr::Wdtst,
2378 nmisr::Wdtst,
2379 Nmisr_SPEC,
2380 crate::common::R,
2381 > {
2382 crate::common::RegisterField::<
2383 1,
2384 0x1,
2385 1,
2386 0,
2387 nmisr::Wdtst,
2388 nmisr::Wdtst,
2389 Nmisr_SPEC,
2390 crate::common::R,
2391 >::from_register(self, 0)
2392 }
2393
2394 #[doc = "Voltage Monitor 1 Interrupt Status Flag"]
2395 #[inline(always)]
2396 pub fn lvd1st(
2397 self,
2398 ) -> crate::common::RegisterField<
2399 2,
2400 0x1,
2401 1,
2402 0,
2403 nmisr::Lvd1St,
2404 nmisr::Lvd1St,
2405 Nmisr_SPEC,
2406 crate::common::R,
2407 > {
2408 crate::common::RegisterField::<
2409 2,
2410 0x1,
2411 1,
2412 0,
2413 nmisr::Lvd1St,
2414 nmisr::Lvd1St,
2415 Nmisr_SPEC,
2416 crate::common::R,
2417 >::from_register(self, 0)
2418 }
2419
2420 #[doc = "Voltage Monitor 2 Interrupt Status Flag"]
2421 #[inline(always)]
2422 pub fn lvd2st(
2423 self,
2424 ) -> crate::common::RegisterField<
2425 3,
2426 0x1,
2427 1,
2428 0,
2429 nmisr::Lvd2St,
2430 nmisr::Lvd2St,
2431 Nmisr_SPEC,
2432 crate::common::R,
2433 > {
2434 crate::common::RegisterField::<
2435 3,
2436 0x1,
2437 1,
2438 0,
2439 nmisr::Lvd2St,
2440 nmisr::Lvd2St,
2441 Nmisr_SPEC,
2442 crate::common::R,
2443 >::from_register(self, 0)
2444 }
2445
2446 #[doc = "Main Clock Oscillation Stop Detection Interrupt Status Flag"]
2447 #[inline(always)]
2448 pub fn ostst(
2449 self,
2450 ) -> crate::common::RegisterField<
2451 6,
2452 0x1,
2453 1,
2454 0,
2455 nmisr::Ostst,
2456 nmisr::Ostst,
2457 Nmisr_SPEC,
2458 crate::common::R,
2459 > {
2460 crate::common::RegisterField::<
2461 6,
2462 0x1,
2463 1,
2464 0,
2465 nmisr::Ostst,
2466 nmisr::Ostst,
2467 Nmisr_SPEC,
2468 crate::common::R,
2469 >::from_register(self, 0)
2470 }
2471
2472 #[doc = "NMI Pin Interrupt Status Flag"]
2473 #[inline(always)]
2474 pub fn nmist(
2475 self,
2476 ) -> crate::common::RegisterField<
2477 7,
2478 0x1,
2479 1,
2480 0,
2481 nmisr::Nmist,
2482 nmisr::Nmist,
2483 Nmisr_SPEC,
2484 crate::common::R,
2485 > {
2486 crate::common::RegisterField::<
2487 7,
2488 0x1,
2489 1,
2490 0,
2491 nmisr::Nmist,
2492 nmisr::Nmist,
2493 Nmisr_SPEC,
2494 crate::common::R,
2495 >::from_register(self, 0)
2496 }
2497
2498 #[doc = "SRAM Parity Error Interrupt Status Flag"]
2499 #[inline(always)]
2500 pub fn rpest(
2501 self,
2502 ) -> crate::common::RegisterField<
2503 8,
2504 0x1,
2505 1,
2506 0,
2507 nmisr::Rpest,
2508 nmisr::Rpest,
2509 Nmisr_SPEC,
2510 crate::common::R,
2511 > {
2512 crate::common::RegisterField::<
2513 8,
2514 0x1,
2515 1,
2516 0,
2517 nmisr::Rpest,
2518 nmisr::Rpest,
2519 Nmisr_SPEC,
2520 crate::common::R,
2521 >::from_register(self, 0)
2522 }
2523
2524 #[doc = "Bus Master MPU Error Interrupt Status Flag"]
2525 #[inline(always)]
2526 pub fn busmst(
2527 self,
2528 ) -> crate::common::RegisterField<
2529 11,
2530 0x1,
2531 1,
2532 0,
2533 nmisr::Busmst,
2534 nmisr::Busmst,
2535 Nmisr_SPEC,
2536 crate::common::R,
2537 > {
2538 crate::common::RegisterField::<
2539 11,
2540 0x1,
2541 1,
2542 0,
2543 nmisr::Busmst,
2544 nmisr::Busmst,
2545 Nmisr_SPEC,
2546 crate::common::R,
2547 >::from_register(self, 0)
2548 }
2549
2550 #[inline(always)]
2551 pub fn tzfst(
2552 self,
2553 ) -> crate::common::RegisterField<
2554 13,
2555 0x1,
2556 1,
2557 0,
2558 nmisr::Tzfst,
2559 nmisr::Tzfst,
2560 Nmisr_SPEC,
2561 crate::common::R,
2562 > {
2563 crate::common::RegisterField::<
2564 13,
2565 0x1,
2566 1,
2567 0,
2568 nmisr::Tzfst,
2569 nmisr::Tzfst,
2570 Nmisr_SPEC,
2571 crate::common::R,
2572 >::from_register(self, 0)
2573 }
2574
2575 #[inline(always)]
2576 pub fn cpest(
2577 self,
2578 ) -> crate::common::RegisterField<
2579 15,
2580 0x1,
2581 1,
2582 0,
2583 nmisr::Cpest,
2584 nmisr::Cpest,
2585 Nmisr_SPEC,
2586 crate::common::R,
2587 > {
2588 crate::common::RegisterField::<
2589 15,
2590 0x1,
2591 1,
2592 0,
2593 nmisr::Cpest,
2594 nmisr::Cpest,
2595 Nmisr_SPEC,
2596 crate::common::R,
2597 >::from_register(self, 0)
2598 }
2599}
2600impl ::core::default::Default for Nmisr {
2601 #[inline(always)]
2602 fn default() -> Nmisr {
2603 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
2604 }
2605}
2606pub mod nmisr {
2607
2608 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2609 pub struct Iwdtst_SPEC;
2610 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
2611 impl Iwdtst {
2612 #[doc = "Interrupt not requested"]
2613 pub const _0: Self = Self::new(0);
2614
2615 #[doc = "Interrupt requested"]
2616 pub const _1: Self = Self::new(1);
2617 }
2618 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2619 pub struct Wdtst_SPEC;
2620 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
2621 impl Wdtst {
2622 #[doc = "Interrupt not requested"]
2623 pub const _0: Self = Self::new(0);
2624
2625 #[doc = "Interrupt requested"]
2626 pub const _1: Self = Self::new(1);
2627 }
2628 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2629 pub struct Lvd1St_SPEC;
2630 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
2631 impl Lvd1St {
2632 #[doc = "Interrupt not requested"]
2633 pub const _0: Self = Self::new(0);
2634
2635 #[doc = "Interrupt requested"]
2636 pub const _1: Self = Self::new(1);
2637 }
2638 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2639 pub struct Lvd2St_SPEC;
2640 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
2641 impl Lvd2St {
2642 #[doc = "Interrupt not requested"]
2643 pub const _0: Self = Self::new(0);
2644
2645 #[doc = "Interrupt requested"]
2646 pub const _1: Self = Self::new(1);
2647 }
2648 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2649 pub struct Ostst_SPEC;
2650 pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
2651 impl Ostst {
2652 #[doc = "Interrupt not requested for main clock oscillation stop"]
2653 pub const _0: Self = Self::new(0);
2654
2655 #[doc = "Interrupt requested for main clock oscillation stop"]
2656 pub const _1: Self = Self::new(1);
2657 }
2658 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2659 pub struct Nmist_SPEC;
2660 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
2661 impl Nmist {
2662 #[doc = "Interrupt not requested"]
2663 pub const _0: Self = Self::new(0);
2664
2665 #[doc = "Interrupt requested"]
2666 pub const _1: Self = Self::new(1);
2667 }
2668 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2669 pub struct Rpest_SPEC;
2670 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
2671 impl Rpest {
2672 #[doc = "Interrupt not requested"]
2673 pub const _0: Self = Self::new(0);
2674
2675 #[doc = "Interrupt requested"]
2676 pub const _1: Self = Self::new(1);
2677 }
2678 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2679 pub struct Busmst_SPEC;
2680 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
2681 impl Busmst {
2682 #[doc = "Interrupt not requested"]
2683 pub const _0: Self = Self::new(0);
2684
2685 #[doc = "Interrupt requested"]
2686 pub const _1: Self = Self::new(1);
2687 }
2688 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2689 pub struct Tzfst_SPEC;
2690 pub type Tzfst = crate::EnumBitfieldStruct<u8, Tzfst_SPEC>;
2691 impl Tzfst {
2692 #[doc = "Interrupt not requested"]
2693 pub const _0: Self = Self::new(0);
2694
2695 #[doc = "Interrupt requested"]
2696 pub const _1: Self = Self::new(1);
2697 }
2698 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2699 pub struct Cpest_SPEC;
2700 pub type Cpest = crate::EnumBitfieldStruct<u8, Cpest_SPEC>;
2701 impl Cpest {
2702 #[doc = "Interrupt not requested"]
2703 pub const _0: Self = Self::new(0);
2704
2705 #[doc = "Interrupt requested"]
2706 pub const _1: Self = Self::new(1);
2707 }
2708}
2709#[doc(hidden)]
2710#[derive(Copy, Clone, Eq, PartialEq)]
2711pub struct Wupen0_SPEC;
2712impl crate::sealed::RegSpec for Wupen0_SPEC {
2713 type DataType = u32;
2714}
2715
2716#[doc = "Wake Up Interrupt Enable Register 0"]
2717pub type Wupen0 = crate::RegValueT<Wupen0_SPEC>;
2718
2719impl Wupen0 {
2720 #[doc = "IRQn Interrupt Software Standby/Snooze Mode Returns Enable bit (n = 0 to 15)"]
2721 #[inline(always)]
2722 pub fn irqwupen(
2723 self,
2724 ) -> crate::common::RegisterField<
2725 0,
2726 0xffff,
2727 1,
2728 0,
2729 wupen0::Irqwupen,
2730 wupen0::Irqwupen,
2731 Wupen0_SPEC,
2732 crate::common::RW,
2733 > {
2734 crate::common::RegisterField::<
2735 0,
2736 0xffff,
2737 1,
2738 0,
2739 wupen0::Irqwupen,
2740 wupen0::Irqwupen,
2741 Wupen0_SPEC,
2742 crate::common::RW,
2743 >::from_register(self, 0)
2744 }
2745
2746 #[doc = "IWDT Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2747 #[inline(always)]
2748 pub fn iwdtwupen(
2749 self,
2750 ) -> crate::common::RegisterField<
2751 16,
2752 0x1,
2753 1,
2754 0,
2755 wupen0::Iwdtwupen,
2756 wupen0::Iwdtwupen,
2757 Wupen0_SPEC,
2758 crate::common::RW,
2759 > {
2760 crate::common::RegisterField::<
2761 16,
2762 0x1,
2763 1,
2764 0,
2765 wupen0::Iwdtwupen,
2766 wupen0::Iwdtwupen,
2767 Wupen0_SPEC,
2768 crate::common::RW,
2769 >::from_register(self, 0)
2770 }
2771
2772 #[doc = "LVD1 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2773 #[inline(always)]
2774 pub fn lvd1wupen(
2775 self,
2776 ) -> crate::common::RegisterField<
2777 18,
2778 0x1,
2779 1,
2780 0,
2781 wupen0::Lvd1Wupen,
2782 wupen0::Lvd1Wupen,
2783 Wupen0_SPEC,
2784 crate::common::RW,
2785 > {
2786 crate::common::RegisterField::<
2787 18,
2788 0x1,
2789 1,
2790 0,
2791 wupen0::Lvd1Wupen,
2792 wupen0::Lvd1Wupen,
2793 Wupen0_SPEC,
2794 crate::common::RW,
2795 >::from_register(self, 0)
2796 }
2797
2798 #[doc = "LVD2 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2799 #[inline(always)]
2800 pub fn lvd2wupen(
2801 self,
2802 ) -> crate::common::RegisterField<
2803 19,
2804 0x1,
2805 1,
2806 0,
2807 wupen0::Lvd2Wupen,
2808 wupen0::Lvd2Wupen,
2809 Wupen0_SPEC,
2810 crate::common::RW,
2811 > {
2812 crate::common::RegisterField::<
2813 19,
2814 0x1,
2815 1,
2816 0,
2817 wupen0::Lvd2Wupen,
2818 wupen0::Lvd2Wupen,
2819 Wupen0_SPEC,
2820 crate::common::RW,
2821 >::from_register(self, 0)
2822 }
2823
2824 #[doc = "RTC Alarm Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2825 #[inline(always)]
2826 pub fn rtcalmwupen(
2827 self,
2828 ) -> crate::common::RegisterField<
2829 24,
2830 0x1,
2831 1,
2832 0,
2833 wupen0::Rtcalmwupen,
2834 wupen0::Rtcalmwupen,
2835 Wupen0_SPEC,
2836 crate::common::RW,
2837 > {
2838 crate::common::RegisterField::<
2839 24,
2840 0x1,
2841 1,
2842 0,
2843 wupen0::Rtcalmwupen,
2844 wupen0::Rtcalmwupen,
2845 Wupen0_SPEC,
2846 crate::common::RW,
2847 >::from_register(self, 0)
2848 }
2849
2850 #[doc = "RTC Period Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2851 #[inline(always)]
2852 pub fn rtcprdwupen(
2853 self,
2854 ) -> crate::common::RegisterField<
2855 25,
2856 0x1,
2857 1,
2858 0,
2859 wupen0::Rtcprdwupen,
2860 wupen0::Rtcprdwupen,
2861 Wupen0_SPEC,
2862 crate::common::RW,
2863 > {
2864 crate::common::RegisterField::<
2865 25,
2866 0x1,
2867 1,
2868 0,
2869 wupen0::Rtcprdwupen,
2870 wupen0::Rtcprdwupen,
2871 Wupen0_SPEC,
2872 crate::common::RW,
2873 >::from_register(self, 0)
2874 }
2875
2876 #[doc = "USBFS0 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2877 #[inline(always)]
2878 pub fn usbfs0wupen(
2879 self,
2880 ) -> crate::common::RegisterField<
2881 27,
2882 0x1,
2883 1,
2884 0,
2885 wupen0::Usbfs0Wupen,
2886 wupen0::Usbfs0Wupen,
2887 Wupen0_SPEC,
2888 crate::common::RW,
2889 > {
2890 crate::common::RegisterField::<
2891 27,
2892 0x1,
2893 1,
2894 0,
2895 wupen0::Usbfs0Wupen,
2896 wupen0::Usbfs0Wupen,
2897 Wupen0_SPEC,
2898 crate::common::RW,
2899 >::from_register(self, 0)
2900 }
2901
2902 #[doc = "AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2903 #[inline(always)]
2904 pub fn agt1udwupen(
2905 self,
2906 ) -> crate::common::RegisterField<
2907 28,
2908 0x1,
2909 1,
2910 0,
2911 wupen0::Agt1Udwupen,
2912 wupen0::Agt1Udwupen,
2913 Wupen0_SPEC,
2914 crate::common::RW,
2915 > {
2916 crate::common::RegisterField::<
2917 28,
2918 0x1,
2919 1,
2920 0,
2921 wupen0::Agt1Udwupen,
2922 wupen0::Agt1Udwupen,
2923 Wupen0_SPEC,
2924 crate::common::RW,
2925 >::from_register(self, 0)
2926 }
2927
2928 #[doc = "AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2929 #[inline(always)]
2930 pub fn agt1cawupen(
2931 self,
2932 ) -> crate::common::RegisterField<
2933 29,
2934 0x1,
2935 1,
2936 0,
2937 wupen0::Agt1Cawupen,
2938 wupen0::Agt1Cawupen,
2939 Wupen0_SPEC,
2940 crate::common::RW,
2941 > {
2942 crate::common::RegisterField::<
2943 29,
2944 0x1,
2945 1,
2946 0,
2947 wupen0::Agt1Cawupen,
2948 wupen0::Agt1Cawupen,
2949 Wupen0_SPEC,
2950 crate::common::RW,
2951 >::from_register(self, 0)
2952 }
2953
2954 #[doc = "AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2955 #[inline(always)]
2956 pub fn agt1cbwupen(
2957 self,
2958 ) -> crate::common::RegisterField<
2959 30,
2960 0x1,
2961 1,
2962 0,
2963 wupen0::Agt1Cbwupen,
2964 wupen0::Agt1Cbwupen,
2965 Wupen0_SPEC,
2966 crate::common::RW,
2967 > {
2968 crate::common::RegisterField::<
2969 30,
2970 0x1,
2971 1,
2972 0,
2973 wupen0::Agt1Cbwupen,
2974 wupen0::Agt1Cbwupen,
2975 Wupen0_SPEC,
2976 crate::common::RW,
2977 >::from_register(self, 0)
2978 }
2979
2980 #[doc = "IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2981 #[inline(always)]
2982 pub fn iic0wupen(
2983 self,
2984 ) -> crate::common::RegisterField<
2985 31,
2986 0x1,
2987 1,
2988 0,
2989 wupen0::Iic0Wupen,
2990 wupen0::Iic0Wupen,
2991 Wupen0_SPEC,
2992 crate::common::RW,
2993 > {
2994 crate::common::RegisterField::<
2995 31,
2996 0x1,
2997 1,
2998 0,
2999 wupen0::Iic0Wupen,
3000 wupen0::Iic0Wupen,
3001 Wupen0_SPEC,
3002 crate::common::RW,
3003 >::from_register(self, 0)
3004 }
3005}
3006impl ::core::default::Default for Wupen0 {
3007 #[inline(always)]
3008 fn default() -> Wupen0 {
3009 <crate::RegValueT<Wupen0_SPEC> as RegisterValue<_>>::new(0)
3010 }
3011}
3012pub mod wupen0 {
3013
3014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3015 pub struct Irqwupen_SPEC;
3016 pub type Irqwupen = crate::EnumBitfieldStruct<u8, Irqwupen_SPEC>;
3017 impl Irqwupen {
3018 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt is disabled"]
3019 pub const _0: Self = Self::new(0);
3020
3021 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt is enabled"]
3022 pub const _1: Self = Self::new(1);
3023 }
3024 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3025 pub struct Iwdtwupen_SPEC;
3026 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
3027 impl Iwdtwupen {
3028 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt is disabled"]
3029 pub const _0: Self = Self::new(0);
3030
3031 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt is enabled"]
3032 pub const _1: Self = Self::new(1);
3033 }
3034 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3035 pub struct Lvd1Wupen_SPEC;
3036 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
3037 impl Lvd1Wupen {
3038 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt is disabled"]
3039 pub const _0: Self = Self::new(0);
3040
3041 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt is enabled"]
3042 pub const _1: Self = Self::new(1);
3043 }
3044 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3045 pub struct Lvd2Wupen_SPEC;
3046 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
3047 impl Lvd2Wupen {
3048 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt is disabled"]
3049 pub const _0: Self = Self::new(0);
3050
3051 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt is enabled"]
3052 pub const _1: Self = Self::new(1);
3053 }
3054 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3055 pub struct Rtcalmwupen_SPEC;
3056 pub type Rtcalmwupen = crate::EnumBitfieldStruct<u8, Rtcalmwupen_SPEC>;
3057 impl Rtcalmwupen {
3058 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt is disabled"]
3059 pub const _0: Self = Self::new(0);
3060
3061 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt is enabled"]
3062 pub const _1: Self = Self::new(1);
3063 }
3064 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3065 pub struct Rtcprdwupen_SPEC;
3066 pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
3067 impl Rtcprdwupen {
3068 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt is disabled"]
3069 pub const _0: Self = Self::new(0);
3070
3071 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt is enabled"]
3072 pub const _1: Self = Self::new(1);
3073 }
3074 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3075 pub struct Usbfs0Wupen_SPEC;
3076 pub type Usbfs0Wupen = crate::EnumBitfieldStruct<u8, Usbfs0Wupen_SPEC>;
3077 impl Usbfs0Wupen {
3078 #[doc = "Software Standby/Snooze Mode returns by USBFS0 interrupt is disabled"]
3079 pub const _0: Self = Self::new(0);
3080
3081 #[doc = "Software Standby/Snooze Mode returns by USBFS0 interrupt is enabled"]
3082 pub const _1: Self = Self::new(1);
3083 }
3084 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3085 pub struct Agt1Udwupen_SPEC;
3086 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
3087 impl Agt1Udwupen {
3088 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled"]
3089 pub const _0: Self = Self::new(0);
3090
3091 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled"]
3092 pub const _1: Self = Self::new(1);
3093 }
3094 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3095 pub struct Agt1Cawupen_SPEC;
3096 pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
3097 impl Agt1Cawupen {
3098 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled"]
3099 pub const _0: Self = Self::new(0);
3100
3101 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled"]
3102 pub const _1: Self = Self::new(1);
3103 }
3104 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3105 pub struct Agt1Cbwupen_SPEC;
3106 pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
3107 impl Agt1Cbwupen {
3108 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled"]
3109 pub const _0: Self = Self::new(0);
3110
3111 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled"]
3112 pub const _1: Self = Self::new(1);
3113 }
3114 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3115 pub struct Iic0Wupen_SPEC;
3116 pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
3117 impl Iic0Wupen {
3118 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt is disabled"]
3119 pub const _0: Self = Self::new(0);
3120
3121 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt is enabled"]
3122 pub const _1: Self = Self::new(1);
3123 }
3124}
3125#[doc(hidden)]
3126#[derive(Copy, Clone, Eq, PartialEq)]
3127pub struct Wupen1_SPEC;
3128impl crate::sealed::RegSpec for Wupen1_SPEC {
3129 type DataType = u32;
3130}
3131
3132#[doc = "Wake Up interrupt enable register 1"]
3133pub type Wupen1 = crate::RegValueT<Wupen1_SPEC>;
3134
3135impl Wupen1 {
3136 #[doc = "AGT3 Underflow Interrupt Software Standby Return Enable bit"]
3137 #[inline(always)]
3138 pub fn agt3udwupen(
3139 self,
3140 ) -> crate::common::RegisterField<
3141 0,
3142 0x1,
3143 1,
3144 0,
3145 wupen1::Agt3Udwupen,
3146 wupen1::Agt3Udwupen,
3147 Wupen1_SPEC,
3148 crate::common::RW,
3149 > {
3150 crate::common::RegisterField::<
3151 0,
3152 0x1,
3153 1,
3154 0,
3155 wupen1::Agt3Udwupen,
3156 wupen1::Agt3Udwupen,
3157 Wupen1_SPEC,
3158 crate::common::RW,
3159 >::from_register(self, 0)
3160 }
3161
3162 #[doc = "AGT3 Compare Match A Interrupt Software Standby Return Enable bit"]
3163 #[inline(always)]
3164 pub fn agt3cawupen(
3165 self,
3166 ) -> crate::common::RegisterField<
3167 1,
3168 0x1,
3169 1,
3170 0,
3171 wupen1::Agt3Cawupen,
3172 wupen1::Agt3Cawupen,
3173 Wupen1_SPEC,
3174 crate::common::RW,
3175 > {
3176 crate::common::RegisterField::<
3177 1,
3178 0x1,
3179 1,
3180 0,
3181 wupen1::Agt3Cawupen,
3182 wupen1::Agt3Cawupen,
3183 Wupen1_SPEC,
3184 crate::common::RW,
3185 >::from_register(self, 0)
3186 }
3187
3188 #[doc = "AGT3 Compare Match B Interrupt Software Standby Return Enable bit"]
3189 #[inline(always)]
3190 pub fn agt3cbwupen(
3191 self,
3192 ) -> crate::common::RegisterField<
3193 2,
3194 0x1,
3195 1,
3196 0,
3197 wupen1::Agt3Cbwupen,
3198 wupen1::Agt3Cbwupen,
3199 Wupen1_SPEC,
3200 crate::common::RW,
3201 > {
3202 crate::common::RegisterField::<
3203 2,
3204 0x1,
3205 1,
3206 0,
3207 wupen1::Agt3Cbwupen,
3208 wupen1::Agt3Cbwupen,
3209 Wupen1_SPEC,
3210 crate::common::RW,
3211 >::from_register(self, 0)
3212 }
3213}
3214impl ::core::default::Default for Wupen1 {
3215 #[inline(always)]
3216 fn default() -> Wupen1 {
3217 <crate::RegValueT<Wupen1_SPEC> as RegisterValue<_>>::new(0)
3218 }
3219}
3220pub mod wupen1 {
3221
3222 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3223 pub struct Agt3Udwupen_SPEC;
3224 pub type Agt3Udwupen = crate::EnumBitfieldStruct<u8, Agt3Udwupen_SPEC>;
3225 impl Agt3Udwupen {
3226 #[doc = "Software standby returns by AGT3 underflow interrupt is disabled"]
3227 pub const _0: Self = Self::new(0);
3228
3229 #[doc = "Software standby returns by AGT3 underflow interrupt is enabled"]
3230 pub const _1: Self = Self::new(1);
3231 }
3232 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3233 pub struct Agt3Cawupen_SPEC;
3234 pub type Agt3Cawupen = crate::EnumBitfieldStruct<u8, Agt3Cawupen_SPEC>;
3235 impl Agt3Cawupen {
3236 #[doc = "Software standby returns by AGT3 compare match A interrupt is disabled"]
3237 pub const _0: Self = Self::new(0);
3238
3239 #[doc = "Software standby returns by AGT3 compare match A interrupt is enabled"]
3240 pub const _1: Self = Self::new(1);
3241 }
3242 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3243 pub struct Agt3Cbwupen_SPEC;
3244 pub type Agt3Cbwupen = crate::EnumBitfieldStruct<u8, Agt3Cbwupen_SPEC>;
3245 impl Agt3Cbwupen {
3246 #[doc = "Software standby returns by AGT3 compare match B interrupt is disabled"]
3247 pub const _0: Self = Self::new(0);
3248
3249 #[doc = "Software standby returns by AGT3 compare match B interrupt is enabled"]
3250 pub const _1: Self = Self::new(1);
3251 }
3252}
3253#[doc(hidden)]
3254#[derive(Copy, Clone, Eq, PartialEq)]
3255pub struct Selsr0_SPEC;
3256impl crate::sealed::RegSpec for Selsr0_SPEC {
3257 type DataType = u16;
3258}
3259
3260#[doc = "SYS Event Link Setting Register"]
3261pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
3262
3263impl NoBitfieldReg<Selsr0_SPEC> for Selsr0 {}
3264impl ::core::default::Default for Selsr0 {
3265 #[inline(always)]
3266 fn default() -> Selsr0 {
3267 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
3268 }
3269}
3270
3271#[doc(hidden)]
3272#[derive(Copy, Clone, Eq, PartialEq)]
3273pub struct Delsr_SPEC;
3274impl crate::sealed::RegSpec for Delsr_SPEC {
3275 type DataType = u32;
3276}
3277
3278#[doc = "DMAC Event Link Setting Register %s"]
3279pub type Delsr = crate::RegValueT<Delsr_SPEC>;
3280
3281impl Delsr {
3282 #[doc = "DMAC Event Link Select"]
3283 #[inline(always)]
3284 pub fn dels(
3285 self,
3286 ) -> crate::common::RegisterField<
3287 0,
3288 0x1ff,
3289 1,
3290 0,
3291 delsr::Dels,
3292 delsr::Dels,
3293 Delsr_SPEC,
3294 crate::common::RW,
3295 > {
3296 crate::common::RegisterField::<
3297 0,
3298 0x1ff,
3299 1,
3300 0,
3301 delsr::Dels,
3302 delsr::Dels,
3303 Delsr_SPEC,
3304 crate::common::RW,
3305 >::from_register(self, 0)
3306 }
3307
3308 #[doc = "DMAC Activation Request Status Flag"]
3309 #[inline(always)]
3310 pub fn ir(
3311 self,
3312 ) -> crate::common::RegisterField<
3313 16,
3314 0x1,
3315 1,
3316 0,
3317 delsr::Ir,
3318 delsr::Ir,
3319 Delsr_SPEC,
3320 crate::common::RW,
3321 > {
3322 crate::common::RegisterField::<
3323 16,
3324 0x1,
3325 1,
3326 0,
3327 delsr::Ir,
3328 delsr::Ir,
3329 Delsr_SPEC,
3330 crate::common::RW,
3331 >::from_register(self, 0)
3332 }
3333}
3334impl ::core::default::Default for Delsr {
3335 #[inline(always)]
3336 fn default() -> Delsr {
3337 <crate::RegValueT<Delsr_SPEC> as RegisterValue<_>>::new(0)
3338 }
3339}
3340pub mod delsr {
3341
3342 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3343 pub struct Dels_SPEC;
3344 pub type Dels = crate::EnumBitfieldStruct<u8, Dels_SPEC>;
3345 impl Dels {
3346 #[doc = "Disable interrupts to the associated DMAC module."]
3347 pub const _0_X_00: Self = Self::new(0);
3348
3349 #[doc = "Event signal number to be linked. For details, see ."]
3350 pub const OTHERS: Self = Self::new(0);
3351 }
3352 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3353 pub struct Ir_SPEC;
3354 pub type Ir = crate::EnumBitfieldStruct<u8, Ir_SPEC>;
3355 impl Ir {
3356 #[doc = "No DMAC activation request occurred."]
3357 pub const _0: Self = Self::new(0);
3358
3359 #[doc = "DMAC activation request occurred."]
3360 pub const _1: Self = Self::new(1);
3361 }
3362}
3363#[doc(hidden)]
3364#[derive(Copy, Clone, Eq, PartialEq)]
3365pub struct Ielsr_SPEC;
3366impl crate::sealed::RegSpec for Ielsr_SPEC {
3367 type DataType = u32;
3368}
3369
3370#[doc = "ICU Event Link Setting Register %s"]
3371pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
3372
3373impl NoBitfieldReg<Ielsr_SPEC> for Ielsr {}
3374impl ::core::default::Default for Ielsr {
3375 #[inline(always)]
3376 fn default() -> Ielsr {
3377 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
3378 }
3379}