1#[doc = "Register `SIMR2` reader"]
2pub struct R(crate::R<SIMR2_SPEC>);
3impl core::ops::Deref for R {
4 type Target = crate::R<SIMR2_SPEC>;
5 #[inline(always)]
6 fn deref(&self) -> &Self::Target {
7 &self.0
8 }
9}
10impl From<crate::R<SIMR2_SPEC>> for R {
11 #[inline(always)]
12 fn from(reader: crate::R<SIMR2_SPEC>) -> Self {
13 R(reader)
14 }
15}
16#[doc = "Register `SIMR2` writer"]
17pub struct W(crate::W<SIMR2_SPEC>);
18impl core::ops::Deref for W {
19 type Target = crate::W<SIMR2_SPEC>;
20 #[inline(always)]
21 fn deref(&self) -> &Self::Target {
22 &self.0
23 }
24}
25impl core::ops::DerefMut for W {
26 #[inline(always)]
27 fn deref_mut(&mut self) -> &mut Self::Target {
28 &mut self.0
29 }
30}
31impl From<crate::W<SIMR2_SPEC>> for W {
32 #[inline(always)]
33 fn from(writer: crate::W<SIMR2_SPEC>) -> Self {
34 W(writer)
35 }
36}
37#[doc = "Field `IICINTM` reader - IIC Interrupt Mode Select"]
38pub type IICINTM_R = crate::BitReader<IICINTM_A>;
39#[doc = "IIC Interrupt Mode Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum IICINTM_A {
42 #[doc = "0: Use ACK/NACK interrupts"]
43 _0 = 0,
44 #[doc = "1: Use reception and transmission interrupts"]
45 _1 = 1,
46}
47impl From<IICINTM_A> for bool {
48 #[inline(always)]
49 fn from(variant: IICINTM_A) -> Self {
50 variant as u8 != 0
51 }
52}
53impl IICINTM_R {
54 #[doc = "Get enumerated values variant"]
55 #[inline(always)]
56 pub fn variant(&self) -> IICINTM_A {
57 match self.bits {
58 false => IICINTM_A::_0,
59 true => IICINTM_A::_1,
60 }
61 }
62 #[doc = "Checks if the value of the field is `_0`"]
63 #[inline(always)]
64 pub fn is_0(&self) -> bool {
65 *self == IICINTM_A::_0
66 }
67 #[doc = "Checks if the value of the field is `_1`"]
68 #[inline(always)]
69 pub fn is_1(&self) -> bool {
70 *self == IICINTM_A::_1
71 }
72}
73#[doc = "Field `IICINTM` writer - IIC Interrupt Mode Select"]
74pub type IICINTM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SIMR2_SPEC, IICINTM_A, O>;
75impl<'a, const O: u8> IICINTM_W<'a, O> {
76 #[doc = "Use ACK/NACK interrupts"]
77 #[inline(always)]
78 pub fn _0(self) -> &'a mut W {
79 self.variant(IICINTM_A::_0)
80 }
81 #[doc = "Use reception and transmission interrupts"]
82 #[inline(always)]
83 pub fn _1(self) -> &'a mut W {
84 self.variant(IICINTM_A::_1)
85 }
86}
87#[doc = "Field `IICCSC` reader - Clock Synchronization"]
88pub type IICCSC_R = crate::BitReader<IICCSC_A>;
89#[doc = "Clock Synchronization\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum IICCSC_A {
92 #[doc = "0: Do not synchronize with clock signal"]
93 _0 = 0,
94 #[doc = "1: Synchronize with clock signal"]
95 _1 = 1,
96}
97impl From<IICCSC_A> for bool {
98 #[inline(always)]
99 fn from(variant: IICCSC_A) -> Self {
100 variant as u8 != 0
101 }
102}
103impl IICCSC_R {
104 #[doc = "Get enumerated values variant"]
105 #[inline(always)]
106 pub fn variant(&self) -> IICCSC_A {
107 match self.bits {
108 false => IICCSC_A::_0,
109 true => IICCSC_A::_1,
110 }
111 }
112 #[doc = "Checks if the value of the field is `_0`"]
113 #[inline(always)]
114 pub fn is_0(&self) -> bool {
115 *self == IICCSC_A::_0
116 }
117 #[doc = "Checks if the value of the field is `_1`"]
118 #[inline(always)]
119 pub fn is_1(&self) -> bool {
120 *self == IICCSC_A::_1
121 }
122}
123#[doc = "Field `IICCSC` writer - Clock Synchronization"]
124pub type IICCSC_W<'a, const O: u8> = crate::BitWriter<'a, u8, SIMR2_SPEC, IICCSC_A, O>;
125impl<'a, const O: u8> IICCSC_W<'a, O> {
126 #[doc = "Do not synchronize with clock signal"]
127 #[inline(always)]
128 pub fn _0(self) -> &'a mut W {
129 self.variant(IICCSC_A::_0)
130 }
131 #[doc = "Synchronize with clock signal"]
132 #[inline(always)]
133 pub fn _1(self) -> &'a mut W {
134 self.variant(IICCSC_A::_1)
135 }
136}
137#[doc = "Field `IICACKT` reader - ACK Transmission Data"]
138pub type IICACKT_R = crate::BitReader<IICACKT_A>;
139#[doc = "ACK Transmission Data\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum IICACKT_A {
142 #[doc = "0: ACK transmission"]
143 _0 = 0,
144 #[doc = "1: NACK transmission and ACK/NACK reception"]
145 _1 = 1,
146}
147impl From<IICACKT_A> for bool {
148 #[inline(always)]
149 fn from(variant: IICACKT_A) -> Self {
150 variant as u8 != 0
151 }
152}
153impl IICACKT_R {
154 #[doc = "Get enumerated values variant"]
155 #[inline(always)]
156 pub fn variant(&self) -> IICACKT_A {
157 match self.bits {
158 false => IICACKT_A::_0,
159 true => IICACKT_A::_1,
160 }
161 }
162 #[doc = "Checks if the value of the field is `_0`"]
163 #[inline(always)]
164 pub fn is_0(&self) -> bool {
165 *self == IICACKT_A::_0
166 }
167 #[doc = "Checks if the value of the field is `_1`"]
168 #[inline(always)]
169 pub fn is_1(&self) -> bool {
170 *self == IICACKT_A::_1
171 }
172}
173#[doc = "Field `IICACKT` writer - ACK Transmission Data"]
174pub type IICACKT_W<'a, const O: u8> = crate::BitWriter<'a, u8, SIMR2_SPEC, IICACKT_A, O>;
175impl<'a, const O: u8> IICACKT_W<'a, O> {
176 #[doc = "ACK transmission"]
177 #[inline(always)]
178 pub fn _0(self) -> &'a mut W {
179 self.variant(IICACKT_A::_0)
180 }
181 #[doc = "NACK transmission and ACK/NACK reception"]
182 #[inline(always)]
183 pub fn _1(self) -> &'a mut W {
184 self.variant(IICACKT_A::_1)
185 }
186}
187impl R {
188 #[doc = "Bit 0 - IIC Interrupt Mode Select"]
189 #[inline(always)]
190 pub fn iicintm(&self) -> IICINTM_R {
191 IICINTM_R::new((self.bits & 1) != 0)
192 }
193 #[doc = "Bit 1 - Clock Synchronization"]
194 #[inline(always)]
195 pub fn iiccsc(&self) -> IICCSC_R {
196 IICCSC_R::new(((self.bits >> 1) & 1) != 0)
197 }
198 #[doc = "Bit 5 - ACK Transmission Data"]
199 #[inline(always)]
200 pub fn iicackt(&self) -> IICACKT_R {
201 IICACKT_R::new(((self.bits >> 5) & 1) != 0)
202 }
203}
204impl W {
205 #[doc = "Bit 0 - IIC Interrupt Mode Select"]
206 #[inline(always)]
207 #[must_use]
208 pub fn iicintm(&mut self) -> IICINTM_W<0> {
209 IICINTM_W::new(self)
210 }
211 #[doc = "Bit 1 - Clock Synchronization"]
212 #[inline(always)]
213 #[must_use]
214 pub fn iiccsc(&mut self) -> IICCSC_W<1> {
215 IICCSC_W::new(self)
216 }
217 #[doc = "Bit 5 - ACK Transmission Data"]
218 #[inline(always)]
219 #[must_use]
220 pub fn iicackt(&mut self) -> IICACKT_W<5> {
221 IICACKT_W::new(self)
222 }
223 #[doc = "Writes raw bits to the register."]
224 #[inline(always)]
225 pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
226 self.0.bits(bits);
227 self
228 }
229}
230#[doc = "IIC Mode Register 2\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [simr2](index.html) module"]
231pub struct SIMR2_SPEC;
232impl crate::RegisterSpec for SIMR2_SPEC {
233 type Ux = u8;
234}
235#[doc = "`read()` method returns [simr2::R](R) reader structure"]
236impl crate::Readable for SIMR2_SPEC {
237 type Reader = R;
238}
239#[doc = "`write(|w| ..)` method takes [simr2::W](W) writer structure"]
240impl crate::Writable for SIMR2_SPEC {
241 type Writer = W;
242 const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
243 const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
244}
245#[doc = "`reset()` method sets SIMR2 to value 0"]
246impl crate::Resettable for SIMR2_SPEC {
247 const RESET_VALUE: Self::Ux = 0;
248}