ra4m2/sci0/
spmr.rs

1#[doc = "Register `SPMR` reader"]
2pub struct R(crate::R<SPMR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SPMR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SPMR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SPMR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SPMR` writer"]
17pub struct W(crate::W<SPMR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SPMR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SPMR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SPMR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SSE` reader - SSn Pin Function Enable"]
38pub type SSE_R = crate::BitReader<SSE_A>;
39#[doc = "SSn Pin Function Enable\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SSE_A {
42    #[doc = "0: Disable SSn pin function"]
43    _0 = 0,
44    #[doc = "1: Enable SSn pin function"]
45    _1 = 1,
46}
47impl From<SSE_A> for bool {
48    #[inline(always)]
49    fn from(variant: SSE_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SSE_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SSE_A {
57        match self.bits {
58            false => SSE_A::_0,
59            true => SSE_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == SSE_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == SSE_A::_1
71    }
72}
73#[doc = "Field `SSE` writer - SSn Pin Function Enable"]
74pub type SSE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, SSE_A, O>;
75impl<'a, const O: u8> SSE_W<'a, O> {
76    #[doc = "Disable SSn pin function"]
77    #[inline(always)]
78    pub fn _0(self) -> &'a mut W {
79        self.variant(SSE_A::_0)
80    }
81    #[doc = "Enable SSn pin function"]
82    #[inline(always)]
83    pub fn _1(self) -> &'a mut W {
84        self.variant(SSE_A::_1)
85    }
86}
87#[doc = "Field `CTSE` reader - CTS Enable"]
88pub type CTSE_R = crate::BitReader<CTSE_A>;
89#[doc = "CTS Enable\n\nValue on reset: 0"]
90#[derive(Clone, Copy, Debug, PartialEq, Eq)]
91pub enum CTSE_A {
92    #[doc = "0: Disable CTS function (enable RTS output function)"]
93    _0 = 0,
94    #[doc = "1: Enable CTS function"]
95    _1 = 1,
96}
97impl From<CTSE_A> for bool {
98    #[inline(always)]
99    fn from(variant: CTSE_A) -> Self {
100        variant as u8 != 0
101    }
102}
103impl CTSE_R {
104    #[doc = "Get enumerated values variant"]
105    #[inline(always)]
106    pub fn variant(&self) -> CTSE_A {
107        match self.bits {
108            false => CTSE_A::_0,
109            true => CTSE_A::_1,
110        }
111    }
112    #[doc = "Checks if the value of the field is `_0`"]
113    #[inline(always)]
114    pub fn is_0(&self) -> bool {
115        *self == CTSE_A::_0
116    }
117    #[doc = "Checks if the value of the field is `_1`"]
118    #[inline(always)]
119    pub fn is_1(&self) -> bool {
120        *self == CTSE_A::_1
121    }
122}
123#[doc = "Field `CTSE` writer - CTS Enable"]
124pub type CTSE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, CTSE_A, O>;
125impl<'a, const O: u8> CTSE_W<'a, O> {
126    #[doc = "Disable CTS function (enable RTS output function)"]
127    #[inline(always)]
128    pub fn _0(self) -> &'a mut W {
129        self.variant(CTSE_A::_0)
130    }
131    #[doc = "Enable CTS function"]
132    #[inline(always)]
133    pub fn _1(self) -> &'a mut W {
134        self.variant(CTSE_A::_1)
135    }
136}
137#[doc = "Field `MSS` reader - Master Slave Select"]
138pub type MSS_R = crate::BitReader<MSS_A>;
139#[doc = "Master Slave Select\n\nValue on reset: 0"]
140#[derive(Clone, Copy, Debug, PartialEq, Eq)]
141pub enum MSS_A {
142    #[doc = "0: Transmit through TXDn pin and receive through RXDn pin (master mode)"]
143    _0 = 0,
144    #[doc = "1: Receive through TXDn pin and transmit through RXDn pin (slave mode)"]
145    _1 = 1,
146}
147impl From<MSS_A> for bool {
148    #[inline(always)]
149    fn from(variant: MSS_A) -> Self {
150        variant as u8 != 0
151    }
152}
153impl MSS_R {
154    #[doc = "Get enumerated values variant"]
155    #[inline(always)]
156    pub fn variant(&self) -> MSS_A {
157        match self.bits {
158            false => MSS_A::_0,
159            true => MSS_A::_1,
160        }
161    }
162    #[doc = "Checks if the value of the field is `_0`"]
163    #[inline(always)]
164    pub fn is_0(&self) -> bool {
165        *self == MSS_A::_0
166    }
167    #[doc = "Checks if the value of the field is `_1`"]
168    #[inline(always)]
169    pub fn is_1(&self) -> bool {
170        *self == MSS_A::_1
171    }
172}
173#[doc = "Field `MSS` writer - Master Slave Select"]
174pub type MSS_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, MSS_A, O>;
175impl<'a, const O: u8> MSS_W<'a, O> {
176    #[doc = "Transmit through TXDn pin and receive through RXDn pin (master mode)"]
177    #[inline(always)]
178    pub fn _0(self) -> &'a mut W {
179        self.variant(MSS_A::_0)
180    }
181    #[doc = "Receive through TXDn pin and transmit through RXDn pin (slave mode)"]
182    #[inline(always)]
183    pub fn _1(self) -> &'a mut W {
184        self.variant(MSS_A::_1)
185    }
186}
187#[doc = "Field `CSTPEN` reader - CTS external pin Enable"]
188pub type CSTPEN_R = crate::BitReader<CSTPEN_A>;
189#[doc = "CTS external pin Enable\n\nValue on reset: 0"]
190#[derive(Clone, Copy, Debug, PartialEq, Eq)]
191pub enum CSTPEN_A {
192    #[doc = "0: Alternate setting to use CTS and RTS functions as either one terminal"]
193    _0 = 0,
194    #[doc = "1: Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
195    _1 = 1,
196}
197impl From<CSTPEN_A> for bool {
198    #[inline(always)]
199    fn from(variant: CSTPEN_A) -> Self {
200        variant as u8 != 0
201    }
202}
203impl CSTPEN_R {
204    #[doc = "Get enumerated values variant"]
205    #[inline(always)]
206    pub fn variant(&self) -> CSTPEN_A {
207        match self.bits {
208            false => CSTPEN_A::_0,
209            true => CSTPEN_A::_1,
210        }
211    }
212    #[doc = "Checks if the value of the field is `_0`"]
213    #[inline(always)]
214    pub fn is_0(&self) -> bool {
215        *self == CSTPEN_A::_0
216    }
217    #[doc = "Checks if the value of the field is `_1`"]
218    #[inline(always)]
219    pub fn is_1(&self) -> bool {
220        *self == CSTPEN_A::_1
221    }
222}
223#[doc = "Field `CSTPEN` writer - CTS external pin Enable"]
224pub type CSTPEN_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, CSTPEN_A, O>;
225impl<'a, const O: u8> CSTPEN_W<'a, O> {
226    #[doc = "Alternate setting to use CTS and RTS functions as either one terminal"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(CSTPEN_A::_0)
230    }
231    #[doc = "Dedicated setting for separately using CTS and RTS functions with 2 terminals These bits for the other SCI channels than SCIn (n = 0, 3, 4, 9) are reserved."]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(CSTPEN_A::_1)
235    }
236}
237#[doc = "Field `MFF` reader - Mode Fault Flag"]
238pub type MFF_R = crate::BitReader<MFF_A>;
239#[doc = "Mode Fault Flag\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq, Eq)]
241pub enum MFF_A {
242    #[doc = "0: No mode fault error"]
243    _0 = 0,
244    #[doc = "1: Mode fault error"]
245    _1 = 1,
246}
247impl From<MFF_A> for bool {
248    #[inline(always)]
249    fn from(variant: MFF_A) -> Self {
250        variant as u8 != 0
251    }
252}
253impl MFF_R {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub fn variant(&self) -> MFF_A {
257        match self.bits {
258            false => MFF_A::_0,
259            true => MFF_A::_1,
260        }
261    }
262    #[doc = "Checks if the value of the field is `_0`"]
263    #[inline(always)]
264    pub fn is_0(&self) -> bool {
265        *self == MFF_A::_0
266    }
267    #[doc = "Checks if the value of the field is `_1`"]
268    #[inline(always)]
269    pub fn is_1(&self) -> bool {
270        *self == MFF_A::_1
271    }
272}
273#[doc = "Field `MFF` writer - Mode Fault Flag"]
274pub type MFF_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, MFF_A, O>;
275impl<'a, const O: u8> MFF_W<'a, O> {
276    #[doc = "No mode fault error"]
277    #[inline(always)]
278    pub fn _0(self) -> &'a mut W {
279        self.variant(MFF_A::_0)
280    }
281    #[doc = "Mode fault error"]
282    #[inline(always)]
283    pub fn _1(self) -> &'a mut W {
284        self.variant(MFF_A::_1)
285    }
286}
287#[doc = "Field `CKPOL` reader - Clock Polarity Select"]
288pub type CKPOL_R = crate::BitReader<CKPOL_A>;
289#[doc = "Clock Polarity Select\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum CKPOL_A {
292    #[doc = "0: Do not invert clock polarity"]
293    _0 = 0,
294    #[doc = "1: Invert clock polarity"]
295    _1 = 1,
296}
297impl From<CKPOL_A> for bool {
298    #[inline(always)]
299    fn from(variant: CKPOL_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl CKPOL_R {
304    #[doc = "Get enumerated values variant"]
305    #[inline(always)]
306    pub fn variant(&self) -> CKPOL_A {
307        match self.bits {
308            false => CKPOL_A::_0,
309            true => CKPOL_A::_1,
310        }
311    }
312    #[doc = "Checks if the value of the field is `_0`"]
313    #[inline(always)]
314    pub fn is_0(&self) -> bool {
315        *self == CKPOL_A::_0
316    }
317    #[doc = "Checks if the value of the field is `_1`"]
318    #[inline(always)]
319    pub fn is_1(&self) -> bool {
320        *self == CKPOL_A::_1
321    }
322}
323#[doc = "Field `CKPOL` writer - Clock Polarity Select"]
324pub type CKPOL_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, CKPOL_A, O>;
325impl<'a, const O: u8> CKPOL_W<'a, O> {
326    #[doc = "Do not invert clock polarity"]
327    #[inline(always)]
328    pub fn _0(self) -> &'a mut W {
329        self.variant(CKPOL_A::_0)
330    }
331    #[doc = "Invert clock polarity"]
332    #[inline(always)]
333    pub fn _1(self) -> &'a mut W {
334        self.variant(CKPOL_A::_1)
335    }
336}
337#[doc = "Field `CKPH` reader - Clock Phase Select"]
338pub type CKPH_R = crate::BitReader<CKPH_A>;
339#[doc = "Clock Phase Select\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum CKPH_A {
342    #[doc = "0: Do not delay clock"]
343    _0 = 0,
344    #[doc = "1: Delay clock"]
345    _1 = 1,
346}
347impl From<CKPH_A> for bool {
348    #[inline(always)]
349    fn from(variant: CKPH_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl CKPH_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub fn variant(&self) -> CKPH_A {
357        match self.bits {
358            false => CKPH_A::_0,
359            true => CKPH_A::_1,
360        }
361    }
362    #[doc = "Checks if the value of the field is `_0`"]
363    #[inline(always)]
364    pub fn is_0(&self) -> bool {
365        *self == CKPH_A::_0
366    }
367    #[doc = "Checks if the value of the field is `_1`"]
368    #[inline(always)]
369    pub fn is_1(&self) -> bool {
370        *self == CKPH_A::_1
371    }
372}
373#[doc = "Field `CKPH` writer - Clock Phase Select"]
374pub type CKPH_W<'a, const O: u8> = crate::BitWriter<'a, u8, SPMR_SPEC, CKPH_A, O>;
375impl<'a, const O: u8> CKPH_W<'a, O> {
376    #[doc = "Do not delay clock"]
377    #[inline(always)]
378    pub fn _0(self) -> &'a mut W {
379        self.variant(CKPH_A::_0)
380    }
381    #[doc = "Delay clock"]
382    #[inline(always)]
383    pub fn _1(self) -> &'a mut W {
384        self.variant(CKPH_A::_1)
385    }
386}
387impl R {
388    #[doc = "Bit 0 - SSn Pin Function Enable"]
389    #[inline(always)]
390    pub fn sse(&self) -> SSE_R {
391        SSE_R::new((self.bits & 1) != 0)
392    }
393    #[doc = "Bit 1 - CTS Enable"]
394    #[inline(always)]
395    pub fn ctse(&self) -> CTSE_R {
396        CTSE_R::new(((self.bits >> 1) & 1) != 0)
397    }
398    #[doc = "Bit 2 - Master Slave Select"]
399    #[inline(always)]
400    pub fn mss(&self) -> MSS_R {
401        MSS_R::new(((self.bits >> 2) & 1) != 0)
402    }
403    #[doc = "Bit 3 - CTS external pin Enable"]
404    #[inline(always)]
405    pub fn cstpen(&self) -> CSTPEN_R {
406        CSTPEN_R::new(((self.bits >> 3) & 1) != 0)
407    }
408    #[doc = "Bit 4 - Mode Fault Flag"]
409    #[inline(always)]
410    pub fn mff(&self) -> MFF_R {
411        MFF_R::new(((self.bits >> 4) & 1) != 0)
412    }
413    #[doc = "Bit 6 - Clock Polarity Select"]
414    #[inline(always)]
415    pub fn ckpol(&self) -> CKPOL_R {
416        CKPOL_R::new(((self.bits >> 6) & 1) != 0)
417    }
418    #[doc = "Bit 7 - Clock Phase Select"]
419    #[inline(always)]
420    pub fn ckph(&self) -> CKPH_R {
421        CKPH_R::new(((self.bits >> 7) & 1) != 0)
422    }
423}
424impl W {
425    #[doc = "Bit 0 - SSn Pin Function Enable"]
426    #[inline(always)]
427    #[must_use]
428    pub fn sse(&mut self) -> SSE_W<0> {
429        SSE_W::new(self)
430    }
431    #[doc = "Bit 1 - CTS Enable"]
432    #[inline(always)]
433    #[must_use]
434    pub fn ctse(&mut self) -> CTSE_W<1> {
435        CTSE_W::new(self)
436    }
437    #[doc = "Bit 2 - Master Slave Select"]
438    #[inline(always)]
439    #[must_use]
440    pub fn mss(&mut self) -> MSS_W<2> {
441        MSS_W::new(self)
442    }
443    #[doc = "Bit 3 - CTS external pin Enable"]
444    #[inline(always)]
445    #[must_use]
446    pub fn cstpen(&mut self) -> CSTPEN_W<3> {
447        CSTPEN_W::new(self)
448    }
449    #[doc = "Bit 4 - Mode Fault Flag"]
450    #[inline(always)]
451    #[must_use]
452    pub fn mff(&mut self) -> MFF_W<4> {
453        MFF_W::new(self)
454    }
455    #[doc = "Bit 6 - Clock Polarity Select"]
456    #[inline(always)]
457    #[must_use]
458    pub fn ckpol(&mut self) -> CKPOL_W<6> {
459        CKPOL_W::new(self)
460    }
461    #[doc = "Bit 7 - Clock Phase Select"]
462    #[inline(always)]
463    #[must_use]
464    pub fn ckph(&mut self) -> CKPH_W<7> {
465        CKPH_W::new(self)
466    }
467    #[doc = "Writes raw bits to the register."]
468    #[inline(always)]
469    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
470        self.0.bits(bits);
471        self
472    }
473}
474#[doc = "SPI Mode Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [spmr](index.html) module"]
475pub struct SPMR_SPEC;
476impl crate::RegisterSpec for SPMR_SPEC {
477    type Ux = u8;
478}
479#[doc = "`read()` method returns [spmr::R](R) reader structure"]
480impl crate::Readable for SPMR_SPEC {
481    type Reader = R;
482}
483#[doc = "`write(|w| ..)` method takes [spmr::W](W) writer structure"]
484impl crate::Writable for SPMR_SPEC {
485    type Writer = W;
486    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
487    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
488}
489#[doc = "`reset()` method sets SPMR to value 0"]
490impl crate::Resettable for SPMR_SPEC {
491    const RESET_VALUE: Self::Ux = 0;
492}
ra4m2/sci0/spmr.rs

ra4m2/sci0/
spmr.rs
