ra4m2/sdhi0/
sd_clk_ctrl.rs

1#[doc = "Register `SD_CLK_CTRL` reader"]
2pub struct R(crate::R<SD_CLK_CTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SD_CLK_CTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SD_CLK_CTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SD_CLK_CTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SD_CLK_CTRL` writer"]
17pub struct W(crate::W<SD_CLK_CTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SD_CLK_CTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SD_CLK_CTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SD_CLK_CTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKSEL` reader - SDHI Clock Frequency Select"]
38pub type CLKSEL_R = crate::FieldReader<u8, CLKSEL_A>;
39#[doc = "SDHI Clock Frequency Select\n\nValue on reset: 32"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKSEL_A {
43    #[doc = "255: PCLKB"]
44    _0X_FF = 255,
45    #[doc = "0: PCLKB/2"]
46    _0X00 = 0,
47    #[doc = "1: PCLKB/4"]
48    _0X01 = 1,
49    #[doc = "2: PCLKB/8"]
50    _0X02 = 2,
51    #[doc = "4: PCLKB/16"]
52    _0X04 = 4,
53    #[doc = "8: PCLKB/32"]
54    _0X08 = 8,
55    #[doc = "16: PCLKB/64"]
56    _0X10 = 16,
57    #[doc = "32: PCLKB/128"]
58    _0X20 = 32,
59    #[doc = "64: PCLKB/256"]
60    _0X40 = 64,
61    #[doc = "128: PCLKB/512"]
62    _0X80 = 128,
63}
64impl From<CLKSEL_A> for u8 {
65    #[inline(always)]
66    fn from(variant: CLKSEL_A) -> Self {
67        variant as _
68    }
69}
70impl CLKSEL_R {
71    #[doc = "Get enumerated values variant"]
72    #[inline(always)]
73    pub fn variant(&self) -> Option<CLKSEL_A> {
74        match self.bits {
75            255 => Some(CLKSEL_A::_0X_FF),
76            0 => Some(CLKSEL_A::_0X00),
77            1 => Some(CLKSEL_A::_0X01),
78            2 => Some(CLKSEL_A::_0X02),
79            4 => Some(CLKSEL_A::_0X04),
80            8 => Some(CLKSEL_A::_0X08),
81            16 => Some(CLKSEL_A::_0X10),
82            32 => Some(CLKSEL_A::_0X20),
83            64 => Some(CLKSEL_A::_0X40),
84            128 => Some(CLKSEL_A::_0X80),
85            _ => None,
86        }
87    }
88    #[doc = "Checks if the value of the field is `_0X_FF`"]
89    #[inline(always)]
90    pub fn is_0x_ff(&self) -> bool {
91        *self == CLKSEL_A::_0X_FF
92    }
93    #[doc = "Checks if the value of the field is `_0X00`"]
94    #[inline(always)]
95    pub fn is_0x00(&self) -> bool {
96        *self == CLKSEL_A::_0X00
97    }
98    #[doc = "Checks if the value of the field is `_0X01`"]
99    #[inline(always)]
100    pub fn is_0x01(&self) -> bool {
101        *self == CLKSEL_A::_0X01
102    }
103    #[doc = "Checks if the value of the field is `_0X02`"]
104    #[inline(always)]
105    pub fn is_0x02(&self) -> bool {
106        *self == CLKSEL_A::_0X02
107    }
108    #[doc = "Checks if the value of the field is `_0X04`"]
109    #[inline(always)]
110    pub fn is_0x04(&self) -> bool {
111        *self == CLKSEL_A::_0X04
112    }
113    #[doc = "Checks if the value of the field is `_0X08`"]
114    #[inline(always)]
115    pub fn is_0x08(&self) -> bool {
116        *self == CLKSEL_A::_0X08
117    }
118    #[doc = "Checks if the value of the field is `_0X10`"]
119    #[inline(always)]
120    pub fn is_0x10(&self) -> bool {
121        *self == CLKSEL_A::_0X10
122    }
123    #[doc = "Checks if the value of the field is `_0X20`"]
124    #[inline(always)]
125    pub fn is_0x20(&self) -> bool {
126        *self == CLKSEL_A::_0X20
127    }
128    #[doc = "Checks if the value of the field is `_0X40`"]
129    #[inline(always)]
130    pub fn is_0x40(&self) -> bool {
131        *self == CLKSEL_A::_0X40
132    }
133    #[doc = "Checks if the value of the field is `_0X80`"]
134    #[inline(always)]
135    pub fn is_0x80(&self) -> bool {
136        *self == CLKSEL_A::_0X80
137    }
138}
139#[doc = "Field `CLKSEL` writer - SDHI Clock Frequency Select"]
140pub type CLKSEL_W<'a, const O: u8> =
141    crate::FieldWriter<'a, u32, SD_CLK_CTRL_SPEC, u8, CLKSEL_A, 8, O>;
142impl<'a, const O: u8> CLKSEL_W<'a, O> {
143    #[doc = "PCLKB"]
144    #[inline(always)]
145    pub fn _0x_ff(self) -> &'a mut W {
146        self.variant(CLKSEL_A::_0X_FF)
147    }
148    #[doc = "PCLKB/2"]
149    #[inline(always)]
150    pub fn _0x00(self) -> &'a mut W {
151        self.variant(CLKSEL_A::_0X00)
152    }
153    #[doc = "PCLKB/4"]
154    #[inline(always)]
155    pub fn _0x01(self) -> &'a mut W {
156        self.variant(CLKSEL_A::_0X01)
157    }
158    #[doc = "PCLKB/8"]
159    #[inline(always)]
160    pub fn _0x02(self) -> &'a mut W {
161        self.variant(CLKSEL_A::_0X02)
162    }
163    #[doc = "PCLKB/16"]
164    #[inline(always)]
165    pub fn _0x04(self) -> &'a mut W {
166        self.variant(CLKSEL_A::_0X04)
167    }
168    #[doc = "PCLKB/32"]
169    #[inline(always)]
170    pub fn _0x08(self) -> &'a mut W {
171        self.variant(CLKSEL_A::_0X08)
172    }
173    #[doc = "PCLKB/64"]
174    #[inline(always)]
175    pub fn _0x10(self) -> &'a mut W {
176        self.variant(CLKSEL_A::_0X10)
177    }
178    #[doc = "PCLKB/128"]
179    #[inline(always)]
180    pub fn _0x20(self) -> &'a mut W {
181        self.variant(CLKSEL_A::_0X20)
182    }
183    #[doc = "PCLKB/256"]
184    #[inline(always)]
185    pub fn _0x40(self) -> &'a mut W {
186        self.variant(CLKSEL_A::_0X40)
187    }
188    #[doc = "PCLKB/512"]
189    #[inline(always)]
190    pub fn _0x80(self) -> &'a mut W {
191        self.variant(CLKSEL_A::_0X80)
192    }
193}
194#[doc = "Field `CLKEN` reader - SD/MMC Clock Output Control"]
195pub type CLKEN_R = crate::BitReader<CLKEN_A>;
196#[doc = "SD/MMC Clock Output Control\n\nValue on reset: 0"]
197#[derive(Clone, Copy, Debug, PartialEq, Eq)]
198pub enum CLKEN_A {
199    #[doc = "0: Disable SD/MMC clock output (fix SDnCLK signal low)"]
200    _0 = 0,
201    #[doc = "1: Enable SD/MMC clock output"]
202    _1 = 1,
203}
204impl From<CLKEN_A> for bool {
205    #[inline(always)]
206    fn from(variant: CLKEN_A) -> Self {
207        variant as u8 != 0
208    }
209}
210impl CLKEN_R {
211    #[doc = "Get enumerated values variant"]
212    #[inline(always)]
213    pub fn variant(&self) -> CLKEN_A {
214        match self.bits {
215            false => CLKEN_A::_0,
216            true => CLKEN_A::_1,
217        }
218    }
219    #[doc = "Checks if the value of the field is `_0`"]
220    #[inline(always)]
221    pub fn is_0(&self) -> bool {
222        *self == CLKEN_A::_0
223    }
224    #[doc = "Checks if the value of the field is `_1`"]
225    #[inline(always)]
226    pub fn is_1(&self) -> bool {
227        *self == CLKEN_A::_1
228    }
229}
230#[doc = "Field `CLKEN` writer - SD/MMC Clock Output Control"]
231pub type CLKEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SD_CLK_CTRL_SPEC, CLKEN_A, O>;
232impl<'a, const O: u8> CLKEN_W<'a, O> {
233    #[doc = "Disable SD/MMC clock output (fix SDnCLK signal low)"]
234    #[inline(always)]
235    pub fn _0(self) -> &'a mut W {
236        self.variant(CLKEN_A::_0)
237    }
238    #[doc = "Enable SD/MMC clock output"]
239    #[inline(always)]
240    pub fn _1(self) -> &'a mut W {
241        self.variant(CLKEN_A::_1)
242    }
243}
244#[doc = "Field `CLKCTRLEN` reader - SD/MMC Clock Output Automatic Control Select"]
245pub type CLKCTRLEN_R = crate::BitReader<CLKCTRLEN_A>;
246#[doc = "SD/MMC Clock Output Automatic Control Select\n\nValue on reset: 0"]
247#[derive(Clone, Copy, Debug, PartialEq, Eq)]
248pub enum CLKCTRLEN_A {
249    #[doc = "0: Disable automatic control of SD/MMC clock output"]
250    _0 = 0,
251    #[doc = "1: Enable automatic control of SD/MMC clock output"]
252    _1 = 1,
253}
254impl From<CLKCTRLEN_A> for bool {
255    #[inline(always)]
256    fn from(variant: CLKCTRLEN_A) -> Self {
257        variant as u8 != 0
258    }
259}
260impl CLKCTRLEN_R {
261    #[doc = "Get enumerated values variant"]
262    #[inline(always)]
263    pub fn variant(&self) -> CLKCTRLEN_A {
264        match self.bits {
265            false => CLKCTRLEN_A::_0,
266            true => CLKCTRLEN_A::_1,
267        }
268    }
269    #[doc = "Checks if the value of the field is `_0`"]
270    #[inline(always)]
271    pub fn is_0(&self) -> bool {
272        *self == CLKCTRLEN_A::_0
273    }
274    #[doc = "Checks if the value of the field is `_1`"]
275    #[inline(always)]
276    pub fn is_1(&self) -> bool {
277        *self == CLKCTRLEN_A::_1
278    }
279}
280#[doc = "Field `CLKCTRLEN` writer - SD/MMC Clock Output Automatic Control Select"]
281pub type CLKCTRLEN_W<'a, const O: u8> = crate::BitWriter<'a, u32, SD_CLK_CTRL_SPEC, CLKCTRLEN_A, O>;
282impl<'a, const O: u8> CLKCTRLEN_W<'a, O> {
283    #[doc = "Disable automatic control of SD/MMC clock output"]
284    #[inline(always)]
285    pub fn _0(self) -> &'a mut W {
286        self.variant(CLKCTRLEN_A::_0)
287    }
288    #[doc = "Enable automatic control of SD/MMC clock output"]
289    #[inline(always)]
290    pub fn _1(self) -> &'a mut W {
291        self.variant(CLKCTRLEN_A::_1)
292    }
293}
294impl R {
295    #[doc = "Bits 0:7 - SDHI Clock Frequency Select"]
296    #[inline(always)]
297    pub fn clksel(&self) -> CLKSEL_R {
298        CLKSEL_R::new((self.bits & 0xff) as u8)
299    }
300    #[doc = "Bit 8 - SD/MMC Clock Output Control"]
301    #[inline(always)]
302    pub fn clken(&self) -> CLKEN_R {
303        CLKEN_R::new(((self.bits >> 8) & 1) != 0)
304    }
305    #[doc = "Bit 9 - SD/MMC Clock Output Automatic Control Select"]
306    #[inline(always)]
307    pub fn clkctrlen(&self) -> CLKCTRLEN_R {
308        CLKCTRLEN_R::new(((self.bits >> 9) & 1) != 0)
309    }
310}
311impl W {
312    #[doc = "Bits 0:7 - SDHI Clock Frequency Select"]
313    #[inline(always)]
314    #[must_use]
315    pub fn clksel(&mut self) -> CLKSEL_W<0> {
316        CLKSEL_W::new(self)
317    }
318    #[doc = "Bit 8 - SD/MMC Clock Output Control"]
319    #[inline(always)]
320    #[must_use]
321    pub fn clken(&mut self) -> CLKEN_W<8> {
322        CLKEN_W::new(self)
323    }
324    #[doc = "Bit 9 - SD/MMC Clock Output Automatic Control Select"]
325    #[inline(always)]
326    #[must_use]
327    pub fn clkctrlen(&mut self) -> CLKCTRLEN_W<9> {
328        CLKCTRLEN_W::new(self)
329    }
330    #[doc = "Writes raw bits to the register."]
331    #[inline(always)]
332    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
333        self.0.bits(bits);
334        self
335    }
336}
337#[doc = "SD Clock Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [sd_clk_ctrl](index.html) module"]
338pub struct SD_CLK_CTRL_SPEC;
339impl crate::RegisterSpec for SD_CLK_CTRL_SPEC {
340    type Ux = u32;
341}
342#[doc = "`read()` method returns [sd_clk_ctrl::R](R) reader structure"]
343impl crate::Readable for SD_CLK_CTRL_SPEC {
344    type Reader = R;
345}
346#[doc = "`write(|w| ..)` method takes [sd_clk_ctrl::W](W) writer structure"]
347impl crate::Writable for SD_CLK_CTRL_SPEC {
348    type Writer = W;
349    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
350    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
351}
352#[doc = "`reset()` method sets SD_CLK_CTRL to value 0x20"]
353impl crate::Resettable for SD_CLK_CTRL_SPEC {
354    const RESET_VALUE: Self::Ux = 0x20;
355}
ra4m2/sdhi0/sd_clk_ctrl.rs

ra4m2/sdhi0/
sd_clk_ctrl.rs
