1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"USB 2.0 Full-Speed Module"]
28unsafe impl ::core::marker::Send for super::Usbfs {}
29unsafe impl ::core::marker::Sync for super::Usbfs {}
30impl super::Usbfs {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "System Configuration Control Register"]
38 #[inline(always)]
39 pub const fn syscfg(
40 &self,
41 ) -> &'static crate::common::Reg<self::Syscfg_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Syscfg_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "System Configuration Status Register 0"]
50 #[inline(always)]
51 pub const fn syssts0(
52 &self,
53 ) -> &'static crate::common::Reg<self::Syssts0_SPEC, crate::common::R> {
54 unsafe {
55 crate::common::Reg::<self::Syssts0_SPEC, crate::common::R>::from_ptr(
56 self._svd2pac_as_ptr().add(4usize),
57 )
58 }
59 }
60
61 #[doc = "Device State Control Register 0"]
62 #[inline(always)]
63 pub const fn dvstctr0(
64 &self,
65 ) -> &'static crate::common::Reg<self::Dvstctr0_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Dvstctr0_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(8usize),
69 )
70 }
71 }
72
73 #[doc = "CFIFO Port Register"]
74 #[inline(always)]
75 pub const fn cfifo(&self) -> &'static crate::common::Reg<self::Cfifo_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Cfifo_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(20usize),
79 )
80 }
81 }
82
83 #[doc = "CFIFO Port Register"]
84 #[inline(always)]
85 pub const fn cfifol(
86 &self,
87 ) -> &'static crate::common::Reg<self::Cfifol_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Cfifol_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(20usize),
91 )
92 }
93 }
94
95 #[doc = "D%sFIFO Port Register"]
96 #[inline(always)]
97 pub const fn dfifo(
98 &self,
99 ) -> &'static crate::common::ClusterRegisterArray<
100 crate::common::Reg<self::Dfifo_SPEC, crate::common::RW>,
101 2,
102 0x4,
103 > {
104 unsafe {
105 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x18usize))
106 }
107 }
108 #[inline(always)]
109 pub const fn d0fifo(&self) -> &'static crate::common::Reg<self::Dfifo_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::Dfifo_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(0x18usize),
113 )
114 }
115 }
116 #[inline(always)]
117 pub const fn d1fifo(&self) -> &'static crate::common::Reg<self::Dfifo_SPEC, crate::common::RW> {
118 unsafe {
119 crate::common::Reg::<self::Dfifo_SPEC, crate::common::RW>::from_ptr(
120 self._svd2pac_as_ptr().add(0x1cusize),
121 )
122 }
123 }
124
125 #[doc = "D%sFIFO Port Register"]
126 #[inline(always)]
127 pub const fn dfifol(
128 &self,
129 ) -> &'static crate::common::ClusterRegisterArray<
130 crate::common::Reg<self::Dfifol_SPEC, crate::common::RW>,
131 2,
132 0x4,
133 > {
134 unsafe {
135 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x18usize))
136 }
137 }
138 #[inline(always)]
139 pub const fn d0fifol(
140 &self,
141 ) -> &'static crate::common::Reg<self::Dfifol_SPEC, crate::common::RW> {
142 unsafe {
143 crate::common::Reg::<self::Dfifol_SPEC, crate::common::RW>::from_ptr(
144 self._svd2pac_as_ptr().add(0x18usize),
145 )
146 }
147 }
148 #[inline(always)]
149 pub const fn d1fifol(
150 &self,
151 ) -> &'static crate::common::Reg<self::Dfifol_SPEC, crate::common::RW> {
152 unsafe {
153 crate::common::Reg::<self::Dfifol_SPEC, crate::common::RW>::from_ptr(
154 self._svd2pac_as_ptr().add(0x1cusize),
155 )
156 }
157 }
158
159 #[doc = "CFIFO Port Select Register"]
160 #[inline(always)]
161 pub const fn cfifosel(
162 &self,
163 ) -> &'static crate::common::Reg<self::Cfifosel_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Cfifosel_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(32usize),
167 )
168 }
169 }
170
171 #[doc = "CFIFO Port Control Register"]
172 #[inline(always)]
173 pub const fn cfifoctr(
174 &self,
175 ) -> &'static crate::common::Reg<self::Cfifoctr_SPEC, crate::common::RW> {
176 unsafe {
177 crate::common::Reg::<self::Cfifoctr_SPEC, crate::common::RW>::from_ptr(
178 self._svd2pac_as_ptr().add(34usize),
179 )
180 }
181 }
182
183 #[doc = "D%sFIFO Port Select Register"]
184 #[inline(always)]
185 pub const fn dfifosel(
186 &self,
187 ) -> &'static crate::common::ClusterRegisterArray<
188 crate::common::Reg<self::Dfifosel_SPEC, crate::common::RW>,
189 2,
190 0x4,
191 > {
192 unsafe {
193 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x28usize))
194 }
195 }
196 #[inline(always)]
197 pub const fn d0fifosel(
198 &self,
199 ) -> &'static crate::common::Reg<self::Dfifosel_SPEC, crate::common::RW> {
200 unsafe {
201 crate::common::Reg::<self::Dfifosel_SPEC, crate::common::RW>::from_ptr(
202 self._svd2pac_as_ptr().add(0x28usize),
203 )
204 }
205 }
206 #[inline(always)]
207 pub const fn d1fifosel(
208 &self,
209 ) -> &'static crate::common::Reg<self::Dfifosel_SPEC, crate::common::RW> {
210 unsafe {
211 crate::common::Reg::<self::Dfifosel_SPEC, crate::common::RW>::from_ptr(
212 self._svd2pac_as_ptr().add(0x2cusize),
213 )
214 }
215 }
216
217 #[doc = "D%sFIFO Port Control Register"]
218 #[inline(always)]
219 pub const fn dfifoctr(
220 &self,
221 ) -> &'static crate::common::ClusterRegisterArray<
222 crate::common::Reg<self::Dfifoctr_SPEC, crate::common::RW>,
223 2,
224 0x4,
225 > {
226 unsafe {
227 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x2ausize))
228 }
229 }
230 #[inline(always)]
231 pub const fn d0fifoctr(
232 &self,
233 ) -> &'static crate::common::Reg<self::Dfifoctr_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::Dfifoctr_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(0x2ausize),
237 )
238 }
239 }
240 #[inline(always)]
241 pub const fn d1fifoctr(
242 &self,
243 ) -> &'static crate::common::Reg<self::Dfifoctr_SPEC, crate::common::RW> {
244 unsafe {
245 crate::common::Reg::<self::Dfifoctr_SPEC, crate::common::RW>::from_ptr(
246 self._svd2pac_as_ptr().add(0x2eusize),
247 )
248 }
249 }
250
251 #[doc = "Interrupt Enable Register 0"]
252 #[inline(always)]
253 pub const fn intenb0(
254 &self,
255 ) -> &'static crate::common::Reg<self::Intenb0_SPEC, crate::common::RW> {
256 unsafe {
257 crate::common::Reg::<self::Intenb0_SPEC, crate::common::RW>::from_ptr(
258 self._svd2pac_as_ptr().add(48usize),
259 )
260 }
261 }
262
263 #[doc = "Interrupt Enable Register 1"]
264 #[inline(always)]
265 pub const fn intenb1(
266 &self,
267 ) -> &'static crate::common::Reg<self::Intenb1_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Intenb1_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(50usize),
271 )
272 }
273 }
274
275 #[doc = "BRDY Interrupt Enable Register"]
276 #[inline(always)]
277 pub const fn brdyenb(
278 &self,
279 ) -> &'static crate::common::Reg<self::Brdyenb_SPEC, crate::common::RW> {
280 unsafe {
281 crate::common::Reg::<self::Brdyenb_SPEC, crate::common::RW>::from_ptr(
282 self._svd2pac_as_ptr().add(54usize),
283 )
284 }
285 }
286
287 #[doc = "NRDY Interrupt Enable Register"]
288 #[inline(always)]
289 pub const fn nrdyenb(
290 &self,
291 ) -> &'static crate::common::Reg<self::Nrdyenb_SPEC, crate::common::RW> {
292 unsafe {
293 crate::common::Reg::<self::Nrdyenb_SPEC, crate::common::RW>::from_ptr(
294 self._svd2pac_as_ptr().add(56usize),
295 )
296 }
297 }
298
299 #[doc = "BEMP Interrupt Enable Register"]
300 #[inline(always)]
301 pub const fn bempenb(
302 &self,
303 ) -> &'static crate::common::Reg<self::Bempenb_SPEC, crate::common::RW> {
304 unsafe {
305 crate::common::Reg::<self::Bempenb_SPEC, crate::common::RW>::from_ptr(
306 self._svd2pac_as_ptr().add(58usize),
307 )
308 }
309 }
310
311 #[doc = "SOF Output Configuration Register"]
312 #[inline(always)]
313 pub const fn sofcfg(
314 &self,
315 ) -> &'static crate::common::Reg<self::Sofcfg_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Sofcfg_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(60usize),
319 )
320 }
321 }
322
323 #[doc = "Interrupt Status Register 0"]
324 #[inline(always)]
325 pub const fn intsts0(
326 &self,
327 ) -> &'static crate::common::Reg<self::Intsts0_SPEC, crate::common::RW> {
328 unsafe {
329 crate::common::Reg::<self::Intsts0_SPEC, crate::common::RW>::from_ptr(
330 self._svd2pac_as_ptr().add(64usize),
331 )
332 }
333 }
334
335 #[doc = "Interrupt Status Register 1"]
336 #[inline(always)]
337 pub const fn intsts1(
338 &self,
339 ) -> &'static crate::common::Reg<self::Intsts1_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::Intsts1_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(66usize),
343 )
344 }
345 }
346
347 #[doc = "BRDY Interrupt Status Register"]
348 #[inline(always)]
349 pub const fn brdysts(
350 &self,
351 ) -> &'static crate::common::Reg<self::Brdysts_SPEC, crate::common::RW> {
352 unsafe {
353 crate::common::Reg::<self::Brdysts_SPEC, crate::common::RW>::from_ptr(
354 self._svd2pac_as_ptr().add(70usize),
355 )
356 }
357 }
358
359 #[doc = "NRDY Interrupt Status Register"]
360 #[inline(always)]
361 pub const fn nrdysts(
362 &self,
363 ) -> &'static crate::common::Reg<self::Nrdysts_SPEC, crate::common::RW> {
364 unsafe {
365 crate::common::Reg::<self::Nrdysts_SPEC, crate::common::RW>::from_ptr(
366 self._svd2pac_as_ptr().add(72usize),
367 )
368 }
369 }
370
371 #[doc = "BEMP Interrupt Status Register"]
372 #[inline(always)]
373 pub const fn bempsts(
374 &self,
375 ) -> &'static crate::common::Reg<self::Bempsts_SPEC, crate::common::RW> {
376 unsafe {
377 crate::common::Reg::<self::Bempsts_SPEC, crate::common::RW>::from_ptr(
378 self._svd2pac_as_ptr().add(74usize),
379 )
380 }
381 }
382
383 #[doc = "Frame Number Register"]
384 #[inline(always)]
385 pub const fn frmnum(
386 &self,
387 ) -> &'static crate::common::Reg<self::Frmnum_SPEC, crate::common::RW> {
388 unsafe {
389 crate::common::Reg::<self::Frmnum_SPEC, crate::common::RW>::from_ptr(
390 self._svd2pac_as_ptr().add(76usize),
391 )
392 }
393 }
394
395 #[doc = "Device State Change Register"]
396 #[inline(always)]
397 pub const fn dvchgr(
398 &self,
399 ) -> &'static crate::common::Reg<self::Dvchgr_SPEC, crate::common::RW> {
400 unsafe {
401 crate::common::Reg::<self::Dvchgr_SPEC, crate::common::RW>::from_ptr(
402 self._svd2pac_as_ptr().add(78usize),
403 )
404 }
405 }
406
407 #[doc = "USB Address Register"]
408 #[inline(always)]
409 pub const fn usbaddr(
410 &self,
411 ) -> &'static crate::common::Reg<self::Usbaddr_SPEC, crate::common::RW> {
412 unsafe {
413 crate::common::Reg::<self::Usbaddr_SPEC, crate::common::RW>::from_ptr(
414 self._svd2pac_as_ptr().add(80usize),
415 )
416 }
417 }
418
419 #[doc = "USB Request Type Register"]
420 #[inline(always)]
421 pub const fn usbreq(
422 &self,
423 ) -> &'static crate::common::Reg<self::Usbreq_SPEC, crate::common::RW> {
424 unsafe {
425 crate::common::Reg::<self::Usbreq_SPEC, crate::common::RW>::from_ptr(
426 self._svd2pac_as_ptr().add(84usize),
427 )
428 }
429 }
430
431 #[doc = "USB Request Value Register"]
432 #[inline(always)]
433 pub const fn usbval(
434 &self,
435 ) -> &'static crate::common::Reg<self::Usbval_SPEC, crate::common::RW> {
436 unsafe {
437 crate::common::Reg::<self::Usbval_SPEC, crate::common::RW>::from_ptr(
438 self._svd2pac_as_ptr().add(86usize),
439 )
440 }
441 }
442
443 #[doc = "USB Request Index Register"]
444 #[inline(always)]
445 pub const fn usbindx(
446 &self,
447 ) -> &'static crate::common::Reg<self::Usbindx_SPEC, crate::common::RW> {
448 unsafe {
449 crate::common::Reg::<self::Usbindx_SPEC, crate::common::RW>::from_ptr(
450 self._svd2pac_as_ptr().add(88usize),
451 )
452 }
453 }
454
455 #[doc = "USB Request Length Register"]
456 #[inline(always)]
457 pub const fn usbleng(
458 &self,
459 ) -> &'static crate::common::Reg<self::Usbleng_SPEC, crate::common::RW> {
460 unsafe {
461 crate::common::Reg::<self::Usbleng_SPEC, crate::common::RW>::from_ptr(
462 self._svd2pac_as_ptr().add(90usize),
463 )
464 }
465 }
466
467 #[doc = "DCP Configuration Register"]
468 #[inline(always)]
469 pub const fn dcpcfg(
470 &self,
471 ) -> &'static crate::common::Reg<self::Dcpcfg_SPEC, crate::common::RW> {
472 unsafe {
473 crate::common::Reg::<self::Dcpcfg_SPEC, crate::common::RW>::from_ptr(
474 self._svd2pac_as_ptr().add(92usize),
475 )
476 }
477 }
478
479 #[doc = "DCP Maximum Packet Size Register"]
480 #[inline(always)]
481 pub const fn dcpmaxp(
482 &self,
483 ) -> &'static crate::common::Reg<self::Dcpmaxp_SPEC, crate::common::RW> {
484 unsafe {
485 crate::common::Reg::<self::Dcpmaxp_SPEC, crate::common::RW>::from_ptr(
486 self._svd2pac_as_ptr().add(94usize),
487 )
488 }
489 }
490
491 #[doc = "DCP Control Register"]
492 #[inline(always)]
493 pub const fn dcpctr(
494 &self,
495 ) -> &'static crate::common::Reg<self::Dcpctr_SPEC, crate::common::RW> {
496 unsafe {
497 crate::common::Reg::<self::Dcpctr_SPEC, crate::common::RW>::from_ptr(
498 self._svd2pac_as_ptr().add(96usize),
499 )
500 }
501 }
502
503 #[doc = "Pipe Window Select Register"]
504 #[inline(always)]
505 pub const fn pipesel(
506 &self,
507 ) -> &'static crate::common::Reg<self::Pipesel_SPEC, crate::common::RW> {
508 unsafe {
509 crate::common::Reg::<self::Pipesel_SPEC, crate::common::RW>::from_ptr(
510 self._svd2pac_as_ptr().add(100usize),
511 )
512 }
513 }
514
515 #[doc = "Pipe Configuration Register"]
516 #[inline(always)]
517 pub const fn pipecfg(
518 &self,
519 ) -> &'static crate::common::Reg<self::Pipecfg_SPEC, crate::common::RW> {
520 unsafe {
521 crate::common::Reg::<self::Pipecfg_SPEC, crate::common::RW>::from_ptr(
522 self._svd2pac_as_ptr().add(104usize),
523 )
524 }
525 }
526
527 #[doc = "Pipe Maximum Packet Size Register"]
528 #[inline(always)]
529 pub const fn pipemaxp(
530 &self,
531 ) -> &'static crate::common::Reg<self::Pipemaxp_SPEC, crate::common::RW> {
532 unsafe {
533 crate::common::Reg::<self::Pipemaxp_SPEC, crate::common::RW>::from_ptr(
534 self._svd2pac_as_ptr().add(108usize),
535 )
536 }
537 }
538
539 #[doc = "Pipe Cycle Control Register"]
540 #[inline(always)]
541 pub const fn pipeperi(
542 &self,
543 ) -> &'static crate::common::Reg<self::Pipeperi_SPEC, crate::common::RW> {
544 unsafe {
545 crate::common::Reg::<self::Pipeperi_SPEC, crate::common::RW>::from_ptr(
546 self._svd2pac_as_ptr().add(110usize),
547 )
548 }
549 }
550
551 #[doc = "PIPE%s Control Registers"]
552 #[inline(always)]
553 pub const fn pipectr(
554 &self,
555 ) -> &'static crate::common::ClusterRegisterArray<
556 crate::common::Reg<self::Pipectr_SPEC, crate::common::RW>,
557 4,
558 0x2,
559 > {
560 unsafe {
561 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x7ausize))
562 }
563 }
564 #[inline(always)]
565 pub const fn pipe6ctr(
566 &self,
567 ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
568 unsafe {
569 crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
570 self._svd2pac_as_ptr().add(0x7ausize),
571 )
572 }
573 }
574 #[inline(always)]
575 pub const fn pipe7ctr(
576 &self,
577 ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
578 unsafe {
579 crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
580 self._svd2pac_as_ptr().add(0x7cusize),
581 )
582 }
583 }
584 #[inline(always)]
585 pub const fn pipe8ctr(
586 &self,
587 ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
588 unsafe {
589 crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
590 self._svd2pac_as_ptr().add(0x7eusize),
591 )
592 }
593 }
594 #[inline(always)]
595 pub const fn pipe9ctr(
596 &self,
597 ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
598 unsafe {
599 crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
600 self._svd2pac_as_ptr().add(0x80usize),
601 )
602 }
603 }
604
605 #[doc = "PIPE%s Transaction Counter Enable Register"]
606 #[inline(always)]
607 pub const fn pipetre(
608 &self,
609 ) -> &'static crate::common::ClusterRegisterArray<
610 crate::common::Reg<self::Pipetre_SPEC, crate::common::RW>,
611 5,
612 0x4,
613 > {
614 unsafe {
615 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x90usize))
616 }
617 }
618 #[inline(always)]
619 pub const fn pipe1tre(
620 &self,
621 ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
622 unsafe {
623 crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
624 self._svd2pac_as_ptr().add(0x90usize),
625 )
626 }
627 }
628 #[inline(always)]
629 pub const fn pipe2tre(
630 &self,
631 ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
632 unsafe {
633 crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
634 self._svd2pac_as_ptr().add(0x94usize),
635 )
636 }
637 }
638 #[inline(always)]
639 pub const fn pipe3tre(
640 &self,
641 ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
642 unsafe {
643 crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
644 self._svd2pac_as_ptr().add(0x98usize),
645 )
646 }
647 }
648 #[inline(always)]
649 pub const fn pipe4tre(
650 &self,
651 ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
652 unsafe {
653 crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
654 self._svd2pac_as_ptr().add(0x9cusize),
655 )
656 }
657 }
658 #[inline(always)]
659 pub const fn pipe5tre(
660 &self,
661 ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
662 unsafe {
663 crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
664 self._svd2pac_as_ptr().add(0xa0usize),
665 )
666 }
667 }
668
669 #[doc = "PIPE%s Transaction Counter Register"]
670 #[inline(always)]
671 pub const fn pipetrn(
672 &self,
673 ) -> &'static crate::common::ClusterRegisterArray<
674 crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW>,
675 5,
676 0x4,
677 > {
678 unsafe {
679 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x92usize))
680 }
681 }
682 #[inline(always)]
683 pub const fn pipe1trn(
684 &self,
685 ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
686 unsafe {
687 crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
688 self._svd2pac_as_ptr().add(0x92usize),
689 )
690 }
691 }
692 #[inline(always)]
693 pub const fn pipe2trn(
694 &self,
695 ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
696 unsafe {
697 crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
698 self._svd2pac_as_ptr().add(0x96usize),
699 )
700 }
701 }
702 #[inline(always)]
703 pub const fn pipe3trn(
704 &self,
705 ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
706 unsafe {
707 crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
708 self._svd2pac_as_ptr().add(0x9ausize),
709 )
710 }
711 }
712 #[inline(always)]
713 pub const fn pipe4trn(
714 &self,
715 ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
716 unsafe {
717 crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
718 self._svd2pac_as_ptr().add(0x9eusize),
719 )
720 }
721 }
722 #[inline(always)]
723 pub const fn pipe5trn(
724 &self,
725 ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
726 unsafe {
727 crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
728 self._svd2pac_as_ptr().add(0xa2usize),
729 )
730 }
731 }
732
733 #[doc = "Battery Charging Control Register 1"]
734 #[inline(always)]
735 pub const fn bcctrl1(
736 &self,
737 ) -> &'static crate::common::Reg<self::Bcctrl1_SPEC, crate::common::RW> {
738 unsafe {
739 crate::common::Reg::<self::Bcctrl1_SPEC, crate::common::RW>::from_ptr(
740 self._svd2pac_as_ptr().add(176usize),
741 )
742 }
743 }
744
745 #[doc = "Battery Charging Control Register 2"]
746 #[inline(always)]
747 pub const fn bcctrl2(
748 &self,
749 ) -> &'static crate::common::Reg<self::Bcctrl2_SPEC, crate::common::RW> {
750 unsafe {
751 crate::common::Reg::<self::Bcctrl2_SPEC, crate::common::RW>::from_ptr(
752 self._svd2pac_as_ptr().add(180usize),
753 )
754 }
755 }
756
757 #[doc = "Device Address %s Configuration Register"]
758 #[inline(always)]
759 pub const fn devadd(
760 &self,
761 ) -> &'static crate::common::ClusterRegisterArray<
762 crate::common::Reg<self::Devadd_SPEC, crate::common::RW>,
763 6,
764 0x2,
765 > {
766 unsafe {
767 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xd0usize))
768 }
769 }
770 #[inline(always)]
771 pub const fn devadd0(
772 &self,
773 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
774 unsafe {
775 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
776 self._svd2pac_as_ptr().add(0xd0usize),
777 )
778 }
779 }
780 #[inline(always)]
781 pub const fn devadd1(
782 &self,
783 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
784 unsafe {
785 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
786 self._svd2pac_as_ptr().add(0xd2usize),
787 )
788 }
789 }
790 #[inline(always)]
791 pub const fn devadd2(
792 &self,
793 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
794 unsafe {
795 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
796 self._svd2pac_as_ptr().add(0xd4usize),
797 )
798 }
799 }
800 #[inline(always)]
801 pub const fn devadd3(
802 &self,
803 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
804 unsafe {
805 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
806 self._svd2pac_as_ptr().add(0xd6usize),
807 )
808 }
809 }
810 #[inline(always)]
811 pub const fn devadd4(
812 &self,
813 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
814 unsafe {
815 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
816 self._svd2pac_as_ptr().add(0xd8usize),
817 )
818 }
819 }
820 #[inline(always)]
821 pub const fn devadd5(
822 &self,
823 ) -> &'static crate::common::Reg<self::Devadd_SPEC, crate::common::RW> {
824 unsafe {
825 crate::common::Reg::<self::Devadd_SPEC, crate::common::RW>::from_ptr(
826 self._svd2pac_as_ptr().add(0xdausize),
827 )
828 }
829 }
830
831 #[doc = "PHY Single-ended Receiver Control Register"]
832 #[inline(always)]
833 pub const fn physectrl(
834 &self,
835 ) -> &'static crate::common::Reg<self::Physectrl_SPEC, crate::common::RW> {
836 unsafe {
837 crate::common::Reg::<self::Physectrl_SPEC, crate::common::RW>::from_ptr(
838 self._svd2pac_as_ptr().add(244usize),
839 )
840 }
841 }
842
843 #[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
844 #[inline(always)]
845 pub const fn dpusr0r(
846 &self,
847 ) -> &'static crate::common::Reg<self::Dpusr0R_SPEC, crate::common::RW> {
848 unsafe {
849 crate::common::Reg::<self::Dpusr0R_SPEC, crate::common::RW>::from_ptr(
850 self._svd2pac_as_ptr().add(1024usize),
851 )
852 }
853 }
854
855 #[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
856 #[inline(always)]
857 pub const fn dpusr1r(
858 &self,
859 ) -> &'static crate::common::Reg<self::Dpusr1R_SPEC, crate::common::RW> {
860 unsafe {
861 crate::common::Reg::<self::Dpusr1R_SPEC, crate::common::RW>::from_ptr(
862 self._svd2pac_as_ptr().add(1028usize),
863 )
864 }
865 }
866}
867#[doc(hidden)]
868#[derive(Copy, Clone, Eq, PartialEq)]
869pub struct Syscfg_SPEC;
870impl crate::sealed::RegSpec for Syscfg_SPEC {
871 type DataType = u16;
872}
873
874#[doc = "System Configuration Control Register"]
875pub type Syscfg = crate::RegValueT<Syscfg_SPEC>;
876
877impl Syscfg {
878 #[doc = "USBFS Operation Enable"]
879 #[inline(always)]
880 pub fn usbe(
881 self,
882 ) -> crate::common::RegisterField<
883 0,
884 0x1,
885 1,
886 0,
887 syscfg::Usbe,
888 syscfg::Usbe,
889 Syscfg_SPEC,
890 crate::common::RW,
891 > {
892 crate::common::RegisterField::<
893 0,
894 0x1,
895 1,
896 0,
897 syscfg::Usbe,
898 syscfg::Usbe,
899 Syscfg_SPEC,
900 crate::common::RW,
901 >::from_register(self, 0)
902 }
903
904 #[doc = "D+ Line Resistor Control"]
905 #[inline(always)]
906 pub fn dprpu(
907 self,
908 ) -> crate::common::RegisterField<
909 4,
910 0x1,
911 1,
912 0,
913 syscfg::Dprpu,
914 syscfg::Dprpu,
915 Syscfg_SPEC,
916 crate::common::RW,
917 > {
918 crate::common::RegisterField::<
919 4,
920 0x1,
921 1,
922 0,
923 syscfg::Dprpu,
924 syscfg::Dprpu,
925 Syscfg_SPEC,
926 crate::common::RW,
927 >::from_register(self, 0)
928 }
929
930 #[doc = "D+/D– Line Resistor Control"]
931 #[inline(always)]
932 pub fn drpd(
933 self,
934 ) -> crate::common::RegisterField<
935 5,
936 0x1,
937 1,
938 0,
939 syscfg::Drpd,
940 syscfg::Drpd,
941 Syscfg_SPEC,
942 crate::common::RW,
943 > {
944 crate::common::RegisterField::<
945 5,
946 0x1,
947 1,
948 0,
949 syscfg::Drpd,
950 syscfg::Drpd,
951 Syscfg_SPEC,
952 crate::common::RW,
953 >::from_register(self, 0)
954 }
955
956 #[doc = "Controller Function Select"]
957 #[inline(always)]
958 pub fn dcfm(
959 self,
960 ) -> crate::common::RegisterField<
961 6,
962 0x1,
963 1,
964 0,
965 syscfg::Dcfm,
966 syscfg::Dcfm,
967 Syscfg_SPEC,
968 crate::common::RW,
969 > {
970 crate::common::RegisterField::<
971 6,
972 0x1,
973 1,
974 0,
975 syscfg::Dcfm,
976 syscfg::Dcfm,
977 Syscfg_SPEC,
978 crate::common::RW,
979 >::from_register(self, 0)
980 }
981
982 #[doc = "USB Clock Enable"]
983 #[inline(always)]
984 pub fn scke(
985 self,
986 ) -> crate::common::RegisterField<
987 10,
988 0x1,
989 1,
990 0,
991 syscfg::Scke,
992 syscfg::Scke,
993 Syscfg_SPEC,
994 crate::common::RW,
995 > {
996 crate::common::RegisterField::<
997 10,
998 0x1,
999 1,
1000 0,
1001 syscfg::Scke,
1002 syscfg::Scke,
1003 Syscfg_SPEC,
1004 crate::common::RW,
1005 >::from_register(self, 0)
1006 }
1007}
1008impl ::core::default::Default for Syscfg {
1009 #[inline(always)]
1010 fn default() -> Syscfg {
1011 <crate::RegValueT<Syscfg_SPEC> as RegisterValue<_>>::new(0)
1012 }
1013}
1014pub mod syscfg {
1015
1016 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1017 pub struct Usbe_SPEC;
1018 pub type Usbe = crate::EnumBitfieldStruct<u8, Usbe_SPEC>;
1019 impl Usbe {
1020 #[doc = "Disable"]
1021 pub const _0: Self = Self::new(0);
1022
1023 #[doc = "Enable"]
1024 pub const _1: Self = Self::new(1);
1025 }
1026 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1027 pub struct Dprpu_SPEC;
1028 pub type Dprpu = crate::EnumBitfieldStruct<u8, Dprpu_SPEC>;
1029 impl Dprpu {
1030 #[doc = "Disable line pull-up"]
1031 pub const _0: Self = Self::new(0);
1032
1033 #[doc = "Enable line pull-up"]
1034 pub const _1: Self = Self::new(1);
1035 }
1036 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1037 pub struct Drpd_SPEC;
1038 pub type Drpd = crate::EnumBitfieldStruct<u8, Drpd_SPEC>;
1039 impl Drpd {
1040 #[doc = "Disable line pull-down"]
1041 pub const _0: Self = Self::new(0);
1042
1043 #[doc = "Enable line pull-down"]
1044 pub const _1: Self = Self::new(1);
1045 }
1046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1047 pub struct Dcfm_SPEC;
1048 pub type Dcfm = crate::EnumBitfieldStruct<u8, Dcfm_SPEC>;
1049 impl Dcfm {
1050 #[doc = "Select device controller"]
1051 pub const _0: Self = Self::new(0);
1052
1053 #[doc = "Select host controller"]
1054 pub const _1: Self = Self::new(1);
1055 }
1056 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1057 pub struct Scke_SPEC;
1058 pub type Scke = crate::EnumBitfieldStruct<u8, Scke_SPEC>;
1059 impl Scke {
1060 #[doc = "Stop clock supply to the USBFS"]
1061 pub const _0: Self = Self::new(0);
1062
1063 #[doc = "Enable clock supply to the USBFS"]
1064 pub const _1: Self = Self::new(1);
1065 }
1066}
1067#[doc(hidden)]
1068#[derive(Copy, Clone, Eq, PartialEq)]
1069pub struct Syssts0_SPEC;
1070impl crate::sealed::RegSpec for Syssts0_SPEC {
1071 type DataType = u16;
1072}
1073
1074#[doc = "System Configuration Status Register 0"]
1075pub type Syssts0 = crate::RegValueT<Syssts0_SPEC>;
1076
1077impl Syssts0 {
1078 #[doc = "USB Data Line Status Monitor"]
1079 #[inline(always)]
1080 pub fn lnst(
1081 self,
1082 ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Syssts0_SPEC, crate::common::R> {
1083 crate::common::RegisterField::<0,0x3,1,0,u8,u8,Syssts0_SPEC,crate::common::R>::from_register(self,0)
1084 }
1085
1086 #[doc = "External ID0 Input Pin Monitor"]
1087 #[inline(always)]
1088 pub fn idmon(
1089 self,
1090 ) -> crate::common::RegisterField<
1091 2,
1092 0x1,
1093 1,
1094 0,
1095 syssts0::Idmon,
1096 syssts0::Idmon,
1097 Syssts0_SPEC,
1098 crate::common::R,
1099 > {
1100 crate::common::RegisterField::<
1101 2,
1102 0x1,
1103 1,
1104 0,
1105 syssts0::Idmon,
1106 syssts0::Idmon,
1107 Syssts0_SPEC,
1108 crate::common::R,
1109 >::from_register(self, 0)
1110 }
1111
1112 #[doc = "Active Monitor When the Host Controller Is Selected"]
1113 #[inline(always)]
1114 pub fn sofea(
1115 self,
1116 ) -> crate::common::RegisterField<
1117 5,
1118 0x1,
1119 1,
1120 0,
1121 syssts0::Sofea,
1122 syssts0::Sofea,
1123 Syssts0_SPEC,
1124 crate::common::R,
1125 > {
1126 crate::common::RegisterField::<
1127 5,
1128 0x1,
1129 1,
1130 0,
1131 syssts0::Sofea,
1132 syssts0::Sofea,
1133 Syssts0_SPEC,
1134 crate::common::R,
1135 >::from_register(self, 0)
1136 }
1137
1138 #[doc = "USB Host Sequencer Status Monitor"]
1139 #[inline(always)]
1140 pub fn htact(
1141 self,
1142 ) -> crate::common::RegisterField<
1143 6,
1144 0x1,
1145 1,
1146 0,
1147 syssts0::Htact,
1148 syssts0::Htact,
1149 Syssts0_SPEC,
1150 crate::common::R,
1151 > {
1152 crate::common::RegisterField::<
1153 6,
1154 0x1,
1155 1,
1156 0,
1157 syssts0::Htact,
1158 syssts0::Htact,
1159 Syssts0_SPEC,
1160 crate::common::R,
1161 >::from_register(self, 0)
1162 }
1163
1164 #[doc = "External USB_OVRCURA/ USB_OVRCURB Input Pin Monitor"]
1165 #[inline(always)]
1166 pub fn ovcmon(
1167 self,
1168 ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, Syssts0_SPEC, crate::common::R> {
1169 crate::common::RegisterField::<14,0x3,1,0,u8,u8,Syssts0_SPEC,crate::common::R>::from_register(self,0)
1170 }
1171}
1172impl ::core::default::Default for Syssts0 {
1173 #[inline(always)]
1174 fn default() -> Syssts0 {
1175 <crate::RegValueT<Syssts0_SPEC> as RegisterValue<_>>::new(0)
1176 }
1177}
1178pub mod syssts0 {
1179
1180 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1181 pub struct Idmon_SPEC;
1182 pub type Idmon = crate::EnumBitfieldStruct<u8, Idmon_SPEC>;
1183 impl Idmon {
1184 #[doc = "USB_ID pin is low"]
1185 pub const _0: Self = Self::new(0);
1186
1187 #[doc = "USB_ID pin is high"]
1188 pub const _1: Self = Self::new(1);
1189 }
1190 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1191 pub struct Sofea_SPEC;
1192 pub type Sofea = crate::EnumBitfieldStruct<u8, Sofea_SPEC>;
1193 impl Sofea {
1194 #[doc = "SOF output stopped"]
1195 pub const _0: Self = Self::new(0);
1196
1197 #[doc = "SOF output operating"]
1198 pub const _1: Self = Self::new(1);
1199 }
1200 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1201 pub struct Htact_SPEC;
1202 pub type Htact = crate::EnumBitfieldStruct<u8, Htact_SPEC>;
1203 impl Htact {
1204 #[doc = "Host sequencer completely stopped"]
1205 pub const _0: Self = Self::new(0);
1206
1207 #[doc = "Host sequencer not completely stopped"]
1208 pub const _1: Self = Self::new(1);
1209 }
1210}
1211#[doc(hidden)]
1212#[derive(Copy, Clone, Eq, PartialEq)]
1213pub struct Dvstctr0_SPEC;
1214impl crate::sealed::RegSpec for Dvstctr0_SPEC {
1215 type DataType = u16;
1216}
1217
1218#[doc = "Device State Control Register 0"]
1219pub type Dvstctr0 = crate::RegValueT<Dvstctr0_SPEC>;
1220
1221impl Dvstctr0 {
1222 #[doc = "USB Bus Reset Status"]
1223 #[inline(always)]
1224 pub fn rhst(
1225 self,
1226 ) -> crate::common::RegisterField<
1227 0,
1228 0x7,
1229 1,
1230 0,
1231 dvstctr0::Rhst,
1232 dvstctr0::Rhst,
1233 Dvstctr0_SPEC,
1234 crate::common::R,
1235 > {
1236 crate::common::RegisterField::<
1237 0,
1238 0x7,
1239 1,
1240 0,
1241 dvstctr0::Rhst,
1242 dvstctr0::Rhst,
1243 Dvstctr0_SPEC,
1244 crate::common::R,
1245 >::from_register(self, 0)
1246 }
1247
1248 #[doc = "USB Bus Enable"]
1249 #[inline(always)]
1250 pub fn uact(
1251 self,
1252 ) -> crate::common::RegisterField<
1253 4,
1254 0x1,
1255 1,
1256 0,
1257 dvstctr0::Uact,
1258 dvstctr0::Uact,
1259 Dvstctr0_SPEC,
1260 crate::common::RW,
1261 > {
1262 crate::common::RegisterField::<
1263 4,
1264 0x1,
1265 1,
1266 0,
1267 dvstctr0::Uact,
1268 dvstctr0::Uact,
1269 Dvstctr0_SPEC,
1270 crate::common::RW,
1271 >::from_register(self, 0)
1272 }
1273
1274 #[doc = "Resume Output"]
1275 #[inline(always)]
1276 pub fn resume(
1277 self,
1278 ) -> crate::common::RegisterField<
1279 5,
1280 0x1,
1281 1,
1282 0,
1283 dvstctr0::Resume,
1284 dvstctr0::Resume,
1285 Dvstctr0_SPEC,
1286 crate::common::RW,
1287 > {
1288 crate::common::RegisterField::<
1289 5,
1290 0x1,
1291 1,
1292 0,
1293 dvstctr0::Resume,
1294 dvstctr0::Resume,
1295 Dvstctr0_SPEC,
1296 crate::common::RW,
1297 >::from_register(self, 0)
1298 }
1299
1300 #[doc = "USB Bus Reset Output"]
1301 #[inline(always)]
1302 pub fn usbrst(
1303 self,
1304 ) -> crate::common::RegisterField<
1305 6,
1306 0x1,
1307 1,
1308 0,
1309 dvstctr0::Usbrst,
1310 dvstctr0::Usbrst,
1311 Dvstctr0_SPEC,
1312 crate::common::RW,
1313 > {
1314 crate::common::RegisterField::<
1315 6,
1316 0x1,
1317 1,
1318 0,
1319 dvstctr0::Usbrst,
1320 dvstctr0::Usbrst,
1321 Dvstctr0_SPEC,
1322 crate::common::RW,
1323 >::from_register(self, 0)
1324 }
1325
1326 #[doc = "Wakeup Detection Enable"]
1327 #[inline(always)]
1328 pub fn rwupe(
1329 self,
1330 ) -> crate::common::RegisterField<
1331 7,
1332 0x1,
1333 1,
1334 0,
1335 dvstctr0::Rwupe,
1336 dvstctr0::Rwupe,
1337 Dvstctr0_SPEC,
1338 crate::common::RW,
1339 > {
1340 crate::common::RegisterField::<
1341 7,
1342 0x1,
1343 1,
1344 0,
1345 dvstctr0::Rwupe,
1346 dvstctr0::Rwupe,
1347 Dvstctr0_SPEC,
1348 crate::common::RW,
1349 >::from_register(self, 0)
1350 }
1351
1352 #[doc = "Wakeup Output"]
1353 #[inline(always)]
1354 pub fn wkup(
1355 self,
1356 ) -> crate::common::RegisterField<
1357 8,
1358 0x1,
1359 1,
1360 0,
1361 dvstctr0::Wkup,
1362 dvstctr0::Wkup,
1363 Dvstctr0_SPEC,
1364 crate::common::RW,
1365 > {
1366 crate::common::RegisterField::<
1367 8,
1368 0x1,
1369 1,
1370 0,
1371 dvstctr0::Wkup,
1372 dvstctr0::Wkup,
1373 Dvstctr0_SPEC,
1374 crate::common::RW,
1375 >::from_register(self, 0)
1376 }
1377
1378 #[doc = "USB_VBUSEN Output Pin Control"]
1379 #[inline(always)]
1380 pub fn vbusen(
1381 self,
1382 ) -> crate::common::RegisterField<
1383 9,
1384 0x1,
1385 1,
1386 0,
1387 dvstctr0::Vbusen,
1388 dvstctr0::Vbusen,
1389 Dvstctr0_SPEC,
1390 crate::common::RW,
1391 > {
1392 crate::common::RegisterField::<
1393 9,
1394 0x1,
1395 1,
1396 0,
1397 dvstctr0::Vbusen,
1398 dvstctr0::Vbusen,
1399 Dvstctr0_SPEC,
1400 crate::common::RW,
1401 >::from_register(self, 0)
1402 }
1403
1404 #[doc = "USB_EXICEN Output Pin Control"]
1405 #[inline(always)]
1406 pub fn exicen(
1407 self,
1408 ) -> crate::common::RegisterField<
1409 10,
1410 0x1,
1411 1,
1412 0,
1413 dvstctr0::Exicen,
1414 dvstctr0::Exicen,
1415 Dvstctr0_SPEC,
1416 crate::common::RW,
1417 > {
1418 crate::common::RegisterField::<
1419 10,
1420 0x1,
1421 1,
1422 0,
1423 dvstctr0::Exicen,
1424 dvstctr0::Exicen,
1425 Dvstctr0_SPEC,
1426 crate::common::RW,
1427 >::from_register(self, 0)
1428 }
1429
1430 #[doc = "Host Negotiation Protocol (HNP) Control"]
1431 #[inline(always)]
1432 pub fn hnpbtoa(
1433 self,
1434 ) -> crate::common::RegisterFieldBool<11, 1, 0, Dvstctr0_SPEC, crate::common::RW> {
1435 crate::common::RegisterFieldBool::<11,1,0,Dvstctr0_SPEC,crate::common::RW>::from_register(self,0)
1436 }
1437}
1438impl ::core::default::Default for Dvstctr0 {
1439 #[inline(always)]
1440 fn default() -> Dvstctr0 {
1441 <crate::RegValueT<Dvstctr0_SPEC> as RegisterValue<_>>::new(0)
1442 }
1443}
1444pub mod dvstctr0 {
1445
1446 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1447 pub struct Rhst_SPEC;
1448 pub type Rhst = crate::EnumBitfieldStruct<u8, Rhst_SPEC>;
1449 impl Rhst {
1450 #[doc = "In host controller mode: Communication speed indeterminate (powered state or no connection) In device controller mode: Communication speed indeterminate"]
1451 pub const _000: Self = Self::new(0);
1452
1453 #[doc = "In host controller mode: Low-speed connection In device controller mode: USB bus reset in progress"]
1454 pub const _001: Self = Self::new(1);
1455
1456 #[doc = "In host controller mode: Full-speed connection In device controller mode: USB bus reset in progress or full-speed connection"]
1457 pub const _010: Self = Self::new(2);
1458
1459 #[doc = "Setting prohibited"]
1460 pub const _011: Self = Self::new(3);
1461 }
1462 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1463 pub struct Uact_SPEC;
1464 pub type Uact = crate::EnumBitfieldStruct<u8, Uact_SPEC>;
1465 impl Uact {
1466 #[doc = "Disable downstream port (disable SOF transmission)"]
1467 pub const _0: Self = Self::new(0);
1468
1469 #[doc = "Enable downstream port (enable SOF transmission)"]
1470 pub const _1: Self = Self::new(1);
1471 }
1472 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1473 pub struct Resume_SPEC;
1474 pub type Resume = crate::EnumBitfieldStruct<u8, Resume_SPEC>;
1475 impl Resume {
1476 #[doc = "Do not output resume signal"]
1477 pub const _0: Self = Self::new(0);
1478
1479 #[doc = "Output resume signal"]
1480 pub const _1: Self = Self::new(1);
1481 }
1482 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1483 pub struct Usbrst_SPEC;
1484 pub type Usbrst = crate::EnumBitfieldStruct<u8, Usbrst_SPEC>;
1485 impl Usbrst {
1486 #[doc = "Do not output USB bus reset signal"]
1487 pub const _0: Self = Self::new(0);
1488
1489 #[doc = "Output USB bus reset signal"]
1490 pub const _1: Self = Self::new(1);
1491 }
1492 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1493 pub struct Rwupe_SPEC;
1494 pub type Rwupe = crate::EnumBitfieldStruct<u8, Rwupe_SPEC>;
1495 impl Rwupe {
1496 #[doc = "Disable downstream port remote wakeup"]
1497 pub const _0: Self = Self::new(0);
1498
1499 #[doc = "Enable downstream port remote wakeup"]
1500 pub const _1: Self = Self::new(1);
1501 }
1502 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1503 pub struct Wkup_SPEC;
1504 pub type Wkup = crate::EnumBitfieldStruct<u8, Wkup_SPEC>;
1505 impl Wkup {
1506 #[doc = "Do not output remote wakeup signal"]
1507 pub const _0: Self = Self::new(0);
1508
1509 #[doc = "Output remote wakeup signal"]
1510 pub const _1: Self = Self::new(1);
1511 }
1512 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1513 pub struct Vbusen_SPEC;
1514 pub type Vbusen = crate::EnumBitfieldStruct<u8, Vbusen_SPEC>;
1515 impl Vbusen {
1516 #[doc = "Output low on external USB_VBUSEN pin"]
1517 pub const _0: Self = Self::new(0);
1518
1519 #[doc = "Output high on external USB_VBUSEN pin"]
1520 pub const _1: Self = Self::new(1);
1521 }
1522 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1523 pub struct Exicen_SPEC;
1524 pub type Exicen = crate::EnumBitfieldStruct<u8, Exicen_SPEC>;
1525 impl Exicen {
1526 #[doc = "Output low on external USB_EXICEN pin"]
1527 pub const _0: Self = Self::new(0);
1528
1529 #[doc = "Output high on external USB_EXICEN pin"]
1530 pub const _1: Self = Self::new(1);
1531 }
1532}
1533#[doc(hidden)]
1534#[derive(Copy, Clone, Eq, PartialEq)]
1535pub struct Cfifo_SPEC;
1536impl crate::sealed::RegSpec for Cfifo_SPEC {
1537 type DataType = u16;
1538}
1539
1540#[doc = "CFIFO Port Register"]
1541pub type Cfifo = crate::RegValueT<Cfifo_SPEC>;
1542
1543impl Cfifo {
1544 #[doc = "FIFO Port"]
1545 #[inline(always)]
1546 pub fn fifoport(
1547 self,
1548 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cfifo_SPEC, crate::common::RW>
1549 {
1550 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cfifo_SPEC,crate::common::RW>::from_register(self,0)
1551 }
1552}
1553impl ::core::default::Default for Cfifo {
1554 #[inline(always)]
1555 fn default() -> Cfifo {
1556 <crate::RegValueT<Cfifo_SPEC> as RegisterValue<_>>::new(0)
1557 }
1558}
1559
1560#[doc(hidden)]
1561#[derive(Copy, Clone, Eq, PartialEq)]
1562pub struct Cfifol_SPEC;
1563impl crate::sealed::RegSpec for Cfifol_SPEC {
1564 type DataType = u8;
1565}
1566
1567#[doc = "CFIFO Port Register"]
1568pub type Cfifol = crate::RegValueT<Cfifol_SPEC>;
1569
1570impl NoBitfieldReg<Cfifol_SPEC> for Cfifol {}
1571impl ::core::default::Default for Cfifol {
1572 #[inline(always)]
1573 fn default() -> Cfifol {
1574 <crate::RegValueT<Cfifol_SPEC> as RegisterValue<_>>::new(0)
1575 }
1576}
1577
1578#[doc(hidden)]
1579#[derive(Copy, Clone, Eq, PartialEq)]
1580pub struct Dfifo_SPEC;
1581impl crate::sealed::RegSpec for Dfifo_SPEC {
1582 type DataType = u16;
1583}
1584
1585#[doc = "D%sFIFO Port Register"]
1586pub type Dfifo = crate::RegValueT<Dfifo_SPEC>;
1587
1588impl Dfifo {
1589 #[doc = "FIFO Port"]
1590 #[inline(always)]
1591 pub fn fifoport(
1592 self,
1593 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Dfifo_SPEC, crate::common::RW>
1594 {
1595 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Dfifo_SPEC,crate::common::RW>::from_register(self,0)
1596 }
1597}
1598impl ::core::default::Default for Dfifo {
1599 #[inline(always)]
1600 fn default() -> Dfifo {
1601 <crate::RegValueT<Dfifo_SPEC> as RegisterValue<_>>::new(0)
1602 }
1603}
1604
1605#[doc(hidden)]
1606#[derive(Copy, Clone, Eq, PartialEq)]
1607pub struct Dfifol_SPEC;
1608impl crate::sealed::RegSpec for Dfifol_SPEC {
1609 type DataType = u8;
1610}
1611
1612#[doc = "D%sFIFO Port Register"]
1613pub type Dfifol = crate::RegValueT<Dfifol_SPEC>;
1614
1615impl NoBitfieldReg<Dfifol_SPEC> for Dfifol {}
1616impl ::core::default::Default for Dfifol {
1617 #[inline(always)]
1618 fn default() -> Dfifol {
1619 <crate::RegValueT<Dfifol_SPEC> as RegisterValue<_>>::new(0)
1620 }
1621}
1622
1623#[doc(hidden)]
1624#[derive(Copy, Clone, Eq, PartialEq)]
1625pub struct Cfifosel_SPEC;
1626impl crate::sealed::RegSpec for Cfifosel_SPEC {
1627 type DataType = u16;
1628}
1629
1630#[doc = "CFIFO Port Select Register"]
1631pub type Cfifosel = crate::RegValueT<Cfifosel_SPEC>;
1632
1633impl Cfifosel {
1634 #[doc = "CFIFO Port Access Pipe Specification"]
1635 #[inline(always)]
1636 pub fn curpipe(
1637 self,
1638 ) -> crate::common::RegisterField<
1639 0,
1640 0xf,
1641 1,
1642 0,
1643 cfifosel::Curpipe,
1644 cfifosel::Curpipe,
1645 Cfifosel_SPEC,
1646 crate::common::RW,
1647 > {
1648 crate::common::RegisterField::<
1649 0,
1650 0xf,
1651 1,
1652 0,
1653 cfifosel::Curpipe,
1654 cfifosel::Curpipe,
1655 Cfifosel_SPEC,
1656 crate::common::RW,
1657 >::from_register(self, 0)
1658 }
1659
1660 #[doc = "CFIFO Port Access Direction When DCP Is Selected"]
1661 #[inline(always)]
1662 pub fn isel(
1663 self,
1664 ) -> crate::common::RegisterField<
1665 5,
1666 0x1,
1667 1,
1668 0,
1669 cfifosel::Isel,
1670 cfifosel::Isel,
1671 Cfifosel_SPEC,
1672 crate::common::RW,
1673 > {
1674 crate::common::RegisterField::<
1675 5,
1676 0x1,
1677 1,
1678 0,
1679 cfifosel::Isel,
1680 cfifosel::Isel,
1681 Cfifosel_SPEC,
1682 crate::common::RW,
1683 >::from_register(self, 0)
1684 }
1685
1686 #[doc = "CFIFO Port Endian Control"]
1687 #[inline(always)]
1688 pub fn bigend(
1689 self,
1690 ) -> crate::common::RegisterField<
1691 8,
1692 0x1,
1693 1,
1694 0,
1695 cfifosel::Bigend,
1696 cfifosel::Bigend,
1697 Cfifosel_SPEC,
1698 crate::common::RW,
1699 > {
1700 crate::common::RegisterField::<
1701 8,
1702 0x1,
1703 1,
1704 0,
1705 cfifosel::Bigend,
1706 cfifosel::Bigend,
1707 Cfifosel_SPEC,
1708 crate::common::RW,
1709 >::from_register(self, 0)
1710 }
1711
1712 #[doc = "CFIFO Port Access Bit Width"]
1713 #[inline(always)]
1714 pub fn mbw(
1715 self,
1716 ) -> crate::common::RegisterField<
1717 10,
1718 0x1,
1719 1,
1720 0,
1721 cfifosel::Mbw,
1722 cfifosel::Mbw,
1723 Cfifosel_SPEC,
1724 crate::common::RW,
1725 > {
1726 crate::common::RegisterField::<
1727 10,
1728 0x1,
1729 1,
1730 0,
1731 cfifosel::Mbw,
1732 cfifosel::Mbw,
1733 Cfifosel_SPEC,
1734 crate::common::RW,
1735 >::from_register(self, 0)
1736 }
1737
1738 #[doc = "Buffer Pointer Rewind"]
1739 #[inline(always)]
1740 pub fn rew(
1741 self,
1742 ) -> crate::common::RegisterField<
1743 14,
1744 0x1,
1745 1,
1746 0,
1747 cfifosel::Rew,
1748 cfifosel::Rew,
1749 Cfifosel_SPEC,
1750 crate::common::W,
1751 > {
1752 crate::common::RegisterField::<
1753 14,
1754 0x1,
1755 1,
1756 0,
1757 cfifosel::Rew,
1758 cfifosel::Rew,
1759 Cfifosel_SPEC,
1760 crate::common::W,
1761 >::from_register(self, 0)
1762 }
1763
1764 #[doc = "Read Count Mode"]
1765 #[inline(always)]
1766 pub fn rcnt(
1767 self,
1768 ) -> crate::common::RegisterField<
1769 15,
1770 0x1,
1771 1,
1772 0,
1773 cfifosel::Rcnt,
1774 cfifosel::Rcnt,
1775 Cfifosel_SPEC,
1776 crate::common::RW,
1777 > {
1778 crate::common::RegisterField::<
1779 15,
1780 0x1,
1781 1,
1782 0,
1783 cfifosel::Rcnt,
1784 cfifosel::Rcnt,
1785 Cfifosel_SPEC,
1786 crate::common::RW,
1787 >::from_register(self, 0)
1788 }
1789}
1790impl ::core::default::Default for Cfifosel {
1791 #[inline(always)]
1792 fn default() -> Cfifosel {
1793 <crate::RegValueT<Cfifosel_SPEC> as RegisterValue<_>>::new(0)
1794 }
1795}
1796pub mod cfifosel {
1797
1798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1799 pub struct Curpipe_SPEC;
1800 pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
1801 impl Curpipe {
1802 #[doc = "Default Control Pipe"]
1803 pub const _0_X_0: Self = Self::new(0);
1804
1805 #[doc = "Pipe 1"]
1806 pub const _0_X_1: Self = Self::new(1);
1807
1808 #[doc = "Pipe 2"]
1809 pub const _0_X_2: Self = Self::new(2);
1810
1811 #[doc = "Pipe 3"]
1812 pub const _0_X_3: Self = Self::new(3);
1813
1814 #[doc = "Pipe 4"]
1815 pub const _0_X_4: Self = Self::new(4);
1816
1817 #[doc = "Pipe 5"]
1818 pub const _0_X_5: Self = Self::new(5);
1819
1820 #[doc = "Pipe 6"]
1821 pub const _0_X_6: Self = Self::new(6);
1822
1823 #[doc = "Pipe 7"]
1824 pub const _0_X_7: Self = Self::new(7);
1825
1826 #[doc = "Pipe 8"]
1827 pub const _0_X_8: Self = Self::new(8);
1828
1829 #[doc = "Pipe 9"]
1830 pub const _0_X_9: Self = Self::new(9);
1831 }
1832 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1833 pub struct Isel_SPEC;
1834 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
1835 impl Isel {
1836 #[doc = "Select reading from the FIFO buffer"]
1837 pub const _0: Self = Self::new(0);
1838
1839 #[doc = "Select writing to the FIFO buffer"]
1840 pub const _1: Self = Self::new(1);
1841 }
1842 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1843 pub struct Bigend_SPEC;
1844 pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
1845 impl Bigend {
1846 #[doc = "Little endian"]
1847 pub const _0: Self = Self::new(0);
1848
1849 #[doc = "Big endian"]
1850 pub const _1: Self = Self::new(1);
1851 }
1852 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1853 pub struct Mbw_SPEC;
1854 pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
1855 impl Mbw {
1856 #[doc = "8-bit width"]
1857 pub const _0: Self = Self::new(0);
1858
1859 #[doc = "16-bit width"]
1860 pub const _1: Self = Self::new(1);
1861 }
1862 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1863 pub struct Rew_SPEC;
1864 pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
1865 impl Rew {
1866 #[doc = "Do not rewind buffer pointer"]
1867 pub const _0: Self = Self::new(0);
1868
1869 #[doc = "Rewind buffer pointer"]
1870 pub const _1: Self = Self::new(1);
1871 }
1872 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1873 pub struct Rcnt_SPEC;
1874 pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
1875 impl Rcnt {
1876 #[doc = "The DTLN\\[8:0\\] bits (CFIFOCTR.DTLN\\[8:0\\], D0FIFOCTR.DTLN\\[8:0\\], D1FIFOCTR.DTLN\\[8:0\\]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN\\[8:0\\] value is cleared when all data is read from only a single plane."]
1877 pub const _0: Self = Self::new(0);
1878
1879 #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the CFIFO."]
1880 pub const _1: Self = Self::new(1);
1881 }
1882}
1883#[doc(hidden)]
1884#[derive(Copy, Clone, Eq, PartialEq)]
1885pub struct Cfifoctr_SPEC;
1886impl crate::sealed::RegSpec for Cfifoctr_SPEC {
1887 type DataType = u16;
1888}
1889
1890#[doc = "CFIFO Port Control Register"]
1891pub type Cfifoctr = crate::RegValueT<Cfifoctr_SPEC>;
1892
1893impl Cfifoctr {
1894 #[doc = "Receive Data Length"]
1895 #[inline(always)]
1896 pub fn dtln(
1897 self,
1898 ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cfifoctr_SPEC, crate::common::R>
1899 {
1900 crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cfifoctr_SPEC,crate::common::R>::from_register(self,0)
1901 }
1902
1903 #[doc = "FIFO Port Ready"]
1904 #[inline(always)]
1905 pub fn frdy(
1906 self,
1907 ) -> crate::common::RegisterField<
1908 13,
1909 0x1,
1910 1,
1911 0,
1912 cfifoctr::Frdy,
1913 cfifoctr::Frdy,
1914 Cfifoctr_SPEC,
1915 crate::common::R,
1916 > {
1917 crate::common::RegisterField::<
1918 13,
1919 0x1,
1920 1,
1921 0,
1922 cfifoctr::Frdy,
1923 cfifoctr::Frdy,
1924 Cfifoctr_SPEC,
1925 crate::common::R,
1926 >::from_register(self, 0)
1927 }
1928
1929 #[doc = "CPU Buffer Clear"]
1930 #[inline(always)]
1931 pub fn bclr(
1932 self,
1933 ) -> crate::common::RegisterField<
1934 14,
1935 0x1,
1936 1,
1937 0,
1938 cfifoctr::Bclr,
1939 cfifoctr::Bclr,
1940 Cfifoctr_SPEC,
1941 crate::common::W,
1942 > {
1943 crate::common::RegisterField::<
1944 14,
1945 0x1,
1946 1,
1947 0,
1948 cfifoctr::Bclr,
1949 cfifoctr::Bclr,
1950 Cfifoctr_SPEC,
1951 crate::common::W,
1952 >::from_register(self, 0)
1953 }
1954
1955 #[doc = "Buffer Memory Valid Flag"]
1956 #[inline(always)]
1957 pub fn bval(
1958 self,
1959 ) -> crate::common::RegisterField<
1960 15,
1961 0x1,
1962 1,
1963 0,
1964 cfifoctr::Bval,
1965 cfifoctr::Bval,
1966 Cfifoctr_SPEC,
1967 crate::common::RW,
1968 > {
1969 crate::common::RegisterField::<
1970 15,
1971 0x1,
1972 1,
1973 0,
1974 cfifoctr::Bval,
1975 cfifoctr::Bval,
1976 Cfifoctr_SPEC,
1977 crate::common::RW,
1978 >::from_register(self, 0)
1979 }
1980}
1981impl ::core::default::Default for Cfifoctr {
1982 #[inline(always)]
1983 fn default() -> Cfifoctr {
1984 <crate::RegValueT<Cfifoctr_SPEC> as RegisterValue<_>>::new(0)
1985 }
1986}
1987pub mod cfifoctr {
1988
1989 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1990 pub struct Frdy_SPEC;
1991 pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
1992 impl Frdy {
1993 #[doc = "FIFO port access disabled"]
1994 pub const _0: Self = Self::new(0);
1995
1996 #[doc = "FIFO port access enabled"]
1997 pub const _1: Self = Self::new(1);
1998 }
1999 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2000 pub struct Bclr_SPEC;
2001 pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
2002 impl Bclr {
2003 #[doc = "No operation"]
2004 pub const _0: Self = Self::new(0);
2005
2006 #[doc = "Clear FIFO buffer on the CPU side"]
2007 pub const _1: Self = Self::new(1);
2008 }
2009 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2010 pub struct Bval_SPEC;
2011 pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
2012 impl Bval {
2013 #[doc = "Invalid (writing 0 has no effect)"]
2014 pub const _0: Self = Self::new(0);
2015
2016 #[doc = "Writing ended"]
2017 pub const _1: Self = Self::new(1);
2018 }
2019}
2020#[doc(hidden)]
2021#[derive(Copy, Clone, Eq, PartialEq)]
2022pub struct Dfifosel_SPEC;
2023impl crate::sealed::RegSpec for Dfifosel_SPEC {
2024 type DataType = u16;
2025}
2026
2027#[doc = "D%sFIFO Port Select Register"]
2028pub type Dfifosel = crate::RegValueT<Dfifosel_SPEC>;
2029
2030impl Dfifosel {
2031 #[doc = "FIFO Port Access Pipe Specification"]
2032 #[inline(always)]
2033 pub fn curpipe(
2034 self,
2035 ) -> crate::common::RegisterField<
2036 0,
2037 0xf,
2038 1,
2039 0,
2040 dfifosel::Curpipe,
2041 dfifosel::Curpipe,
2042 Dfifosel_SPEC,
2043 crate::common::RW,
2044 > {
2045 crate::common::RegisterField::<
2046 0,
2047 0xf,
2048 1,
2049 0,
2050 dfifosel::Curpipe,
2051 dfifosel::Curpipe,
2052 Dfifosel_SPEC,
2053 crate::common::RW,
2054 >::from_register(self, 0)
2055 }
2056
2057 #[doc = "FIFO Port Endian Control"]
2058 #[inline(always)]
2059 pub fn bigend(
2060 self,
2061 ) -> crate::common::RegisterField<
2062 8,
2063 0x1,
2064 1,
2065 0,
2066 dfifosel::Bigend,
2067 dfifosel::Bigend,
2068 Dfifosel_SPEC,
2069 crate::common::RW,
2070 > {
2071 crate::common::RegisterField::<
2072 8,
2073 0x1,
2074 1,
2075 0,
2076 dfifosel::Bigend,
2077 dfifosel::Bigend,
2078 Dfifosel_SPEC,
2079 crate::common::RW,
2080 >::from_register(self, 0)
2081 }
2082
2083 #[doc = "FIFO Port Access Bit Width"]
2084 #[inline(always)]
2085 pub fn mbw(
2086 self,
2087 ) -> crate::common::RegisterField<
2088 10,
2089 0x1,
2090 1,
2091 0,
2092 dfifosel::Mbw,
2093 dfifosel::Mbw,
2094 Dfifosel_SPEC,
2095 crate::common::RW,
2096 > {
2097 crate::common::RegisterField::<
2098 10,
2099 0x1,
2100 1,
2101 0,
2102 dfifosel::Mbw,
2103 dfifosel::Mbw,
2104 Dfifosel_SPEC,
2105 crate::common::RW,
2106 >::from_register(self, 0)
2107 }
2108
2109 #[doc = "DMA/DTC Transfer Request Enable"]
2110 #[inline(always)]
2111 pub fn dreqe(
2112 self,
2113 ) -> crate::common::RegisterField<
2114 12,
2115 0x1,
2116 1,
2117 0,
2118 dfifosel::Dreqe,
2119 dfifosel::Dreqe,
2120 Dfifosel_SPEC,
2121 crate::common::RW,
2122 > {
2123 crate::common::RegisterField::<
2124 12,
2125 0x1,
2126 1,
2127 0,
2128 dfifosel::Dreqe,
2129 dfifosel::Dreqe,
2130 Dfifosel_SPEC,
2131 crate::common::RW,
2132 >::from_register(self, 0)
2133 }
2134
2135 #[doc = "Auto Buffer Memory Clear Mode Accessed after Specified Pipe Data is Read"]
2136 #[inline(always)]
2137 pub fn dclrm(
2138 self,
2139 ) -> crate::common::RegisterField<
2140 13,
2141 0x1,
2142 1,
2143 0,
2144 dfifosel::Dclrm,
2145 dfifosel::Dclrm,
2146 Dfifosel_SPEC,
2147 crate::common::RW,
2148 > {
2149 crate::common::RegisterField::<
2150 13,
2151 0x1,
2152 1,
2153 0,
2154 dfifosel::Dclrm,
2155 dfifosel::Dclrm,
2156 Dfifosel_SPEC,
2157 crate::common::RW,
2158 >::from_register(self, 0)
2159 }
2160
2161 #[doc = "Buffer Pointer Rewind"]
2162 #[inline(always)]
2163 pub fn rew(
2164 self,
2165 ) -> crate::common::RegisterField<
2166 14,
2167 0x1,
2168 1,
2169 0,
2170 dfifosel::Rew,
2171 dfifosel::Rew,
2172 Dfifosel_SPEC,
2173 crate::common::W,
2174 > {
2175 crate::common::RegisterField::<
2176 14,
2177 0x1,
2178 1,
2179 0,
2180 dfifosel::Rew,
2181 dfifosel::Rew,
2182 Dfifosel_SPEC,
2183 crate::common::W,
2184 >::from_register(self, 0)
2185 }
2186
2187 #[doc = "Read Count Mode"]
2188 #[inline(always)]
2189 pub fn rcnt(
2190 self,
2191 ) -> crate::common::RegisterField<
2192 15,
2193 0x1,
2194 1,
2195 0,
2196 dfifosel::Rcnt,
2197 dfifosel::Rcnt,
2198 Dfifosel_SPEC,
2199 crate::common::RW,
2200 > {
2201 crate::common::RegisterField::<
2202 15,
2203 0x1,
2204 1,
2205 0,
2206 dfifosel::Rcnt,
2207 dfifosel::Rcnt,
2208 Dfifosel_SPEC,
2209 crate::common::RW,
2210 >::from_register(self, 0)
2211 }
2212}
2213impl ::core::default::Default for Dfifosel {
2214 #[inline(always)]
2215 fn default() -> Dfifosel {
2216 <crate::RegValueT<Dfifosel_SPEC> as RegisterValue<_>>::new(0)
2217 }
2218}
2219pub mod dfifosel {
2220
2221 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2222 pub struct Curpipe_SPEC;
2223 pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
2224 impl Curpipe {
2225 #[doc = "Default Control Pipe"]
2226 pub const _0_X_0: Self = Self::new(0);
2227
2228 #[doc = "Pipe 1"]
2229 pub const _0_X_1: Self = Self::new(1);
2230
2231 #[doc = "Pipe 2"]
2232 pub const _0_X_2: Self = Self::new(2);
2233
2234 #[doc = "Pipe 3"]
2235 pub const _0_X_3: Self = Self::new(3);
2236
2237 #[doc = "Pipe 4"]
2238 pub const _0_X_4: Self = Self::new(4);
2239
2240 #[doc = "Pipe 5"]
2241 pub const _0_X_5: Self = Self::new(5);
2242
2243 #[doc = "Pipe 6"]
2244 pub const _0_X_6: Self = Self::new(6);
2245
2246 #[doc = "Pipe 7"]
2247 pub const _0_X_7: Self = Self::new(7);
2248
2249 #[doc = "Pipe 8"]
2250 pub const _0_X_8: Self = Self::new(8);
2251
2252 #[doc = "Pipe 9"]
2253 pub const _0_X_9: Self = Self::new(9);
2254 }
2255 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2256 pub struct Bigend_SPEC;
2257 pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
2258 impl Bigend {
2259 #[doc = "Little endian"]
2260 pub const _0: Self = Self::new(0);
2261
2262 #[doc = "Big endian"]
2263 pub const _1: Self = Self::new(1);
2264 }
2265 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2266 pub struct Mbw_SPEC;
2267 pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
2268 impl Mbw {
2269 #[doc = "8-bit width"]
2270 pub const _0: Self = Self::new(0);
2271
2272 #[doc = "16-bit width"]
2273 pub const _1: Self = Self::new(1);
2274 }
2275 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2276 pub struct Dreqe_SPEC;
2277 pub type Dreqe = crate::EnumBitfieldStruct<u8, Dreqe_SPEC>;
2278 impl Dreqe {
2279 #[doc = "Disable DMA/DTC transfer request"]
2280 pub const _0: Self = Self::new(0);
2281
2282 #[doc = "Enable DMA/DTC transfer request"]
2283 pub const _1: Self = Self::new(1);
2284 }
2285 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2286 pub struct Dclrm_SPEC;
2287 pub type Dclrm = crate::EnumBitfieldStruct<u8, Dclrm_SPEC>;
2288 impl Dclrm {
2289 #[doc = "Disable auto buffer clear mode"]
2290 pub const _0: Self = Self::new(0);
2291
2292 #[doc = "Enable auto buffer clear mode"]
2293 pub const _1: Self = Self::new(1);
2294 }
2295 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2296 pub struct Rew_SPEC;
2297 pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
2298 impl Rew {
2299 #[doc = "Do not rewind buffer pointer"]
2300 pub const _0: Self = Self::new(0);
2301
2302 #[doc = "Rewind buffer pointer"]
2303 pub const _1: Self = Self::new(1);
2304 }
2305 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2306 pub struct Rcnt_SPEC;
2307 pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
2308 impl Rcnt {
2309 #[doc = "Clear DTLN\\[8:0\\] bits in (CFIFOCTR.DTLN\\[8:0\\], D0FIFOCTR.DTLN\\[8:0\\], D1FIFOCTR.DTLN\\[8:0\\]) when all receive data is read from DnFIFO (after read of a single plane in double buffer mode)"]
2310 pub const _0: Self = Self::new(0);
2311
2312 #[doc = "Decrement DTLN\\[8:0\\] bits each time receive data is read from DnFIFO"]
2313 pub const _1: Self = Self::new(1);
2314 }
2315}
2316#[doc(hidden)]
2317#[derive(Copy, Clone, Eq, PartialEq)]
2318pub struct Dfifoctr_SPEC;
2319impl crate::sealed::RegSpec for Dfifoctr_SPEC {
2320 type DataType = u16;
2321}
2322
2323#[doc = "D%sFIFO Port Control Register"]
2324pub type Dfifoctr = crate::RegValueT<Dfifoctr_SPEC>;
2325
2326impl Dfifoctr {
2327 #[doc = "Receive Data Length"]
2328 #[inline(always)]
2329 pub fn dtln(
2330 self,
2331 ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Dfifoctr_SPEC, crate::common::R>
2332 {
2333 crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Dfifoctr_SPEC,crate::common::R>::from_register(self,0)
2334 }
2335
2336 #[doc = "FIFO Port Ready"]
2337 #[inline(always)]
2338 pub fn frdy(
2339 self,
2340 ) -> crate::common::RegisterField<
2341 13,
2342 0x1,
2343 1,
2344 0,
2345 dfifoctr::Frdy,
2346 dfifoctr::Frdy,
2347 Dfifoctr_SPEC,
2348 crate::common::R,
2349 > {
2350 crate::common::RegisterField::<
2351 13,
2352 0x1,
2353 1,
2354 0,
2355 dfifoctr::Frdy,
2356 dfifoctr::Frdy,
2357 Dfifoctr_SPEC,
2358 crate::common::R,
2359 >::from_register(self, 0)
2360 }
2361
2362 #[doc = "CPU Buffer Clear"]
2363 #[inline(always)]
2364 pub fn bclr(
2365 self,
2366 ) -> crate::common::RegisterField<
2367 14,
2368 0x1,
2369 1,
2370 0,
2371 dfifoctr::Bclr,
2372 dfifoctr::Bclr,
2373 Dfifoctr_SPEC,
2374 crate::common::RW,
2375 > {
2376 crate::common::RegisterField::<
2377 14,
2378 0x1,
2379 1,
2380 0,
2381 dfifoctr::Bclr,
2382 dfifoctr::Bclr,
2383 Dfifoctr_SPEC,
2384 crate::common::RW,
2385 >::from_register(self, 0)
2386 }
2387
2388 #[doc = "Buffer Memory Valid Flag"]
2389 #[inline(always)]
2390 pub fn bval(
2391 self,
2392 ) -> crate::common::RegisterField<
2393 15,
2394 0x1,
2395 1,
2396 0,
2397 dfifoctr::Bval,
2398 dfifoctr::Bval,
2399 Dfifoctr_SPEC,
2400 crate::common::RW,
2401 > {
2402 crate::common::RegisterField::<
2403 15,
2404 0x1,
2405 1,
2406 0,
2407 dfifoctr::Bval,
2408 dfifoctr::Bval,
2409 Dfifoctr_SPEC,
2410 crate::common::RW,
2411 >::from_register(self, 0)
2412 }
2413}
2414impl ::core::default::Default for Dfifoctr {
2415 #[inline(always)]
2416 fn default() -> Dfifoctr {
2417 <crate::RegValueT<Dfifoctr_SPEC> as RegisterValue<_>>::new(0)
2418 }
2419}
2420pub mod dfifoctr {
2421
2422 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2423 pub struct Frdy_SPEC;
2424 pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
2425 impl Frdy {
2426 #[doc = "FIFO port access disabled"]
2427 pub const _0: Self = Self::new(0);
2428
2429 #[doc = "FIFO port access enabled"]
2430 pub const _1: Self = Self::new(1);
2431 }
2432 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2433 pub struct Bclr_SPEC;
2434 pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
2435 impl Bclr {
2436 #[doc = "No operation"]
2437 pub const _0: Self = Self::new(0);
2438
2439 #[doc = "Clear FIFO buffer on the CPU side"]
2440 pub const _1: Self = Self::new(1);
2441 }
2442 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2443 pub struct Bval_SPEC;
2444 pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
2445 impl Bval {
2446 #[doc = "Invalid (writing 0 has no effect)"]
2447 pub const _0: Self = Self::new(0);
2448
2449 #[doc = "Writing ended"]
2450 pub const _1: Self = Self::new(1);
2451 }
2452}
2453#[doc(hidden)]
2454#[derive(Copy, Clone, Eq, PartialEq)]
2455pub struct Intenb0_SPEC;
2456impl crate::sealed::RegSpec for Intenb0_SPEC {
2457 type DataType = u16;
2458}
2459
2460#[doc = "Interrupt Enable Register 0"]
2461pub type Intenb0 = crate::RegValueT<Intenb0_SPEC>;
2462
2463impl Intenb0 {
2464 #[doc = "Buffer Ready Interrupt Enable"]
2465 #[inline(always)]
2466 pub fn brdye(
2467 self,
2468 ) -> crate::common::RegisterField<
2469 8,
2470 0x1,
2471 1,
2472 0,
2473 intenb0::Brdye,
2474 intenb0::Brdye,
2475 Intenb0_SPEC,
2476 crate::common::RW,
2477 > {
2478 crate::common::RegisterField::<
2479 8,
2480 0x1,
2481 1,
2482 0,
2483 intenb0::Brdye,
2484 intenb0::Brdye,
2485 Intenb0_SPEC,
2486 crate::common::RW,
2487 >::from_register(self, 0)
2488 }
2489
2490 #[doc = "Buffer Not Ready Response Interrupt Enable"]
2491 #[inline(always)]
2492 pub fn nrdye(
2493 self,
2494 ) -> crate::common::RegisterField<
2495 9,
2496 0x1,
2497 1,
2498 0,
2499 intenb0::Nrdye,
2500 intenb0::Nrdye,
2501 Intenb0_SPEC,
2502 crate::common::RW,
2503 > {
2504 crate::common::RegisterField::<
2505 9,
2506 0x1,
2507 1,
2508 0,
2509 intenb0::Nrdye,
2510 intenb0::Nrdye,
2511 Intenb0_SPEC,
2512 crate::common::RW,
2513 >::from_register(self, 0)
2514 }
2515
2516 #[doc = "Buffer Empty Interrupt Enable"]
2517 #[inline(always)]
2518 pub fn bempe(
2519 self,
2520 ) -> crate::common::RegisterField<
2521 10,
2522 0x1,
2523 1,
2524 0,
2525 intenb0::Bempe,
2526 intenb0::Bempe,
2527 Intenb0_SPEC,
2528 crate::common::RW,
2529 > {
2530 crate::common::RegisterField::<
2531 10,
2532 0x1,
2533 1,
2534 0,
2535 intenb0::Bempe,
2536 intenb0::Bempe,
2537 Intenb0_SPEC,
2538 crate::common::RW,
2539 >::from_register(self, 0)
2540 }
2541
2542 #[doc = "Control Transfer Stage Transition Interrupt Enable"]
2543 #[inline(always)]
2544 pub fn ctre(
2545 self,
2546 ) -> crate::common::RegisterField<
2547 11,
2548 0x1,
2549 1,
2550 0,
2551 intenb0::Ctre,
2552 intenb0::Ctre,
2553 Intenb0_SPEC,
2554 crate::common::RW,
2555 > {
2556 crate::common::RegisterField::<
2557 11,
2558 0x1,
2559 1,
2560 0,
2561 intenb0::Ctre,
2562 intenb0::Ctre,
2563 Intenb0_SPEC,
2564 crate::common::RW,
2565 >::from_register(self, 0)
2566 }
2567
2568 #[doc = "Device State Transition Interrupt Enable"]
2569 #[inline(always)]
2570 pub fn dvse(
2571 self,
2572 ) -> crate::common::RegisterField<
2573 12,
2574 0x1,
2575 1,
2576 0,
2577 intenb0::Dvse,
2578 intenb0::Dvse,
2579 Intenb0_SPEC,
2580 crate::common::RW,
2581 > {
2582 crate::common::RegisterField::<
2583 12,
2584 0x1,
2585 1,
2586 0,
2587 intenb0::Dvse,
2588 intenb0::Dvse,
2589 Intenb0_SPEC,
2590 crate::common::RW,
2591 >::from_register(self, 0)
2592 }
2593
2594 #[doc = "Frame Number Update Interrupt Enable"]
2595 #[inline(always)]
2596 pub fn sofe(
2597 self,
2598 ) -> crate::common::RegisterField<
2599 13,
2600 0x1,
2601 1,
2602 0,
2603 intenb0::Sofe,
2604 intenb0::Sofe,
2605 Intenb0_SPEC,
2606 crate::common::RW,
2607 > {
2608 crate::common::RegisterField::<
2609 13,
2610 0x1,
2611 1,
2612 0,
2613 intenb0::Sofe,
2614 intenb0::Sofe,
2615 Intenb0_SPEC,
2616 crate::common::RW,
2617 >::from_register(self, 0)
2618 }
2619
2620 #[doc = "Resume Interrupt Enable"]
2621 #[inline(always)]
2622 pub fn rsme(
2623 self,
2624 ) -> crate::common::RegisterField<
2625 14,
2626 0x1,
2627 1,
2628 0,
2629 intenb0::Rsme,
2630 intenb0::Rsme,
2631 Intenb0_SPEC,
2632 crate::common::RW,
2633 > {
2634 crate::common::RegisterField::<
2635 14,
2636 0x1,
2637 1,
2638 0,
2639 intenb0::Rsme,
2640 intenb0::Rsme,
2641 Intenb0_SPEC,
2642 crate::common::RW,
2643 >::from_register(self, 0)
2644 }
2645
2646 #[doc = "VBUS Interrupt Enable"]
2647 #[inline(always)]
2648 pub fn vbse(
2649 self,
2650 ) -> crate::common::RegisterField<
2651 15,
2652 0x1,
2653 1,
2654 0,
2655 intenb0::Vbse,
2656 intenb0::Vbse,
2657 Intenb0_SPEC,
2658 crate::common::RW,
2659 > {
2660 crate::common::RegisterField::<
2661 15,
2662 0x1,
2663 1,
2664 0,
2665 intenb0::Vbse,
2666 intenb0::Vbse,
2667 Intenb0_SPEC,
2668 crate::common::RW,
2669 >::from_register(self, 0)
2670 }
2671}
2672impl ::core::default::Default for Intenb0 {
2673 #[inline(always)]
2674 fn default() -> Intenb0 {
2675 <crate::RegValueT<Intenb0_SPEC> as RegisterValue<_>>::new(0)
2676 }
2677}
2678pub mod intenb0 {
2679
2680 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2681 pub struct Brdye_SPEC;
2682 pub type Brdye = crate::EnumBitfieldStruct<u8, Brdye_SPEC>;
2683 impl Brdye {
2684 #[doc = "Disable interrupt request"]
2685 pub const _0: Self = Self::new(0);
2686
2687 #[doc = "Enable interrupt request"]
2688 pub const _1: Self = Self::new(1);
2689 }
2690 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2691 pub struct Nrdye_SPEC;
2692 pub type Nrdye = crate::EnumBitfieldStruct<u8, Nrdye_SPEC>;
2693 impl Nrdye {
2694 #[doc = "Disable interrupt request"]
2695 pub const _0: Self = Self::new(0);
2696
2697 #[doc = "Enable interrupt request"]
2698 pub const _1: Self = Self::new(1);
2699 }
2700 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2701 pub struct Bempe_SPEC;
2702 pub type Bempe = crate::EnumBitfieldStruct<u8, Bempe_SPEC>;
2703 impl Bempe {
2704 #[doc = "Disable interrupt request"]
2705 pub const _0: Self = Self::new(0);
2706
2707 #[doc = "Enable interrupt request"]
2708 pub const _1: Self = Self::new(1);
2709 }
2710 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2711 pub struct Ctre_SPEC;
2712 pub type Ctre = crate::EnumBitfieldStruct<u8, Ctre_SPEC>;
2713 impl Ctre {
2714 #[doc = "Disable interrupt request"]
2715 pub const _0: Self = Self::new(0);
2716
2717 #[doc = "Enable interrupt request"]
2718 pub const _1: Self = Self::new(1);
2719 }
2720 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2721 pub struct Dvse_SPEC;
2722 pub type Dvse = crate::EnumBitfieldStruct<u8, Dvse_SPEC>;
2723 impl Dvse {
2724 #[doc = "Disable interrupt request"]
2725 pub const _0: Self = Self::new(0);
2726
2727 #[doc = "Enable interrupt request"]
2728 pub const _1: Self = Self::new(1);
2729 }
2730 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2731 pub struct Sofe_SPEC;
2732 pub type Sofe = crate::EnumBitfieldStruct<u8, Sofe_SPEC>;
2733 impl Sofe {
2734 #[doc = "Disable interrupt request"]
2735 pub const _0: Self = Self::new(0);
2736
2737 #[doc = "Enable interrupt request"]
2738 pub const _1: Self = Self::new(1);
2739 }
2740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2741 pub struct Rsme_SPEC;
2742 pub type Rsme = crate::EnumBitfieldStruct<u8, Rsme_SPEC>;
2743 impl Rsme {
2744 #[doc = "Disable interrupt request"]
2745 pub const _0: Self = Self::new(0);
2746
2747 #[doc = "Enable interrupt request"]
2748 pub const _1: Self = Self::new(1);
2749 }
2750 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2751 pub struct Vbse_SPEC;
2752 pub type Vbse = crate::EnumBitfieldStruct<u8, Vbse_SPEC>;
2753 impl Vbse {
2754 #[doc = "Disable interrupt request"]
2755 pub const _0: Self = Self::new(0);
2756
2757 #[doc = "Enable interrupt request"]
2758 pub const _1: Self = Self::new(1);
2759 }
2760}
2761#[doc(hidden)]
2762#[derive(Copy, Clone, Eq, PartialEq)]
2763pub struct Intenb1_SPEC;
2764impl crate::sealed::RegSpec for Intenb1_SPEC {
2765 type DataType = u16;
2766}
2767
2768#[doc = "Interrupt Enable Register 1"]
2769pub type Intenb1 = crate::RegValueT<Intenb1_SPEC>;
2770
2771impl Intenb1 {
2772 #[doc = "PDDETINT Detection Interrupt Request Enable"]
2773 #[inline(always)]
2774 pub fn pddetinte(
2775 self,
2776 ) -> crate::common::RegisterField<
2777 0,
2778 0x1,
2779 1,
2780 0,
2781 intenb1::Pddetinte,
2782 intenb1::Pddetinte,
2783 Intenb1_SPEC,
2784 crate::common::RW,
2785 > {
2786 crate::common::RegisterField::<
2787 0,
2788 0x1,
2789 1,
2790 0,
2791 intenb1::Pddetinte,
2792 intenb1::Pddetinte,
2793 Intenb1_SPEC,
2794 crate::common::RW,
2795 >::from_register(self, 0)
2796 }
2797
2798 #[doc = "Setup Transaction Normal Response Interrupt Enable"]
2799 #[inline(always)]
2800 pub fn sacke(
2801 self,
2802 ) -> crate::common::RegisterField<
2803 4,
2804 0x1,
2805 1,
2806 0,
2807 intenb1::Sacke,
2808 intenb1::Sacke,
2809 Intenb1_SPEC,
2810 crate::common::RW,
2811 > {
2812 crate::common::RegisterField::<
2813 4,
2814 0x1,
2815 1,
2816 0,
2817 intenb1::Sacke,
2818 intenb1::Sacke,
2819 Intenb1_SPEC,
2820 crate::common::RW,
2821 >::from_register(self, 0)
2822 }
2823
2824 #[doc = "Setup Transaction Error Interrupt Enable"]
2825 #[inline(always)]
2826 pub fn signe(
2827 self,
2828 ) -> crate::common::RegisterField<
2829 5,
2830 0x1,
2831 1,
2832 0,
2833 intenb1::Signe,
2834 intenb1::Signe,
2835 Intenb1_SPEC,
2836 crate::common::RW,
2837 > {
2838 crate::common::RegisterField::<
2839 5,
2840 0x1,
2841 1,
2842 0,
2843 intenb1::Signe,
2844 intenb1::Signe,
2845 Intenb1_SPEC,
2846 crate::common::RW,
2847 >::from_register(self, 0)
2848 }
2849
2850 #[doc = "EOF Error Detection Interrupt Enable"]
2851 #[inline(always)]
2852 pub fn eoferre(
2853 self,
2854 ) -> crate::common::RegisterField<
2855 6,
2856 0x1,
2857 1,
2858 0,
2859 intenb1::Eoferre,
2860 intenb1::Eoferre,
2861 Intenb1_SPEC,
2862 crate::common::RW,
2863 > {
2864 crate::common::RegisterField::<
2865 6,
2866 0x1,
2867 1,
2868 0,
2869 intenb1::Eoferre,
2870 intenb1::Eoferre,
2871 Intenb1_SPEC,
2872 crate::common::RW,
2873 >::from_register(self, 0)
2874 }
2875
2876 #[doc = "Connection Detection Interrupt Enable"]
2877 #[inline(always)]
2878 pub fn attche(
2879 self,
2880 ) -> crate::common::RegisterField<
2881 11,
2882 0x1,
2883 1,
2884 0,
2885 intenb1::Attche,
2886 intenb1::Attche,
2887 Intenb1_SPEC,
2888 crate::common::RW,
2889 > {
2890 crate::common::RegisterField::<
2891 11,
2892 0x1,
2893 1,
2894 0,
2895 intenb1::Attche,
2896 intenb1::Attche,
2897 Intenb1_SPEC,
2898 crate::common::RW,
2899 >::from_register(self, 0)
2900 }
2901
2902 #[doc = "Disconnection Detection Interrupt Enable"]
2903 #[inline(always)]
2904 pub fn dtche(
2905 self,
2906 ) -> crate::common::RegisterField<
2907 12,
2908 0x1,
2909 1,
2910 0,
2911 intenb1::Dtche,
2912 intenb1::Dtche,
2913 Intenb1_SPEC,
2914 crate::common::RW,
2915 > {
2916 crate::common::RegisterField::<
2917 12,
2918 0x1,
2919 1,
2920 0,
2921 intenb1::Dtche,
2922 intenb1::Dtche,
2923 Intenb1_SPEC,
2924 crate::common::RW,
2925 >::from_register(self, 0)
2926 }
2927
2928 #[doc = "USB Bus Change Interrupt Enable"]
2929 #[inline(always)]
2930 pub fn bchge(
2931 self,
2932 ) -> crate::common::RegisterField<
2933 14,
2934 0x1,
2935 1,
2936 0,
2937 intenb1::Bchge,
2938 intenb1::Bchge,
2939 Intenb1_SPEC,
2940 crate::common::RW,
2941 > {
2942 crate::common::RegisterField::<
2943 14,
2944 0x1,
2945 1,
2946 0,
2947 intenb1::Bchge,
2948 intenb1::Bchge,
2949 Intenb1_SPEC,
2950 crate::common::RW,
2951 >::from_register(self, 0)
2952 }
2953
2954 #[doc = "Overcurrent Input Change Interrupt Enable"]
2955 #[inline(always)]
2956 pub fn ovrcre(
2957 self,
2958 ) -> crate::common::RegisterField<
2959 15,
2960 0x1,
2961 1,
2962 0,
2963 intenb1::Ovrcre,
2964 intenb1::Ovrcre,
2965 Intenb1_SPEC,
2966 crate::common::RW,
2967 > {
2968 crate::common::RegisterField::<
2969 15,
2970 0x1,
2971 1,
2972 0,
2973 intenb1::Ovrcre,
2974 intenb1::Ovrcre,
2975 Intenb1_SPEC,
2976 crate::common::RW,
2977 >::from_register(self, 0)
2978 }
2979}
2980impl ::core::default::Default for Intenb1 {
2981 #[inline(always)]
2982 fn default() -> Intenb1 {
2983 <crate::RegValueT<Intenb1_SPEC> as RegisterValue<_>>::new(0)
2984 }
2985}
2986pub mod intenb1 {
2987
2988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2989 pub struct Pddetinte_SPEC;
2990 pub type Pddetinte = crate::EnumBitfieldStruct<u8, Pddetinte_SPEC>;
2991 impl Pddetinte {
2992 #[doc = "Disable interrupt request"]
2993 pub const _0: Self = Self::new(0);
2994
2995 #[doc = "Enable interrupt request"]
2996 pub const _1: Self = Self::new(1);
2997 }
2998 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2999 pub struct Sacke_SPEC;
3000 pub type Sacke = crate::EnumBitfieldStruct<u8, Sacke_SPEC>;
3001 impl Sacke {
3002 #[doc = "Disable interrupt request"]
3003 pub const _0: Self = Self::new(0);
3004
3005 #[doc = "Enable interrupt request"]
3006 pub const _1: Self = Self::new(1);
3007 }
3008 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3009 pub struct Signe_SPEC;
3010 pub type Signe = crate::EnumBitfieldStruct<u8, Signe_SPEC>;
3011 impl Signe {
3012 #[doc = "Disable interrupt request"]
3013 pub const _0: Self = Self::new(0);
3014
3015 #[doc = "Enable interrupt request"]
3016 pub const _1: Self = Self::new(1);
3017 }
3018 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3019 pub struct Eoferre_SPEC;
3020 pub type Eoferre = crate::EnumBitfieldStruct<u8, Eoferre_SPEC>;
3021 impl Eoferre {
3022 #[doc = "Disable interrupt request"]
3023 pub const _0: Self = Self::new(0);
3024
3025 #[doc = "Enable interrupt request"]
3026 pub const _1: Self = Self::new(1);
3027 }
3028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3029 pub struct Attche_SPEC;
3030 pub type Attche = crate::EnumBitfieldStruct<u8, Attche_SPEC>;
3031 impl Attche {
3032 #[doc = "Disable interrupt request"]
3033 pub const _0: Self = Self::new(0);
3034
3035 #[doc = "Enable interrupt request"]
3036 pub const _1: Self = Self::new(1);
3037 }
3038 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3039 pub struct Dtche_SPEC;
3040 pub type Dtche = crate::EnumBitfieldStruct<u8, Dtche_SPEC>;
3041 impl Dtche {
3042 #[doc = "Disable interrupt request"]
3043 pub const _0: Self = Self::new(0);
3044
3045 #[doc = "Enable interrupt request"]
3046 pub const _1: Self = Self::new(1);
3047 }
3048 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3049 pub struct Bchge_SPEC;
3050 pub type Bchge = crate::EnumBitfieldStruct<u8, Bchge_SPEC>;
3051 impl Bchge {
3052 #[doc = "Disable interrupt request"]
3053 pub const _0: Self = Self::new(0);
3054
3055 #[doc = "Enable interrupt request"]
3056 pub const _1: Self = Self::new(1);
3057 }
3058 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3059 pub struct Ovrcre_SPEC;
3060 pub type Ovrcre = crate::EnumBitfieldStruct<u8, Ovrcre_SPEC>;
3061 impl Ovrcre {
3062 #[doc = "Disable interrupt request"]
3063 pub const _0: Self = Self::new(0);
3064
3065 #[doc = "Enable interrupt request"]
3066 pub const _1: Self = Self::new(1);
3067 }
3068}
3069#[doc(hidden)]
3070#[derive(Copy, Clone, Eq, PartialEq)]
3071pub struct Brdyenb_SPEC;
3072impl crate::sealed::RegSpec for Brdyenb_SPEC {
3073 type DataType = u16;
3074}
3075
3076#[doc = "BRDY Interrupt Enable Register"]
3077pub type Brdyenb = crate::RegValueT<Brdyenb_SPEC>;
3078
3079impl Brdyenb {
3080 #[doc = "BRDY Interrupt Enable for Pipe 0"]
3081 #[inline(always)]
3082 pub fn pipe0brdye(
3083 self,
3084 ) -> crate::common::RegisterField<
3085 0,
3086 0x1,
3087 1,
3088 0,
3089 brdyenb::Pipe0Brdye,
3090 brdyenb::Pipe0Brdye,
3091 Brdyenb_SPEC,
3092 crate::common::RW,
3093 > {
3094 crate::common::RegisterField::<
3095 0,
3096 0x1,
3097 1,
3098 0,
3099 brdyenb::Pipe0Brdye,
3100 brdyenb::Pipe0Brdye,
3101 Brdyenb_SPEC,
3102 crate::common::RW,
3103 >::from_register(self, 0)
3104 }
3105
3106 #[doc = "BRDY Interrupt Enable for Pipe 1"]
3107 #[inline(always)]
3108 pub fn pipe1brdye(
3109 self,
3110 ) -> crate::common::RegisterField<
3111 1,
3112 0x1,
3113 1,
3114 0,
3115 brdyenb::Pipe1Brdye,
3116 brdyenb::Pipe1Brdye,
3117 Brdyenb_SPEC,
3118 crate::common::RW,
3119 > {
3120 crate::common::RegisterField::<
3121 1,
3122 0x1,
3123 1,
3124 0,
3125 brdyenb::Pipe1Brdye,
3126 brdyenb::Pipe1Brdye,
3127 Brdyenb_SPEC,
3128 crate::common::RW,
3129 >::from_register(self, 0)
3130 }
3131
3132 #[doc = "BRDY Interrupt Enable for Pipe 2"]
3133 #[inline(always)]
3134 pub fn pipe2brdye(
3135 self,
3136 ) -> crate::common::RegisterField<
3137 2,
3138 0x1,
3139 1,
3140 0,
3141 brdyenb::Pipe2Brdye,
3142 brdyenb::Pipe2Brdye,
3143 Brdyenb_SPEC,
3144 crate::common::RW,
3145 > {
3146 crate::common::RegisterField::<
3147 2,
3148 0x1,
3149 1,
3150 0,
3151 brdyenb::Pipe2Brdye,
3152 brdyenb::Pipe2Brdye,
3153 Brdyenb_SPEC,
3154 crate::common::RW,
3155 >::from_register(self, 0)
3156 }
3157
3158 #[doc = "BRDY Interrupt Enable for Pipe 3"]
3159 #[inline(always)]
3160 pub fn pipe3brdye(
3161 self,
3162 ) -> crate::common::RegisterField<
3163 3,
3164 0x1,
3165 1,
3166 0,
3167 brdyenb::Pipe3Brdye,
3168 brdyenb::Pipe3Brdye,
3169 Brdyenb_SPEC,
3170 crate::common::RW,
3171 > {
3172 crate::common::RegisterField::<
3173 3,
3174 0x1,
3175 1,
3176 0,
3177 brdyenb::Pipe3Brdye,
3178 brdyenb::Pipe3Brdye,
3179 Brdyenb_SPEC,
3180 crate::common::RW,
3181 >::from_register(self, 0)
3182 }
3183
3184 #[doc = "BRDY Interrupt Enable for Pipe 4"]
3185 #[inline(always)]
3186 pub fn pipe4brdye(
3187 self,
3188 ) -> crate::common::RegisterField<
3189 4,
3190 0x1,
3191 1,
3192 0,
3193 brdyenb::Pipe4Brdye,
3194 brdyenb::Pipe4Brdye,
3195 Brdyenb_SPEC,
3196 crate::common::RW,
3197 > {
3198 crate::common::RegisterField::<
3199 4,
3200 0x1,
3201 1,
3202 0,
3203 brdyenb::Pipe4Brdye,
3204 brdyenb::Pipe4Brdye,
3205 Brdyenb_SPEC,
3206 crate::common::RW,
3207 >::from_register(self, 0)
3208 }
3209
3210 #[doc = "BRDY Interrupt Enable for Pipe 5"]
3211 #[inline(always)]
3212 pub fn pipe5brdye(
3213 self,
3214 ) -> crate::common::RegisterField<
3215 5,
3216 0x1,
3217 1,
3218 0,
3219 brdyenb::Pipe5Brdye,
3220 brdyenb::Pipe5Brdye,
3221 Brdyenb_SPEC,
3222 crate::common::RW,
3223 > {
3224 crate::common::RegisterField::<
3225 5,
3226 0x1,
3227 1,
3228 0,
3229 brdyenb::Pipe5Brdye,
3230 brdyenb::Pipe5Brdye,
3231 Brdyenb_SPEC,
3232 crate::common::RW,
3233 >::from_register(self, 0)
3234 }
3235
3236 #[doc = "BRDY Interrupt Enable for Pipe 6"]
3237 #[inline(always)]
3238 pub fn pipe6brdye(
3239 self,
3240 ) -> crate::common::RegisterField<
3241 6,
3242 0x1,
3243 1,
3244 0,
3245 brdyenb::Pipe6Brdye,
3246 brdyenb::Pipe6Brdye,
3247 Brdyenb_SPEC,
3248 crate::common::RW,
3249 > {
3250 crate::common::RegisterField::<
3251 6,
3252 0x1,
3253 1,
3254 0,
3255 brdyenb::Pipe6Brdye,
3256 brdyenb::Pipe6Brdye,
3257 Brdyenb_SPEC,
3258 crate::common::RW,
3259 >::from_register(self, 0)
3260 }
3261
3262 #[doc = "BRDY Interrupt Enable for Pipe 7"]
3263 #[inline(always)]
3264 pub fn pipe7brdye(
3265 self,
3266 ) -> crate::common::RegisterField<
3267 7,
3268 0x1,
3269 1,
3270 0,
3271 brdyenb::Pipe7Brdye,
3272 brdyenb::Pipe7Brdye,
3273 Brdyenb_SPEC,
3274 crate::common::RW,
3275 > {
3276 crate::common::RegisterField::<
3277 7,
3278 0x1,
3279 1,
3280 0,
3281 brdyenb::Pipe7Brdye,
3282 brdyenb::Pipe7Brdye,
3283 Brdyenb_SPEC,
3284 crate::common::RW,
3285 >::from_register(self, 0)
3286 }
3287
3288 #[doc = "BRDY Interrupt Enable for Pipe 8"]
3289 #[inline(always)]
3290 pub fn pipe8brdye(
3291 self,
3292 ) -> crate::common::RegisterField<
3293 8,
3294 0x1,
3295 1,
3296 0,
3297 brdyenb::Pipe8Brdye,
3298 brdyenb::Pipe8Brdye,
3299 Brdyenb_SPEC,
3300 crate::common::RW,
3301 > {
3302 crate::common::RegisterField::<
3303 8,
3304 0x1,
3305 1,
3306 0,
3307 brdyenb::Pipe8Brdye,
3308 brdyenb::Pipe8Brdye,
3309 Brdyenb_SPEC,
3310 crate::common::RW,
3311 >::from_register(self, 0)
3312 }
3313
3314 #[doc = "BRDY Interrupt Enable for Pipe 9"]
3315 #[inline(always)]
3316 pub fn pipe9brdye(
3317 self,
3318 ) -> crate::common::RegisterField<
3319 9,
3320 0x1,
3321 1,
3322 0,
3323 brdyenb::Pipe9Brdye,
3324 brdyenb::Pipe9Brdye,
3325 Brdyenb_SPEC,
3326 crate::common::RW,
3327 > {
3328 crate::common::RegisterField::<
3329 9,
3330 0x1,
3331 1,
3332 0,
3333 brdyenb::Pipe9Brdye,
3334 brdyenb::Pipe9Brdye,
3335 Brdyenb_SPEC,
3336 crate::common::RW,
3337 >::from_register(self, 0)
3338 }
3339}
3340impl ::core::default::Default for Brdyenb {
3341 #[inline(always)]
3342 fn default() -> Brdyenb {
3343 <crate::RegValueT<Brdyenb_SPEC> as RegisterValue<_>>::new(0)
3344 }
3345}
3346pub mod brdyenb {
3347
3348 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3349 pub struct Pipe0Brdye_SPEC;
3350 pub type Pipe0Brdye = crate::EnumBitfieldStruct<u8, Pipe0Brdye_SPEC>;
3351 impl Pipe0Brdye {
3352 #[doc = "Disable interrupt request"]
3353 pub const _0: Self = Self::new(0);
3354
3355 #[doc = "Enable interrupt request"]
3356 pub const _1: Self = Self::new(1);
3357 }
3358 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3359 pub struct Pipe1Brdye_SPEC;
3360 pub type Pipe1Brdye = crate::EnumBitfieldStruct<u8, Pipe1Brdye_SPEC>;
3361 impl Pipe1Brdye {
3362 #[doc = "Disable interrupt request"]
3363 pub const _0: Self = Self::new(0);
3364
3365 #[doc = "Enable interrupt request"]
3366 pub const _1: Self = Self::new(1);
3367 }
3368 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3369 pub struct Pipe2Brdye_SPEC;
3370 pub type Pipe2Brdye = crate::EnumBitfieldStruct<u8, Pipe2Brdye_SPEC>;
3371 impl Pipe2Brdye {
3372 #[doc = "Disable interrupt request"]
3373 pub const _0: Self = Self::new(0);
3374
3375 #[doc = "Enable interrupt request"]
3376 pub const _1: Self = Self::new(1);
3377 }
3378 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3379 pub struct Pipe3Brdye_SPEC;
3380 pub type Pipe3Brdye = crate::EnumBitfieldStruct<u8, Pipe3Brdye_SPEC>;
3381 impl Pipe3Brdye {
3382 #[doc = "Disable interrupt request"]
3383 pub const _0: Self = Self::new(0);
3384
3385 #[doc = "Enable interrupt request"]
3386 pub const _1: Self = Self::new(1);
3387 }
3388 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3389 pub struct Pipe4Brdye_SPEC;
3390 pub type Pipe4Brdye = crate::EnumBitfieldStruct<u8, Pipe4Brdye_SPEC>;
3391 impl Pipe4Brdye {
3392 #[doc = "Disable interrupt request"]
3393 pub const _0: Self = Self::new(0);
3394
3395 #[doc = "Enable interrupt request"]
3396 pub const _1: Self = Self::new(1);
3397 }
3398 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3399 pub struct Pipe5Brdye_SPEC;
3400 pub type Pipe5Brdye = crate::EnumBitfieldStruct<u8, Pipe5Brdye_SPEC>;
3401 impl Pipe5Brdye {
3402 #[doc = "Disable interrupt request"]
3403 pub const _0: Self = Self::new(0);
3404
3405 #[doc = "Enable interrupt request"]
3406 pub const _1: Self = Self::new(1);
3407 }
3408 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3409 pub struct Pipe6Brdye_SPEC;
3410 pub type Pipe6Brdye = crate::EnumBitfieldStruct<u8, Pipe6Brdye_SPEC>;
3411 impl Pipe6Brdye {
3412 #[doc = "Disable interrupt request"]
3413 pub const _0: Self = Self::new(0);
3414
3415 #[doc = "Enable interrupt request"]
3416 pub const _1: Self = Self::new(1);
3417 }
3418 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3419 pub struct Pipe7Brdye_SPEC;
3420 pub type Pipe7Brdye = crate::EnumBitfieldStruct<u8, Pipe7Brdye_SPEC>;
3421 impl Pipe7Brdye {
3422 #[doc = "Disable interrupt request"]
3423 pub const _0: Self = Self::new(0);
3424
3425 #[doc = "Enable interrupt request"]
3426 pub const _1: Self = Self::new(1);
3427 }
3428 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3429 pub struct Pipe8Brdye_SPEC;
3430 pub type Pipe8Brdye = crate::EnumBitfieldStruct<u8, Pipe8Brdye_SPEC>;
3431 impl Pipe8Brdye {
3432 #[doc = "Disable interrupt request"]
3433 pub const _0: Self = Self::new(0);
3434
3435 #[doc = "Enable interrupt request"]
3436 pub const _1: Self = Self::new(1);
3437 }
3438 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3439 pub struct Pipe9Brdye_SPEC;
3440 pub type Pipe9Brdye = crate::EnumBitfieldStruct<u8, Pipe9Brdye_SPEC>;
3441 impl Pipe9Brdye {
3442 #[doc = "Disable interrupt request"]
3443 pub const _0: Self = Self::new(0);
3444
3445 #[doc = "Enable interrupt request"]
3446 pub const _1: Self = Self::new(1);
3447 }
3448}
3449#[doc(hidden)]
3450#[derive(Copy, Clone, Eq, PartialEq)]
3451pub struct Nrdyenb_SPEC;
3452impl crate::sealed::RegSpec for Nrdyenb_SPEC {
3453 type DataType = u16;
3454}
3455
3456#[doc = "NRDY Interrupt Enable Register"]
3457pub type Nrdyenb = crate::RegValueT<Nrdyenb_SPEC>;
3458
3459impl Nrdyenb {
3460 #[doc = "NRDY Interrupt Enable for Pipe 0"]
3461 #[inline(always)]
3462 pub fn pipe0nrdye(
3463 self,
3464 ) -> crate::common::RegisterField<
3465 0,
3466 0x1,
3467 1,
3468 0,
3469 nrdyenb::Pipe0Nrdye,
3470 nrdyenb::Pipe0Nrdye,
3471 Nrdyenb_SPEC,
3472 crate::common::RW,
3473 > {
3474 crate::common::RegisterField::<
3475 0,
3476 0x1,
3477 1,
3478 0,
3479 nrdyenb::Pipe0Nrdye,
3480 nrdyenb::Pipe0Nrdye,
3481 Nrdyenb_SPEC,
3482 crate::common::RW,
3483 >::from_register(self, 0)
3484 }
3485
3486 #[doc = "NRDY Interrupt Enable for Pipe 1"]
3487 #[inline(always)]
3488 pub fn pipe1nrdye(
3489 self,
3490 ) -> crate::common::RegisterField<
3491 1,
3492 0x1,
3493 1,
3494 0,
3495 nrdyenb::Pipe1Nrdye,
3496 nrdyenb::Pipe1Nrdye,
3497 Nrdyenb_SPEC,
3498 crate::common::RW,
3499 > {
3500 crate::common::RegisterField::<
3501 1,
3502 0x1,
3503 1,
3504 0,
3505 nrdyenb::Pipe1Nrdye,
3506 nrdyenb::Pipe1Nrdye,
3507 Nrdyenb_SPEC,
3508 crate::common::RW,
3509 >::from_register(self, 0)
3510 }
3511
3512 #[doc = "NRDY Interrupt Enable for Pipe 2"]
3513 #[inline(always)]
3514 pub fn pipe2nrdye(
3515 self,
3516 ) -> crate::common::RegisterField<
3517 2,
3518 0x1,
3519 1,
3520 0,
3521 nrdyenb::Pipe2Nrdye,
3522 nrdyenb::Pipe2Nrdye,
3523 Nrdyenb_SPEC,
3524 crate::common::RW,
3525 > {
3526 crate::common::RegisterField::<
3527 2,
3528 0x1,
3529 1,
3530 0,
3531 nrdyenb::Pipe2Nrdye,
3532 nrdyenb::Pipe2Nrdye,
3533 Nrdyenb_SPEC,
3534 crate::common::RW,
3535 >::from_register(self, 0)
3536 }
3537
3538 #[doc = "NRDY Interrupt Enable for Pipe 3"]
3539 #[inline(always)]
3540 pub fn pipe3nrdye(
3541 self,
3542 ) -> crate::common::RegisterField<
3543 3,
3544 0x1,
3545 1,
3546 0,
3547 nrdyenb::Pipe3Nrdye,
3548 nrdyenb::Pipe3Nrdye,
3549 Nrdyenb_SPEC,
3550 crate::common::RW,
3551 > {
3552 crate::common::RegisterField::<
3553 3,
3554 0x1,
3555 1,
3556 0,
3557 nrdyenb::Pipe3Nrdye,
3558 nrdyenb::Pipe3Nrdye,
3559 Nrdyenb_SPEC,
3560 crate::common::RW,
3561 >::from_register(self, 0)
3562 }
3563
3564 #[doc = "NRDY Interrupt Enable for Pipe 4"]
3565 #[inline(always)]
3566 pub fn pipe4nrdye(
3567 self,
3568 ) -> crate::common::RegisterField<
3569 4,
3570 0x1,
3571 1,
3572 0,
3573 nrdyenb::Pipe4Nrdye,
3574 nrdyenb::Pipe4Nrdye,
3575 Nrdyenb_SPEC,
3576 crate::common::RW,
3577 > {
3578 crate::common::RegisterField::<
3579 4,
3580 0x1,
3581 1,
3582 0,
3583 nrdyenb::Pipe4Nrdye,
3584 nrdyenb::Pipe4Nrdye,
3585 Nrdyenb_SPEC,
3586 crate::common::RW,
3587 >::from_register(self, 0)
3588 }
3589
3590 #[doc = "NRDY Interrupt Enable for Pipe 5"]
3591 #[inline(always)]
3592 pub fn pipe5nrdye(
3593 self,
3594 ) -> crate::common::RegisterField<
3595 5,
3596 0x1,
3597 1,
3598 0,
3599 nrdyenb::Pipe5Nrdye,
3600 nrdyenb::Pipe5Nrdye,
3601 Nrdyenb_SPEC,
3602 crate::common::RW,
3603 > {
3604 crate::common::RegisterField::<
3605 5,
3606 0x1,
3607 1,
3608 0,
3609 nrdyenb::Pipe5Nrdye,
3610 nrdyenb::Pipe5Nrdye,
3611 Nrdyenb_SPEC,
3612 crate::common::RW,
3613 >::from_register(self, 0)
3614 }
3615
3616 #[doc = "NRDY Interrupt Enable for Pipe 6"]
3617 #[inline(always)]
3618 pub fn pipe6nrdye(
3619 self,
3620 ) -> crate::common::RegisterField<
3621 6,
3622 0x1,
3623 1,
3624 0,
3625 nrdyenb::Pipe6Nrdye,
3626 nrdyenb::Pipe6Nrdye,
3627 Nrdyenb_SPEC,
3628 crate::common::RW,
3629 > {
3630 crate::common::RegisterField::<
3631 6,
3632 0x1,
3633 1,
3634 0,
3635 nrdyenb::Pipe6Nrdye,
3636 nrdyenb::Pipe6Nrdye,
3637 Nrdyenb_SPEC,
3638 crate::common::RW,
3639 >::from_register(self, 0)
3640 }
3641
3642 #[doc = "NRDY Interrupt Enable for Pipe 7"]
3643 #[inline(always)]
3644 pub fn pipe7nrdye(
3645 self,
3646 ) -> crate::common::RegisterField<
3647 7,
3648 0x1,
3649 1,
3650 0,
3651 nrdyenb::Pipe7Nrdye,
3652 nrdyenb::Pipe7Nrdye,
3653 Nrdyenb_SPEC,
3654 crate::common::RW,
3655 > {
3656 crate::common::RegisterField::<
3657 7,
3658 0x1,
3659 1,
3660 0,
3661 nrdyenb::Pipe7Nrdye,
3662 nrdyenb::Pipe7Nrdye,
3663 Nrdyenb_SPEC,
3664 crate::common::RW,
3665 >::from_register(self, 0)
3666 }
3667
3668 #[doc = "NRDY Interrupt Enable for Pipe 8"]
3669 #[inline(always)]
3670 pub fn pipe8nrdye(
3671 self,
3672 ) -> crate::common::RegisterField<
3673 8,
3674 0x1,
3675 1,
3676 0,
3677 nrdyenb::Pipe8Nrdye,
3678 nrdyenb::Pipe8Nrdye,
3679 Nrdyenb_SPEC,
3680 crate::common::RW,
3681 > {
3682 crate::common::RegisterField::<
3683 8,
3684 0x1,
3685 1,
3686 0,
3687 nrdyenb::Pipe8Nrdye,
3688 nrdyenb::Pipe8Nrdye,
3689 Nrdyenb_SPEC,
3690 crate::common::RW,
3691 >::from_register(self, 0)
3692 }
3693
3694 #[doc = "NRDY Interrupt Enable for Pipe 9"]
3695 #[inline(always)]
3696 pub fn pipe9nrdye(
3697 self,
3698 ) -> crate::common::RegisterField<
3699 9,
3700 0x1,
3701 1,
3702 0,
3703 nrdyenb::Pipe9Nrdye,
3704 nrdyenb::Pipe9Nrdye,
3705 Nrdyenb_SPEC,
3706 crate::common::RW,
3707 > {
3708 crate::common::RegisterField::<
3709 9,
3710 0x1,
3711 1,
3712 0,
3713 nrdyenb::Pipe9Nrdye,
3714 nrdyenb::Pipe9Nrdye,
3715 Nrdyenb_SPEC,
3716 crate::common::RW,
3717 >::from_register(self, 0)
3718 }
3719}
3720impl ::core::default::Default for Nrdyenb {
3721 #[inline(always)]
3722 fn default() -> Nrdyenb {
3723 <crate::RegValueT<Nrdyenb_SPEC> as RegisterValue<_>>::new(0)
3724 }
3725}
3726pub mod nrdyenb {
3727
3728 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3729 pub struct Pipe0Nrdye_SPEC;
3730 pub type Pipe0Nrdye = crate::EnumBitfieldStruct<u8, Pipe0Nrdye_SPEC>;
3731 impl Pipe0Nrdye {
3732 #[doc = "Disable interrupt request"]
3733 pub const _0: Self = Self::new(0);
3734
3735 #[doc = "Enable interrupt request"]
3736 pub const _1: Self = Self::new(1);
3737 }
3738 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3739 pub struct Pipe1Nrdye_SPEC;
3740 pub type Pipe1Nrdye = crate::EnumBitfieldStruct<u8, Pipe1Nrdye_SPEC>;
3741 impl Pipe1Nrdye {
3742 #[doc = "Disable interrupt request"]
3743 pub const _0: Self = Self::new(0);
3744
3745 #[doc = "Enable interrupt request"]
3746 pub const _1: Self = Self::new(1);
3747 }
3748 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3749 pub struct Pipe2Nrdye_SPEC;
3750 pub type Pipe2Nrdye = crate::EnumBitfieldStruct<u8, Pipe2Nrdye_SPEC>;
3751 impl Pipe2Nrdye {
3752 #[doc = "Disable interrupt request"]
3753 pub const _0: Self = Self::new(0);
3754
3755 #[doc = "Enable interrupt request"]
3756 pub const _1: Self = Self::new(1);
3757 }
3758 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3759 pub struct Pipe3Nrdye_SPEC;
3760 pub type Pipe3Nrdye = crate::EnumBitfieldStruct<u8, Pipe3Nrdye_SPEC>;
3761 impl Pipe3Nrdye {
3762 #[doc = "Disable interrupt request"]
3763 pub const _0: Self = Self::new(0);
3764
3765 #[doc = "Enable interrupt request"]
3766 pub const _1: Self = Self::new(1);
3767 }
3768 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3769 pub struct Pipe4Nrdye_SPEC;
3770 pub type Pipe4Nrdye = crate::EnumBitfieldStruct<u8, Pipe4Nrdye_SPEC>;
3771 impl Pipe4Nrdye {
3772 #[doc = "Disable interrupt request"]
3773 pub const _0: Self = Self::new(0);
3774
3775 #[doc = "Enable interrupt request"]
3776 pub const _1: Self = Self::new(1);
3777 }
3778 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3779 pub struct Pipe5Nrdye_SPEC;
3780 pub type Pipe5Nrdye = crate::EnumBitfieldStruct<u8, Pipe5Nrdye_SPEC>;
3781 impl Pipe5Nrdye {
3782 #[doc = "Disable interrupt request"]
3783 pub const _0: Self = Self::new(0);
3784
3785 #[doc = "Enable interrupt request"]
3786 pub const _1: Self = Self::new(1);
3787 }
3788 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3789 pub struct Pipe6Nrdye_SPEC;
3790 pub type Pipe6Nrdye = crate::EnumBitfieldStruct<u8, Pipe6Nrdye_SPEC>;
3791 impl Pipe6Nrdye {
3792 #[doc = "Disable interrupt request"]
3793 pub const _0: Self = Self::new(0);
3794
3795 #[doc = "Enable interrupt request"]
3796 pub const _1: Self = Self::new(1);
3797 }
3798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3799 pub struct Pipe7Nrdye_SPEC;
3800 pub type Pipe7Nrdye = crate::EnumBitfieldStruct<u8, Pipe7Nrdye_SPEC>;
3801 impl Pipe7Nrdye {
3802 #[doc = "Disable interrupt request"]
3803 pub const _0: Self = Self::new(0);
3804
3805 #[doc = "Enable interrupt request"]
3806 pub const _1: Self = Self::new(1);
3807 }
3808 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3809 pub struct Pipe8Nrdye_SPEC;
3810 pub type Pipe8Nrdye = crate::EnumBitfieldStruct<u8, Pipe8Nrdye_SPEC>;
3811 impl Pipe8Nrdye {
3812 #[doc = "Disable interrupt request"]
3813 pub const _0: Self = Self::new(0);
3814
3815 #[doc = "Enable interrupt request"]
3816 pub const _1: Self = Self::new(1);
3817 }
3818 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3819 pub struct Pipe9Nrdye_SPEC;
3820 pub type Pipe9Nrdye = crate::EnumBitfieldStruct<u8, Pipe9Nrdye_SPEC>;
3821 impl Pipe9Nrdye {
3822 #[doc = "Disable interrupt request"]
3823 pub const _0: Self = Self::new(0);
3824
3825 #[doc = "Enable interrupt request"]
3826 pub const _1: Self = Self::new(1);
3827 }
3828}
3829#[doc(hidden)]
3830#[derive(Copy, Clone, Eq, PartialEq)]
3831pub struct Bempenb_SPEC;
3832impl crate::sealed::RegSpec for Bempenb_SPEC {
3833 type DataType = u16;
3834}
3835
3836#[doc = "BEMP Interrupt Enable Register"]
3837pub type Bempenb = crate::RegValueT<Bempenb_SPEC>;
3838
3839impl Bempenb {
3840 #[doc = "BEMP Interrupt Enable for Pipe 0"]
3841 #[inline(always)]
3842 pub fn pipe0bempe(
3843 self,
3844 ) -> crate::common::RegisterField<
3845 0,
3846 0x1,
3847 1,
3848 0,
3849 bempenb::Pipe0Bempe,
3850 bempenb::Pipe0Bempe,
3851 Bempenb_SPEC,
3852 crate::common::RW,
3853 > {
3854 crate::common::RegisterField::<
3855 0,
3856 0x1,
3857 1,
3858 0,
3859 bempenb::Pipe0Bempe,
3860 bempenb::Pipe0Bempe,
3861 Bempenb_SPEC,
3862 crate::common::RW,
3863 >::from_register(self, 0)
3864 }
3865
3866 #[doc = "BEMP Interrupt Enable for Pipe 1"]
3867 #[inline(always)]
3868 pub fn pipe1bempe(
3869 self,
3870 ) -> crate::common::RegisterField<
3871 1,
3872 0x1,
3873 1,
3874 0,
3875 bempenb::Pipe1Bempe,
3876 bempenb::Pipe1Bempe,
3877 Bempenb_SPEC,
3878 crate::common::RW,
3879 > {
3880 crate::common::RegisterField::<
3881 1,
3882 0x1,
3883 1,
3884 0,
3885 bempenb::Pipe1Bempe,
3886 bempenb::Pipe1Bempe,
3887 Bempenb_SPEC,
3888 crate::common::RW,
3889 >::from_register(self, 0)
3890 }
3891
3892 #[doc = "BEMP Interrupt Enable for Pipe 2"]
3893 #[inline(always)]
3894 pub fn pipe2bempe(
3895 self,
3896 ) -> crate::common::RegisterField<
3897 2,
3898 0x1,
3899 1,
3900 0,
3901 bempenb::Pipe2Bempe,
3902 bempenb::Pipe2Bempe,
3903 Bempenb_SPEC,
3904 crate::common::RW,
3905 > {
3906 crate::common::RegisterField::<
3907 2,
3908 0x1,
3909 1,
3910 0,
3911 bempenb::Pipe2Bempe,
3912 bempenb::Pipe2Bempe,
3913 Bempenb_SPEC,
3914 crate::common::RW,
3915 >::from_register(self, 0)
3916 }
3917
3918 #[doc = "BEMP Interrupt Enable for Pipe 3"]
3919 #[inline(always)]
3920 pub fn pipe3bempe(
3921 self,
3922 ) -> crate::common::RegisterField<
3923 3,
3924 0x1,
3925 1,
3926 0,
3927 bempenb::Pipe3Bempe,
3928 bempenb::Pipe3Bempe,
3929 Bempenb_SPEC,
3930 crate::common::RW,
3931 > {
3932 crate::common::RegisterField::<
3933 3,
3934 0x1,
3935 1,
3936 0,
3937 bempenb::Pipe3Bempe,
3938 bempenb::Pipe3Bempe,
3939 Bempenb_SPEC,
3940 crate::common::RW,
3941 >::from_register(self, 0)
3942 }
3943
3944 #[doc = "BEMP Interrupt Enable for Pipe 4"]
3945 #[inline(always)]
3946 pub fn pipe4bempe(
3947 self,
3948 ) -> crate::common::RegisterField<
3949 4,
3950 0x1,
3951 1,
3952 0,
3953 bempenb::Pipe4Bempe,
3954 bempenb::Pipe4Bempe,
3955 Bempenb_SPEC,
3956 crate::common::RW,
3957 > {
3958 crate::common::RegisterField::<
3959 4,
3960 0x1,
3961 1,
3962 0,
3963 bempenb::Pipe4Bempe,
3964 bempenb::Pipe4Bempe,
3965 Bempenb_SPEC,
3966 crate::common::RW,
3967 >::from_register(self, 0)
3968 }
3969
3970 #[doc = "BEMP Interrupt Enable for Pipe 5"]
3971 #[inline(always)]
3972 pub fn pipe5bempe(
3973 self,
3974 ) -> crate::common::RegisterField<
3975 5,
3976 0x1,
3977 1,
3978 0,
3979 bempenb::Pipe5Bempe,
3980 bempenb::Pipe5Bempe,
3981 Bempenb_SPEC,
3982 crate::common::RW,
3983 > {
3984 crate::common::RegisterField::<
3985 5,
3986 0x1,
3987 1,
3988 0,
3989 bempenb::Pipe5Bempe,
3990 bempenb::Pipe5Bempe,
3991 Bempenb_SPEC,
3992 crate::common::RW,
3993 >::from_register(self, 0)
3994 }
3995
3996 #[doc = "BEMP Interrupt Enable for Pipe 6"]
3997 #[inline(always)]
3998 pub fn pipe6bempe(
3999 self,
4000 ) -> crate::common::RegisterField<
4001 6,
4002 0x1,
4003 1,
4004 0,
4005 bempenb::Pipe6Bempe,
4006 bempenb::Pipe6Bempe,
4007 Bempenb_SPEC,
4008 crate::common::RW,
4009 > {
4010 crate::common::RegisterField::<
4011 6,
4012 0x1,
4013 1,
4014 0,
4015 bempenb::Pipe6Bempe,
4016 bempenb::Pipe6Bempe,
4017 Bempenb_SPEC,
4018 crate::common::RW,
4019 >::from_register(self, 0)
4020 }
4021
4022 #[doc = "BEMP Interrupt Enable for Pipe 7"]
4023 #[inline(always)]
4024 pub fn pipe7bempe(
4025 self,
4026 ) -> crate::common::RegisterField<
4027 7,
4028 0x1,
4029 1,
4030 0,
4031 bempenb::Pipe7Bempe,
4032 bempenb::Pipe7Bempe,
4033 Bempenb_SPEC,
4034 crate::common::RW,
4035 > {
4036 crate::common::RegisterField::<
4037 7,
4038 0x1,
4039 1,
4040 0,
4041 bempenb::Pipe7Bempe,
4042 bempenb::Pipe7Bempe,
4043 Bempenb_SPEC,
4044 crate::common::RW,
4045 >::from_register(self, 0)
4046 }
4047
4048 #[doc = "BEMP Interrupt Enable for Pipe 8"]
4049 #[inline(always)]
4050 pub fn pipe8bempe(
4051 self,
4052 ) -> crate::common::RegisterField<
4053 8,
4054 0x1,
4055 1,
4056 0,
4057 bempenb::Pipe8Bempe,
4058 bempenb::Pipe8Bempe,
4059 Bempenb_SPEC,
4060 crate::common::RW,
4061 > {
4062 crate::common::RegisterField::<
4063 8,
4064 0x1,
4065 1,
4066 0,
4067 bempenb::Pipe8Bempe,
4068 bempenb::Pipe8Bempe,
4069 Bempenb_SPEC,
4070 crate::common::RW,
4071 >::from_register(self, 0)
4072 }
4073
4074 #[doc = "BEMP Interrupt Enable for Pipe 9"]
4075 #[inline(always)]
4076 pub fn pipe9bempe(
4077 self,
4078 ) -> crate::common::RegisterField<
4079 9,
4080 0x1,
4081 1,
4082 0,
4083 bempenb::Pipe9Bempe,
4084 bempenb::Pipe9Bempe,
4085 Bempenb_SPEC,
4086 crate::common::RW,
4087 > {
4088 crate::common::RegisterField::<
4089 9,
4090 0x1,
4091 1,
4092 0,
4093 bempenb::Pipe9Bempe,
4094 bempenb::Pipe9Bempe,
4095 Bempenb_SPEC,
4096 crate::common::RW,
4097 >::from_register(self, 0)
4098 }
4099}
4100impl ::core::default::Default for Bempenb {
4101 #[inline(always)]
4102 fn default() -> Bempenb {
4103 <crate::RegValueT<Bempenb_SPEC> as RegisterValue<_>>::new(0)
4104 }
4105}
4106pub mod bempenb {
4107
4108 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4109 pub struct Pipe0Bempe_SPEC;
4110 pub type Pipe0Bempe = crate::EnumBitfieldStruct<u8, Pipe0Bempe_SPEC>;
4111 impl Pipe0Bempe {
4112 #[doc = "Disable interrupt request"]
4113 pub const _0: Self = Self::new(0);
4114
4115 #[doc = "Enable interrupt request"]
4116 pub const _1: Self = Self::new(1);
4117 }
4118 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4119 pub struct Pipe1Bempe_SPEC;
4120 pub type Pipe1Bempe = crate::EnumBitfieldStruct<u8, Pipe1Bempe_SPEC>;
4121 impl Pipe1Bempe {
4122 #[doc = "Disable interrupt request"]
4123 pub const _0: Self = Self::new(0);
4124
4125 #[doc = "Enable interrupt request"]
4126 pub const _1: Self = Self::new(1);
4127 }
4128 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4129 pub struct Pipe2Bempe_SPEC;
4130 pub type Pipe2Bempe = crate::EnumBitfieldStruct<u8, Pipe2Bempe_SPEC>;
4131 impl Pipe2Bempe {
4132 #[doc = "Disable interrupt request"]
4133 pub const _0: Self = Self::new(0);
4134
4135 #[doc = "Enable interrupt request"]
4136 pub const _1: Self = Self::new(1);
4137 }
4138 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4139 pub struct Pipe3Bempe_SPEC;
4140 pub type Pipe3Bempe = crate::EnumBitfieldStruct<u8, Pipe3Bempe_SPEC>;
4141 impl Pipe3Bempe {
4142 #[doc = "Disable interrupt request"]
4143 pub const _0: Self = Self::new(0);
4144
4145 #[doc = "Enable interrupt request"]
4146 pub const _1: Self = Self::new(1);
4147 }
4148 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4149 pub struct Pipe4Bempe_SPEC;
4150 pub type Pipe4Bempe = crate::EnumBitfieldStruct<u8, Pipe4Bempe_SPEC>;
4151 impl Pipe4Bempe {
4152 #[doc = "Disable interrupt request"]
4153 pub const _0: Self = Self::new(0);
4154
4155 #[doc = "Enable interrupt request"]
4156 pub const _1: Self = Self::new(1);
4157 }
4158 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4159 pub struct Pipe5Bempe_SPEC;
4160 pub type Pipe5Bempe = crate::EnumBitfieldStruct<u8, Pipe5Bempe_SPEC>;
4161 impl Pipe5Bempe {
4162 #[doc = "Disable interrupt request"]
4163 pub const _0: Self = Self::new(0);
4164
4165 #[doc = "Enable interrupt request"]
4166 pub const _1: Self = Self::new(1);
4167 }
4168 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4169 pub struct Pipe6Bempe_SPEC;
4170 pub type Pipe6Bempe = crate::EnumBitfieldStruct<u8, Pipe6Bempe_SPEC>;
4171 impl Pipe6Bempe {
4172 #[doc = "Disable interrupt request"]
4173 pub const _0: Self = Self::new(0);
4174
4175 #[doc = "Enable interrupt request"]
4176 pub const _1: Self = Self::new(1);
4177 }
4178 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4179 pub struct Pipe7Bempe_SPEC;
4180 pub type Pipe7Bempe = crate::EnumBitfieldStruct<u8, Pipe7Bempe_SPEC>;
4181 impl Pipe7Bempe {
4182 #[doc = "Disable interrupt request"]
4183 pub const _0: Self = Self::new(0);
4184
4185 #[doc = "Enable interrupt request"]
4186 pub const _1: Self = Self::new(1);
4187 }
4188 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4189 pub struct Pipe8Bempe_SPEC;
4190 pub type Pipe8Bempe = crate::EnumBitfieldStruct<u8, Pipe8Bempe_SPEC>;
4191 impl Pipe8Bempe {
4192 #[doc = "Disable interrupt request"]
4193 pub const _0: Self = Self::new(0);
4194
4195 #[doc = "Enable interrupt request"]
4196 pub const _1: Self = Self::new(1);
4197 }
4198 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4199 pub struct Pipe9Bempe_SPEC;
4200 pub type Pipe9Bempe = crate::EnumBitfieldStruct<u8, Pipe9Bempe_SPEC>;
4201 impl Pipe9Bempe {
4202 #[doc = "Disable interrupt request"]
4203 pub const _0: Self = Self::new(0);
4204
4205 #[doc = "Enable interrupt request"]
4206 pub const _1: Self = Self::new(1);
4207 }
4208}
4209#[doc(hidden)]
4210#[derive(Copy, Clone, Eq, PartialEq)]
4211pub struct Sofcfg_SPEC;
4212impl crate::sealed::RegSpec for Sofcfg_SPEC {
4213 type DataType = u16;
4214}
4215
4216#[doc = "SOF Output Configuration Register"]
4217pub type Sofcfg = crate::RegValueT<Sofcfg_SPEC>;
4218
4219impl Sofcfg {
4220 #[doc = "Edge Interrupt Output Status Monitor"]
4221 #[inline(always)]
4222 pub fn edgests(
4223 self,
4224 ) -> crate::common::RegisterFieldBool<4, 1, 0, Sofcfg_SPEC, crate::common::R> {
4225 crate::common::RegisterFieldBool::<4, 1, 0, Sofcfg_SPEC, crate::common::R>::from_register(
4226 self, 0,
4227 )
4228 }
4229
4230 #[doc = "BRDY Interrupt Status Clear Timing"]
4231 #[inline(always)]
4232 pub fn brdym(
4233 self,
4234 ) -> crate::common::RegisterField<
4235 6,
4236 0x1,
4237 1,
4238 0,
4239 sofcfg::Brdym,
4240 sofcfg::Brdym,
4241 Sofcfg_SPEC,
4242 crate::common::RW,
4243 > {
4244 crate::common::RegisterField::<
4245 6,
4246 0x1,
4247 1,
4248 0,
4249 sofcfg::Brdym,
4250 sofcfg::Brdym,
4251 Sofcfg_SPEC,
4252 crate::common::RW,
4253 >::from_register(self, 0)
4254 }
4255
4256 #[doc = "Transaction-Enabled Time Select"]
4257 #[inline(always)]
4258 pub fn trnensel(
4259 self,
4260 ) -> crate::common::RegisterField<
4261 8,
4262 0x1,
4263 1,
4264 0,
4265 sofcfg::Trnensel,
4266 sofcfg::Trnensel,
4267 Sofcfg_SPEC,
4268 crate::common::RW,
4269 > {
4270 crate::common::RegisterField::<
4271 8,
4272 0x1,
4273 1,
4274 0,
4275 sofcfg::Trnensel,
4276 sofcfg::Trnensel,
4277 Sofcfg_SPEC,
4278 crate::common::RW,
4279 >::from_register(self, 0)
4280 }
4281}
4282impl ::core::default::Default for Sofcfg {
4283 #[inline(always)]
4284 fn default() -> Sofcfg {
4285 <crate::RegValueT<Sofcfg_SPEC> as RegisterValue<_>>::new(0)
4286 }
4287}
4288pub mod sofcfg {
4289
4290 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4291 pub struct Brdym_SPEC;
4292 pub type Brdym = crate::EnumBitfieldStruct<u8, Brdym_SPEC>;
4293 impl Brdym {
4294 #[doc = "Clear BRDY flag by software"]
4295 pub const _0: Self = Self::new(0);
4296
4297 #[doc = "Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer"]
4298 pub const _1: Self = Self::new(1);
4299 }
4300 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4301 pub struct Trnensel_SPEC;
4302 pub type Trnensel = crate::EnumBitfieldStruct<u8, Trnensel_SPEC>;
4303 impl Trnensel {
4304 #[doc = "Not low-speed communication"]
4305 pub const _0: Self = Self::new(0);
4306
4307 #[doc = "Low-speed communication"]
4308 pub const _1: Self = Self::new(1);
4309 }
4310}
4311#[doc(hidden)]
4312#[derive(Copy, Clone, Eq, PartialEq)]
4313pub struct Intsts0_SPEC;
4314impl crate::sealed::RegSpec for Intsts0_SPEC {
4315 type DataType = u16;
4316}
4317
4318#[doc = "Interrupt Status Register 0"]
4319pub type Intsts0 = crate::RegValueT<Intsts0_SPEC>;
4320
4321impl Intsts0 {
4322 #[doc = "Control Transfer Stage"]
4323 #[inline(always)]
4324 pub fn ctsq(
4325 self,
4326 ) -> crate::common::RegisterField<
4327 0,
4328 0x7,
4329 1,
4330 0,
4331 intsts0::Ctsq,
4332 intsts0::Ctsq,
4333 Intsts0_SPEC,
4334 crate::common::R,
4335 > {
4336 crate::common::RegisterField::<
4337 0,
4338 0x7,
4339 1,
4340 0,
4341 intsts0::Ctsq,
4342 intsts0::Ctsq,
4343 Intsts0_SPEC,
4344 crate::common::R,
4345 >::from_register(self, 0)
4346 }
4347
4348 #[doc = "USB Request Reception"]
4349 #[inline(always)]
4350 pub fn valid(
4351 self,
4352 ) -> crate::common::RegisterField<
4353 3,
4354 0x1,
4355 1,
4356 0,
4357 intsts0::Valid,
4358 intsts0::Valid,
4359 Intsts0_SPEC,
4360 crate::common::RW,
4361 > {
4362 crate::common::RegisterField::<
4363 3,
4364 0x1,
4365 1,
4366 0,
4367 intsts0::Valid,
4368 intsts0::Valid,
4369 Intsts0_SPEC,
4370 crate::common::RW,
4371 >::from_register(self, 0)
4372 }
4373
4374 #[doc = "Device State"]
4375 #[inline(always)]
4376 pub fn dvsq(
4377 self,
4378 ) -> crate::common::RegisterField<
4379 4,
4380 0x7,
4381 1,
4382 0,
4383 intsts0::Dvsq,
4384 intsts0::Dvsq,
4385 Intsts0_SPEC,
4386 crate::common::R,
4387 > {
4388 crate::common::RegisterField::<
4389 4,
4390 0x7,
4391 1,
4392 0,
4393 intsts0::Dvsq,
4394 intsts0::Dvsq,
4395 Intsts0_SPEC,
4396 crate::common::R,
4397 >::from_register(self, 0)
4398 }
4399
4400 #[doc = "VBUS Input Status"]
4401 #[inline(always)]
4402 pub fn vbsts(
4403 self,
4404 ) -> crate::common::RegisterField<
4405 7,
4406 0x1,
4407 1,
4408 0,
4409 intsts0::Vbsts,
4410 intsts0::Vbsts,
4411 Intsts0_SPEC,
4412 crate::common::R,
4413 > {
4414 crate::common::RegisterField::<
4415 7,
4416 0x1,
4417 1,
4418 0,
4419 intsts0::Vbsts,
4420 intsts0::Vbsts,
4421 Intsts0_SPEC,
4422 crate::common::R,
4423 >::from_register(self, 0)
4424 }
4425
4426 #[doc = "Buffer Ready Interrupt Status"]
4427 #[inline(always)]
4428 pub fn brdy(
4429 self,
4430 ) -> crate::common::RegisterField<
4431 8,
4432 0x1,
4433 1,
4434 0,
4435 intsts0::Brdy,
4436 intsts0::Brdy,
4437 Intsts0_SPEC,
4438 crate::common::R,
4439 > {
4440 crate::common::RegisterField::<
4441 8,
4442 0x1,
4443 1,
4444 0,
4445 intsts0::Brdy,
4446 intsts0::Brdy,
4447 Intsts0_SPEC,
4448 crate::common::R,
4449 >::from_register(self, 0)
4450 }
4451
4452 #[doc = "Buffer Not Ready Interrupt Status"]
4453 #[inline(always)]
4454 pub fn nrdy(
4455 self,
4456 ) -> crate::common::RegisterField<
4457 9,
4458 0x1,
4459 1,
4460 0,
4461 intsts0::Nrdy,
4462 intsts0::Nrdy,
4463 Intsts0_SPEC,
4464 crate::common::R,
4465 > {
4466 crate::common::RegisterField::<
4467 9,
4468 0x1,
4469 1,
4470 0,
4471 intsts0::Nrdy,
4472 intsts0::Nrdy,
4473 Intsts0_SPEC,
4474 crate::common::R,
4475 >::from_register(self, 0)
4476 }
4477
4478 #[doc = "Buffer Empty Interrupt Status"]
4479 #[inline(always)]
4480 pub fn bemp(
4481 self,
4482 ) -> crate::common::RegisterField<
4483 10,
4484 0x1,
4485 1,
4486 0,
4487 intsts0::Bemp,
4488 intsts0::Bemp,
4489 Intsts0_SPEC,
4490 crate::common::R,
4491 > {
4492 crate::common::RegisterField::<
4493 10,
4494 0x1,
4495 1,
4496 0,
4497 intsts0::Bemp,
4498 intsts0::Bemp,
4499 Intsts0_SPEC,
4500 crate::common::R,
4501 >::from_register(self, 0)
4502 }
4503
4504 #[doc = "Control Transfer Stage Transition Interrupt Status"]
4505 #[inline(always)]
4506 pub fn ctrt(
4507 self,
4508 ) -> crate::common::RegisterField<
4509 11,
4510 0x1,
4511 1,
4512 0,
4513 intsts0::Ctrt,
4514 intsts0::Ctrt,
4515 Intsts0_SPEC,
4516 crate::common::RW,
4517 > {
4518 crate::common::RegisterField::<
4519 11,
4520 0x1,
4521 1,
4522 0,
4523 intsts0::Ctrt,
4524 intsts0::Ctrt,
4525 Intsts0_SPEC,
4526 crate::common::RW,
4527 >::from_register(self, 0)
4528 }
4529
4530 #[doc = "Device State Transition Interrupt Status"]
4531 #[inline(always)]
4532 pub fn dvst(
4533 self,
4534 ) -> crate::common::RegisterField<
4535 12,
4536 0x1,
4537 1,
4538 0,
4539 intsts0::Dvst,
4540 intsts0::Dvst,
4541 Intsts0_SPEC,
4542 crate::common::RW,
4543 > {
4544 crate::common::RegisterField::<
4545 12,
4546 0x1,
4547 1,
4548 0,
4549 intsts0::Dvst,
4550 intsts0::Dvst,
4551 Intsts0_SPEC,
4552 crate::common::RW,
4553 >::from_register(self, 0)
4554 }
4555
4556 #[doc = "Frame Number Refresh Interrupt Status"]
4557 #[inline(always)]
4558 pub fn sofr(
4559 self,
4560 ) -> crate::common::RegisterField<
4561 13,
4562 0x1,
4563 1,
4564 0,
4565 intsts0::Sofr,
4566 intsts0::Sofr,
4567 Intsts0_SPEC,
4568 crate::common::RW,
4569 > {
4570 crate::common::RegisterField::<
4571 13,
4572 0x1,
4573 1,
4574 0,
4575 intsts0::Sofr,
4576 intsts0::Sofr,
4577 Intsts0_SPEC,
4578 crate::common::RW,
4579 >::from_register(self, 0)
4580 }
4581
4582 #[doc = "Resume Interrupt Status"]
4583 #[inline(always)]
4584 pub fn resm(
4585 self,
4586 ) -> crate::common::RegisterField<
4587 14,
4588 0x1,
4589 1,
4590 0,
4591 intsts0::Resm,
4592 intsts0::Resm,
4593 Intsts0_SPEC,
4594 crate::common::RW,
4595 > {
4596 crate::common::RegisterField::<
4597 14,
4598 0x1,
4599 1,
4600 0,
4601 intsts0::Resm,
4602 intsts0::Resm,
4603 Intsts0_SPEC,
4604 crate::common::RW,
4605 >::from_register(self, 0)
4606 }
4607
4608 #[doc = "VBUS Interrupt Status"]
4609 #[inline(always)]
4610 pub fn vbint(
4611 self,
4612 ) -> crate::common::RegisterField<
4613 15,
4614 0x1,
4615 1,
4616 0,
4617 intsts0::Vbint,
4618 intsts0::Vbint,
4619 Intsts0_SPEC,
4620 crate::common::RW,
4621 > {
4622 crate::common::RegisterField::<
4623 15,
4624 0x1,
4625 1,
4626 0,
4627 intsts0::Vbint,
4628 intsts0::Vbint,
4629 Intsts0_SPEC,
4630 crate::common::RW,
4631 >::from_register(self, 0)
4632 }
4633}
4634impl ::core::default::Default for Intsts0 {
4635 #[inline(always)]
4636 fn default() -> Intsts0 {
4637 <crate::RegValueT<Intsts0_SPEC> as RegisterValue<_>>::new(0)
4638 }
4639}
4640pub mod intsts0 {
4641
4642 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4643 pub struct Ctsq_SPEC;
4644 pub type Ctsq = crate::EnumBitfieldStruct<u8, Ctsq_SPEC>;
4645 impl Ctsq {
4646 #[doc = "Idle or setup stage"]
4647 pub const _000: Self = Self::new(0);
4648
4649 #[doc = "Control read data stage"]
4650 pub const _001: Self = Self::new(1);
4651
4652 #[doc = "Control read status stage"]
4653 pub const _010: Self = Self::new(2);
4654
4655 #[doc = "Control write data stage"]
4656 pub const _011: Self = Self::new(3);
4657
4658 #[doc = "Control write status stage"]
4659 pub const _100: Self = Self::new(4);
4660
4661 #[doc = "Control write (no data) status stage"]
4662 pub const _101: Self = Self::new(5);
4663
4664 #[doc = "Control transfer sequence error"]
4665 pub const _110: Self = Self::new(6);
4666 }
4667 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4668 pub struct Valid_SPEC;
4669 pub type Valid = crate::EnumBitfieldStruct<u8, Valid_SPEC>;
4670 impl Valid {
4671 #[doc = "Setup packet not received"]
4672 pub const _0: Self = Self::new(0);
4673
4674 #[doc = "Setup packet received"]
4675 pub const _1: Self = Self::new(1);
4676 }
4677 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4678 pub struct Dvsq_SPEC;
4679 pub type Dvsq = crate::EnumBitfieldStruct<u8, Dvsq_SPEC>;
4680 impl Dvsq {
4681 #[doc = "Powered state"]
4682 pub const _000: Self = Self::new(0);
4683
4684 #[doc = "Default state"]
4685 pub const _001: Self = Self::new(1);
4686
4687 #[doc = "Address state"]
4688 pub const _010: Self = Self::new(2);
4689
4690 #[doc = "Configured state"]
4691 pub const _011: Self = Self::new(3);
4692 }
4693 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4694 pub struct Vbsts_SPEC;
4695 pub type Vbsts = crate::EnumBitfieldStruct<u8, Vbsts_SPEC>;
4696 impl Vbsts {
4697 #[doc = "USB_VBUS pin is low"]
4698 pub const _0: Self = Self::new(0);
4699
4700 #[doc = "USB_VBUS pin is high"]
4701 pub const _1: Self = Self::new(1);
4702 }
4703 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4704 pub struct Brdy_SPEC;
4705 pub type Brdy = crate::EnumBitfieldStruct<u8, Brdy_SPEC>;
4706 impl Brdy {
4707 #[doc = "No BRDY interrupt occurred"]
4708 pub const _0: Self = Self::new(0);
4709
4710 #[doc = "BRDY interrupt occurred"]
4711 pub const _1: Self = Self::new(1);
4712 }
4713 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4714 pub struct Nrdy_SPEC;
4715 pub type Nrdy = crate::EnumBitfieldStruct<u8, Nrdy_SPEC>;
4716 impl Nrdy {
4717 #[doc = "No NRDY interrupt occurred"]
4718 pub const _0: Self = Self::new(0);
4719
4720 #[doc = "NRDY interrupt occurred"]
4721 pub const _1: Self = Self::new(1);
4722 }
4723 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4724 pub struct Bemp_SPEC;
4725 pub type Bemp = crate::EnumBitfieldStruct<u8, Bemp_SPEC>;
4726 impl Bemp {
4727 #[doc = "No BEMP interrupt occurred"]
4728 pub const _0: Self = Self::new(0);
4729
4730 #[doc = "BEMP interrupt occurred"]
4731 pub const _1: Self = Self::new(1);
4732 }
4733 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4734 pub struct Ctrt_SPEC;
4735 pub type Ctrt = crate::EnumBitfieldStruct<u8, Ctrt_SPEC>;
4736 impl Ctrt {
4737 #[doc = "No control transfer stage transition interrupt occurred"]
4738 pub const _0: Self = Self::new(0);
4739
4740 #[doc = "Control transfer stage transition interrupt occurred"]
4741 pub const _1: Self = Self::new(1);
4742 }
4743 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4744 pub struct Dvst_SPEC;
4745 pub type Dvst = crate::EnumBitfieldStruct<u8, Dvst_SPEC>;
4746 impl Dvst {
4747 #[doc = "No device state transition interrupt occurred"]
4748 pub const _0: Self = Self::new(0);
4749
4750 #[doc = "Device state transition interrupt occurred"]
4751 pub const _1: Self = Self::new(1);
4752 }
4753 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4754 pub struct Sofr_SPEC;
4755 pub type Sofr = crate::EnumBitfieldStruct<u8, Sofr_SPEC>;
4756 impl Sofr {
4757 #[doc = "No SOF interrupt occurred"]
4758 pub const _0: Self = Self::new(0);
4759
4760 #[doc = "SOF interrupt occurred"]
4761 pub const _1: Self = Self::new(1);
4762 }
4763 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4764 pub struct Resm_SPEC;
4765 pub type Resm = crate::EnumBitfieldStruct<u8, Resm_SPEC>;
4766 impl Resm {
4767 #[doc = "No resume interrupt occurred"]
4768 pub const _0: Self = Self::new(0);
4769
4770 #[doc = "Resume interrupt occurred"]
4771 pub const _1: Self = Self::new(1);
4772 }
4773 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4774 pub struct Vbint_SPEC;
4775 pub type Vbint = crate::EnumBitfieldStruct<u8, Vbint_SPEC>;
4776 impl Vbint {
4777 #[doc = "No VBUS interrupt occurred"]
4778 pub const _0: Self = Self::new(0);
4779
4780 #[doc = "VBUS interrupt occurred"]
4781 pub const _1: Self = Self::new(1);
4782 }
4783}
4784#[doc(hidden)]
4785#[derive(Copy, Clone, Eq, PartialEq)]
4786pub struct Intsts1_SPEC;
4787impl crate::sealed::RegSpec for Intsts1_SPEC {
4788 type DataType = u16;
4789}
4790
4791#[doc = "Interrupt Status Register 1"]
4792pub type Intsts1 = crate::RegValueT<Intsts1_SPEC>;
4793
4794impl Intsts1 {
4795 #[doc = "PDDET Detection Interrupt Status Flag"]
4796 #[inline(always)]
4797 pub fn pddetint(
4798 self,
4799 ) -> crate::common::RegisterField<
4800 0,
4801 0x1,
4802 1,
4803 0,
4804 intsts1::Pddetint,
4805 intsts1::Pddetint,
4806 Intsts1_SPEC,
4807 crate::common::RW,
4808 > {
4809 crate::common::RegisterField::<
4810 0,
4811 0x1,
4812 1,
4813 0,
4814 intsts1::Pddetint,
4815 intsts1::Pddetint,
4816 Intsts1_SPEC,
4817 crate::common::RW,
4818 >::from_register(self, 0)
4819 }
4820
4821 #[doc = "Setup Transaction Normal Response Interrupt Status"]
4822 #[inline(always)]
4823 pub fn sack(
4824 self,
4825 ) -> crate::common::RegisterField<
4826 4,
4827 0x1,
4828 1,
4829 0,
4830 intsts1::Sack,
4831 intsts1::Sack,
4832 Intsts1_SPEC,
4833 crate::common::RW,
4834 > {
4835 crate::common::RegisterField::<
4836 4,
4837 0x1,
4838 1,
4839 0,
4840 intsts1::Sack,
4841 intsts1::Sack,
4842 Intsts1_SPEC,
4843 crate::common::RW,
4844 >::from_register(self, 0)
4845 }
4846
4847 #[doc = "Setup Transaction Error Interrupt Status"]
4848 #[inline(always)]
4849 pub fn sign(
4850 self,
4851 ) -> crate::common::RegisterField<
4852 5,
4853 0x1,
4854 1,
4855 0,
4856 intsts1::Sign,
4857 intsts1::Sign,
4858 Intsts1_SPEC,
4859 crate::common::RW,
4860 > {
4861 crate::common::RegisterField::<
4862 5,
4863 0x1,
4864 1,
4865 0,
4866 intsts1::Sign,
4867 intsts1::Sign,
4868 Intsts1_SPEC,
4869 crate::common::RW,
4870 >::from_register(self, 0)
4871 }
4872
4873 #[doc = "EOF Error Detection Interrupt Status"]
4874 #[inline(always)]
4875 pub fn eoferr(
4876 self,
4877 ) -> crate::common::RegisterField<
4878 6,
4879 0x1,
4880 1,
4881 0,
4882 intsts1::Eoferr,
4883 intsts1::Eoferr,
4884 Intsts1_SPEC,
4885 crate::common::RW,
4886 > {
4887 crate::common::RegisterField::<
4888 6,
4889 0x1,
4890 1,
4891 0,
4892 intsts1::Eoferr,
4893 intsts1::Eoferr,
4894 Intsts1_SPEC,
4895 crate::common::RW,
4896 >::from_register(self, 0)
4897 }
4898
4899 #[doc = "ATTCH Interrupt Status"]
4900 #[inline(always)]
4901 pub fn attch(
4902 self,
4903 ) -> crate::common::RegisterField<
4904 11,
4905 0x1,
4906 1,
4907 0,
4908 intsts1::Attch,
4909 intsts1::Attch,
4910 Intsts1_SPEC,
4911 crate::common::RW,
4912 > {
4913 crate::common::RegisterField::<
4914 11,
4915 0x1,
4916 1,
4917 0,
4918 intsts1::Attch,
4919 intsts1::Attch,
4920 Intsts1_SPEC,
4921 crate::common::RW,
4922 >::from_register(self, 0)
4923 }
4924
4925 #[doc = "USB Disconnection Detection Interrupt Status"]
4926 #[inline(always)]
4927 pub fn dtch(
4928 self,
4929 ) -> crate::common::RegisterField<
4930 12,
4931 0x1,
4932 1,
4933 0,
4934 intsts1::Dtch,
4935 intsts1::Dtch,
4936 Intsts1_SPEC,
4937 crate::common::RW,
4938 > {
4939 crate::common::RegisterField::<
4940 12,
4941 0x1,
4942 1,
4943 0,
4944 intsts1::Dtch,
4945 intsts1::Dtch,
4946 Intsts1_SPEC,
4947 crate::common::RW,
4948 >::from_register(self, 0)
4949 }
4950
4951 #[doc = "USB Bus Change Interrupt Status"]
4952 #[inline(always)]
4953 pub fn bchg(
4954 self,
4955 ) -> crate::common::RegisterField<
4956 14,
4957 0x1,
4958 1,
4959 0,
4960 intsts1::Bchg,
4961 intsts1::Bchg,
4962 Intsts1_SPEC,
4963 crate::common::RW,
4964 > {
4965 crate::common::RegisterField::<
4966 14,
4967 0x1,
4968 1,
4969 0,
4970 intsts1::Bchg,
4971 intsts1::Bchg,
4972 Intsts1_SPEC,
4973 crate::common::RW,
4974 >::from_register(self, 0)
4975 }
4976
4977 #[doc = "Overcurrent Input Change Interrupt Status"]
4978 #[inline(always)]
4979 pub fn ovrcr(
4980 self,
4981 ) -> crate::common::RegisterField<
4982 15,
4983 0x1,
4984 1,
4985 0,
4986 intsts1::Ovrcr,
4987 intsts1::Ovrcr,
4988 Intsts1_SPEC,
4989 crate::common::RW,
4990 > {
4991 crate::common::RegisterField::<
4992 15,
4993 0x1,
4994 1,
4995 0,
4996 intsts1::Ovrcr,
4997 intsts1::Ovrcr,
4998 Intsts1_SPEC,
4999 crate::common::RW,
5000 >::from_register(self, 0)
5001 }
5002}
5003impl ::core::default::Default for Intsts1 {
5004 #[inline(always)]
5005 fn default() -> Intsts1 {
5006 <crate::RegValueT<Intsts1_SPEC> as RegisterValue<_>>::new(0)
5007 }
5008}
5009pub mod intsts1 {
5010
5011 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5012 pub struct Pddetint_SPEC;
5013 pub type Pddetint = crate::EnumBitfieldStruct<u8, Pddetint_SPEC>;
5014 impl Pddetint {
5015 #[doc = "No PDDET interrupt occurred"]
5016 pub const _0: Self = Self::new(0);
5017
5018 #[doc = "PDDET interrupt occurred"]
5019 pub const _1: Self = Self::new(1);
5020 }
5021 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5022 pub struct Sack_SPEC;
5023 pub type Sack = crate::EnumBitfieldStruct<u8, Sack_SPEC>;
5024 impl Sack {
5025 #[doc = "No SACK interrupt occurred"]
5026 pub const _0: Self = Self::new(0);
5027
5028 #[doc = "SACK interrupt occurred"]
5029 pub const _1: Self = Self::new(1);
5030 }
5031 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5032 pub struct Sign_SPEC;
5033 pub type Sign = crate::EnumBitfieldStruct<u8, Sign_SPEC>;
5034 impl Sign {
5035 #[doc = "No SIGN interrupt occurred"]
5036 pub const _0: Self = Self::new(0);
5037
5038 #[doc = "SIGN interrupt occurred"]
5039 pub const _1: Self = Self::new(1);
5040 }
5041 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5042 pub struct Eoferr_SPEC;
5043 pub type Eoferr = crate::EnumBitfieldStruct<u8, Eoferr_SPEC>;
5044 impl Eoferr {
5045 #[doc = "No EOFERR interrupt occurred"]
5046 pub const _0: Self = Self::new(0);
5047
5048 #[doc = "EOFERR interrupt occurred"]
5049 pub const _1: Self = Self::new(1);
5050 }
5051 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5052 pub struct Attch_SPEC;
5053 pub type Attch = crate::EnumBitfieldStruct<u8, Attch_SPEC>;
5054 impl Attch {
5055 #[doc = "No ATTCH interrupt occurred"]
5056 pub const _0: Self = Self::new(0);
5057
5058 #[doc = "ATTCH interrupt occurred"]
5059 pub const _1: Self = Self::new(1);
5060 }
5061 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5062 pub struct Dtch_SPEC;
5063 pub type Dtch = crate::EnumBitfieldStruct<u8, Dtch_SPEC>;
5064 impl Dtch {
5065 #[doc = "No DTCH interrupt occurred"]
5066 pub const _0: Self = Self::new(0);
5067
5068 #[doc = "DTCH interrupt occurred"]
5069 pub const _1: Self = Self::new(1);
5070 }
5071 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5072 pub struct Bchg_SPEC;
5073 pub type Bchg = crate::EnumBitfieldStruct<u8, Bchg_SPEC>;
5074 impl Bchg {
5075 #[doc = "No BCHG interrupt occurred"]
5076 pub const _0: Self = Self::new(0);
5077
5078 #[doc = "BCHG interrupt occurred"]
5079 pub const _1: Self = Self::new(1);
5080 }
5081 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5082 pub struct Ovrcr_SPEC;
5083 pub type Ovrcr = crate::EnumBitfieldStruct<u8, Ovrcr_SPEC>;
5084 impl Ovrcr {
5085 #[doc = "No OVRCR interrupt occurred"]
5086 pub const _0: Self = Self::new(0);
5087
5088 #[doc = "OVRCR interrupt occurred"]
5089 pub const _1: Self = Self::new(1);
5090 }
5091}
5092#[doc(hidden)]
5093#[derive(Copy, Clone, Eq, PartialEq)]
5094pub struct Brdysts_SPEC;
5095impl crate::sealed::RegSpec for Brdysts_SPEC {
5096 type DataType = u16;
5097}
5098
5099#[doc = "BRDY Interrupt Status Register"]
5100pub type Brdysts = crate::RegValueT<Brdysts_SPEC>;
5101
5102impl Brdysts {
5103 #[doc = "BRDY Interrupt Status for Pipe 0"]
5104 #[inline(always)]
5105 pub fn pipe0brdy(
5106 self,
5107 ) -> crate::common::RegisterField<
5108 0,
5109 0x1,
5110 1,
5111 0,
5112 brdysts::Pipe0Brdy,
5113 brdysts::Pipe0Brdy,
5114 Brdysts_SPEC,
5115 crate::common::RW,
5116 > {
5117 crate::common::RegisterField::<
5118 0,
5119 0x1,
5120 1,
5121 0,
5122 brdysts::Pipe0Brdy,
5123 brdysts::Pipe0Brdy,
5124 Brdysts_SPEC,
5125 crate::common::RW,
5126 >::from_register(self, 0)
5127 }
5128
5129 #[doc = "BRDY Interrupt Status for Pipe 1"]
5130 #[inline(always)]
5131 pub fn pipe1brdy(
5132 self,
5133 ) -> crate::common::RegisterField<
5134 1,
5135 0x1,
5136 1,
5137 0,
5138 brdysts::Pipe1Brdy,
5139 brdysts::Pipe1Brdy,
5140 Brdysts_SPEC,
5141 crate::common::RW,
5142 > {
5143 crate::common::RegisterField::<
5144 1,
5145 0x1,
5146 1,
5147 0,
5148 brdysts::Pipe1Brdy,
5149 brdysts::Pipe1Brdy,
5150 Brdysts_SPEC,
5151 crate::common::RW,
5152 >::from_register(self, 0)
5153 }
5154
5155 #[doc = "BRDY Interrupt Status for Pipe 2"]
5156 #[inline(always)]
5157 pub fn pipe2brdy(
5158 self,
5159 ) -> crate::common::RegisterField<
5160 2,
5161 0x1,
5162 1,
5163 0,
5164 brdysts::Pipe2Brdy,
5165 brdysts::Pipe2Brdy,
5166 Brdysts_SPEC,
5167 crate::common::RW,
5168 > {
5169 crate::common::RegisterField::<
5170 2,
5171 0x1,
5172 1,
5173 0,
5174 brdysts::Pipe2Brdy,
5175 brdysts::Pipe2Brdy,
5176 Brdysts_SPEC,
5177 crate::common::RW,
5178 >::from_register(self, 0)
5179 }
5180
5181 #[doc = "BRDY Interrupt Status for Pipe 3"]
5182 #[inline(always)]
5183 pub fn pipe3brdy(
5184 self,
5185 ) -> crate::common::RegisterField<
5186 3,
5187 0x1,
5188 1,
5189 0,
5190 brdysts::Pipe3Brdy,
5191 brdysts::Pipe3Brdy,
5192 Brdysts_SPEC,
5193 crate::common::RW,
5194 > {
5195 crate::common::RegisterField::<
5196 3,
5197 0x1,
5198 1,
5199 0,
5200 brdysts::Pipe3Brdy,
5201 brdysts::Pipe3Brdy,
5202 Brdysts_SPEC,
5203 crate::common::RW,
5204 >::from_register(self, 0)
5205 }
5206
5207 #[doc = "BRDY Interrupt Status for Pipe 4"]
5208 #[inline(always)]
5209 pub fn pipe4brdy(
5210 self,
5211 ) -> crate::common::RegisterField<
5212 4,
5213 0x1,
5214 1,
5215 0,
5216 brdysts::Pipe4Brdy,
5217 brdysts::Pipe4Brdy,
5218 Brdysts_SPEC,
5219 crate::common::RW,
5220 > {
5221 crate::common::RegisterField::<
5222 4,
5223 0x1,
5224 1,
5225 0,
5226 brdysts::Pipe4Brdy,
5227 brdysts::Pipe4Brdy,
5228 Brdysts_SPEC,
5229 crate::common::RW,
5230 >::from_register(self, 0)
5231 }
5232
5233 #[doc = "BRDY Interrupt Status for Pipe 5"]
5234 #[inline(always)]
5235 pub fn pipe5brdy(
5236 self,
5237 ) -> crate::common::RegisterField<
5238 5,
5239 0x1,
5240 1,
5241 0,
5242 brdysts::Pipe5Brdy,
5243 brdysts::Pipe5Brdy,
5244 Brdysts_SPEC,
5245 crate::common::RW,
5246 > {
5247 crate::common::RegisterField::<
5248 5,
5249 0x1,
5250 1,
5251 0,
5252 brdysts::Pipe5Brdy,
5253 brdysts::Pipe5Brdy,
5254 Brdysts_SPEC,
5255 crate::common::RW,
5256 >::from_register(self, 0)
5257 }
5258
5259 #[doc = "BRDY Interrupt Status for Pipe 6"]
5260 #[inline(always)]
5261 pub fn pipe6brdy(
5262 self,
5263 ) -> crate::common::RegisterField<
5264 6,
5265 0x1,
5266 1,
5267 0,
5268 brdysts::Pipe6Brdy,
5269 brdysts::Pipe6Brdy,
5270 Brdysts_SPEC,
5271 crate::common::RW,
5272 > {
5273 crate::common::RegisterField::<
5274 6,
5275 0x1,
5276 1,
5277 0,
5278 brdysts::Pipe6Brdy,
5279 brdysts::Pipe6Brdy,
5280 Brdysts_SPEC,
5281 crate::common::RW,
5282 >::from_register(self, 0)
5283 }
5284
5285 #[doc = "BRDY Interrupt Status for Pipe 7"]
5286 #[inline(always)]
5287 pub fn pipe7brdy(
5288 self,
5289 ) -> crate::common::RegisterField<
5290 7,
5291 0x1,
5292 1,
5293 0,
5294 brdysts::Pipe7Brdy,
5295 brdysts::Pipe7Brdy,
5296 Brdysts_SPEC,
5297 crate::common::RW,
5298 > {
5299 crate::common::RegisterField::<
5300 7,
5301 0x1,
5302 1,
5303 0,
5304 brdysts::Pipe7Brdy,
5305 brdysts::Pipe7Brdy,
5306 Brdysts_SPEC,
5307 crate::common::RW,
5308 >::from_register(self, 0)
5309 }
5310
5311 #[doc = "BRDY Interrupt Status for Pipe 8"]
5312 #[inline(always)]
5313 pub fn pipe8brdy(
5314 self,
5315 ) -> crate::common::RegisterField<
5316 8,
5317 0x1,
5318 1,
5319 0,
5320 brdysts::Pipe8Brdy,
5321 brdysts::Pipe8Brdy,
5322 Brdysts_SPEC,
5323 crate::common::RW,
5324 > {
5325 crate::common::RegisterField::<
5326 8,
5327 0x1,
5328 1,
5329 0,
5330 brdysts::Pipe8Brdy,
5331 brdysts::Pipe8Brdy,
5332 Brdysts_SPEC,
5333 crate::common::RW,
5334 >::from_register(self, 0)
5335 }
5336
5337 #[doc = "BRDY Interrupt Status for Pipe 9"]
5338 #[inline(always)]
5339 pub fn pipe9brdy(
5340 self,
5341 ) -> crate::common::RegisterField<
5342 9,
5343 0x1,
5344 1,
5345 0,
5346 brdysts::Pipe9Brdy,
5347 brdysts::Pipe9Brdy,
5348 Brdysts_SPEC,
5349 crate::common::RW,
5350 > {
5351 crate::common::RegisterField::<
5352 9,
5353 0x1,
5354 1,
5355 0,
5356 brdysts::Pipe9Brdy,
5357 brdysts::Pipe9Brdy,
5358 Brdysts_SPEC,
5359 crate::common::RW,
5360 >::from_register(self, 0)
5361 }
5362}
5363impl ::core::default::Default for Brdysts {
5364 #[inline(always)]
5365 fn default() -> Brdysts {
5366 <crate::RegValueT<Brdysts_SPEC> as RegisterValue<_>>::new(0)
5367 }
5368}
5369pub mod brdysts {
5370
5371 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5372 pub struct Pipe0Brdy_SPEC;
5373 pub type Pipe0Brdy = crate::EnumBitfieldStruct<u8, Pipe0Brdy_SPEC>;
5374 impl Pipe0Brdy {
5375 #[doc = "No BRDY interrupt occurred"]
5376 pub const _0: Self = Self::new(0);
5377
5378 #[doc = "BRDY interrupt occurred"]
5379 pub const _1: Self = Self::new(1);
5380 }
5381 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5382 pub struct Pipe1Brdy_SPEC;
5383 pub type Pipe1Brdy = crate::EnumBitfieldStruct<u8, Pipe1Brdy_SPEC>;
5384 impl Pipe1Brdy {
5385 #[doc = "No BRDY interrupt occurred"]
5386 pub const _0: Self = Self::new(0);
5387
5388 #[doc = "BRDY interrupt occurred"]
5389 pub const _1: Self = Self::new(1);
5390 }
5391 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5392 pub struct Pipe2Brdy_SPEC;
5393 pub type Pipe2Brdy = crate::EnumBitfieldStruct<u8, Pipe2Brdy_SPEC>;
5394 impl Pipe2Brdy {
5395 #[doc = "No BRDY interrupt occurred"]
5396 pub const _0: Self = Self::new(0);
5397
5398 #[doc = "BRDY interrupt occurred"]
5399 pub const _1: Self = Self::new(1);
5400 }
5401 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5402 pub struct Pipe3Brdy_SPEC;
5403 pub type Pipe3Brdy = crate::EnumBitfieldStruct<u8, Pipe3Brdy_SPEC>;
5404 impl Pipe3Brdy {
5405 #[doc = "No BRDY interrupt occurred"]
5406 pub const _0: Self = Self::new(0);
5407
5408 #[doc = "BRDY interrupt occurred"]
5409 pub const _1: Self = Self::new(1);
5410 }
5411 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5412 pub struct Pipe4Brdy_SPEC;
5413 pub type Pipe4Brdy = crate::EnumBitfieldStruct<u8, Pipe4Brdy_SPEC>;
5414 impl Pipe4Brdy {
5415 #[doc = "No BRDY interrupt occurred"]
5416 pub const _0: Self = Self::new(0);
5417
5418 #[doc = "BRDY interrupt occurred"]
5419 pub const _1: Self = Self::new(1);
5420 }
5421 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5422 pub struct Pipe5Brdy_SPEC;
5423 pub type Pipe5Brdy = crate::EnumBitfieldStruct<u8, Pipe5Brdy_SPEC>;
5424 impl Pipe5Brdy {
5425 #[doc = "No BRDY interrupt occurred"]
5426 pub const _0: Self = Self::new(0);
5427
5428 #[doc = "BRDY interrupt occurred"]
5429 pub const _1: Self = Self::new(1);
5430 }
5431 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5432 pub struct Pipe6Brdy_SPEC;
5433 pub type Pipe6Brdy = crate::EnumBitfieldStruct<u8, Pipe6Brdy_SPEC>;
5434 impl Pipe6Brdy {
5435 #[doc = "No BRDY interrupt occurred"]
5436 pub const _0: Self = Self::new(0);
5437
5438 #[doc = "BRDY interrupt occurred"]
5439 pub const _1: Self = Self::new(1);
5440 }
5441 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5442 pub struct Pipe7Brdy_SPEC;
5443 pub type Pipe7Brdy = crate::EnumBitfieldStruct<u8, Pipe7Brdy_SPEC>;
5444 impl Pipe7Brdy {
5445 #[doc = "No BRDY interrupt occurred"]
5446 pub const _0: Self = Self::new(0);
5447
5448 #[doc = "BRDY interrupt occurred"]
5449 pub const _1: Self = Self::new(1);
5450 }
5451 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5452 pub struct Pipe8Brdy_SPEC;
5453 pub type Pipe8Brdy = crate::EnumBitfieldStruct<u8, Pipe8Brdy_SPEC>;
5454 impl Pipe8Brdy {
5455 #[doc = "No BRDY interrupt occurred"]
5456 pub const _0: Self = Self::new(0);
5457
5458 #[doc = "BRDY interrupt occurred"]
5459 pub const _1: Self = Self::new(1);
5460 }
5461 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5462 pub struct Pipe9Brdy_SPEC;
5463 pub type Pipe9Brdy = crate::EnumBitfieldStruct<u8, Pipe9Brdy_SPEC>;
5464 impl Pipe9Brdy {
5465 #[doc = "No BRDY interrupt occurred"]
5466 pub const _0: Self = Self::new(0);
5467
5468 #[doc = "BRDY interrupt occurred"]
5469 pub const _1: Self = Self::new(1);
5470 }
5471}
5472#[doc(hidden)]
5473#[derive(Copy, Clone, Eq, PartialEq)]
5474pub struct Nrdysts_SPEC;
5475impl crate::sealed::RegSpec for Nrdysts_SPEC {
5476 type DataType = u16;
5477}
5478
5479#[doc = "NRDY Interrupt Status Register"]
5480pub type Nrdysts = crate::RegValueT<Nrdysts_SPEC>;
5481
5482impl Nrdysts {
5483 #[doc = "NRDY Interrupt Status for Pipe 0"]
5484 #[inline(always)]
5485 pub fn pipe0nrdy(
5486 self,
5487 ) -> crate::common::RegisterField<
5488 0,
5489 0x1,
5490 1,
5491 0,
5492 nrdysts::Pipe0Nrdy,
5493 nrdysts::Pipe0Nrdy,
5494 Nrdysts_SPEC,
5495 crate::common::RW,
5496 > {
5497 crate::common::RegisterField::<
5498 0,
5499 0x1,
5500 1,
5501 0,
5502 nrdysts::Pipe0Nrdy,
5503 nrdysts::Pipe0Nrdy,
5504 Nrdysts_SPEC,
5505 crate::common::RW,
5506 >::from_register(self, 0)
5507 }
5508
5509 #[doc = "NRDY Interrupt Status for Pipe 1"]
5510 #[inline(always)]
5511 pub fn pipe1nrdy(
5512 self,
5513 ) -> crate::common::RegisterField<
5514 1,
5515 0x1,
5516 1,
5517 0,
5518 nrdysts::Pipe1Nrdy,
5519 nrdysts::Pipe1Nrdy,
5520 Nrdysts_SPEC,
5521 crate::common::RW,
5522 > {
5523 crate::common::RegisterField::<
5524 1,
5525 0x1,
5526 1,
5527 0,
5528 nrdysts::Pipe1Nrdy,
5529 nrdysts::Pipe1Nrdy,
5530 Nrdysts_SPEC,
5531 crate::common::RW,
5532 >::from_register(self, 0)
5533 }
5534
5535 #[doc = "NRDY Interrupt Status for Pipe 2"]
5536 #[inline(always)]
5537 pub fn pipe2nrdy(
5538 self,
5539 ) -> crate::common::RegisterField<
5540 2,
5541 0x1,
5542 1,
5543 0,
5544 nrdysts::Pipe2Nrdy,
5545 nrdysts::Pipe2Nrdy,
5546 Nrdysts_SPEC,
5547 crate::common::RW,
5548 > {
5549 crate::common::RegisterField::<
5550 2,
5551 0x1,
5552 1,
5553 0,
5554 nrdysts::Pipe2Nrdy,
5555 nrdysts::Pipe2Nrdy,
5556 Nrdysts_SPEC,
5557 crate::common::RW,
5558 >::from_register(self, 0)
5559 }
5560
5561 #[doc = "NRDY Interrupt Status for Pipe 3"]
5562 #[inline(always)]
5563 pub fn pipe3nrdy(
5564 self,
5565 ) -> crate::common::RegisterField<
5566 3,
5567 0x1,
5568 1,
5569 0,
5570 nrdysts::Pipe3Nrdy,
5571 nrdysts::Pipe3Nrdy,
5572 Nrdysts_SPEC,
5573 crate::common::RW,
5574 > {
5575 crate::common::RegisterField::<
5576 3,
5577 0x1,
5578 1,
5579 0,
5580 nrdysts::Pipe3Nrdy,
5581 nrdysts::Pipe3Nrdy,
5582 Nrdysts_SPEC,
5583 crate::common::RW,
5584 >::from_register(self, 0)
5585 }
5586
5587 #[doc = "NRDY Interrupt Status for Pipe 4"]
5588 #[inline(always)]
5589 pub fn pipe4nrdy(
5590 self,
5591 ) -> crate::common::RegisterField<
5592 4,
5593 0x1,
5594 1,
5595 0,
5596 nrdysts::Pipe4Nrdy,
5597 nrdysts::Pipe4Nrdy,
5598 Nrdysts_SPEC,
5599 crate::common::RW,
5600 > {
5601 crate::common::RegisterField::<
5602 4,
5603 0x1,
5604 1,
5605 0,
5606 nrdysts::Pipe4Nrdy,
5607 nrdysts::Pipe4Nrdy,
5608 Nrdysts_SPEC,
5609 crate::common::RW,
5610 >::from_register(self, 0)
5611 }
5612
5613 #[doc = "NRDY Interrupt Status for Pipe 5"]
5614 #[inline(always)]
5615 pub fn pipe5nrdy(
5616 self,
5617 ) -> crate::common::RegisterField<
5618 5,
5619 0x1,
5620 1,
5621 0,
5622 nrdysts::Pipe5Nrdy,
5623 nrdysts::Pipe5Nrdy,
5624 Nrdysts_SPEC,
5625 crate::common::RW,
5626 > {
5627 crate::common::RegisterField::<
5628 5,
5629 0x1,
5630 1,
5631 0,
5632 nrdysts::Pipe5Nrdy,
5633 nrdysts::Pipe5Nrdy,
5634 Nrdysts_SPEC,
5635 crate::common::RW,
5636 >::from_register(self, 0)
5637 }
5638
5639 #[doc = "NRDY Interrupt Status for Pipe 6"]
5640 #[inline(always)]
5641 pub fn pipe6nrdy(
5642 self,
5643 ) -> crate::common::RegisterField<
5644 6,
5645 0x1,
5646 1,
5647 0,
5648 nrdysts::Pipe6Nrdy,
5649 nrdysts::Pipe6Nrdy,
5650 Nrdysts_SPEC,
5651 crate::common::RW,
5652 > {
5653 crate::common::RegisterField::<
5654 6,
5655 0x1,
5656 1,
5657 0,
5658 nrdysts::Pipe6Nrdy,
5659 nrdysts::Pipe6Nrdy,
5660 Nrdysts_SPEC,
5661 crate::common::RW,
5662 >::from_register(self, 0)
5663 }
5664
5665 #[doc = "NRDY Interrupt Status for Pipe 7"]
5666 #[inline(always)]
5667 pub fn pipe7nrdy(
5668 self,
5669 ) -> crate::common::RegisterField<
5670 7,
5671 0x1,
5672 1,
5673 0,
5674 nrdysts::Pipe7Nrdy,
5675 nrdysts::Pipe7Nrdy,
5676 Nrdysts_SPEC,
5677 crate::common::RW,
5678 > {
5679 crate::common::RegisterField::<
5680 7,
5681 0x1,
5682 1,
5683 0,
5684 nrdysts::Pipe7Nrdy,
5685 nrdysts::Pipe7Nrdy,
5686 Nrdysts_SPEC,
5687 crate::common::RW,
5688 >::from_register(self, 0)
5689 }
5690
5691 #[doc = "NRDY Interrupt Status for Pipe 8"]
5692 #[inline(always)]
5693 pub fn pipe8nrdy(
5694 self,
5695 ) -> crate::common::RegisterField<
5696 8,
5697 0x1,
5698 1,
5699 0,
5700 nrdysts::Pipe8Nrdy,
5701 nrdysts::Pipe8Nrdy,
5702 Nrdysts_SPEC,
5703 crate::common::RW,
5704 > {
5705 crate::common::RegisterField::<
5706 8,
5707 0x1,
5708 1,
5709 0,
5710 nrdysts::Pipe8Nrdy,
5711 nrdysts::Pipe8Nrdy,
5712 Nrdysts_SPEC,
5713 crate::common::RW,
5714 >::from_register(self, 0)
5715 }
5716
5717 #[doc = "NRDY Interrupt Status for Pipe 9"]
5718 #[inline(always)]
5719 pub fn pipe9nrdy(
5720 self,
5721 ) -> crate::common::RegisterField<
5722 9,
5723 0x1,
5724 1,
5725 0,
5726 nrdysts::Pipe9Nrdy,
5727 nrdysts::Pipe9Nrdy,
5728 Nrdysts_SPEC,
5729 crate::common::RW,
5730 > {
5731 crate::common::RegisterField::<
5732 9,
5733 0x1,
5734 1,
5735 0,
5736 nrdysts::Pipe9Nrdy,
5737 nrdysts::Pipe9Nrdy,
5738 Nrdysts_SPEC,
5739 crate::common::RW,
5740 >::from_register(self, 0)
5741 }
5742}
5743impl ::core::default::Default for Nrdysts {
5744 #[inline(always)]
5745 fn default() -> Nrdysts {
5746 <crate::RegValueT<Nrdysts_SPEC> as RegisterValue<_>>::new(0)
5747 }
5748}
5749pub mod nrdysts {
5750
5751 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5752 pub struct Pipe0Nrdy_SPEC;
5753 pub type Pipe0Nrdy = crate::EnumBitfieldStruct<u8, Pipe0Nrdy_SPEC>;
5754 impl Pipe0Nrdy {
5755 #[doc = "No NRDY interrupt occurred"]
5756 pub const _0: Self = Self::new(0);
5757
5758 #[doc = "NRDY interrupt occurred"]
5759 pub const _1: Self = Self::new(1);
5760 }
5761 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5762 pub struct Pipe1Nrdy_SPEC;
5763 pub type Pipe1Nrdy = crate::EnumBitfieldStruct<u8, Pipe1Nrdy_SPEC>;
5764 impl Pipe1Nrdy {
5765 #[doc = "No NRDY interrupt occurred"]
5766 pub const _0: Self = Self::new(0);
5767
5768 #[doc = "NRDY interrupt occurred"]
5769 pub const _1: Self = Self::new(1);
5770 }
5771 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5772 pub struct Pipe2Nrdy_SPEC;
5773 pub type Pipe2Nrdy = crate::EnumBitfieldStruct<u8, Pipe2Nrdy_SPEC>;
5774 impl Pipe2Nrdy {
5775 #[doc = "No NRDY interrupt occurred"]
5776 pub const _0: Self = Self::new(0);
5777
5778 #[doc = "NRDY interrupt occurred"]
5779 pub const _1: Self = Self::new(1);
5780 }
5781 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5782 pub struct Pipe3Nrdy_SPEC;
5783 pub type Pipe3Nrdy = crate::EnumBitfieldStruct<u8, Pipe3Nrdy_SPEC>;
5784 impl Pipe3Nrdy {
5785 #[doc = "No NRDY interrupt occurred"]
5786 pub const _0: Self = Self::new(0);
5787
5788 #[doc = "NRDY interrupt occurred"]
5789 pub const _1: Self = Self::new(1);
5790 }
5791 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5792 pub struct Pipe4Nrdy_SPEC;
5793 pub type Pipe4Nrdy = crate::EnumBitfieldStruct<u8, Pipe4Nrdy_SPEC>;
5794 impl Pipe4Nrdy {
5795 #[doc = "No NRDY interrupt occurred"]
5796 pub const _0: Self = Self::new(0);
5797
5798 #[doc = "NRDY interrupt occurred"]
5799 pub const _1: Self = Self::new(1);
5800 }
5801 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5802 pub struct Pipe5Nrdy_SPEC;
5803 pub type Pipe5Nrdy = crate::EnumBitfieldStruct<u8, Pipe5Nrdy_SPEC>;
5804 impl Pipe5Nrdy {
5805 #[doc = "No NRDY interrupt occurred"]
5806 pub const _0: Self = Self::new(0);
5807
5808 #[doc = "NRDY interrupt occurred"]
5809 pub const _1: Self = Self::new(1);
5810 }
5811 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5812 pub struct Pipe6Nrdy_SPEC;
5813 pub type Pipe6Nrdy = crate::EnumBitfieldStruct<u8, Pipe6Nrdy_SPEC>;
5814 impl Pipe6Nrdy {
5815 #[doc = "No NRDY interrupt occurred"]
5816 pub const _0: Self = Self::new(0);
5817
5818 #[doc = "NRDY interrupt occurred"]
5819 pub const _1: Self = Self::new(1);
5820 }
5821 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5822 pub struct Pipe7Nrdy_SPEC;
5823 pub type Pipe7Nrdy = crate::EnumBitfieldStruct<u8, Pipe7Nrdy_SPEC>;
5824 impl Pipe7Nrdy {
5825 #[doc = "No NRDY interrupt occurred"]
5826 pub const _0: Self = Self::new(0);
5827
5828 #[doc = "NRDY interrupt occurred"]
5829 pub const _1: Self = Self::new(1);
5830 }
5831 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5832 pub struct Pipe8Nrdy_SPEC;
5833 pub type Pipe8Nrdy = crate::EnumBitfieldStruct<u8, Pipe8Nrdy_SPEC>;
5834 impl Pipe8Nrdy {
5835 #[doc = "No NRDY interrupt occurred"]
5836 pub const _0: Self = Self::new(0);
5837
5838 #[doc = "NRDY interrupt occurred"]
5839 pub const _1: Self = Self::new(1);
5840 }
5841 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5842 pub struct Pipe9Nrdy_SPEC;
5843 pub type Pipe9Nrdy = crate::EnumBitfieldStruct<u8, Pipe9Nrdy_SPEC>;
5844 impl Pipe9Nrdy {
5845 #[doc = "No NRDY interrupt occurred"]
5846 pub const _0: Self = Self::new(0);
5847
5848 #[doc = "NRDY interrupt occurred"]
5849 pub const _1: Self = Self::new(1);
5850 }
5851}
5852#[doc(hidden)]
5853#[derive(Copy, Clone, Eq, PartialEq)]
5854pub struct Bempsts_SPEC;
5855impl crate::sealed::RegSpec for Bempsts_SPEC {
5856 type DataType = u16;
5857}
5858
5859#[doc = "BEMP Interrupt Status Register"]
5860pub type Bempsts = crate::RegValueT<Bempsts_SPEC>;
5861
5862impl Bempsts {
5863 #[doc = "BEMP Interrupt Status for Pipe 0"]
5864 #[inline(always)]
5865 pub fn pipe0bemp(
5866 self,
5867 ) -> crate::common::RegisterField<
5868 0,
5869 0x1,
5870 1,
5871 0,
5872 bempsts::Pipe0Bemp,
5873 bempsts::Pipe0Bemp,
5874 Bempsts_SPEC,
5875 crate::common::RW,
5876 > {
5877 crate::common::RegisterField::<
5878 0,
5879 0x1,
5880 1,
5881 0,
5882 bempsts::Pipe0Bemp,
5883 bempsts::Pipe0Bemp,
5884 Bempsts_SPEC,
5885 crate::common::RW,
5886 >::from_register(self, 0)
5887 }
5888
5889 #[doc = "BEMP Interrupt Status for Pipe 1"]
5890 #[inline(always)]
5891 pub fn pipe1bemp(
5892 self,
5893 ) -> crate::common::RegisterField<
5894 1,
5895 0x1,
5896 1,
5897 0,
5898 bempsts::Pipe1Bemp,
5899 bempsts::Pipe1Bemp,
5900 Bempsts_SPEC,
5901 crate::common::RW,
5902 > {
5903 crate::common::RegisterField::<
5904 1,
5905 0x1,
5906 1,
5907 0,
5908 bempsts::Pipe1Bemp,
5909 bempsts::Pipe1Bemp,
5910 Bempsts_SPEC,
5911 crate::common::RW,
5912 >::from_register(self, 0)
5913 }
5914
5915 #[doc = "BEMP Interrupt Status for Pipe 2"]
5916 #[inline(always)]
5917 pub fn pipe2bemp(
5918 self,
5919 ) -> crate::common::RegisterField<
5920 2,
5921 0x1,
5922 1,
5923 0,
5924 bempsts::Pipe2Bemp,
5925 bempsts::Pipe2Bemp,
5926 Bempsts_SPEC,
5927 crate::common::RW,
5928 > {
5929 crate::common::RegisterField::<
5930 2,
5931 0x1,
5932 1,
5933 0,
5934 bempsts::Pipe2Bemp,
5935 bempsts::Pipe2Bemp,
5936 Bempsts_SPEC,
5937 crate::common::RW,
5938 >::from_register(self, 0)
5939 }
5940
5941 #[doc = "BEMP Interrupt Status for Pipe 3"]
5942 #[inline(always)]
5943 pub fn pipe3bemp(
5944 self,
5945 ) -> crate::common::RegisterField<
5946 3,
5947 0x1,
5948 1,
5949 0,
5950 bempsts::Pipe3Bemp,
5951 bempsts::Pipe3Bemp,
5952 Bempsts_SPEC,
5953 crate::common::RW,
5954 > {
5955 crate::common::RegisterField::<
5956 3,
5957 0x1,
5958 1,
5959 0,
5960 bempsts::Pipe3Bemp,
5961 bempsts::Pipe3Bemp,
5962 Bempsts_SPEC,
5963 crate::common::RW,
5964 >::from_register(self, 0)
5965 }
5966
5967 #[doc = "BEMP Interrupt Status for Pipe 4"]
5968 #[inline(always)]
5969 pub fn pipe4bemp(
5970 self,
5971 ) -> crate::common::RegisterField<
5972 4,
5973 0x1,
5974 1,
5975 0,
5976 bempsts::Pipe4Bemp,
5977 bempsts::Pipe4Bemp,
5978 Bempsts_SPEC,
5979 crate::common::RW,
5980 > {
5981 crate::common::RegisterField::<
5982 4,
5983 0x1,
5984 1,
5985 0,
5986 bempsts::Pipe4Bemp,
5987 bempsts::Pipe4Bemp,
5988 Bempsts_SPEC,
5989 crate::common::RW,
5990 >::from_register(self, 0)
5991 }
5992
5993 #[doc = "BEMP Interrupt Status for Pipe 5"]
5994 #[inline(always)]
5995 pub fn pipe5bemp(
5996 self,
5997 ) -> crate::common::RegisterField<
5998 5,
5999 0x1,
6000 1,
6001 0,
6002 bempsts::Pipe5Bemp,
6003 bempsts::Pipe5Bemp,
6004 Bempsts_SPEC,
6005 crate::common::RW,
6006 > {
6007 crate::common::RegisterField::<
6008 5,
6009 0x1,
6010 1,
6011 0,
6012 bempsts::Pipe5Bemp,
6013 bempsts::Pipe5Bemp,
6014 Bempsts_SPEC,
6015 crate::common::RW,
6016 >::from_register(self, 0)
6017 }
6018
6019 #[doc = "BEMP Interrupt Status for Pipe 6"]
6020 #[inline(always)]
6021 pub fn pipe6bemp(
6022 self,
6023 ) -> crate::common::RegisterField<
6024 6,
6025 0x1,
6026 1,
6027 0,
6028 bempsts::Pipe6Bemp,
6029 bempsts::Pipe6Bemp,
6030 Bempsts_SPEC,
6031 crate::common::RW,
6032 > {
6033 crate::common::RegisterField::<
6034 6,
6035 0x1,
6036 1,
6037 0,
6038 bempsts::Pipe6Bemp,
6039 bempsts::Pipe6Bemp,
6040 Bempsts_SPEC,
6041 crate::common::RW,
6042 >::from_register(self, 0)
6043 }
6044
6045 #[doc = "BEMP Interrupt Status for Pipe 7"]
6046 #[inline(always)]
6047 pub fn pipe7bemp(
6048 self,
6049 ) -> crate::common::RegisterField<
6050 7,
6051 0x1,
6052 1,
6053 0,
6054 bempsts::Pipe7Bemp,
6055 bempsts::Pipe7Bemp,
6056 Bempsts_SPEC,
6057 crate::common::RW,
6058 > {
6059 crate::common::RegisterField::<
6060 7,
6061 0x1,
6062 1,
6063 0,
6064 bempsts::Pipe7Bemp,
6065 bempsts::Pipe7Bemp,
6066 Bempsts_SPEC,
6067 crate::common::RW,
6068 >::from_register(self, 0)
6069 }
6070
6071 #[doc = "BEMP Interrupt Status for Pipe 8"]
6072 #[inline(always)]
6073 pub fn pipe8bemp(
6074 self,
6075 ) -> crate::common::RegisterField<
6076 8,
6077 0x1,
6078 1,
6079 0,
6080 bempsts::Pipe8Bemp,
6081 bempsts::Pipe8Bemp,
6082 Bempsts_SPEC,
6083 crate::common::RW,
6084 > {
6085 crate::common::RegisterField::<
6086 8,
6087 0x1,
6088 1,
6089 0,
6090 bempsts::Pipe8Bemp,
6091 bempsts::Pipe8Bemp,
6092 Bempsts_SPEC,
6093 crate::common::RW,
6094 >::from_register(self, 0)
6095 }
6096
6097 #[doc = "BEMP Interrupt Status for Pipe 9"]
6098 #[inline(always)]
6099 pub fn pipe9bemp(
6100 self,
6101 ) -> crate::common::RegisterField<
6102 9,
6103 0x1,
6104 1,
6105 0,
6106 bempsts::Pipe9Bemp,
6107 bempsts::Pipe9Bemp,
6108 Bempsts_SPEC,
6109 crate::common::RW,
6110 > {
6111 crate::common::RegisterField::<
6112 9,
6113 0x1,
6114 1,
6115 0,
6116 bempsts::Pipe9Bemp,
6117 bempsts::Pipe9Bemp,
6118 Bempsts_SPEC,
6119 crate::common::RW,
6120 >::from_register(self, 0)
6121 }
6122}
6123impl ::core::default::Default for Bempsts {
6124 #[inline(always)]
6125 fn default() -> Bempsts {
6126 <crate::RegValueT<Bempsts_SPEC> as RegisterValue<_>>::new(0)
6127 }
6128}
6129pub mod bempsts {
6130
6131 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6132 pub struct Pipe0Bemp_SPEC;
6133 pub type Pipe0Bemp = crate::EnumBitfieldStruct<u8, Pipe0Bemp_SPEC>;
6134 impl Pipe0Bemp {
6135 #[doc = "No BEMP interrupt occurred"]
6136 pub const _0: Self = Self::new(0);
6137
6138 #[doc = "BEMP interrupt occurred"]
6139 pub const _1: Self = Self::new(1);
6140 }
6141 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6142 pub struct Pipe1Bemp_SPEC;
6143 pub type Pipe1Bemp = crate::EnumBitfieldStruct<u8, Pipe1Bemp_SPEC>;
6144 impl Pipe1Bemp {
6145 #[doc = "No BEMP interrupt occurred"]
6146 pub const _0: Self = Self::new(0);
6147
6148 #[doc = "BEMP interrupt occurred"]
6149 pub const _1: Self = Self::new(1);
6150 }
6151 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6152 pub struct Pipe2Bemp_SPEC;
6153 pub type Pipe2Bemp = crate::EnumBitfieldStruct<u8, Pipe2Bemp_SPEC>;
6154 impl Pipe2Bemp {
6155 #[doc = "No BEMP interrupt occurred"]
6156 pub const _0: Self = Self::new(0);
6157
6158 #[doc = "BEMP interrupt occurred"]
6159 pub const _1: Self = Self::new(1);
6160 }
6161 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6162 pub struct Pipe3Bemp_SPEC;
6163 pub type Pipe3Bemp = crate::EnumBitfieldStruct<u8, Pipe3Bemp_SPEC>;
6164 impl Pipe3Bemp {
6165 #[doc = "No BEMP interrupt occurred"]
6166 pub const _0: Self = Self::new(0);
6167
6168 #[doc = "BEMP interrupt occurred"]
6169 pub const _1: Self = Self::new(1);
6170 }
6171 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6172 pub struct Pipe4Bemp_SPEC;
6173 pub type Pipe4Bemp = crate::EnumBitfieldStruct<u8, Pipe4Bemp_SPEC>;
6174 impl Pipe4Bemp {
6175 #[doc = "No BEMP interrupt occurred"]
6176 pub const _0: Self = Self::new(0);
6177
6178 #[doc = "BEMP interrupt occurred"]
6179 pub const _1: Self = Self::new(1);
6180 }
6181 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6182 pub struct Pipe5Bemp_SPEC;
6183 pub type Pipe5Bemp = crate::EnumBitfieldStruct<u8, Pipe5Bemp_SPEC>;
6184 impl Pipe5Bemp {
6185 #[doc = "No BEMP interrupt occurred"]
6186 pub const _0: Self = Self::new(0);
6187
6188 #[doc = "BEMP interrupt occurred"]
6189 pub const _1: Self = Self::new(1);
6190 }
6191 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6192 pub struct Pipe6Bemp_SPEC;
6193 pub type Pipe6Bemp = crate::EnumBitfieldStruct<u8, Pipe6Bemp_SPEC>;
6194 impl Pipe6Bemp {
6195 #[doc = "No BEMP interrupt occurred"]
6196 pub const _0: Self = Self::new(0);
6197
6198 #[doc = "BEMP interrupt occurred"]
6199 pub const _1: Self = Self::new(1);
6200 }
6201 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6202 pub struct Pipe7Bemp_SPEC;
6203 pub type Pipe7Bemp = crate::EnumBitfieldStruct<u8, Pipe7Bemp_SPEC>;
6204 impl Pipe7Bemp {
6205 #[doc = "No BEMP interrupt occurred"]
6206 pub const _0: Self = Self::new(0);
6207
6208 #[doc = "BEMP interrupt occurred"]
6209 pub const _1: Self = Self::new(1);
6210 }
6211 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6212 pub struct Pipe8Bemp_SPEC;
6213 pub type Pipe8Bemp = crate::EnumBitfieldStruct<u8, Pipe8Bemp_SPEC>;
6214 impl Pipe8Bemp {
6215 #[doc = "No BEMP interrupt occurred"]
6216 pub const _0: Self = Self::new(0);
6217
6218 #[doc = "BEMP interrupt occurred"]
6219 pub const _1: Self = Self::new(1);
6220 }
6221 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6222 pub struct Pipe9Bemp_SPEC;
6223 pub type Pipe9Bemp = crate::EnumBitfieldStruct<u8, Pipe9Bemp_SPEC>;
6224 impl Pipe9Bemp {
6225 #[doc = "No BEMP interrupt occurred"]
6226 pub const _0: Self = Self::new(0);
6227
6228 #[doc = "BEMP interrupt occurred"]
6229 pub const _1: Self = Self::new(1);
6230 }
6231}
6232#[doc(hidden)]
6233#[derive(Copy, Clone, Eq, PartialEq)]
6234pub struct Frmnum_SPEC;
6235impl crate::sealed::RegSpec for Frmnum_SPEC {
6236 type DataType = u16;
6237}
6238
6239#[doc = "Frame Number Register"]
6240pub type Frmnum = crate::RegValueT<Frmnum_SPEC>;
6241
6242impl Frmnum {
6243 #[doc = "Frame Number"]
6244 #[inline(always)]
6245 pub fn frnm(
6246 self,
6247 ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Frmnum_SPEC, crate::common::R> {
6248 crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Frmnum_SPEC,crate::common::R>::from_register(self,0)
6249 }
6250
6251 #[doc = "Receive Data Error"]
6252 #[inline(always)]
6253 pub fn crce(
6254 self,
6255 ) -> crate::common::RegisterField<
6256 14,
6257 0x1,
6258 1,
6259 0,
6260 frmnum::Crce,
6261 frmnum::Crce,
6262 Frmnum_SPEC,
6263 crate::common::RW,
6264 > {
6265 crate::common::RegisterField::<
6266 14,
6267 0x1,
6268 1,
6269 0,
6270 frmnum::Crce,
6271 frmnum::Crce,
6272 Frmnum_SPEC,
6273 crate::common::RW,
6274 >::from_register(self, 0)
6275 }
6276
6277 #[doc = "Overrun/Underrun Detection Status"]
6278 #[inline(always)]
6279 pub fn ovrn(
6280 self,
6281 ) -> crate::common::RegisterField<
6282 15,
6283 0x1,
6284 1,
6285 0,
6286 frmnum::Ovrn,
6287 frmnum::Ovrn,
6288 Frmnum_SPEC,
6289 crate::common::RW,
6290 > {
6291 crate::common::RegisterField::<
6292 15,
6293 0x1,
6294 1,
6295 0,
6296 frmnum::Ovrn,
6297 frmnum::Ovrn,
6298 Frmnum_SPEC,
6299 crate::common::RW,
6300 >::from_register(self, 0)
6301 }
6302}
6303impl ::core::default::Default for Frmnum {
6304 #[inline(always)]
6305 fn default() -> Frmnum {
6306 <crate::RegValueT<Frmnum_SPEC> as RegisterValue<_>>::new(0)
6307 }
6308}
6309pub mod frmnum {
6310
6311 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6312 pub struct Crce_SPEC;
6313 pub type Crce = crate::EnumBitfieldStruct<u8, Crce_SPEC>;
6314 impl Crce {
6315 #[doc = "No error occurred"]
6316 pub const _0: Self = Self::new(0);
6317
6318 #[doc = "Error occurred"]
6319 pub const _1: Self = Self::new(1);
6320 }
6321 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6322 pub struct Ovrn_SPEC;
6323 pub type Ovrn = crate::EnumBitfieldStruct<u8, Ovrn_SPEC>;
6324 impl Ovrn {
6325 #[doc = "No error occurred"]
6326 pub const _0: Self = Self::new(0);
6327
6328 #[doc = "Error occurred"]
6329 pub const _1: Self = Self::new(1);
6330 }
6331}
6332#[doc(hidden)]
6333#[derive(Copy, Clone, Eq, PartialEq)]
6334pub struct Dvchgr_SPEC;
6335impl crate::sealed::RegSpec for Dvchgr_SPEC {
6336 type DataType = u16;
6337}
6338
6339#[doc = "Device State Change Register"]
6340pub type Dvchgr = crate::RegValueT<Dvchgr_SPEC>;
6341
6342impl Dvchgr {
6343 #[doc = "Device State Change"]
6344 #[inline(always)]
6345 pub fn dvchg(
6346 self,
6347 ) -> crate::common::RegisterField<
6348 15,
6349 0x1,
6350 1,
6351 0,
6352 dvchgr::Dvchg,
6353 dvchgr::Dvchg,
6354 Dvchgr_SPEC,
6355 crate::common::RW,
6356 > {
6357 crate::common::RegisterField::<
6358 15,
6359 0x1,
6360 1,
6361 0,
6362 dvchgr::Dvchg,
6363 dvchgr::Dvchg,
6364 Dvchgr_SPEC,
6365 crate::common::RW,
6366 >::from_register(self, 0)
6367 }
6368}
6369impl ::core::default::Default for Dvchgr {
6370 #[inline(always)]
6371 fn default() -> Dvchgr {
6372 <crate::RegValueT<Dvchgr_SPEC> as RegisterValue<_>>::new(0)
6373 }
6374}
6375pub mod dvchgr {
6376
6377 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6378 pub struct Dvchg_SPEC;
6379 pub type Dvchg = crate::EnumBitfieldStruct<u8, Dvchg_SPEC>;
6380 impl Dvchg {
6381 #[doc = "Disable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
6382 pub const _0: Self = Self::new(0);
6383
6384 #[doc = "Enable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
6385 pub const _1: Self = Self::new(1);
6386 }
6387}
6388#[doc(hidden)]
6389#[derive(Copy, Clone, Eq, PartialEq)]
6390pub struct Usbaddr_SPEC;
6391impl crate::sealed::RegSpec for Usbaddr_SPEC {
6392 type DataType = u16;
6393}
6394
6395#[doc = "USB Address Register"]
6396pub type Usbaddr = crate::RegValueT<Usbaddr_SPEC>;
6397
6398impl Usbaddr {
6399 #[doc = "USB Address"]
6400 #[inline(always)]
6401 pub fn usbaddr(
6402 self,
6403 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Usbaddr_SPEC, crate::common::RW> {
6404 crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Usbaddr_SPEC,crate::common::RW>::from_register(self,0)
6405 }
6406
6407 #[doc = "Status Recovery"]
6408 #[inline(always)]
6409 pub fn stsrecov(
6410 self,
6411 ) -> crate::common::RegisterField<
6412 8,
6413 0xf,
6414 1,
6415 0,
6416 usbaddr::Stsrecov,
6417 usbaddr::Stsrecov,
6418 Usbaddr_SPEC,
6419 crate::common::RW,
6420 > {
6421 crate::common::RegisterField::<
6422 8,
6423 0xf,
6424 1,
6425 0,
6426 usbaddr::Stsrecov,
6427 usbaddr::Stsrecov,
6428 Usbaddr_SPEC,
6429 crate::common::RW,
6430 >::from_register(self, 0)
6431 }
6432}
6433impl ::core::default::Default for Usbaddr {
6434 #[inline(always)]
6435 fn default() -> Usbaddr {
6436 <crate::RegValueT<Usbaddr_SPEC> as RegisterValue<_>>::new(0)
6437 }
6438}
6439pub mod usbaddr {
6440
6441 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6442 pub struct Stsrecov_SPEC;
6443 pub type Stsrecov = crate::EnumBitfieldStruct<u8, Stsrecov_SPEC>;
6444 impl Stsrecov {
6445 #[doc = "Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the low-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 001b)"]
6446 pub const _0_X_4: Self = Self::new(4);
6447
6448 #[doc = "Recovery in device controller mode: Setting prohibited Recovery in host controller mode: Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b)"]
6449 pub const _0_X_8: Self = Self::new(8);
6450
6451 #[doc = "Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 001b (default state) Recovery in host controller mode: Setting prohibited"]
6452 pub const _0_X_9: Self = Self::new(9);
6453
6454 #[doc = "Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 010b (address state) Recovery in host controller mode: Setting prohibited"]
6455 pub const _0_X_A: Self = Self::new(10);
6456
6457 #[doc = "Recovery in device controller mode: Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 011b (configured state) Recovery in host controller mode: Setting prohibited"]
6458 pub const _0_X_B: Self = Self::new(11);
6459 }
6460}
6461#[doc(hidden)]
6462#[derive(Copy, Clone, Eq, PartialEq)]
6463pub struct Usbreq_SPEC;
6464impl crate::sealed::RegSpec for Usbreq_SPEC {
6465 type DataType = u16;
6466}
6467
6468#[doc = "USB Request Type Register"]
6469pub type Usbreq = crate::RegValueT<Usbreq_SPEC>;
6470
6471impl Usbreq {
6472 #[doc = "Request Type"]
6473 #[inline(always)]
6474 pub fn bmrequesttype(
6475 self,
6476 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::RW> {
6477 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::RW>::from_register(self,0)
6478 }
6479
6480 #[doc = "Request"]
6481 #[inline(always)]
6482 pub fn brequest(
6483 self,
6484 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::RW> {
6485 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::RW>::from_register(self,0)
6486 }
6487}
6488impl ::core::default::Default for Usbreq {
6489 #[inline(always)]
6490 fn default() -> Usbreq {
6491 <crate::RegValueT<Usbreq_SPEC> as RegisterValue<_>>::new(0)
6492 }
6493}
6494
6495#[doc(hidden)]
6496#[derive(Copy, Clone, Eq, PartialEq)]
6497pub struct Usbval_SPEC;
6498impl crate::sealed::RegSpec for Usbval_SPEC {
6499 type DataType = u16;
6500}
6501
6502#[doc = "USB Request Value Register"]
6503pub type Usbval = crate::RegValueT<Usbval_SPEC>;
6504
6505impl Usbval {
6506 #[doc = "Value"]
6507 #[inline(always)]
6508 pub fn wvalue(
6509 self,
6510 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbval_SPEC, crate::common::RW>
6511 {
6512 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbval_SPEC,crate::common::RW>::from_register(self,0)
6513 }
6514}
6515impl ::core::default::Default for Usbval {
6516 #[inline(always)]
6517 fn default() -> Usbval {
6518 <crate::RegValueT<Usbval_SPEC> as RegisterValue<_>>::new(0)
6519 }
6520}
6521
6522#[doc(hidden)]
6523#[derive(Copy, Clone, Eq, PartialEq)]
6524pub struct Usbindx_SPEC;
6525impl crate::sealed::RegSpec for Usbindx_SPEC {
6526 type DataType = u16;
6527}
6528
6529#[doc = "USB Request Index Register"]
6530pub type Usbindx = crate::RegValueT<Usbindx_SPEC>;
6531
6532impl Usbindx {
6533 #[doc = "Index"]
6534 #[inline(always)]
6535 pub fn windex(
6536 self,
6537 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbindx_SPEC, crate::common::RW>
6538 {
6539 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbindx_SPEC,crate::common::RW>::from_register(self,0)
6540 }
6541}
6542impl ::core::default::Default for Usbindx {
6543 #[inline(always)]
6544 fn default() -> Usbindx {
6545 <crate::RegValueT<Usbindx_SPEC> as RegisterValue<_>>::new(0)
6546 }
6547}
6548
6549#[doc(hidden)]
6550#[derive(Copy, Clone, Eq, PartialEq)]
6551pub struct Usbleng_SPEC;
6552impl crate::sealed::RegSpec for Usbleng_SPEC {
6553 type DataType = u16;
6554}
6555
6556#[doc = "USB Request Length Register"]
6557pub type Usbleng = crate::RegValueT<Usbleng_SPEC>;
6558
6559impl Usbleng {
6560 #[doc = "Length"]
6561 #[inline(always)]
6562 pub fn wlentuh(
6563 self,
6564 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbleng_SPEC, crate::common::RW>
6565 {
6566 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbleng_SPEC,crate::common::RW>::from_register(self,0)
6567 }
6568}
6569impl ::core::default::Default for Usbleng {
6570 #[inline(always)]
6571 fn default() -> Usbleng {
6572 <crate::RegValueT<Usbleng_SPEC> as RegisterValue<_>>::new(0)
6573 }
6574}
6575
6576#[doc(hidden)]
6577#[derive(Copy, Clone, Eq, PartialEq)]
6578pub struct Dcpcfg_SPEC;
6579impl crate::sealed::RegSpec for Dcpcfg_SPEC {
6580 type DataType = u16;
6581}
6582
6583#[doc = "DCP Configuration Register"]
6584pub type Dcpcfg = crate::RegValueT<Dcpcfg_SPEC>;
6585
6586impl Dcpcfg {
6587 #[doc = "Transfer Direction"]
6588 #[inline(always)]
6589 pub fn dir(
6590 self,
6591 ) -> crate::common::RegisterField<
6592 4,
6593 0x1,
6594 1,
6595 0,
6596 dcpcfg::Dir,
6597 dcpcfg::Dir,
6598 Dcpcfg_SPEC,
6599 crate::common::RW,
6600 > {
6601 crate::common::RegisterField::<
6602 4,
6603 0x1,
6604 1,
6605 0,
6606 dcpcfg::Dir,
6607 dcpcfg::Dir,
6608 Dcpcfg_SPEC,
6609 crate::common::RW,
6610 >::from_register(self, 0)
6611 }
6612
6613 #[doc = "Pipe Disabled at End of Transfer"]
6614 #[inline(always)]
6615 pub fn shtnak(
6616 self,
6617 ) -> crate::common::RegisterField<
6618 7,
6619 0x1,
6620 1,
6621 0,
6622 dcpcfg::Shtnak,
6623 dcpcfg::Shtnak,
6624 Dcpcfg_SPEC,
6625 crate::common::RW,
6626 > {
6627 crate::common::RegisterField::<
6628 7,
6629 0x1,
6630 1,
6631 0,
6632 dcpcfg::Shtnak,
6633 dcpcfg::Shtnak,
6634 Dcpcfg_SPEC,
6635 crate::common::RW,
6636 >::from_register(self, 0)
6637 }
6638}
6639impl ::core::default::Default for Dcpcfg {
6640 #[inline(always)]
6641 fn default() -> Dcpcfg {
6642 <crate::RegValueT<Dcpcfg_SPEC> as RegisterValue<_>>::new(0)
6643 }
6644}
6645pub mod dcpcfg {
6646
6647 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6648 pub struct Dir_SPEC;
6649 pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
6650 impl Dir {
6651 #[doc = "Data receiving direction"]
6652 pub const _0: Self = Self::new(0);
6653
6654 #[doc = "Data transmitting direction"]
6655 pub const _1: Self = Self::new(1);
6656 }
6657 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6658 pub struct Shtnak_SPEC;
6659 pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
6660 impl Shtnak {
6661 #[doc = "Keep pipe open after transfer ends"]
6662 pub const _0: Self = Self::new(0);
6663
6664 #[doc = "Disable pipe after transfer ends"]
6665 pub const _1: Self = Self::new(1);
6666 }
6667}
6668#[doc(hidden)]
6669#[derive(Copy, Clone, Eq, PartialEq)]
6670pub struct Dcpmaxp_SPEC;
6671impl crate::sealed::RegSpec for Dcpmaxp_SPEC {
6672 type DataType = u16;
6673}
6674
6675#[doc = "DCP Maximum Packet Size Register"]
6676pub type Dcpmaxp = crate::RegValueT<Dcpmaxp_SPEC>;
6677
6678impl Dcpmaxp {
6679 #[doc = "Maximum Packet Size"]
6680 #[inline(always)]
6681 pub fn mxps(
6682 self,
6683 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Dcpmaxp_SPEC, crate::common::RW> {
6684 crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Dcpmaxp_SPEC,crate::common::RW>::from_register(self,0)
6685 }
6686
6687 #[doc = "Device Select"]
6688 #[inline(always)]
6689 pub fn devsel(
6690 self,
6691 ) -> crate::common::RegisterField<
6692 12,
6693 0xf,
6694 1,
6695 0,
6696 dcpmaxp::Devsel,
6697 dcpmaxp::Devsel,
6698 Dcpmaxp_SPEC,
6699 crate::common::RW,
6700 > {
6701 crate::common::RegisterField::<
6702 12,
6703 0xf,
6704 1,
6705 0,
6706 dcpmaxp::Devsel,
6707 dcpmaxp::Devsel,
6708 Dcpmaxp_SPEC,
6709 crate::common::RW,
6710 >::from_register(self, 0)
6711 }
6712}
6713impl ::core::default::Default for Dcpmaxp {
6714 #[inline(always)]
6715 fn default() -> Dcpmaxp {
6716 <crate::RegValueT<Dcpmaxp_SPEC> as RegisterValue<_>>::new(64)
6717 }
6718}
6719pub mod dcpmaxp {
6720
6721 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6722 pub struct Devsel_SPEC;
6723 pub type Devsel = crate::EnumBitfieldStruct<u8, Devsel_SPEC>;
6724 impl Devsel {
6725 #[doc = "Address 0000b"]
6726 pub const _0_X_0: Self = Self::new(0);
6727
6728 #[doc = "Address 0001b"]
6729 pub const _0_X_1: Self = Self::new(1);
6730
6731 #[doc = "Address 0010b"]
6732 pub const _0_X_2: Self = Self::new(2);
6733
6734 #[doc = "Address 0011b"]
6735 pub const _0_X_3: Self = Self::new(3);
6736
6737 #[doc = "Address 0100b"]
6738 pub const _0_X_4: Self = Self::new(4);
6739
6740 #[doc = "Address 0101b"]
6741 pub const _0_X_5: Self = Self::new(5);
6742 }
6743}
6744#[doc(hidden)]
6745#[derive(Copy, Clone, Eq, PartialEq)]
6746pub struct Dcpctr_SPEC;
6747impl crate::sealed::RegSpec for Dcpctr_SPEC {
6748 type DataType = u16;
6749}
6750
6751#[doc = "DCP Control Register"]
6752pub type Dcpctr = crate::RegValueT<Dcpctr_SPEC>;
6753
6754impl Dcpctr {
6755 #[doc = "Response PID"]
6756 #[inline(always)]
6757 pub fn pid(
6758 self,
6759 ) -> crate::common::RegisterField<
6760 0,
6761 0x3,
6762 1,
6763 0,
6764 dcpctr::Pid,
6765 dcpctr::Pid,
6766 Dcpctr_SPEC,
6767 crate::common::RW,
6768 > {
6769 crate::common::RegisterField::<
6770 0,
6771 0x3,
6772 1,
6773 0,
6774 dcpctr::Pid,
6775 dcpctr::Pid,
6776 Dcpctr_SPEC,
6777 crate::common::RW,
6778 >::from_register(self, 0)
6779 }
6780
6781 #[doc = "Control Transfer End Enable"]
6782 #[inline(always)]
6783 pub fn ccpl(
6784 self,
6785 ) -> crate::common::RegisterField<
6786 2,
6787 0x1,
6788 1,
6789 0,
6790 dcpctr::Ccpl,
6791 dcpctr::Ccpl,
6792 Dcpctr_SPEC,
6793 crate::common::RW,
6794 > {
6795 crate::common::RegisterField::<
6796 2,
6797 0x1,
6798 1,
6799 0,
6800 dcpctr::Ccpl,
6801 dcpctr::Ccpl,
6802 Dcpctr_SPEC,
6803 crate::common::RW,
6804 >::from_register(self, 0)
6805 }
6806
6807 #[doc = "Pipe Busy"]
6808 #[inline(always)]
6809 pub fn pbusy(
6810 self,
6811 ) -> crate::common::RegisterField<
6812 5,
6813 0x1,
6814 1,
6815 0,
6816 dcpctr::Pbusy,
6817 dcpctr::Pbusy,
6818 Dcpctr_SPEC,
6819 crate::common::R,
6820 > {
6821 crate::common::RegisterField::<
6822 5,
6823 0x1,
6824 1,
6825 0,
6826 dcpctr::Pbusy,
6827 dcpctr::Pbusy,
6828 Dcpctr_SPEC,
6829 crate::common::R,
6830 >::from_register(self, 0)
6831 }
6832
6833 #[doc = "Sequence Toggle Bit Monitor"]
6834 #[inline(always)]
6835 pub fn sqmon(
6836 self,
6837 ) -> crate::common::RegisterField<
6838 6,
6839 0x1,
6840 1,
6841 0,
6842 dcpctr::Sqmon,
6843 dcpctr::Sqmon,
6844 Dcpctr_SPEC,
6845 crate::common::R,
6846 > {
6847 crate::common::RegisterField::<
6848 6,
6849 0x1,
6850 1,
6851 0,
6852 dcpctr::Sqmon,
6853 dcpctr::Sqmon,
6854 Dcpctr_SPEC,
6855 crate::common::R,
6856 >::from_register(self, 0)
6857 }
6858
6859 #[doc = "Sequence Toggle Bit Set"]
6860 #[inline(always)]
6861 pub fn sqset(
6862 self,
6863 ) -> crate::common::RegisterField<
6864 7,
6865 0x1,
6866 1,
6867 0,
6868 dcpctr::Sqset,
6869 dcpctr::Sqset,
6870 Dcpctr_SPEC,
6871 crate::common::RW,
6872 > {
6873 crate::common::RegisterField::<
6874 7,
6875 0x1,
6876 1,
6877 0,
6878 dcpctr::Sqset,
6879 dcpctr::Sqset,
6880 Dcpctr_SPEC,
6881 crate::common::RW,
6882 >::from_register(self, 0)
6883 }
6884
6885 #[doc = "Sequence Toggle Bit Clear"]
6886 #[inline(always)]
6887 pub fn sqclr(
6888 self,
6889 ) -> crate::common::RegisterField<
6890 8,
6891 0x1,
6892 1,
6893 0,
6894 dcpctr::Sqclr,
6895 dcpctr::Sqclr,
6896 Dcpctr_SPEC,
6897 crate::common::RW,
6898 > {
6899 crate::common::RegisterField::<
6900 8,
6901 0x1,
6902 1,
6903 0,
6904 dcpctr::Sqclr,
6905 dcpctr::Sqclr,
6906 Dcpctr_SPEC,
6907 crate::common::RW,
6908 >::from_register(self, 0)
6909 }
6910
6911 #[doc = "SUREQ Bit Clear"]
6912 #[inline(always)]
6913 pub fn sureqclr(
6914 self,
6915 ) -> crate::common::RegisterField<
6916 11,
6917 0x1,
6918 1,
6919 0,
6920 dcpctr::Sureqclr,
6921 dcpctr::Sureqclr,
6922 Dcpctr_SPEC,
6923 crate::common::RW,
6924 > {
6925 crate::common::RegisterField::<
6926 11,
6927 0x1,
6928 1,
6929 0,
6930 dcpctr::Sureqclr,
6931 dcpctr::Sureqclr,
6932 Dcpctr_SPEC,
6933 crate::common::RW,
6934 >::from_register(self, 0)
6935 }
6936
6937 #[doc = "Setup Token Transmission"]
6938 #[inline(always)]
6939 pub fn sureq(
6940 self,
6941 ) -> crate::common::RegisterField<
6942 14,
6943 0x1,
6944 1,
6945 0,
6946 dcpctr::Sureq,
6947 dcpctr::Sureq,
6948 Dcpctr_SPEC,
6949 crate::common::RW,
6950 > {
6951 crate::common::RegisterField::<
6952 14,
6953 0x1,
6954 1,
6955 0,
6956 dcpctr::Sureq,
6957 dcpctr::Sureq,
6958 Dcpctr_SPEC,
6959 crate::common::RW,
6960 >::from_register(self, 0)
6961 }
6962
6963 #[doc = "Buffer Status"]
6964 #[inline(always)]
6965 pub fn bsts(
6966 self,
6967 ) -> crate::common::RegisterField<
6968 15,
6969 0x1,
6970 1,
6971 0,
6972 dcpctr::Bsts,
6973 dcpctr::Bsts,
6974 Dcpctr_SPEC,
6975 crate::common::R,
6976 > {
6977 crate::common::RegisterField::<
6978 15,
6979 0x1,
6980 1,
6981 0,
6982 dcpctr::Bsts,
6983 dcpctr::Bsts,
6984 Dcpctr_SPEC,
6985 crate::common::R,
6986 >::from_register(self, 0)
6987 }
6988}
6989impl ::core::default::Default for Dcpctr {
6990 #[inline(always)]
6991 fn default() -> Dcpctr {
6992 <crate::RegValueT<Dcpctr_SPEC> as RegisterValue<_>>::new(64)
6993 }
6994}
6995pub mod dcpctr {
6996
6997 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6998 pub struct Pid_SPEC;
6999 pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
7000 impl Pid {
7001 #[doc = "NAK response"]
7002 pub const _00: Self = Self::new(0);
7003
7004 #[doc = "BUF response (depends on the buffer state)"]
7005 pub const _01: Self = Self::new(1);
7006
7007 #[doc = "STALL response"]
7008 pub const _10: Self = Self::new(2);
7009
7010 #[doc = "STALL response"]
7011 pub const _11: Self = Self::new(3);
7012 }
7013 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7014 pub struct Ccpl_SPEC;
7015 pub type Ccpl = crate::EnumBitfieldStruct<u8, Ccpl_SPEC>;
7016 impl Ccpl {
7017 #[doc = "Disable control transfer completion"]
7018 pub const _0: Self = Self::new(0);
7019
7020 #[doc = "Enable control transfer completion"]
7021 pub const _1: Self = Self::new(1);
7022 }
7023 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7024 pub struct Pbusy_SPEC;
7025 pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
7026 impl Pbusy {
7027 #[doc = "DCP not used for the USB bus"]
7028 pub const _0: Self = Self::new(0);
7029
7030 #[doc = "DCP in use for the USB bus"]
7031 pub const _1: Self = Self::new(1);
7032 }
7033 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7034 pub struct Sqmon_SPEC;
7035 pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
7036 impl Sqmon {
7037 #[doc = "DATA0"]
7038 pub const _0: Self = Self::new(0);
7039
7040 #[doc = "ATA1"]
7041 pub const _1: Self = Self::new(1);
7042 }
7043 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7044 pub struct Sqset_SPEC;
7045 pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
7046 impl Sqset {
7047 #[doc = "Invalid (writing 0 has no effect)"]
7048 pub const _0: Self = Self::new(0);
7049
7050 #[doc = "Set the expected value for the next transaction to DATA1"]
7051 pub const _1: Self = Self::new(1);
7052 }
7053 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7054 pub struct Sqclr_SPEC;
7055 pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
7056 impl Sqclr {
7057 #[doc = "Invalid (writing 0 has no effect)"]
7058 pub const _0: Self = Self::new(0);
7059
7060 #[doc = "Clear the expected value for the next transaction to DATA0"]
7061 pub const _1: Self = Self::new(1);
7062 }
7063 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7064 pub struct Sureqclr_SPEC;
7065 pub type Sureqclr = crate::EnumBitfieldStruct<u8, Sureqclr_SPEC>;
7066 impl Sureqclr {
7067 #[doc = "Invalid (writing 0 has no effect)"]
7068 pub const _0: Self = Self::new(0);
7069
7070 #[doc = "Clear SUREQ to 0"]
7071 pub const _1: Self = Self::new(1);
7072 }
7073 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7074 pub struct Sureq_SPEC;
7075 pub type Sureq = crate::EnumBitfieldStruct<u8, Sureq_SPEC>;
7076 impl Sureq {
7077 #[doc = "Invalid (writing 0 has no effect)"]
7078 pub const _0: Self = Self::new(0);
7079
7080 #[doc = "Transmit setup packet"]
7081 pub const _1: Self = Self::new(1);
7082 }
7083 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7084 pub struct Bsts_SPEC;
7085 pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
7086 impl Bsts {
7087 #[doc = "Buffer access disabled"]
7088 pub const _0: Self = Self::new(0);
7089
7090 #[doc = "Buffer access enabled"]
7091 pub const _1: Self = Self::new(1);
7092 }
7093}
7094#[doc(hidden)]
7095#[derive(Copy, Clone, Eq, PartialEq)]
7096pub struct Pipesel_SPEC;
7097impl crate::sealed::RegSpec for Pipesel_SPEC {
7098 type DataType = u16;
7099}
7100
7101#[doc = "Pipe Window Select Register"]
7102pub type Pipesel = crate::RegValueT<Pipesel_SPEC>;
7103
7104impl Pipesel {
7105 #[doc = "Pipe Window Select"]
7106 #[inline(always)]
7107 pub fn pipesel(
7108 self,
7109 ) -> crate::common::RegisterField<
7110 0,
7111 0xf,
7112 1,
7113 0,
7114 pipesel::Pipesel,
7115 pipesel::Pipesel,
7116 Pipesel_SPEC,
7117 crate::common::RW,
7118 > {
7119 crate::common::RegisterField::<
7120 0,
7121 0xf,
7122 1,
7123 0,
7124 pipesel::Pipesel,
7125 pipesel::Pipesel,
7126 Pipesel_SPEC,
7127 crate::common::RW,
7128 >::from_register(self, 0)
7129 }
7130}
7131impl ::core::default::Default for Pipesel {
7132 #[inline(always)]
7133 fn default() -> Pipesel {
7134 <crate::RegValueT<Pipesel_SPEC> as RegisterValue<_>>::new(0)
7135 }
7136}
7137pub mod pipesel {
7138
7139 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7140 pub struct Pipesel_SPEC;
7141 pub type Pipesel = crate::EnumBitfieldStruct<u8, Pipesel_SPEC>;
7142 impl Pipesel {
7143 #[doc = "No pipe selected"]
7144 pub const _0_X_0: Self = Self::new(0);
7145
7146 #[doc = "Pipe 1"]
7147 pub const _0_X_1: Self = Self::new(1);
7148
7149 #[doc = "Pipe 2"]
7150 pub const _0_X_2: Self = Self::new(2);
7151
7152 #[doc = "Pipe 3"]
7153 pub const _0_X_3: Self = Self::new(3);
7154
7155 #[doc = "Pipe 4"]
7156 pub const _0_X_4: Self = Self::new(4);
7157
7158 #[doc = "Pipe 5"]
7159 pub const _0_X_5: Self = Self::new(5);
7160
7161 #[doc = "Pipe 6"]
7162 pub const _0_X_6: Self = Self::new(6);
7163
7164 #[doc = "Pipe 7"]
7165 pub const _0_X_7: Self = Self::new(7);
7166
7167 #[doc = "Pipe 8"]
7168 pub const _0_X_8: Self = Self::new(8);
7169
7170 #[doc = "Pipe 9"]
7171 pub const _0_X_9: Self = Self::new(9);
7172 }
7173}
7174#[doc(hidden)]
7175#[derive(Copy, Clone, Eq, PartialEq)]
7176pub struct Pipecfg_SPEC;
7177impl crate::sealed::RegSpec for Pipecfg_SPEC {
7178 type DataType = u16;
7179}
7180
7181#[doc = "Pipe Configuration Register"]
7182pub type Pipecfg = crate::RegValueT<Pipecfg_SPEC>;
7183
7184impl Pipecfg {
7185 #[doc = "Endpoint Number"]
7186 #[inline(always)]
7187 pub fn epnum(
7188 self,
7189 ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Pipecfg_SPEC, crate::common::RW> {
7190 crate::common::RegisterField::<0,0xf,1,0,u8,u8,Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
7191 }
7192
7193 #[doc = "Transfer Direction"]
7194 #[inline(always)]
7195 pub fn dir(
7196 self,
7197 ) -> crate::common::RegisterField<
7198 4,
7199 0x1,
7200 1,
7201 0,
7202 pipecfg::Dir,
7203 pipecfg::Dir,
7204 Pipecfg_SPEC,
7205 crate::common::RW,
7206 > {
7207 crate::common::RegisterField::<
7208 4,
7209 0x1,
7210 1,
7211 0,
7212 pipecfg::Dir,
7213 pipecfg::Dir,
7214 Pipecfg_SPEC,
7215 crate::common::RW,
7216 >::from_register(self, 0)
7217 }
7218
7219 #[doc = "Pipe Disabled at End of Transfer"]
7220 #[inline(always)]
7221 pub fn shtnak(
7222 self,
7223 ) -> crate::common::RegisterField<
7224 7,
7225 0x1,
7226 1,
7227 0,
7228 pipecfg::Shtnak,
7229 pipecfg::Shtnak,
7230 Pipecfg_SPEC,
7231 crate::common::RW,
7232 > {
7233 crate::common::RegisterField::<
7234 7,
7235 0x1,
7236 1,
7237 0,
7238 pipecfg::Shtnak,
7239 pipecfg::Shtnak,
7240 Pipecfg_SPEC,
7241 crate::common::RW,
7242 >::from_register(self, 0)
7243 }
7244
7245 #[doc = "Double Buffer Mode"]
7246 #[inline(always)]
7247 pub fn dblb(
7248 self,
7249 ) -> crate::common::RegisterField<
7250 9,
7251 0x1,
7252 1,
7253 0,
7254 pipecfg::Dblb,
7255 pipecfg::Dblb,
7256 Pipecfg_SPEC,
7257 crate::common::RW,
7258 > {
7259 crate::common::RegisterField::<
7260 9,
7261 0x1,
7262 1,
7263 0,
7264 pipecfg::Dblb,
7265 pipecfg::Dblb,
7266 Pipecfg_SPEC,
7267 crate::common::RW,
7268 >::from_register(self, 0)
7269 }
7270
7271 #[doc = "BRDY Interrupt Operation Specification"]
7272 #[inline(always)]
7273 pub fn bfre(
7274 self,
7275 ) -> crate::common::RegisterField<
7276 10,
7277 0x1,
7278 1,
7279 0,
7280 pipecfg::Bfre,
7281 pipecfg::Bfre,
7282 Pipecfg_SPEC,
7283 crate::common::RW,
7284 > {
7285 crate::common::RegisterField::<
7286 10,
7287 0x1,
7288 1,
7289 0,
7290 pipecfg::Bfre,
7291 pipecfg::Bfre,
7292 Pipecfg_SPEC,
7293 crate::common::RW,
7294 >::from_register(self, 0)
7295 }
7296
7297 #[doc = "Transfer Type"]
7298 #[inline(always)]
7299 pub fn r#type(
7300 self,
7301 ) -> crate::common::RegisterField<
7302 14,
7303 0x3,
7304 1,
7305 0,
7306 pipecfg::Type,
7307 pipecfg::Type,
7308 Pipecfg_SPEC,
7309 crate::common::RW,
7310 > {
7311 crate::common::RegisterField::<
7312 14,
7313 0x3,
7314 1,
7315 0,
7316 pipecfg::Type,
7317 pipecfg::Type,
7318 Pipecfg_SPEC,
7319 crate::common::RW,
7320 >::from_register(self, 0)
7321 }
7322}
7323impl ::core::default::Default for Pipecfg {
7324 #[inline(always)]
7325 fn default() -> Pipecfg {
7326 <crate::RegValueT<Pipecfg_SPEC> as RegisterValue<_>>::new(0)
7327 }
7328}
7329pub mod pipecfg {
7330
7331 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7332 pub struct Dir_SPEC;
7333 pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
7334 impl Dir {
7335 #[doc = "Receiving direction"]
7336 pub const _0: Self = Self::new(0);
7337
7338 #[doc = "Transmitting direction"]
7339 pub const _1: Self = Self::new(1);
7340 }
7341 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7342 pub struct Shtnak_SPEC;
7343 pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
7344 impl Shtnak {
7345 #[doc = "Continue pipe operation after transfer ends"]
7346 pub const _0: Self = Self::new(0);
7347
7348 #[doc = "Disable pipe after transfer ends"]
7349 pub const _1: Self = Self::new(1);
7350 }
7351 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7352 pub struct Dblb_SPEC;
7353 pub type Dblb = crate::EnumBitfieldStruct<u8, Dblb_SPEC>;
7354 impl Dblb {
7355 #[doc = "Single buffer"]
7356 pub const _0: Self = Self::new(0);
7357
7358 #[doc = "Double buffer"]
7359 pub const _1: Self = Self::new(1);
7360 }
7361 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7362 pub struct Bfre_SPEC;
7363 pub type Bfre = crate::EnumBitfieldStruct<u8, Bfre_SPEC>;
7364 impl Bfre {
7365 #[doc = "Generate BRDY interrupt on transmitting or receiving data"]
7366 pub const _0: Self = Self::new(0);
7367
7368 #[doc = "Generate BRDY interrupt on completion of reading data"]
7369 pub const _1: Self = Self::new(1);
7370 }
7371 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7372 pub struct Type_SPEC;
7373 pub type Type = crate::EnumBitfieldStruct<u8, Type_SPEC>;
7374 impl Type {
7375 #[doc = "Pipe not used"]
7376 pub const _00: Self = Self::new(0);
7377
7378 #[doc = "Pipes 1 and 2: Bulk transfer Pipes 3 to 5: Bulk transfer Pipes 6 to 9: Setting prohibited"]
7379 pub const _01: Self = Self::new(1);
7380
7381 #[doc = "Pipes 1 and 2: Setting prohibited Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Interrupt transfer"]
7382 pub const _10: Self = Self::new(2);
7383
7384 #[doc = "Pipes 1 and 2: Isochronous transfer Pipes 3 to 5: Setting prohibited Pipes 6 to 9: Setting prohibited"]
7385 pub const _11: Self = Self::new(3);
7386 }
7387}
7388#[doc(hidden)]
7389#[derive(Copy, Clone, Eq, PartialEq)]
7390pub struct Pipemaxp_SPEC;
7391impl crate::sealed::RegSpec for Pipemaxp_SPEC {
7392 type DataType = u16;
7393}
7394
7395#[doc = "Pipe Maximum Packet Size Register"]
7396pub type Pipemaxp = crate::RegValueT<Pipemaxp_SPEC>;
7397
7398impl Pipemaxp {
7399 #[doc = "Maximum Packet Size"]
7400 #[inline(always)]
7401 pub fn mxps(
7402 self,
7403 ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Pipemaxp_SPEC, crate::common::RW>
7404 {
7405 crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Pipemaxp_SPEC,crate::common::RW>::from_register(self,0)
7406 }
7407
7408 #[doc = "Device Select"]
7409 #[inline(always)]
7410 pub fn devsel(
7411 self,
7412 ) -> crate::common::RegisterField<
7413 12,
7414 0xf,
7415 1,
7416 0,
7417 pipemaxp::Devsel,
7418 pipemaxp::Devsel,
7419 Pipemaxp_SPEC,
7420 crate::common::RW,
7421 > {
7422 crate::common::RegisterField::<
7423 12,
7424 0xf,
7425 1,
7426 0,
7427 pipemaxp::Devsel,
7428 pipemaxp::Devsel,
7429 Pipemaxp_SPEC,
7430 crate::common::RW,
7431 >::from_register(self, 0)
7432 }
7433}
7434impl ::core::default::Default for Pipemaxp {
7435 #[inline(always)]
7436 fn default() -> Pipemaxp {
7437 <crate::RegValueT<Pipemaxp_SPEC> as RegisterValue<_>>::new(0)
7438 }
7439}
7440pub mod pipemaxp {
7441
7442 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7443 pub struct Devsel_SPEC;
7444 pub type Devsel = crate::EnumBitfieldStruct<u8, Devsel_SPEC>;
7445 impl Devsel {
7446 #[doc = "Address 0000b"]
7447 pub const _0_X_0: Self = Self::new(0);
7448
7449 #[doc = "Address 0001b"]
7450 pub const _0_X_1: Self = Self::new(1);
7451
7452 #[doc = "Address 0010b"]
7453 pub const _0_X_2: Self = Self::new(2);
7454
7455 #[doc = "Address 0011b"]
7456 pub const _0_X_3: Self = Self::new(3);
7457
7458 #[doc = "Address 0100b"]
7459 pub const _0_X_4: Self = Self::new(4);
7460
7461 #[doc = "Address 0101b"]
7462 pub const _0_X_5: Self = Self::new(5);
7463 }
7464}
7465#[doc(hidden)]
7466#[derive(Copy, Clone, Eq, PartialEq)]
7467pub struct Pipeperi_SPEC;
7468impl crate::sealed::RegSpec for Pipeperi_SPEC {
7469 type DataType = u16;
7470}
7471
7472#[doc = "Pipe Cycle Control Register"]
7473pub type Pipeperi = crate::RegValueT<Pipeperi_SPEC>;
7474
7475impl Pipeperi {
7476 #[doc = "Interval Error Detection Interval"]
7477 #[inline(always)]
7478 pub fn iitv(
7479 self,
7480 ) -> crate::common::RegisterField<0, 0x7, 1, 0, u8, u8, Pipeperi_SPEC, crate::common::RW> {
7481 crate::common::RegisterField::<0,0x7,1,0,u8,u8,Pipeperi_SPEC,crate::common::RW>::from_register(self,0)
7482 }
7483
7484 #[doc = "Isochronous IN Buffer Flush"]
7485 #[inline(always)]
7486 pub fn ifis(
7487 self,
7488 ) -> crate::common::RegisterField<
7489 12,
7490 0x1,
7491 1,
7492 0,
7493 pipeperi::Ifis,
7494 pipeperi::Ifis,
7495 Pipeperi_SPEC,
7496 crate::common::RW,
7497 > {
7498 crate::common::RegisterField::<
7499 12,
7500 0x1,
7501 1,
7502 0,
7503 pipeperi::Ifis,
7504 pipeperi::Ifis,
7505 Pipeperi_SPEC,
7506 crate::common::RW,
7507 >::from_register(self, 0)
7508 }
7509}
7510impl ::core::default::Default for Pipeperi {
7511 #[inline(always)]
7512 fn default() -> Pipeperi {
7513 <crate::RegValueT<Pipeperi_SPEC> as RegisterValue<_>>::new(0)
7514 }
7515}
7516pub mod pipeperi {
7517
7518 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7519 pub struct Ifis_SPEC;
7520 pub type Ifis = crate::EnumBitfieldStruct<u8, Ifis_SPEC>;
7521 impl Ifis {
7522 #[doc = "Do not flush buffer"]
7523 pub const _0: Self = Self::new(0);
7524
7525 #[doc = "Flush buffer"]
7526 pub const _1: Self = Self::new(1);
7527 }
7528}
7529#[doc(hidden)]
7530#[derive(Copy, Clone, Eq, PartialEq)]
7531pub struct Pipectr_SPEC;
7532impl crate::sealed::RegSpec for Pipectr_SPEC {
7533 type DataType = u16;
7534}
7535
7536#[doc = "PIPE%s Control Registers"]
7537pub type Pipectr = crate::RegValueT<Pipectr_SPEC>;
7538
7539impl Pipectr {
7540 #[doc = "Response PID"]
7541 #[inline(always)]
7542 pub fn pid(
7543 self,
7544 ) -> crate::common::RegisterField<
7545 0,
7546 0x3,
7547 1,
7548 0,
7549 pipectr::Pid,
7550 pipectr::Pid,
7551 Pipectr_SPEC,
7552 crate::common::RW,
7553 > {
7554 crate::common::RegisterField::<
7555 0,
7556 0x3,
7557 1,
7558 0,
7559 pipectr::Pid,
7560 pipectr::Pid,
7561 Pipectr_SPEC,
7562 crate::common::RW,
7563 >::from_register(self, 0)
7564 }
7565
7566 #[doc = "Pipe Busy"]
7567 #[inline(always)]
7568 pub fn pbusy(
7569 self,
7570 ) -> crate::common::RegisterField<
7571 5,
7572 0x1,
7573 1,
7574 0,
7575 pipectr::Pbusy,
7576 pipectr::Pbusy,
7577 Pipectr_SPEC,
7578 crate::common::R,
7579 > {
7580 crate::common::RegisterField::<
7581 5,
7582 0x1,
7583 1,
7584 0,
7585 pipectr::Pbusy,
7586 pipectr::Pbusy,
7587 Pipectr_SPEC,
7588 crate::common::R,
7589 >::from_register(self, 0)
7590 }
7591
7592 #[doc = "Sequence Toggle Bit Confirmation"]
7593 #[inline(always)]
7594 pub fn sqmon(
7595 self,
7596 ) -> crate::common::RegisterField<
7597 6,
7598 0x1,
7599 1,
7600 0,
7601 pipectr::Sqmon,
7602 pipectr::Sqmon,
7603 Pipectr_SPEC,
7604 crate::common::R,
7605 > {
7606 crate::common::RegisterField::<
7607 6,
7608 0x1,
7609 1,
7610 0,
7611 pipectr::Sqmon,
7612 pipectr::Sqmon,
7613 Pipectr_SPEC,
7614 crate::common::R,
7615 >::from_register(self, 0)
7616 }
7617
7618 #[doc = "Sequence Toggle Bit Set"]
7619 #[inline(always)]
7620 pub fn sqset(
7621 self,
7622 ) -> crate::common::RegisterField<
7623 7,
7624 0x1,
7625 1,
7626 0,
7627 pipectr::Sqset,
7628 pipectr::Sqset,
7629 Pipectr_SPEC,
7630 crate::common::W,
7631 > {
7632 crate::common::RegisterField::<
7633 7,
7634 0x1,
7635 1,
7636 0,
7637 pipectr::Sqset,
7638 pipectr::Sqset,
7639 Pipectr_SPEC,
7640 crate::common::W,
7641 >::from_register(self, 0)
7642 }
7643
7644 #[doc = "Sequence Toggle Bit Clear"]
7645 #[inline(always)]
7646 pub fn sqclr(
7647 self,
7648 ) -> crate::common::RegisterField<
7649 8,
7650 0x1,
7651 1,
7652 0,
7653 pipectr::Sqclr,
7654 pipectr::Sqclr,
7655 Pipectr_SPEC,
7656 crate::common::W,
7657 > {
7658 crate::common::RegisterField::<
7659 8,
7660 0x1,
7661 1,
7662 0,
7663 pipectr::Sqclr,
7664 pipectr::Sqclr,
7665 Pipectr_SPEC,
7666 crate::common::W,
7667 >::from_register(self, 0)
7668 }
7669
7670 #[doc = "Auto Buffer Clear Mode"]
7671 #[inline(always)]
7672 pub fn aclrm(
7673 self,
7674 ) -> crate::common::RegisterField<
7675 9,
7676 0x1,
7677 1,
7678 0,
7679 pipectr::Aclrm,
7680 pipectr::Aclrm,
7681 Pipectr_SPEC,
7682 crate::common::RW,
7683 > {
7684 crate::common::RegisterField::<
7685 9,
7686 0x1,
7687 1,
7688 0,
7689 pipectr::Aclrm,
7690 pipectr::Aclrm,
7691 Pipectr_SPEC,
7692 crate::common::RW,
7693 >::from_register(self, 0)
7694 }
7695
7696 #[doc = "Buffer Status"]
7697 #[inline(always)]
7698 pub fn bsts(
7699 self,
7700 ) -> crate::common::RegisterField<
7701 15,
7702 0x1,
7703 1,
7704 0,
7705 pipectr::Bsts,
7706 pipectr::Bsts,
7707 Pipectr_SPEC,
7708 crate::common::R,
7709 > {
7710 crate::common::RegisterField::<
7711 15,
7712 0x1,
7713 1,
7714 0,
7715 pipectr::Bsts,
7716 pipectr::Bsts,
7717 Pipectr_SPEC,
7718 crate::common::R,
7719 >::from_register(self, 0)
7720 }
7721}
7722impl ::core::default::Default for Pipectr {
7723 #[inline(always)]
7724 fn default() -> Pipectr {
7725 <crate::RegValueT<Pipectr_SPEC> as RegisterValue<_>>::new(0)
7726 }
7727}
7728pub mod pipectr {
7729
7730 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7731 pub struct Pid_SPEC;
7732 pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
7733 impl Pid {
7734 #[doc = "NAK response"]
7735 pub const _00: Self = Self::new(0);
7736
7737 #[doc = "BUF response (depends buffer state)"]
7738 pub const _01: Self = Self::new(1);
7739
7740 #[doc = "STALL response"]
7741 pub const _10: Self = Self::new(2);
7742
7743 #[doc = "STALL response"]
7744 pub const _11: Self = Self::new(3);
7745 }
7746 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7747 pub struct Pbusy_SPEC;
7748 pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
7749 impl Pbusy {
7750 #[doc = "Pipe n not in use for the transaction"]
7751 pub const _0: Self = Self::new(0);
7752
7753 #[doc = "Pipe n in use for the transaction"]
7754 pub const _1: Self = Self::new(1);
7755 }
7756 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7757 pub struct Sqmon_SPEC;
7758 pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
7759 impl Sqmon {
7760 #[doc = "DATA0"]
7761 pub const _0: Self = Self::new(0);
7762
7763 #[doc = "DATA1"]
7764 pub const _1: Self = Self::new(1);
7765 }
7766 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7767 pub struct Sqset_SPEC;
7768 pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
7769 impl Sqset {
7770 #[doc = "Invalid (writing 0 has no effect)"]
7771 pub const _0: Self = Self::new(0);
7772
7773 #[doc = "Set the expected value for the next transaction to DATA0"]
7774 pub const _1: Self = Self::new(1);
7775 }
7776 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7777 pub struct Sqclr_SPEC;
7778 pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
7779 impl Sqclr {
7780 #[doc = "Invalid (writing 0 has no effect)"]
7781 pub const _0: Self = Self::new(0);
7782
7783 #[doc = "Clear the expected value for the next transaction to DATA0"]
7784 pub const _1: Self = Self::new(1);
7785 }
7786 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7787 pub struct Aclrm_SPEC;
7788 pub type Aclrm = crate::EnumBitfieldStruct<u8, Aclrm_SPEC>;
7789 impl Aclrm {
7790 #[doc = "Disable"]
7791 pub const _0: Self = Self::new(0);
7792
7793 #[doc = "Enable (all buffers initialized)"]
7794 pub const _1: Self = Self::new(1);
7795 }
7796 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7797 pub struct Bsts_SPEC;
7798 pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
7799 impl Bsts {
7800 #[doc = "Buffer access disabled"]
7801 pub const _0: Self = Self::new(0);
7802
7803 #[doc = "Buffer access enabled"]
7804 pub const _1: Self = Self::new(1);
7805 }
7806}
7807#[doc(hidden)]
7808#[derive(Copy, Clone, Eq, PartialEq)]
7809pub struct Pipetre_SPEC;
7810impl crate::sealed::RegSpec for Pipetre_SPEC {
7811 type DataType = u16;
7812}
7813
7814#[doc = "PIPE%s Transaction Counter Enable Register"]
7815pub type Pipetre = crate::RegValueT<Pipetre_SPEC>;
7816
7817impl Pipetre {
7818 #[doc = "Transaction Counter Clear"]
7819 #[inline(always)]
7820 pub fn trclr(
7821 self,
7822 ) -> crate::common::RegisterField<
7823 8,
7824 0x1,
7825 1,
7826 0,
7827 pipetre::Trclr,
7828 pipetre::Trclr,
7829 Pipetre_SPEC,
7830 crate::common::RW,
7831 > {
7832 crate::common::RegisterField::<
7833 8,
7834 0x1,
7835 1,
7836 0,
7837 pipetre::Trclr,
7838 pipetre::Trclr,
7839 Pipetre_SPEC,
7840 crate::common::RW,
7841 >::from_register(self, 0)
7842 }
7843
7844 #[doc = "Transaction Counter Enable"]
7845 #[inline(always)]
7846 pub fn trenb(
7847 self,
7848 ) -> crate::common::RegisterField<
7849 9,
7850 0x1,
7851 1,
7852 0,
7853 pipetre::Trenb,
7854 pipetre::Trenb,
7855 Pipetre_SPEC,
7856 crate::common::RW,
7857 > {
7858 crate::common::RegisterField::<
7859 9,
7860 0x1,
7861 1,
7862 0,
7863 pipetre::Trenb,
7864 pipetre::Trenb,
7865 Pipetre_SPEC,
7866 crate::common::RW,
7867 >::from_register(self, 0)
7868 }
7869}
7870impl ::core::default::Default for Pipetre {
7871 #[inline(always)]
7872 fn default() -> Pipetre {
7873 <crate::RegValueT<Pipetre_SPEC> as RegisterValue<_>>::new(0)
7874 }
7875}
7876pub mod pipetre {
7877
7878 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7879 pub struct Trclr_SPEC;
7880 pub type Trclr = crate::EnumBitfieldStruct<u8, Trclr_SPEC>;
7881 impl Trclr {
7882 #[doc = "Invalid (writing 0 has no effect)"]
7883 pub const _0: Self = Self::new(0);
7884
7885 #[doc = "Clear counter value"]
7886 pub const _1: Self = Self::new(1);
7887 }
7888 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7889 pub struct Trenb_SPEC;
7890 pub type Trenb = crate::EnumBitfieldStruct<u8, Trenb_SPEC>;
7891 impl Trenb {
7892 #[doc = "Disable transaction counter"]
7893 pub const _0: Self = Self::new(0);
7894
7895 #[doc = "Enable transaction counter"]
7896 pub const _1: Self = Self::new(1);
7897 }
7898}
7899#[doc(hidden)]
7900#[derive(Copy, Clone, Eq, PartialEq)]
7901pub struct Pipetrn_SPEC;
7902impl crate::sealed::RegSpec for Pipetrn_SPEC {
7903 type DataType = u16;
7904}
7905
7906#[doc = "PIPE%s Transaction Counter Register"]
7907pub type Pipetrn = crate::RegValueT<Pipetrn_SPEC>;
7908
7909impl Pipetrn {
7910 #[doc = "Transaction Counter"]
7911 #[inline(always)]
7912 pub fn trncnt(
7913 self,
7914 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Pipetrn_SPEC, crate::common::RW>
7915 {
7916 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Pipetrn_SPEC,crate::common::RW>::from_register(self,0)
7917 }
7918}
7919impl ::core::default::Default for Pipetrn {
7920 #[inline(always)]
7921 fn default() -> Pipetrn {
7922 <crate::RegValueT<Pipetrn_SPEC> as RegisterValue<_>>::new(0)
7923 }
7924}
7925
7926#[doc(hidden)]
7927#[derive(Copy, Clone, Eq, PartialEq)]
7928pub struct Bcctrl1_SPEC;
7929impl crate::sealed::RegSpec for Bcctrl1_SPEC {
7930 type DataType = u32;
7931}
7932
7933#[doc = "Battery Charging Control Register 1"]
7934pub type Bcctrl1 = crate::RegValueT<Bcctrl1_SPEC>;
7935
7936impl Bcctrl1 {
7937 #[doc = "D- Line Pull-down Control"]
7938 #[inline(always)]
7939 pub fn rpdme(
7940 self,
7941 ) -> crate::common::RegisterField<
7942 0,
7943 0x1,
7944 1,
7945 0,
7946 bcctrl1::Rpdme,
7947 bcctrl1::Rpdme,
7948 Bcctrl1_SPEC,
7949 crate::common::RW,
7950 > {
7951 crate::common::RegisterField::<
7952 0,
7953 0x1,
7954 1,
7955 0,
7956 bcctrl1::Rpdme,
7957 bcctrl1::Rpdme,
7958 Bcctrl1_SPEC,
7959 crate::common::RW,
7960 >::from_register(self, 0)
7961 }
7962
7963 #[doc = "D+ Line IDPSRC Output Control"]
7964 #[inline(always)]
7965 pub fn idpsrce(
7966 self,
7967 ) -> crate::common::RegisterField<
7968 1,
7969 0x1,
7970 1,
7971 0,
7972 bcctrl1::Idpsrce,
7973 bcctrl1::Idpsrce,
7974 Bcctrl1_SPEC,
7975 crate::common::RW,
7976 > {
7977 crate::common::RegisterField::<
7978 1,
7979 0x1,
7980 1,
7981 0,
7982 bcctrl1::Idpsrce,
7983 bcctrl1::Idpsrce,
7984 Bcctrl1_SPEC,
7985 crate::common::RW,
7986 >::from_register(self, 0)
7987 }
7988
7989 #[doc = "D- Line VDMSRC (0.6 V) Output Control"]
7990 #[inline(always)]
7991 pub fn vdmsrce(
7992 self,
7993 ) -> crate::common::RegisterField<
7994 2,
7995 0x1,
7996 1,
7997 0,
7998 bcctrl1::Vdmsrce,
7999 bcctrl1::Vdmsrce,
8000 Bcctrl1_SPEC,
8001 crate::common::RW,
8002 > {
8003 crate::common::RegisterField::<
8004 2,
8005 0x1,
8006 1,
8007 0,
8008 bcctrl1::Vdmsrce,
8009 bcctrl1::Vdmsrce,
8010 Bcctrl1_SPEC,
8011 crate::common::RW,
8012 >::from_register(self, 0)
8013 }
8014
8015 #[doc = "D+ Line VDPSRC (0.6 V) Output Control"]
8016 #[inline(always)]
8017 pub fn vdpsrce(
8018 self,
8019 ) -> crate::common::RegisterField<
8020 3,
8021 0x1,
8022 1,
8023 0,
8024 bcctrl1::Vdpsrce,
8025 bcctrl1::Vdpsrce,
8026 Bcctrl1_SPEC,
8027 crate::common::RW,
8028 > {
8029 crate::common::RegisterField::<
8030 3,
8031 0x1,
8032 1,
8033 0,
8034 bcctrl1::Vdpsrce,
8035 bcctrl1::Vdpsrce,
8036 Bcctrl1_SPEC,
8037 crate::common::RW,
8038 >::from_register(self, 0)
8039 }
8040
8041 #[doc = "D+ Line 0.6\u{a0}V Input Detection Control"]
8042 #[inline(always)]
8043 pub fn pddete(
8044 self,
8045 ) -> crate::common::RegisterField<
8046 4,
8047 0x1,
8048 1,
8049 0,
8050 bcctrl1::Pddete,
8051 bcctrl1::Pddete,
8052 Bcctrl1_SPEC,
8053 crate::common::RW,
8054 > {
8055 crate::common::RegisterField::<
8056 4,
8057 0x1,
8058 1,
8059 0,
8060 bcctrl1::Pddete,
8061 bcctrl1::Pddete,
8062 Bcctrl1_SPEC,
8063 crate::common::RW,
8064 >::from_register(self, 0)
8065 }
8066
8067 #[doc = "D- Line 0.6\u{a0}V Input Detection Control"]
8068 #[inline(always)]
8069 pub fn chgdete(
8070 self,
8071 ) -> crate::common::RegisterField<
8072 5,
8073 0x1,
8074 1,
8075 0,
8076 bcctrl1::Chgdete,
8077 bcctrl1::Chgdete,
8078 Bcctrl1_SPEC,
8079 crate::common::RW,
8080 > {
8081 crate::common::RegisterField::<
8082 5,
8083 0x1,
8084 1,
8085 0,
8086 bcctrl1::Chgdete,
8087 bcctrl1::Chgdete,
8088 Bcctrl1_SPEC,
8089 crate::common::RW,
8090 >::from_register(self, 0)
8091 }
8092
8093 #[doc = "D+ Line 0.6 V Input Detection Status Flag"]
8094 #[inline(always)]
8095 pub fn pddetsts(
8096 self,
8097 ) -> crate::common::RegisterField<
8098 8,
8099 0x1,
8100 1,
8101 0,
8102 bcctrl1::Pddetsts,
8103 bcctrl1::Pddetsts,
8104 Bcctrl1_SPEC,
8105 crate::common::R,
8106 > {
8107 crate::common::RegisterField::<
8108 8,
8109 0x1,
8110 1,
8111 0,
8112 bcctrl1::Pddetsts,
8113 bcctrl1::Pddetsts,
8114 Bcctrl1_SPEC,
8115 crate::common::R,
8116 >::from_register(self, 0)
8117 }
8118
8119 #[doc = "D- Line 0.6 V Input Detection Status Flag"]
8120 #[inline(always)]
8121 pub fn chgdetsts(
8122 self,
8123 ) -> crate::common::RegisterField<
8124 9,
8125 0x1,
8126 1,
8127 0,
8128 bcctrl1::Chgdetsts,
8129 bcctrl1::Chgdetsts,
8130 Bcctrl1_SPEC,
8131 crate::common::R,
8132 > {
8133 crate::common::RegisterField::<
8134 9,
8135 0x1,
8136 1,
8137 0,
8138 bcctrl1::Chgdetsts,
8139 bcctrl1::Chgdetsts,
8140 Bcctrl1_SPEC,
8141 crate::common::R,
8142 >::from_register(self, 0)
8143 }
8144}
8145impl ::core::default::Default for Bcctrl1 {
8146 #[inline(always)]
8147 fn default() -> Bcctrl1 {
8148 <crate::RegValueT<Bcctrl1_SPEC> as RegisterValue<_>>::new(0)
8149 }
8150}
8151pub mod bcctrl1 {
8152
8153 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8154 pub struct Rpdme_SPEC;
8155 pub type Rpdme = crate::EnumBitfieldStruct<u8, Rpdme_SPEC>;
8156 impl Rpdme {
8157 #[doc = "Disable D- Line Pull-down"]
8158 pub const _0: Self = Self::new(0);
8159
8160 #[doc = "Enable D- Line Pull-down"]
8161 pub const _1: Self = Self::new(1);
8162 }
8163 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8164 pub struct Idpsrce_SPEC;
8165 pub type Idpsrce = crate::EnumBitfieldStruct<u8, Idpsrce_SPEC>;
8166 impl Idpsrce {
8167 #[doc = "Stopped"]
8168 pub const _0: Self = Self::new(0);
8169
8170 #[doc = "10 µA output"]
8171 pub const _1: Self = Self::new(1);
8172 }
8173 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8174 pub struct Vdmsrce_SPEC;
8175 pub type Vdmsrce = crate::EnumBitfieldStruct<u8, Vdmsrce_SPEC>;
8176 impl Vdmsrce {
8177 #[doc = "Stopped"]
8178 pub const _0: Self = Self::new(0);
8179
8180 #[doc = "0.6 V output"]
8181 pub const _1: Self = Self::new(1);
8182 }
8183 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8184 pub struct Vdpsrce_SPEC;
8185 pub type Vdpsrce = crate::EnumBitfieldStruct<u8, Vdpsrce_SPEC>;
8186 impl Vdpsrce {
8187 #[doc = "Stopped"]
8188 pub const _0: Self = Self::new(0);
8189
8190 #[doc = "0.6 V output"]
8191 pub const _1: Self = Self::new(1);
8192 }
8193 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8194 pub struct Pddete_SPEC;
8195 pub type Pddete = crate::EnumBitfieldStruct<u8, Pddete_SPEC>;
8196 impl Pddete {
8197 #[doc = "Disable detection"]
8198 pub const _0: Self = Self::new(0);
8199
8200 #[doc = "Enable detection"]
8201 pub const _1: Self = Self::new(1);
8202 }
8203 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8204 pub struct Chgdete_SPEC;
8205 pub type Chgdete = crate::EnumBitfieldStruct<u8, Chgdete_SPEC>;
8206 impl Chgdete {
8207 #[doc = "Disable detection"]
8208 pub const _0: Self = Self::new(0);
8209
8210 #[doc = "Enable detection"]
8211 pub const _1: Self = Self::new(1);
8212 }
8213 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8214 pub struct Pddetsts_SPEC;
8215 pub type Pddetsts = crate::EnumBitfieldStruct<u8, Pddetsts_SPEC>;
8216 impl Pddetsts {
8217 #[doc = "Not detected"]
8218 pub const _0: Self = Self::new(0);
8219
8220 #[doc = "Detected"]
8221 pub const _1: Self = Self::new(1);
8222 }
8223 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8224 pub struct Chgdetsts_SPEC;
8225 pub type Chgdetsts = crate::EnumBitfieldStruct<u8, Chgdetsts_SPEC>;
8226 impl Chgdetsts {
8227 #[doc = "Not detected"]
8228 pub const _0: Self = Self::new(0);
8229
8230 #[doc = "Detected"]
8231 pub const _1: Self = Self::new(1);
8232 }
8233}
8234#[doc(hidden)]
8235#[derive(Copy, Clone, Eq, PartialEq)]
8236pub struct Bcctrl2_SPEC;
8237impl crate::sealed::RegSpec for Bcctrl2_SPEC {
8238 type DataType = u32;
8239}
8240
8241#[doc = "Battery Charging Control Register 2"]
8242pub type Bcctrl2 = crate::RegValueT<Bcctrl2_SPEC>;
8243
8244impl Bcctrl2 {
8245 #[doc = "Dedicated Charging Port (DCP) Mode Control"]
8246 #[inline(always)]
8247 pub fn dcpmode(
8248 self,
8249 ) -> crate::common::RegisterField<
8250 6,
8251 0x1,
8252 1,
8253 0,
8254 bcctrl2::Dcpmode,
8255 bcctrl2::Dcpmode,
8256 Bcctrl2_SPEC,
8257 crate::common::RW,
8258 > {
8259 crate::common::RegisterField::<
8260 6,
8261 0x1,
8262 1,
8263 0,
8264 bcctrl2::Dcpmode,
8265 bcctrl2::Dcpmode,
8266 Bcctrl2_SPEC,
8267 crate::common::RW,
8268 >::from_register(self, 0)
8269 }
8270
8271 #[doc = "Battery Charging Enable"]
8272 #[inline(always)]
8273 pub fn batchge(
8274 self,
8275 ) -> crate::common::RegisterField<
8276 7,
8277 0x1,
8278 1,
8279 0,
8280 bcctrl2::Batchge,
8281 bcctrl2::Batchge,
8282 Bcctrl2_SPEC,
8283 crate::common::RW,
8284 > {
8285 crate::common::RegisterField::<
8286 7,
8287 0x1,
8288 1,
8289 0,
8290 bcctrl2::Batchge,
8291 bcctrl2::Batchge,
8292 Bcctrl2_SPEC,
8293 crate::common::RW,
8294 >::from_register(self, 0)
8295 }
8296
8297 #[doc = "Detect Sensitivity Adjustment"]
8298 #[inline(always)]
8299 pub fn phydet(
8300 self,
8301 ) -> crate::common::RegisterField<12, 0x3, 1, 0, u8, u8, Bcctrl2_SPEC, crate::common::RW> {
8302 crate::common::RegisterField::<12,0x3,1,0,u8,u8,Bcctrl2_SPEC,crate::common::RW>::from_register(self,0)
8303 }
8304}
8305impl ::core::default::Default for Bcctrl2 {
8306 #[inline(always)]
8307 fn default() -> Bcctrl2 {
8308 <crate::RegValueT<Bcctrl2_SPEC> as RegisterValue<_>>::new(8192)
8309 }
8310}
8311pub mod bcctrl2 {
8312
8313 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8314 pub struct Dcpmode_SPEC;
8315 pub type Dcpmode = crate::EnumBitfieldStruct<u8, Dcpmode_SPEC>;
8316 impl Dcpmode {
8317 #[doc = "Disable DCP"]
8318 pub const _0: Self = Self::new(0);
8319
8320 #[doc = "Enable DCP"]
8321 pub const _1: Self = Self::new(1);
8322 }
8323 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8324 pub struct Batchge_SPEC;
8325 pub type Batchge = crate::EnumBitfieldStruct<u8, Batchge_SPEC>;
8326 impl Batchge {
8327 #[doc = "Disable Battery Charging"]
8328 pub const _0: Self = Self::new(0);
8329
8330 #[doc = "Enable Battery Charging"]
8331 pub const _1: Self = Self::new(1);
8332 }
8333}
8334#[doc(hidden)]
8335#[derive(Copy, Clone, Eq, PartialEq)]
8336pub struct Devadd_SPEC;
8337impl crate::sealed::RegSpec for Devadd_SPEC {
8338 type DataType = u16;
8339}
8340
8341#[doc = "Device Address %s Configuration Register"]
8342pub type Devadd = crate::RegValueT<Devadd_SPEC>;
8343
8344impl Devadd {
8345 #[doc = "Transfer Speed of Communication Target Device"]
8346 #[inline(always)]
8347 pub fn usbspd(
8348 self,
8349 ) -> crate::common::RegisterField<
8350 6,
8351 0x3,
8352 1,
8353 0,
8354 devadd::Usbspd,
8355 devadd::Usbspd,
8356 Devadd_SPEC,
8357 crate::common::RW,
8358 > {
8359 crate::common::RegisterField::<
8360 6,
8361 0x3,
8362 1,
8363 0,
8364 devadd::Usbspd,
8365 devadd::Usbspd,
8366 Devadd_SPEC,
8367 crate::common::RW,
8368 >::from_register(self, 0)
8369 }
8370}
8371impl ::core::default::Default for Devadd {
8372 #[inline(always)]
8373 fn default() -> Devadd {
8374 <crate::RegValueT<Devadd_SPEC> as RegisterValue<_>>::new(0)
8375 }
8376}
8377pub mod devadd {
8378
8379 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8380 pub struct Usbspd_SPEC;
8381 pub type Usbspd = crate::EnumBitfieldStruct<u8, Usbspd_SPEC>;
8382 impl Usbspd {
8383 #[doc = "Do not use DEVADDn"]
8384 pub const _00: Self = Self::new(0);
8385
8386 #[doc = "Low-speed"]
8387 pub const _01: Self = Self::new(1);
8388
8389 #[doc = "Full-speed"]
8390 pub const _10: Self = Self::new(2);
8391
8392 #[doc = "Setting prohibited"]
8393 pub const _11: Self = Self::new(3);
8394 }
8395}
8396#[doc(hidden)]
8397#[derive(Copy, Clone, Eq, PartialEq)]
8398pub struct Physectrl_SPEC;
8399impl crate::sealed::RegSpec for Physectrl_SPEC {
8400 type DataType = u32;
8401}
8402
8403#[doc = "PHY Single-ended Receiver Control Register"]
8404pub type Physectrl = crate::RegValueT<Physectrl_SPEC>;
8405
8406impl Physectrl {
8407 #[doc = "Single-ended Receiver Enable"]
8408 #[inline(always)]
8409 pub fn cnen(
8410 self,
8411 ) -> crate::common::RegisterField<
8412 4,
8413 0x1,
8414 1,
8415 0,
8416 physectrl::Cnen,
8417 physectrl::Cnen,
8418 Physectrl_SPEC,
8419 crate::common::RW,
8420 > {
8421 crate::common::RegisterField::<
8422 4,
8423 0x1,
8424 1,
8425 0,
8426 physectrl::Cnen,
8427 physectrl::Cnen,
8428 Physectrl_SPEC,
8429 crate::common::RW,
8430 >::from_register(self, 0)
8431 }
8432}
8433impl ::core::default::Default for Physectrl {
8434 #[inline(always)]
8435 fn default() -> Physectrl {
8436 <crate::RegValueT<Physectrl_SPEC> as RegisterValue<_>>::new(0)
8437 }
8438}
8439pub mod physectrl {
8440
8441 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8442 pub struct Cnen_SPEC;
8443 pub type Cnen = crate::EnumBitfieldStruct<u8, Cnen_SPEC>;
8444 impl Cnen {
8445 #[doc = "Single-ended receiver operation is disabled"]
8446 pub const _0: Self = Self::new(0);
8447
8448 #[doc = "Single-ended receiver operation is enabled"]
8449 pub const _1: Self = Self::new(1);
8450 }
8451}
8452#[doc(hidden)]
8453#[derive(Copy, Clone, Eq, PartialEq)]
8454pub struct Dpusr0R_SPEC;
8455impl crate::sealed::RegSpec for Dpusr0R_SPEC {
8456 type DataType = u32;
8457}
8458
8459#[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
8460pub type Dpusr0R = crate::RegValueT<Dpusr0R_SPEC>;
8461
8462impl Dpusr0R {
8463 #[doc = "USB Single-ended Receiver Control"]
8464 #[inline(always)]
8465 pub fn srpc0(
8466 self,
8467 ) -> crate::common::RegisterField<
8468 0,
8469 0x1,
8470 1,
8471 0,
8472 dpusr0r::Srpc0,
8473 dpusr0r::Srpc0,
8474 Dpusr0R_SPEC,
8475 crate::common::RW,
8476 > {
8477 crate::common::RegisterField::<
8478 0,
8479 0x1,
8480 1,
8481 0,
8482 dpusr0r::Srpc0,
8483 dpusr0r::Srpc0,
8484 Dpusr0R_SPEC,
8485 crate::common::RW,
8486 >::from_register(self, 0)
8487 }
8488
8489 #[doc = "DP Pull-Up Resistor Control"]
8490 #[inline(always)]
8491 pub fn rpue0(
8492 self,
8493 ) -> crate::common::RegisterField<
8494 1,
8495 0x1,
8496 1,
8497 0,
8498 dpusr0r::Rpue0,
8499 dpusr0r::Rpue0,
8500 Dpusr0R_SPEC,
8501 crate::common::RW,
8502 > {
8503 crate::common::RegisterField::<
8504 1,
8505 0x1,
8506 1,
8507 0,
8508 dpusr0r::Rpue0,
8509 dpusr0r::Rpue0,
8510 Dpusr0R_SPEC,
8511 crate::common::RW,
8512 >::from_register(self, 0)
8513 }
8514
8515 #[doc = "D+/D- Pull-Down Resistor Control"]
8516 #[inline(always)]
8517 pub fn drpd0(
8518 self,
8519 ) -> crate::common::RegisterField<
8520 3,
8521 0x1,
8522 1,
8523 0,
8524 dpusr0r::Drpd0,
8525 dpusr0r::Drpd0,
8526 Dpusr0R_SPEC,
8527 crate::common::RW,
8528 > {
8529 crate::common::RegisterField::<
8530 3,
8531 0x1,
8532 1,
8533 0,
8534 dpusr0r::Drpd0,
8535 dpusr0r::Drpd0,
8536 Dpusr0R_SPEC,
8537 crate::common::RW,
8538 >::from_register(self, 0)
8539 }
8540
8541 #[doc = "USB Transceiver Output Fix"]
8542 #[inline(always)]
8543 pub fn fixphy0(
8544 self,
8545 ) -> crate::common::RegisterField<
8546 4,
8547 0x1,
8548 1,
8549 0,
8550 dpusr0r::Fixphy0,
8551 dpusr0r::Fixphy0,
8552 Dpusr0R_SPEC,
8553 crate::common::RW,
8554 > {
8555 crate::common::RegisterField::<
8556 4,
8557 0x1,
8558 1,
8559 0,
8560 dpusr0r::Fixphy0,
8561 dpusr0r::Fixphy0,
8562 Dpusr0R_SPEC,
8563 crate::common::RW,
8564 >::from_register(self, 0)
8565 }
8566
8567 #[doc = "USB D+ Input"]
8568 #[inline(always)]
8569 pub fn dp0(self) -> crate::common::RegisterFieldBool<16, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8570 crate::common::RegisterFieldBool::<16, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8571 self, 0,
8572 )
8573 }
8574
8575 #[doc = "USB D- Input"]
8576 #[inline(always)]
8577 pub fn dm0(self) -> crate::common::RegisterFieldBool<17, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8578 crate::common::RegisterFieldBool::<17, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8579 self, 0,
8580 )
8581 }
8582
8583 #[doc = "USB OVRCURA Input"]
8584 #[inline(always)]
8585 pub fn dovca0(
8586 self,
8587 ) -> crate::common::RegisterFieldBool<20, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8588 crate::common::RegisterFieldBool::<20, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8589 self, 0,
8590 )
8591 }
8592
8593 #[doc = "USB VBUS Input"]
8594 #[inline(always)]
8595 pub fn dvbsts0(
8596 self,
8597 ) -> crate::common::RegisterFieldBool<23, 1, 0, Dpusr0R_SPEC, crate::common::R> {
8598 crate::common::RegisterFieldBool::<23, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
8599 self, 0,
8600 )
8601 }
8602}
8603impl ::core::default::Default for Dpusr0R {
8604 #[inline(always)]
8605 fn default() -> Dpusr0R {
8606 <crate::RegValueT<Dpusr0R_SPEC> as RegisterValue<_>>::new(0)
8607 }
8608}
8609pub mod dpusr0r {
8610
8611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8612 pub struct Srpc0_SPEC;
8613 pub type Srpc0 = crate::EnumBitfieldStruct<u8, Srpc0_SPEC>;
8614 impl Srpc0 {
8615 #[doc = "Disable input through DP and DM inputs"]
8616 pub const _0: Self = Self::new(0);
8617
8618 #[doc = "Enable input through DP and DM inputs"]
8619 pub const _1: Self = Self::new(1);
8620 }
8621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8622 pub struct Rpue0_SPEC;
8623 pub type Rpue0 = crate::EnumBitfieldStruct<u8, Rpue0_SPEC>;
8624 impl Rpue0 {
8625 #[doc = "Disable DP pull-up resistor"]
8626 pub const _0: Self = Self::new(0);
8627
8628 #[doc = "Enable DP pull-up resistor"]
8629 pub const _1: Self = Self::new(1);
8630 }
8631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8632 pub struct Drpd0_SPEC;
8633 pub type Drpd0 = crate::EnumBitfieldStruct<u8, Drpd0_SPEC>;
8634 impl Drpd0 {
8635 #[doc = "Disable DP/DM pull-down resistor"]
8636 pub const _0: Self = Self::new(0);
8637
8638 #[doc = "Enable DP/DM pull-down resistor"]
8639 pub const _1: Self = Self::new(1);
8640 }
8641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8642 pub struct Fixphy0_SPEC;
8643 pub type Fixphy0 = crate::EnumBitfieldStruct<u8, Fixphy0_SPEC>;
8644 impl Fixphy0 {
8645 #[doc = "Fix outputs in Normal mode and on return from Deep Software Standby mode"]
8646 pub const _0: Self = Self::new(0);
8647
8648 #[doc = "Fix outputs on transition to Deep Software Standby mode"]
8649 pub const _1: Self = Self::new(1);
8650 }
8651}
8652#[doc(hidden)]
8653#[derive(Copy, Clone, Eq, PartialEq)]
8654pub struct Dpusr1R_SPEC;
8655impl crate::sealed::RegSpec for Dpusr1R_SPEC {
8656 type DataType = u32;
8657}
8658
8659#[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
8660pub type Dpusr1R = crate::RegValueT<Dpusr1R_SPEC>;
8661
8662impl Dpusr1R {
8663 #[doc = "USB DP Interrupt Enable/Clear"]
8664 #[inline(always)]
8665 pub fn dpinte0(
8666 self,
8667 ) -> crate::common::RegisterField<
8668 0,
8669 0x1,
8670 1,
8671 0,
8672 dpusr1r::Dpinte0,
8673 dpusr1r::Dpinte0,
8674 Dpusr1R_SPEC,
8675 crate::common::RW,
8676 > {
8677 crate::common::RegisterField::<
8678 0,
8679 0x1,
8680 1,
8681 0,
8682 dpusr1r::Dpinte0,
8683 dpusr1r::Dpinte0,
8684 Dpusr1R_SPEC,
8685 crate::common::RW,
8686 >::from_register(self, 0)
8687 }
8688
8689 #[doc = "USB DM Interrupt Enable/Clear"]
8690 #[inline(always)]
8691 pub fn dminte0(
8692 self,
8693 ) -> crate::common::RegisterField<
8694 1,
8695 0x1,
8696 1,
8697 0,
8698 dpusr1r::Dminte0,
8699 dpusr1r::Dminte0,
8700 Dpusr1R_SPEC,
8701 crate::common::RW,
8702 > {
8703 crate::common::RegisterField::<
8704 1,
8705 0x1,
8706 1,
8707 0,
8708 dpusr1r::Dminte0,
8709 dpusr1r::Dminte0,
8710 Dpusr1R_SPEC,
8711 crate::common::RW,
8712 >::from_register(self, 0)
8713 }
8714
8715 #[doc = "USB OVRCURA Interrupt Enable/Clear"]
8716 #[inline(always)]
8717 pub fn dovrcrae0(
8718 self,
8719 ) -> crate::common::RegisterField<
8720 4,
8721 0x1,
8722 1,
8723 0,
8724 dpusr1r::Dovrcrae0,
8725 dpusr1r::Dovrcrae0,
8726 Dpusr1R_SPEC,
8727 crate::common::RW,
8728 > {
8729 crate::common::RegisterField::<
8730 4,
8731 0x1,
8732 1,
8733 0,
8734 dpusr1r::Dovrcrae0,
8735 dpusr1r::Dovrcrae0,
8736 Dpusr1R_SPEC,
8737 crate::common::RW,
8738 >::from_register(self, 0)
8739 }
8740
8741 #[doc = "USB VBUS Interrupt Enable/Clear"]
8742 #[inline(always)]
8743 pub fn dvbse0(
8744 self,
8745 ) -> crate::common::RegisterField<
8746 7,
8747 0x1,
8748 1,
8749 0,
8750 dpusr1r::Dvbse0,
8751 dpusr1r::Dvbse0,
8752 Dpusr1R_SPEC,
8753 crate::common::RW,
8754 > {
8755 crate::common::RegisterField::<
8756 7,
8757 0x1,
8758 1,
8759 0,
8760 dpusr1r::Dvbse0,
8761 dpusr1r::Dvbse0,
8762 Dpusr1R_SPEC,
8763 crate::common::RW,
8764 >::from_register(self, 0)
8765 }
8766
8767 #[doc = "USB DP Interrupt Source Recovery"]
8768 #[inline(always)]
8769 pub fn dpint0(
8770 self,
8771 ) -> crate::common::RegisterField<
8772 16,
8773 0x1,
8774 1,
8775 0,
8776 dpusr1r::Dpint0,
8777 dpusr1r::Dpint0,
8778 Dpusr1R_SPEC,
8779 crate::common::R,
8780 > {
8781 crate::common::RegisterField::<
8782 16,
8783 0x1,
8784 1,
8785 0,
8786 dpusr1r::Dpint0,
8787 dpusr1r::Dpint0,
8788 Dpusr1R_SPEC,
8789 crate::common::R,
8790 >::from_register(self, 0)
8791 }
8792
8793 #[doc = "USB DM Interrupt Source Recovery"]
8794 #[inline(always)]
8795 pub fn dmint0(
8796 self,
8797 ) -> crate::common::RegisterField<
8798 17,
8799 0x1,
8800 1,
8801 0,
8802 dpusr1r::Dmint0,
8803 dpusr1r::Dmint0,
8804 Dpusr1R_SPEC,
8805 crate::common::R,
8806 > {
8807 crate::common::RegisterField::<
8808 17,
8809 0x1,
8810 1,
8811 0,
8812 dpusr1r::Dmint0,
8813 dpusr1r::Dmint0,
8814 Dpusr1R_SPEC,
8815 crate::common::R,
8816 >::from_register(self, 0)
8817 }
8818
8819 #[doc = "USB OVRCURA Interrupt Source Recovery"]
8820 #[inline(always)]
8821 pub fn dovrcra0(
8822 self,
8823 ) -> crate::common::RegisterField<
8824 20,
8825 0x1,
8826 1,
8827 0,
8828 dpusr1r::Dovrcra0,
8829 dpusr1r::Dovrcra0,
8830 Dpusr1R_SPEC,
8831 crate::common::R,
8832 > {
8833 crate::common::RegisterField::<
8834 20,
8835 0x1,
8836 1,
8837 0,
8838 dpusr1r::Dovrcra0,
8839 dpusr1r::Dovrcra0,
8840 Dpusr1R_SPEC,
8841 crate::common::R,
8842 >::from_register(self, 0)
8843 }
8844
8845 #[doc = "USB VBUS Interrupt Source Recovery"]
8846 #[inline(always)]
8847 pub fn dvbint0(
8848 self,
8849 ) -> crate::common::RegisterField<
8850 23,
8851 0x1,
8852 1,
8853 0,
8854 dpusr1r::Dvbint0,
8855 dpusr1r::Dvbint0,
8856 Dpusr1R_SPEC,
8857 crate::common::R,
8858 > {
8859 crate::common::RegisterField::<
8860 23,
8861 0x1,
8862 1,
8863 0,
8864 dpusr1r::Dvbint0,
8865 dpusr1r::Dvbint0,
8866 Dpusr1R_SPEC,
8867 crate::common::R,
8868 >::from_register(self, 0)
8869 }
8870}
8871impl ::core::default::Default for Dpusr1R {
8872 #[inline(always)]
8873 fn default() -> Dpusr1R {
8874 <crate::RegValueT<Dpusr1R_SPEC> as RegisterValue<_>>::new(0)
8875 }
8876}
8877pub mod dpusr1r {
8878
8879 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8880 pub struct Dpinte0_SPEC;
8881 pub type Dpinte0 = crate::EnumBitfieldStruct<u8, Dpinte0_SPEC>;
8882 impl Dpinte0 {
8883 #[doc = "Disable recovery from Deep Software Standby mode by DP input"]
8884 pub const _0: Self = Self::new(0);
8885
8886 #[doc = "Enable recovery from Deep Software Standby mode by DP input"]
8887 pub const _1: Self = Self::new(1);
8888 }
8889 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8890 pub struct Dminte0_SPEC;
8891 pub type Dminte0 = crate::EnumBitfieldStruct<u8, Dminte0_SPEC>;
8892 impl Dminte0 {
8893 #[doc = "Disable recovery from Deep Software Standby mode by DM input"]
8894 pub const _0: Self = Self::new(0);
8895
8896 #[doc = "Enable recovery from Deep Software Standby mode by DM input"]
8897 pub const _1: Self = Self::new(1);
8898 }
8899 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8900 pub struct Dovrcrae0_SPEC;
8901 pub type Dovrcrae0 = crate::EnumBitfieldStruct<u8, Dovrcrae0_SPEC>;
8902 impl Dovrcrae0 {
8903 #[doc = "Disable recovery from Deep Software Standby mode by OVRCURA input"]
8904 pub const _0: Self = Self::new(0);
8905
8906 #[doc = "Enable recovery from Deep Software Standby mode by OVRCURA input"]
8907 pub const _1: Self = Self::new(1);
8908 }
8909 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8910 pub struct Dvbse0_SPEC;
8911 pub type Dvbse0 = crate::EnumBitfieldStruct<u8, Dvbse0_SPEC>;
8912 impl Dvbse0 {
8913 #[doc = "Disable recovery from Deep Software Standby mode by VBUS input"]
8914 pub const _0: Self = Self::new(0);
8915
8916 #[doc = "Enable recovery from Deep Software Standby mode by VBUS input"]
8917 pub const _1: Self = Self::new(1);
8918 }
8919 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8920 pub struct Dpint0_SPEC;
8921 pub type Dpint0 = crate::EnumBitfieldStruct<u8, Dpint0_SPEC>;
8922 impl Dpint0 {
8923 #[doc = "System has not recovered from Deep Software Standby mode"]
8924 pub const _0: Self = Self::new(0);
8925
8926 #[doc = "System recovered from Deep Software Standby mode because of DP"]
8927 pub const _1: Self = Self::new(1);
8928 }
8929 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8930 pub struct Dmint0_SPEC;
8931 pub type Dmint0 = crate::EnumBitfieldStruct<u8, Dmint0_SPEC>;
8932 impl Dmint0 {
8933 #[doc = "System has not recovered from Deep Software Standby mode"]
8934 pub const _0: Self = Self::new(0);
8935
8936 #[doc = "System recovered from Deep Software Standby mode because of DM input"]
8937 pub const _1: Self = Self::new(1);
8938 }
8939 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8940 pub struct Dovrcra0_SPEC;
8941 pub type Dovrcra0 = crate::EnumBitfieldStruct<u8, Dovrcra0_SPEC>;
8942 impl Dovrcra0 {
8943 #[doc = "System has not recovered from Deep Software Standby mode"]
8944 pub const _0: Self = Self::new(0);
8945
8946 #[doc = "System recovered from Deep Software Standby mode because of OVRCURA input"]
8947 pub const _1: Self = Self::new(1);
8948 }
8949 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8950 pub struct Dvbint0_SPEC;
8951 pub type Dvbint0 = crate::EnumBitfieldStruct<u8, Dvbint0_SPEC>;
8952 impl Dvbint0 {
8953 #[doc = "System has not recovered from Deep Software Standby mode"]
8954 pub const _0: Self = Self::new(0);
8955
8956 #[doc = "System recovered from Deep Software Standby mode because of VBUS input"]
8957 pub const _1: Self = Self::new(1);
8958 }
8959}