1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Interrupt Controller"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 16,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114 #[inline(always)]
115 pub const fn irqcr8(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
116 unsafe {
117 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
118 self._svd2pac_as_ptr().add(0x8usize),
119 )
120 }
121 }
122 #[inline(always)]
123 pub const fn irqcr9(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(0x9usize),
127 )
128 }
129 }
130 #[inline(always)]
131 pub const fn irqcr10(
132 &self,
133 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(0xausize),
137 )
138 }
139 }
140 #[inline(always)]
141 pub const fn irqcr11(
142 &self,
143 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(0xbusize),
147 )
148 }
149 }
150 #[inline(always)]
151 pub const fn irqcr12(
152 &self,
153 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
154 unsafe {
155 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
156 self._svd2pac_as_ptr().add(0xcusize),
157 )
158 }
159 }
160 #[inline(always)]
161 pub const fn irqcr13(
162 &self,
163 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(0xdusize),
167 )
168 }
169 }
170 #[inline(always)]
171 pub const fn irqcr14(
172 &self,
173 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
174 unsafe {
175 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
176 self._svd2pac_as_ptr().add(0xeusize),
177 )
178 }
179 }
180 #[inline(always)]
181 pub const fn irqcr15(
182 &self,
183 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
184 unsafe {
185 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
186 self._svd2pac_as_ptr().add(0xfusize),
187 )
188 }
189 }
190
191 #[doc = "NMI Pin Interrupt Control Register"]
192 #[inline(always)]
193 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
194 unsafe {
195 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
196 self._svd2pac_as_ptr().add(256usize),
197 )
198 }
199 }
200
201 #[doc = "Non-Maskable Interrupt Enable Register"]
202 #[inline(always)]
203 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
204 unsafe {
205 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
206 self._svd2pac_as_ptr().add(288usize),
207 )
208 }
209 }
210
211 #[doc = "Non-Maskable Interrupt Status Clear Register"]
212 #[inline(always)]
213 pub const fn nmiclr(
214 &self,
215 ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
216 unsafe {
217 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
218 self._svd2pac_as_ptr().add(304usize),
219 )
220 }
221 }
222
223 #[doc = "Non-Maskable Interrupt Status Register"]
224 #[inline(always)]
225 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
226 unsafe {
227 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
228 self._svd2pac_as_ptr().add(320usize),
229 )
230 }
231 }
232
233 #[doc = "Wake Up Interrupt Enable Register 0"]
234 #[inline(always)]
235 pub const fn wupen0(
236 &self,
237 ) -> &'static crate::common::Reg<self::Wupen0_SPEC, crate::common::RW> {
238 unsafe {
239 crate::common::Reg::<self::Wupen0_SPEC, crate::common::RW>::from_ptr(
240 self._svd2pac_as_ptr().add(416usize),
241 )
242 }
243 }
244
245 #[doc = "Wake Up interrupt enable register 1"]
246 #[inline(always)]
247 pub const fn wupen1(
248 &self,
249 ) -> &'static crate::common::Reg<self::Wupen1_SPEC, crate::common::RW> {
250 unsafe {
251 crate::common::Reg::<self::Wupen1_SPEC, crate::common::RW>::from_ptr(
252 self._svd2pac_as_ptr().add(420usize),
253 )
254 }
255 }
256
257 #[doc = "SYS Event Link Setting Register"]
258 #[inline(always)]
259 pub const fn selsr0(
260 &self,
261 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(512usize),
265 )
266 }
267 }
268
269 #[doc = "DMAC Event Link Setting Register %s"]
270 #[inline(always)]
271 pub const fn delsr(
272 &self,
273 ) -> &'static crate::common::ClusterRegisterArray<
274 crate::common::Reg<self::Delsr_SPEC, crate::common::RW>,
275 8,
276 0x4,
277 > {
278 unsafe {
279 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x280usize))
280 }
281 }
282 #[inline(always)]
283 pub const fn delsr0(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
284 unsafe {
285 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
286 self._svd2pac_as_ptr().add(0x280usize),
287 )
288 }
289 }
290 #[inline(always)]
291 pub const fn delsr1(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
292 unsafe {
293 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
294 self._svd2pac_as_ptr().add(0x284usize),
295 )
296 }
297 }
298 #[inline(always)]
299 pub const fn delsr2(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
300 unsafe {
301 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
302 self._svd2pac_as_ptr().add(0x288usize),
303 )
304 }
305 }
306 #[inline(always)]
307 pub const fn delsr3(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
308 unsafe {
309 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
310 self._svd2pac_as_ptr().add(0x28cusize),
311 )
312 }
313 }
314 #[inline(always)]
315 pub const fn delsr4(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(0x290usize),
319 )
320 }
321 }
322 #[inline(always)]
323 pub const fn delsr5(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
324 unsafe {
325 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
326 self._svd2pac_as_ptr().add(0x294usize),
327 )
328 }
329 }
330 #[inline(always)]
331 pub const fn delsr6(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
332 unsafe {
333 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
334 self._svd2pac_as_ptr().add(0x298usize),
335 )
336 }
337 }
338 #[inline(always)]
339 pub const fn delsr7(&self) -> &'static crate::common::Reg<self::Delsr_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::Delsr_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(0x29cusize),
343 )
344 }
345 }
346
347 #[doc = "ICU Event Link Setting Register %s"]
348 #[inline(always)]
349 pub const fn ielsr(
350 &self,
351 ) -> &'static crate::common::ClusterRegisterArray<
352 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
353 96,
354 0x4,
355 > {
356 unsafe {
357 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x300usize))
358 }
359 }
360 #[inline(always)]
361 pub const fn ielsr0(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
362 unsafe {
363 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
364 self._svd2pac_as_ptr().add(0x300usize),
365 )
366 }
367 }
368 #[inline(always)]
369 pub const fn ielsr1(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
370 unsafe {
371 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
372 self._svd2pac_as_ptr().add(0x304usize),
373 )
374 }
375 }
376 #[inline(always)]
377 pub const fn ielsr2(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
378 unsafe {
379 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
380 self._svd2pac_as_ptr().add(0x308usize),
381 )
382 }
383 }
384 #[inline(always)]
385 pub const fn ielsr3(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(0x30cusize),
389 )
390 }
391 }
392 #[inline(always)]
393 pub const fn ielsr4(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
394 unsafe {
395 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
396 self._svd2pac_as_ptr().add(0x310usize),
397 )
398 }
399 }
400 #[inline(always)]
401 pub const fn ielsr5(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
402 unsafe {
403 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
404 self._svd2pac_as_ptr().add(0x314usize),
405 )
406 }
407 }
408 #[inline(always)]
409 pub const fn ielsr6(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
410 unsafe {
411 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
412 self._svd2pac_as_ptr().add(0x318usize),
413 )
414 }
415 }
416 #[inline(always)]
417 pub const fn ielsr7(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
418 unsafe {
419 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
420 self._svd2pac_as_ptr().add(0x31cusize),
421 )
422 }
423 }
424 #[inline(always)]
425 pub const fn ielsr8(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x320usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn ielsr9(&self) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
434 unsafe {
435 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
436 self._svd2pac_as_ptr().add(0x324usize),
437 )
438 }
439 }
440 #[inline(always)]
441 pub const fn ielsr10(
442 &self,
443 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
444 unsafe {
445 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
446 self._svd2pac_as_ptr().add(0x328usize),
447 )
448 }
449 }
450 #[inline(always)]
451 pub const fn ielsr11(
452 &self,
453 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
454 unsafe {
455 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
456 self._svd2pac_as_ptr().add(0x32cusize),
457 )
458 }
459 }
460 #[inline(always)]
461 pub const fn ielsr12(
462 &self,
463 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
464 unsafe {
465 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
466 self._svd2pac_as_ptr().add(0x330usize),
467 )
468 }
469 }
470 #[inline(always)]
471 pub const fn ielsr13(
472 &self,
473 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
474 unsafe {
475 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
476 self._svd2pac_as_ptr().add(0x334usize),
477 )
478 }
479 }
480 #[inline(always)]
481 pub const fn ielsr14(
482 &self,
483 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
484 unsafe {
485 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
486 self._svd2pac_as_ptr().add(0x338usize),
487 )
488 }
489 }
490 #[inline(always)]
491 pub const fn ielsr15(
492 &self,
493 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
494 unsafe {
495 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
496 self._svd2pac_as_ptr().add(0x33cusize),
497 )
498 }
499 }
500 #[inline(always)]
501 pub const fn ielsr16(
502 &self,
503 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
504 unsafe {
505 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
506 self._svd2pac_as_ptr().add(0x340usize),
507 )
508 }
509 }
510 #[inline(always)]
511 pub const fn ielsr17(
512 &self,
513 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
514 unsafe {
515 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
516 self._svd2pac_as_ptr().add(0x344usize),
517 )
518 }
519 }
520 #[inline(always)]
521 pub const fn ielsr18(
522 &self,
523 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
524 unsafe {
525 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
526 self._svd2pac_as_ptr().add(0x348usize),
527 )
528 }
529 }
530 #[inline(always)]
531 pub const fn ielsr19(
532 &self,
533 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
534 unsafe {
535 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
536 self._svd2pac_as_ptr().add(0x34cusize),
537 )
538 }
539 }
540 #[inline(always)]
541 pub const fn ielsr20(
542 &self,
543 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
544 unsafe {
545 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
546 self._svd2pac_as_ptr().add(0x350usize),
547 )
548 }
549 }
550 #[inline(always)]
551 pub const fn ielsr21(
552 &self,
553 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
554 unsafe {
555 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
556 self._svd2pac_as_ptr().add(0x354usize),
557 )
558 }
559 }
560 #[inline(always)]
561 pub const fn ielsr22(
562 &self,
563 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
564 unsafe {
565 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
566 self._svd2pac_as_ptr().add(0x358usize),
567 )
568 }
569 }
570 #[inline(always)]
571 pub const fn ielsr23(
572 &self,
573 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
574 unsafe {
575 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
576 self._svd2pac_as_ptr().add(0x35cusize),
577 )
578 }
579 }
580 #[inline(always)]
581 pub const fn ielsr24(
582 &self,
583 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
584 unsafe {
585 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
586 self._svd2pac_as_ptr().add(0x360usize),
587 )
588 }
589 }
590 #[inline(always)]
591 pub const fn ielsr25(
592 &self,
593 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
594 unsafe {
595 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
596 self._svd2pac_as_ptr().add(0x364usize),
597 )
598 }
599 }
600 #[inline(always)]
601 pub const fn ielsr26(
602 &self,
603 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
604 unsafe {
605 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
606 self._svd2pac_as_ptr().add(0x368usize),
607 )
608 }
609 }
610 #[inline(always)]
611 pub const fn ielsr27(
612 &self,
613 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
614 unsafe {
615 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
616 self._svd2pac_as_ptr().add(0x36cusize),
617 )
618 }
619 }
620 #[inline(always)]
621 pub const fn ielsr28(
622 &self,
623 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
624 unsafe {
625 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
626 self._svd2pac_as_ptr().add(0x370usize),
627 )
628 }
629 }
630 #[inline(always)]
631 pub const fn ielsr29(
632 &self,
633 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
634 unsafe {
635 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
636 self._svd2pac_as_ptr().add(0x374usize),
637 )
638 }
639 }
640 #[inline(always)]
641 pub const fn ielsr30(
642 &self,
643 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
644 unsafe {
645 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
646 self._svd2pac_as_ptr().add(0x378usize),
647 )
648 }
649 }
650 #[inline(always)]
651 pub const fn ielsr31(
652 &self,
653 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
654 unsafe {
655 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
656 self._svd2pac_as_ptr().add(0x37cusize),
657 )
658 }
659 }
660 #[inline(always)]
661 pub const fn ielsr32(
662 &self,
663 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
664 unsafe {
665 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
666 self._svd2pac_as_ptr().add(0x380usize),
667 )
668 }
669 }
670 #[inline(always)]
671 pub const fn ielsr33(
672 &self,
673 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
674 unsafe {
675 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
676 self._svd2pac_as_ptr().add(0x384usize),
677 )
678 }
679 }
680 #[inline(always)]
681 pub const fn ielsr34(
682 &self,
683 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
684 unsafe {
685 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
686 self._svd2pac_as_ptr().add(0x388usize),
687 )
688 }
689 }
690 #[inline(always)]
691 pub const fn ielsr35(
692 &self,
693 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
694 unsafe {
695 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
696 self._svd2pac_as_ptr().add(0x38cusize),
697 )
698 }
699 }
700 #[inline(always)]
701 pub const fn ielsr36(
702 &self,
703 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
704 unsafe {
705 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
706 self._svd2pac_as_ptr().add(0x390usize),
707 )
708 }
709 }
710 #[inline(always)]
711 pub const fn ielsr37(
712 &self,
713 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
714 unsafe {
715 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
716 self._svd2pac_as_ptr().add(0x394usize),
717 )
718 }
719 }
720 #[inline(always)]
721 pub const fn ielsr38(
722 &self,
723 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
724 unsafe {
725 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
726 self._svd2pac_as_ptr().add(0x398usize),
727 )
728 }
729 }
730 #[inline(always)]
731 pub const fn ielsr39(
732 &self,
733 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
734 unsafe {
735 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
736 self._svd2pac_as_ptr().add(0x39cusize),
737 )
738 }
739 }
740 #[inline(always)]
741 pub const fn ielsr40(
742 &self,
743 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
744 unsafe {
745 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
746 self._svd2pac_as_ptr().add(0x3a0usize),
747 )
748 }
749 }
750 #[inline(always)]
751 pub const fn ielsr41(
752 &self,
753 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
754 unsafe {
755 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
756 self._svd2pac_as_ptr().add(0x3a4usize),
757 )
758 }
759 }
760 #[inline(always)]
761 pub const fn ielsr42(
762 &self,
763 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
764 unsafe {
765 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
766 self._svd2pac_as_ptr().add(0x3a8usize),
767 )
768 }
769 }
770 #[inline(always)]
771 pub const fn ielsr43(
772 &self,
773 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
774 unsafe {
775 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
776 self._svd2pac_as_ptr().add(0x3acusize),
777 )
778 }
779 }
780 #[inline(always)]
781 pub const fn ielsr44(
782 &self,
783 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
784 unsafe {
785 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
786 self._svd2pac_as_ptr().add(0x3b0usize),
787 )
788 }
789 }
790 #[inline(always)]
791 pub const fn ielsr45(
792 &self,
793 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
794 unsafe {
795 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
796 self._svd2pac_as_ptr().add(0x3b4usize),
797 )
798 }
799 }
800 #[inline(always)]
801 pub const fn ielsr46(
802 &self,
803 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
804 unsafe {
805 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
806 self._svd2pac_as_ptr().add(0x3b8usize),
807 )
808 }
809 }
810 #[inline(always)]
811 pub const fn ielsr47(
812 &self,
813 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
814 unsafe {
815 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
816 self._svd2pac_as_ptr().add(0x3bcusize),
817 )
818 }
819 }
820 #[inline(always)]
821 pub const fn ielsr48(
822 &self,
823 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
824 unsafe {
825 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
826 self._svd2pac_as_ptr().add(0x3c0usize),
827 )
828 }
829 }
830 #[inline(always)]
831 pub const fn ielsr49(
832 &self,
833 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
834 unsafe {
835 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
836 self._svd2pac_as_ptr().add(0x3c4usize),
837 )
838 }
839 }
840 #[inline(always)]
841 pub const fn ielsr50(
842 &self,
843 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
844 unsafe {
845 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
846 self._svd2pac_as_ptr().add(0x3c8usize),
847 )
848 }
849 }
850 #[inline(always)]
851 pub const fn ielsr51(
852 &self,
853 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
854 unsafe {
855 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
856 self._svd2pac_as_ptr().add(0x3ccusize),
857 )
858 }
859 }
860 #[inline(always)]
861 pub const fn ielsr52(
862 &self,
863 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
864 unsafe {
865 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
866 self._svd2pac_as_ptr().add(0x3d0usize),
867 )
868 }
869 }
870 #[inline(always)]
871 pub const fn ielsr53(
872 &self,
873 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
874 unsafe {
875 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
876 self._svd2pac_as_ptr().add(0x3d4usize),
877 )
878 }
879 }
880 #[inline(always)]
881 pub const fn ielsr54(
882 &self,
883 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
884 unsafe {
885 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
886 self._svd2pac_as_ptr().add(0x3d8usize),
887 )
888 }
889 }
890 #[inline(always)]
891 pub const fn ielsr55(
892 &self,
893 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
894 unsafe {
895 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
896 self._svd2pac_as_ptr().add(0x3dcusize),
897 )
898 }
899 }
900 #[inline(always)]
901 pub const fn ielsr56(
902 &self,
903 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
904 unsafe {
905 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
906 self._svd2pac_as_ptr().add(0x3e0usize),
907 )
908 }
909 }
910 #[inline(always)]
911 pub const fn ielsr57(
912 &self,
913 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
914 unsafe {
915 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
916 self._svd2pac_as_ptr().add(0x3e4usize),
917 )
918 }
919 }
920 #[inline(always)]
921 pub const fn ielsr58(
922 &self,
923 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
924 unsafe {
925 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
926 self._svd2pac_as_ptr().add(0x3e8usize),
927 )
928 }
929 }
930 #[inline(always)]
931 pub const fn ielsr59(
932 &self,
933 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
934 unsafe {
935 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
936 self._svd2pac_as_ptr().add(0x3ecusize),
937 )
938 }
939 }
940 #[inline(always)]
941 pub const fn ielsr60(
942 &self,
943 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
944 unsafe {
945 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
946 self._svd2pac_as_ptr().add(0x3f0usize),
947 )
948 }
949 }
950 #[inline(always)]
951 pub const fn ielsr61(
952 &self,
953 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
954 unsafe {
955 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
956 self._svd2pac_as_ptr().add(0x3f4usize),
957 )
958 }
959 }
960 #[inline(always)]
961 pub const fn ielsr62(
962 &self,
963 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
964 unsafe {
965 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
966 self._svd2pac_as_ptr().add(0x3f8usize),
967 )
968 }
969 }
970 #[inline(always)]
971 pub const fn ielsr63(
972 &self,
973 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
974 unsafe {
975 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
976 self._svd2pac_as_ptr().add(0x3fcusize),
977 )
978 }
979 }
980 #[inline(always)]
981 pub const fn ielsr64(
982 &self,
983 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
984 unsafe {
985 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
986 self._svd2pac_as_ptr().add(0x400usize),
987 )
988 }
989 }
990 #[inline(always)]
991 pub const fn ielsr65(
992 &self,
993 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
994 unsafe {
995 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
996 self._svd2pac_as_ptr().add(0x404usize),
997 )
998 }
999 }
1000 #[inline(always)]
1001 pub const fn ielsr66(
1002 &self,
1003 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1004 unsafe {
1005 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1006 self._svd2pac_as_ptr().add(0x408usize),
1007 )
1008 }
1009 }
1010 #[inline(always)]
1011 pub const fn ielsr67(
1012 &self,
1013 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1014 unsafe {
1015 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1016 self._svd2pac_as_ptr().add(0x40cusize),
1017 )
1018 }
1019 }
1020 #[inline(always)]
1021 pub const fn ielsr68(
1022 &self,
1023 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1024 unsafe {
1025 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1026 self._svd2pac_as_ptr().add(0x410usize),
1027 )
1028 }
1029 }
1030 #[inline(always)]
1031 pub const fn ielsr69(
1032 &self,
1033 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1034 unsafe {
1035 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1036 self._svd2pac_as_ptr().add(0x414usize),
1037 )
1038 }
1039 }
1040 #[inline(always)]
1041 pub const fn ielsr70(
1042 &self,
1043 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1044 unsafe {
1045 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1046 self._svd2pac_as_ptr().add(0x418usize),
1047 )
1048 }
1049 }
1050 #[inline(always)]
1051 pub const fn ielsr71(
1052 &self,
1053 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1054 unsafe {
1055 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1056 self._svd2pac_as_ptr().add(0x41cusize),
1057 )
1058 }
1059 }
1060 #[inline(always)]
1061 pub const fn ielsr72(
1062 &self,
1063 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1064 unsafe {
1065 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1066 self._svd2pac_as_ptr().add(0x420usize),
1067 )
1068 }
1069 }
1070 #[inline(always)]
1071 pub const fn ielsr73(
1072 &self,
1073 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1074 unsafe {
1075 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1076 self._svd2pac_as_ptr().add(0x424usize),
1077 )
1078 }
1079 }
1080 #[inline(always)]
1081 pub const fn ielsr74(
1082 &self,
1083 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1084 unsafe {
1085 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1086 self._svd2pac_as_ptr().add(0x428usize),
1087 )
1088 }
1089 }
1090 #[inline(always)]
1091 pub const fn ielsr75(
1092 &self,
1093 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1094 unsafe {
1095 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1096 self._svd2pac_as_ptr().add(0x42cusize),
1097 )
1098 }
1099 }
1100 #[inline(always)]
1101 pub const fn ielsr76(
1102 &self,
1103 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1104 unsafe {
1105 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1106 self._svd2pac_as_ptr().add(0x430usize),
1107 )
1108 }
1109 }
1110 #[inline(always)]
1111 pub const fn ielsr77(
1112 &self,
1113 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1114 unsafe {
1115 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1116 self._svd2pac_as_ptr().add(0x434usize),
1117 )
1118 }
1119 }
1120 #[inline(always)]
1121 pub const fn ielsr78(
1122 &self,
1123 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1124 unsafe {
1125 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1126 self._svd2pac_as_ptr().add(0x438usize),
1127 )
1128 }
1129 }
1130 #[inline(always)]
1131 pub const fn ielsr79(
1132 &self,
1133 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1134 unsafe {
1135 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1136 self._svd2pac_as_ptr().add(0x43cusize),
1137 )
1138 }
1139 }
1140 #[inline(always)]
1141 pub const fn ielsr80(
1142 &self,
1143 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1144 unsafe {
1145 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1146 self._svd2pac_as_ptr().add(0x440usize),
1147 )
1148 }
1149 }
1150 #[inline(always)]
1151 pub const fn ielsr81(
1152 &self,
1153 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1154 unsafe {
1155 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1156 self._svd2pac_as_ptr().add(0x444usize),
1157 )
1158 }
1159 }
1160 #[inline(always)]
1161 pub const fn ielsr82(
1162 &self,
1163 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1164 unsafe {
1165 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1166 self._svd2pac_as_ptr().add(0x448usize),
1167 )
1168 }
1169 }
1170 #[inline(always)]
1171 pub const fn ielsr83(
1172 &self,
1173 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1174 unsafe {
1175 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1176 self._svd2pac_as_ptr().add(0x44cusize),
1177 )
1178 }
1179 }
1180 #[inline(always)]
1181 pub const fn ielsr84(
1182 &self,
1183 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1184 unsafe {
1185 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1186 self._svd2pac_as_ptr().add(0x450usize),
1187 )
1188 }
1189 }
1190 #[inline(always)]
1191 pub const fn ielsr85(
1192 &self,
1193 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1194 unsafe {
1195 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1196 self._svd2pac_as_ptr().add(0x454usize),
1197 )
1198 }
1199 }
1200 #[inline(always)]
1201 pub const fn ielsr86(
1202 &self,
1203 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1204 unsafe {
1205 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1206 self._svd2pac_as_ptr().add(0x458usize),
1207 )
1208 }
1209 }
1210 #[inline(always)]
1211 pub const fn ielsr87(
1212 &self,
1213 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1214 unsafe {
1215 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1216 self._svd2pac_as_ptr().add(0x45cusize),
1217 )
1218 }
1219 }
1220 #[inline(always)]
1221 pub const fn ielsr88(
1222 &self,
1223 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1224 unsafe {
1225 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1226 self._svd2pac_as_ptr().add(0x460usize),
1227 )
1228 }
1229 }
1230 #[inline(always)]
1231 pub const fn ielsr89(
1232 &self,
1233 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1234 unsafe {
1235 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1236 self._svd2pac_as_ptr().add(0x464usize),
1237 )
1238 }
1239 }
1240 #[inline(always)]
1241 pub const fn ielsr90(
1242 &self,
1243 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1244 unsafe {
1245 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1246 self._svd2pac_as_ptr().add(0x468usize),
1247 )
1248 }
1249 }
1250 #[inline(always)]
1251 pub const fn ielsr91(
1252 &self,
1253 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1254 unsafe {
1255 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1256 self._svd2pac_as_ptr().add(0x46cusize),
1257 )
1258 }
1259 }
1260 #[inline(always)]
1261 pub const fn ielsr92(
1262 &self,
1263 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1264 unsafe {
1265 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1266 self._svd2pac_as_ptr().add(0x470usize),
1267 )
1268 }
1269 }
1270 #[inline(always)]
1271 pub const fn ielsr93(
1272 &self,
1273 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1274 unsafe {
1275 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1276 self._svd2pac_as_ptr().add(0x474usize),
1277 )
1278 }
1279 }
1280 #[inline(always)]
1281 pub const fn ielsr94(
1282 &self,
1283 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1284 unsafe {
1285 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1286 self._svd2pac_as_ptr().add(0x478usize),
1287 )
1288 }
1289 }
1290 #[inline(always)]
1291 pub const fn ielsr95(
1292 &self,
1293 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
1294 unsafe {
1295 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
1296 self._svd2pac_as_ptr().add(0x47cusize),
1297 )
1298 }
1299 }
1300}
1301#[doc(hidden)]
1302#[derive(Copy, Clone, Eq, PartialEq)]
1303pub struct Irqcr_SPEC;
1304impl crate::sealed::RegSpec for Irqcr_SPEC {
1305 type DataType = u8;
1306}
1307
1308#[doc = "IRQ Control Register %s"]
1309pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
1310
1311impl Irqcr {
1312 #[doc = "IRQi Detection Sense Select"]
1313 #[inline(always)]
1314 pub fn irqmd(
1315 self,
1316 ) -> crate::common::RegisterField<
1317 0,
1318 0x3,
1319 1,
1320 0,
1321 irqcr::Irqmd,
1322 irqcr::Irqmd,
1323 Irqcr_SPEC,
1324 crate::common::RW,
1325 > {
1326 crate::common::RegisterField::<
1327 0,
1328 0x3,
1329 1,
1330 0,
1331 irqcr::Irqmd,
1332 irqcr::Irqmd,
1333 Irqcr_SPEC,
1334 crate::common::RW,
1335 >::from_register(self, 0)
1336 }
1337
1338 #[doc = "IRQi Digital Filter Sampling Clock Select"]
1339 #[inline(always)]
1340 pub fn fclksel(
1341 self,
1342 ) -> crate::common::RegisterField<
1343 4,
1344 0x3,
1345 1,
1346 0,
1347 irqcr::Fclksel,
1348 irqcr::Fclksel,
1349 Irqcr_SPEC,
1350 crate::common::RW,
1351 > {
1352 crate::common::RegisterField::<
1353 4,
1354 0x3,
1355 1,
1356 0,
1357 irqcr::Fclksel,
1358 irqcr::Fclksel,
1359 Irqcr_SPEC,
1360 crate::common::RW,
1361 >::from_register(self, 0)
1362 }
1363
1364 #[doc = "IRQi Digital Filter Enable"]
1365 #[inline(always)]
1366 pub fn flten(
1367 self,
1368 ) -> crate::common::RegisterField<
1369 7,
1370 0x1,
1371 1,
1372 0,
1373 irqcr::Flten,
1374 irqcr::Flten,
1375 Irqcr_SPEC,
1376 crate::common::RW,
1377 > {
1378 crate::common::RegisterField::<
1379 7,
1380 0x1,
1381 1,
1382 0,
1383 irqcr::Flten,
1384 irqcr::Flten,
1385 Irqcr_SPEC,
1386 crate::common::RW,
1387 >::from_register(self, 0)
1388 }
1389}
1390impl ::core::default::Default for Irqcr {
1391 #[inline(always)]
1392 fn default() -> Irqcr {
1393 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
1394 }
1395}
1396pub mod irqcr {
1397
1398 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1399 pub struct Irqmd_SPEC;
1400 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
1401 impl Irqmd {
1402 #[doc = "Falling edge"]
1403 pub const _00: Self = Self::new(0);
1404
1405 #[doc = "Rising edge"]
1406 pub const _01: Self = Self::new(1);
1407
1408 #[doc = "Rising and falling edges"]
1409 pub const _10: Self = Self::new(2);
1410
1411 #[doc = "Low level"]
1412 pub const _11: Self = Self::new(3);
1413 }
1414 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1415 pub struct Fclksel_SPEC;
1416 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
1417 impl Fclksel {
1418 #[doc = "PCLKB"]
1419 pub const _00: Self = Self::new(0);
1420
1421 #[doc = "PCLKB/8"]
1422 pub const _01: Self = Self::new(1);
1423
1424 #[doc = "PCLKB/32"]
1425 pub const _10: Self = Self::new(2);
1426
1427 #[doc = "PCLKB/64"]
1428 pub const _11: Self = Self::new(3);
1429 }
1430 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1431 pub struct Flten_SPEC;
1432 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
1433 impl Flten {
1434 #[doc = "Digital filter is disabled"]
1435 pub const _0: Self = Self::new(0);
1436
1437 #[doc = "Digital filter is enabled."]
1438 pub const _1: Self = Self::new(1);
1439 }
1440}
1441#[doc(hidden)]
1442#[derive(Copy, Clone, Eq, PartialEq)]
1443pub struct Nmicr_SPEC;
1444impl crate::sealed::RegSpec for Nmicr_SPEC {
1445 type DataType = u8;
1446}
1447
1448#[doc = "NMI Pin Interrupt Control Register"]
1449pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
1450
1451impl Nmicr {
1452 #[doc = "NMI Detection Set"]
1453 #[inline(always)]
1454 pub fn nmimd(
1455 self,
1456 ) -> crate::common::RegisterField<
1457 0,
1458 0x1,
1459 1,
1460 0,
1461 nmicr::Nmimd,
1462 nmicr::Nmimd,
1463 Nmicr_SPEC,
1464 crate::common::RW,
1465 > {
1466 crate::common::RegisterField::<
1467 0,
1468 0x1,
1469 1,
1470 0,
1471 nmicr::Nmimd,
1472 nmicr::Nmimd,
1473 Nmicr_SPEC,
1474 crate::common::RW,
1475 >::from_register(self, 0)
1476 }
1477
1478 #[doc = "NMI Digital Filter Sampling Clock Select"]
1479 #[inline(always)]
1480 pub fn nfclksel(
1481 self,
1482 ) -> crate::common::RegisterField<
1483 4,
1484 0x3,
1485 1,
1486 0,
1487 nmicr::Nfclksel,
1488 nmicr::Nfclksel,
1489 Nmicr_SPEC,
1490 crate::common::RW,
1491 > {
1492 crate::common::RegisterField::<
1493 4,
1494 0x3,
1495 1,
1496 0,
1497 nmicr::Nfclksel,
1498 nmicr::Nfclksel,
1499 Nmicr_SPEC,
1500 crate::common::RW,
1501 >::from_register(self, 0)
1502 }
1503
1504 #[doc = "NMI Digital Filter Enable"]
1505 #[inline(always)]
1506 pub fn nflten(
1507 self,
1508 ) -> crate::common::RegisterField<
1509 7,
1510 0x1,
1511 1,
1512 0,
1513 nmicr::Nflten,
1514 nmicr::Nflten,
1515 Nmicr_SPEC,
1516 crate::common::RW,
1517 > {
1518 crate::common::RegisterField::<
1519 7,
1520 0x1,
1521 1,
1522 0,
1523 nmicr::Nflten,
1524 nmicr::Nflten,
1525 Nmicr_SPEC,
1526 crate::common::RW,
1527 >::from_register(self, 0)
1528 }
1529}
1530impl ::core::default::Default for Nmicr {
1531 #[inline(always)]
1532 fn default() -> Nmicr {
1533 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
1534 }
1535}
1536pub mod nmicr {
1537
1538 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1539 pub struct Nmimd_SPEC;
1540 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
1541 impl Nmimd {
1542 #[doc = "Falling edge"]
1543 pub const _0: Self = Self::new(0);
1544
1545 #[doc = "Rising edge"]
1546 pub const _1: Self = Self::new(1);
1547 }
1548 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1549 pub struct Nfclksel_SPEC;
1550 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
1551 impl Nfclksel {
1552 #[doc = "PCLKB"]
1553 pub const _00: Self = Self::new(0);
1554
1555 #[doc = "PCLKB/8"]
1556 pub const _01: Self = Self::new(1);
1557
1558 #[doc = "PCLKB/32"]
1559 pub const _10: Self = Self::new(2);
1560
1561 #[doc = "PCLKB/64"]
1562 pub const _11: Self = Self::new(3);
1563 }
1564 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1565 pub struct Nflten_SPEC;
1566 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
1567 impl Nflten {
1568 #[doc = "Disabled."]
1569 pub const _0: Self = Self::new(0);
1570
1571 #[doc = "Enabled."]
1572 pub const _1: Self = Self::new(1);
1573 }
1574}
1575#[doc(hidden)]
1576#[derive(Copy, Clone, Eq, PartialEq)]
1577pub struct Nmier_SPEC;
1578impl crate::sealed::RegSpec for Nmier_SPEC {
1579 type DataType = u16;
1580}
1581
1582#[doc = "Non-Maskable Interrupt Enable Register"]
1583pub type Nmier = crate::RegValueT<Nmier_SPEC>;
1584
1585impl Nmier {
1586 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
1587 #[inline(always)]
1588 pub fn iwdten(
1589 self,
1590 ) -> crate::common::RegisterField<
1591 0,
1592 0x1,
1593 1,
1594 0,
1595 nmier::Iwdten,
1596 nmier::Iwdten,
1597 Nmier_SPEC,
1598 crate::common::RW,
1599 > {
1600 crate::common::RegisterField::<
1601 0,
1602 0x1,
1603 1,
1604 0,
1605 nmier::Iwdten,
1606 nmier::Iwdten,
1607 Nmier_SPEC,
1608 crate::common::RW,
1609 >::from_register(self, 0)
1610 }
1611
1612 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
1613 #[inline(always)]
1614 pub fn wdten(
1615 self,
1616 ) -> crate::common::RegisterField<
1617 1,
1618 0x1,
1619 1,
1620 0,
1621 nmier::Wdten,
1622 nmier::Wdten,
1623 Nmier_SPEC,
1624 crate::common::RW,
1625 > {
1626 crate::common::RegisterField::<
1627 1,
1628 0x1,
1629 1,
1630 0,
1631 nmier::Wdten,
1632 nmier::Wdten,
1633 Nmier_SPEC,
1634 crate::common::RW,
1635 >::from_register(self, 0)
1636 }
1637
1638 #[doc = "Voltage monitor 1 Interrupt Enable"]
1639 #[inline(always)]
1640 pub fn lvd1en(
1641 self,
1642 ) -> crate::common::RegisterField<
1643 2,
1644 0x1,
1645 1,
1646 0,
1647 nmier::Lvd1En,
1648 nmier::Lvd1En,
1649 Nmier_SPEC,
1650 crate::common::RW,
1651 > {
1652 crate::common::RegisterField::<
1653 2,
1654 0x1,
1655 1,
1656 0,
1657 nmier::Lvd1En,
1658 nmier::Lvd1En,
1659 Nmier_SPEC,
1660 crate::common::RW,
1661 >::from_register(self, 0)
1662 }
1663
1664 #[doc = "Voltage monitor 2 Interrupt Enable"]
1665 #[inline(always)]
1666 pub fn lvd2en(
1667 self,
1668 ) -> crate::common::RegisterField<
1669 3,
1670 0x1,
1671 1,
1672 0,
1673 nmier::Lvd2En,
1674 nmier::Lvd2En,
1675 Nmier_SPEC,
1676 crate::common::RW,
1677 > {
1678 crate::common::RegisterField::<
1679 3,
1680 0x1,
1681 1,
1682 0,
1683 nmier::Lvd2En,
1684 nmier::Lvd2En,
1685 Nmier_SPEC,
1686 crate::common::RW,
1687 >::from_register(self, 0)
1688 }
1689
1690 #[doc = "Main Clock Oscillation Stop Detection Interrupt Enable"]
1691 #[inline(always)]
1692 pub fn osten(
1693 self,
1694 ) -> crate::common::RegisterField<
1695 6,
1696 0x1,
1697 1,
1698 0,
1699 nmier::Osten,
1700 nmier::Osten,
1701 Nmier_SPEC,
1702 crate::common::RW,
1703 > {
1704 crate::common::RegisterField::<
1705 6,
1706 0x1,
1707 1,
1708 0,
1709 nmier::Osten,
1710 nmier::Osten,
1711 Nmier_SPEC,
1712 crate::common::RW,
1713 >::from_register(self, 0)
1714 }
1715
1716 #[doc = "NMI Pin Interrupt Enable"]
1717 #[inline(always)]
1718 pub fn nmien(
1719 self,
1720 ) -> crate::common::RegisterField<
1721 7,
1722 0x1,
1723 1,
1724 0,
1725 nmier::Nmien,
1726 nmier::Nmien,
1727 Nmier_SPEC,
1728 crate::common::RW,
1729 > {
1730 crate::common::RegisterField::<
1731 7,
1732 0x1,
1733 1,
1734 0,
1735 nmier::Nmien,
1736 nmier::Nmien,
1737 Nmier_SPEC,
1738 crate::common::RW,
1739 >::from_register(self, 0)
1740 }
1741
1742 #[doc = "SRAM Parity Error Interrupt Enable"]
1743 #[inline(always)]
1744 pub fn rpeen(
1745 self,
1746 ) -> crate::common::RegisterField<
1747 8,
1748 0x1,
1749 1,
1750 0,
1751 nmier::Rpeen,
1752 nmier::Rpeen,
1753 Nmier_SPEC,
1754 crate::common::RW,
1755 > {
1756 crate::common::RegisterField::<
1757 8,
1758 0x1,
1759 1,
1760 0,
1761 nmier::Rpeen,
1762 nmier::Rpeen,
1763 Nmier_SPEC,
1764 crate::common::RW,
1765 >::from_register(self, 0)
1766 }
1767
1768 #[doc = "SRAM ECC Error Interrupt Enable"]
1769 #[inline(always)]
1770 pub fn reccen(
1771 self,
1772 ) -> crate::common::RegisterField<
1773 9,
1774 0x1,
1775 1,
1776 0,
1777 nmier::Reccen,
1778 nmier::Reccen,
1779 Nmier_SPEC,
1780 crate::common::RW,
1781 > {
1782 crate::common::RegisterField::<
1783 9,
1784 0x1,
1785 1,
1786 0,
1787 nmier::Reccen,
1788 nmier::Reccen,
1789 Nmier_SPEC,
1790 crate::common::RW,
1791 >::from_register(self, 0)
1792 }
1793
1794 #[doc = "Bus Master MPU Error Interrupt Enable"]
1795 #[inline(always)]
1796 pub fn busmen(
1797 self,
1798 ) -> crate::common::RegisterField<
1799 11,
1800 0x1,
1801 1,
1802 0,
1803 nmier::Busmen,
1804 nmier::Busmen,
1805 Nmier_SPEC,
1806 crate::common::RW,
1807 > {
1808 crate::common::RegisterField::<
1809 11,
1810 0x1,
1811 1,
1812 0,
1813 nmier::Busmen,
1814 nmier::Busmen,
1815 Nmier_SPEC,
1816 crate::common::RW,
1817 >::from_register(self, 0)
1818 }
1819
1820 #[inline(always)]
1821 pub fn tzfen(
1822 self,
1823 ) -> crate::common::RegisterField<
1824 13,
1825 0x1,
1826 1,
1827 0,
1828 nmier::Tzfen,
1829 nmier::Tzfen,
1830 Nmier_SPEC,
1831 crate::common::RW,
1832 > {
1833 crate::common::RegisterField::<
1834 13,
1835 0x1,
1836 1,
1837 0,
1838 nmier::Tzfen,
1839 nmier::Tzfen,
1840 Nmier_SPEC,
1841 crate::common::RW,
1842 >::from_register(self, 0)
1843 }
1844}
1845impl ::core::default::Default for Nmier {
1846 #[inline(always)]
1847 fn default() -> Nmier {
1848 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1849 }
1850}
1851pub mod nmier {
1852
1853 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1854 pub struct Iwdten_SPEC;
1855 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1856 impl Iwdten {
1857 #[doc = "Disabled"]
1858 pub const _0: Self = Self::new(0);
1859
1860 #[doc = "Enabled."]
1861 pub const _1: Self = Self::new(1);
1862 }
1863 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1864 pub struct Wdten_SPEC;
1865 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1866 impl Wdten {
1867 #[doc = "Disabled"]
1868 pub const _0: Self = Self::new(0);
1869
1870 #[doc = "Enabled"]
1871 pub const _1: Self = Self::new(1);
1872 }
1873 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1874 pub struct Lvd1En_SPEC;
1875 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1876 impl Lvd1En {
1877 #[doc = "Disabled"]
1878 pub const _0: Self = Self::new(0);
1879
1880 #[doc = "Enabled"]
1881 pub const _1: Self = Self::new(1);
1882 }
1883 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1884 pub struct Lvd2En_SPEC;
1885 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1886 impl Lvd2En {
1887 #[doc = "Disabled"]
1888 pub const _0: Self = Self::new(0);
1889
1890 #[doc = "Enabled"]
1891 pub const _1: Self = Self::new(1);
1892 }
1893 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1894 pub struct Osten_SPEC;
1895 pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
1896 impl Osten {
1897 #[doc = "Disabled"]
1898 pub const _0: Self = Self::new(0);
1899
1900 #[doc = "Enabled"]
1901 pub const _1: Self = Self::new(1);
1902 }
1903 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1904 pub struct Nmien_SPEC;
1905 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1906 impl Nmien {
1907 #[doc = "Disabled"]
1908 pub const _0: Self = Self::new(0);
1909
1910 #[doc = "Enabled"]
1911 pub const _1: Self = Self::new(1);
1912 }
1913 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1914 pub struct Rpeen_SPEC;
1915 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1916 impl Rpeen {
1917 #[doc = "Disabled"]
1918 pub const _0: Self = Self::new(0);
1919
1920 #[doc = "Enabled"]
1921 pub const _1: Self = Self::new(1);
1922 }
1923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1924 pub struct Reccen_SPEC;
1925 pub type Reccen = crate::EnumBitfieldStruct<u8, Reccen_SPEC>;
1926 impl Reccen {
1927 #[doc = "Disabled"]
1928 pub const _0: Self = Self::new(0);
1929
1930 #[doc = "Enabled"]
1931 pub const _1: Self = Self::new(1);
1932 }
1933 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1934 pub struct Busmen_SPEC;
1935 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1936 impl Busmen {
1937 #[doc = "Disabled"]
1938 pub const _0: Self = Self::new(0);
1939
1940 #[doc = "Enabled"]
1941 pub const _1: Self = Self::new(1);
1942 }
1943 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1944 pub struct Tzfen_SPEC;
1945 pub type Tzfen = crate::EnumBitfieldStruct<u8, Tzfen_SPEC>;
1946 impl Tzfen {
1947 #[doc = "Disabled"]
1948 pub const _0: Self = Self::new(0);
1949
1950 #[doc = "Enabled"]
1951 pub const _1: Self = Self::new(1);
1952 }
1953}
1954#[doc(hidden)]
1955#[derive(Copy, Clone, Eq, PartialEq)]
1956pub struct Nmiclr_SPEC;
1957impl crate::sealed::RegSpec for Nmiclr_SPEC {
1958 type DataType = u16;
1959}
1960
1961#[doc = "Non-Maskable Interrupt Status Clear Register"]
1962pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1963
1964impl Nmiclr {
1965 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1966 #[inline(always)]
1967 pub fn iwdtclr(
1968 self,
1969 ) -> crate::common::RegisterField<
1970 0,
1971 0x1,
1972 1,
1973 0,
1974 nmiclr::Iwdtclr,
1975 nmiclr::Iwdtclr,
1976 Nmiclr_SPEC,
1977 crate::common::RW,
1978 > {
1979 crate::common::RegisterField::<
1980 0,
1981 0x1,
1982 1,
1983 0,
1984 nmiclr::Iwdtclr,
1985 nmiclr::Iwdtclr,
1986 Nmiclr_SPEC,
1987 crate::common::RW,
1988 >::from_register(self, 0)
1989 }
1990
1991 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1992 #[inline(always)]
1993 pub fn wdtclr(
1994 self,
1995 ) -> crate::common::RegisterField<
1996 1,
1997 0x1,
1998 1,
1999 0,
2000 nmiclr::Wdtclr,
2001 nmiclr::Wdtclr,
2002 Nmiclr_SPEC,
2003 crate::common::RW,
2004 > {
2005 crate::common::RegisterField::<
2006 1,
2007 0x1,
2008 1,
2009 0,
2010 nmiclr::Wdtclr,
2011 nmiclr::Wdtclr,
2012 Nmiclr_SPEC,
2013 crate::common::RW,
2014 >::from_register(self, 0)
2015 }
2016
2017 #[doc = "Voltage Monitor 1 Interrupt Status Flag Clear"]
2018 #[inline(always)]
2019 pub fn lvd1clr(
2020 self,
2021 ) -> crate::common::RegisterField<
2022 2,
2023 0x1,
2024 1,
2025 0,
2026 nmiclr::Lvd1Clr,
2027 nmiclr::Lvd1Clr,
2028 Nmiclr_SPEC,
2029 crate::common::RW,
2030 > {
2031 crate::common::RegisterField::<
2032 2,
2033 0x1,
2034 1,
2035 0,
2036 nmiclr::Lvd1Clr,
2037 nmiclr::Lvd1Clr,
2038 Nmiclr_SPEC,
2039 crate::common::RW,
2040 >::from_register(self, 0)
2041 }
2042
2043 #[doc = "Voltage Monitor 2 Interrupt Status Flag Clear"]
2044 #[inline(always)]
2045 pub fn lvd2clr(
2046 self,
2047 ) -> crate::common::RegisterField<
2048 3,
2049 0x1,
2050 1,
2051 0,
2052 nmiclr::Lvd2Clr,
2053 nmiclr::Lvd2Clr,
2054 Nmiclr_SPEC,
2055 crate::common::RW,
2056 > {
2057 crate::common::RegisterField::<
2058 3,
2059 0x1,
2060 1,
2061 0,
2062 nmiclr::Lvd2Clr,
2063 nmiclr::Lvd2Clr,
2064 Nmiclr_SPEC,
2065 crate::common::RW,
2066 >::from_register(self, 0)
2067 }
2068
2069 #[doc = "Oscillation Stop Detection Interrupt Status Flag Clear"]
2070 #[inline(always)]
2071 pub fn ostclr(
2072 self,
2073 ) -> crate::common::RegisterField<
2074 6,
2075 0x1,
2076 1,
2077 0,
2078 nmiclr::Ostclr,
2079 nmiclr::Ostclr,
2080 Nmiclr_SPEC,
2081 crate::common::RW,
2082 > {
2083 crate::common::RegisterField::<
2084 6,
2085 0x1,
2086 1,
2087 0,
2088 nmiclr::Ostclr,
2089 nmiclr::Ostclr,
2090 Nmiclr_SPEC,
2091 crate::common::RW,
2092 >::from_register(self, 0)
2093 }
2094
2095 #[doc = "NMI Pin Interrupt Status Flag Clear"]
2096 #[inline(always)]
2097 pub fn nmiclr(
2098 self,
2099 ) -> crate::common::RegisterField<
2100 7,
2101 0x1,
2102 1,
2103 0,
2104 nmiclr::Nmiclr,
2105 nmiclr::Nmiclr,
2106 Nmiclr_SPEC,
2107 crate::common::RW,
2108 > {
2109 crate::common::RegisterField::<
2110 7,
2111 0x1,
2112 1,
2113 0,
2114 nmiclr::Nmiclr,
2115 nmiclr::Nmiclr,
2116 Nmiclr_SPEC,
2117 crate::common::RW,
2118 >::from_register(self, 0)
2119 }
2120
2121 #[doc = "SRAM Parity Error Interrupt Status Flag Clear"]
2122 #[inline(always)]
2123 pub fn rpeclr(
2124 self,
2125 ) -> crate::common::RegisterField<
2126 8,
2127 0x1,
2128 1,
2129 0,
2130 nmiclr::Rpeclr,
2131 nmiclr::Rpeclr,
2132 Nmiclr_SPEC,
2133 crate::common::RW,
2134 > {
2135 crate::common::RegisterField::<
2136 8,
2137 0x1,
2138 1,
2139 0,
2140 nmiclr::Rpeclr,
2141 nmiclr::Rpeclr,
2142 Nmiclr_SPEC,
2143 crate::common::RW,
2144 >::from_register(self, 0)
2145 }
2146
2147 #[doc = "SRAM ECC Error Interrupt Status Flag Clear"]
2148 #[inline(always)]
2149 pub fn reccclr(
2150 self,
2151 ) -> crate::common::RegisterField<
2152 9,
2153 0x1,
2154 1,
2155 0,
2156 nmiclr::Reccclr,
2157 nmiclr::Reccclr,
2158 Nmiclr_SPEC,
2159 crate::common::RW,
2160 > {
2161 crate::common::RegisterField::<
2162 9,
2163 0x1,
2164 1,
2165 0,
2166 nmiclr::Reccclr,
2167 nmiclr::Reccclr,
2168 Nmiclr_SPEC,
2169 crate::common::RW,
2170 >::from_register(self, 0)
2171 }
2172
2173 #[doc = "Bus Master MPU Error Interrupt Status Flag Clear"]
2174 #[inline(always)]
2175 pub fn busmclr(
2176 self,
2177 ) -> crate::common::RegisterField<
2178 11,
2179 0x1,
2180 1,
2181 0,
2182 nmiclr::Busmclr,
2183 nmiclr::Busmclr,
2184 Nmiclr_SPEC,
2185 crate::common::RW,
2186 > {
2187 crate::common::RegisterField::<
2188 11,
2189 0x1,
2190 1,
2191 0,
2192 nmiclr::Busmclr,
2193 nmiclr::Busmclr,
2194 Nmiclr_SPEC,
2195 crate::common::RW,
2196 >::from_register(self, 0)
2197 }
2198
2199 #[inline(always)]
2200 pub fn tzfclr(
2201 self,
2202 ) -> crate::common::RegisterField<
2203 13,
2204 0x1,
2205 1,
2206 0,
2207 nmiclr::Tzfclr,
2208 nmiclr::Tzfclr,
2209 Nmiclr_SPEC,
2210 crate::common::RW,
2211 > {
2212 crate::common::RegisterField::<
2213 13,
2214 0x1,
2215 1,
2216 0,
2217 nmiclr::Tzfclr,
2218 nmiclr::Tzfclr,
2219 Nmiclr_SPEC,
2220 crate::common::RW,
2221 >::from_register(self, 0)
2222 }
2223}
2224impl ::core::default::Default for Nmiclr {
2225 #[inline(always)]
2226 fn default() -> Nmiclr {
2227 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
2228 }
2229}
2230pub mod nmiclr {
2231
2232 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2233 pub struct Iwdtclr_SPEC;
2234 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
2235 impl Iwdtclr {
2236 #[doc = "No effect"]
2237 pub const _0: Self = Self::new(0);
2238
2239 #[doc = "Clear the NMISR.IWDTST flag"]
2240 pub const _1: Self = Self::new(1);
2241 }
2242 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2243 pub struct Wdtclr_SPEC;
2244 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
2245 impl Wdtclr {
2246 #[doc = "No effect"]
2247 pub const _0: Self = Self::new(0);
2248
2249 #[doc = "Clear the NMISR.WDTST flag"]
2250 pub const _1: Self = Self::new(1);
2251 }
2252 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2253 pub struct Lvd1Clr_SPEC;
2254 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
2255 impl Lvd1Clr {
2256 #[doc = "No effect"]
2257 pub const _0: Self = Self::new(0);
2258
2259 #[doc = "Clear the NMISR.LVD1ST flag"]
2260 pub const _1: Self = Self::new(1);
2261 }
2262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2263 pub struct Lvd2Clr_SPEC;
2264 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
2265 impl Lvd2Clr {
2266 #[doc = "No effect"]
2267 pub const _0: Self = Self::new(0);
2268
2269 #[doc = "Clear the NMISR.LVD2ST flag."]
2270 pub const _1: Self = Self::new(1);
2271 }
2272 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2273 pub struct Ostclr_SPEC;
2274 pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
2275 impl Ostclr {
2276 #[doc = "No effect"]
2277 pub const _0: Self = Self::new(0);
2278
2279 #[doc = "Clear the NMISR.OSTST flag"]
2280 pub const _1: Self = Self::new(1);
2281 }
2282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2283 pub struct Nmiclr_SPEC;
2284 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
2285 impl Nmiclr {
2286 #[doc = "No effect"]
2287 pub const _0: Self = Self::new(0);
2288
2289 #[doc = "Clear the NMISR.NMIST flag"]
2290 pub const _1: Self = Self::new(1);
2291 }
2292 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2293 pub struct Rpeclr_SPEC;
2294 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
2295 impl Rpeclr {
2296 #[doc = "No effect"]
2297 pub const _0: Self = Self::new(0);
2298
2299 #[doc = "Clear the NMISR.RPEST flag"]
2300 pub const _1: Self = Self::new(1);
2301 }
2302 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2303 pub struct Reccclr_SPEC;
2304 pub type Reccclr = crate::EnumBitfieldStruct<u8, Reccclr_SPEC>;
2305 impl Reccclr {
2306 #[doc = "No effect"]
2307 pub const _0: Self = Self::new(0);
2308
2309 #[doc = "Clear the NMISR.RECCST flag"]
2310 pub const _1: Self = Self::new(1);
2311 }
2312 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2313 pub struct Busmclr_SPEC;
2314 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
2315 impl Busmclr {
2316 #[doc = "No effect"]
2317 pub const _0: Self = Self::new(0);
2318
2319 #[doc = "Clear the NMISR.BUSMST flag"]
2320 pub const _1: Self = Self::new(1);
2321 }
2322 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2323 pub struct Tzfclr_SPEC;
2324 pub type Tzfclr = crate::EnumBitfieldStruct<u8, Tzfclr_SPEC>;
2325 impl Tzfclr {
2326 #[doc = "No effect"]
2327 pub const _0: Self = Self::new(0);
2328
2329 #[doc = "Clear the NMISR.TZFCLR flag"]
2330 pub const _1: Self = Self::new(1);
2331 }
2332}
2333#[doc(hidden)]
2334#[derive(Copy, Clone, Eq, PartialEq)]
2335pub struct Nmisr_SPEC;
2336impl crate::sealed::RegSpec for Nmisr_SPEC {
2337 type DataType = u16;
2338}
2339
2340#[doc = "Non-Maskable Interrupt Status Register"]
2341pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
2342
2343impl Nmisr {
2344 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag"]
2345 #[inline(always)]
2346 pub fn iwdtst(
2347 self,
2348 ) -> crate::common::RegisterField<
2349 0,
2350 0x1,
2351 1,
2352 0,
2353 nmisr::Iwdtst,
2354 nmisr::Iwdtst,
2355 Nmisr_SPEC,
2356 crate::common::R,
2357 > {
2358 crate::common::RegisterField::<
2359 0,
2360 0x1,
2361 1,
2362 0,
2363 nmisr::Iwdtst,
2364 nmisr::Iwdtst,
2365 Nmisr_SPEC,
2366 crate::common::R,
2367 >::from_register(self, 0)
2368 }
2369
2370 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag"]
2371 #[inline(always)]
2372 pub fn wdtst(
2373 self,
2374 ) -> crate::common::RegisterField<
2375 1,
2376 0x1,
2377 1,
2378 0,
2379 nmisr::Wdtst,
2380 nmisr::Wdtst,
2381 Nmisr_SPEC,
2382 crate::common::R,
2383 > {
2384 crate::common::RegisterField::<
2385 1,
2386 0x1,
2387 1,
2388 0,
2389 nmisr::Wdtst,
2390 nmisr::Wdtst,
2391 Nmisr_SPEC,
2392 crate::common::R,
2393 >::from_register(self, 0)
2394 }
2395
2396 #[doc = "Voltage Monitor 1 Interrupt Status Flag"]
2397 #[inline(always)]
2398 pub fn lvd1st(
2399 self,
2400 ) -> crate::common::RegisterField<
2401 2,
2402 0x1,
2403 1,
2404 0,
2405 nmisr::Lvd1St,
2406 nmisr::Lvd1St,
2407 Nmisr_SPEC,
2408 crate::common::R,
2409 > {
2410 crate::common::RegisterField::<
2411 2,
2412 0x1,
2413 1,
2414 0,
2415 nmisr::Lvd1St,
2416 nmisr::Lvd1St,
2417 Nmisr_SPEC,
2418 crate::common::R,
2419 >::from_register(self, 0)
2420 }
2421
2422 #[doc = "Voltage Monitor 2 Interrupt Status Flag"]
2423 #[inline(always)]
2424 pub fn lvd2st(
2425 self,
2426 ) -> crate::common::RegisterField<
2427 3,
2428 0x1,
2429 1,
2430 0,
2431 nmisr::Lvd2St,
2432 nmisr::Lvd2St,
2433 Nmisr_SPEC,
2434 crate::common::R,
2435 > {
2436 crate::common::RegisterField::<
2437 3,
2438 0x1,
2439 1,
2440 0,
2441 nmisr::Lvd2St,
2442 nmisr::Lvd2St,
2443 Nmisr_SPEC,
2444 crate::common::R,
2445 >::from_register(self, 0)
2446 }
2447
2448 #[doc = "Main Clock Oscillation Stop Detection Interrupt Status Flag"]
2449 #[inline(always)]
2450 pub fn ostst(
2451 self,
2452 ) -> crate::common::RegisterField<
2453 6,
2454 0x1,
2455 1,
2456 0,
2457 nmisr::Ostst,
2458 nmisr::Ostst,
2459 Nmisr_SPEC,
2460 crate::common::R,
2461 > {
2462 crate::common::RegisterField::<
2463 6,
2464 0x1,
2465 1,
2466 0,
2467 nmisr::Ostst,
2468 nmisr::Ostst,
2469 Nmisr_SPEC,
2470 crate::common::R,
2471 >::from_register(self, 0)
2472 }
2473
2474 #[doc = "NMI Pin Interrupt Status Flag"]
2475 #[inline(always)]
2476 pub fn nmist(
2477 self,
2478 ) -> crate::common::RegisterField<
2479 7,
2480 0x1,
2481 1,
2482 0,
2483 nmisr::Nmist,
2484 nmisr::Nmist,
2485 Nmisr_SPEC,
2486 crate::common::R,
2487 > {
2488 crate::common::RegisterField::<
2489 7,
2490 0x1,
2491 1,
2492 0,
2493 nmisr::Nmist,
2494 nmisr::Nmist,
2495 Nmisr_SPEC,
2496 crate::common::R,
2497 >::from_register(self, 0)
2498 }
2499
2500 #[doc = "SRAM Parity Error Interrupt Status Flag"]
2501 #[inline(always)]
2502 pub fn rpest(
2503 self,
2504 ) -> crate::common::RegisterField<
2505 8,
2506 0x1,
2507 1,
2508 0,
2509 nmisr::Rpest,
2510 nmisr::Rpest,
2511 Nmisr_SPEC,
2512 crate::common::R,
2513 > {
2514 crate::common::RegisterField::<
2515 8,
2516 0x1,
2517 1,
2518 0,
2519 nmisr::Rpest,
2520 nmisr::Rpest,
2521 Nmisr_SPEC,
2522 crate::common::R,
2523 >::from_register(self, 0)
2524 }
2525
2526 #[doc = "SRAM ECC Error Interrupt Status Flag"]
2527 #[inline(always)]
2528 pub fn reccst(
2529 self,
2530 ) -> crate::common::RegisterField<
2531 9,
2532 0x1,
2533 1,
2534 0,
2535 nmisr::Reccst,
2536 nmisr::Reccst,
2537 Nmisr_SPEC,
2538 crate::common::R,
2539 > {
2540 crate::common::RegisterField::<
2541 9,
2542 0x1,
2543 1,
2544 0,
2545 nmisr::Reccst,
2546 nmisr::Reccst,
2547 Nmisr_SPEC,
2548 crate::common::R,
2549 >::from_register(self, 0)
2550 }
2551
2552 #[doc = "Bus Master MPU Error Interrupt Status Flag"]
2553 #[inline(always)]
2554 pub fn busmst(
2555 self,
2556 ) -> crate::common::RegisterField<
2557 11,
2558 0x1,
2559 1,
2560 0,
2561 nmisr::Busmst,
2562 nmisr::Busmst,
2563 Nmisr_SPEC,
2564 crate::common::R,
2565 > {
2566 crate::common::RegisterField::<
2567 11,
2568 0x1,
2569 1,
2570 0,
2571 nmisr::Busmst,
2572 nmisr::Busmst,
2573 Nmisr_SPEC,
2574 crate::common::R,
2575 >::from_register(self, 0)
2576 }
2577
2578 #[inline(always)]
2579 pub fn tzfst(
2580 self,
2581 ) -> crate::common::RegisterField<
2582 13,
2583 0x1,
2584 1,
2585 0,
2586 nmisr::Tzfst,
2587 nmisr::Tzfst,
2588 Nmisr_SPEC,
2589 crate::common::R,
2590 > {
2591 crate::common::RegisterField::<
2592 13,
2593 0x1,
2594 1,
2595 0,
2596 nmisr::Tzfst,
2597 nmisr::Tzfst,
2598 Nmisr_SPEC,
2599 crate::common::R,
2600 >::from_register(self, 0)
2601 }
2602}
2603impl ::core::default::Default for Nmisr {
2604 #[inline(always)]
2605 fn default() -> Nmisr {
2606 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
2607 }
2608}
2609pub mod nmisr {
2610
2611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2612 pub struct Iwdtst_SPEC;
2613 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
2614 impl Iwdtst {
2615 #[doc = "Interrupt not requested"]
2616 pub const _0: Self = Self::new(0);
2617
2618 #[doc = "Interrupt requested"]
2619 pub const _1: Self = Self::new(1);
2620 }
2621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2622 pub struct Wdtst_SPEC;
2623 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
2624 impl Wdtst {
2625 #[doc = "Interrupt not requested"]
2626 pub const _0: Self = Self::new(0);
2627
2628 #[doc = "Interrupt requested"]
2629 pub const _1: Self = Self::new(1);
2630 }
2631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2632 pub struct Lvd1St_SPEC;
2633 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
2634 impl Lvd1St {
2635 #[doc = "Interrupt not requested"]
2636 pub const _0: Self = Self::new(0);
2637
2638 #[doc = "Interrupt requested"]
2639 pub const _1: Self = Self::new(1);
2640 }
2641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2642 pub struct Lvd2St_SPEC;
2643 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
2644 impl Lvd2St {
2645 #[doc = "Interrupt not requested"]
2646 pub const _0: Self = Self::new(0);
2647
2648 #[doc = "Interrupt requested"]
2649 pub const _1: Self = Self::new(1);
2650 }
2651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2652 pub struct Ostst_SPEC;
2653 pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
2654 impl Ostst {
2655 #[doc = "Interrupt not requested for main clock oscillation stop"]
2656 pub const _0: Self = Self::new(0);
2657
2658 #[doc = "Interrupt requested for main clock oscillation stop"]
2659 pub const _1: Self = Self::new(1);
2660 }
2661 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2662 pub struct Nmist_SPEC;
2663 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
2664 impl Nmist {
2665 #[doc = "Interrupt not requested"]
2666 pub const _0: Self = Self::new(0);
2667
2668 #[doc = "Interrupt requested"]
2669 pub const _1: Self = Self::new(1);
2670 }
2671 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2672 pub struct Rpest_SPEC;
2673 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
2674 impl Rpest {
2675 #[doc = "Interrupt not requested"]
2676 pub const _0: Self = Self::new(0);
2677
2678 #[doc = "Interrupt requested"]
2679 pub const _1: Self = Self::new(1);
2680 }
2681 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2682 pub struct Reccst_SPEC;
2683 pub type Reccst = crate::EnumBitfieldStruct<u8, Reccst_SPEC>;
2684 impl Reccst {
2685 #[doc = "Interrupt not requested"]
2686 pub const _0: Self = Self::new(0);
2687
2688 #[doc = "Interrupt requested"]
2689 pub const _1: Self = Self::new(1);
2690 }
2691 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2692 pub struct Busmst_SPEC;
2693 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
2694 impl Busmst {
2695 #[doc = "Interrupt not requested"]
2696 pub const _0: Self = Self::new(0);
2697
2698 #[doc = "Interrupt requested"]
2699 pub const _1: Self = Self::new(1);
2700 }
2701 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2702 pub struct Tzfst_SPEC;
2703 pub type Tzfst = crate::EnumBitfieldStruct<u8, Tzfst_SPEC>;
2704 impl Tzfst {
2705 #[doc = "Interrupt not requested"]
2706 pub const _0: Self = Self::new(0);
2707
2708 #[doc = "Interrupt requested"]
2709 pub const _1: Self = Self::new(1);
2710 }
2711}
2712#[doc(hidden)]
2713#[derive(Copy, Clone, Eq, PartialEq)]
2714pub struct Wupen0_SPEC;
2715impl crate::sealed::RegSpec for Wupen0_SPEC {
2716 type DataType = u32;
2717}
2718
2719#[doc = "Wake Up Interrupt Enable Register 0"]
2720pub type Wupen0 = crate::RegValueT<Wupen0_SPEC>;
2721
2722impl Wupen0 {
2723 #[doc = "IRQn Interrupt Software Standby/Snooze Mode Returns Enable bit (n = 0 to 15)"]
2724 #[inline(always)]
2725 pub fn irqwupen(
2726 self,
2727 ) -> crate::common::RegisterField<
2728 0,
2729 0xffff,
2730 1,
2731 0,
2732 wupen0::Irqwupen,
2733 wupen0::Irqwupen,
2734 Wupen0_SPEC,
2735 crate::common::RW,
2736 > {
2737 crate::common::RegisterField::<
2738 0,
2739 0xffff,
2740 1,
2741 0,
2742 wupen0::Irqwupen,
2743 wupen0::Irqwupen,
2744 Wupen0_SPEC,
2745 crate::common::RW,
2746 >::from_register(self, 0)
2747 }
2748
2749 #[doc = "IWDT Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2750 #[inline(always)]
2751 pub fn iwdtwupen(
2752 self,
2753 ) -> crate::common::RegisterField<
2754 16,
2755 0x1,
2756 1,
2757 0,
2758 wupen0::Iwdtwupen,
2759 wupen0::Iwdtwupen,
2760 Wupen0_SPEC,
2761 crate::common::RW,
2762 > {
2763 crate::common::RegisterField::<
2764 16,
2765 0x1,
2766 1,
2767 0,
2768 wupen0::Iwdtwupen,
2769 wupen0::Iwdtwupen,
2770 Wupen0_SPEC,
2771 crate::common::RW,
2772 >::from_register(self, 0)
2773 }
2774
2775 #[doc = "LVD1 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2776 #[inline(always)]
2777 pub fn lvd1wupen(
2778 self,
2779 ) -> crate::common::RegisterField<
2780 18,
2781 0x1,
2782 1,
2783 0,
2784 wupen0::Lvd1Wupen,
2785 wupen0::Lvd1Wupen,
2786 Wupen0_SPEC,
2787 crate::common::RW,
2788 > {
2789 crate::common::RegisterField::<
2790 18,
2791 0x1,
2792 1,
2793 0,
2794 wupen0::Lvd1Wupen,
2795 wupen0::Lvd1Wupen,
2796 Wupen0_SPEC,
2797 crate::common::RW,
2798 >::from_register(self, 0)
2799 }
2800
2801 #[doc = "LVD2 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2802 #[inline(always)]
2803 pub fn lvd2wupen(
2804 self,
2805 ) -> crate::common::RegisterField<
2806 19,
2807 0x1,
2808 1,
2809 0,
2810 wupen0::Lvd2Wupen,
2811 wupen0::Lvd2Wupen,
2812 Wupen0_SPEC,
2813 crate::common::RW,
2814 > {
2815 crate::common::RegisterField::<
2816 19,
2817 0x1,
2818 1,
2819 0,
2820 wupen0::Lvd2Wupen,
2821 wupen0::Lvd2Wupen,
2822 Wupen0_SPEC,
2823 crate::common::RW,
2824 >::from_register(self, 0)
2825 }
2826
2827 #[doc = "RTC Alarm Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2828 #[inline(always)]
2829 pub fn rtcalmwupen(
2830 self,
2831 ) -> crate::common::RegisterField<
2832 24,
2833 0x1,
2834 1,
2835 0,
2836 wupen0::Rtcalmwupen,
2837 wupen0::Rtcalmwupen,
2838 Wupen0_SPEC,
2839 crate::common::RW,
2840 > {
2841 crate::common::RegisterField::<
2842 24,
2843 0x1,
2844 1,
2845 0,
2846 wupen0::Rtcalmwupen,
2847 wupen0::Rtcalmwupen,
2848 Wupen0_SPEC,
2849 crate::common::RW,
2850 >::from_register(self, 0)
2851 }
2852
2853 #[doc = "RTC Period Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2854 #[inline(always)]
2855 pub fn rtcprdwupen(
2856 self,
2857 ) -> crate::common::RegisterField<
2858 25,
2859 0x1,
2860 1,
2861 0,
2862 wupen0::Rtcprdwupen,
2863 wupen0::Rtcprdwupen,
2864 Wupen0_SPEC,
2865 crate::common::RW,
2866 > {
2867 crate::common::RegisterField::<
2868 25,
2869 0x1,
2870 1,
2871 0,
2872 wupen0::Rtcprdwupen,
2873 wupen0::Rtcprdwupen,
2874 Wupen0_SPEC,
2875 crate::common::RW,
2876 >::from_register(self, 0)
2877 }
2878
2879 #[doc = "USBFS0 Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2880 #[inline(always)]
2881 pub fn usbfs0wupen(
2882 self,
2883 ) -> crate::common::RegisterField<
2884 27,
2885 0x1,
2886 1,
2887 0,
2888 wupen0::Usbfs0Wupen,
2889 wupen0::Usbfs0Wupen,
2890 Wupen0_SPEC,
2891 crate::common::RW,
2892 > {
2893 crate::common::RegisterField::<
2894 27,
2895 0x1,
2896 1,
2897 0,
2898 wupen0::Usbfs0Wupen,
2899 wupen0::Usbfs0Wupen,
2900 Wupen0_SPEC,
2901 crate::common::RW,
2902 >::from_register(self, 0)
2903 }
2904
2905 #[doc = "AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2906 #[inline(always)]
2907 pub fn agt1udwupen(
2908 self,
2909 ) -> crate::common::RegisterField<
2910 28,
2911 0x1,
2912 1,
2913 0,
2914 wupen0::Agt1Udwupen,
2915 wupen0::Agt1Udwupen,
2916 Wupen0_SPEC,
2917 crate::common::RW,
2918 > {
2919 crate::common::RegisterField::<
2920 28,
2921 0x1,
2922 1,
2923 0,
2924 wupen0::Agt1Udwupen,
2925 wupen0::Agt1Udwupen,
2926 Wupen0_SPEC,
2927 crate::common::RW,
2928 >::from_register(self, 0)
2929 }
2930
2931 #[doc = "AGT1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2932 #[inline(always)]
2933 pub fn agt1cawupen(
2934 self,
2935 ) -> crate::common::RegisterField<
2936 29,
2937 0x1,
2938 1,
2939 0,
2940 wupen0::Agt1Cawupen,
2941 wupen0::Agt1Cawupen,
2942 Wupen0_SPEC,
2943 crate::common::RW,
2944 > {
2945 crate::common::RegisterField::<
2946 29,
2947 0x1,
2948 1,
2949 0,
2950 wupen0::Agt1Cawupen,
2951 wupen0::Agt1Cawupen,
2952 Wupen0_SPEC,
2953 crate::common::RW,
2954 >::from_register(self, 0)
2955 }
2956
2957 #[doc = "AGT1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2958 #[inline(always)]
2959 pub fn agt1cbwupen(
2960 self,
2961 ) -> crate::common::RegisterField<
2962 30,
2963 0x1,
2964 1,
2965 0,
2966 wupen0::Agt1Cbwupen,
2967 wupen0::Agt1Cbwupen,
2968 Wupen0_SPEC,
2969 crate::common::RW,
2970 > {
2971 crate::common::RegisterField::<
2972 30,
2973 0x1,
2974 1,
2975 0,
2976 wupen0::Agt1Cbwupen,
2977 wupen0::Agt1Cbwupen,
2978 Wupen0_SPEC,
2979 crate::common::RW,
2980 >::from_register(self, 0)
2981 }
2982
2983 #[doc = "IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable bit"]
2984 #[inline(always)]
2985 pub fn iic0wupen(
2986 self,
2987 ) -> crate::common::RegisterField<
2988 31,
2989 0x1,
2990 1,
2991 0,
2992 wupen0::Iic0Wupen,
2993 wupen0::Iic0Wupen,
2994 Wupen0_SPEC,
2995 crate::common::RW,
2996 > {
2997 crate::common::RegisterField::<
2998 31,
2999 0x1,
3000 1,
3001 0,
3002 wupen0::Iic0Wupen,
3003 wupen0::Iic0Wupen,
3004 Wupen0_SPEC,
3005 crate::common::RW,
3006 >::from_register(self, 0)
3007 }
3008}
3009impl ::core::default::Default for Wupen0 {
3010 #[inline(always)]
3011 fn default() -> Wupen0 {
3012 <crate::RegValueT<Wupen0_SPEC> as RegisterValue<_>>::new(0)
3013 }
3014}
3015pub mod wupen0 {
3016
3017 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3018 pub struct Irqwupen_SPEC;
3019 pub type Irqwupen = crate::EnumBitfieldStruct<u8, Irqwupen_SPEC>;
3020 impl Irqwupen {
3021 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt is disabled"]
3022 pub const _0: Self = Self::new(0);
3023
3024 #[doc = "Software Standby/Snooze Mode returns by IRQn interrupt is enabled"]
3025 pub const _1: Self = Self::new(1);
3026 }
3027 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3028 pub struct Iwdtwupen_SPEC;
3029 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
3030 impl Iwdtwupen {
3031 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt is disabled"]
3032 pub const _0: Self = Self::new(0);
3033
3034 #[doc = "Software Standby/Snooze Mode returns by IWDT interrupt is enabled"]
3035 pub const _1: Self = Self::new(1);
3036 }
3037 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3038 pub struct Lvd1Wupen_SPEC;
3039 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
3040 impl Lvd1Wupen {
3041 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt is disabled"]
3042 pub const _0: Self = Self::new(0);
3043
3044 #[doc = "Software Standby/Snooze Mode returns by LVD1 interrupt is enabled"]
3045 pub const _1: Self = Self::new(1);
3046 }
3047 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3048 pub struct Lvd2Wupen_SPEC;
3049 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
3050 impl Lvd2Wupen {
3051 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt is disabled"]
3052 pub const _0: Self = Self::new(0);
3053
3054 #[doc = "Software Standby/Snooze Mode returns by LVD2 interrupt is enabled"]
3055 pub const _1: Self = Self::new(1);
3056 }
3057 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3058 pub struct Rtcalmwupen_SPEC;
3059 pub type Rtcalmwupen = crate::EnumBitfieldStruct<u8, Rtcalmwupen_SPEC>;
3060 impl Rtcalmwupen {
3061 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt is disabled"]
3062 pub const _0: Self = Self::new(0);
3063
3064 #[doc = "Software Standby/Snooze Mode returns by RTC alarm interrupt is enabled"]
3065 pub const _1: Self = Self::new(1);
3066 }
3067 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3068 pub struct Rtcprdwupen_SPEC;
3069 pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
3070 impl Rtcprdwupen {
3071 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt is disabled"]
3072 pub const _0: Self = Self::new(0);
3073
3074 #[doc = "Software Standby/Snooze Mode returns by RTC period interrupt is enabled"]
3075 pub const _1: Self = Self::new(1);
3076 }
3077 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3078 pub struct Usbfs0Wupen_SPEC;
3079 pub type Usbfs0Wupen = crate::EnumBitfieldStruct<u8, Usbfs0Wupen_SPEC>;
3080 impl Usbfs0Wupen {
3081 #[doc = "Software Standby/Snooze Mode returns by USBFS0 interrupt is disabled"]
3082 pub const _0: Self = Self::new(0);
3083
3084 #[doc = "Software Standby/Snooze Mode returns by USBFS0 interrupt is enabled"]
3085 pub const _1: Self = Self::new(1);
3086 }
3087 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3088 pub struct Agt1Udwupen_SPEC;
3089 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
3090 impl Agt1Udwupen {
3091 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt is disabled"]
3092 pub const _0: Self = Self::new(0);
3093
3094 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt is enabled"]
3095 pub const _1: Self = Self::new(1);
3096 }
3097 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3098 pub struct Agt1Cawupen_SPEC;
3099 pub type Agt1Cawupen = crate::EnumBitfieldStruct<u8, Agt1Cawupen_SPEC>;
3100 impl Agt1Cawupen {
3101 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is disabled"]
3102 pub const _0: Self = Self::new(0);
3103
3104 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match A interrupt is enabled"]
3105 pub const _1: Self = Self::new(1);
3106 }
3107 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3108 pub struct Agt1Cbwupen_SPEC;
3109 pub type Agt1Cbwupen = crate::EnumBitfieldStruct<u8, Agt1Cbwupen_SPEC>;
3110 impl Agt1Cbwupen {
3111 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is disabled"]
3112 pub const _0: Self = Self::new(0);
3113
3114 #[doc = "Software Standby/Snooze Mode returns by AGT1 compare match B interrupt is enabled"]
3115 pub const _1: Self = Self::new(1);
3116 }
3117 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3118 pub struct Iic0Wupen_SPEC;
3119 pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
3120 impl Iic0Wupen {
3121 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt is disabled"]
3122 pub const _0: Self = Self::new(0);
3123
3124 #[doc = "Software Standby/Snooze Mode returns by IIC0 address match interrupt is enabled"]
3125 pub const _1: Self = Self::new(1);
3126 }
3127}
3128#[doc(hidden)]
3129#[derive(Copy, Clone, Eq, PartialEq)]
3130pub struct Wupen1_SPEC;
3131impl crate::sealed::RegSpec for Wupen1_SPEC {
3132 type DataType = u32;
3133}
3134
3135#[doc = "Wake Up interrupt enable register 1"]
3136pub type Wupen1 = crate::RegValueT<Wupen1_SPEC>;
3137
3138impl Wupen1 {
3139 #[doc = "AGT3 Underflow Interrupt Software Standby Return Enable bit"]
3140 #[inline(always)]
3141 pub fn agt3udwupen(
3142 self,
3143 ) -> crate::common::RegisterField<
3144 0,
3145 0x1,
3146 1,
3147 0,
3148 wupen1::Agt3Udwupen,
3149 wupen1::Agt3Udwupen,
3150 Wupen1_SPEC,
3151 crate::common::RW,
3152 > {
3153 crate::common::RegisterField::<
3154 0,
3155 0x1,
3156 1,
3157 0,
3158 wupen1::Agt3Udwupen,
3159 wupen1::Agt3Udwupen,
3160 Wupen1_SPEC,
3161 crate::common::RW,
3162 >::from_register(self, 0)
3163 }
3164
3165 #[doc = "AGT3 Compare Match A Interrupt Software Standby Return Enable bit"]
3166 #[inline(always)]
3167 pub fn agt3cawupen(
3168 self,
3169 ) -> crate::common::RegisterField<
3170 1,
3171 0x1,
3172 1,
3173 0,
3174 wupen1::Agt3Cawupen,
3175 wupen1::Agt3Cawupen,
3176 Wupen1_SPEC,
3177 crate::common::RW,
3178 > {
3179 crate::common::RegisterField::<
3180 1,
3181 0x1,
3182 1,
3183 0,
3184 wupen1::Agt3Cawupen,
3185 wupen1::Agt3Cawupen,
3186 Wupen1_SPEC,
3187 crate::common::RW,
3188 >::from_register(self, 0)
3189 }
3190
3191 #[doc = "AGT3 Compare Match B Interrupt Software Standby Return Enable bit"]
3192 #[inline(always)]
3193 pub fn agt3cbwupen(
3194 self,
3195 ) -> crate::common::RegisterField<
3196 2,
3197 0x1,
3198 1,
3199 0,
3200 wupen1::Agt3Cbwupen,
3201 wupen1::Agt3Cbwupen,
3202 Wupen1_SPEC,
3203 crate::common::RW,
3204 > {
3205 crate::common::RegisterField::<
3206 2,
3207 0x1,
3208 1,
3209 0,
3210 wupen1::Agt3Cbwupen,
3211 wupen1::Agt3Cbwupen,
3212 Wupen1_SPEC,
3213 crate::common::RW,
3214 >::from_register(self, 0)
3215 }
3216}
3217impl ::core::default::Default for Wupen1 {
3218 #[inline(always)]
3219 fn default() -> Wupen1 {
3220 <crate::RegValueT<Wupen1_SPEC> as RegisterValue<_>>::new(0)
3221 }
3222}
3223pub mod wupen1 {
3224
3225 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3226 pub struct Agt3Udwupen_SPEC;
3227 pub type Agt3Udwupen = crate::EnumBitfieldStruct<u8, Agt3Udwupen_SPEC>;
3228 impl Agt3Udwupen {
3229 #[doc = "Software standby returns by AGT3 underflow interrupt is disabled"]
3230 pub const _0: Self = Self::new(0);
3231
3232 #[doc = "Software standby returns by AGT3 underflow interrupt is enabled"]
3233 pub const _1: Self = Self::new(1);
3234 }
3235 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3236 pub struct Agt3Cawupen_SPEC;
3237 pub type Agt3Cawupen = crate::EnumBitfieldStruct<u8, Agt3Cawupen_SPEC>;
3238 impl Agt3Cawupen {
3239 #[doc = "Software standby returns by AGT3 compare match A interrupt is disabled"]
3240 pub const _0: Self = Self::new(0);
3241
3242 #[doc = "Software standby returns by AGT3 compare match A interrupt is enabled"]
3243 pub const _1: Self = Self::new(1);
3244 }
3245 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3246 pub struct Agt3Cbwupen_SPEC;
3247 pub type Agt3Cbwupen = crate::EnumBitfieldStruct<u8, Agt3Cbwupen_SPEC>;
3248 impl Agt3Cbwupen {
3249 #[doc = "Software standby returns by AGT3 compare match B interrupt is disabled"]
3250 pub const _0: Self = Self::new(0);
3251
3252 #[doc = "Software standby returns by AGT3 compare match B interrupt is enabled"]
3253 pub const _1: Self = Self::new(1);
3254 }
3255}
3256#[doc(hidden)]
3257#[derive(Copy, Clone, Eq, PartialEq)]
3258pub struct Selsr0_SPEC;
3259impl crate::sealed::RegSpec for Selsr0_SPEC {
3260 type DataType = u16;
3261}
3262
3263#[doc = "SYS Event Link Setting Register"]
3264pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
3265
3266impl NoBitfieldReg<Selsr0_SPEC> for Selsr0 {}
3267impl ::core::default::Default for Selsr0 {
3268 #[inline(always)]
3269 fn default() -> Selsr0 {
3270 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
3271 }
3272}
3273
3274#[doc(hidden)]
3275#[derive(Copy, Clone, Eq, PartialEq)]
3276pub struct Delsr_SPEC;
3277impl crate::sealed::RegSpec for Delsr_SPEC {
3278 type DataType = u32;
3279}
3280
3281#[doc = "DMAC Event Link Setting Register %s"]
3282pub type Delsr = crate::RegValueT<Delsr_SPEC>;
3283
3284impl Delsr {
3285 #[doc = "DMAC Event Link Select"]
3286 #[inline(always)]
3287 pub fn dels(
3288 self,
3289 ) -> crate::common::RegisterField<
3290 0,
3291 0x1ff,
3292 1,
3293 0,
3294 delsr::Dels,
3295 delsr::Dels,
3296 Delsr_SPEC,
3297 crate::common::RW,
3298 > {
3299 crate::common::RegisterField::<
3300 0,
3301 0x1ff,
3302 1,
3303 0,
3304 delsr::Dels,
3305 delsr::Dels,
3306 Delsr_SPEC,
3307 crate::common::RW,
3308 >::from_register(self, 0)
3309 }
3310
3311 #[doc = "DMAC Activation Request Status Flag"]
3312 #[inline(always)]
3313 pub fn ir(
3314 self,
3315 ) -> crate::common::RegisterField<
3316 16,
3317 0x1,
3318 1,
3319 0,
3320 delsr::Ir,
3321 delsr::Ir,
3322 Delsr_SPEC,
3323 crate::common::RW,
3324 > {
3325 crate::common::RegisterField::<
3326 16,
3327 0x1,
3328 1,
3329 0,
3330 delsr::Ir,
3331 delsr::Ir,
3332 Delsr_SPEC,
3333 crate::common::RW,
3334 >::from_register(self, 0)
3335 }
3336}
3337impl ::core::default::Default for Delsr {
3338 #[inline(always)]
3339 fn default() -> Delsr {
3340 <crate::RegValueT<Delsr_SPEC> as RegisterValue<_>>::new(0)
3341 }
3342}
3343pub mod delsr {
3344
3345 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3346 pub struct Dels_SPEC;
3347 pub type Dels = crate::EnumBitfieldStruct<u8, Dels_SPEC>;
3348 impl Dels {
3349 #[doc = "Disable interrupts to the associated DMAC module."]
3350 pub const _0_X_00: Self = Self::new(0);
3351 }
3352 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3353 pub struct Ir_SPEC;
3354 pub type Ir = crate::EnumBitfieldStruct<u8, Ir_SPEC>;
3355 impl Ir {
3356 #[doc = "No DMAC activation request occurred."]
3357 pub const _0: Self = Self::new(0);
3358
3359 #[doc = "DMAC activation request occurred."]
3360 pub const _1: Self = Self::new(1);
3361 }
3362}
3363#[doc(hidden)]
3364#[derive(Copy, Clone, Eq, PartialEq)]
3365pub struct Ielsr_SPEC;
3366impl crate::sealed::RegSpec for Ielsr_SPEC {
3367 type DataType = u32;
3368}
3369
3370#[doc = "ICU Event Link Setting Register %s"]
3371pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
3372
3373impl NoBitfieldReg<Ielsr_SPEC> for Ielsr {}
3374impl ::core::default::Default for Ielsr {
3375 #[inline(always)]
3376 fn default() -> Ielsr {
3377 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
3378 }
3379}