ra4m1/sci0/
ftdrhl.rs

1#[doc = "Register `FTDRHL` writer"]
2pub struct W(crate::W<FTDRHL_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<FTDRHL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<FTDRHL_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<FTDRHL_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `TDAT` writer - Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)"]
23pub type TDAT_W<'a, const O: u8> = crate::FieldWriter<'a, u16, FTDRHL_SPEC, u16, u16, 9, O>;
24#[doc = "Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)\n\nValue on reset: 1"]
25#[derive(Clone, Copy, Debug, PartialEq, Eq)]
26pub enum MPBT_AW {
27    #[doc = "0: Data transmission cycles"]
28    _0 = 0,
29    #[doc = "1: ID transmission cycles"]
30    _1 = 1,
31}
32impl From<MPBT_AW> for bool {
33    #[inline(always)]
34    fn from(variant: MPBT_AW) -> Self {
35        variant as u8 != 0
36    }
37}
38#[doc = "Field `MPBT` writer - Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)"]
39pub type MPBT_W<'a, const O: u8> = crate::BitWriter<'a, u16, FTDRHL_SPEC, MPBT_AW, O>;
40impl<'a, const O: u8> MPBT_W<'a, O> {
41    #[doc = "Data transmission cycles"]
42    #[inline(always)]
43    pub fn _0(self) -> &'a mut W {
44        self.variant(MPBT_AW::_0)
45    }
46    #[doc = "ID transmission cycles"]
47    #[inline(always)]
48    pub fn _1(self) -> &'a mut W {
49        self.variant(MPBT_AW::_1)
50    }
51}
52impl W {
53    #[doc = "Bits 0:8 - Serial transmit data (Valid only in asynchronous mode(including multi-processor) or clock synchronous mode, and FIFO selected)"]
54    #[inline(always)]
55    #[must_use]
56    pub fn tdat(&mut self) -> TDAT_W<0> {
57        TDAT_W::new(self)
58    }
59    #[doc = "Bit 9 - Multi-processor transfer bit flag (Valid only in asynchronous mode and SMR.MP=1 and FIFO selected)"]
60    #[inline(always)]
61    #[must_use]
62    pub fn mpbt(&mut self) -> MPBT_W<9> {
63        MPBT_W::new(self)
64    }
65    #[doc = "Writes raw bits to the register."]
66    #[inline(always)]
67    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
68        self.0.bits(bits);
69        self
70    }
71}
72#[doc = "Transmit FIFO Data Register HL\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ftdrhl](index.html) module"]
73pub struct FTDRHL_SPEC;
74impl crate::RegisterSpec for FTDRHL_SPEC {
75    type Ux = u16;
76}
77#[doc = "`write(|w| ..)` method takes [ftdrhl::W](W) writer structure"]
78impl crate::Writable for FTDRHL_SPEC {
79    type Writer = W;
80    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
81    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
82}
83#[doc = "`reset()` method sets FTDRHL to value 0xffff"]
84impl crate::Resettable for FTDRHL_SPEC {
85    const RESET_VALUE: Self::Ux = 0xffff;
86}
ra4m1/sci0/ftdrhl.rs

ra4m1/sci0/
ftdrhl.rs
