ra4m1_fsp_pac/
lib.rs

1/*!Peripheral access API for R7FA4M1AB microcontrollers (generated using svd2rust v0.37.1 ( ))
2
3You can find an overview of the generated API [here].
4
5API features to be included in the [next] svd2rust release can be generated by cloning the svd2rust [repository], checking out the above commit, and running `cargo doc --open`.
6
7[here]: https://docs.rs/svd2rust/0.37.1/svd2rust/#peripheral-api
8[next]: https://github.com/rust-embedded/svd2rust/blob/master/CHANGELOG.md#unreleased
9[repository]: https://github.com/rust-embedded/svd2rust*/
10#![allow(non_camel_case_types)]
11#![allow(non_snake_case)]
12#![no_std]
13#![cfg_attr(docsrs, feature(doc_cfg))]
14///Number available in the NVIC for configuring priority
15pub const NVIC_PRIO_BITS: u8 = 4;
16#[allow(unused_imports)]
17use generic::*;
18///Common register and bit access and modify traits
19pub mod generic;
20#[cfg(feature = "rt")]
21extern "C" {
22    fn IEL0();
23    fn IEL1();
24    fn IEL2();
25    fn IEL3();
26    fn IEL4();
27    fn IEL5();
28    fn IEL6();
29    fn IEL7();
30    fn IEL8();
31    fn IEL9();
32    fn IEL10();
33    fn IEL11();
34    fn IEL12();
35    fn IEL13();
36    fn IEL14();
37    fn IEL15();
38    fn IEL16();
39    fn IEL17();
40    fn IEL18();
41    fn IEL19();
42    fn IEL20();
43    fn IEL21();
44    fn IEL22();
45    fn IEL23();
46    fn IEL24();
47    fn IEL25();
48    fn IEL26();
49    fn IEL27();
50    fn IEL28();
51    fn IEL29();
52    fn IEL30();
53    fn IEL31();
54}
55#[doc(hidden)]
56#[repr(C)]
57pub union Vector {
58    _handler: unsafe extern "C" fn(),
59    _reserved: u32,
60}
61#[cfg(feature = "rt")]
62#[doc(hidden)]
63#[cfg_attr(feature = "fsp", link_section = ".application_vectors")]
64#[cfg_attr(
65    feature = "cortex-m-rt-device",
66    link_section = ".vector_table.interrupts"
67)]
68#[no_mangle]
69pub static __INTERRUPTS: [Vector; 32] = [
70    Vector { _handler: IEL0 },
71    Vector { _handler: IEL1 },
72    Vector { _handler: IEL2 },
73    Vector { _handler: IEL3 },
74    Vector { _handler: IEL4 },
75    Vector { _handler: IEL5 },
76    Vector { _handler: IEL6 },
77    Vector { _handler: IEL7 },
78    Vector { _handler: IEL8 },
79    Vector { _handler: IEL9 },
80    Vector { _handler: IEL10 },
81    Vector { _handler: IEL11 },
82    Vector { _handler: IEL12 },
83    Vector { _handler: IEL13 },
84    Vector { _handler: IEL14 },
85    Vector { _handler: IEL15 },
86    Vector { _handler: IEL16 },
87    Vector { _handler: IEL17 },
88    Vector { _handler: IEL18 },
89    Vector { _handler: IEL19 },
90    Vector { _handler: IEL20 },
91    Vector { _handler: IEL21 },
92    Vector { _handler: IEL22 },
93    Vector { _handler: IEL23 },
94    Vector { _handler: IEL24 },
95    Vector { _handler: IEL25 },
96    Vector { _handler: IEL26 },
97    Vector { _handler: IEL27 },
98    Vector { _handler: IEL28 },
99    Vector { _handler: IEL29 },
100    Vector { _handler: IEL30 },
101    Vector { _handler: IEL31 },
102];
103///Enumeration of all the interrupts.
104#[derive(Copy, Clone, Debug, PartialEq, Eq)]
105#[repr(u16)]
106pub enum Interrupt {
107    ///0 - ICU Interrupt 0
108    IEL0 = 0,
109    ///1 - ICU Interrupt 1
110    IEL1 = 1,
111    ///2 - ICU Interrupt 2
112    IEL2 = 2,
113    ///3 - ICU Interrupt 3
114    IEL3 = 3,
115    ///4 - ICU Interrupt 4
116    IEL4 = 4,
117    ///5 - ICU Interrupt 5
118    IEL5 = 5,
119    ///6 - ICU Interrupt 6
120    IEL6 = 6,
121    ///7 - ICU Interrupt 7
122    IEL7 = 7,
123    ///8 - ICU Interrupt 8
124    IEL8 = 8,
125    ///9 - ICU Interrupt 9
126    IEL9 = 9,
127    ///10 - ICU Interrupt 10
128    IEL10 = 10,
129    ///11 - ICU Interrupt 11
130    IEL11 = 11,
131    ///12 - ICU Interrupt 12
132    IEL12 = 12,
133    ///13 - ICU Interrupt 13
134    IEL13 = 13,
135    ///14 - ICU Interrupt 14
136    IEL14 = 14,
137    ///15 - ICU Interrupt 15
138    IEL15 = 15,
139    ///16 - ICU Interrupt 16
140    IEL16 = 16,
141    ///17 - ICU Interrupt 17
142    IEL17 = 17,
143    ///18 - ICU Interrupt 18
144    IEL18 = 18,
145    ///19 - ICU Interrupt 19
146    IEL19 = 19,
147    ///20 - ICU Interrupt 20
148    IEL20 = 20,
149    ///21 - ICU Interrupt 21
150    IEL21 = 21,
151    ///22 - ICU Interrupt 22
152    IEL22 = 22,
153    ///23 - ICU Interrupt 23
154    IEL23 = 23,
155    ///24 - ICU Interrupt 24
156    IEL24 = 24,
157    ///25 - ICU Interrupt 25
158    IEL25 = 25,
159    ///26 - ICU Interrupt 26
160    IEL26 = 26,
161    ///27 - ICU Interrupt 27
162    IEL27 = 27,
163    ///28 - ICU Interrupt 28
164    IEL28 = 28,
165    ///29 - ICU Interrupt 29
166    IEL29 = 29,
167    ///30 - ICU Interrupt 30
168    IEL30 = 30,
169    ///31 - ICU Interrupt 31
170    IEL31 = 31,
171}
172unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
173    #[inline(always)]
174    fn number(self) -> u16 {
175        self as u16
176    }
177}
178///System Control
179pub type SYSTEM = crate::Periph<system::RegisterBlock, 0x4001_e000>;
180impl core::fmt::Debug for SYSTEM {
181    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
182        f.debug_struct("SYSTEM").finish()
183    }
184}
185///System Control
186pub mod system;
187///BUS Control
188pub type BUS = crate::Periph<bus::RegisterBlock, 0x4000_3000>;
189impl core::fmt::Debug for BUS {
190    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
191        f.debug_struct("BUS").finish()
192    }
193}
194///BUS Control
195pub mod bus;
196///Clock Frequency Accuracy Measurement Circuit
197pub type CAC = crate::Periph<cac::RegisterBlock, 0x4004_4600>;
198impl core::fmt::Debug for CAC {
199    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
200        f.debug_struct("CAC").finish()
201    }
202}
203///Clock Frequency Accuracy Measurement Circuit
204pub mod cac;
205///CAN0 Module
206pub type CAN0 = crate::Periph<can0::RegisterBlock, 0x4005_0000>;
207impl core::fmt::Debug for CAN0 {
208    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
209        f.debug_struct("CAN0").finish()
210    }
211}
212///CAN0 Module
213pub mod can0;
214///Debug Function
215pub type DBG = crate::Periph<dbg::RegisterBlock, 0x4001_b000>;
216impl core::fmt::Debug for DBG {
217    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
218        f.debug_struct("DBG").finish()
219    }
220}
221///Debug Function
222pub mod dbg;
223///CRC Calculator
224pub type CRC = crate::Periph<crc::RegisterBlock, 0x4007_4000>;
225impl core::fmt::Debug for CRC {
226    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
227        f.debug_struct("CRC").finish()
228    }
229}
230///CRC Calculator
231pub mod crc;
232///Capacitive Touch Sensing Unit
233pub type CTSU = crate::Periph<ctsu::RegisterBlock, 0x4008_1000>;
234impl core::fmt::Debug for CTSU {
235    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
236        f.debug_struct("CTSU").finish()
237    }
238}
239///Capacitive Touch Sensing Unit
240pub mod ctsu;
241///12-bit D/A converter
242pub type DAC12 = crate::Periph<dac12::RegisterBlock, 0x4005_e000>;
243impl core::fmt::Debug for DAC12 {
244    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
245        f.debug_struct("DAC12").finish()
246    }
247}
248///12-bit D/A converter
249pub mod dac12;
250///8-bit D/A converter
251pub type DAC8 = crate::Periph<dac8::RegisterBlock, 0x4009_e000>;
252impl core::fmt::Debug for DAC8 {
253    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
254        f.debug_struct("DAC8").finish()
255    }
256}
257///8-bit D/A converter
258pub mod dac8;
259///Direct memory access controller 0
260pub type DMAC0 = crate::Periph<dmac0::RegisterBlock, 0x4000_5000>;
261impl core::fmt::Debug for DMAC0 {
262    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
263        f.debug_struct("DMAC0").finish()
264    }
265}
266///Direct memory access controller 0
267pub mod dmac0;
268///Direct memory access controller 1
269pub type DMAC1 = crate::Periph<dmac0::RegisterBlock, 0x4000_5040>;
270impl core::fmt::Debug for DMAC1 {
271    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
272        f.debug_struct("DMAC1").finish()
273    }
274}
275///Direct memory access controller 1
276pub use self::dmac0 as dmac1;
277///Direct memory access controller 2
278pub type DMAC2 = crate::Periph<dmac0::RegisterBlock, 0x4000_5080>;
279impl core::fmt::Debug for DMAC2 {
280    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
281        f.debug_struct("DMAC2").finish()
282    }
283}
284///Direct memory access controller 2
285pub use self::dmac0 as dmac2;
286///Direct memory access controller 3
287pub type DMAC3 = crate::Periph<dmac0::RegisterBlock, 0x4000_50c0>;
288impl core::fmt::Debug for DMAC3 {
289    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
290        f.debug_struct("DMAC3").finish()
291    }
292}
293///Direct memory access controller 3
294pub use self::dmac0 as dmac3;
295///DMAC Module Activation
296pub type DMA = crate::Periph<dma::RegisterBlock, 0x4000_5200>;
297impl core::fmt::Debug for DMA {
298    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
299        f.debug_struct("DMA").finish()
300    }
301}
302///DMAC Module Activation
303pub mod dma;
304///Data Operation Circuit
305pub type DOC = crate::Periph<doc::RegisterBlock, 0x4005_4100>;
306impl core::fmt::Debug for DOC {
307    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
308        f.debug_struct("DOC").finish()
309    }
310}
311///Data Operation Circuit
312pub mod doc;
313///Data Transfer Controller
314pub type DTC = crate::Periph<dtc::RegisterBlock, 0x4000_5400>;
315impl core::fmt::Debug for DTC {
316    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
317        f.debug_struct("DTC").finish()
318    }
319}
320///Data Transfer Controller
321pub mod dtc;
322///Event Link Controller
323pub type ELC = crate::Periph<elc::RegisterBlock, 0x4004_1000>;
324impl core::fmt::Debug for ELC {
325    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
326        f.debug_struct("ELC").finish()
327    }
328}
329///Event Link Controller
330pub mod elc;
331///Flash Cache
332pub type FCACHE = crate::Periph<fcache::RegisterBlock, 0x4001_c000>;
333impl core::fmt::Debug for FCACHE {
334    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
335        f.debug_struct("FCACHE").finish()
336    }
337}
338///Flash Cache
339pub mod fcache;
340///Port 0 Control Registers
341pub type PORT0 = crate::Periph<port0::RegisterBlock, 0x4004_0000>;
342impl core::fmt::Debug for PORT0 {
343    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
344        f.debug_struct("PORT0").finish()
345    }
346}
347///Port 0 Control Registers
348pub mod port0;
349///Port 1 Control Registers
350pub type PORT1 = crate::Periph<port1::RegisterBlock, 0x4004_0020>;
351impl core::fmt::Debug for PORT1 {
352    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
353        f.debug_struct("PORT1").finish()
354    }
355}
356///Port 1 Control Registers
357pub mod port1;
358///Port 2 Control Registers
359pub type PORT2 = crate::Periph<port1::RegisterBlock, 0x4004_0040>;
360impl core::fmt::Debug for PORT2 {
361    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
362        f.debug_struct("PORT2").finish()
363    }
364}
365///Port 2 Control Registers
366pub use self::port1 as port2;
367///Port 3 Control Registers
368pub type PORT3 = crate::Periph<port1::RegisterBlock, 0x4004_0060>;
369impl core::fmt::Debug for PORT3 {
370    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
371        f.debug_struct("PORT3").finish()
372    }
373}
374///Port 3 Control Registers
375pub use self::port1 as port3;
376///Port 4 Control Registers
377pub type PORT4 = crate::Periph<port1::RegisterBlock, 0x4004_0080>;
378impl core::fmt::Debug for PORT4 {
379    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
380        f.debug_struct("PORT4").finish()
381    }
382}
383///Port 4 Control Registers
384pub use self::port1 as port4;
385///Port 5 Control Registers
386pub type PORT5 = crate::Periph<port0::RegisterBlock, 0x4004_00a0>;
387impl core::fmt::Debug for PORT5 {
388    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
389        f.debug_struct("PORT5").finish()
390    }
391}
392///Port 5 Control Registers
393pub use self::port0 as port5;
394///Port 6 Control Registers
395pub type PORT6 = crate::Periph<port0::RegisterBlock, 0x4004_00c0>;
396impl core::fmt::Debug for PORT6 {
397    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
398        f.debug_struct("PORT6").finish()
399    }
400}
401///Port 6 Control Registers
402pub use self::port0 as port6;
403///Port 7 Control Registers
404pub type PORT7 = crate::Periph<port0::RegisterBlock, 0x4004_00e0>;
405impl core::fmt::Debug for PORT7 {
406    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
407        f.debug_struct("PORT7").finish()
408    }
409}
410///Port 7 Control Registers
411pub use self::port0 as port7;
412///Port 8 Control Registers
413pub type PORT8 = crate::Periph<port0::RegisterBlock, 0x4004_0100>;
414impl core::fmt::Debug for PORT8 {
415    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
416        f.debug_struct("PORT8").finish()
417    }
418}
419///Port 8 Control Registers
420pub use self::port0 as port8;
421///Port 9 Control Registers
422pub type PORT9 = crate::Periph<port0::RegisterBlock, 0x4004_0120>;
423impl core::fmt::Debug for PORT9 {
424    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
425        f.debug_struct("PORT9").finish()
426    }
427}
428///Port 9 Control Registers
429pub use self::port0 as port9;
430///Pmn Pin Function Control Register
431pub type PFS = crate::Periph<pfs::RegisterBlock, 0x4004_0800>;
432impl core::fmt::Debug for PFS {
433    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
434        f.debug_struct("PFS").finish()
435    }
436}
437///Pmn Pin Function Control Register
438pub mod pfs;
439///Miscellaneous Port Control Register
440pub type PMISC = crate::Periph<pmisc::RegisterBlock, 0x4004_0d00>;
441impl core::fmt::Debug for PMISC {
442    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
443        f.debug_struct("PMISC").finish()
444    }
445}
446///Miscellaneous Port Control Register
447pub mod pmisc;
448///Interrupt Controller
449pub type ICU = crate::Periph<icu::RegisterBlock, 0x4000_6000>;
450impl core::fmt::Debug for ICU {
451    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
452        f.debug_struct("ICU").finish()
453    }
454}
455///Interrupt Controller
456pub mod icu;
457///Inter-Integrated Circuit 0
458pub type IIC0 = crate::Periph<iic0::RegisterBlock, 0x4005_3000>;
459impl core::fmt::Debug for IIC0 {
460    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
461        f.debug_struct("IIC0").finish()
462    }
463}
464///Inter-Integrated Circuit 0
465pub mod iic0;
466///Inter-Integrated Circuit 1
467pub type IIC1 = crate::Periph<iic1::RegisterBlock, 0x4005_3100>;
468impl core::fmt::Debug for IIC1 {
469    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
470        f.debug_struct("IIC1").finish()
471    }
472}
473///Inter-Integrated Circuit 1
474pub mod iic1;
475///Independent Watchdog Timer
476pub type IWDT = crate::Periph<iwdt::RegisterBlock, 0x4004_4400>;
477impl core::fmt::Debug for IWDT {
478    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
479        f.debug_struct("IWDT").finish()
480    }
481}
482///Independent Watchdog Timer
483pub mod iwdt;
484///Key Interrupt Function
485pub type KINT = crate::Periph<kint::RegisterBlock, 0x4008_0000>;
486impl core::fmt::Debug for KINT {
487    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
488        f.debug_struct("KINT").finish()
489    }
490}
491///Key Interrupt Function
492pub mod kint;
493///Module Stop Control B,C,D
494pub type MSTP = crate::Periph<mstp::RegisterBlock, 0x4004_7000>;
495impl core::fmt::Debug for MSTP {
496    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
497        f.debug_struct("MSTP").finish()
498    }
499}
500///Module Stop Control B,C,D
501pub mod mstp;
502///Bus Master MPU
503pub type MMPU = crate::Periph<mmpu::RegisterBlock, 0x4000_0000>;
504impl core::fmt::Debug for MMPU {
505    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
506        f.debug_struct("MMPU").finish()
507    }
508}
509///Bus Master MPU
510pub mod mmpu;
511///Bus Slave MPU
512pub type SMPU = crate::Periph<smpu::RegisterBlock, 0x4000_0c00>;
513impl core::fmt::Debug for SMPU {
514    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
515        f.debug_struct("SMPU").finish()
516    }
517}
518///Bus Slave MPU
519pub mod smpu;
520///CPU Stack Pointer Monitor
521pub type SPMON = crate::Periph<spmon::RegisterBlock, 0x4000_0d00>;
522impl core::fmt::Debug for SPMON {
523    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
524        f.debug_struct("SPMON").finish()
525    }
526}
527///CPU Stack Pointer Monitor
528pub mod spmon;
529///OperationalAmplifier
530pub type OPAMP = crate::Periph<opamp::RegisterBlock, 0x4008_6000>;
531impl core::fmt::Debug for OPAMP {
532    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
533        f.debug_struct("OPAMP").finish()
534    }
535}
536///OperationalAmplifier
537pub mod opamp;
538///Port Output Enable Module for GPT
539pub type POEG = crate::Periph<poeg::RegisterBlock, 0x4004_2000>;
540impl core::fmt::Debug for POEG {
541    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
542        f.debug_struct("POEG").finish()
543    }
544}
545///Port Output Enable Module for GPT
546pub mod poeg;
547///SRAM Control
548pub type SRAM = crate::Periph<sram::RegisterBlock, 0x4000_2000>;
549impl core::fmt::Debug for SRAM {
550    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
551        f.debug_struct("SRAM").finish()
552    }
553}
554///SRAM Control
555pub mod sram;
556///Realtime Clock
557pub type RTC = crate::Periph<rtc::RegisterBlock, 0x4004_4000>;
558impl core::fmt::Debug for RTC {
559    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
560        f.debug_struct("RTC").finish()
561    }
562}
563///Realtime Clock
564pub mod rtc;
565///Serial Communication Interface 0
566pub type SCI0 = crate::Periph<sci0::RegisterBlock, 0x4007_0000>;
567impl core::fmt::Debug for SCI0 {
568    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
569        f.debug_struct("SCI0").finish()
570    }
571}
572///Serial Communication Interface 0
573pub mod sci0;
574///Serial Communication Interface 1
575pub type SCI1 = crate::Periph<sci0::RegisterBlock, 0x4007_0020>;
576impl core::fmt::Debug for SCI1 {
577    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
578        f.debug_struct("SCI1").finish()
579    }
580}
581///Serial Communication Interface 1
582pub use self::sci0 as sci1;
583///Serial Communication Interface 2
584pub type SCI2 = crate::Periph<sci2::RegisterBlock, 0x4007_0040>;
585impl core::fmt::Debug for SCI2 {
586    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
587        f.debug_struct("SCI2").finish()
588    }
589}
590///Serial Communication Interface 2
591pub mod sci2;
592///Serial Communication Interface 9
593pub type SCI9 = crate::Periph<sci2::RegisterBlock, 0x4007_0120>;
594impl core::fmt::Debug for SCI9 {
595    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
596        f.debug_struct("SCI9").finish()
597    }
598}
599///Serial Communication Interface 9
600pub use self::sci2 as sci9;
601///Segment LCD Controller/Driver
602pub type SLCDC = crate::Periph<slcdc::RegisterBlock, 0x4008_2000>;
603impl core::fmt::Debug for SLCDC {
604    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
605        f.debug_struct("SLCDC").finish()
606    }
607}
608///Segment LCD Controller/Driver
609pub mod slcdc;
610///Serial Peripheral Interface 0
611pub type SPI0 = crate::Periph<spi0::RegisterBlock, 0x4007_2000>;
612impl core::fmt::Debug for SPI0 {
613    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
614        f.debug_struct("SPI0").finish()
615    }
616}
617///Serial Peripheral Interface 0
618pub mod spi0;
619///Serial Peripheral Interface 1
620pub type SPI1 = crate::Periph<spi1::RegisterBlock, 0x4007_2100>;
621impl core::fmt::Debug for SPI1 {
622    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
623        f.debug_struct("SPI1").finish()
624    }
625}
626///Serial Peripheral Interface 1
627pub mod spi1;
628///Serial Sound Interface Ver.2.0
629pub type SSIE0 = crate::Periph<ssie0::RegisterBlock, 0x4004_e000>;
630impl core::fmt::Debug for SSIE0 {
631    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
632        f.debug_struct("SSIE0").finish()
633    }
634}
635///Serial Sound Interface Ver.2.0
636pub mod ssie0;
637///Temperature Sensor
638pub type TSN = crate::Periph<tsn::RegisterBlock, 0x407e_c000>;
639impl core::fmt::Debug for TSN {
640    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
641        f.debug_struct("TSN").finish()
642    }
643}
644///Temperature Sensor
645pub mod tsn;
646///USB 2.0 FS Module
647pub type USBFS = crate::Periph<usbfs::RegisterBlock, 0x4009_0000>;
648impl core::fmt::Debug for USBFS {
649    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
650        f.debug_struct("USBFS").finish()
651    }
652}
653///USB 2.0 FS Module
654pub mod usbfs;
655///Watchdog Timer
656pub type WDT = crate::Periph<wdt::RegisterBlock, 0x4004_4200>;
657impl core::fmt::Debug for WDT {
658    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
659        f.debug_struct("WDT").finish()
660    }
661}
662///Watchdog Timer
663pub mod wdt;
664///Low-Power Analog Comparator
665pub type ACMPLP = crate::Periph<acmplp::RegisterBlock, 0x4008_5e00>;
666impl core::fmt::Debug for ACMPLP {
667    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
668        f.debug_struct("ACMPLP").finish()
669    }
670}
671///Low-Power Analog Comparator
672pub mod acmplp;
673///14bit A/D Converter
674pub type ADC140 = crate::Periph<adc140::RegisterBlock, 0x4005_c000>;
675impl core::fmt::Debug for ADC140 {
676    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
677        f.debug_struct("ADC140").finish()
678    }
679}
680///14bit A/D Converter
681pub mod adc140;
682///Asynchronous General purpose Timer 0
683pub type AGT0 = crate::Periph<agt0::RegisterBlock, 0x4008_4000>;
684impl core::fmt::Debug for AGT0 {
685    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
686        f.debug_struct("AGT0").finish()
687    }
688}
689///Asynchronous General purpose Timer 0
690pub mod agt0;
691///Asynchronous General purpose Timer 1
692pub type AGT1 = crate::Periph<agt0::RegisterBlock, 0x4008_4100>;
693impl core::fmt::Debug for AGT1 {
694    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
695        f.debug_struct("AGT1").finish()
696    }
697}
698///Asynchronous General purpose Timer 1
699pub use self::agt0 as agt1;
700///General PWM Timer 0 (32-bit)
701pub type GPT320 = crate::Periph<gpt320::RegisterBlock, 0x4007_8000>;
702impl core::fmt::Debug for GPT320 {
703    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
704        f.debug_struct("GPT320").finish()
705    }
706}
707///General PWM Timer 0 (32-bit)
708pub mod gpt320;
709///General PWM Timer 1 (32-bit)
710pub type GPT321 = crate::Periph<gpt320::RegisterBlock, 0x4007_8100>;
711impl core::fmt::Debug for GPT321 {
712    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
713        f.debug_struct("GPT321").finish()
714    }
715}
716///General PWM Timer 1 (32-bit)
717pub use self::gpt320 as gpt321;
718///General PWM Timer 2 (16-bit)
719pub type GPT162 = crate::Periph<gpt162::RegisterBlock, 0x4007_8200>;
720impl core::fmt::Debug for GPT162 {
721    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
722        f.debug_struct("GPT162").finish()
723    }
724}
725///General PWM Timer 2 (16-bit)
726pub mod gpt162;
727///General PWM Timer 3 (16-bit)
728pub type GPT163 = crate::Periph<gpt162::RegisterBlock, 0x4007_8300>;
729impl core::fmt::Debug for GPT163 {
730    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
731        f.debug_struct("GPT163").finish()
732    }
733}
734///General PWM Timer 3 (16-bit)
735pub use self::gpt162 as gpt163;
736///General PWM Timer 4 (16-bit)
737pub type GPT164 = crate::Periph<gpt162::RegisterBlock, 0x4007_8400>;
738impl core::fmt::Debug for GPT164 {
739    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
740        f.debug_struct("GPT164").finish()
741    }
742}
743///General PWM Timer 4 (16-bit)
744pub use self::gpt162 as gpt164;
745///General PWM Timer 5 (16-bit)
746pub type GPT165 = crate::Periph<gpt162::RegisterBlock, 0x4007_8500>;
747impl core::fmt::Debug for GPT165 {
748    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
749        f.debug_struct("GPT165").finish()
750    }
751}
752///General PWM Timer 5 (16-bit)
753pub use self::gpt162 as gpt165;
754///General PWM Timer 6 (16-bit)
755pub type GPT166 = crate::Periph<gpt162::RegisterBlock, 0x4007_8600>;
756impl core::fmt::Debug for GPT166 {
757    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
758        f.debug_struct("GPT166").finish()
759    }
760}
761///General PWM Timer 6 (16-bit)
762pub use self::gpt162 as gpt166;
763///General PWM Timer 7 (16-bit)
764pub type GPT167 = crate::Periph<gpt162::RegisterBlock, 0x4007_8700>;
765impl core::fmt::Debug for GPT167 {
766    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
767        f.debug_struct("GPT167").finish()
768    }
769}
770///General PWM Timer 7 (16-bit)
771pub use self::gpt162 as gpt167;
772///Output Phase Switching Controller
773pub type GPT_OPS = crate::Periph<gpt_ops::RegisterBlock, 0x4007_8ff0>;
774impl core::fmt::Debug for GPT_OPS {
775    fn fmt(&self, f: &mut core::fmt::Formatter) -> core::fmt::Result {
776        f.debug_struct("GPT_OPS").finish()
777    }
778}
779///Output Phase Switching Controller
780pub mod gpt_ops;
781#[no_mangle]
782static mut DEVICE_PERIPHERALS: bool = false;
783/// All the peripherals.
784#[allow(non_snake_case)]
785pub struct Peripherals {
786    ///SYSTEM
787    pub SYSTEM: SYSTEM,
788    ///BUS
789    pub BUS: BUS,
790    ///CAC
791    pub CAC: CAC,
792    ///CAN0
793    pub CAN0: CAN0,
794    ///DBG
795    pub DBG: DBG,
796    ///CRC
797    pub CRC: CRC,
798    ///CTSU
799    pub CTSU: CTSU,
800    ///DAC12
801    pub DAC12: DAC12,
802    ///DAC8
803    pub DAC8: DAC8,
804    ///DMAC0
805    pub DMAC0: DMAC0,
806    ///DMAC1
807    pub DMAC1: DMAC1,
808    ///DMAC2
809    pub DMAC2: DMAC2,
810    ///DMAC3
811    pub DMAC3: DMAC3,
812    ///DMA
813    pub DMA: DMA,
814    ///DOC
815    pub DOC: DOC,
816    ///DTC
817    pub DTC: DTC,
818    ///ELC
819    pub ELC: ELC,
820    ///FCACHE
821    pub FCACHE: FCACHE,
822    ///PORT0
823    pub PORT0: PORT0,
824    ///PORT1
825    pub PORT1: PORT1,
826    ///PORT2
827    pub PORT2: PORT2,
828    ///PORT3
829    pub PORT3: PORT3,
830    ///PORT4
831    pub PORT4: PORT4,
832    ///PORT5
833    pub PORT5: PORT5,
834    ///PORT6
835    pub PORT6: PORT6,
836    ///PORT7
837    pub PORT7: PORT7,
838    ///PORT8
839    pub PORT8: PORT8,
840    ///PORT9
841    pub PORT9: PORT9,
842    ///PFS
843    pub PFS: PFS,
844    ///PMISC
845    pub PMISC: PMISC,
846    ///ICU
847    pub ICU: ICU,
848    ///IIC0
849    pub IIC0: IIC0,
850    ///IIC1
851    pub IIC1: IIC1,
852    ///IWDT
853    pub IWDT: IWDT,
854    ///KINT
855    pub KINT: KINT,
856    ///MSTP
857    pub MSTP: MSTP,
858    ///MMPU
859    pub MMPU: MMPU,
860    ///SMPU
861    pub SMPU: SMPU,
862    ///SPMON
863    pub SPMON: SPMON,
864    ///OPAMP
865    pub OPAMP: OPAMP,
866    ///POEG
867    pub POEG: POEG,
868    ///SRAM
869    pub SRAM: SRAM,
870    ///RTC
871    pub RTC: RTC,
872    ///SCI0
873    pub SCI0: SCI0,
874    ///SCI1
875    pub SCI1: SCI1,
876    ///SCI2
877    pub SCI2: SCI2,
878    ///SCI9
879    pub SCI9: SCI9,
880    ///SLCDC
881    pub SLCDC: SLCDC,
882    ///SPI0
883    pub SPI0: SPI0,
884    ///SPI1
885    pub SPI1: SPI1,
886    ///SSIE0
887    pub SSIE0: SSIE0,
888    ///TSN
889    pub TSN: TSN,
890    ///USBFS
891    pub USBFS: USBFS,
892    ///WDT
893    pub WDT: WDT,
894    ///ACMPLP
895    pub ACMPLP: ACMPLP,
896    ///ADC140
897    pub ADC140: ADC140,
898    ///AGT0
899    pub AGT0: AGT0,
900    ///AGT1
901    pub AGT1: AGT1,
902    ///GPT320
903    pub GPT320: GPT320,
904    ///GPT321
905    pub GPT321: GPT321,
906    ///GPT162
907    pub GPT162: GPT162,
908    ///GPT163
909    pub GPT163: GPT163,
910    ///GPT164
911    pub GPT164: GPT164,
912    ///GPT165
913    pub GPT165: GPT165,
914    ///GPT166
915    pub GPT166: GPT166,
916    ///GPT167
917    pub GPT167: GPT167,
918    ///GPT_OPS
919    pub GPT_OPS: GPT_OPS,
920}
921impl Peripherals {
922    /// Returns all the peripherals *once*.
923    #[cfg(feature = "critical-section")]
924    #[inline]
925    pub fn take() -> Option<Self> {
926        critical_section::with(|_| {
927            if unsafe { DEVICE_PERIPHERALS } {
928                return None;
929            }
930            Some(unsafe { Peripherals::steal() })
931        })
932    }
933    /// Unchecked version of `Peripherals::take`.
934    ///
935    /// # Safety
936    ///
937    /// Each of the returned peripherals must be used at most once.
938    #[inline]
939    pub unsafe fn steal() -> Self {
940        DEVICE_PERIPHERALS = true;
941        Peripherals {
942            SYSTEM: SYSTEM::steal(),
943            BUS: BUS::steal(),
944            CAC: CAC::steal(),
945            CAN0: CAN0::steal(),
946            DBG: DBG::steal(),
947            CRC: CRC::steal(),
948            CTSU: CTSU::steal(),
949            DAC12: DAC12::steal(),
950            DAC8: DAC8::steal(),
951            DMAC0: DMAC0::steal(),
952            DMAC1: DMAC1::steal(),
953            DMAC2: DMAC2::steal(),
954            DMAC3: DMAC3::steal(),
955            DMA: DMA::steal(),
956            DOC: DOC::steal(),
957            DTC: DTC::steal(),
958            ELC: ELC::steal(),
959            FCACHE: FCACHE::steal(),
960            PORT0: PORT0::steal(),
961            PORT1: PORT1::steal(),
962            PORT2: PORT2::steal(),
963            PORT3: PORT3::steal(),
964            PORT4: PORT4::steal(),
965            PORT5: PORT5::steal(),
966            PORT6: PORT6::steal(),
967            PORT7: PORT7::steal(),
968            PORT8: PORT8::steal(),
969            PORT9: PORT9::steal(),
970            PFS: PFS::steal(),
971            PMISC: PMISC::steal(),
972            ICU: ICU::steal(),
973            IIC0: IIC0::steal(),
974            IIC1: IIC1::steal(),
975            IWDT: IWDT::steal(),
976            KINT: KINT::steal(),
977            MSTP: MSTP::steal(),
978            MMPU: MMPU::steal(),
979            SMPU: SMPU::steal(),
980            SPMON: SPMON::steal(),
981            OPAMP: OPAMP::steal(),
982            POEG: POEG::steal(),
983            SRAM: SRAM::steal(),
984            RTC: RTC::steal(),
985            SCI0: SCI0::steal(),
986            SCI1: SCI1::steal(),
987            SCI2: SCI2::steal(),
988            SCI9: SCI9::steal(),
989            SLCDC: SLCDC::steal(),
990            SPI0: SPI0::steal(),
991            SPI1: SPI1::steal(),
992            SSIE0: SSIE0::steal(),
993            TSN: TSN::steal(),
994            USBFS: USBFS::steal(),
995            WDT: WDT::steal(),
996            ACMPLP: ACMPLP::steal(),
997            ADC140: ADC140::steal(),
998            AGT0: AGT0::steal(),
999            AGT1: AGT1::steal(),
1000            GPT320: GPT320::steal(),
1001            GPT321: GPT321::steal(),
1002            GPT162: GPT162::steal(),
1003            GPT163: GPT163::steal(),
1004            GPT164: GPT164::steal(),
1005            GPT165: GPT165::steal(),
1006            GPT166: GPT166::steal(),
1007            GPT167: GPT167::steal(),
1008            GPT_OPS: GPT_OPS::steal(),
1009        }
1010    }
1011}
1012#[cfg(all(feature = "fsp", feature = "cortex-m-rt-device"))]
1013compile_error!("Cannot enable both `fsp` and `cortex-m-rt-device` features at the same time.");
1014pub use self::Interrupt as interrupt;
1015impl Interrupt {
1016    pub const fn try_from_u16(n: u16) -> Option<Self> {
1017        #[cfg(feature = "rt")]
1018        const {
1019            assert!(__INTERRUPTS.len() == 32);
1020            assert!(__INTERRUPTS.len() <= (u16::MAX as usize));
1021        };
1022        if n >= 32 as u16 {
1023            return None;
1024        }
1025        Some(unsafe { ::core::mem::transmute(n as u16) })
1026    }
1027}
1028#[derive(Debug)]
1029pub struct InvalidInterruptNumber;
1030impl TryFrom<u16> for Interrupt {
1031    type Error = InvalidInterruptNumber;
1032    fn try_from(value: u16) -> Result<Self, Self::Error> {
1033        Interrupt::try_from_u16(value).ok_or(InvalidInterruptNumber)
1034    }
1035}
1036impl core::error::Error for InvalidInterruptNumber {}
1037impl core::fmt::Display for InvalidInterruptNumber {
1038    fn fmt(&self, f: &mut core::fmt::Formatter<'_>) -> core::fmt::Result {
1039        write!(f, "Invalid interrupt number")
1040    }
1041}
ra4m1_fsp_pac/lib.rs

ra4m1_fsp_pac/
lib.rs
