ra4e2_pac/
pfs.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.30.00, with svd2pac 0.6.0 on Thu, 24 Jul 2025 04:48:35 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Control Register"]
28unsafe impl ::core::marker::Send for super::Pfs {}
29unsafe impl ::core::marker::Sync for super::Pfs {}
30impl super::Pfs {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Port 00%s Pin Function Select Register"]
38    #[inline(always)]
39    pub const fn p00pfs(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW>,
43        3,
44        0x4,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x10usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn p004pfs(
52        &self,
53    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(0x10usize),
57            )
58        }
59    }
60    #[inline(always)]
61    pub const fn p005pfs(
62        &self,
63    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
64        unsafe {
65            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
66                self._svd2pac_as_ptr().add(0x14usize),
67            )
68        }
69    }
70    #[inline(always)]
71    pub const fn p006pfs(
72        &self,
73    ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(0x18usize),
77            )
78        }
79    }
80
81    #[doc = "Port 00%s Pin Function Select Register"]
82    #[inline(always)]
83    pub const fn p00pfs_ha(
84        &self,
85    ) -> &'static crate::common::ClusterRegisterArray<
86        crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW>,
87        3,
88        0x4,
89    > {
90        unsafe {
91            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12usize))
92        }
93    }
94    #[inline(always)]
95    pub const fn p004pfs_ha(
96        &self,
97    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
98        unsafe {
99            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
100                self._svd2pac_as_ptr().add(0x12usize),
101            )
102        }
103    }
104    #[inline(always)]
105    pub const fn p005pfs_ha(
106        &self,
107    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(0x16usize),
111            )
112        }
113    }
114    #[inline(always)]
115    pub const fn p006pfs_ha(
116        &self,
117    ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
118        unsafe {
119            crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
120                self._svd2pac_as_ptr().add(0x1ausize),
121            )
122        }
123    }
124
125    #[doc = "Port 00%s Pin Function Select Register"]
126    #[inline(always)]
127    pub const fn p00pfs_by(
128        &self,
129    ) -> &'static crate::common::ClusterRegisterArray<
130        crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW>,
131        3,
132        0x4,
133    > {
134        unsafe {
135            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x13usize))
136        }
137    }
138    #[inline(always)]
139    pub const fn p004pfs_by(
140        &self,
141    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
142        unsafe {
143            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
144                self._svd2pac_as_ptr().add(0x13usize),
145            )
146        }
147    }
148    #[inline(always)]
149    pub const fn p005pfs_by(
150        &self,
151    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0x17usize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn p006pfs_by(
160        &self,
161    ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
162        unsafe {
163            crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
164                self._svd2pac_as_ptr().add(0x1busize),
165            )
166        }
167    }
168
169    #[doc = "Port 008 Pin Function Select Register"]
170    #[inline(always)]
171    pub const fn p008pfs(
172        &self,
173    ) -> &'static crate::common::Reg<self::P008Pfs_SPEC, crate::common::RW> {
174        unsafe {
175            crate::common::Reg::<self::P008Pfs_SPEC, crate::common::RW>::from_ptr(
176                self._svd2pac_as_ptr().add(32usize),
177            )
178        }
179    }
180
181    #[doc = "Port 008 Pin Function Select Register"]
182    #[inline(always)]
183    pub const fn p008pfs_ha(
184        &self,
185    ) -> &'static crate::common::Reg<self::P008PfsHa_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::P008PfsHa_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(34usize),
189            )
190        }
191    }
192
193    #[doc = "Port 008 Pin Function Select Register"]
194    #[inline(always)]
195    pub const fn p008pfs_by(
196        &self,
197    ) -> &'static crate::common::Reg<self::P008PfsBy_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::P008PfsBy_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(35usize),
201            )
202        }
203    }
204
205    #[doc = "Port 0%s Pin Function Select Register"]
206    #[inline(always)]
207    pub const fn p0pfs(
208        &self,
209    ) -> &'static crate::common::ClusterRegisterArray<
210        crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW>,
211        3,
212        0x4,
213    > {
214        unsafe {
215            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x34usize))
216        }
217    }
218    #[inline(always)]
219    pub const fn p013pfs(
220        &self,
221    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
222        unsafe {
223            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
224                self._svd2pac_as_ptr().add(0x34usize),
225            )
226        }
227    }
228    #[inline(always)]
229    pub const fn p014pfs(
230        &self,
231    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
232        unsafe {
233            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
234                self._svd2pac_as_ptr().add(0x38usize),
235            )
236        }
237    }
238    #[inline(always)]
239    pub const fn p015pfs(
240        &self,
241    ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
242        unsafe {
243            crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
244                self._svd2pac_as_ptr().add(0x3cusize),
245            )
246        }
247    }
248
249    #[doc = "Port 0%s Pin Function Select Register"]
250    #[inline(always)]
251    pub const fn p0pfs_ha(
252        &self,
253    ) -> &'static crate::common::ClusterRegisterArray<
254        crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW>,
255        3,
256        0x4,
257    > {
258        unsafe {
259            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x36usize))
260        }
261    }
262    #[inline(always)]
263    pub const fn p013pfs_ha(
264        &self,
265    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(0x36usize),
269            )
270        }
271    }
272    #[inline(always)]
273    pub const fn p014pfs_ha(
274        &self,
275    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
276        unsafe {
277            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
278                self._svd2pac_as_ptr().add(0x3ausize),
279            )
280        }
281    }
282    #[inline(always)]
283    pub const fn p015pfs_ha(
284        &self,
285    ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
286        unsafe {
287            crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
288                self._svd2pac_as_ptr().add(0x3eusize),
289            )
290        }
291    }
292
293    #[doc = "Port 0%s Pin Function Select Register"]
294    #[inline(always)]
295    pub const fn p0pfs_by(
296        &self,
297    ) -> &'static crate::common::ClusterRegisterArray<
298        crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW>,
299        3,
300        0x4,
301    > {
302        unsafe {
303            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x37usize))
304        }
305    }
306    #[inline(always)]
307    pub const fn p013pfs_by(
308        &self,
309    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
310        unsafe {
311            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
312                self._svd2pac_as_ptr().add(0x37usize),
313            )
314        }
315    }
316    #[inline(always)]
317    pub const fn p014pfs_by(
318        &self,
319    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
320        unsafe {
321            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
322                self._svd2pac_as_ptr().add(0x3busize),
323            )
324        }
325    }
326    #[inline(always)]
327    pub const fn p015pfs_by(
328        &self,
329    ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
330        unsafe {
331            crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
332                self._svd2pac_as_ptr().add(0x3fusize),
333            )
334        }
335    }
336
337    #[doc = "Port 10%s Pin Function Select Register"]
338    #[inline(always)]
339    pub const fn p10pfs(
340        &self,
341    ) -> &'static crate::common::ClusterRegisterArray<
342        crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW>,
343        8,
344        0x4,
345    > {
346        unsafe {
347            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x48usize))
348        }
349    }
350    #[inline(always)]
351    pub const fn p102pfs(
352        &self,
353    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
354        unsafe {
355            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
356                self._svd2pac_as_ptr().add(0x48usize),
357            )
358        }
359    }
360    #[inline(always)]
361    pub const fn p103pfs(
362        &self,
363    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
364        unsafe {
365            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
366                self._svd2pac_as_ptr().add(0x4cusize),
367            )
368        }
369    }
370    #[inline(always)]
371    pub const fn p104pfs(
372        &self,
373    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
374        unsafe {
375            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
376                self._svd2pac_as_ptr().add(0x50usize),
377            )
378        }
379    }
380    #[inline(always)]
381    pub const fn p105pfs(
382        &self,
383    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
384        unsafe {
385            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
386                self._svd2pac_as_ptr().add(0x54usize),
387            )
388        }
389    }
390    #[inline(always)]
391    pub const fn p106pfs(
392        &self,
393    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
394        unsafe {
395            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
396                self._svd2pac_as_ptr().add(0x58usize),
397            )
398        }
399    }
400    #[inline(always)]
401    pub const fn p107pfs(
402        &self,
403    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
404        unsafe {
405            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
406                self._svd2pac_as_ptr().add(0x5cusize),
407            )
408        }
409    }
410    #[inline(always)]
411    pub const fn p108pfs(
412        &self,
413    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
414        unsafe {
415            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
416                self._svd2pac_as_ptr().add(0x60usize),
417            )
418        }
419    }
420    #[inline(always)]
421    pub const fn p109pfs(
422        &self,
423    ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
424        unsafe {
425            crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
426                self._svd2pac_as_ptr().add(0x64usize),
427            )
428        }
429    }
430
431    #[doc = "Port 10%s Pin Function Select Register"]
432    #[inline(always)]
433    pub const fn p10pfs_ha(
434        &self,
435    ) -> &'static crate::common::ClusterRegisterArray<
436        crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW>,
437        8,
438        0x4,
439    > {
440        unsafe {
441            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4ausize))
442        }
443    }
444    #[inline(always)]
445    pub const fn p102pfs_ha(
446        &self,
447    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
448        unsafe {
449            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
450                self._svd2pac_as_ptr().add(0x4ausize),
451            )
452        }
453    }
454    #[inline(always)]
455    pub const fn p103pfs_ha(
456        &self,
457    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
458        unsafe {
459            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
460                self._svd2pac_as_ptr().add(0x4eusize),
461            )
462        }
463    }
464    #[inline(always)]
465    pub const fn p104pfs_ha(
466        &self,
467    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
468        unsafe {
469            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
470                self._svd2pac_as_ptr().add(0x52usize),
471            )
472        }
473    }
474    #[inline(always)]
475    pub const fn p105pfs_ha(
476        &self,
477    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
478        unsafe {
479            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
480                self._svd2pac_as_ptr().add(0x56usize),
481            )
482        }
483    }
484    #[inline(always)]
485    pub const fn p106pfs_ha(
486        &self,
487    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
488        unsafe {
489            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
490                self._svd2pac_as_ptr().add(0x5ausize),
491            )
492        }
493    }
494    #[inline(always)]
495    pub const fn p107pfs_ha(
496        &self,
497    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
498        unsafe {
499            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
500                self._svd2pac_as_ptr().add(0x5eusize),
501            )
502        }
503    }
504    #[inline(always)]
505    pub const fn p108pfs_ha(
506        &self,
507    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
508        unsafe {
509            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
510                self._svd2pac_as_ptr().add(0x62usize),
511            )
512        }
513    }
514    #[inline(always)]
515    pub const fn p109pfs_ha(
516        &self,
517    ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
518        unsafe {
519            crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
520                self._svd2pac_as_ptr().add(0x66usize),
521            )
522        }
523    }
524
525    #[doc = "Port 10%s Pin Function Select Register"]
526    #[inline(always)]
527    pub const fn p10pfs_by(
528        &self,
529    ) -> &'static crate::common::ClusterRegisterArray<
530        crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW>,
531        8,
532        0x4,
533    > {
534        unsafe {
535            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4busize))
536        }
537    }
538    #[inline(always)]
539    pub const fn p102pfs_by(
540        &self,
541    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
542        unsafe {
543            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
544                self._svd2pac_as_ptr().add(0x4busize),
545            )
546        }
547    }
548    #[inline(always)]
549    pub const fn p103pfs_by(
550        &self,
551    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
552        unsafe {
553            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
554                self._svd2pac_as_ptr().add(0x4fusize),
555            )
556        }
557    }
558    #[inline(always)]
559    pub const fn p104pfs_by(
560        &self,
561    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
562        unsafe {
563            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
564                self._svd2pac_as_ptr().add(0x53usize),
565            )
566        }
567    }
568    #[inline(always)]
569    pub const fn p105pfs_by(
570        &self,
571    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
572        unsafe {
573            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
574                self._svd2pac_as_ptr().add(0x57usize),
575            )
576        }
577    }
578    #[inline(always)]
579    pub const fn p106pfs_by(
580        &self,
581    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
582        unsafe {
583            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
584                self._svd2pac_as_ptr().add(0x5busize),
585            )
586        }
587    }
588    #[inline(always)]
589    pub const fn p107pfs_by(
590        &self,
591    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
592        unsafe {
593            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
594                self._svd2pac_as_ptr().add(0x5fusize),
595            )
596        }
597    }
598    #[inline(always)]
599    pub const fn p108pfs_by(
600        &self,
601    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
602        unsafe {
603            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
604                self._svd2pac_as_ptr().add(0x63usize),
605            )
606        }
607    }
608    #[inline(always)]
609    pub const fn p109pfs_by(
610        &self,
611    ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
612        unsafe {
613            crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
614                self._svd2pac_as_ptr().add(0x67usize),
615            )
616        }
617    }
618
619    #[doc = "Port 1%s Pin Function Select Register"]
620    #[inline(always)]
621    pub const fn p1pfs(
622        &self,
623    ) -> &'static crate::common::ClusterRegisterArray<
624        crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW>,
625        4,
626        0x4,
627    > {
628        unsafe {
629            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x68usize))
630        }
631    }
632    #[inline(always)]
633    pub const fn p110pfs(
634        &self,
635    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
636        unsafe {
637            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
638                self._svd2pac_as_ptr().add(0x68usize),
639            )
640        }
641    }
642    #[inline(always)]
643    pub const fn p111pfs(
644        &self,
645    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
646        unsafe {
647            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
648                self._svd2pac_as_ptr().add(0x6cusize),
649            )
650        }
651    }
652    #[inline(always)]
653    pub const fn p112pfs(
654        &self,
655    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
656        unsafe {
657            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
658                self._svd2pac_as_ptr().add(0x70usize),
659            )
660        }
661    }
662    #[inline(always)]
663    pub const fn p113pfs(
664        &self,
665    ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
666        unsafe {
667            crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
668                self._svd2pac_as_ptr().add(0x74usize),
669            )
670        }
671    }
672
673    #[doc = "Port 1%s Pin Function Select Register"]
674    #[inline(always)]
675    pub const fn p1pfs_ha(
676        &self,
677    ) -> &'static crate::common::ClusterRegisterArray<
678        crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW>,
679        4,
680        0x4,
681    > {
682        unsafe {
683            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6ausize))
684        }
685    }
686    #[inline(always)]
687    pub const fn p110pfs_ha(
688        &self,
689    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
690        unsafe {
691            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
692                self._svd2pac_as_ptr().add(0x6ausize),
693            )
694        }
695    }
696    #[inline(always)]
697    pub const fn p111pfs_ha(
698        &self,
699    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
700        unsafe {
701            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
702                self._svd2pac_as_ptr().add(0x6eusize),
703            )
704        }
705    }
706    #[inline(always)]
707    pub const fn p112pfs_ha(
708        &self,
709    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
710        unsafe {
711            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
712                self._svd2pac_as_ptr().add(0x72usize),
713            )
714        }
715    }
716    #[inline(always)]
717    pub const fn p113pfs_ha(
718        &self,
719    ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
720        unsafe {
721            crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
722                self._svd2pac_as_ptr().add(0x76usize),
723            )
724        }
725    }
726
727    #[doc = "Port 1%s Pin Function Select Register"]
728    #[inline(always)]
729    pub const fn p1pfs_by(
730        &self,
731    ) -> &'static crate::common::ClusterRegisterArray<
732        crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW>,
733        4,
734        0x4,
735    > {
736        unsafe {
737            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6busize))
738        }
739    }
740    #[inline(always)]
741    pub const fn p110pfs_by(
742        &self,
743    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
744        unsafe {
745            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
746                self._svd2pac_as_ptr().add(0x6busize),
747            )
748        }
749    }
750    #[inline(always)]
751    pub const fn p111pfs_by(
752        &self,
753    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
754        unsafe {
755            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
756                self._svd2pac_as_ptr().add(0x6fusize),
757            )
758        }
759    }
760    #[inline(always)]
761    pub const fn p112pfs_by(
762        &self,
763    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
764        unsafe {
765            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
766                self._svd2pac_as_ptr().add(0x73usize),
767            )
768        }
769    }
770    #[inline(always)]
771    pub const fn p113pfs_by(
772        &self,
773    ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
774        unsafe {
775            crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
776                self._svd2pac_as_ptr().add(0x77usize),
777            )
778        }
779    }
780
781    #[doc = "Port 200 Pin Function Select Register"]
782    #[inline(always)]
783    pub const fn p200pfs(
784        &self,
785    ) -> &'static crate::common::Reg<self::P200Pfs_SPEC, crate::common::RW> {
786        unsafe {
787            crate::common::Reg::<self::P200Pfs_SPEC, crate::common::RW>::from_ptr(
788                self._svd2pac_as_ptr().add(128usize),
789            )
790        }
791    }
792
793    #[doc = "Port 200 Pin Function Select Register"]
794    #[inline(always)]
795    pub const fn p200pfs_ha(
796        &self,
797    ) -> &'static crate::common::Reg<self::P200PfsHa_SPEC, crate::common::RW> {
798        unsafe {
799            crate::common::Reg::<self::P200PfsHa_SPEC, crate::common::RW>::from_ptr(
800                self._svd2pac_as_ptr().add(130usize),
801            )
802        }
803    }
804
805    #[doc = "Port 200 Pin Function Select Register"]
806    #[inline(always)]
807    pub const fn p200pfs_by(
808        &self,
809    ) -> &'static crate::common::Reg<self::P200PfsBy_SPEC, crate::common::RW> {
810        unsafe {
811            crate::common::Reg::<self::P200PfsBy_SPEC, crate::common::RW>::from_ptr(
812                self._svd2pac_as_ptr().add(131usize),
813            )
814        }
815    }
816
817    #[doc = "Port 201 Pin Function Select Register"]
818    #[inline(always)]
819    pub const fn p201pfs(
820        &self,
821    ) -> &'static crate::common::Reg<self::P201Pfs_SPEC, crate::common::RW> {
822        unsafe {
823            crate::common::Reg::<self::P201Pfs_SPEC, crate::common::RW>::from_ptr(
824                self._svd2pac_as_ptr().add(132usize),
825            )
826        }
827    }
828
829    #[doc = "Port 201 Pin Function Select Register"]
830    #[inline(always)]
831    pub const fn p201pfs_ha(
832        &self,
833    ) -> &'static crate::common::Reg<self::P201PfsHa_SPEC, crate::common::RW> {
834        unsafe {
835            crate::common::Reg::<self::P201PfsHa_SPEC, crate::common::RW>::from_ptr(
836                self._svd2pac_as_ptr().add(134usize),
837            )
838        }
839    }
840
841    #[doc = "Port 201 Pin Function Select Register"]
842    #[inline(always)]
843    pub const fn p201pfs_by(
844        &self,
845    ) -> &'static crate::common::Reg<self::P201PfsBy_SPEC, crate::common::RW> {
846        unsafe {
847            crate::common::Reg::<self::P201PfsBy_SPEC, crate::common::RW>::from_ptr(
848                self._svd2pac_as_ptr().add(135usize),
849            )
850        }
851    }
852
853    #[doc = "Port 20%s Pin Function Select Register"]
854    #[inline(always)]
855    pub const fn p20pfs(
856        &self,
857    ) -> &'static crate::common::ClusterRegisterArray<
858        crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW>,
859        4,
860        0x4,
861    > {
862        unsafe {
863            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x94usize))
864        }
865    }
866    #[inline(always)]
867    pub const fn p205pfs(
868        &self,
869    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
870        unsafe {
871            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
872                self._svd2pac_as_ptr().add(0x94usize),
873            )
874        }
875    }
876    #[inline(always)]
877    pub const fn p206pfs(
878        &self,
879    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
880        unsafe {
881            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
882                self._svd2pac_as_ptr().add(0x98usize),
883            )
884        }
885    }
886    #[inline(always)]
887    pub const fn p207pfs(
888        &self,
889    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
890        unsafe {
891            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
892                self._svd2pac_as_ptr().add(0x9cusize),
893            )
894        }
895    }
896    #[inline(always)]
897    pub const fn p208pfs(
898        &self,
899    ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
900        unsafe {
901            crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
902                self._svd2pac_as_ptr().add(0xa0usize),
903            )
904        }
905    }
906
907    #[doc = "Port 20%s Pin Function Select Register"]
908    #[inline(always)]
909    pub const fn p20pfs_ha(
910        &self,
911    ) -> &'static crate::common::ClusterRegisterArray<
912        crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW>,
913        4,
914        0x4,
915    > {
916        unsafe {
917            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x96usize))
918        }
919    }
920    #[inline(always)]
921    pub const fn p205pfs_ha(
922        &self,
923    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
924        unsafe {
925            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
926                self._svd2pac_as_ptr().add(0x96usize),
927            )
928        }
929    }
930    #[inline(always)]
931    pub const fn p206pfs_ha(
932        &self,
933    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
934        unsafe {
935            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
936                self._svd2pac_as_ptr().add(0x9ausize),
937            )
938        }
939    }
940    #[inline(always)]
941    pub const fn p207pfs_ha(
942        &self,
943    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
944        unsafe {
945            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
946                self._svd2pac_as_ptr().add(0x9eusize),
947            )
948        }
949    }
950    #[inline(always)]
951    pub const fn p208pfs_ha(
952        &self,
953    ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
954        unsafe {
955            crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
956                self._svd2pac_as_ptr().add(0xa2usize),
957            )
958        }
959    }
960
961    #[doc = "Port 20%s Pin Function Select Register"]
962    #[inline(always)]
963    pub const fn p20pfs_by(
964        &self,
965    ) -> &'static crate::common::ClusterRegisterArray<
966        crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW>,
967        4,
968        0x4,
969    > {
970        unsafe {
971            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x97usize))
972        }
973    }
974    #[inline(always)]
975    pub const fn p205pfs_by(
976        &self,
977    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
978        unsafe {
979            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
980                self._svd2pac_as_ptr().add(0x97usize),
981            )
982        }
983    }
984    #[inline(always)]
985    pub const fn p206pfs_by(
986        &self,
987    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
988        unsafe {
989            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
990                self._svd2pac_as_ptr().add(0x9busize),
991            )
992        }
993    }
994    #[inline(always)]
995    pub const fn p207pfs_by(
996        &self,
997    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
998        unsafe {
999            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
1000                self._svd2pac_as_ptr().add(0x9fusize),
1001            )
1002        }
1003    }
1004    #[inline(always)]
1005    pub const fn p208pfs_by(
1006        &self,
1007    ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
1008        unsafe {
1009            crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
1010                self._svd2pac_as_ptr().add(0xa3usize),
1011            )
1012        }
1013    }
1014
1015    #[doc = "Port 2%s Pin Function Select Register"]
1016    #[inline(always)]
1017    pub const fn p2pfs(
1018        &self,
1019    ) -> &'static crate::common::ClusterRegisterArray<
1020        crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW>,
1021        2,
1022        0x4,
1023    > {
1024        unsafe {
1025            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb0usize))
1026        }
1027    }
1028    #[inline(always)]
1029    pub const fn p212pfs(
1030        &self,
1031    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1032        unsafe {
1033            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1034                self._svd2pac_as_ptr().add(0xb0usize),
1035            )
1036        }
1037    }
1038    #[inline(always)]
1039    pub const fn p213pfs(
1040        &self,
1041    ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1042        unsafe {
1043            crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1044                self._svd2pac_as_ptr().add(0xb4usize),
1045            )
1046        }
1047    }
1048
1049    #[doc = "Port 2%s Pin Function Select Register"]
1050    #[inline(always)]
1051    pub const fn p2pfs_ha(
1052        &self,
1053    ) -> &'static crate::common::ClusterRegisterArray<
1054        crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW>,
1055        2,
1056        0x4,
1057    > {
1058        unsafe {
1059            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb2usize))
1060        }
1061    }
1062    #[inline(always)]
1063    pub const fn p212pfs_ha(
1064        &self,
1065    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1066        unsafe {
1067            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1068                self._svd2pac_as_ptr().add(0xb2usize),
1069            )
1070        }
1071    }
1072    #[inline(always)]
1073    pub const fn p213pfs_ha(
1074        &self,
1075    ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1076        unsafe {
1077            crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1078                self._svd2pac_as_ptr().add(0xb6usize),
1079            )
1080        }
1081    }
1082
1083    #[doc = "Port 2%s Pin Function Select Register"]
1084    #[inline(always)]
1085    pub const fn p2pfs_by(
1086        &self,
1087    ) -> &'static crate::common::ClusterRegisterArray<
1088        crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW>,
1089        2,
1090        0x4,
1091    > {
1092        unsafe {
1093            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb3usize))
1094        }
1095    }
1096    #[inline(always)]
1097    pub const fn p212pfs_by(
1098        &self,
1099    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1100        unsafe {
1101            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1102                self._svd2pac_as_ptr().add(0xb3usize),
1103            )
1104        }
1105    }
1106    #[inline(always)]
1107    pub const fn p213pfs_by(
1108        &self,
1109    ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1110        unsafe {
1111            crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1112                self._svd2pac_as_ptr().add(0xb7usize),
1113            )
1114        }
1115    }
1116
1117    #[doc = "Port 300 Pin Function Select Register"]
1118    #[inline(always)]
1119    pub const fn p300pfs(
1120        &self,
1121    ) -> &'static crate::common::Reg<self::P300Pfs_SPEC, crate::common::RW> {
1122        unsafe {
1123            crate::common::Reg::<self::P300Pfs_SPEC, crate::common::RW>::from_ptr(
1124                self._svd2pac_as_ptr().add(192usize),
1125            )
1126        }
1127    }
1128
1129    #[doc = "Port 300 Pin Function Select Register"]
1130    #[inline(always)]
1131    pub const fn p300pfs_ha(
1132        &self,
1133    ) -> &'static crate::common::Reg<self::P300PfsHa_SPEC, crate::common::RW> {
1134        unsafe {
1135            crate::common::Reg::<self::P300PfsHa_SPEC, crate::common::RW>::from_ptr(
1136                self._svd2pac_as_ptr().add(194usize),
1137            )
1138        }
1139    }
1140
1141    #[doc = "Port 300 Pin Function Select Register"]
1142    #[inline(always)]
1143    pub const fn p300pfs_by(
1144        &self,
1145    ) -> &'static crate::common::Reg<self::P300PfsBy_SPEC, crate::common::RW> {
1146        unsafe {
1147            crate::common::Reg::<self::P300PfsBy_SPEC, crate::common::RW>::from_ptr(
1148                self._svd2pac_as_ptr().add(195usize),
1149            )
1150        }
1151    }
1152
1153    #[doc = "Port 30%s Pin Function Select Register"]
1154    #[inline(always)]
1155    pub const fn p30pfs(
1156        &self,
1157    ) -> &'static crate::common::ClusterRegisterArray<
1158        crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW>,
1159        4,
1160        0x4,
1161    > {
1162        unsafe {
1163            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc4usize))
1164        }
1165    }
1166    #[inline(always)]
1167    pub const fn p301pfs(
1168        &self,
1169    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1170        unsafe {
1171            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1172                self._svd2pac_as_ptr().add(0xc4usize),
1173            )
1174        }
1175    }
1176    #[inline(always)]
1177    pub const fn p302pfs(
1178        &self,
1179    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1180        unsafe {
1181            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1182                self._svd2pac_as_ptr().add(0xc8usize),
1183            )
1184        }
1185    }
1186    #[inline(always)]
1187    pub const fn p303pfs(
1188        &self,
1189    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1190        unsafe {
1191            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1192                self._svd2pac_as_ptr().add(0xccusize),
1193            )
1194        }
1195    }
1196    #[inline(always)]
1197    pub const fn p304pfs(
1198        &self,
1199    ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1200        unsafe {
1201            crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1202                self._svd2pac_as_ptr().add(0xd0usize),
1203            )
1204        }
1205    }
1206
1207    #[doc = "Port 30%s Pin Function Select Register"]
1208    #[inline(always)]
1209    pub const fn p30pfs_ha(
1210        &self,
1211    ) -> &'static crate::common::ClusterRegisterArray<
1212        crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW>,
1213        4,
1214        0x4,
1215    > {
1216        unsafe {
1217            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc6usize))
1218        }
1219    }
1220    #[inline(always)]
1221    pub const fn p301pfs_ha(
1222        &self,
1223    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1224        unsafe {
1225            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1226                self._svd2pac_as_ptr().add(0xc6usize),
1227            )
1228        }
1229    }
1230    #[inline(always)]
1231    pub const fn p302pfs_ha(
1232        &self,
1233    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1234        unsafe {
1235            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1236                self._svd2pac_as_ptr().add(0xcausize),
1237            )
1238        }
1239    }
1240    #[inline(always)]
1241    pub const fn p303pfs_ha(
1242        &self,
1243    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1244        unsafe {
1245            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1246                self._svd2pac_as_ptr().add(0xceusize),
1247            )
1248        }
1249    }
1250    #[inline(always)]
1251    pub const fn p304pfs_ha(
1252        &self,
1253    ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1254        unsafe {
1255            crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1256                self._svd2pac_as_ptr().add(0xd2usize),
1257            )
1258        }
1259    }
1260
1261    #[doc = "Port 30%s Pin Function Select Register"]
1262    #[inline(always)]
1263    pub const fn p30pfs_by(
1264        &self,
1265    ) -> &'static crate::common::ClusterRegisterArray<
1266        crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW>,
1267        4,
1268        0x4,
1269    > {
1270        unsafe {
1271            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc7usize))
1272        }
1273    }
1274    #[inline(always)]
1275    pub const fn p301pfs_by(
1276        &self,
1277    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1278        unsafe {
1279            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1280                self._svd2pac_as_ptr().add(0xc7usize),
1281            )
1282        }
1283    }
1284    #[inline(always)]
1285    pub const fn p302pfs_by(
1286        &self,
1287    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1288        unsafe {
1289            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1290                self._svd2pac_as_ptr().add(0xcbusize),
1291            )
1292        }
1293    }
1294    #[inline(always)]
1295    pub const fn p303pfs_by(
1296        &self,
1297    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1298        unsafe {
1299            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1300                self._svd2pac_as_ptr().add(0xcfusize),
1301            )
1302        }
1303    }
1304    #[inline(always)]
1305    pub const fn p304pfs_by(
1306        &self,
1307    ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1308        unsafe {
1309            crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1310                self._svd2pac_as_ptr().add(0xd3usize),
1311            )
1312        }
1313    }
1314
1315    #[doc = "Port 40%s Pin Function Select Register"]
1316    #[inline(always)]
1317    pub const fn p40pfs(
1318        &self,
1319    ) -> &'static crate::common::ClusterRegisterArray<
1320        crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW>,
1321        3,
1322        0x4,
1323    > {
1324        unsafe {
1325            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11cusize))
1326        }
1327    }
1328    #[inline(always)]
1329    pub const fn p407pfs(
1330        &self,
1331    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1332        unsafe {
1333            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1334                self._svd2pac_as_ptr().add(0x11cusize),
1335            )
1336        }
1337    }
1338    #[inline(always)]
1339    pub const fn p408pfs(
1340        &self,
1341    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1342        unsafe {
1343            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1344                self._svd2pac_as_ptr().add(0x120usize),
1345            )
1346        }
1347    }
1348    #[inline(always)]
1349    pub const fn p409pfs(
1350        &self,
1351    ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1352        unsafe {
1353            crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1354                self._svd2pac_as_ptr().add(0x124usize),
1355            )
1356        }
1357    }
1358
1359    #[doc = "Port 40%s Pin Function Select Register"]
1360    #[inline(always)]
1361    pub const fn p40pfs_ha(
1362        &self,
1363    ) -> &'static crate::common::ClusterRegisterArray<
1364        crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW>,
1365        3,
1366        0x4,
1367    > {
1368        unsafe {
1369            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11eusize))
1370        }
1371    }
1372    #[inline(always)]
1373    pub const fn p407pfs_ha(
1374        &self,
1375    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1376        unsafe {
1377            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1378                self._svd2pac_as_ptr().add(0x11eusize),
1379            )
1380        }
1381    }
1382    #[inline(always)]
1383    pub const fn p408pfs_ha(
1384        &self,
1385    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1386        unsafe {
1387            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1388                self._svd2pac_as_ptr().add(0x122usize),
1389            )
1390        }
1391    }
1392    #[inline(always)]
1393    pub const fn p409pfs_ha(
1394        &self,
1395    ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1396        unsafe {
1397            crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1398                self._svd2pac_as_ptr().add(0x126usize),
1399            )
1400        }
1401    }
1402
1403    #[doc = "Port 40%s Pin Function Select Register"]
1404    #[inline(always)]
1405    pub const fn p40pfs_by(
1406        &self,
1407    ) -> &'static crate::common::ClusterRegisterArray<
1408        crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW>,
1409        3,
1410        0x4,
1411    > {
1412        unsafe {
1413            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x11fusize))
1414        }
1415    }
1416    #[inline(always)]
1417    pub const fn p407pfs_by(
1418        &self,
1419    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1420        unsafe {
1421            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1422                self._svd2pac_as_ptr().add(0x11fusize),
1423            )
1424        }
1425    }
1426    #[inline(always)]
1427    pub const fn p408pfs_by(
1428        &self,
1429    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1430        unsafe {
1431            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1432                self._svd2pac_as_ptr().add(0x123usize),
1433            )
1434        }
1435    }
1436    #[inline(always)]
1437    pub const fn p409pfs_by(
1438        &self,
1439    ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1440        unsafe {
1441            crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1442                self._svd2pac_as_ptr().add(0x127usize),
1443            )
1444        }
1445    }
1446
1447    #[doc = "Port 4%s Pin Function Select Register"]
1448    #[inline(always)]
1449    pub const fn p4pfs(
1450        &self,
1451    ) -> &'static crate::common::ClusterRegisterArray<
1452        crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW>,
1453        2,
1454        0x4,
1455    > {
1456        unsafe {
1457            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x128usize))
1458        }
1459    }
1460    #[inline(always)]
1461    pub const fn p410pfs(
1462        &self,
1463    ) -> &'static crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW> {
1464        unsafe {
1465            crate::common::Reg::<self::P4Pfs_SPEC, crate::common::RW>::from_ptr(
1466                self._svd2pac_as_ptr().add(0x128usize),
1467            )
1468        }
1469    }
1470    #[inline(always)]
1471    pub const fn p411pfs(
1472        &self,
1473    ) -> &'static crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW> {
1474        unsafe {
1475            crate::common::Reg::<self::P4Pfs_SPEC, crate::common::RW>::from_ptr(
1476                self._svd2pac_as_ptr().add(0x12cusize),
1477            )
1478        }
1479    }
1480
1481    #[doc = "Port 4%s Pin Function Select Register"]
1482    #[inline(always)]
1483    pub const fn p4pfs_ha(
1484        &self,
1485    ) -> &'static crate::common::ClusterRegisterArray<
1486        crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW>,
1487        2,
1488        0x4,
1489    > {
1490        unsafe {
1491            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12ausize))
1492        }
1493    }
1494    #[inline(always)]
1495    pub const fn p410pfs_ha(
1496        &self,
1497    ) -> &'static crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW> {
1498        unsafe {
1499            crate::common::Reg::<self::P4PfsHa_SPEC, crate::common::RW>::from_ptr(
1500                self._svd2pac_as_ptr().add(0x12ausize),
1501            )
1502        }
1503    }
1504    #[inline(always)]
1505    pub const fn p411pfs_ha(
1506        &self,
1507    ) -> &'static crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW> {
1508        unsafe {
1509            crate::common::Reg::<self::P4PfsHa_SPEC, crate::common::RW>::from_ptr(
1510                self._svd2pac_as_ptr().add(0x12eusize),
1511            )
1512        }
1513    }
1514
1515    #[doc = "Port 4%s Pin Function Select Register"]
1516    #[inline(always)]
1517    pub const fn p4pfs_by(
1518        &self,
1519    ) -> &'static crate::common::ClusterRegisterArray<
1520        crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW>,
1521        2,
1522        0x4,
1523    > {
1524        unsafe {
1525            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12busize))
1526        }
1527    }
1528    #[inline(always)]
1529    pub const fn p410pfs_by(
1530        &self,
1531    ) -> &'static crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW> {
1532        unsafe {
1533            crate::common::Reg::<self::P4PfsBy_SPEC, crate::common::RW>::from_ptr(
1534                self._svd2pac_as_ptr().add(0x12busize),
1535            )
1536        }
1537    }
1538    #[inline(always)]
1539    pub const fn p411pfs_by(
1540        &self,
1541    ) -> &'static crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW> {
1542        unsafe {
1543            crate::common::Reg::<self::P4PfsBy_SPEC, crate::common::RW>::from_ptr(
1544                self._svd2pac_as_ptr().add(0x12fusize),
1545            )
1546        }
1547    }
1548
1549    #[doc = "Port 500 Pin Function Select Register"]
1550    #[inline(always)]
1551    pub const fn p500pfs(
1552        &self,
1553    ) -> &'static crate::common::Reg<self::P500Pfs_SPEC, crate::common::RW> {
1554        unsafe {
1555            crate::common::Reg::<self::P500Pfs_SPEC, crate::common::RW>::from_ptr(
1556                self._svd2pac_as_ptr().add(320usize),
1557            )
1558        }
1559    }
1560
1561    #[doc = "Port 500 Pin Function Select Register"]
1562    #[inline(always)]
1563    pub const fn p500pfs_ha(
1564        &self,
1565    ) -> &'static crate::common::Reg<self::P500PfsHa_SPEC, crate::common::RW> {
1566        unsafe {
1567            crate::common::Reg::<self::P500PfsHa_SPEC, crate::common::RW>::from_ptr(
1568                self._svd2pac_as_ptr().add(322usize),
1569            )
1570        }
1571    }
1572
1573    #[doc = "Port 500 Pin Function Select Register"]
1574    #[inline(always)]
1575    pub const fn p500pfs_by(
1576        &self,
1577    ) -> &'static crate::common::Reg<self::P500PfsBy_SPEC, crate::common::RW> {
1578        unsafe {
1579            crate::common::Reg::<self::P500PfsBy_SPEC, crate::common::RW>::from_ptr(
1580                self._svd2pac_as_ptr().add(323usize),
1581            )
1582        }
1583    }
1584
1585    #[doc = "Port 80%s Pin Function Select Register"]
1586    #[inline(always)]
1587    pub const fn p80pfs(
1588        &self,
1589    ) -> &'static crate::common::ClusterRegisterArray<
1590        crate::common::Reg<self::P80Pfs_SPEC, crate::common::RW>,
1591        2,
1592        0x4,
1593    > {
1594        unsafe {
1595            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x238usize))
1596        }
1597    }
1598    #[inline(always)]
1599    pub const fn p8014pfs(
1600        &self,
1601    ) -> &'static crate::common::Reg<self::P80Pfs_SPEC, crate::common::RW> {
1602        unsafe {
1603            crate::common::Reg::<self::P80Pfs_SPEC, crate::common::RW>::from_ptr(
1604                self._svd2pac_as_ptr().add(0x238usize),
1605            )
1606        }
1607    }
1608    #[inline(always)]
1609    pub const fn p8015pfs(
1610        &self,
1611    ) -> &'static crate::common::Reg<self::P80Pfs_SPEC, crate::common::RW> {
1612        unsafe {
1613            crate::common::Reg::<self::P80Pfs_SPEC, crate::common::RW>::from_ptr(
1614                self._svd2pac_as_ptr().add(0x23cusize),
1615            )
1616        }
1617    }
1618
1619    #[doc = "Port 80%s Pin Function Select Register"]
1620    #[inline(always)]
1621    pub const fn p80pfs_ha(
1622        &self,
1623    ) -> &'static crate::common::ClusterRegisterArray<
1624        crate::common::Reg<self::P80PfsHa_SPEC, crate::common::RW>,
1625        2,
1626        0x4,
1627    > {
1628        unsafe {
1629            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x23ausize))
1630        }
1631    }
1632    #[inline(always)]
1633    pub const fn p8014pfs_ha(
1634        &self,
1635    ) -> &'static crate::common::Reg<self::P80PfsHa_SPEC, crate::common::RW> {
1636        unsafe {
1637            crate::common::Reg::<self::P80PfsHa_SPEC, crate::common::RW>::from_ptr(
1638                self._svd2pac_as_ptr().add(0x23ausize),
1639            )
1640        }
1641    }
1642    #[inline(always)]
1643    pub const fn p8015pfs_ha(
1644        &self,
1645    ) -> &'static crate::common::Reg<self::P80PfsHa_SPEC, crate::common::RW> {
1646        unsafe {
1647            crate::common::Reg::<self::P80PfsHa_SPEC, crate::common::RW>::from_ptr(
1648                self._svd2pac_as_ptr().add(0x23eusize),
1649            )
1650        }
1651    }
1652
1653    #[doc = "Port 80%s Pin Function Select Register"]
1654    #[inline(always)]
1655    pub const fn p80pfs_by(
1656        &self,
1657    ) -> &'static crate::common::ClusterRegisterArray<
1658        crate::common::Reg<self::P80PfsBy_SPEC, crate::common::RW>,
1659        2,
1660        0x4,
1661    > {
1662        unsafe {
1663            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x23busize))
1664        }
1665    }
1666    #[inline(always)]
1667    pub const fn p8014pfs_by(
1668        &self,
1669    ) -> &'static crate::common::Reg<self::P80PfsBy_SPEC, crate::common::RW> {
1670        unsafe {
1671            crate::common::Reg::<self::P80PfsBy_SPEC, crate::common::RW>::from_ptr(
1672                self._svd2pac_as_ptr().add(0x23busize),
1673            )
1674        }
1675    }
1676    #[inline(always)]
1677    pub const fn p8015pfs_by(
1678        &self,
1679    ) -> &'static crate::common::Reg<self::P80PfsBy_SPEC, crate::common::RW> {
1680        unsafe {
1681            crate::common::Reg::<self::P80PfsBy_SPEC, crate::common::RW>::from_ptr(
1682                self._svd2pac_as_ptr().add(0x23fusize),
1683            )
1684        }
1685    }
1686
1687    #[doc = "Write-Protect Register"]
1688    #[inline(always)]
1689    pub const fn pwpr(&self) -> &'static crate::common::Reg<self::Pwpr_SPEC, crate::common::RW> {
1690        unsafe {
1691            crate::common::Reg::<self::Pwpr_SPEC, crate::common::RW>::from_ptr(
1692                self._svd2pac_as_ptr().add(1283usize),
1693            )
1694        }
1695    }
1696
1697    #[doc = "Write-Protect Register for Secure"]
1698    #[inline(always)]
1699    pub const fn pwprs(&self) -> &'static crate::common::Reg<self::Pwprs_SPEC, crate::common::RW> {
1700        unsafe {
1701            crate::common::Reg::<self::Pwprs_SPEC, crate::common::RW>::from_ptr(
1702                self._svd2pac_as_ptr().add(1285usize),
1703            )
1704        }
1705    }
1706
1707    #[doc = "RI3C Slope Control Register"]
1708    #[inline(always)]
1709    pub const fn pfi3c(&self) -> &'static crate::common::Reg<self::Pfi3C_SPEC, crate::common::RW> {
1710        unsafe {
1711            crate::common::Reg::<self::Pfi3C_SPEC, crate::common::RW>::from_ptr(
1712                self._svd2pac_as_ptr().add(1292usize),
1713            )
1714        }
1715    }
1716
1717    #[doc = "Port Security Attribution register"]
1718    #[inline(always)]
1719    pub const fn psar(
1720        &self,
1721    ) -> &'static crate::common::ClusterRegisterArray<
1722        crate::common::Reg<self::Psar_SPEC, crate::common::RW>,
1723        6,
1724        0x2,
1725    > {
1726        unsafe {
1727            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x510usize))
1728        }
1729    }
1730    #[inline(always)]
1731    pub const fn p0sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1732        unsafe {
1733            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1734                self._svd2pac_as_ptr().add(0x510usize),
1735            )
1736        }
1737    }
1738    #[inline(always)]
1739    pub const fn p1sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1740        unsafe {
1741            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1742                self._svd2pac_as_ptr().add(0x512usize),
1743            )
1744        }
1745    }
1746    #[inline(always)]
1747    pub const fn p2sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1748        unsafe {
1749            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1750                self._svd2pac_as_ptr().add(0x514usize),
1751            )
1752        }
1753    }
1754    #[inline(always)]
1755    pub const fn p3sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1756        unsafe {
1757            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1758                self._svd2pac_as_ptr().add(0x516usize),
1759            )
1760        }
1761    }
1762    #[inline(always)]
1763    pub const fn p4sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1764        unsafe {
1765            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1766                self._svd2pac_as_ptr().add(0x518usize),
1767            )
1768        }
1769    }
1770    #[inline(always)]
1771    pub const fn p5sar(&self) -> &'static crate::common::Reg<self::Psar_SPEC, crate::common::RW> {
1772        unsafe {
1773            crate::common::Reg::<self::Psar_SPEC, crate::common::RW>::from_ptr(
1774                self._svd2pac_as_ptr().add(0x51ausize),
1775            )
1776        }
1777    }
1778
1779    #[doc = "Port Security Attribution register"]
1780    #[inline(always)]
1781    pub const fn p8sar(&self) -> &'static crate::common::Reg<self::P8Sar_SPEC, crate::common::RW> {
1782        unsafe {
1783            crate::common::Reg::<self::P8Sar_SPEC, crate::common::RW>::from_ptr(
1784                self._svd2pac_as_ptr().add(1312usize),
1785            )
1786        }
1787    }
1788}
1789#[doc(hidden)]
1790#[derive(Copy, Clone, Eq, PartialEq)]
1791pub struct P00Pfs_SPEC;
1792impl crate::sealed::RegSpec for P00Pfs_SPEC {
1793    type DataType = u32;
1794}
1795
1796#[doc = "Port 00%s Pin Function Select Register"]
1797pub type P00Pfs = crate::RegValueT<P00Pfs_SPEC>;
1798
1799impl P00Pfs {
1800    #[doc = "Port Output Data"]
1801    #[inline(always)]
1802    pub fn podr(
1803        self,
1804    ) -> crate::common::RegisterField<
1805        0,
1806        0x1,
1807        1,
1808        0,
1809        p00pfs::Podr,
1810        p00pfs::Podr,
1811        P00Pfs_SPEC,
1812        crate::common::RW,
1813    > {
1814        crate::common::RegisterField::<
1815            0,
1816            0x1,
1817            1,
1818            0,
1819            p00pfs::Podr,
1820            p00pfs::Podr,
1821            P00Pfs_SPEC,
1822            crate::common::RW,
1823        >::from_register(self, 0)
1824    }
1825
1826    #[doc = "Port State"]
1827    #[inline(always)]
1828    pub fn pidr(
1829        self,
1830    ) -> crate::common::RegisterField<
1831        1,
1832        0x1,
1833        1,
1834        0,
1835        p00pfs::Pidr,
1836        p00pfs::Pidr,
1837        P00Pfs_SPEC,
1838        crate::common::R,
1839    > {
1840        crate::common::RegisterField::<
1841            1,
1842            0x1,
1843            1,
1844            0,
1845            p00pfs::Pidr,
1846            p00pfs::Pidr,
1847            P00Pfs_SPEC,
1848            crate::common::R,
1849        >::from_register(self, 0)
1850    }
1851
1852    #[doc = "Port Direction"]
1853    #[inline(always)]
1854    pub fn pdr(
1855        self,
1856    ) -> crate::common::RegisterField<
1857        2,
1858        0x1,
1859        1,
1860        0,
1861        p00pfs::Pdr,
1862        p00pfs::Pdr,
1863        P00Pfs_SPEC,
1864        crate::common::RW,
1865    > {
1866        crate::common::RegisterField::<
1867            2,
1868            0x1,
1869            1,
1870            0,
1871            p00pfs::Pdr,
1872            p00pfs::Pdr,
1873            P00Pfs_SPEC,
1874            crate::common::RW,
1875        >::from_register(self, 0)
1876    }
1877
1878    #[doc = "Pull-up Control"]
1879    #[inline(always)]
1880    pub fn pcr(
1881        self,
1882    ) -> crate::common::RegisterField<
1883        4,
1884        0x1,
1885        1,
1886        0,
1887        p00pfs::Pcr,
1888        p00pfs::Pcr,
1889        P00Pfs_SPEC,
1890        crate::common::RW,
1891    > {
1892        crate::common::RegisterField::<
1893            4,
1894            0x1,
1895            1,
1896            0,
1897            p00pfs::Pcr,
1898            p00pfs::Pcr,
1899            P00Pfs_SPEC,
1900            crate::common::RW,
1901        >::from_register(self, 0)
1902    }
1903
1904    #[doc = "N-Channel Open-Drain Control"]
1905    #[inline(always)]
1906    pub fn ncodr(
1907        self,
1908    ) -> crate::common::RegisterField<
1909        6,
1910        0x1,
1911        1,
1912        0,
1913        p00pfs::Ncodr,
1914        p00pfs::Ncodr,
1915        P00Pfs_SPEC,
1916        crate::common::RW,
1917    > {
1918        crate::common::RegisterField::<
1919            6,
1920            0x1,
1921            1,
1922            0,
1923            p00pfs::Ncodr,
1924            p00pfs::Ncodr,
1925            P00Pfs_SPEC,
1926            crate::common::RW,
1927        >::from_register(self, 0)
1928    }
1929
1930    #[doc = "Port Drive Capability"]
1931    #[inline(always)]
1932    pub fn dscr(
1933        self,
1934    ) -> crate::common::RegisterField<
1935        10,
1936        0x3,
1937        1,
1938        0,
1939        p00pfs::Dscr,
1940        p00pfs::Dscr,
1941        P00Pfs_SPEC,
1942        crate::common::RW,
1943    > {
1944        crate::common::RegisterField::<
1945            10,
1946            0x3,
1947            1,
1948            0,
1949            p00pfs::Dscr,
1950            p00pfs::Dscr,
1951            P00Pfs_SPEC,
1952            crate::common::RW,
1953        >::from_register(self, 0)
1954    }
1955
1956    #[doc = "Event on Falling/Event on Rising"]
1957    #[inline(always)]
1958    pub fn eofr(
1959        self,
1960    ) -> crate::common::RegisterField<
1961        12,
1962        0x3,
1963        1,
1964        0,
1965        p00pfs::Eofr,
1966        p00pfs::Eofr,
1967        P00Pfs_SPEC,
1968        crate::common::RW,
1969    > {
1970        crate::common::RegisterField::<
1971            12,
1972            0x3,
1973            1,
1974            0,
1975            p00pfs::Eofr,
1976            p00pfs::Eofr,
1977            P00Pfs_SPEC,
1978            crate::common::RW,
1979        >::from_register(self, 0)
1980    }
1981
1982    #[doc = "IRQ Input Enable"]
1983    #[inline(always)]
1984    pub fn isel(
1985        self,
1986    ) -> crate::common::RegisterField<
1987        14,
1988        0x1,
1989        1,
1990        0,
1991        p00pfs::Isel,
1992        p00pfs::Isel,
1993        P00Pfs_SPEC,
1994        crate::common::RW,
1995    > {
1996        crate::common::RegisterField::<
1997            14,
1998            0x1,
1999            1,
2000            0,
2001            p00pfs::Isel,
2002            p00pfs::Isel,
2003            P00Pfs_SPEC,
2004            crate::common::RW,
2005        >::from_register(self, 0)
2006    }
2007
2008    #[doc = "Analog Input Enable"]
2009    #[inline(always)]
2010    pub fn asel(
2011        self,
2012    ) -> crate::common::RegisterField<
2013        15,
2014        0x1,
2015        1,
2016        0,
2017        p00pfs::Asel,
2018        p00pfs::Asel,
2019        P00Pfs_SPEC,
2020        crate::common::RW,
2021    > {
2022        crate::common::RegisterField::<
2023            15,
2024            0x1,
2025            1,
2026            0,
2027            p00pfs::Asel,
2028            p00pfs::Asel,
2029            P00Pfs_SPEC,
2030            crate::common::RW,
2031        >::from_register(self, 0)
2032    }
2033
2034    #[doc = "Port Mode Control"]
2035    #[inline(always)]
2036    pub fn pmr(
2037        self,
2038    ) -> crate::common::RegisterField<
2039        16,
2040        0x1,
2041        1,
2042        0,
2043        p00pfs::Pmr,
2044        p00pfs::Pmr,
2045        P00Pfs_SPEC,
2046        crate::common::RW,
2047    > {
2048        crate::common::RegisterField::<
2049            16,
2050            0x1,
2051            1,
2052            0,
2053            p00pfs::Pmr,
2054            p00pfs::Pmr,
2055            P00Pfs_SPEC,
2056            crate::common::RW,
2057        >::from_register(self, 0)
2058    }
2059
2060    #[doc = "Peripheral Select"]
2061    #[inline(always)]
2062    pub fn psel(
2063        self,
2064    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P00Pfs_SPEC, crate::common::RW> {
2065        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P00Pfs_SPEC,crate::common::RW>::from_register(self,0)
2066    }
2067}
2068impl ::core::default::Default for P00Pfs {
2069    #[inline(always)]
2070    fn default() -> P00Pfs {
2071        <crate::RegValueT<P00Pfs_SPEC> as RegisterValue<_>>::new(0)
2072    }
2073}
2074pub mod p00pfs {
2075
2076    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2077    pub struct Podr_SPEC;
2078    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2079    impl Podr {
2080        #[doc = "Output low"]
2081        pub const _0: Self = Self::new(0);
2082
2083        #[doc = "Output high"]
2084        pub const _1: Self = Self::new(1);
2085    }
2086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2087    pub struct Pidr_SPEC;
2088    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2089    impl Pidr {
2090        #[doc = "Low level"]
2091        pub const _0: Self = Self::new(0);
2092
2093        #[doc = "High level"]
2094        pub const _1: Self = Self::new(1);
2095    }
2096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2097    pub struct Pdr_SPEC;
2098    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2099    impl Pdr {
2100        #[doc = "Input (functions as an input pin)"]
2101        pub const _0: Self = Self::new(0);
2102
2103        #[doc = "Output (functions as an output pin)"]
2104        pub const _1: Self = Self::new(1);
2105    }
2106    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2107    pub struct Pcr_SPEC;
2108    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2109    impl Pcr {
2110        #[doc = "Disable input pull-up"]
2111        pub const _0: Self = Self::new(0);
2112
2113        #[doc = "Enable input pull-up"]
2114        pub const _1: Self = Self::new(1);
2115    }
2116    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2117    pub struct Ncodr_SPEC;
2118    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2119    impl Ncodr {
2120        #[doc = "Output CMOS"]
2121        pub const _0: Self = Self::new(0);
2122
2123        #[doc = "Output NMOS open-drain"]
2124        pub const _1: Self = Self::new(1);
2125    }
2126    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2127    pub struct Dscr_SPEC;
2128    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
2129    impl Dscr {
2130        #[doc = "Low drive"]
2131        pub const _00: Self = Self::new(0);
2132
2133        #[doc = "Middle drive"]
2134        pub const _01: Self = Self::new(1);
2135
2136        #[doc = "Setting prohibited"]
2137        pub const _10: Self = Self::new(2);
2138
2139        #[doc = "High drive"]
2140        pub const _11: Self = Self::new(3);
2141    }
2142    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2143    pub struct Eofr_SPEC;
2144    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
2145    impl Eofr {
2146        #[doc = "Don\'t care"]
2147        pub const _00: Self = Self::new(0);
2148
2149        #[doc = "Detect rising edge"]
2150        pub const _01: Self = Self::new(1);
2151
2152        #[doc = "Detect falling edge"]
2153        pub const _10: Self = Self::new(2);
2154
2155        #[doc = "Detect both edges"]
2156        pub const _11: Self = Self::new(3);
2157    }
2158    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2159    pub struct Isel_SPEC;
2160    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2161    impl Isel {
2162        #[doc = "Do not use as IRQn input pin"]
2163        pub const _0: Self = Self::new(0);
2164
2165        #[doc = "Use as IRQn input pin"]
2166        pub const _1: Self = Self::new(1);
2167    }
2168    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2169    pub struct Asel_SPEC;
2170    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2171    impl Asel {
2172        #[doc = "Do not use as analog pin"]
2173        pub const _0: Self = Self::new(0);
2174
2175        #[doc = "Use as analog pin"]
2176        pub const _1: Self = Self::new(1);
2177    }
2178    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2179    pub struct Pmr_SPEC;
2180    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
2181    impl Pmr {
2182        #[doc = "Use as general I/O pin"]
2183        pub const _0: Self = Self::new(0);
2184
2185        #[doc = "Use as I/O port for peripheral functions"]
2186        pub const _1: Self = Self::new(1);
2187    }
2188}
2189#[doc(hidden)]
2190#[derive(Copy, Clone, Eq, PartialEq)]
2191pub struct P00PfsHa_SPEC;
2192impl crate::sealed::RegSpec for P00PfsHa_SPEC {
2193    type DataType = u16;
2194}
2195
2196#[doc = "Port 00%s Pin Function Select Register"]
2197pub type P00PfsHa = crate::RegValueT<P00PfsHa_SPEC>;
2198
2199impl P00PfsHa {
2200    #[doc = "Port Output Data"]
2201    #[inline(always)]
2202    pub fn podr(
2203        self,
2204    ) -> crate::common::RegisterField<
2205        0,
2206        0x1,
2207        1,
2208        0,
2209        p00pfs_ha::Podr,
2210        p00pfs_ha::Podr,
2211        P00PfsHa_SPEC,
2212        crate::common::RW,
2213    > {
2214        crate::common::RegisterField::<
2215            0,
2216            0x1,
2217            1,
2218            0,
2219            p00pfs_ha::Podr,
2220            p00pfs_ha::Podr,
2221            P00PfsHa_SPEC,
2222            crate::common::RW,
2223        >::from_register(self, 0)
2224    }
2225
2226    #[doc = "Port State"]
2227    #[inline(always)]
2228    pub fn pidr(
2229        self,
2230    ) -> crate::common::RegisterField<
2231        1,
2232        0x1,
2233        1,
2234        0,
2235        p00pfs_ha::Pidr,
2236        p00pfs_ha::Pidr,
2237        P00PfsHa_SPEC,
2238        crate::common::R,
2239    > {
2240        crate::common::RegisterField::<
2241            1,
2242            0x1,
2243            1,
2244            0,
2245            p00pfs_ha::Pidr,
2246            p00pfs_ha::Pidr,
2247            P00PfsHa_SPEC,
2248            crate::common::R,
2249        >::from_register(self, 0)
2250    }
2251
2252    #[doc = "Port Direction"]
2253    #[inline(always)]
2254    pub fn pdr(
2255        self,
2256    ) -> crate::common::RegisterField<
2257        2,
2258        0x1,
2259        1,
2260        0,
2261        p00pfs_ha::Pdr,
2262        p00pfs_ha::Pdr,
2263        P00PfsHa_SPEC,
2264        crate::common::RW,
2265    > {
2266        crate::common::RegisterField::<
2267            2,
2268            0x1,
2269            1,
2270            0,
2271            p00pfs_ha::Pdr,
2272            p00pfs_ha::Pdr,
2273            P00PfsHa_SPEC,
2274            crate::common::RW,
2275        >::from_register(self, 0)
2276    }
2277
2278    #[doc = "Pull-up Control"]
2279    #[inline(always)]
2280    pub fn pcr(
2281        self,
2282    ) -> crate::common::RegisterField<
2283        4,
2284        0x1,
2285        1,
2286        0,
2287        p00pfs_ha::Pcr,
2288        p00pfs_ha::Pcr,
2289        P00PfsHa_SPEC,
2290        crate::common::RW,
2291    > {
2292        crate::common::RegisterField::<
2293            4,
2294            0x1,
2295            1,
2296            0,
2297            p00pfs_ha::Pcr,
2298            p00pfs_ha::Pcr,
2299            P00PfsHa_SPEC,
2300            crate::common::RW,
2301        >::from_register(self, 0)
2302    }
2303
2304    #[doc = "N-Channel Open-Drain Control"]
2305    #[inline(always)]
2306    pub fn ncodr(
2307        self,
2308    ) -> crate::common::RegisterField<
2309        6,
2310        0x1,
2311        1,
2312        0,
2313        p00pfs_ha::Ncodr,
2314        p00pfs_ha::Ncodr,
2315        P00PfsHa_SPEC,
2316        crate::common::RW,
2317    > {
2318        crate::common::RegisterField::<
2319            6,
2320            0x1,
2321            1,
2322            0,
2323            p00pfs_ha::Ncodr,
2324            p00pfs_ha::Ncodr,
2325            P00PfsHa_SPEC,
2326            crate::common::RW,
2327        >::from_register(self, 0)
2328    }
2329
2330    #[doc = "Port Drive Capability"]
2331    #[inline(always)]
2332    pub fn dscr(
2333        self,
2334    ) -> crate::common::RegisterField<
2335        10,
2336        0x3,
2337        1,
2338        0,
2339        p00pfs_ha::Dscr,
2340        p00pfs_ha::Dscr,
2341        P00PfsHa_SPEC,
2342        crate::common::RW,
2343    > {
2344        crate::common::RegisterField::<
2345            10,
2346            0x3,
2347            1,
2348            0,
2349            p00pfs_ha::Dscr,
2350            p00pfs_ha::Dscr,
2351            P00PfsHa_SPEC,
2352            crate::common::RW,
2353        >::from_register(self, 0)
2354    }
2355
2356    #[doc = "Event on Falling/Event on Rising"]
2357    #[inline(always)]
2358    pub fn eofr(
2359        self,
2360    ) -> crate::common::RegisterField<
2361        12,
2362        0x3,
2363        1,
2364        0,
2365        p00pfs_ha::Eofr,
2366        p00pfs_ha::Eofr,
2367        P00PfsHa_SPEC,
2368        crate::common::RW,
2369    > {
2370        crate::common::RegisterField::<
2371            12,
2372            0x3,
2373            1,
2374            0,
2375            p00pfs_ha::Eofr,
2376            p00pfs_ha::Eofr,
2377            P00PfsHa_SPEC,
2378            crate::common::RW,
2379        >::from_register(self, 0)
2380    }
2381
2382    #[doc = "IRQ Input Enable"]
2383    #[inline(always)]
2384    pub fn isel(
2385        self,
2386    ) -> crate::common::RegisterField<
2387        14,
2388        0x1,
2389        1,
2390        0,
2391        p00pfs_ha::Isel,
2392        p00pfs_ha::Isel,
2393        P00PfsHa_SPEC,
2394        crate::common::RW,
2395    > {
2396        crate::common::RegisterField::<
2397            14,
2398            0x1,
2399            1,
2400            0,
2401            p00pfs_ha::Isel,
2402            p00pfs_ha::Isel,
2403            P00PfsHa_SPEC,
2404            crate::common::RW,
2405        >::from_register(self, 0)
2406    }
2407
2408    #[doc = "Analog Input Enable"]
2409    #[inline(always)]
2410    pub fn asel(
2411        self,
2412    ) -> crate::common::RegisterField<
2413        15,
2414        0x1,
2415        1,
2416        0,
2417        p00pfs_ha::Asel,
2418        p00pfs_ha::Asel,
2419        P00PfsHa_SPEC,
2420        crate::common::RW,
2421    > {
2422        crate::common::RegisterField::<
2423            15,
2424            0x1,
2425            1,
2426            0,
2427            p00pfs_ha::Asel,
2428            p00pfs_ha::Asel,
2429            P00PfsHa_SPEC,
2430            crate::common::RW,
2431        >::from_register(self, 0)
2432    }
2433}
2434impl ::core::default::Default for P00PfsHa {
2435    #[inline(always)]
2436    fn default() -> P00PfsHa {
2437        <crate::RegValueT<P00PfsHa_SPEC> as RegisterValue<_>>::new(0)
2438    }
2439}
2440pub mod p00pfs_ha {
2441
2442    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2443    pub struct Podr_SPEC;
2444    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2445    impl Podr {
2446        #[doc = "Output low"]
2447        pub const _0: Self = Self::new(0);
2448
2449        #[doc = "Output high"]
2450        pub const _1: Self = Self::new(1);
2451    }
2452    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2453    pub struct Pidr_SPEC;
2454    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2455    impl Pidr {
2456        #[doc = "Low level"]
2457        pub const _0: Self = Self::new(0);
2458
2459        #[doc = "High level"]
2460        pub const _1: Self = Self::new(1);
2461    }
2462    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2463    pub struct Pdr_SPEC;
2464    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2465    impl Pdr {
2466        #[doc = "Input (functions as an input pin)"]
2467        pub const _0: Self = Self::new(0);
2468
2469        #[doc = "Output (functions as an output pin)"]
2470        pub const _1: Self = Self::new(1);
2471    }
2472    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2473    pub struct Pcr_SPEC;
2474    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2475    impl Pcr {
2476        #[doc = "Disable input pull-up"]
2477        pub const _0: Self = Self::new(0);
2478
2479        #[doc = "Enable input pull-up"]
2480        pub const _1: Self = Self::new(1);
2481    }
2482    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2483    pub struct Ncodr_SPEC;
2484    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2485    impl Ncodr {
2486        #[doc = "Output CMOS"]
2487        pub const _0: Self = Self::new(0);
2488
2489        #[doc = "Output NMOS open-drain"]
2490        pub const _1: Self = Self::new(1);
2491    }
2492    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2493    pub struct Dscr_SPEC;
2494    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
2495    impl Dscr {
2496        #[doc = "Low drive"]
2497        pub const _00: Self = Self::new(0);
2498
2499        #[doc = "Middle drive"]
2500        pub const _01: Self = Self::new(1);
2501
2502        #[doc = "Setting prohibited"]
2503        pub const _10: Self = Self::new(2);
2504
2505        #[doc = "High drive"]
2506        pub const _11: Self = Self::new(3);
2507    }
2508    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2509    pub struct Eofr_SPEC;
2510    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
2511    impl Eofr {
2512        #[doc = "Don\'t care"]
2513        pub const _00: Self = Self::new(0);
2514
2515        #[doc = "Detect rising edge"]
2516        pub const _01: Self = Self::new(1);
2517
2518        #[doc = "Detect falling edge"]
2519        pub const _10: Self = Self::new(2);
2520
2521        #[doc = "Detect both edges"]
2522        pub const _11: Self = Self::new(3);
2523    }
2524    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2525    pub struct Isel_SPEC;
2526    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2527    impl Isel {
2528        #[doc = "Do not use as IRQn input pin"]
2529        pub const _0: Self = Self::new(0);
2530
2531        #[doc = "Use as IRQn input pin"]
2532        pub const _1: Self = Self::new(1);
2533    }
2534    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2535    pub struct Asel_SPEC;
2536    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2537    impl Asel {
2538        #[doc = "Do not use as analog pin"]
2539        pub const _0: Self = Self::new(0);
2540
2541        #[doc = "Use as analog pin"]
2542        pub const _1: Self = Self::new(1);
2543    }
2544}
2545#[doc(hidden)]
2546#[derive(Copy, Clone, Eq, PartialEq)]
2547pub struct P00PfsBy_SPEC;
2548impl crate::sealed::RegSpec for P00PfsBy_SPEC {
2549    type DataType = u8;
2550}
2551
2552#[doc = "Port 00%s Pin Function Select Register"]
2553pub type P00PfsBy = crate::RegValueT<P00PfsBy_SPEC>;
2554
2555impl P00PfsBy {
2556    #[doc = "Port Output Data"]
2557    #[inline(always)]
2558    pub fn podr(
2559        self,
2560    ) -> crate::common::RegisterField<
2561        0,
2562        0x1,
2563        1,
2564        0,
2565        p00pfs_by::Podr,
2566        p00pfs_by::Podr,
2567        P00PfsBy_SPEC,
2568        crate::common::RW,
2569    > {
2570        crate::common::RegisterField::<
2571            0,
2572            0x1,
2573            1,
2574            0,
2575            p00pfs_by::Podr,
2576            p00pfs_by::Podr,
2577            P00PfsBy_SPEC,
2578            crate::common::RW,
2579        >::from_register(self, 0)
2580    }
2581
2582    #[doc = "Port State"]
2583    #[inline(always)]
2584    pub fn pidr(
2585        self,
2586    ) -> crate::common::RegisterField<
2587        1,
2588        0x1,
2589        1,
2590        0,
2591        p00pfs_by::Pidr,
2592        p00pfs_by::Pidr,
2593        P00PfsBy_SPEC,
2594        crate::common::R,
2595    > {
2596        crate::common::RegisterField::<
2597            1,
2598            0x1,
2599            1,
2600            0,
2601            p00pfs_by::Pidr,
2602            p00pfs_by::Pidr,
2603            P00PfsBy_SPEC,
2604            crate::common::R,
2605        >::from_register(self, 0)
2606    }
2607
2608    #[doc = "Port Direction"]
2609    #[inline(always)]
2610    pub fn pdr(
2611        self,
2612    ) -> crate::common::RegisterField<
2613        2,
2614        0x1,
2615        1,
2616        0,
2617        p00pfs_by::Pdr,
2618        p00pfs_by::Pdr,
2619        P00PfsBy_SPEC,
2620        crate::common::RW,
2621    > {
2622        crate::common::RegisterField::<
2623            2,
2624            0x1,
2625            1,
2626            0,
2627            p00pfs_by::Pdr,
2628            p00pfs_by::Pdr,
2629            P00PfsBy_SPEC,
2630            crate::common::RW,
2631        >::from_register(self, 0)
2632    }
2633
2634    #[doc = "Pull-up Control"]
2635    #[inline(always)]
2636    pub fn pcr(
2637        self,
2638    ) -> crate::common::RegisterField<
2639        4,
2640        0x1,
2641        1,
2642        0,
2643        p00pfs_by::Pcr,
2644        p00pfs_by::Pcr,
2645        P00PfsBy_SPEC,
2646        crate::common::RW,
2647    > {
2648        crate::common::RegisterField::<
2649            4,
2650            0x1,
2651            1,
2652            0,
2653            p00pfs_by::Pcr,
2654            p00pfs_by::Pcr,
2655            P00PfsBy_SPEC,
2656            crate::common::RW,
2657        >::from_register(self, 0)
2658    }
2659
2660    #[doc = "N-Channel Open-Drain Control"]
2661    #[inline(always)]
2662    pub fn ncodr(
2663        self,
2664    ) -> crate::common::RegisterField<
2665        6,
2666        0x1,
2667        1,
2668        0,
2669        p00pfs_by::Ncodr,
2670        p00pfs_by::Ncodr,
2671        P00PfsBy_SPEC,
2672        crate::common::RW,
2673    > {
2674        crate::common::RegisterField::<
2675            6,
2676            0x1,
2677            1,
2678            0,
2679            p00pfs_by::Ncodr,
2680            p00pfs_by::Ncodr,
2681            P00PfsBy_SPEC,
2682            crate::common::RW,
2683        >::from_register(self, 0)
2684    }
2685}
2686impl ::core::default::Default for P00PfsBy {
2687    #[inline(always)]
2688    fn default() -> P00PfsBy {
2689        <crate::RegValueT<P00PfsBy_SPEC> as RegisterValue<_>>::new(0)
2690    }
2691}
2692pub mod p00pfs_by {
2693
2694    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2695    pub struct Podr_SPEC;
2696    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2697    impl Podr {
2698        #[doc = "Output low"]
2699        pub const _0: Self = Self::new(0);
2700
2701        #[doc = "Output high"]
2702        pub const _1: Self = Self::new(1);
2703    }
2704    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2705    pub struct Pidr_SPEC;
2706    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2707    impl Pidr {
2708        #[doc = "Low level"]
2709        pub const _0: Self = Self::new(0);
2710
2711        #[doc = "High level"]
2712        pub const _1: Self = Self::new(1);
2713    }
2714    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2715    pub struct Pdr_SPEC;
2716    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2717    impl Pdr {
2718        #[doc = "Input (functions as an input pin)"]
2719        pub const _0: Self = Self::new(0);
2720
2721        #[doc = "Output (functions as an output pin)"]
2722        pub const _1: Self = Self::new(1);
2723    }
2724    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2725    pub struct Pcr_SPEC;
2726    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2727    impl Pcr {
2728        #[doc = "Disable input pull-up"]
2729        pub const _0: Self = Self::new(0);
2730
2731        #[doc = "Enable input pull-up"]
2732        pub const _1: Self = Self::new(1);
2733    }
2734    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2735    pub struct Ncodr_SPEC;
2736    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2737    impl Ncodr {
2738        #[doc = "Output CMOS"]
2739        pub const _0: Self = Self::new(0);
2740
2741        #[doc = "Output NMOS open-drain"]
2742        pub const _1: Self = Self::new(1);
2743    }
2744}
2745#[doc(hidden)]
2746#[derive(Copy, Clone, Eq, PartialEq)]
2747pub struct P008Pfs_SPEC;
2748impl crate::sealed::RegSpec for P008Pfs_SPEC {
2749    type DataType = u32;
2750}
2751
2752#[doc = "Port 008 Pin Function Select Register"]
2753pub type P008Pfs = crate::RegValueT<P008Pfs_SPEC>;
2754
2755impl P008Pfs {
2756    #[doc = "Port Output Data"]
2757    #[inline(always)]
2758    pub fn podr(
2759        self,
2760    ) -> crate::common::RegisterField<
2761        0,
2762        0x1,
2763        1,
2764        0,
2765        p008pfs::Podr,
2766        p008pfs::Podr,
2767        P008Pfs_SPEC,
2768        crate::common::RW,
2769    > {
2770        crate::common::RegisterField::<
2771            0,
2772            0x1,
2773            1,
2774            0,
2775            p008pfs::Podr,
2776            p008pfs::Podr,
2777            P008Pfs_SPEC,
2778            crate::common::RW,
2779        >::from_register(self, 0)
2780    }
2781
2782    #[doc = "Port State"]
2783    #[inline(always)]
2784    pub fn pidr(
2785        self,
2786    ) -> crate::common::RegisterField<
2787        1,
2788        0x1,
2789        1,
2790        0,
2791        p008pfs::Pidr,
2792        p008pfs::Pidr,
2793        P008Pfs_SPEC,
2794        crate::common::R,
2795    > {
2796        crate::common::RegisterField::<
2797            1,
2798            0x1,
2799            1,
2800            0,
2801            p008pfs::Pidr,
2802            p008pfs::Pidr,
2803            P008Pfs_SPEC,
2804            crate::common::R,
2805        >::from_register(self, 0)
2806    }
2807
2808    #[doc = "Port Direction"]
2809    #[inline(always)]
2810    pub fn pdr(
2811        self,
2812    ) -> crate::common::RegisterField<
2813        2,
2814        0x1,
2815        1,
2816        0,
2817        p008pfs::Pdr,
2818        p008pfs::Pdr,
2819        P008Pfs_SPEC,
2820        crate::common::RW,
2821    > {
2822        crate::common::RegisterField::<
2823            2,
2824            0x1,
2825            1,
2826            0,
2827            p008pfs::Pdr,
2828            p008pfs::Pdr,
2829            P008Pfs_SPEC,
2830            crate::common::RW,
2831        >::from_register(self, 0)
2832    }
2833
2834    #[doc = "Pull-up Control"]
2835    #[inline(always)]
2836    pub fn pcr(
2837        self,
2838    ) -> crate::common::RegisterField<
2839        4,
2840        0x1,
2841        1,
2842        0,
2843        p008pfs::Pcr,
2844        p008pfs::Pcr,
2845        P008Pfs_SPEC,
2846        crate::common::RW,
2847    > {
2848        crate::common::RegisterField::<
2849            4,
2850            0x1,
2851            1,
2852            0,
2853            p008pfs::Pcr,
2854            p008pfs::Pcr,
2855            P008Pfs_SPEC,
2856            crate::common::RW,
2857        >::from_register(self, 0)
2858    }
2859
2860    #[doc = "N-Channel Open-Drain Control"]
2861    #[inline(always)]
2862    pub fn ncodr(
2863        self,
2864    ) -> crate::common::RegisterField<
2865        6,
2866        0x1,
2867        1,
2868        0,
2869        p008pfs::Ncodr,
2870        p008pfs::Ncodr,
2871        P008Pfs_SPEC,
2872        crate::common::RW,
2873    > {
2874        crate::common::RegisterField::<
2875            6,
2876            0x1,
2877            1,
2878            0,
2879            p008pfs::Ncodr,
2880            p008pfs::Ncodr,
2881            P008Pfs_SPEC,
2882            crate::common::RW,
2883        >::from_register(self, 0)
2884    }
2885
2886    #[doc = "Port Drive Capability"]
2887    #[inline(always)]
2888    pub fn dscr(
2889        self,
2890    ) -> crate::common::RegisterField<
2891        10,
2892        0x3,
2893        1,
2894        0,
2895        p008pfs::Dscr,
2896        p008pfs::Dscr,
2897        P008Pfs_SPEC,
2898        crate::common::RW,
2899    > {
2900        crate::common::RegisterField::<
2901            10,
2902            0x3,
2903            1,
2904            0,
2905            p008pfs::Dscr,
2906            p008pfs::Dscr,
2907            P008Pfs_SPEC,
2908            crate::common::RW,
2909        >::from_register(self, 0)
2910    }
2911
2912    #[doc = "Event on Falling/Event on Rising"]
2913    #[inline(always)]
2914    pub fn eofr(
2915        self,
2916    ) -> crate::common::RegisterField<
2917        12,
2918        0x3,
2919        1,
2920        0,
2921        p008pfs::Eofr,
2922        p008pfs::Eofr,
2923        P008Pfs_SPEC,
2924        crate::common::RW,
2925    > {
2926        crate::common::RegisterField::<
2927            12,
2928            0x3,
2929            1,
2930            0,
2931            p008pfs::Eofr,
2932            p008pfs::Eofr,
2933            P008Pfs_SPEC,
2934            crate::common::RW,
2935        >::from_register(self, 0)
2936    }
2937
2938    #[doc = "IRQ Input Enable"]
2939    #[inline(always)]
2940    pub fn isel(
2941        self,
2942    ) -> crate::common::RegisterField<
2943        14,
2944        0x1,
2945        1,
2946        0,
2947        p008pfs::Isel,
2948        p008pfs::Isel,
2949        P008Pfs_SPEC,
2950        crate::common::RW,
2951    > {
2952        crate::common::RegisterField::<
2953            14,
2954            0x1,
2955            1,
2956            0,
2957            p008pfs::Isel,
2958            p008pfs::Isel,
2959            P008Pfs_SPEC,
2960            crate::common::RW,
2961        >::from_register(self, 0)
2962    }
2963
2964    #[doc = "Analog Input Enable"]
2965    #[inline(always)]
2966    pub fn asel(
2967        self,
2968    ) -> crate::common::RegisterField<
2969        15,
2970        0x1,
2971        1,
2972        0,
2973        p008pfs::Asel,
2974        p008pfs::Asel,
2975        P008Pfs_SPEC,
2976        crate::common::RW,
2977    > {
2978        crate::common::RegisterField::<
2979            15,
2980            0x1,
2981            1,
2982            0,
2983            p008pfs::Asel,
2984            p008pfs::Asel,
2985            P008Pfs_SPEC,
2986            crate::common::RW,
2987        >::from_register(self, 0)
2988    }
2989
2990    #[doc = "Port Mode Control"]
2991    #[inline(always)]
2992    pub fn pmr(
2993        self,
2994    ) -> crate::common::RegisterField<
2995        16,
2996        0x1,
2997        1,
2998        0,
2999        p008pfs::Pmr,
3000        p008pfs::Pmr,
3001        P008Pfs_SPEC,
3002        crate::common::RW,
3003    > {
3004        crate::common::RegisterField::<
3005            16,
3006            0x1,
3007            1,
3008            0,
3009            p008pfs::Pmr,
3010            p008pfs::Pmr,
3011            P008Pfs_SPEC,
3012            crate::common::RW,
3013        >::from_register(self, 0)
3014    }
3015
3016    #[doc = "Peripheral Select"]
3017    #[inline(always)]
3018    pub fn psel(
3019        self,
3020    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P008Pfs_SPEC, crate::common::RW> {
3021        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P008Pfs_SPEC,crate::common::RW>::from_register(self,0)
3022    }
3023}
3024impl ::core::default::Default for P008Pfs {
3025    #[inline(always)]
3026    fn default() -> P008Pfs {
3027        <crate::RegValueT<P008Pfs_SPEC> as RegisterValue<_>>::new(66576)
3028    }
3029}
3030pub mod p008pfs {
3031
3032    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3033    pub struct Podr_SPEC;
3034    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3035    impl Podr {
3036        #[doc = "Output low"]
3037        pub const _0: Self = Self::new(0);
3038
3039        #[doc = "Output high"]
3040        pub const _1: Self = Self::new(1);
3041    }
3042    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3043    pub struct Pidr_SPEC;
3044    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3045    impl Pidr {
3046        #[doc = "Low level"]
3047        pub const _0: Self = Self::new(0);
3048
3049        #[doc = "High level"]
3050        pub const _1: Self = Self::new(1);
3051    }
3052    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3053    pub struct Pdr_SPEC;
3054    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3055    impl Pdr {
3056        #[doc = "Input (functions as an input pin)"]
3057        pub const _0: Self = Self::new(0);
3058
3059        #[doc = "Output (functions as an output pin)"]
3060        pub const _1: Self = Self::new(1);
3061    }
3062    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3063    pub struct Pcr_SPEC;
3064    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3065    impl Pcr {
3066        #[doc = "Disable input pull-up"]
3067        pub const _0: Self = Self::new(0);
3068
3069        #[doc = "Enable input pull-up"]
3070        pub const _1: Self = Self::new(1);
3071    }
3072    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3073    pub struct Ncodr_SPEC;
3074    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3075    impl Ncodr {
3076        #[doc = "Output CMOS"]
3077        pub const _0: Self = Self::new(0);
3078
3079        #[doc = "Output NMOS open-drain"]
3080        pub const _1: Self = Self::new(1);
3081    }
3082    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3083    pub struct Dscr_SPEC;
3084    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
3085    impl Dscr {
3086        #[doc = "Low drive"]
3087        pub const _00: Self = Self::new(0);
3088
3089        #[doc = "Middle drive"]
3090        pub const _01: Self = Self::new(1);
3091
3092        #[doc = "Setting prohibited"]
3093        pub const _10: Self = Self::new(2);
3094
3095        #[doc = "High drive"]
3096        pub const _11: Self = Self::new(3);
3097    }
3098    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3099    pub struct Eofr_SPEC;
3100    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3101    impl Eofr {
3102        #[doc = "Don\'t care"]
3103        pub const _00: Self = Self::new(0);
3104
3105        #[doc = "Detect rising edge"]
3106        pub const _01: Self = Self::new(1);
3107
3108        #[doc = "Detect falling edge"]
3109        pub const _10: Self = Self::new(2);
3110
3111        #[doc = "Detect both edges"]
3112        pub const _11: Self = Self::new(3);
3113    }
3114    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3115    pub struct Isel_SPEC;
3116    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3117    impl Isel {
3118        #[doc = "Do not use as IRQn input pin"]
3119        pub const _0: Self = Self::new(0);
3120
3121        #[doc = "Use as IRQn input pin"]
3122        pub const _1: Self = Self::new(1);
3123    }
3124    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3125    pub struct Asel_SPEC;
3126    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3127    impl Asel {
3128        #[doc = "Do not use as analog pin"]
3129        pub const _0: Self = Self::new(0);
3130
3131        #[doc = "Use as analog pin"]
3132        pub const _1: Self = Self::new(1);
3133    }
3134    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3135    pub struct Pmr_SPEC;
3136    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
3137    impl Pmr {
3138        #[doc = "Use as general I/O pin"]
3139        pub const _0: Self = Self::new(0);
3140
3141        #[doc = "Use as I/O port for peripheral functions"]
3142        pub const _1: Self = Self::new(1);
3143    }
3144}
3145#[doc(hidden)]
3146#[derive(Copy, Clone, Eq, PartialEq)]
3147pub struct P008PfsHa_SPEC;
3148impl crate::sealed::RegSpec for P008PfsHa_SPEC {
3149    type DataType = u16;
3150}
3151
3152#[doc = "Port 008 Pin Function Select Register"]
3153pub type P008PfsHa = crate::RegValueT<P008PfsHa_SPEC>;
3154
3155impl P008PfsHa {
3156    #[doc = "Port Output Data"]
3157    #[inline(always)]
3158    pub fn podr(
3159        self,
3160    ) -> crate::common::RegisterField<
3161        0,
3162        0x1,
3163        1,
3164        0,
3165        p008pfs_ha::Podr,
3166        p008pfs_ha::Podr,
3167        P008PfsHa_SPEC,
3168        crate::common::RW,
3169    > {
3170        crate::common::RegisterField::<
3171            0,
3172            0x1,
3173            1,
3174            0,
3175            p008pfs_ha::Podr,
3176            p008pfs_ha::Podr,
3177            P008PfsHa_SPEC,
3178            crate::common::RW,
3179        >::from_register(self, 0)
3180    }
3181
3182    #[doc = "Port State"]
3183    #[inline(always)]
3184    pub fn pidr(
3185        self,
3186    ) -> crate::common::RegisterField<
3187        1,
3188        0x1,
3189        1,
3190        0,
3191        p008pfs_ha::Pidr,
3192        p008pfs_ha::Pidr,
3193        P008PfsHa_SPEC,
3194        crate::common::R,
3195    > {
3196        crate::common::RegisterField::<
3197            1,
3198            0x1,
3199            1,
3200            0,
3201            p008pfs_ha::Pidr,
3202            p008pfs_ha::Pidr,
3203            P008PfsHa_SPEC,
3204            crate::common::R,
3205        >::from_register(self, 0)
3206    }
3207
3208    #[doc = "Port Direction"]
3209    #[inline(always)]
3210    pub fn pdr(
3211        self,
3212    ) -> crate::common::RegisterField<
3213        2,
3214        0x1,
3215        1,
3216        0,
3217        p008pfs_ha::Pdr,
3218        p008pfs_ha::Pdr,
3219        P008PfsHa_SPEC,
3220        crate::common::RW,
3221    > {
3222        crate::common::RegisterField::<
3223            2,
3224            0x1,
3225            1,
3226            0,
3227            p008pfs_ha::Pdr,
3228            p008pfs_ha::Pdr,
3229            P008PfsHa_SPEC,
3230            crate::common::RW,
3231        >::from_register(self, 0)
3232    }
3233
3234    #[doc = "Pull-up Control"]
3235    #[inline(always)]
3236    pub fn pcr(
3237        self,
3238    ) -> crate::common::RegisterField<
3239        4,
3240        0x1,
3241        1,
3242        0,
3243        p008pfs_ha::Pcr,
3244        p008pfs_ha::Pcr,
3245        P008PfsHa_SPEC,
3246        crate::common::RW,
3247    > {
3248        crate::common::RegisterField::<
3249            4,
3250            0x1,
3251            1,
3252            0,
3253            p008pfs_ha::Pcr,
3254            p008pfs_ha::Pcr,
3255            P008PfsHa_SPEC,
3256            crate::common::RW,
3257        >::from_register(self, 0)
3258    }
3259
3260    #[doc = "N-Channel Open-Drain Control"]
3261    #[inline(always)]
3262    pub fn ncodr(
3263        self,
3264    ) -> crate::common::RegisterField<
3265        6,
3266        0x1,
3267        1,
3268        0,
3269        p008pfs_ha::Ncodr,
3270        p008pfs_ha::Ncodr,
3271        P008PfsHa_SPEC,
3272        crate::common::RW,
3273    > {
3274        crate::common::RegisterField::<
3275            6,
3276            0x1,
3277            1,
3278            0,
3279            p008pfs_ha::Ncodr,
3280            p008pfs_ha::Ncodr,
3281            P008PfsHa_SPEC,
3282            crate::common::RW,
3283        >::from_register(self, 0)
3284    }
3285
3286    #[doc = "Port Drive Capability"]
3287    #[inline(always)]
3288    pub fn dscr(
3289        self,
3290    ) -> crate::common::RegisterField<
3291        10,
3292        0x3,
3293        1,
3294        0,
3295        p008pfs_ha::Dscr,
3296        p008pfs_ha::Dscr,
3297        P008PfsHa_SPEC,
3298        crate::common::RW,
3299    > {
3300        crate::common::RegisterField::<
3301            10,
3302            0x3,
3303            1,
3304            0,
3305            p008pfs_ha::Dscr,
3306            p008pfs_ha::Dscr,
3307            P008PfsHa_SPEC,
3308            crate::common::RW,
3309        >::from_register(self, 0)
3310    }
3311
3312    #[doc = "Event on Falling/Event on Rising"]
3313    #[inline(always)]
3314    pub fn eofr(
3315        self,
3316    ) -> crate::common::RegisterField<
3317        12,
3318        0x3,
3319        1,
3320        0,
3321        p008pfs_ha::Eofr,
3322        p008pfs_ha::Eofr,
3323        P008PfsHa_SPEC,
3324        crate::common::RW,
3325    > {
3326        crate::common::RegisterField::<
3327            12,
3328            0x3,
3329            1,
3330            0,
3331            p008pfs_ha::Eofr,
3332            p008pfs_ha::Eofr,
3333            P008PfsHa_SPEC,
3334            crate::common::RW,
3335        >::from_register(self, 0)
3336    }
3337
3338    #[doc = "IRQ Input Enable"]
3339    #[inline(always)]
3340    pub fn isel(
3341        self,
3342    ) -> crate::common::RegisterField<
3343        14,
3344        0x1,
3345        1,
3346        0,
3347        p008pfs_ha::Isel,
3348        p008pfs_ha::Isel,
3349        P008PfsHa_SPEC,
3350        crate::common::RW,
3351    > {
3352        crate::common::RegisterField::<
3353            14,
3354            0x1,
3355            1,
3356            0,
3357            p008pfs_ha::Isel,
3358            p008pfs_ha::Isel,
3359            P008PfsHa_SPEC,
3360            crate::common::RW,
3361        >::from_register(self, 0)
3362    }
3363
3364    #[doc = "Analog Input Enable"]
3365    #[inline(always)]
3366    pub fn asel(
3367        self,
3368    ) -> crate::common::RegisterField<
3369        15,
3370        0x1,
3371        1,
3372        0,
3373        p008pfs_ha::Asel,
3374        p008pfs_ha::Asel,
3375        P008PfsHa_SPEC,
3376        crate::common::RW,
3377    > {
3378        crate::common::RegisterField::<
3379            15,
3380            0x1,
3381            1,
3382            0,
3383            p008pfs_ha::Asel,
3384            p008pfs_ha::Asel,
3385            P008PfsHa_SPEC,
3386            crate::common::RW,
3387        >::from_register(self, 0)
3388    }
3389}
3390impl ::core::default::Default for P008PfsHa {
3391    #[inline(always)]
3392    fn default() -> P008PfsHa {
3393        <crate::RegValueT<P008PfsHa_SPEC> as RegisterValue<_>>::new(1040)
3394    }
3395}
3396pub mod p008pfs_ha {
3397
3398    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3399    pub struct Podr_SPEC;
3400    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3401    impl Podr {
3402        #[doc = "Output low"]
3403        pub const _0: Self = Self::new(0);
3404
3405        #[doc = "Output high"]
3406        pub const _1: Self = Self::new(1);
3407    }
3408    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3409    pub struct Pidr_SPEC;
3410    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3411    impl Pidr {
3412        #[doc = "Low level"]
3413        pub const _0: Self = Self::new(0);
3414
3415        #[doc = "High level"]
3416        pub const _1: Self = Self::new(1);
3417    }
3418    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3419    pub struct Pdr_SPEC;
3420    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3421    impl Pdr {
3422        #[doc = "Input (functions as an input pin)"]
3423        pub const _0: Self = Self::new(0);
3424
3425        #[doc = "Output (functions as an output pin)"]
3426        pub const _1: Self = Self::new(1);
3427    }
3428    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3429    pub struct Pcr_SPEC;
3430    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3431    impl Pcr {
3432        #[doc = "Disable input pull-up"]
3433        pub const _0: Self = Self::new(0);
3434
3435        #[doc = "Enable input pull-up"]
3436        pub const _1: Self = Self::new(1);
3437    }
3438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3439    pub struct Ncodr_SPEC;
3440    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3441    impl Ncodr {
3442        #[doc = "Output CMOS"]
3443        pub const _0: Self = Self::new(0);
3444
3445        #[doc = "Output NMOS open-drain"]
3446        pub const _1: Self = Self::new(1);
3447    }
3448    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3449    pub struct Dscr_SPEC;
3450    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
3451    impl Dscr {
3452        #[doc = "Low drive"]
3453        pub const _00: Self = Self::new(0);
3454
3455        #[doc = "Middle drive"]
3456        pub const _01: Self = Self::new(1);
3457
3458        #[doc = "Setting prohibited"]
3459        pub const _10: Self = Self::new(2);
3460
3461        #[doc = "High drive"]
3462        pub const _11: Self = Self::new(3);
3463    }
3464    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3465    pub struct Eofr_SPEC;
3466    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3467    impl Eofr {
3468        #[doc = "Don\'t care"]
3469        pub const _00: Self = Self::new(0);
3470
3471        #[doc = "Detect rising edge"]
3472        pub const _01: Self = Self::new(1);
3473
3474        #[doc = "Detect falling edge"]
3475        pub const _10: Self = Self::new(2);
3476
3477        #[doc = "Detect both edges"]
3478        pub const _11: Self = Self::new(3);
3479    }
3480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3481    pub struct Isel_SPEC;
3482    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3483    impl Isel {
3484        #[doc = "Do not use as IRQn input pin"]
3485        pub const _0: Self = Self::new(0);
3486
3487        #[doc = "Use as IRQn input pin"]
3488        pub const _1: Self = Self::new(1);
3489    }
3490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3491    pub struct Asel_SPEC;
3492    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3493    impl Asel {
3494        #[doc = "Do not use as analog pin"]
3495        pub const _0: Self = Self::new(0);
3496
3497        #[doc = "Use as analog pin"]
3498        pub const _1: Self = Self::new(1);
3499    }
3500}
3501#[doc(hidden)]
3502#[derive(Copy, Clone, Eq, PartialEq)]
3503pub struct P008PfsBy_SPEC;
3504impl crate::sealed::RegSpec for P008PfsBy_SPEC {
3505    type DataType = u8;
3506}
3507
3508#[doc = "Port 008 Pin Function Select Register"]
3509pub type P008PfsBy = crate::RegValueT<P008PfsBy_SPEC>;
3510
3511impl P008PfsBy {
3512    #[doc = "Port Output Data"]
3513    #[inline(always)]
3514    pub fn podr(
3515        self,
3516    ) -> crate::common::RegisterField<
3517        0,
3518        0x1,
3519        1,
3520        0,
3521        p008pfs_by::Podr,
3522        p008pfs_by::Podr,
3523        P008PfsBy_SPEC,
3524        crate::common::RW,
3525    > {
3526        crate::common::RegisterField::<
3527            0,
3528            0x1,
3529            1,
3530            0,
3531            p008pfs_by::Podr,
3532            p008pfs_by::Podr,
3533            P008PfsBy_SPEC,
3534            crate::common::RW,
3535        >::from_register(self, 0)
3536    }
3537
3538    #[doc = "Port State"]
3539    #[inline(always)]
3540    pub fn pidr(
3541        self,
3542    ) -> crate::common::RegisterField<
3543        1,
3544        0x1,
3545        1,
3546        0,
3547        p008pfs_by::Pidr,
3548        p008pfs_by::Pidr,
3549        P008PfsBy_SPEC,
3550        crate::common::R,
3551    > {
3552        crate::common::RegisterField::<
3553            1,
3554            0x1,
3555            1,
3556            0,
3557            p008pfs_by::Pidr,
3558            p008pfs_by::Pidr,
3559            P008PfsBy_SPEC,
3560            crate::common::R,
3561        >::from_register(self, 0)
3562    }
3563
3564    #[doc = "Port Direction"]
3565    #[inline(always)]
3566    pub fn pdr(
3567        self,
3568    ) -> crate::common::RegisterField<
3569        2,
3570        0x1,
3571        1,
3572        0,
3573        p008pfs_by::Pdr,
3574        p008pfs_by::Pdr,
3575        P008PfsBy_SPEC,
3576        crate::common::RW,
3577    > {
3578        crate::common::RegisterField::<
3579            2,
3580            0x1,
3581            1,
3582            0,
3583            p008pfs_by::Pdr,
3584            p008pfs_by::Pdr,
3585            P008PfsBy_SPEC,
3586            crate::common::RW,
3587        >::from_register(self, 0)
3588    }
3589
3590    #[doc = "Pull-up Control"]
3591    #[inline(always)]
3592    pub fn pcr(
3593        self,
3594    ) -> crate::common::RegisterField<
3595        4,
3596        0x1,
3597        1,
3598        0,
3599        p008pfs_by::Pcr,
3600        p008pfs_by::Pcr,
3601        P008PfsBy_SPEC,
3602        crate::common::RW,
3603    > {
3604        crate::common::RegisterField::<
3605            4,
3606            0x1,
3607            1,
3608            0,
3609            p008pfs_by::Pcr,
3610            p008pfs_by::Pcr,
3611            P008PfsBy_SPEC,
3612            crate::common::RW,
3613        >::from_register(self, 0)
3614    }
3615
3616    #[doc = "N-Channel Open-Drain Control"]
3617    #[inline(always)]
3618    pub fn ncodr(
3619        self,
3620    ) -> crate::common::RegisterField<
3621        6,
3622        0x1,
3623        1,
3624        0,
3625        p008pfs_by::Ncodr,
3626        p008pfs_by::Ncodr,
3627        P008PfsBy_SPEC,
3628        crate::common::RW,
3629    > {
3630        crate::common::RegisterField::<
3631            6,
3632            0x1,
3633            1,
3634            0,
3635            p008pfs_by::Ncodr,
3636            p008pfs_by::Ncodr,
3637            P008PfsBy_SPEC,
3638            crate::common::RW,
3639        >::from_register(self, 0)
3640    }
3641}
3642impl ::core::default::Default for P008PfsBy {
3643    #[inline(always)]
3644    fn default() -> P008PfsBy {
3645        <crate::RegValueT<P008PfsBy_SPEC> as RegisterValue<_>>::new(16)
3646    }
3647}
3648pub mod p008pfs_by {
3649
3650    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3651    pub struct Podr_SPEC;
3652    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3653    impl Podr {
3654        #[doc = "Output low"]
3655        pub const _0: Self = Self::new(0);
3656
3657        #[doc = "Output high"]
3658        pub const _1: Self = Self::new(1);
3659    }
3660    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3661    pub struct Pidr_SPEC;
3662    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3663    impl Pidr {
3664        #[doc = "Low level"]
3665        pub const _0: Self = Self::new(0);
3666
3667        #[doc = "High level"]
3668        pub const _1: Self = Self::new(1);
3669    }
3670    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3671    pub struct Pdr_SPEC;
3672    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3673    impl Pdr {
3674        #[doc = "Input (functions as an input pin)"]
3675        pub const _0: Self = Self::new(0);
3676
3677        #[doc = "Output (functions as an output pin)"]
3678        pub const _1: Self = Self::new(1);
3679    }
3680    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3681    pub struct Pcr_SPEC;
3682    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3683    impl Pcr {
3684        #[doc = "Disable input pull-up"]
3685        pub const _0: Self = Self::new(0);
3686
3687        #[doc = "Enable input pull-up"]
3688        pub const _1: Self = Self::new(1);
3689    }
3690    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3691    pub struct Ncodr_SPEC;
3692    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3693    impl Ncodr {
3694        #[doc = "Output CMOS"]
3695        pub const _0: Self = Self::new(0);
3696
3697        #[doc = "Output NMOS open-drain"]
3698        pub const _1: Self = Self::new(1);
3699    }
3700}
3701#[doc(hidden)]
3702#[derive(Copy, Clone, Eq, PartialEq)]
3703pub struct P0Pfs_SPEC;
3704impl crate::sealed::RegSpec for P0Pfs_SPEC {
3705    type DataType = u32;
3706}
3707
3708#[doc = "Port 0%s Pin Function Select Register"]
3709pub type P0Pfs = crate::RegValueT<P0Pfs_SPEC>;
3710
3711impl P0Pfs {
3712    #[doc = "Port Output Data"]
3713    #[inline(always)]
3714    pub fn podr(
3715        self,
3716    ) -> crate::common::RegisterField<
3717        0,
3718        0x1,
3719        1,
3720        0,
3721        p0pfs::Podr,
3722        p0pfs::Podr,
3723        P0Pfs_SPEC,
3724        crate::common::RW,
3725    > {
3726        crate::common::RegisterField::<
3727            0,
3728            0x1,
3729            1,
3730            0,
3731            p0pfs::Podr,
3732            p0pfs::Podr,
3733            P0Pfs_SPEC,
3734            crate::common::RW,
3735        >::from_register(self, 0)
3736    }
3737
3738    #[doc = "Port State"]
3739    #[inline(always)]
3740    pub fn pidr(
3741        self,
3742    ) -> crate::common::RegisterField<
3743        1,
3744        0x1,
3745        1,
3746        0,
3747        p0pfs::Pidr,
3748        p0pfs::Pidr,
3749        P0Pfs_SPEC,
3750        crate::common::R,
3751    > {
3752        crate::common::RegisterField::<
3753            1,
3754            0x1,
3755            1,
3756            0,
3757            p0pfs::Pidr,
3758            p0pfs::Pidr,
3759            P0Pfs_SPEC,
3760            crate::common::R,
3761        >::from_register(self, 0)
3762    }
3763
3764    #[doc = "Port Direction"]
3765    #[inline(always)]
3766    pub fn pdr(
3767        self,
3768    ) -> crate::common::RegisterField<
3769        2,
3770        0x1,
3771        1,
3772        0,
3773        p0pfs::Pdr,
3774        p0pfs::Pdr,
3775        P0Pfs_SPEC,
3776        crate::common::RW,
3777    > {
3778        crate::common::RegisterField::<
3779            2,
3780            0x1,
3781            1,
3782            0,
3783            p0pfs::Pdr,
3784            p0pfs::Pdr,
3785            P0Pfs_SPEC,
3786            crate::common::RW,
3787        >::from_register(self, 0)
3788    }
3789
3790    #[doc = "Pull-up Control"]
3791    #[inline(always)]
3792    pub fn pcr(
3793        self,
3794    ) -> crate::common::RegisterField<
3795        4,
3796        0x1,
3797        1,
3798        0,
3799        p0pfs::Pcr,
3800        p0pfs::Pcr,
3801        P0Pfs_SPEC,
3802        crate::common::RW,
3803    > {
3804        crate::common::RegisterField::<
3805            4,
3806            0x1,
3807            1,
3808            0,
3809            p0pfs::Pcr,
3810            p0pfs::Pcr,
3811            P0Pfs_SPEC,
3812            crate::common::RW,
3813        >::from_register(self, 0)
3814    }
3815
3816    #[doc = "N-Channel Open-Drain Control"]
3817    #[inline(always)]
3818    pub fn ncodr(
3819        self,
3820    ) -> crate::common::RegisterField<
3821        6,
3822        0x1,
3823        1,
3824        0,
3825        p0pfs::Ncodr,
3826        p0pfs::Ncodr,
3827        P0Pfs_SPEC,
3828        crate::common::RW,
3829    > {
3830        crate::common::RegisterField::<
3831            6,
3832            0x1,
3833            1,
3834            0,
3835            p0pfs::Ncodr,
3836            p0pfs::Ncodr,
3837            P0Pfs_SPEC,
3838            crate::common::RW,
3839        >::from_register(self, 0)
3840    }
3841
3842    #[doc = "Port Drive Capability"]
3843    #[inline(always)]
3844    pub fn dscr(
3845        self,
3846    ) -> crate::common::RegisterField<
3847        10,
3848        0x3,
3849        1,
3850        0,
3851        p0pfs::Dscr,
3852        p0pfs::Dscr,
3853        P0Pfs_SPEC,
3854        crate::common::RW,
3855    > {
3856        crate::common::RegisterField::<
3857            10,
3858            0x3,
3859            1,
3860            0,
3861            p0pfs::Dscr,
3862            p0pfs::Dscr,
3863            P0Pfs_SPEC,
3864            crate::common::RW,
3865        >::from_register(self, 0)
3866    }
3867
3868    #[doc = "Event on Falling/Event on Rising"]
3869    #[inline(always)]
3870    pub fn eofr(
3871        self,
3872    ) -> crate::common::RegisterField<
3873        12,
3874        0x3,
3875        1,
3876        0,
3877        p0pfs::Eofr,
3878        p0pfs::Eofr,
3879        P0Pfs_SPEC,
3880        crate::common::RW,
3881    > {
3882        crate::common::RegisterField::<
3883            12,
3884            0x3,
3885            1,
3886            0,
3887            p0pfs::Eofr,
3888            p0pfs::Eofr,
3889            P0Pfs_SPEC,
3890            crate::common::RW,
3891        >::from_register(self, 0)
3892    }
3893
3894    #[doc = "IRQ Input Enable"]
3895    #[inline(always)]
3896    pub fn isel(
3897        self,
3898    ) -> crate::common::RegisterField<
3899        14,
3900        0x1,
3901        1,
3902        0,
3903        p0pfs::Isel,
3904        p0pfs::Isel,
3905        P0Pfs_SPEC,
3906        crate::common::RW,
3907    > {
3908        crate::common::RegisterField::<
3909            14,
3910            0x1,
3911            1,
3912            0,
3913            p0pfs::Isel,
3914            p0pfs::Isel,
3915            P0Pfs_SPEC,
3916            crate::common::RW,
3917        >::from_register(self, 0)
3918    }
3919
3920    #[doc = "Analog Input Enable"]
3921    #[inline(always)]
3922    pub fn asel(
3923        self,
3924    ) -> crate::common::RegisterField<
3925        15,
3926        0x1,
3927        1,
3928        0,
3929        p0pfs::Asel,
3930        p0pfs::Asel,
3931        P0Pfs_SPEC,
3932        crate::common::RW,
3933    > {
3934        crate::common::RegisterField::<
3935            15,
3936            0x1,
3937            1,
3938            0,
3939            p0pfs::Asel,
3940            p0pfs::Asel,
3941            P0Pfs_SPEC,
3942            crate::common::RW,
3943        >::from_register(self, 0)
3944    }
3945
3946    #[doc = "Port Mode Control"]
3947    #[inline(always)]
3948    pub fn pmr(
3949        self,
3950    ) -> crate::common::RegisterField<
3951        16,
3952        0x1,
3953        1,
3954        0,
3955        p0pfs::Pmr,
3956        p0pfs::Pmr,
3957        P0Pfs_SPEC,
3958        crate::common::RW,
3959    > {
3960        crate::common::RegisterField::<
3961            16,
3962            0x1,
3963            1,
3964            0,
3965            p0pfs::Pmr,
3966            p0pfs::Pmr,
3967            P0Pfs_SPEC,
3968            crate::common::RW,
3969        >::from_register(self, 0)
3970    }
3971
3972    #[doc = "Peripheral Select"]
3973    #[inline(always)]
3974    pub fn psel(
3975        self,
3976    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P0Pfs_SPEC, crate::common::RW> {
3977        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P0Pfs_SPEC,crate::common::RW>::from_register(self,0)
3978    }
3979}
3980impl ::core::default::Default for P0Pfs {
3981    #[inline(always)]
3982    fn default() -> P0Pfs {
3983        <crate::RegValueT<P0Pfs_SPEC> as RegisterValue<_>>::new(0)
3984    }
3985}
3986pub mod p0pfs {
3987
3988    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3989    pub struct Podr_SPEC;
3990    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3991    impl Podr {
3992        #[doc = "Output low"]
3993        pub const _0: Self = Self::new(0);
3994
3995        #[doc = "Output high"]
3996        pub const _1: Self = Self::new(1);
3997    }
3998    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3999    pub struct Pidr_SPEC;
4000    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4001    impl Pidr {
4002        #[doc = "Low level"]
4003        pub const _0: Self = Self::new(0);
4004
4005        #[doc = "High level"]
4006        pub const _1: Self = Self::new(1);
4007    }
4008    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4009    pub struct Pdr_SPEC;
4010    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4011    impl Pdr {
4012        #[doc = "Input (functions as an input pin)"]
4013        pub const _0: Self = Self::new(0);
4014
4015        #[doc = "Output (functions as an output pin)"]
4016        pub const _1: Self = Self::new(1);
4017    }
4018    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4019    pub struct Pcr_SPEC;
4020    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4021    impl Pcr {
4022        #[doc = "Disable input pull-up"]
4023        pub const _0: Self = Self::new(0);
4024
4025        #[doc = "Enable input pull-up"]
4026        pub const _1: Self = Self::new(1);
4027    }
4028    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4029    pub struct Ncodr_SPEC;
4030    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4031    impl Ncodr {
4032        #[doc = "Output CMOS"]
4033        pub const _0: Self = Self::new(0);
4034
4035        #[doc = "Output NMOS open-drain"]
4036        pub const _1: Self = Self::new(1);
4037    }
4038    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4039    pub struct Dscr_SPEC;
4040    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
4041    impl Dscr {
4042        #[doc = "Low drive"]
4043        pub const _00: Self = Self::new(0);
4044
4045        #[doc = "Middle drive"]
4046        pub const _01: Self = Self::new(1);
4047
4048        #[doc = "Setting prohibited"]
4049        pub const _10: Self = Self::new(2);
4050
4051        #[doc = "High drive"]
4052        pub const _11: Self = Self::new(3);
4053    }
4054    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4055    pub struct Eofr_SPEC;
4056    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
4057    impl Eofr {
4058        #[doc = "Don\'t care"]
4059        pub const _00: Self = Self::new(0);
4060
4061        #[doc = "Detect rising edge"]
4062        pub const _01: Self = Self::new(1);
4063
4064        #[doc = "Detect falling edge"]
4065        pub const _10: Self = Self::new(2);
4066
4067        #[doc = "Detect both edges"]
4068        pub const _11: Self = Self::new(3);
4069    }
4070    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4071    pub struct Isel_SPEC;
4072    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
4073    impl Isel {
4074        #[doc = "Do not use as IRQn input pin"]
4075        pub const _0: Self = Self::new(0);
4076
4077        #[doc = "Use as IRQn input pin"]
4078        pub const _1: Self = Self::new(1);
4079    }
4080    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4081    pub struct Asel_SPEC;
4082    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4083    impl Asel {
4084        #[doc = "Do not use as analog pin"]
4085        pub const _0: Self = Self::new(0);
4086
4087        #[doc = "Use as analog pin"]
4088        pub const _1: Self = Self::new(1);
4089    }
4090    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4091    pub struct Pmr_SPEC;
4092    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
4093    impl Pmr {
4094        #[doc = "Use as general I/O pin"]
4095        pub const _0: Self = Self::new(0);
4096
4097        #[doc = "Use as I/O port for peripheral functions"]
4098        pub const _1: Self = Self::new(1);
4099    }
4100}
4101#[doc(hidden)]
4102#[derive(Copy, Clone, Eq, PartialEq)]
4103pub struct P0PfsHa_SPEC;
4104impl crate::sealed::RegSpec for P0PfsHa_SPEC {
4105    type DataType = u16;
4106}
4107
4108#[doc = "Port 0%s Pin Function Select Register"]
4109pub type P0PfsHa = crate::RegValueT<P0PfsHa_SPEC>;
4110
4111impl P0PfsHa {
4112    #[doc = "Port Output Data"]
4113    #[inline(always)]
4114    pub fn podr(
4115        self,
4116    ) -> crate::common::RegisterField<
4117        0,
4118        0x1,
4119        1,
4120        0,
4121        p0pfs_ha::Podr,
4122        p0pfs_ha::Podr,
4123        P0PfsHa_SPEC,
4124        crate::common::RW,
4125    > {
4126        crate::common::RegisterField::<
4127            0,
4128            0x1,
4129            1,
4130            0,
4131            p0pfs_ha::Podr,
4132            p0pfs_ha::Podr,
4133            P0PfsHa_SPEC,
4134            crate::common::RW,
4135        >::from_register(self, 0)
4136    }
4137
4138    #[doc = "Port State"]
4139    #[inline(always)]
4140    pub fn pidr(
4141        self,
4142    ) -> crate::common::RegisterField<
4143        1,
4144        0x1,
4145        1,
4146        0,
4147        p0pfs_ha::Pidr,
4148        p0pfs_ha::Pidr,
4149        P0PfsHa_SPEC,
4150        crate::common::R,
4151    > {
4152        crate::common::RegisterField::<
4153            1,
4154            0x1,
4155            1,
4156            0,
4157            p0pfs_ha::Pidr,
4158            p0pfs_ha::Pidr,
4159            P0PfsHa_SPEC,
4160            crate::common::R,
4161        >::from_register(self, 0)
4162    }
4163
4164    #[doc = "Port Direction"]
4165    #[inline(always)]
4166    pub fn pdr(
4167        self,
4168    ) -> crate::common::RegisterField<
4169        2,
4170        0x1,
4171        1,
4172        0,
4173        p0pfs_ha::Pdr,
4174        p0pfs_ha::Pdr,
4175        P0PfsHa_SPEC,
4176        crate::common::RW,
4177    > {
4178        crate::common::RegisterField::<
4179            2,
4180            0x1,
4181            1,
4182            0,
4183            p0pfs_ha::Pdr,
4184            p0pfs_ha::Pdr,
4185            P0PfsHa_SPEC,
4186            crate::common::RW,
4187        >::from_register(self, 0)
4188    }
4189
4190    #[doc = "Pull-up Control"]
4191    #[inline(always)]
4192    pub fn pcr(
4193        self,
4194    ) -> crate::common::RegisterField<
4195        4,
4196        0x1,
4197        1,
4198        0,
4199        p0pfs_ha::Pcr,
4200        p0pfs_ha::Pcr,
4201        P0PfsHa_SPEC,
4202        crate::common::RW,
4203    > {
4204        crate::common::RegisterField::<
4205            4,
4206            0x1,
4207            1,
4208            0,
4209            p0pfs_ha::Pcr,
4210            p0pfs_ha::Pcr,
4211            P0PfsHa_SPEC,
4212            crate::common::RW,
4213        >::from_register(self, 0)
4214    }
4215
4216    #[doc = "N-Channel Open-Drain Control"]
4217    #[inline(always)]
4218    pub fn ncodr(
4219        self,
4220    ) -> crate::common::RegisterField<
4221        6,
4222        0x1,
4223        1,
4224        0,
4225        p0pfs_ha::Ncodr,
4226        p0pfs_ha::Ncodr,
4227        P0PfsHa_SPEC,
4228        crate::common::RW,
4229    > {
4230        crate::common::RegisterField::<
4231            6,
4232            0x1,
4233            1,
4234            0,
4235            p0pfs_ha::Ncodr,
4236            p0pfs_ha::Ncodr,
4237            P0PfsHa_SPEC,
4238            crate::common::RW,
4239        >::from_register(self, 0)
4240    }
4241
4242    #[doc = "Port Drive Capability"]
4243    #[inline(always)]
4244    pub fn dscr(
4245        self,
4246    ) -> crate::common::RegisterField<
4247        10,
4248        0x3,
4249        1,
4250        0,
4251        p0pfs_ha::Dscr,
4252        p0pfs_ha::Dscr,
4253        P0PfsHa_SPEC,
4254        crate::common::RW,
4255    > {
4256        crate::common::RegisterField::<
4257            10,
4258            0x3,
4259            1,
4260            0,
4261            p0pfs_ha::Dscr,
4262            p0pfs_ha::Dscr,
4263            P0PfsHa_SPEC,
4264            crate::common::RW,
4265        >::from_register(self, 0)
4266    }
4267
4268    #[doc = "Event on Falling/Event on Rising"]
4269    #[inline(always)]
4270    pub fn eofr(
4271        self,
4272    ) -> crate::common::RegisterField<
4273        12,
4274        0x3,
4275        1,
4276        0,
4277        p0pfs_ha::Eofr,
4278        p0pfs_ha::Eofr,
4279        P0PfsHa_SPEC,
4280        crate::common::RW,
4281    > {
4282        crate::common::RegisterField::<
4283            12,
4284            0x3,
4285            1,
4286            0,
4287            p0pfs_ha::Eofr,
4288            p0pfs_ha::Eofr,
4289            P0PfsHa_SPEC,
4290            crate::common::RW,
4291        >::from_register(self, 0)
4292    }
4293
4294    #[doc = "IRQ Input Enable"]
4295    #[inline(always)]
4296    pub fn isel(
4297        self,
4298    ) -> crate::common::RegisterField<
4299        14,
4300        0x1,
4301        1,
4302        0,
4303        p0pfs_ha::Isel,
4304        p0pfs_ha::Isel,
4305        P0PfsHa_SPEC,
4306        crate::common::RW,
4307    > {
4308        crate::common::RegisterField::<
4309            14,
4310            0x1,
4311            1,
4312            0,
4313            p0pfs_ha::Isel,
4314            p0pfs_ha::Isel,
4315            P0PfsHa_SPEC,
4316            crate::common::RW,
4317        >::from_register(self, 0)
4318    }
4319
4320    #[doc = "Analog Input Enable"]
4321    #[inline(always)]
4322    pub fn asel(
4323        self,
4324    ) -> crate::common::RegisterField<
4325        15,
4326        0x1,
4327        1,
4328        0,
4329        p0pfs_ha::Asel,
4330        p0pfs_ha::Asel,
4331        P0PfsHa_SPEC,
4332        crate::common::RW,
4333    > {
4334        crate::common::RegisterField::<
4335            15,
4336            0x1,
4337            1,
4338            0,
4339            p0pfs_ha::Asel,
4340            p0pfs_ha::Asel,
4341            P0PfsHa_SPEC,
4342            crate::common::RW,
4343        >::from_register(self, 0)
4344    }
4345}
4346impl ::core::default::Default for P0PfsHa {
4347    #[inline(always)]
4348    fn default() -> P0PfsHa {
4349        <crate::RegValueT<P0PfsHa_SPEC> as RegisterValue<_>>::new(0)
4350    }
4351}
4352pub mod p0pfs_ha {
4353
4354    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4355    pub struct Podr_SPEC;
4356    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4357    impl Podr {
4358        #[doc = "Output low"]
4359        pub const _0: Self = Self::new(0);
4360
4361        #[doc = "Output high"]
4362        pub const _1: Self = Self::new(1);
4363    }
4364    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4365    pub struct Pidr_SPEC;
4366    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4367    impl Pidr {
4368        #[doc = "Low level"]
4369        pub const _0: Self = Self::new(0);
4370
4371        #[doc = "High level"]
4372        pub const _1: Self = Self::new(1);
4373    }
4374    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4375    pub struct Pdr_SPEC;
4376    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4377    impl Pdr {
4378        #[doc = "Input (functions as an input pin)"]
4379        pub const _0: Self = Self::new(0);
4380
4381        #[doc = "Output (functions as an output pin)"]
4382        pub const _1: Self = Self::new(1);
4383    }
4384    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4385    pub struct Pcr_SPEC;
4386    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4387    impl Pcr {
4388        #[doc = "Disable input pull-up"]
4389        pub const _0: Self = Self::new(0);
4390
4391        #[doc = "Enable input pull-up"]
4392        pub const _1: Self = Self::new(1);
4393    }
4394    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4395    pub struct Ncodr_SPEC;
4396    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4397    impl Ncodr {
4398        #[doc = "Output CMOS"]
4399        pub const _0: Self = Self::new(0);
4400
4401        #[doc = "Output NMOS open-drain"]
4402        pub const _1: Self = Self::new(1);
4403    }
4404    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4405    pub struct Dscr_SPEC;
4406    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
4407    impl Dscr {
4408        #[doc = "Low drive"]
4409        pub const _00: Self = Self::new(0);
4410
4411        #[doc = "Middle drive"]
4412        pub const _01: Self = Self::new(1);
4413
4414        #[doc = "Setting prohibited"]
4415        pub const _10: Self = Self::new(2);
4416
4417        #[doc = "High drive"]
4418        pub const _11: Self = Self::new(3);
4419    }
4420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4421    pub struct Eofr_SPEC;
4422    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
4423    impl Eofr {
4424        #[doc = "Don\'t care"]
4425        pub const _00: Self = Self::new(0);
4426
4427        #[doc = "Detect rising edge"]
4428        pub const _01: Self = Self::new(1);
4429
4430        #[doc = "Detect falling edge"]
4431        pub const _10: Self = Self::new(2);
4432
4433        #[doc = "Detect both edges"]
4434        pub const _11: Self = Self::new(3);
4435    }
4436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4437    pub struct Isel_SPEC;
4438    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
4439    impl Isel {
4440        #[doc = "Do not use as IRQn input pin"]
4441        pub const _0: Self = Self::new(0);
4442
4443        #[doc = "Use as IRQn input pin"]
4444        pub const _1: Self = Self::new(1);
4445    }
4446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4447    pub struct Asel_SPEC;
4448    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4449    impl Asel {
4450        #[doc = "Do not use as analog pin"]
4451        pub const _0: Self = Self::new(0);
4452
4453        #[doc = "Use as analog pin"]
4454        pub const _1: Self = Self::new(1);
4455    }
4456}
4457#[doc(hidden)]
4458#[derive(Copy, Clone, Eq, PartialEq)]
4459pub struct P0PfsBy_SPEC;
4460impl crate::sealed::RegSpec for P0PfsBy_SPEC {
4461    type DataType = u8;
4462}
4463
4464#[doc = "Port 0%s Pin Function Select Register"]
4465pub type P0PfsBy = crate::RegValueT<P0PfsBy_SPEC>;
4466
4467impl P0PfsBy {
4468    #[doc = "Port Output Data"]
4469    #[inline(always)]
4470    pub fn podr(
4471        self,
4472    ) -> crate::common::RegisterField<
4473        0,
4474        0x1,
4475        1,
4476        0,
4477        p0pfs_by::Podr,
4478        p0pfs_by::Podr,
4479        P0PfsBy_SPEC,
4480        crate::common::RW,
4481    > {
4482        crate::common::RegisterField::<
4483            0,
4484            0x1,
4485            1,
4486            0,
4487            p0pfs_by::Podr,
4488            p0pfs_by::Podr,
4489            P0PfsBy_SPEC,
4490            crate::common::RW,
4491        >::from_register(self, 0)
4492    }
4493
4494    #[doc = "Port State"]
4495    #[inline(always)]
4496    pub fn pidr(
4497        self,
4498    ) -> crate::common::RegisterField<
4499        1,
4500        0x1,
4501        1,
4502        0,
4503        p0pfs_by::Pidr,
4504        p0pfs_by::Pidr,
4505        P0PfsBy_SPEC,
4506        crate::common::R,
4507    > {
4508        crate::common::RegisterField::<
4509            1,
4510            0x1,
4511            1,
4512            0,
4513            p0pfs_by::Pidr,
4514            p0pfs_by::Pidr,
4515            P0PfsBy_SPEC,
4516            crate::common::R,
4517        >::from_register(self, 0)
4518    }
4519
4520    #[doc = "Port Direction"]
4521    #[inline(always)]
4522    pub fn pdr(
4523        self,
4524    ) -> crate::common::RegisterField<
4525        2,
4526        0x1,
4527        1,
4528        0,
4529        p0pfs_by::Pdr,
4530        p0pfs_by::Pdr,
4531        P0PfsBy_SPEC,
4532        crate::common::RW,
4533    > {
4534        crate::common::RegisterField::<
4535            2,
4536            0x1,
4537            1,
4538            0,
4539            p0pfs_by::Pdr,
4540            p0pfs_by::Pdr,
4541            P0PfsBy_SPEC,
4542            crate::common::RW,
4543        >::from_register(self, 0)
4544    }
4545
4546    #[doc = "Pull-up Control"]
4547    #[inline(always)]
4548    pub fn pcr(
4549        self,
4550    ) -> crate::common::RegisterField<
4551        4,
4552        0x1,
4553        1,
4554        0,
4555        p0pfs_by::Pcr,
4556        p0pfs_by::Pcr,
4557        P0PfsBy_SPEC,
4558        crate::common::RW,
4559    > {
4560        crate::common::RegisterField::<
4561            4,
4562            0x1,
4563            1,
4564            0,
4565            p0pfs_by::Pcr,
4566            p0pfs_by::Pcr,
4567            P0PfsBy_SPEC,
4568            crate::common::RW,
4569        >::from_register(self, 0)
4570    }
4571
4572    #[doc = "N-Channel Open-Drain Control"]
4573    #[inline(always)]
4574    pub fn ncodr(
4575        self,
4576    ) -> crate::common::RegisterField<
4577        6,
4578        0x1,
4579        1,
4580        0,
4581        p0pfs_by::Ncodr,
4582        p0pfs_by::Ncodr,
4583        P0PfsBy_SPEC,
4584        crate::common::RW,
4585    > {
4586        crate::common::RegisterField::<
4587            6,
4588            0x1,
4589            1,
4590            0,
4591            p0pfs_by::Ncodr,
4592            p0pfs_by::Ncodr,
4593            P0PfsBy_SPEC,
4594            crate::common::RW,
4595        >::from_register(self, 0)
4596    }
4597}
4598impl ::core::default::Default for P0PfsBy {
4599    #[inline(always)]
4600    fn default() -> P0PfsBy {
4601        <crate::RegValueT<P0PfsBy_SPEC> as RegisterValue<_>>::new(0)
4602    }
4603}
4604pub mod p0pfs_by {
4605
4606    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4607    pub struct Podr_SPEC;
4608    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4609    impl Podr {
4610        #[doc = "Output low"]
4611        pub const _0: Self = Self::new(0);
4612
4613        #[doc = "Output high"]
4614        pub const _1: Self = Self::new(1);
4615    }
4616    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4617    pub struct Pidr_SPEC;
4618    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4619    impl Pidr {
4620        #[doc = "Low level"]
4621        pub const _0: Self = Self::new(0);
4622
4623        #[doc = "High level"]
4624        pub const _1: Self = Self::new(1);
4625    }
4626    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4627    pub struct Pdr_SPEC;
4628    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4629    impl Pdr {
4630        #[doc = "Input (functions as an input pin)"]
4631        pub const _0: Self = Self::new(0);
4632
4633        #[doc = "Output (functions as an output pin)"]
4634        pub const _1: Self = Self::new(1);
4635    }
4636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4637    pub struct Pcr_SPEC;
4638    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4639    impl Pcr {
4640        #[doc = "Disable input pull-up"]
4641        pub const _0: Self = Self::new(0);
4642
4643        #[doc = "Enable input pull-up"]
4644        pub const _1: Self = Self::new(1);
4645    }
4646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4647    pub struct Ncodr_SPEC;
4648    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4649    impl Ncodr {
4650        #[doc = "Output CMOS"]
4651        pub const _0: Self = Self::new(0);
4652
4653        #[doc = "Output NMOS open-drain"]
4654        pub const _1: Self = Self::new(1);
4655    }
4656}
4657#[doc(hidden)]
4658#[derive(Copy, Clone, Eq, PartialEq)]
4659pub struct P10Pfs_SPEC;
4660impl crate::sealed::RegSpec for P10Pfs_SPEC {
4661    type DataType = u32;
4662}
4663
4664#[doc = "Port 10%s Pin Function Select Register"]
4665pub type P10Pfs = crate::RegValueT<P10Pfs_SPEC>;
4666
4667impl P10Pfs {
4668    #[doc = "Port Output Data"]
4669    #[inline(always)]
4670    pub fn podr(
4671        self,
4672    ) -> crate::common::RegisterField<
4673        0,
4674        0x1,
4675        1,
4676        0,
4677        p10pfs::Podr,
4678        p10pfs::Podr,
4679        P10Pfs_SPEC,
4680        crate::common::RW,
4681    > {
4682        crate::common::RegisterField::<
4683            0,
4684            0x1,
4685            1,
4686            0,
4687            p10pfs::Podr,
4688            p10pfs::Podr,
4689            P10Pfs_SPEC,
4690            crate::common::RW,
4691        >::from_register(self, 0)
4692    }
4693
4694    #[doc = "Port State"]
4695    #[inline(always)]
4696    pub fn pidr(
4697        self,
4698    ) -> crate::common::RegisterField<
4699        1,
4700        0x1,
4701        1,
4702        0,
4703        p10pfs::Pidr,
4704        p10pfs::Pidr,
4705        P10Pfs_SPEC,
4706        crate::common::R,
4707    > {
4708        crate::common::RegisterField::<
4709            1,
4710            0x1,
4711            1,
4712            0,
4713            p10pfs::Pidr,
4714            p10pfs::Pidr,
4715            P10Pfs_SPEC,
4716            crate::common::R,
4717        >::from_register(self, 0)
4718    }
4719
4720    #[doc = "Port Direction"]
4721    #[inline(always)]
4722    pub fn pdr(
4723        self,
4724    ) -> crate::common::RegisterField<
4725        2,
4726        0x1,
4727        1,
4728        0,
4729        p10pfs::Pdr,
4730        p10pfs::Pdr,
4731        P10Pfs_SPEC,
4732        crate::common::RW,
4733    > {
4734        crate::common::RegisterField::<
4735            2,
4736            0x1,
4737            1,
4738            0,
4739            p10pfs::Pdr,
4740            p10pfs::Pdr,
4741            P10Pfs_SPEC,
4742            crate::common::RW,
4743        >::from_register(self, 0)
4744    }
4745
4746    #[doc = "Pull-up Control"]
4747    #[inline(always)]
4748    pub fn pcr(
4749        self,
4750    ) -> crate::common::RegisterField<
4751        4,
4752        0x1,
4753        1,
4754        0,
4755        p10pfs::Pcr,
4756        p10pfs::Pcr,
4757        P10Pfs_SPEC,
4758        crate::common::RW,
4759    > {
4760        crate::common::RegisterField::<
4761            4,
4762            0x1,
4763            1,
4764            0,
4765            p10pfs::Pcr,
4766            p10pfs::Pcr,
4767            P10Pfs_SPEC,
4768            crate::common::RW,
4769        >::from_register(self, 0)
4770    }
4771
4772    #[doc = "N-Channel Open-Drain Control"]
4773    #[inline(always)]
4774    pub fn ncodr(
4775        self,
4776    ) -> crate::common::RegisterField<
4777        6,
4778        0x1,
4779        1,
4780        0,
4781        p10pfs::Ncodr,
4782        p10pfs::Ncodr,
4783        P10Pfs_SPEC,
4784        crate::common::RW,
4785    > {
4786        crate::common::RegisterField::<
4787            6,
4788            0x1,
4789            1,
4790            0,
4791            p10pfs::Ncodr,
4792            p10pfs::Ncodr,
4793            P10Pfs_SPEC,
4794            crate::common::RW,
4795        >::from_register(self, 0)
4796    }
4797
4798    #[doc = "Port Drive Capability"]
4799    #[inline(always)]
4800    pub fn dscr(
4801        self,
4802    ) -> crate::common::RegisterField<
4803        10,
4804        0x3,
4805        1,
4806        0,
4807        p10pfs::Dscr,
4808        p10pfs::Dscr,
4809        P10Pfs_SPEC,
4810        crate::common::RW,
4811    > {
4812        crate::common::RegisterField::<
4813            10,
4814            0x3,
4815            1,
4816            0,
4817            p10pfs::Dscr,
4818            p10pfs::Dscr,
4819            P10Pfs_SPEC,
4820            crate::common::RW,
4821        >::from_register(self, 0)
4822    }
4823
4824    #[doc = "Event on Falling/Event on Rising"]
4825    #[inline(always)]
4826    pub fn eofr(
4827        self,
4828    ) -> crate::common::RegisterField<
4829        12,
4830        0x3,
4831        1,
4832        0,
4833        p10pfs::Eofr,
4834        p10pfs::Eofr,
4835        P10Pfs_SPEC,
4836        crate::common::RW,
4837    > {
4838        crate::common::RegisterField::<
4839            12,
4840            0x3,
4841            1,
4842            0,
4843            p10pfs::Eofr,
4844            p10pfs::Eofr,
4845            P10Pfs_SPEC,
4846            crate::common::RW,
4847        >::from_register(self, 0)
4848    }
4849
4850    #[doc = "IRQ Input Enable"]
4851    #[inline(always)]
4852    pub fn isel(
4853        self,
4854    ) -> crate::common::RegisterField<
4855        14,
4856        0x1,
4857        1,
4858        0,
4859        p10pfs::Isel,
4860        p10pfs::Isel,
4861        P10Pfs_SPEC,
4862        crate::common::RW,
4863    > {
4864        crate::common::RegisterField::<
4865            14,
4866            0x1,
4867            1,
4868            0,
4869            p10pfs::Isel,
4870            p10pfs::Isel,
4871            P10Pfs_SPEC,
4872            crate::common::RW,
4873        >::from_register(self, 0)
4874    }
4875
4876    #[doc = "Analog Input Enable"]
4877    #[inline(always)]
4878    pub fn asel(
4879        self,
4880    ) -> crate::common::RegisterField<
4881        15,
4882        0x1,
4883        1,
4884        0,
4885        p10pfs::Asel,
4886        p10pfs::Asel,
4887        P10Pfs_SPEC,
4888        crate::common::RW,
4889    > {
4890        crate::common::RegisterField::<
4891            15,
4892            0x1,
4893            1,
4894            0,
4895            p10pfs::Asel,
4896            p10pfs::Asel,
4897            P10Pfs_SPEC,
4898            crate::common::RW,
4899        >::from_register(self, 0)
4900    }
4901
4902    #[doc = "Port Mode Control"]
4903    #[inline(always)]
4904    pub fn pmr(
4905        self,
4906    ) -> crate::common::RegisterField<
4907        16,
4908        0x1,
4909        1,
4910        0,
4911        p10pfs::Pmr,
4912        p10pfs::Pmr,
4913        P10Pfs_SPEC,
4914        crate::common::RW,
4915    > {
4916        crate::common::RegisterField::<
4917            16,
4918            0x1,
4919            1,
4920            0,
4921            p10pfs::Pmr,
4922            p10pfs::Pmr,
4923            P10Pfs_SPEC,
4924            crate::common::RW,
4925        >::from_register(self, 0)
4926    }
4927
4928    #[doc = "Peripheral Select"]
4929    #[inline(always)]
4930    pub fn psel(
4931        self,
4932    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P10Pfs_SPEC, crate::common::RW> {
4933        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P10Pfs_SPEC,crate::common::RW>::from_register(self,0)
4934    }
4935}
4936impl ::core::default::Default for P10Pfs {
4937    #[inline(always)]
4938    fn default() -> P10Pfs {
4939        <crate::RegValueT<P10Pfs_SPEC> as RegisterValue<_>>::new(0)
4940    }
4941}
4942pub mod p10pfs {
4943
4944    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4945    pub struct Podr_SPEC;
4946    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4947    impl Podr {
4948        #[doc = "Output low"]
4949        pub const _0: Self = Self::new(0);
4950
4951        #[doc = "Output high"]
4952        pub const _1: Self = Self::new(1);
4953    }
4954    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4955    pub struct Pidr_SPEC;
4956    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4957    impl Pidr {
4958        #[doc = "Low level"]
4959        pub const _0: Self = Self::new(0);
4960
4961        #[doc = "High level"]
4962        pub const _1: Self = Self::new(1);
4963    }
4964    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4965    pub struct Pdr_SPEC;
4966    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4967    impl Pdr {
4968        #[doc = "Input (functions as an input pin)"]
4969        pub const _0: Self = Self::new(0);
4970
4971        #[doc = "Output (functions as an output pin)"]
4972        pub const _1: Self = Self::new(1);
4973    }
4974    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4975    pub struct Pcr_SPEC;
4976    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4977    impl Pcr {
4978        #[doc = "Disable input pull-up"]
4979        pub const _0: Self = Self::new(0);
4980
4981        #[doc = "Enable input pull-up"]
4982        pub const _1: Self = Self::new(1);
4983    }
4984    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4985    pub struct Ncodr_SPEC;
4986    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4987    impl Ncodr {
4988        #[doc = "Output CMOS"]
4989        pub const _0: Self = Self::new(0);
4990
4991        #[doc = "Output NMOS open-drain"]
4992        pub const _1: Self = Self::new(1);
4993    }
4994    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4995    pub struct Dscr_SPEC;
4996    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
4997    impl Dscr {
4998        #[doc = "Low drive"]
4999        pub const _00: Self = Self::new(0);
5000
5001        #[doc = "Middle drive"]
5002        pub const _01: Self = Self::new(1);
5003
5004        #[doc = "Setting prohibited"]
5005        pub const _10: Self = Self::new(2);
5006
5007        #[doc = "High drive"]
5008        pub const _11: Self = Self::new(3);
5009    }
5010    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5011    pub struct Eofr_SPEC;
5012    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
5013    impl Eofr {
5014        #[doc = "Don\'t care"]
5015        pub const _00: Self = Self::new(0);
5016
5017        #[doc = "Detect rising edge"]
5018        pub const _01: Self = Self::new(1);
5019
5020        #[doc = "Detect falling edge"]
5021        pub const _10: Self = Self::new(2);
5022
5023        #[doc = "Detect both edges"]
5024        pub const _11: Self = Self::new(3);
5025    }
5026    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5027    pub struct Isel_SPEC;
5028    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5029    impl Isel {
5030        #[doc = "Do not use as IRQn input pin"]
5031        pub const _0: Self = Self::new(0);
5032
5033        #[doc = "Use as IRQn input pin"]
5034        pub const _1: Self = Self::new(1);
5035    }
5036    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5037    pub struct Asel_SPEC;
5038    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
5039    impl Asel {
5040        #[doc = "Do not use as analog pin"]
5041        pub const _0: Self = Self::new(0);
5042
5043        #[doc = "Use as analog pin"]
5044        pub const _1: Self = Self::new(1);
5045    }
5046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5047    pub struct Pmr_SPEC;
5048    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
5049    impl Pmr {
5050        #[doc = "Use as general I/O pin"]
5051        pub const _0: Self = Self::new(0);
5052
5053        #[doc = "Use as I/O port for peripheral functions"]
5054        pub const _1: Self = Self::new(1);
5055    }
5056}
5057#[doc(hidden)]
5058#[derive(Copy, Clone, Eq, PartialEq)]
5059pub struct P10PfsHa_SPEC;
5060impl crate::sealed::RegSpec for P10PfsHa_SPEC {
5061    type DataType = u16;
5062}
5063
5064#[doc = "Port 10%s Pin Function Select Register"]
5065pub type P10PfsHa = crate::RegValueT<P10PfsHa_SPEC>;
5066
5067impl P10PfsHa {
5068    #[doc = "Port Output Data"]
5069    #[inline(always)]
5070    pub fn podr(
5071        self,
5072    ) -> crate::common::RegisterField<
5073        0,
5074        0x1,
5075        1,
5076        0,
5077        p10pfs_ha::Podr,
5078        p10pfs_ha::Podr,
5079        P10PfsHa_SPEC,
5080        crate::common::RW,
5081    > {
5082        crate::common::RegisterField::<
5083            0,
5084            0x1,
5085            1,
5086            0,
5087            p10pfs_ha::Podr,
5088            p10pfs_ha::Podr,
5089            P10PfsHa_SPEC,
5090            crate::common::RW,
5091        >::from_register(self, 0)
5092    }
5093
5094    #[doc = "Port State"]
5095    #[inline(always)]
5096    pub fn pidr(
5097        self,
5098    ) -> crate::common::RegisterField<
5099        1,
5100        0x1,
5101        1,
5102        0,
5103        p10pfs_ha::Pidr,
5104        p10pfs_ha::Pidr,
5105        P10PfsHa_SPEC,
5106        crate::common::R,
5107    > {
5108        crate::common::RegisterField::<
5109            1,
5110            0x1,
5111            1,
5112            0,
5113            p10pfs_ha::Pidr,
5114            p10pfs_ha::Pidr,
5115            P10PfsHa_SPEC,
5116            crate::common::R,
5117        >::from_register(self, 0)
5118    }
5119
5120    #[doc = "Port Direction"]
5121    #[inline(always)]
5122    pub fn pdr(
5123        self,
5124    ) -> crate::common::RegisterField<
5125        2,
5126        0x1,
5127        1,
5128        0,
5129        p10pfs_ha::Pdr,
5130        p10pfs_ha::Pdr,
5131        P10PfsHa_SPEC,
5132        crate::common::RW,
5133    > {
5134        crate::common::RegisterField::<
5135            2,
5136            0x1,
5137            1,
5138            0,
5139            p10pfs_ha::Pdr,
5140            p10pfs_ha::Pdr,
5141            P10PfsHa_SPEC,
5142            crate::common::RW,
5143        >::from_register(self, 0)
5144    }
5145
5146    #[doc = "Pull-up Control"]
5147    #[inline(always)]
5148    pub fn pcr(
5149        self,
5150    ) -> crate::common::RegisterField<
5151        4,
5152        0x1,
5153        1,
5154        0,
5155        p10pfs_ha::Pcr,
5156        p10pfs_ha::Pcr,
5157        P10PfsHa_SPEC,
5158        crate::common::RW,
5159    > {
5160        crate::common::RegisterField::<
5161            4,
5162            0x1,
5163            1,
5164            0,
5165            p10pfs_ha::Pcr,
5166            p10pfs_ha::Pcr,
5167            P10PfsHa_SPEC,
5168            crate::common::RW,
5169        >::from_register(self, 0)
5170    }
5171
5172    #[doc = "N-Channel Open-Drain Control"]
5173    #[inline(always)]
5174    pub fn ncodr(
5175        self,
5176    ) -> crate::common::RegisterField<
5177        6,
5178        0x1,
5179        1,
5180        0,
5181        p10pfs_ha::Ncodr,
5182        p10pfs_ha::Ncodr,
5183        P10PfsHa_SPEC,
5184        crate::common::RW,
5185    > {
5186        crate::common::RegisterField::<
5187            6,
5188            0x1,
5189            1,
5190            0,
5191            p10pfs_ha::Ncodr,
5192            p10pfs_ha::Ncodr,
5193            P10PfsHa_SPEC,
5194            crate::common::RW,
5195        >::from_register(self, 0)
5196    }
5197
5198    #[doc = "Port Drive Capability"]
5199    #[inline(always)]
5200    pub fn dscr(
5201        self,
5202    ) -> crate::common::RegisterField<
5203        10,
5204        0x3,
5205        1,
5206        0,
5207        p10pfs_ha::Dscr,
5208        p10pfs_ha::Dscr,
5209        P10PfsHa_SPEC,
5210        crate::common::RW,
5211    > {
5212        crate::common::RegisterField::<
5213            10,
5214            0x3,
5215            1,
5216            0,
5217            p10pfs_ha::Dscr,
5218            p10pfs_ha::Dscr,
5219            P10PfsHa_SPEC,
5220            crate::common::RW,
5221        >::from_register(self, 0)
5222    }
5223
5224    #[doc = "Event on Falling/Event on Rising"]
5225    #[inline(always)]
5226    pub fn eofr(
5227        self,
5228    ) -> crate::common::RegisterField<
5229        12,
5230        0x3,
5231        1,
5232        0,
5233        p10pfs_ha::Eofr,
5234        p10pfs_ha::Eofr,
5235        P10PfsHa_SPEC,
5236        crate::common::RW,
5237    > {
5238        crate::common::RegisterField::<
5239            12,
5240            0x3,
5241            1,
5242            0,
5243            p10pfs_ha::Eofr,
5244            p10pfs_ha::Eofr,
5245            P10PfsHa_SPEC,
5246            crate::common::RW,
5247        >::from_register(self, 0)
5248    }
5249
5250    #[doc = "IRQ Input Enable"]
5251    #[inline(always)]
5252    pub fn isel(
5253        self,
5254    ) -> crate::common::RegisterField<
5255        14,
5256        0x1,
5257        1,
5258        0,
5259        p10pfs_ha::Isel,
5260        p10pfs_ha::Isel,
5261        P10PfsHa_SPEC,
5262        crate::common::RW,
5263    > {
5264        crate::common::RegisterField::<
5265            14,
5266            0x1,
5267            1,
5268            0,
5269            p10pfs_ha::Isel,
5270            p10pfs_ha::Isel,
5271            P10PfsHa_SPEC,
5272            crate::common::RW,
5273        >::from_register(self, 0)
5274    }
5275
5276    #[doc = "Analog Input Enable"]
5277    #[inline(always)]
5278    pub fn asel(
5279        self,
5280    ) -> crate::common::RegisterField<
5281        15,
5282        0x1,
5283        1,
5284        0,
5285        p10pfs_ha::Asel,
5286        p10pfs_ha::Asel,
5287        P10PfsHa_SPEC,
5288        crate::common::RW,
5289    > {
5290        crate::common::RegisterField::<
5291            15,
5292            0x1,
5293            1,
5294            0,
5295            p10pfs_ha::Asel,
5296            p10pfs_ha::Asel,
5297            P10PfsHa_SPEC,
5298            crate::common::RW,
5299        >::from_register(self, 0)
5300    }
5301}
5302impl ::core::default::Default for P10PfsHa {
5303    #[inline(always)]
5304    fn default() -> P10PfsHa {
5305        <crate::RegValueT<P10PfsHa_SPEC> as RegisterValue<_>>::new(0)
5306    }
5307}
5308pub mod p10pfs_ha {
5309
5310    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5311    pub struct Podr_SPEC;
5312    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5313    impl Podr {
5314        #[doc = "Output low"]
5315        pub const _0: Self = Self::new(0);
5316
5317        #[doc = "Output high"]
5318        pub const _1: Self = Self::new(1);
5319    }
5320    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5321    pub struct Pidr_SPEC;
5322    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5323    impl Pidr {
5324        #[doc = "Low level"]
5325        pub const _0: Self = Self::new(0);
5326
5327        #[doc = "High level"]
5328        pub const _1: Self = Self::new(1);
5329    }
5330    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5331    pub struct Pdr_SPEC;
5332    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5333    impl Pdr {
5334        #[doc = "Input (functions as an input pin)"]
5335        pub const _0: Self = Self::new(0);
5336
5337        #[doc = "Output (functions as an output pin)"]
5338        pub const _1: Self = Self::new(1);
5339    }
5340    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5341    pub struct Pcr_SPEC;
5342    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5343    impl Pcr {
5344        #[doc = "Disable input pull-up"]
5345        pub const _0: Self = Self::new(0);
5346
5347        #[doc = "Enable input pull-up"]
5348        pub const _1: Self = Self::new(1);
5349    }
5350    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5351    pub struct Ncodr_SPEC;
5352    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5353    impl Ncodr {
5354        #[doc = "Output CMOS"]
5355        pub const _0: Self = Self::new(0);
5356
5357        #[doc = "Output NMOS open-drain"]
5358        pub const _1: Self = Self::new(1);
5359    }
5360    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5361    pub struct Dscr_SPEC;
5362    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
5363    impl Dscr {
5364        #[doc = "Low drive"]
5365        pub const _00: Self = Self::new(0);
5366
5367        #[doc = "Middle drive"]
5368        pub const _01: Self = Self::new(1);
5369
5370        #[doc = "Setting prohibited"]
5371        pub const _10: Self = Self::new(2);
5372
5373        #[doc = "High drive"]
5374        pub const _11: Self = Self::new(3);
5375    }
5376    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5377    pub struct Eofr_SPEC;
5378    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
5379    impl Eofr {
5380        #[doc = "Don\'t care"]
5381        pub const _00: Self = Self::new(0);
5382
5383        #[doc = "Detect rising edge"]
5384        pub const _01: Self = Self::new(1);
5385
5386        #[doc = "Detect falling edge"]
5387        pub const _10: Self = Self::new(2);
5388
5389        #[doc = "Detect both edges"]
5390        pub const _11: Self = Self::new(3);
5391    }
5392    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5393    pub struct Isel_SPEC;
5394    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5395    impl Isel {
5396        #[doc = "Do not use as IRQn input pin"]
5397        pub const _0: Self = Self::new(0);
5398
5399        #[doc = "Use as IRQn input pin"]
5400        pub const _1: Self = Self::new(1);
5401    }
5402    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5403    pub struct Asel_SPEC;
5404    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
5405    impl Asel {
5406        #[doc = "Do not use as analog pin"]
5407        pub const _0: Self = Self::new(0);
5408
5409        #[doc = "Use as analog pin"]
5410        pub const _1: Self = Self::new(1);
5411    }
5412}
5413#[doc(hidden)]
5414#[derive(Copy, Clone, Eq, PartialEq)]
5415pub struct P10PfsBy_SPEC;
5416impl crate::sealed::RegSpec for P10PfsBy_SPEC {
5417    type DataType = u8;
5418}
5419
5420#[doc = "Port 10%s Pin Function Select Register"]
5421pub type P10PfsBy = crate::RegValueT<P10PfsBy_SPEC>;
5422
5423impl P10PfsBy {
5424    #[doc = "Port Output Data"]
5425    #[inline(always)]
5426    pub fn podr(
5427        self,
5428    ) -> crate::common::RegisterField<
5429        0,
5430        0x1,
5431        1,
5432        0,
5433        p10pfs_by::Podr,
5434        p10pfs_by::Podr,
5435        P10PfsBy_SPEC,
5436        crate::common::RW,
5437    > {
5438        crate::common::RegisterField::<
5439            0,
5440            0x1,
5441            1,
5442            0,
5443            p10pfs_by::Podr,
5444            p10pfs_by::Podr,
5445            P10PfsBy_SPEC,
5446            crate::common::RW,
5447        >::from_register(self, 0)
5448    }
5449
5450    #[doc = "Port State"]
5451    #[inline(always)]
5452    pub fn pidr(
5453        self,
5454    ) -> crate::common::RegisterField<
5455        1,
5456        0x1,
5457        1,
5458        0,
5459        p10pfs_by::Pidr,
5460        p10pfs_by::Pidr,
5461        P10PfsBy_SPEC,
5462        crate::common::R,
5463    > {
5464        crate::common::RegisterField::<
5465            1,
5466            0x1,
5467            1,
5468            0,
5469            p10pfs_by::Pidr,
5470            p10pfs_by::Pidr,
5471            P10PfsBy_SPEC,
5472            crate::common::R,
5473        >::from_register(self, 0)
5474    }
5475
5476    #[doc = "Port Direction"]
5477    #[inline(always)]
5478    pub fn pdr(
5479        self,
5480    ) -> crate::common::RegisterField<
5481        2,
5482        0x1,
5483        1,
5484        0,
5485        p10pfs_by::Pdr,
5486        p10pfs_by::Pdr,
5487        P10PfsBy_SPEC,
5488        crate::common::RW,
5489    > {
5490        crate::common::RegisterField::<
5491            2,
5492            0x1,
5493            1,
5494            0,
5495            p10pfs_by::Pdr,
5496            p10pfs_by::Pdr,
5497            P10PfsBy_SPEC,
5498            crate::common::RW,
5499        >::from_register(self, 0)
5500    }
5501
5502    #[doc = "Pull-up Control"]
5503    #[inline(always)]
5504    pub fn pcr(
5505        self,
5506    ) -> crate::common::RegisterField<
5507        4,
5508        0x1,
5509        1,
5510        0,
5511        p10pfs_by::Pcr,
5512        p10pfs_by::Pcr,
5513        P10PfsBy_SPEC,
5514        crate::common::RW,
5515    > {
5516        crate::common::RegisterField::<
5517            4,
5518            0x1,
5519            1,
5520            0,
5521            p10pfs_by::Pcr,
5522            p10pfs_by::Pcr,
5523            P10PfsBy_SPEC,
5524            crate::common::RW,
5525        >::from_register(self, 0)
5526    }
5527
5528    #[doc = "N-Channel Open-Drain Control"]
5529    #[inline(always)]
5530    pub fn ncodr(
5531        self,
5532    ) -> crate::common::RegisterField<
5533        6,
5534        0x1,
5535        1,
5536        0,
5537        p10pfs_by::Ncodr,
5538        p10pfs_by::Ncodr,
5539        P10PfsBy_SPEC,
5540        crate::common::RW,
5541    > {
5542        crate::common::RegisterField::<
5543            6,
5544            0x1,
5545            1,
5546            0,
5547            p10pfs_by::Ncodr,
5548            p10pfs_by::Ncodr,
5549            P10PfsBy_SPEC,
5550            crate::common::RW,
5551        >::from_register(self, 0)
5552    }
5553}
5554impl ::core::default::Default for P10PfsBy {
5555    #[inline(always)]
5556    fn default() -> P10PfsBy {
5557        <crate::RegValueT<P10PfsBy_SPEC> as RegisterValue<_>>::new(0)
5558    }
5559}
5560pub mod p10pfs_by {
5561
5562    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5563    pub struct Podr_SPEC;
5564    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5565    impl Podr {
5566        #[doc = "Output low"]
5567        pub const _0: Self = Self::new(0);
5568
5569        #[doc = "Output high"]
5570        pub const _1: Self = Self::new(1);
5571    }
5572    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5573    pub struct Pidr_SPEC;
5574    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5575    impl Pidr {
5576        #[doc = "Low level"]
5577        pub const _0: Self = Self::new(0);
5578
5579        #[doc = "High level"]
5580        pub const _1: Self = Self::new(1);
5581    }
5582    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5583    pub struct Pdr_SPEC;
5584    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5585    impl Pdr {
5586        #[doc = "Input (functions as an input pin)"]
5587        pub const _0: Self = Self::new(0);
5588
5589        #[doc = "Output (functions as an output pin)"]
5590        pub const _1: Self = Self::new(1);
5591    }
5592    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5593    pub struct Pcr_SPEC;
5594    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5595    impl Pcr {
5596        #[doc = "Disable input pull-up"]
5597        pub const _0: Self = Self::new(0);
5598
5599        #[doc = "Enable input pull-up"]
5600        pub const _1: Self = Self::new(1);
5601    }
5602    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5603    pub struct Ncodr_SPEC;
5604    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5605    impl Ncodr {
5606        #[doc = "Output CMOS"]
5607        pub const _0: Self = Self::new(0);
5608
5609        #[doc = "Output NMOS open-drain"]
5610        pub const _1: Self = Self::new(1);
5611    }
5612}
5613#[doc(hidden)]
5614#[derive(Copy, Clone, Eq, PartialEq)]
5615pub struct P1Pfs_SPEC;
5616impl crate::sealed::RegSpec for P1Pfs_SPEC {
5617    type DataType = u32;
5618}
5619
5620#[doc = "Port 1%s Pin Function Select Register"]
5621pub type P1Pfs = crate::RegValueT<P1Pfs_SPEC>;
5622
5623impl P1Pfs {
5624    #[doc = "Port Output Data"]
5625    #[inline(always)]
5626    pub fn podr(
5627        self,
5628    ) -> crate::common::RegisterField<
5629        0,
5630        0x1,
5631        1,
5632        0,
5633        p1pfs::Podr,
5634        p1pfs::Podr,
5635        P1Pfs_SPEC,
5636        crate::common::RW,
5637    > {
5638        crate::common::RegisterField::<
5639            0,
5640            0x1,
5641            1,
5642            0,
5643            p1pfs::Podr,
5644            p1pfs::Podr,
5645            P1Pfs_SPEC,
5646            crate::common::RW,
5647        >::from_register(self, 0)
5648    }
5649
5650    #[doc = "Port State"]
5651    #[inline(always)]
5652    pub fn pidr(
5653        self,
5654    ) -> crate::common::RegisterField<
5655        1,
5656        0x1,
5657        1,
5658        0,
5659        p1pfs::Pidr,
5660        p1pfs::Pidr,
5661        P1Pfs_SPEC,
5662        crate::common::R,
5663    > {
5664        crate::common::RegisterField::<
5665            1,
5666            0x1,
5667            1,
5668            0,
5669            p1pfs::Pidr,
5670            p1pfs::Pidr,
5671            P1Pfs_SPEC,
5672            crate::common::R,
5673        >::from_register(self, 0)
5674    }
5675
5676    #[doc = "Port Direction"]
5677    #[inline(always)]
5678    pub fn pdr(
5679        self,
5680    ) -> crate::common::RegisterField<
5681        2,
5682        0x1,
5683        1,
5684        0,
5685        p1pfs::Pdr,
5686        p1pfs::Pdr,
5687        P1Pfs_SPEC,
5688        crate::common::RW,
5689    > {
5690        crate::common::RegisterField::<
5691            2,
5692            0x1,
5693            1,
5694            0,
5695            p1pfs::Pdr,
5696            p1pfs::Pdr,
5697            P1Pfs_SPEC,
5698            crate::common::RW,
5699        >::from_register(self, 0)
5700    }
5701
5702    #[doc = "Pull-up Control"]
5703    #[inline(always)]
5704    pub fn pcr(
5705        self,
5706    ) -> crate::common::RegisterField<
5707        4,
5708        0x1,
5709        1,
5710        0,
5711        p1pfs::Pcr,
5712        p1pfs::Pcr,
5713        P1Pfs_SPEC,
5714        crate::common::RW,
5715    > {
5716        crate::common::RegisterField::<
5717            4,
5718            0x1,
5719            1,
5720            0,
5721            p1pfs::Pcr,
5722            p1pfs::Pcr,
5723            P1Pfs_SPEC,
5724            crate::common::RW,
5725        >::from_register(self, 0)
5726    }
5727
5728    #[doc = "N-Channel Open-Drain Control"]
5729    #[inline(always)]
5730    pub fn ncodr(
5731        self,
5732    ) -> crate::common::RegisterField<
5733        6,
5734        0x1,
5735        1,
5736        0,
5737        p1pfs::Ncodr,
5738        p1pfs::Ncodr,
5739        P1Pfs_SPEC,
5740        crate::common::RW,
5741    > {
5742        crate::common::RegisterField::<
5743            6,
5744            0x1,
5745            1,
5746            0,
5747            p1pfs::Ncodr,
5748            p1pfs::Ncodr,
5749            P1Pfs_SPEC,
5750            crate::common::RW,
5751        >::from_register(self, 0)
5752    }
5753
5754    #[doc = "Port Drive Capability"]
5755    #[inline(always)]
5756    pub fn dscr(
5757        self,
5758    ) -> crate::common::RegisterField<
5759        10,
5760        0x3,
5761        1,
5762        0,
5763        p1pfs::Dscr,
5764        p1pfs::Dscr,
5765        P1Pfs_SPEC,
5766        crate::common::RW,
5767    > {
5768        crate::common::RegisterField::<
5769            10,
5770            0x3,
5771            1,
5772            0,
5773            p1pfs::Dscr,
5774            p1pfs::Dscr,
5775            P1Pfs_SPEC,
5776            crate::common::RW,
5777        >::from_register(self, 0)
5778    }
5779
5780    #[doc = "Event on Falling/Event on Rising"]
5781    #[inline(always)]
5782    pub fn eofr(
5783        self,
5784    ) -> crate::common::RegisterField<
5785        12,
5786        0x3,
5787        1,
5788        0,
5789        p1pfs::Eofr,
5790        p1pfs::Eofr,
5791        P1Pfs_SPEC,
5792        crate::common::RW,
5793    > {
5794        crate::common::RegisterField::<
5795            12,
5796            0x3,
5797            1,
5798            0,
5799            p1pfs::Eofr,
5800            p1pfs::Eofr,
5801            P1Pfs_SPEC,
5802            crate::common::RW,
5803        >::from_register(self, 0)
5804    }
5805
5806    #[doc = "IRQ Input Enable"]
5807    #[inline(always)]
5808    pub fn isel(
5809        self,
5810    ) -> crate::common::RegisterField<
5811        14,
5812        0x1,
5813        1,
5814        0,
5815        p1pfs::Isel,
5816        p1pfs::Isel,
5817        P1Pfs_SPEC,
5818        crate::common::RW,
5819    > {
5820        crate::common::RegisterField::<
5821            14,
5822            0x1,
5823            1,
5824            0,
5825            p1pfs::Isel,
5826            p1pfs::Isel,
5827            P1Pfs_SPEC,
5828            crate::common::RW,
5829        >::from_register(self, 0)
5830    }
5831
5832    #[doc = "Analog Input Enable"]
5833    #[inline(always)]
5834    pub fn asel(
5835        self,
5836    ) -> crate::common::RegisterField<
5837        15,
5838        0x1,
5839        1,
5840        0,
5841        p1pfs::Asel,
5842        p1pfs::Asel,
5843        P1Pfs_SPEC,
5844        crate::common::RW,
5845    > {
5846        crate::common::RegisterField::<
5847            15,
5848            0x1,
5849            1,
5850            0,
5851            p1pfs::Asel,
5852            p1pfs::Asel,
5853            P1Pfs_SPEC,
5854            crate::common::RW,
5855        >::from_register(self, 0)
5856    }
5857
5858    #[doc = "Port Mode Control"]
5859    #[inline(always)]
5860    pub fn pmr(
5861        self,
5862    ) -> crate::common::RegisterField<
5863        16,
5864        0x1,
5865        1,
5866        0,
5867        p1pfs::Pmr,
5868        p1pfs::Pmr,
5869        P1Pfs_SPEC,
5870        crate::common::RW,
5871    > {
5872        crate::common::RegisterField::<
5873            16,
5874            0x1,
5875            1,
5876            0,
5877            p1pfs::Pmr,
5878            p1pfs::Pmr,
5879            P1Pfs_SPEC,
5880            crate::common::RW,
5881        >::from_register(self, 0)
5882    }
5883
5884    #[doc = "Peripheral Select"]
5885    #[inline(always)]
5886    pub fn psel(
5887        self,
5888    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P1Pfs_SPEC, crate::common::RW> {
5889        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P1Pfs_SPEC,crate::common::RW>::from_register(self,0)
5890    }
5891}
5892impl ::core::default::Default for P1Pfs {
5893    #[inline(always)]
5894    fn default() -> P1Pfs {
5895        <crate::RegValueT<P1Pfs_SPEC> as RegisterValue<_>>::new(0)
5896    }
5897}
5898pub mod p1pfs {
5899
5900    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5901    pub struct Podr_SPEC;
5902    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5903    impl Podr {
5904        #[doc = "Output low"]
5905        pub const _0: Self = Self::new(0);
5906
5907        #[doc = "Output high"]
5908        pub const _1: Self = Self::new(1);
5909    }
5910    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5911    pub struct Pidr_SPEC;
5912    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5913    impl Pidr {
5914        #[doc = "Low level"]
5915        pub const _0: Self = Self::new(0);
5916
5917        #[doc = "High level"]
5918        pub const _1: Self = Self::new(1);
5919    }
5920    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5921    pub struct Pdr_SPEC;
5922    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5923    impl Pdr {
5924        #[doc = "Input (functions as an input pin)"]
5925        pub const _0: Self = Self::new(0);
5926
5927        #[doc = "Output (functions as an output pin)"]
5928        pub const _1: Self = Self::new(1);
5929    }
5930    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5931    pub struct Pcr_SPEC;
5932    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5933    impl Pcr {
5934        #[doc = "Disable input pull-up"]
5935        pub const _0: Self = Self::new(0);
5936
5937        #[doc = "Enable input pull-up"]
5938        pub const _1: Self = Self::new(1);
5939    }
5940    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5941    pub struct Ncodr_SPEC;
5942    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5943    impl Ncodr {
5944        #[doc = "Output CMOS"]
5945        pub const _0: Self = Self::new(0);
5946
5947        #[doc = "Output NMOS open-drain"]
5948        pub const _1: Self = Self::new(1);
5949    }
5950    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5951    pub struct Dscr_SPEC;
5952    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
5953    impl Dscr {
5954        #[doc = "Low drive"]
5955        pub const _00: Self = Self::new(0);
5956
5957        #[doc = "Middle drive"]
5958        pub const _01: Self = Self::new(1);
5959
5960        #[doc = "Setting prohibited"]
5961        pub const _10: Self = Self::new(2);
5962
5963        #[doc = "High drive"]
5964        pub const _11: Self = Self::new(3);
5965    }
5966    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5967    pub struct Eofr_SPEC;
5968    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
5969    impl Eofr {
5970        #[doc = "Don\'t care"]
5971        pub const _00: Self = Self::new(0);
5972
5973        #[doc = "Detect rising edge"]
5974        pub const _01: Self = Self::new(1);
5975
5976        #[doc = "Detect falling edge"]
5977        pub const _10: Self = Self::new(2);
5978
5979        #[doc = "Detect both edges"]
5980        pub const _11: Self = Self::new(3);
5981    }
5982    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5983    pub struct Isel_SPEC;
5984    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5985    impl Isel {
5986        #[doc = "Do not use as IRQn input pin"]
5987        pub const _0: Self = Self::new(0);
5988
5989        #[doc = "Use as IRQn input pin"]
5990        pub const _1: Self = Self::new(1);
5991    }
5992    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5993    pub struct Asel_SPEC;
5994    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
5995    impl Asel {
5996        #[doc = "Do not use as analog pin"]
5997        pub const _0: Self = Self::new(0);
5998
5999        #[doc = "Use as analog pin"]
6000        pub const _1: Self = Self::new(1);
6001    }
6002    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6003    pub struct Pmr_SPEC;
6004    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
6005    impl Pmr {
6006        #[doc = "Use as general I/O pin"]
6007        pub const _0: Self = Self::new(0);
6008
6009        #[doc = "Use as I/O port for peripheral functions"]
6010        pub const _1: Self = Self::new(1);
6011    }
6012}
6013#[doc(hidden)]
6014#[derive(Copy, Clone, Eq, PartialEq)]
6015pub struct P1PfsHa_SPEC;
6016impl crate::sealed::RegSpec for P1PfsHa_SPEC {
6017    type DataType = u16;
6018}
6019
6020#[doc = "Port 1%s Pin Function Select Register"]
6021pub type P1PfsHa = crate::RegValueT<P1PfsHa_SPEC>;
6022
6023impl P1PfsHa {
6024    #[doc = "Port Output Data"]
6025    #[inline(always)]
6026    pub fn podr(
6027        self,
6028    ) -> crate::common::RegisterField<
6029        0,
6030        0x1,
6031        1,
6032        0,
6033        p1pfs_ha::Podr,
6034        p1pfs_ha::Podr,
6035        P1PfsHa_SPEC,
6036        crate::common::RW,
6037    > {
6038        crate::common::RegisterField::<
6039            0,
6040            0x1,
6041            1,
6042            0,
6043            p1pfs_ha::Podr,
6044            p1pfs_ha::Podr,
6045            P1PfsHa_SPEC,
6046            crate::common::RW,
6047        >::from_register(self, 0)
6048    }
6049
6050    #[doc = "Port State"]
6051    #[inline(always)]
6052    pub fn pidr(
6053        self,
6054    ) -> crate::common::RegisterField<
6055        1,
6056        0x1,
6057        1,
6058        0,
6059        p1pfs_ha::Pidr,
6060        p1pfs_ha::Pidr,
6061        P1PfsHa_SPEC,
6062        crate::common::R,
6063    > {
6064        crate::common::RegisterField::<
6065            1,
6066            0x1,
6067            1,
6068            0,
6069            p1pfs_ha::Pidr,
6070            p1pfs_ha::Pidr,
6071            P1PfsHa_SPEC,
6072            crate::common::R,
6073        >::from_register(self, 0)
6074    }
6075
6076    #[doc = "Port Direction"]
6077    #[inline(always)]
6078    pub fn pdr(
6079        self,
6080    ) -> crate::common::RegisterField<
6081        2,
6082        0x1,
6083        1,
6084        0,
6085        p1pfs_ha::Pdr,
6086        p1pfs_ha::Pdr,
6087        P1PfsHa_SPEC,
6088        crate::common::RW,
6089    > {
6090        crate::common::RegisterField::<
6091            2,
6092            0x1,
6093            1,
6094            0,
6095            p1pfs_ha::Pdr,
6096            p1pfs_ha::Pdr,
6097            P1PfsHa_SPEC,
6098            crate::common::RW,
6099        >::from_register(self, 0)
6100    }
6101
6102    #[doc = "Pull-up Control"]
6103    #[inline(always)]
6104    pub fn pcr(
6105        self,
6106    ) -> crate::common::RegisterField<
6107        4,
6108        0x1,
6109        1,
6110        0,
6111        p1pfs_ha::Pcr,
6112        p1pfs_ha::Pcr,
6113        P1PfsHa_SPEC,
6114        crate::common::RW,
6115    > {
6116        crate::common::RegisterField::<
6117            4,
6118            0x1,
6119            1,
6120            0,
6121            p1pfs_ha::Pcr,
6122            p1pfs_ha::Pcr,
6123            P1PfsHa_SPEC,
6124            crate::common::RW,
6125        >::from_register(self, 0)
6126    }
6127
6128    #[doc = "N-Channel Open-Drain Control"]
6129    #[inline(always)]
6130    pub fn ncodr(
6131        self,
6132    ) -> crate::common::RegisterField<
6133        6,
6134        0x1,
6135        1,
6136        0,
6137        p1pfs_ha::Ncodr,
6138        p1pfs_ha::Ncodr,
6139        P1PfsHa_SPEC,
6140        crate::common::RW,
6141    > {
6142        crate::common::RegisterField::<
6143            6,
6144            0x1,
6145            1,
6146            0,
6147            p1pfs_ha::Ncodr,
6148            p1pfs_ha::Ncodr,
6149            P1PfsHa_SPEC,
6150            crate::common::RW,
6151        >::from_register(self, 0)
6152    }
6153
6154    #[doc = "Port Drive Capability"]
6155    #[inline(always)]
6156    pub fn dscr(
6157        self,
6158    ) -> crate::common::RegisterField<
6159        10,
6160        0x3,
6161        1,
6162        0,
6163        p1pfs_ha::Dscr,
6164        p1pfs_ha::Dscr,
6165        P1PfsHa_SPEC,
6166        crate::common::RW,
6167    > {
6168        crate::common::RegisterField::<
6169            10,
6170            0x3,
6171            1,
6172            0,
6173            p1pfs_ha::Dscr,
6174            p1pfs_ha::Dscr,
6175            P1PfsHa_SPEC,
6176            crate::common::RW,
6177        >::from_register(self, 0)
6178    }
6179
6180    #[doc = "Event on Falling/Event on Rising"]
6181    #[inline(always)]
6182    pub fn eofr(
6183        self,
6184    ) -> crate::common::RegisterField<
6185        12,
6186        0x3,
6187        1,
6188        0,
6189        p1pfs_ha::Eofr,
6190        p1pfs_ha::Eofr,
6191        P1PfsHa_SPEC,
6192        crate::common::RW,
6193    > {
6194        crate::common::RegisterField::<
6195            12,
6196            0x3,
6197            1,
6198            0,
6199            p1pfs_ha::Eofr,
6200            p1pfs_ha::Eofr,
6201            P1PfsHa_SPEC,
6202            crate::common::RW,
6203        >::from_register(self, 0)
6204    }
6205
6206    #[doc = "IRQ Input Enable"]
6207    #[inline(always)]
6208    pub fn isel(
6209        self,
6210    ) -> crate::common::RegisterField<
6211        14,
6212        0x1,
6213        1,
6214        0,
6215        p1pfs_ha::Isel,
6216        p1pfs_ha::Isel,
6217        P1PfsHa_SPEC,
6218        crate::common::RW,
6219    > {
6220        crate::common::RegisterField::<
6221            14,
6222            0x1,
6223            1,
6224            0,
6225            p1pfs_ha::Isel,
6226            p1pfs_ha::Isel,
6227            P1PfsHa_SPEC,
6228            crate::common::RW,
6229        >::from_register(self, 0)
6230    }
6231
6232    #[doc = "Analog Input Enable"]
6233    #[inline(always)]
6234    pub fn asel(
6235        self,
6236    ) -> crate::common::RegisterField<
6237        15,
6238        0x1,
6239        1,
6240        0,
6241        p1pfs_ha::Asel,
6242        p1pfs_ha::Asel,
6243        P1PfsHa_SPEC,
6244        crate::common::RW,
6245    > {
6246        crate::common::RegisterField::<
6247            15,
6248            0x1,
6249            1,
6250            0,
6251            p1pfs_ha::Asel,
6252            p1pfs_ha::Asel,
6253            P1PfsHa_SPEC,
6254            crate::common::RW,
6255        >::from_register(self, 0)
6256    }
6257}
6258impl ::core::default::Default for P1PfsHa {
6259    #[inline(always)]
6260    fn default() -> P1PfsHa {
6261        <crate::RegValueT<P1PfsHa_SPEC> as RegisterValue<_>>::new(0)
6262    }
6263}
6264pub mod p1pfs_ha {
6265
6266    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6267    pub struct Podr_SPEC;
6268    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6269    impl Podr {
6270        #[doc = "Output low"]
6271        pub const _0: Self = Self::new(0);
6272
6273        #[doc = "Output high"]
6274        pub const _1: Self = Self::new(1);
6275    }
6276    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6277    pub struct Pidr_SPEC;
6278    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6279    impl Pidr {
6280        #[doc = "Low level"]
6281        pub const _0: Self = Self::new(0);
6282
6283        #[doc = "High level"]
6284        pub const _1: Self = Self::new(1);
6285    }
6286    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6287    pub struct Pdr_SPEC;
6288    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6289    impl Pdr {
6290        #[doc = "Input (functions as an input pin)"]
6291        pub const _0: Self = Self::new(0);
6292
6293        #[doc = "Output (functions as an output pin)"]
6294        pub const _1: Self = Self::new(1);
6295    }
6296    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6297    pub struct Pcr_SPEC;
6298    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6299    impl Pcr {
6300        #[doc = "Disable input pull-up"]
6301        pub const _0: Self = Self::new(0);
6302
6303        #[doc = "Enable input pull-up"]
6304        pub const _1: Self = Self::new(1);
6305    }
6306    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6307    pub struct Ncodr_SPEC;
6308    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6309    impl Ncodr {
6310        #[doc = "Output CMOS"]
6311        pub const _0: Self = Self::new(0);
6312
6313        #[doc = "Output NMOS open-drain"]
6314        pub const _1: Self = Self::new(1);
6315    }
6316    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6317    pub struct Dscr_SPEC;
6318    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
6319    impl Dscr {
6320        #[doc = "Low drive"]
6321        pub const _00: Self = Self::new(0);
6322
6323        #[doc = "Middle drive"]
6324        pub const _01: Self = Self::new(1);
6325
6326        #[doc = "Setting prohibited"]
6327        pub const _10: Self = Self::new(2);
6328
6329        #[doc = "High drive"]
6330        pub const _11: Self = Self::new(3);
6331    }
6332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6333    pub struct Eofr_SPEC;
6334    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
6335    impl Eofr {
6336        #[doc = "Don\'t care"]
6337        pub const _00: Self = Self::new(0);
6338
6339        #[doc = "Detect rising edge"]
6340        pub const _01: Self = Self::new(1);
6341
6342        #[doc = "Detect falling edge"]
6343        pub const _10: Self = Self::new(2);
6344
6345        #[doc = "Detect both edges"]
6346        pub const _11: Self = Self::new(3);
6347    }
6348    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6349    pub struct Isel_SPEC;
6350    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
6351    impl Isel {
6352        #[doc = "Do not use as IRQn input pin"]
6353        pub const _0: Self = Self::new(0);
6354
6355        #[doc = "Use as IRQn input pin"]
6356        pub const _1: Self = Self::new(1);
6357    }
6358    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6359    pub struct Asel_SPEC;
6360    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
6361    impl Asel {
6362        #[doc = "Do not use as analog pin"]
6363        pub const _0: Self = Self::new(0);
6364
6365        #[doc = "Use as analog pin"]
6366        pub const _1: Self = Self::new(1);
6367    }
6368}
6369#[doc(hidden)]
6370#[derive(Copy, Clone, Eq, PartialEq)]
6371pub struct P1PfsBy_SPEC;
6372impl crate::sealed::RegSpec for P1PfsBy_SPEC {
6373    type DataType = u8;
6374}
6375
6376#[doc = "Port 1%s Pin Function Select Register"]
6377pub type P1PfsBy = crate::RegValueT<P1PfsBy_SPEC>;
6378
6379impl P1PfsBy {
6380    #[doc = "Port Output Data"]
6381    #[inline(always)]
6382    pub fn podr(
6383        self,
6384    ) -> crate::common::RegisterField<
6385        0,
6386        0x1,
6387        1,
6388        0,
6389        p1pfs_by::Podr,
6390        p1pfs_by::Podr,
6391        P1PfsBy_SPEC,
6392        crate::common::RW,
6393    > {
6394        crate::common::RegisterField::<
6395            0,
6396            0x1,
6397            1,
6398            0,
6399            p1pfs_by::Podr,
6400            p1pfs_by::Podr,
6401            P1PfsBy_SPEC,
6402            crate::common::RW,
6403        >::from_register(self, 0)
6404    }
6405
6406    #[doc = "Port State"]
6407    #[inline(always)]
6408    pub fn pidr(
6409        self,
6410    ) -> crate::common::RegisterField<
6411        1,
6412        0x1,
6413        1,
6414        0,
6415        p1pfs_by::Pidr,
6416        p1pfs_by::Pidr,
6417        P1PfsBy_SPEC,
6418        crate::common::R,
6419    > {
6420        crate::common::RegisterField::<
6421            1,
6422            0x1,
6423            1,
6424            0,
6425            p1pfs_by::Pidr,
6426            p1pfs_by::Pidr,
6427            P1PfsBy_SPEC,
6428            crate::common::R,
6429        >::from_register(self, 0)
6430    }
6431
6432    #[doc = "Port Direction"]
6433    #[inline(always)]
6434    pub fn pdr(
6435        self,
6436    ) -> crate::common::RegisterField<
6437        2,
6438        0x1,
6439        1,
6440        0,
6441        p1pfs_by::Pdr,
6442        p1pfs_by::Pdr,
6443        P1PfsBy_SPEC,
6444        crate::common::RW,
6445    > {
6446        crate::common::RegisterField::<
6447            2,
6448            0x1,
6449            1,
6450            0,
6451            p1pfs_by::Pdr,
6452            p1pfs_by::Pdr,
6453            P1PfsBy_SPEC,
6454            crate::common::RW,
6455        >::from_register(self, 0)
6456    }
6457
6458    #[doc = "Pull-up Control"]
6459    #[inline(always)]
6460    pub fn pcr(
6461        self,
6462    ) -> crate::common::RegisterField<
6463        4,
6464        0x1,
6465        1,
6466        0,
6467        p1pfs_by::Pcr,
6468        p1pfs_by::Pcr,
6469        P1PfsBy_SPEC,
6470        crate::common::RW,
6471    > {
6472        crate::common::RegisterField::<
6473            4,
6474            0x1,
6475            1,
6476            0,
6477            p1pfs_by::Pcr,
6478            p1pfs_by::Pcr,
6479            P1PfsBy_SPEC,
6480            crate::common::RW,
6481        >::from_register(self, 0)
6482    }
6483
6484    #[doc = "N-Channel Open-Drain Control"]
6485    #[inline(always)]
6486    pub fn ncodr(
6487        self,
6488    ) -> crate::common::RegisterField<
6489        6,
6490        0x1,
6491        1,
6492        0,
6493        p1pfs_by::Ncodr,
6494        p1pfs_by::Ncodr,
6495        P1PfsBy_SPEC,
6496        crate::common::RW,
6497    > {
6498        crate::common::RegisterField::<
6499            6,
6500            0x1,
6501            1,
6502            0,
6503            p1pfs_by::Ncodr,
6504            p1pfs_by::Ncodr,
6505            P1PfsBy_SPEC,
6506            crate::common::RW,
6507        >::from_register(self, 0)
6508    }
6509}
6510impl ::core::default::Default for P1PfsBy {
6511    #[inline(always)]
6512    fn default() -> P1PfsBy {
6513        <crate::RegValueT<P1PfsBy_SPEC> as RegisterValue<_>>::new(0)
6514    }
6515}
6516pub mod p1pfs_by {
6517
6518    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6519    pub struct Podr_SPEC;
6520    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6521    impl Podr {
6522        #[doc = "Output low"]
6523        pub const _0: Self = Self::new(0);
6524
6525        #[doc = "Output high"]
6526        pub const _1: Self = Self::new(1);
6527    }
6528    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6529    pub struct Pidr_SPEC;
6530    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6531    impl Pidr {
6532        #[doc = "Low level"]
6533        pub const _0: Self = Self::new(0);
6534
6535        #[doc = "High level"]
6536        pub const _1: Self = Self::new(1);
6537    }
6538    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6539    pub struct Pdr_SPEC;
6540    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6541    impl Pdr {
6542        #[doc = "Input (functions as an input pin)"]
6543        pub const _0: Self = Self::new(0);
6544
6545        #[doc = "Output (functions as an output pin)"]
6546        pub const _1: Self = Self::new(1);
6547    }
6548    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6549    pub struct Pcr_SPEC;
6550    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6551    impl Pcr {
6552        #[doc = "Disable input pull-up"]
6553        pub const _0: Self = Self::new(0);
6554
6555        #[doc = "Enable input pull-up"]
6556        pub const _1: Self = Self::new(1);
6557    }
6558    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6559    pub struct Ncodr_SPEC;
6560    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6561    impl Ncodr {
6562        #[doc = "Output CMOS"]
6563        pub const _0: Self = Self::new(0);
6564
6565        #[doc = "Output NMOS open-drain"]
6566        pub const _1: Self = Self::new(1);
6567    }
6568}
6569#[doc(hidden)]
6570#[derive(Copy, Clone, Eq, PartialEq)]
6571pub struct P200Pfs_SPEC;
6572impl crate::sealed::RegSpec for P200Pfs_SPEC {
6573    type DataType = u32;
6574}
6575
6576#[doc = "Port 200 Pin Function Select Register"]
6577pub type P200Pfs = crate::RegValueT<P200Pfs_SPEC>;
6578
6579impl P200Pfs {
6580    #[doc = "Port Output Data"]
6581    #[inline(always)]
6582    pub fn podr(
6583        self,
6584    ) -> crate::common::RegisterField<
6585        0,
6586        0x1,
6587        1,
6588        0,
6589        p200pfs::Podr,
6590        p200pfs::Podr,
6591        P200Pfs_SPEC,
6592        crate::common::RW,
6593    > {
6594        crate::common::RegisterField::<
6595            0,
6596            0x1,
6597            1,
6598            0,
6599            p200pfs::Podr,
6600            p200pfs::Podr,
6601            P200Pfs_SPEC,
6602            crate::common::RW,
6603        >::from_register(self, 0)
6604    }
6605
6606    #[doc = "Port State"]
6607    #[inline(always)]
6608    pub fn pidr(
6609        self,
6610    ) -> crate::common::RegisterField<
6611        1,
6612        0x1,
6613        1,
6614        0,
6615        p200pfs::Pidr,
6616        p200pfs::Pidr,
6617        P200Pfs_SPEC,
6618        crate::common::R,
6619    > {
6620        crate::common::RegisterField::<
6621            1,
6622            0x1,
6623            1,
6624            0,
6625            p200pfs::Pidr,
6626            p200pfs::Pidr,
6627            P200Pfs_SPEC,
6628            crate::common::R,
6629        >::from_register(self, 0)
6630    }
6631
6632    #[doc = "Port Direction"]
6633    #[inline(always)]
6634    pub fn pdr(
6635        self,
6636    ) -> crate::common::RegisterField<
6637        2,
6638        0x1,
6639        1,
6640        0,
6641        p200pfs::Pdr,
6642        p200pfs::Pdr,
6643        P200Pfs_SPEC,
6644        crate::common::RW,
6645    > {
6646        crate::common::RegisterField::<
6647            2,
6648            0x1,
6649            1,
6650            0,
6651            p200pfs::Pdr,
6652            p200pfs::Pdr,
6653            P200Pfs_SPEC,
6654            crate::common::RW,
6655        >::from_register(self, 0)
6656    }
6657
6658    #[doc = "Pull-up Control"]
6659    #[inline(always)]
6660    pub fn pcr(
6661        self,
6662    ) -> crate::common::RegisterField<
6663        4,
6664        0x1,
6665        1,
6666        0,
6667        p200pfs::Pcr,
6668        p200pfs::Pcr,
6669        P200Pfs_SPEC,
6670        crate::common::RW,
6671    > {
6672        crate::common::RegisterField::<
6673            4,
6674            0x1,
6675            1,
6676            0,
6677            p200pfs::Pcr,
6678            p200pfs::Pcr,
6679            P200Pfs_SPEC,
6680            crate::common::RW,
6681        >::from_register(self, 0)
6682    }
6683
6684    #[doc = "N-Channel Open-Drain Control"]
6685    #[inline(always)]
6686    pub fn ncodr(
6687        self,
6688    ) -> crate::common::RegisterField<
6689        6,
6690        0x1,
6691        1,
6692        0,
6693        p200pfs::Ncodr,
6694        p200pfs::Ncodr,
6695        P200Pfs_SPEC,
6696        crate::common::RW,
6697    > {
6698        crate::common::RegisterField::<
6699            6,
6700            0x1,
6701            1,
6702            0,
6703            p200pfs::Ncodr,
6704            p200pfs::Ncodr,
6705            P200Pfs_SPEC,
6706            crate::common::RW,
6707        >::from_register(self, 0)
6708    }
6709
6710    #[doc = "Port Drive Capability"]
6711    #[inline(always)]
6712    pub fn dscr(
6713        self,
6714    ) -> crate::common::RegisterField<
6715        10,
6716        0x3,
6717        1,
6718        0,
6719        p200pfs::Dscr,
6720        p200pfs::Dscr,
6721        P200Pfs_SPEC,
6722        crate::common::RW,
6723    > {
6724        crate::common::RegisterField::<
6725            10,
6726            0x3,
6727            1,
6728            0,
6729            p200pfs::Dscr,
6730            p200pfs::Dscr,
6731            P200Pfs_SPEC,
6732            crate::common::RW,
6733        >::from_register(self, 0)
6734    }
6735
6736    #[doc = "Event on Falling/Event on Rising"]
6737    #[inline(always)]
6738    pub fn eofr(
6739        self,
6740    ) -> crate::common::RegisterField<
6741        12,
6742        0x3,
6743        1,
6744        0,
6745        p200pfs::Eofr,
6746        p200pfs::Eofr,
6747        P200Pfs_SPEC,
6748        crate::common::RW,
6749    > {
6750        crate::common::RegisterField::<
6751            12,
6752            0x3,
6753            1,
6754            0,
6755            p200pfs::Eofr,
6756            p200pfs::Eofr,
6757            P200Pfs_SPEC,
6758            crate::common::RW,
6759        >::from_register(self, 0)
6760    }
6761
6762    #[doc = "IRQ Input Enable"]
6763    #[inline(always)]
6764    pub fn isel(
6765        self,
6766    ) -> crate::common::RegisterField<
6767        14,
6768        0x1,
6769        1,
6770        0,
6771        p200pfs::Isel,
6772        p200pfs::Isel,
6773        P200Pfs_SPEC,
6774        crate::common::RW,
6775    > {
6776        crate::common::RegisterField::<
6777            14,
6778            0x1,
6779            1,
6780            0,
6781            p200pfs::Isel,
6782            p200pfs::Isel,
6783            P200Pfs_SPEC,
6784            crate::common::RW,
6785        >::from_register(self, 0)
6786    }
6787
6788    #[doc = "Analog Input Enable"]
6789    #[inline(always)]
6790    pub fn asel(
6791        self,
6792    ) -> crate::common::RegisterField<
6793        15,
6794        0x1,
6795        1,
6796        0,
6797        p200pfs::Asel,
6798        p200pfs::Asel,
6799        P200Pfs_SPEC,
6800        crate::common::RW,
6801    > {
6802        crate::common::RegisterField::<
6803            15,
6804            0x1,
6805            1,
6806            0,
6807            p200pfs::Asel,
6808            p200pfs::Asel,
6809            P200Pfs_SPEC,
6810            crate::common::RW,
6811        >::from_register(self, 0)
6812    }
6813
6814    #[doc = "Port Mode Control"]
6815    #[inline(always)]
6816    pub fn pmr(
6817        self,
6818    ) -> crate::common::RegisterField<
6819        16,
6820        0x1,
6821        1,
6822        0,
6823        p200pfs::Pmr,
6824        p200pfs::Pmr,
6825        P200Pfs_SPEC,
6826        crate::common::RW,
6827    > {
6828        crate::common::RegisterField::<
6829            16,
6830            0x1,
6831            1,
6832            0,
6833            p200pfs::Pmr,
6834            p200pfs::Pmr,
6835            P200Pfs_SPEC,
6836            crate::common::RW,
6837        >::from_register(self, 0)
6838    }
6839
6840    #[doc = "Peripheral Select"]
6841    #[inline(always)]
6842    pub fn psel(
6843        self,
6844    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P200Pfs_SPEC, crate::common::RW> {
6845        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P200Pfs_SPEC,crate::common::RW>::from_register(self,0)
6846    }
6847}
6848impl ::core::default::Default for P200Pfs {
6849    #[inline(always)]
6850    fn default() -> P200Pfs {
6851        <crate::RegValueT<P200Pfs_SPEC> as RegisterValue<_>>::new(0)
6852    }
6853}
6854pub mod p200pfs {
6855
6856    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6857    pub struct Podr_SPEC;
6858    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
6859    impl Podr {
6860        #[doc = "Output low"]
6861        pub const _0: Self = Self::new(0);
6862
6863        #[doc = "Output high"]
6864        pub const _1: Self = Self::new(1);
6865    }
6866    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6867    pub struct Pidr_SPEC;
6868    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
6869    impl Pidr {
6870        #[doc = "Low level"]
6871        pub const _0: Self = Self::new(0);
6872
6873        #[doc = "High level"]
6874        pub const _1: Self = Self::new(1);
6875    }
6876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6877    pub struct Pdr_SPEC;
6878    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
6879    impl Pdr {
6880        #[doc = "Input (functions as an input pin)"]
6881        pub const _0: Self = Self::new(0);
6882
6883        #[doc = "Output (functions as an output pin)"]
6884        pub const _1: Self = Self::new(1);
6885    }
6886    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6887    pub struct Pcr_SPEC;
6888    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
6889    impl Pcr {
6890        #[doc = "Disable input pull-up"]
6891        pub const _0: Self = Self::new(0);
6892
6893        #[doc = "Enable input pull-up"]
6894        pub const _1: Self = Self::new(1);
6895    }
6896    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6897    pub struct Ncodr_SPEC;
6898    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
6899    impl Ncodr {
6900        #[doc = "Output CMOS"]
6901        pub const _0: Self = Self::new(0);
6902
6903        #[doc = "Output NMOS open-drain"]
6904        pub const _1: Self = Self::new(1);
6905    }
6906    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6907    pub struct Dscr_SPEC;
6908    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
6909    impl Dscr {
6910        #[doc = "Low drive"]
6911        pub const _00: Self = Self::new(0);
6912
6913        #[doc = "Middle drive"]
6914        pub const _01: Self = Self::new(1);
6915
6916        #[doc = "Setting prohibited"]
6917        pub const _10: Self = Self::new(2);
6918
6919        #[doc = "High drive"]
6920        pub const _11: Self = Self::new(3);
6921    }
6922    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6923    pub struct Eofr_SPEC;
6924    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
6925    impl Eofr {
6926        #[doc = "Don\'t care"]
6927        pub const _00: Self = Self::new(0);
6928
6929        #[doc = "Detect rising edge"]
6930        pub const _01: Self = Self::new(1);
6931
6932        #[doc = "Detect falling edge"]
6933        pub const _10: Self = Self::new(2);
6934
6935        #[doc = "Detect both edges"]
6936        pub const _11: Self = Self::new(3);
6937    }
6938    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6939    pub struct Isel_SPEC;
6940    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
6941    impl Isel {
6942        #[doc = "Do not use as IRQn input pin"]
6943        pub const _0: Self = Self::new(0);
6944
6945        #[doc = "Use as IRQn input pin"]
6946        pub const _1: Self = Self::new(1);
6947    }
6948    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6949    pub struct Asel_SPEC;
6950    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
6951    impl Asel {
6952        #[doc = "Do not use as analog pin"]
6953        pub const _0: Self = Self::new(0);
6954
6955        #[doc = "Use as analog pin"]
6956        pub const _1: Self = Self::new(1);
6957    }
6958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6959    pub struct Pmr_SPEC;
6960    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
6961    impl Pmr {
6962        #[doc = "Use as general I/O pin"]
6963        pub const _0: Self = Self::new(0);
6964
6965        #[doc = "Use as I/O port for peripheral functions"]
6966        pub const _1: Self = Self::new(1);
6967    }
6968}
6969#[doc(hidden)]
6970#[derive(Copy, Clone, Eq, PartialEq)]
6971pub struct P200PfsHa_SPEC;
6972impl crate::sealed::RegSpec for P200PfsHa_SPEC {
6973    type DataType = u16;
6974}
6975
6976#[doc = "Port 200 Pin Function Select Register"]
6977pub type P200PfsHa = crate::RegValueT<P200PfsHa_SPEC>;
6978
6979impl P200PfsHa {
6980    #[doc = "Port Output Data"]
6981    #[inline(always)]
6982    pub fn podr(
6983        self,
6984    ) -> crate::common::RegisterField<
6985        0,
6986        0x1,
6987        1,
6988        0,
6989        p200pfs_ha::Podr,
6990        p200pfs_ha::Podr,
6991        P200PfsHa_SPEC,
6992        crate::common::RW,
6993    > {
6994        crate::common::RegisterField::<
6995            0,
6996            0x1,
6997            1,
6998            0,
6999            p200pfs_ha::Podr,
7000            p200pfs_ha::Podr,
7001            P200PfsHa_SPEC,
7002            crate::common::RW,
7003        >::from_register(self, 0)
7004    }
7005
7006    #[doc = "Port State"]
7007    #[inline(always)]
7008    pub fn pidr(
7009        self,
7010    ) -> crate::common::RegisterField<
7011        1,
7012        0x1,
7013        1,
7014        0,
7015        p200pfs_ha::Pidr,
7016        p200pfs_ha::Pidr,
7017        P200PfsHa_SPEC,
7018        crate::common::R,
7019    > {
7020        crate::common::RegisterField::<
7021            1,
7022            0x1,
7023            1,
7024            0,
7025            p200pfs_ha::Pidr,
7026            p200pfs_ha::Pidr,
7027            P200PfsHa_SPEC,
7028            crate::common::R,
7029        >::from_register(self, 0)
7030    }
7031
7032    #[doc = "Port Direction"]
7033    #[inline(always)]
7034    pub fn pdr(
7035        self,
7036    ) -> crate::common::RegisterField<
7037        2,
7038        0x1,
7039        1,
7040        0,
7041        p200pfs_ha::Pdr,
7042        p200pfs_ha::Pdr,
7043        P200PfsHa_SPEC,
7044        crate::common::RW,
7045    > {
7046        crate::common::RegisterField::<
7047            2,
7048            0x1,
7049            1,
7050            0,
7051            p200pfs_ha::Pdr,
7052            p200pfs_ha::Pdr,
7053            P200PfsHa_SPEC,
7054            crate::common::RW,
7055        >::from_register(self, 0)
7056    }
7057
7058    #[doc = "Pull-up Control"]
7059    #[inline(always)]
7060    pub fn pcr(
7061        self,
7062    ) -> crate::common::RegisterField<
7063        4,
7064        0x1,
7065        1,
7066        0,
7067        p200pfs_ha::Pcr,
7068        p200pfs_ha::Pcr,
7069        P200PfsHa_SPEC,
7070        crate::common::RW,
7071    > {
7072        crate::common::RegisterField::<
7073            4,
7074            0x1,
7075            1,
7076            0,
7077            p200pfs_ha::Pcr,
7078            p200pfs_ha::Pcr,
7079            P200PfsHa_SPEC,
7080            crate::common::RW,
7081        >::from_register(self, 0)
7082    }
7083
7084    #[doc = "N-Channel Open-Drain Control"]
7085    #[inline(always)]
7086    pub fn ncodr(
7087        self,
7088    ) -> crate::common::RegisterField<
7089        6,
7090        0x1,
7091        1,
7092        0,
7093        p200pfs_ha::Ncodr,
7094        p200pfs_ha::Ncodr,
7095        P200PfsHa_SPEC,
7096        crate::common::RW,
7097    > {
7098        crate::common::RegisterField::<
7099            6,
7100            0x1,
7101            1,
7102            0,
7103            p200pfs_ha::Ncodr,
7104            p200pfs_ha::Ncodr,
7105            P200PfsHa_SPEC,
7106            crate::common::RW,
7107        >::from_register(self, 0)
7108    }
7109
7110    #[doc = "Port Drive Capability"]
7111    #[inline(always)]
7112    pub fn dscr(
7113        self,
7114    ) -> crate::common::RegisterField<
7115        10,
7116        0x3,
7117        1,
7118        0,
7119        p200pfs_ha::Dscr,
7120        p200pfs_ha::Dscr,
7121        P200PfsHa_SPEC,
7122        crate::common::RW,
7123    > {
7124        crate::common::RegisterField::<
7125            10,
7126            0x3,
7127            1,
7128            0,
7129            p200pfs_ha::Dscr,
7130            p200pfs_ha::Dscr,
7131            P200PfsHa_SPEC,
7132            crate::common::RW,
7133        >::from_register(self, 0)
7134    }
7135
7136    #[doc = "Event on Falling/Event on Rising"]
7137    #[inline(always)]
7138    pub fn eofr(
7139        self,
7140    ) -> crate::common::RegisterField<
7141        12,
7142        0x3,
7143        1,
7144        0,
7145        p200pfs_ha::Eofr,
7146        p200pfs_ha::Eofr,
7147        P200PfsHa_SPEC,
7148        crate::common::RW,
7149    > {
7150        crate::common::RegisterField::<
7151            12,
7152            0x3,
7153            1,
7154            0,
7155            p200pfs_ha::Eofr,
7156            p200pfs_ha::Eofr,
7157            P200PfsHa_SPEC,
7158            crate::common::RW,
7159        >::from_register(self, 0)
7160    }
7161
7162    #[doc = "IRQ Input Enable"]
7163    #[inline(always)]
7164    pub fn isel(
7165        self,
7166    ) -> crate::common::RegisterField<
7167        14,
7168        0x1,
7169        1,
7170        0,
7171        p200pfs_ha::Isel,
7172        p200pfs_ha::Isel,
7173        P200PfsHa_SPEC,
7174        crate::common::RW,
7175    > {
7176        crate::common::RegisterField::<
7177            14,
7178            0x1,
7179            1,
7180            0,
7181            p200pfs_ha::Isel,
7182            p200pfs_ha::Isel,
7183            P200PfsHa_SPEC,
7184            crate::common::RW,
7185        >::from_register(self, 0)
7186    }
7187
7188    #[doc = "Analog Input Enable"]
7189    #[inline(always)]
7190    pub fn asel(
7191        self,
7192    ) -> crate::common::RegisterField<
7193        15,
7194        0x1,
7195        1,
7196        0,
7197        p200pfs_ha::Asel,
7198        p200pfs_ha::Asel,
7199        P200PfsHa_SPEC,
7200        crate::common::RW,
7201    > {
7202        crate::common::RegisterField::<
7203            15,
7204            0x1,
7205            1,
7206            0,
7207            p200pfs_ha::Asel,
7208            p200pfs_ha::Asel,
7209            P200PfsHa_SPEC,
7210            crate::common::RW,
7211        >::from_register(self, 0)
7212    }
7213}
7214impl ::core::default::Default for P200PfsHa {
7215    #[inline(always)]
7216    fn default() -> P200PfsHa {
7217        <crate::RegValueT<P200PfsHa_SPEC> as RegisterValue<_>>::new(0)
7218    }
7219}
7220pub mod p200pfs_ha {
7221
7222    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7223    pub struct Podr_SPEC;
7224    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7225    impl Podr {
7226        #[doc = "Output low"]
7227        pub const _0: Self = Self::new(0);
7228
7229        #[doc = "Output high"]
7230        pub const _1: Self = Self::new(1);
7231    }
7232    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7233    pub struct Pidr_SPEC;
7234    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7235    impl Pidr {
7236        #[doc = "Low level"]
7237        pub const _0: Self = Self::new(0);
7238
7239        #[doc = "High level"]
7240        pub const _1: Self = Self::new(1);
7241    }
7242    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7243    pub struct Pdr_SPEC;
7244    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7245    impl Pdr {
7246        #[doc = "Input (functions as an input pin)"]
7247        pub const _0: Self = Self::new(0);
7248
7249        #[doc = "Output (functions as an output pin)"]
7250        pub const _1: Self = Self::new(1);
7251    }
7252    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7253    pub struct Pcr_SPEC;
7254    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7255    impl Pcr {
7256        #[doc = "Disable input pull-up"]
7257        pub const _0: Self = Self::new(0);
7258
7259        #[doc = "Enable input pull-up"]
7260        pub const _1: Self = Self::new(1);
7261    }
7262    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7263    pub struct Ncodr_SPEC;
7264    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7265    impl Ncodr {
7266        #[doc = "Output CMOS"]
7267        pub const _0: Self = Self::new(0);
7268
7269        #[doc = "Output NMOS open-drain"]
7270        pub const _1: Self = Self::new(1);
7271    }
7272    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7273    pub struct Dscr_SPEC;
7274    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
7275    impl Dscr {
7276        #[doc = "Low drive"]
7277        pub const _00: Self = Self::new(0);
7278
7279        #[doc = "Middle drive"]
7280        pub const _01: Self = Self::new(1);
7281
7282        #[doc = "Setting prohibited"]
7283        pub const _10: Self = Self::new(2);
7284
7285        #[doc = "High drive"]
7286        pub const _11: Self = Self::new(3);
7287    }
7288    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7289    pub struct Eofr_SPEC;
7290    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
7291    impl Eofr {
7292        #[doc = "Don\'t care"]
7293        pub const _00: Self = Self::new(0);
7294
7295        #[doc = "Detect rising edge"]
7296        pub const _01: Self = Self::new(1);
7297
7298        #[doc = "Detect falling edge"]
7299        pub const _10: Self = Self::new(2);
7300
7301        #[doc = "Detect both edges"]
7302        pub const _11: Self = Self::new(3);
7303    }
7304    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7305    pub struct Isel_SPEC;
7306    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
7307    impl Isel {
7308        #[doc = "Do not use as IRQn input pin"]
7309        pub const _0: Self = Self::new(0);
7310
7311        #[doc = "Use as IRQn input pin"]
7312        pub const _1: Self = Self::new(1);
7313    }
7314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7315    pub struct Asel_SPEC;
7316    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
7317    impl Asel {
7318        #[doc = "Do not use as analog pin"]
7319        pub const _0: Self = Self::new(0);
7320
7321        #[doc = "Use as analog pin"]
7322        pub const _1: Self = Self::new(1);
7323    }
7324}
7325#[doc(hidden)]
7326#[derive(Copy, Clone, Eq, PartialEq)]
7327pub struct P200PfsBy_SPEC;
7328impl crate::sealed::RegSpec for P200PfsBy_SPEC {
7329    type DataType = u8;
7330}
7331
7332#[doc = "Port 200 Pin Function Select Register"]
7333pub type P200PfsBy = crate::RegValueT<P200PfsBy_SPEC>;
7334
7335impl P200PfsBy {
7336    #[doc = "Port Output Data"]
7337    #[inline(always)]
7338    pub fn podr(
7339        self,
7340    ) -> crate::common::RegisterField<
7341        0,
7342        0x1,
7343        1,
7344        0,
7345        p200pfs_by::Podr,
7346        p200pfs_by::Podr,
7347        P200PfsBy_SPEC,
7348        crate::common::RW,
7349    > {
7350        crate::common::RegisterField::<
7351            0,
7352            0x1,
7353            1,
7354            0,
7355            p200pfs_by::Podr,
7356            p200pfs_by::Podr,
7357            P200PfsBy_SPEC,
7358            crate::common::RW,
7359        >::from_register(self, 0)
7360    }
7361
7362    #[doc = "Port State"]
7363    #[inline(always)]
7364    pub fn pidr(
7365        self,
7366    ) -> crate::common::RegisterField<
7367        1,
7368        0x1,
7369        1,
7370        0,
7371        p200pfs_by::Pidr,
7372        p200pfs_by::Pidr,
7373        P200PfsBy_SPEC,
7374        crate::common::R,
7375    > {
7376        crate::common::RegisterField::<
7377            1,
7378            0x1,
7379            1,
7380            0,
7381            p200pfs_by::Pidr,
7382            p200pfs_by::Pidr,
7383            P200PfsBy_SPEC,
7384            crate::common::R,
7385        >::from_register(self, 0)
7386    }
7387
7388    #[doc = "Port Direction"]
7389    #[inline(always)]
7390    pub fn pdr(
7391        self,
7392    ) -> crate::common::RegisterField<
7393        2,
7394        0x1,
7395        1,
7396        0,
7397        p200pfs_by::Pdr,
7398        p200pfs_by::Pdr,
7399        P200PfsBy_SPEC,
7400        crate::common::RW,
7401    > {
7402        crate::common::RegisterField::<
7403            2,
7404            0x1,
7405            1,
7406            0,
7407            p200pfs_by::Pdr,
7408            p200pfs_by::Pdr,
7409            P200PfsBy_SPEC,
7410            crate::common::RW,
7411        >::from_register(self, 0)
7412    }
7413
7414    #[doc = "Pull-up Control"]
7415    #[inline(always)]
7416    pub fn pcr(
7417        self,
7418    ) -> crate::common::RegisterField<
7419        4,
7420        0x1,
7421        1,
7422        0,
7423        p200pfs_by::Pcr,
7424        p200pfs_by::Pcr,
7425        P200PfsBy_SPEC,
7426        crate::common::RW,
7427    > {
7428        crate::common::RegisterField::<
7429            4,
7430            0x1,
7431            1,
7432            0,
7433            p200pfs_by::Pcr,
7434            p200pfs_by::Pcr,
7435            P200PfsBy_SPEC,
7436            crate::common::RW,
7437        >::from_register(self, 0)
7438    }
7439
7440    #[doc = "N-Channel Open-Drain Control"]
7441    #[inline(always)]
7442    pub fn ncodr(
7443        self,
7444    ) -> crate::common::RegisterField<
7445        6,
7446        0x1,
7447        1,
7448        0,
7449        p200pfs_by::Ncodr,
7450        p200pfs_by::Ncodr,
7451        P200PfsBy_SPEC,
7452        crate::common::RW,
7453    > {
7454        crate::common::RegisterField::<
7455            6,
7456            0x1,
7457            1,
7458            0,
7459            p200pfs_by::Ncodr,
7460            p200pfs_by::Ncodr,
7461            P200PfsBy_SPEC,
7462            crate::common::RW,
7463        >::from_register(self, 0)
7464    }
7465}
7466impl ::core::default::Default for P200PfsBy {
7467    #[inline(always)]
7468    fn default() -> P200PfsBy {
7469        <crate::RegValueT<P200PfsBy_SPEC> as RegisterValue<_>>::new(0)
7470    }
7471}
7472pub mod p200pfs_by {
7473
7474    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7475    pub struct Podr_SPEC;
7476    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7477    impl Podr {
7478        #[doc = "Output low"]
7479        pub const _0: Self = Self::new(0);
7480
7481        #[doc = "Output high"]
7482        pub const _1: Self = Self::new(1);
7483    }
7484    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7485    pub struct Pidr_SPEC;
7486    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7487    impl Pidr {
7488        #[doc = "Low level"]
7489        pub const _0: Self = Self::new(0);
7490
7491        #[doc = "High level"]
7492        pub const _1: Self = Self::new(1);
7493    }
7494    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7495    pub struct Pdr_SPEC;
7496    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7497    impl Pdr {
7498        #[doc = "Input (functions as an input pin)"]
7499        pub const _0: Self = Self::new(0);
7500
7501        #[doc = "Output (functions as an output pin)"]
7502        pub const _1: Self = Self::new(1);
7503    }
7504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7505    pub struct Pcr_SPEC;
7506    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7507    impl Pcr {
7508        #[doc = "Disable input pull-up"]
7509        pub const _0: Self = Self::new(0);
7510
7511        #[doc = "Enable input pull-up"]
7512        pub const _1: Self = Self::new(1);
7513    }
7514    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7515    pub struct Ncodr_SPEC;
7516    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7517    impl Ncodr {
7518        #[doc = "Output CMOS"]
7519        pub const _0: Self = Self::new(0);
7520
7521        #[doc = "Output NMOS open-drain"]
7522        pub const _1: Self = Self::new(1);
7523    }
7524}
7525#[doc(hidden)]
7526#[derive(Copy, Clone, Eq, PartialEq)]
7527pub struct P201Pfs_SPEC;
7528impl crate::sealed::RegSpec for P201Pfs_SPEC {
7529    type DataType = u32;
7530}
7531
7532#[doc = "Port 201 Pin Function Select Register"]
7533pub type P201Pfs = crate::RegValueT<P201Pfs_SPEC>;
7534
7535impl P201Pfs {
7536    #[doc = "Port Output Data"]
7537    #[inline(always)]
7538    pub fn podr(
7539        self,
7540    ) -> crate::common::RegisterField<
7541        0,
7542        0x1,
7543        1,
7544        0,
7545        p201pfs::Podr,
7546        p201pfs::Podr,
7547        P201Pfs_SPEC,
7548        crate::common::RW,
7549    > {
7550        crate::common::RegisterField::<
7551            0,
7552            0x1,
7553            1,
7554            0,
7555            p201pfs::Podr,
7556            p201pfs::Podr,
7557            P201Pfs_SPEC,
7558            crate::common::RW,
7559        >::from_register(self, 0)
7560    }
7561
7562    #[doc = "Port State"]
7563    #[inline(always)]
7564    pub fn pidr(
7565        self,
7566    ) -> crate::common::RegisterField<
7567        1,
7568        0x1,
7569        1,
7570        0,
7571        p201pfs::Pidr,
7572        p201pfs::Pidr,
7573        P201Pfs_SPEC,
7574        crate::common::R,
7575    > {
7576        crate::common::RegisterField::<
7577            1,
7578            0x1,
7579            1,
7580            0,
7581            p201pfs::Pidr,
7582            p201pfs::Pidr,
7583            P201Pfs_SPEC,
7584            crate::common::R,
7585        >::from_register(self, 0)
7586    }
7587
7588    #[doc = "Port Direction"]
7589    #[inline(always)]
7590    pub fn pdr(
7591        self,
7592    ) -> crate::common::RegisterField<
7593        2,
7594        0x1,
7595        1,
7596        0,
7597        p201pfs::Pdr,
7598        p201pfs::Pdr,
7599        P201Pfs_SPEC,
7600        crate::common::RW,
7601    > {
7602        crate::common::RegisterField::<
7603            2,
7604            0x1,
7605            1,
7606            0,
7607            p201pfs::Pdr,
7608            p201pfs::Pdr,
7609            P201Pfs_SPEC,
7610            crate::common::RW,
7611        >::from_register(self, 0)
7612    }
7613
7614    #[doc = "Pull-up Control"]
7615    #[inline(always)]
7616    pub fn pcr(
7617        self,
7618    ) -> crate::common::RegisterField<
7619        4,
7620        0x1,
7621        1,
7622        0,
7623        p201pfs::Pcr,
7624        p201pfs::Pcr,
7625        P201Pfs_SPEC,
7626        crate::common::RW,
7627    > {
7628        crate::common::RegisterField::<
7629            4,
7630            0x1,
7631            1,
7632            0,
7633            p201pfs::Pcr,
7634            p201pfs::Pcr,
7635            P201Pfs_SPEC,
7636            crate::common::RW,
7637        >::from_register(self, 0)
7638    }
7639
7640    #[doc = "N-Channel Open-Drain Control"]
7641    #[inline(always)]
7642    pub fn ncodr(
7643        self,
7644    ) -> crate::common::RegisterField<
7645        6,
7646        0x1,
7647        1,
7648        0,
7649        p201pfs::Ncodr,
7650        p201pfs::Ncodr,
7651        P201Pfs_SPEC,
7652        crate::common::RW,
7653    > {
7654        crate::common::RegisterField::<
7655            6,
7656            0x1,
7657            1,
7658            0,
7659            p201pfs::Ncodr,
7660            p201pfs::Ncodr,
7661            P201Pfs_SPEC,
7662            crate::common::RW,
7663        >::from_register(self, 0)
7664    }
7665
7666    #[doc = "Port Drive Capability"]
7667    #[inline(always)]
7668    pub fn dscr(
7669        self,
7670    ) -> crate::common::RegisterField<
7671        10,
7672        0x3,
7673        1,
7674        0,
7675        p201pfs::Dscr,
7676        p201pfs::Dscr,
7677        P201Pfs_SPEC,
7678        crate::common::RW,
7679    > {
7680        crate::common::RegisterField::<
7681            10,
7682            0x3,
7683            1,
7684            0,
7685            p201pfs::Dscr,
7686            p201pfs::Dscr,
7687            P201Pfs_SPEC,
7688            crate::common::RW,
7689        >::from_register(self, 0)
7690    }
7691
7692    #[doc = "Event on Falling/Event on Rising"]
7693    #[inline(always)]
7694    pub fn eofr(
7695        self,
7696    ) -> crate::common::RegisterField<
7697        12,
7698        0x3,
7699        1,
7700        0,
7701        p201pfs::Eofr,
7702        p201pfs::Eofr,
7703        P201Pfs_SPEC,
7704        crate::common::RW,
7705    > {
7706        crate::common::RegisterField::<
7707            12,
7708            0x3,
7709            1,
7710            0,
7711            p201pfs::Eofr,
7712            p201pfs::Eofr,
7713            P201Pfs_SPEC,
7714            crate::common::RW,
7715        >::from_register(self, 0)
7716    }
7717
7718    #[doc = "IRQ Input Enable"]
7719    #[inline(always)]
7720    pub fn isel(
7721        self,
7722    ) -> crate::common::RegisterField<
7723        14,
7724        0x1,
7725        1,
7726        0,
7727        p201pfs::Isel,
7728        p201pfs::Isel,
7729        P201Pfs_SPEC,
7730        crate::common::RW,
7731    > {
7732        crate::common::RegisterField::<
7733            14,
7734            0x1,
7735            1,
7736            0,
7737            p201pfs::Isel,
7738            p201pfs::Isel,
7739            P201Pfs_SPEC,
7740            crate::common::RW,
7741        >::from_register(self, 0)
7742    }
7743
7744    #[doc = "Analog Input Enable"]
7745    #[inline(always)]
7746    pub fn asel(
7747        self,
7748    ) -> crate::common::RegisterField<
7749        15,
7750        0x1,
7751        1,
7752        0,
7753        p201pfs::Asel,
7754        p201pfs::Asel,
7755        P201Pfs_SPEC,
7756        crate::common::RW,
7757    > {
7758        crate::common::RegisterField::<
7759            15,
7760            0x1,
7761            1,
7762            0,
7763            p201pfs::Asel,
7764            p201pfs::Asel,
7765            P201Pfs_SPEC,
7766            crate::common::RW,
7767        >::from_register(self, 0)
7768    }
7769
7770    #[doc = "Port Mode Control"]
7771    #[inline(always)]
7772    pub fn pmr(
7773        self,
7774    ) -> crate::common::RegisterField<
7775        16,
7776        0x1,
7777        1,
7778        0,
7779        p201pfs::Pmr,
7780        p201pfs::Pmr,
7781        P201Pfs_SPEC,
7782        crate::common::RW,
7783    > {
7784        crate::common::RegisterField::<
7785            16,
7786            0x1,
7787            1,
7788            0,
7789            p201pfs::Pmr,
7790            p201pfs::Pmr,
7791            P201Pfs_SPEC,
7792            crate::common::RW,
7793        >::from_register(self, 0)
7794    }
7795
7796    #[doc = "Peripheral Select"]
7797    #[inline(always)]
7798    pub fn psel(
7799        self,
7800    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P201Pfs_SPEC, crate::common::RW> {
7801        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P201Pfs_SPEC,crate::common::RW>::from_register(self,0)
7802    }
7803}
7804impl ::core::default::Default for P201Pfs {
7805    #[inline(always)]
7806    fn default() -> P201Pfs {
7807        <crate::RegValueT<P201Pfs_SPEC> as RegisterValue<_>>::new(16)
7808    }
7809}
7810pub mod p201pfs {
7811
7812    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7813    pub struct Podr_SPEC;
7814    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
7815    impl Podr {
7816        #[doc = "Output low"]
7817        pub const _0: Self = Self::new(0);
7818
7819        #[doc = "Output high"]
7820        pub const _1: Self = Self::new(1);
7821    }
7822    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7823    pub struct Pidr_SPEC;
7824    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
7825    impl Pidr {
7826        #[doc = "Low level"]
7827        pub const _0: Self = Self::new(0);
7828
7829        #[doc = "High level"]
7830        pub const _1: Self = Self::new(1);
7831    }
7832    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7833    pub struct Pdr_SPEC;
7834    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
7835    impl Pdr {
7836        #[doc = "Input (functions as an input pin)"]
7837        pub const _0: Self = Self::new(0);
7838
7839        #[doc = "Output (functions as an output pin)"]
7840        pub const _1: Self = Self::new(1);
7841    }
7842    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7843    pub struct Pcr_SPEC;
7844    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
7845    impl Pcr {
7846        #[doc = "Disable input pull-up"]
7847        pub const _0: Self = Self::new(0);
7848
7849        #[doc = "Enable input pull-up"]
7850        pub const _1: Self = Self::new(1);
7851    }
7852    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7853    pub struct Ncodr_SPEC;
7854    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
7855    impl Ncodr {
7856        #[doc = "Output CMOS"]
7857        pub const _0: Self = Self::new(0);
7858
7859        #[doc = "Output NMOS open-drain"]
7860        pub const _1: Self = Self::new(1);
7861    }
7862    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7863    pub struct Dscr_SPEC;
7864    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
7865    impl Dscr {
7866        #[doc = "Low drive"]
7867        pub const _00: Self = Self::new(0);
7868
7869        #[doc = "Middle drive"]
7870        pub const _01: Self = Self::new(1);
7871
7872        #[doc = "Setting prohibited"]
7873        pub const _10: Self = Self::new(2);
7874
7875        #[doc = "High drive"]
7876        pub const _11: Self = Self::new(3);
7877    }
7878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7879    pub struct Eofr_SPEC;
7880    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
7881    impl Eofr {
7882        #[doc = "Don\'t care"]
7883        pub const _00: Self = Self::new(0);
7884
7885        #[doc = "Detect rising edge"]
7886        pub const _01: Self = Self::new(1);
7887
7888        #[doc = "Detect falling edge"]
7889        pub const _10: Self = Self::new(2);
7890
7891        #[doc = "Detect both edges"]
7892        pub const _11: Self = Self::new(3);
7893    }
7894    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7895    pub struct Isel_SPEC;
7896    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
7897    impl Isel {
7898        #[doc = "Do not use as IRQn input pin"]
7899        pub const _0: Self = Self::new(0);
7900
7901        #[doc = "Use as IRQn input pin"]
7902        pub const _1: Self = Self::new(1);
7903    }
7904    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7905    pub struct Asel_SPEC;
7906    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
7907    impl Asel {
7908        #[doc = "Do not use as analog pin"]
7909        pub const _0: Self = Self::new(0);
7910
7911        #[doc = "Use as analog pin"]
7912        pub const _1: Self = Self::new(1);
7913    }
7914    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7915    pub struct Pmr_SPEC;
7916    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
7917    impl Pmr {
7918        #[doc = "Use as general I/O pin"]
7919        pub const _0: Self = Self::new(0);
7920
7921        #[doc = "Use as I/O port for peripheral functions"]
7922        pub const _1: Self = Self::new(1);
7923    }
7924}
7925#[doc(hidden)]
7926#[derive(Copy, Clone, Eq, PartialEq)]
7927pub struct P201PfsHa_SPEC;
7928impl crate::sealed::RegSpec for P201PfsHa_SPEC {
7929    type DataType = u16;
7930}
7931
7932#[doc = "Port 201 Pin Function Select Register"]
7933pub type P201PfsHa = crate::RegValueT<P201PfsHa_SPEC>;
7934
7935impl P201PfsHa {
7936    #[doc = "Port Output Data"]
7937    #[inline(always)]
7938    pub fn podr(
7939        self,
7940    ) -> crate::common::RegisterField<
7941        0,
7942        0x1,
7943        1,
7944        0,
7945        p201pfs_ha::Podr,
7946        p201pfs_ha::Podr,
7947        P201PfsHa_SPEC,
7948        crate::common::RW,
7949    > {
7950        crate::common::RegisterField::<
7951            0,
7952            0x1,
7953            1,
7954            0,
7955            p201pfs_ha::Podr,
7956            p201pfs_ha::Podr,
7957            P201PfsHa_SPEC,
7958            crate::common::RW,
7959        >::from_register(self, 0)
7960    }
7961
7962    #[doc = "Port State"]
7963    #[inline(always)]
7964    pub fn pidr(
7965        self,
7966    ) -> crate::common::RegisterField<
7967        1,
7968        0x1,
7969        1,
7970        0,
7971        p201pfs_ha::Pidr,
7972        p201pfs_ha::Pidr,
7973        P201PfsHa_SPEC,
7974        crate::common::R,
7975    > {
7976        crate::common::RegisterField::<
7977            1,
7978            0x1,
7979            1,
7980            0,
7981            p201pfs_ha::Pidr,
7982            p201pfs_ha::Pidr,
7983            P201PfsHa_SPEC,
7984            crate::common::R,
7985        >::from_register(self, 0)
7986    }
7987
7988    #[doc = "Port Direction"]
7989    #[inline(always)]
7990    pub fn pdr(
7991        self,
7992    ) -> crate::common::RegisterField<
7993        2,
7994        0x1,
7995        1,
7996        0,
7997        p201pfs_ha::Pdr,
7998        p201pfs_ha::Pdr,
7999        P201PfsHa_SPEC,
8000        crate::common::RW,
8001    > {
8002        crate::common::RegisterField::<
8003            2,
8004            0x1,
8005            1,
8006            0,
8007            p201pfs_ha::Pdr,
8008            p201pfs_ha::Pdr,
8009            P201PfsHa_SPEC,
8010            crate::common::RW,
8011        >::from_register(self, 0)
8012    }
8013
8014    #[doc = "Pull-up Control"]
8015    #[inline(always)]
8016    pub fn pcr(
8017        self,
8018    ) -> crate::common::RegisterField<
8019        4,
8020        0x1,
8021        1,
8022        0,
8023        p201pfs_ha::Pcr,
8024        p201pfs_ha::Pcr,
8025        P201PfsHa_SPEC,
8026        crate::common::RW,
8027    > {
8028        crate::common::RegisterField::<
8029            4,
8030            0x1,
8031            1,
8032            0,
8033            p201pfs_ha::Pcr,
8034            p201pfs_ha::Pcr,
8035            P201PfsHa_SPEC,
8036            crate::common::RW,
8037        >::from_register(self, 0)
8038    }
8039
8040    #[doc = "N-Channel Open-Drain Control"]
8041    #[inline(always)]
8042    pub fn ncodr(
8043        self,
8044    ) -> crate::common::RegisterField<
8045        6,
8046        0x1,
8047        1,
8048        0,
8049        p201pfs_ha::Ncodr,
8050        p201pfs_ha::Ncodr,
8051        P201PfsHa_SPEC,
8052        crate::common::RW,
8053    > {
8054        crate::common::RegisterField::<
8055            6,
8056            0x1,
8057            1,
8058            0,
8059            p201pfs_ha::Ncodr,
8060            p201pfs_ha::Ncodr,
8061            P201PfsHa_SPEC,
8062            crate::common::RW,
8063        >::from_register(self, 0)
8064    }
8065
8066    #[doc = "Port Drive Capability"]
8067    #[inline(always)]
8068    pub fn dscr(
8069        self,
8070    ) -> crate::common::RegisterField<
8071        10,
8072        0x3,
8073        1,
8074        0,
8075        p201pfs_ha::Dscr,
8076        p201pfs_ha::Dscr,
8077        P201PfsHa_SPEC,
8078        crate::common::RW,
8079    > {
8080        crate::common::RegisterField::<
8081            10,
8082            0x3,
8083            1,
8084            0,
8085            p201pfs_ha::Dscr,
8086            p201pfs_ha::Dscr,
8087            P201PfsHa_SPEC,
8088            crate::common::RW,
8089        >::from_register(self, 0)
8090    }
8091
8092    #[doc = "Event on Falling/Event on Rising"]
8093    #[inline(always)]
8094    pub fn eofr(
8095        self,
8096    ) -> crate::common::RegisterField<
8097        12,
8098        0x3,
8099        1,
8100        0,
8101        p201pfs_ha::Eofr,
8102        p201pfs_ha::Eofr,
8103        P201PfsHa_SPEC,
8104        crate::common::RW,
8105    > {
8106        crate::common::RegisterField::<
8107            12,
8108            0x3,
8109            1,
8110            0,
8111            p201pfs_ha::Eofr,
8112            p201pfs_ha::Eofr,
8113            P201PfsHa_SPEC,
8114            crate::common::RW,
8115        >::from_register(self, 0)
8116    }
8117
8118    #[doc = "IRQ Input Enable"]
8119    #[inline(always)]
8120    pub fn isel(
8121        self,
8122    ) -> crate::common::RegisterField<
8123        14,
8124        0x1,
8125        1,
8126        0,
8127        p201pfs_ha::Isel,
8128        p201pfs_ha::Isel,
8129        P201PfsHa_SPEC,
8130        crate::common::RW,
8131    > {
8132        crate::common::RegisterField::<
8133            14,
8134            0x1,
8135            1,
8136            0,
8137            p201pfs_ha::Isel,
8138            p201pfs_ha::Isel,
8139            P201PfsHa_SPEC,
8140            crate::common::RW,
8141        >::from_register(self, 0)
8142    }
8143
8144    #[doc = "Analog Input Enable"]
8145    #[inline(always)]
8146    pub fn asel(
8147        self,
8148    ) -> crate::common::RegisterField<
8149        15,
8150        0x1,
8151        1,
8152        0,
8153        p201pfs_ha::Asel,
8154        p201pfs_ha::Asel,
8155        P201PfsHa_SPEC,
8156        crate::common::RW,
8157    > {
8158        crate::common::RegisterField::<
8159            15,
8160            0x1,
8161            1,
8162            0,
8163            p201pfs_ha::Asel,
8164            p201pfs_ha::Asel,
8165            P201PfsHa_SPEC,
8166            crate::common::RW,
8167        >::from_register(self, 0)
8168    }
8169}
8170impl ::core::default::Default for P201PfsHa {
8171    #[inline(always)]
8172    fn default() -> P201PfsHa {
8173        <crate::RegValueT<P201PfsHa_SPEC> as RegisterValue<_>>::new(16)
8174    }
8175}
8176pub mod p201pfs_ha {
8177
8178    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8179    pub struct Podr_SPEC;
8180    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8181    impl Podr {
8182        #[doc = "Output low"]
8183        pub const _0: Self = Self::new(0);
8184
8185        #[doc = "Output high"]
8186        pub const _1: Self = Self::new(1);
8187    }
8188    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8189    pub struct Pidr_SPEC;
8190    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8191    impl Pidr {
8192        #[doc = "Low level"]
8193        pub const _0: Self = Self::new(0);
8194
8195        #[doc = "High level"]
8196        pub const _1: Self = Self::new(1);
8197    }
8198    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8199    pub struct Pdr_SPEC;
8200    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8201    impl Pdr {
8202        #[doc = "Input (functions as an input pin)"]
8203        pub const _0: Self = Self::new(0);
8204
8205        #[doc = "Output (functions as an output pin)"]
8206        pub const _1: Self = Self::new(1);
8207    }
8208    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8209    pub struct Pcr_SPEC;
8210    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8211    impl Pcr {
8212        #[doc = "Disable input pull-up"]
8213        pub const _0: Self = Self::new(0);
8214
8215        #[doc = "Enable input pull-up"]
8216        pub const _1: Self = Self::new(1);
8217    }
8218    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8219    pub struct Ncodr_SPEC;
8220    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8221    impl Ncodr {
8222        #[doc = "Output CMOS"]
8223        pub const _0: Self = Self::new(0);
8224
8225        #[doc = "Output NMOS open-drain"]
8226        pub const _1: Self = Self::new(1);
8227    }
8228    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8229    pub struct Dscr_SPEC;
8230    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
8231    impl Dscr {
8232        #[doc = "Low drive"]
8233        pub const _00: Self = Self::new(0);
8234
8235        #[doc = "Middle drive"]
8236        pub const _01: Self = Self::new(1);
8237
8238        #[doc = "Setting prohibited"]
8239        pub const _10: Self = Self::new(2);
8240
8241        #[doc = "High drive"]
8242        pub const _11: Self = Self::new(3);
8243    }
8244    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8245    pub struct Eofr_SPEC;
8246    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
8247    impl Eofr {
8248        #[doc = "Don\'t care"]
8249        pub const _00: Self = Self::new(0);
8250
8251        #[doc = "Detect rising edge"]
8252        pub const _01: Self = Self::new(1);
8253
8254        #[doc = "Detect falling edge"]
8255        pub const _10: Self = Self::new(2);
8256
8257        #[doc = "Detect both edges"]
8258        pub const _11: Self = Self::new(3);
8259    }
8260    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8261    pub struct Isel_SPEC;
8262    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
8263    impl Isel {
8264        #[doc = "Do not use as IRQn input pin"]
8265        pub const _0: Self = Self::new(0);
8266
8267        #[doc = "Use as IRQn input pin"]
8268        pub const _1: Self = Self::new(1);
8269    }
8270    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8271    pub struct Asel_SPEC;
8272    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
8273    impl Asel {
8274        #[doc = "Do not use as analog pin"]
8275        pub const _0: Self = Self::new(0);
8276
8277        #[doc = "Use as analog pin"]
8278        pub const _1: Self = Self::new(1);
8279    }
8280}
8281#[doc(hidden)]
8282#[derive(Copy, Clone, Eq, PartialEq)]
8283pub struct P201PfsBy_SPEC;
8284impl crate::sealed::RegSpec for P201PfsBy_SPEC {
8285    type DataType = u8;
8286}
8287
8288#[doc = "Port 201 Pin Function Select Register"]
8289pub type P201PfsBy = crate::RegValueT<P201PfsBy_SPEC>;
8290
8291impl P201PfsBy {
8292    #[doc = "Port Output Data"]
8293    #[inline(always)]
8294    pub fn podr(
8295        self,
8296    ) -> crate::common::RegisterField<
8297        0,
8298        0x1,
8299        1,
8300        0,
8301        p201pfs_by::Podr,
8302        p201pfs_by::Podr,
8303        P201PfsBy_SPEC,
8304        crate::common::RW,
8305    > {
8306        crate::common::RegisterField::<
8307            0,
8308            0x1,
8309            1,
8310            0,
8311            p201pfs_by::Podr,
8312            p201pfs_by::Podr,
8313            P201PfsBy_SPEC,
8314            crate::common::RW,
8315        >::from_register(self, 0)
8316    }
8317
8318    #[doc = "Port State"]
8319    #[inline(always)]
8320    pub fn pidr(
8321        self,
8322    ) -> crate::common::RegisterField<
8323        1,
8324        0x1,
8325        1,
8326        0,
8327        p201pfs_by::Pidr,
8328        p201pfs_by::Pidr,
8329        P201PfsBy_SPEC,
8330        crate::common::R,
8331    > {
8332        crate::common::RegisterField::<
8333            1,
8334            0x1,
8335            1,
8336            0,
8337            p201pfs_by::Pidr,
8338            p201pfs_by::Pidr,
8339            P201PfsBy_SPEC,
8340            crate::common::R,
8341        >::from_register(self, 0)
8342    }
8343
8344    #[doc = "Port Direction"]
8345    #[inline(always)]
8346    pub fn pdr(
8347        self,
8348    ) -> crate::common::RegisterField<
8349        2,
8350        0x1,
8351        1,
8352        0,
8353        p201pfs_by::Pdr,
8354        p201pfs_by::Pdr,
8355        P201PfsBy_SPEC,
8356        crate::common::RW,
8357    > {
8358        crate::common::RegisterField::<
8359            2,
8360            0x1,
8361            1,
8362            0,
8363            p201pfs_by::Pdr,
8364            p201pfs_by::Pdr,
8365            P201PfsBy_SPEC,
8366            crate::common::RW,
8367        >::from_register(self, 0)
8368    }
8369
8370    #[doc = "Pull-up Control"]
8371    #[inline(always)]
8372    pub fn pcr(
8373        self,
8374    ) -> crate::common::RegisterField<
8375        4,
8376        0x1,
8377        1,
8378        0,
8379        p201pfs_by::Pcr,
8380        p201pfs_by::Pcr,
8381        P201PfsBy_SPEC,
8382        crate::common::RW,
8383    > {
8384        crate::common::RegisterField::<
8385            4,
8386            0x1,
8387            1,
8388            0,
8389            p201pfs_by::Pcr,
8390            p201pfs_by::Pcr,
8391            P201PfsBy_SPEC,
8392            crate::common::RW,
8393        >::from_register(self, 0)
8394    }
8395
8396    #[doc = "N-Channel Open-Drain Control"]
8397    #[inline(always)]
8398    pub fn ncodr(
8399        self,
8400    ) -> crate::common::RegisterField<
8401        6,
8402        0x1,
8403        1,
8404        0,
8405        p201pfs_by::Ncodr,
8406        p201pfs_by::Ncodr,
8407        P201PfsBy_SPEC,
8408        crate::common::RW,
8409    > {
8410        crate::common::RegisterField::<
8411            6,
8412            0x1,
8413            1,
8414            0,
8415            p201pfs_by::Ncodr,
8416            p201pfs_by::Ncodr,
8417            P201PfsBy_SPEC,
8418            crate::common::RW,
8419        >::from_register(self, 0)
8420    }
8421}
8422impl ::core::default::Default for P201PfsBy {
8423    #[inline(always)]
8424    fn default() -> P201PfsBy {
8425        <crate::RegValueT<P201PfsBy_SPEC> as RegisterValue<_>>::new(16)
8426    }
8427}
8428pub mod p201pfs_by {
8429
8430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8431    pub struct Podr_SPEC;
8432    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8433    impl Podr {
8434        #[doc = "Output low"]
8435        pub const _0: Self = Self::new(0);
8436
8437        #[doc = "Output high"]
8438        pub const _1: Self = Self::new(1);
8439    }
8440    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8441    pub struct Pidr_SPEC;
8442    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8443    impl Pidr {
8444        #[doc = "Low level"]
8445        pub const _0: Self = Self::new(0);
8446
8447        #[doc = "High level"]
8448        pub const _1: Self = Self::new(1);
8449    }
8450    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8451    pub struct Pdr_SPEC;
8452    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8453    impl Pdr {
8454        #[doc = "Input (functions as an input pin)"]
8455        pub const _0: Self = Self::new(0);
8456
8457        #[doc = "Output (functions as an output pin)"]
8458        pub const _1: Self = Self::new(1);
8459    }
8460    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8461    pub struct Pcr_SPEC;
8462    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8463    impl Pcr {
8464        #[doc = "Disable input pull-up"]
8465        pub const _0: Self = Self::new(0);
8466
8467        #[doc = "Enable input pull-up"]
8468        pub const _1: Self = Self::new(1);
8469    }
8470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8471    pub struct Ncodr_SPEC;
8472    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8473    impl Ncodr {
8474        #[doc = "Output CMOS"]
8475        pub const _0: Self = Self::new(0);
8476
8477        #[doc = "Output NMOS open-drain"]
8478        pub const _1: Self = Self::new(1);
8479    }
8480}
8481#[doc(hidden)]
8482#[derive(Copy, Clone, Eq, PartialEq)]
8483pub struct P20Pfs_SPEC;
8484impl crate::sealed::RegSpec for P20Pfs_SPEC {
8485    type DataType = u32;
8486}
8487
8488#[doc = "Port 20%s Pin Function Select Register"]
8489pub type P20Pfs = crate::RegValueT<P20Pfs_SPEC>;
8490
8491impl P20Pfs {
8492    #[doc = "Port Output Data"]
8493    #[inline(always)]
8494    pub fn podr(
8495        self,
8496    ) -> crate::common::RegisterField<
8497        0,
8498        0x1,
8499        1,
8500        0,
8501        p20pfs::Podr,
8502        p20pfs::Podr,
8503        P20Pfs_SPEC,
8504        crate::common::RW,
8505    > {
8506        crate::common::RegisterField::<
8507            0,
8508            0x1,
8509            1,
8510            0,
8511            p20pfs::Podr,
8512            p20pfs::Podr,
8513            P20Pfs_SPEC,
8514            crate::common::RW,
8515        >::from_register(self, 0)
8516    }
8517
8518    #[doc = "Port State"]
8519    #[inline(always)]
8520    pub fn pidr(
8521        self,
8522    ) -> crate::common::RegisterField<
8523        1,
8524        0x1,
8525        1,
8526        0,
8527        p20pfs::Pidr,
8528        p20pfs::Pidr,
8529        P20Pfs_SPEC,
8530        crate::common::R,
8531    > {
8532        crate::common::RegisterField::<
8533            1,
8534            0x1,
8535            1,
8536            0,
8537            p20pfs::Pidr,
8538            p20pfs::Pidr,
8539            P20Pfs_SPEC,
8540            crate::common::R,
8541        >::from_register(self, 0)
8542    }
8543
8544    #[doc = "Port Direction"]
8545    #[inline(always)]
8546    pub fn pdr(
8547        self,
8548    ) -> crate::common::RegisterField<
8549        2,
8550        0x1,
8551        1,
8552        0,
8553        p20pfs::Pdr,
8554        p20pfs::Pdr,
8555        P20Pfs_SPEC,
8556        crate::common::RW,
8557    > {
8558        crate::common::RegisterField::<
8559            2,
8560            0x1,
8561            1,
8562            0,
8563            p20pfs::Pdr,
8564            p20pfs::Pdr,
8565            P20Pfs_SPEC,
8566            crate::common::RW,
8567        >::from_register(self, 0)
8568    }
8569
8570    #[doc = "Pull-up Control"]
8571    #[inline(always)]
8572    pub fn pcr(
8573        self,
8574    ) -> crate::common::RegisterField<
8575        4,
8576        0x1,
8577        1,
8578        0,
8579        p20pfs::Pcr,
8580        p20pfs::Pcr,
8581        P20Pfs_SPEC,
8582        crate::common::RW,
8583    > {
8584        crate::common::RegisterField::<
8585            4,
8586            0x1,
8587            1,
8588            0,
8589            p20pfs::Pcr,
8590            p20pfs::Pcr,
8591            P20Pfs_SPEC,
8592            crate::common::RW,
8593        >::from_register(self, 0)
8594    }
8595
8596    #[doc = "N-Channel Open-Drain Control"]
8597    #[inline(always)]
8598    pub fn ncodr(
8599        self,
8600    ) -> crate::common::RegisterField<
8601        6,
8602        0x1,
8603        1,
8604        0,
8605        p20pfs::Ncodr,
8606        p20pfs::Ncodr,
8607        P20Pfs_SPEC,
8608        crate::common::RW,
8609    > {
8610        crate::common::RegisterField::<
8611            6,
8612            0x1,
8613            1,
8614            0,
8615            p20pfs::Ncodr,
8616            p20pfs::Ncodr,
8617            P20Pfs_SPEC,
8618            crate::common::RW,
8619        >::from_register(self, 0)
8620    }
8621
8622    #[doc = "Port Drive Capability"]
8623    #[inline(always)]
8624    pub fn dscr(
8625        self,
8626    ) -> crate::common::RegisterField<
8627        10,
8628        0x3,
8629        1,
8630        0,
8631        p20pfs::Dscr,
8632        p20pfs::Dscr,
8633        P20Pfs_SPEC,
8634        crate::common::RW,
8635    > {
8636        crate::common::RegisterField::<
8637            10,
8638            0x3,
8639            1,
8640            0,
8641            p20pfs::Dscr,
8642            p20pfs::Dscr,
8643            P20Pfs_SPEC,
8644            crate::common::RW,
8645        >::from_register(self, 0)
8646    }
8647
8648    #[doc = "Event on Falling/Event on Rising"]
8649    #[inline(always)]
8650    pub fn eofr(
8651        self,
8652    ) -> crate::common::RegisterField<
8653        12,
8654        0x3,
8655        1,
8656        0,
8657        p20pfs::Eofr,
8658        p20pfs::Eofr,
8659        P20Pfs_SPEC,
8660        crate::common::RW,
8661    > {
8662        crate::common::RegisterField::<
8663            12,
8664            0x3,
8665            1,
8666            0,
8667            p20pfs::Eofr,
8668            p20pfs::Eofr,
8669            P20Pfs_SPEC,
8670            crate::common::RW,
8671        >::from_register(self, 0)
8672    }
8673
8674    #[doc = "IRQ Input Enable"]
8675    #[inline(always)]
8676    pub fn isel(
8677        self,
8678    ) -> crate::common::RegisterField<
8679        14,
8680        0x1,
8681        1,
8682        0,
8683        p20pfs::Isel,
8684        p20pfs::Isel,
8685        P20Pfs_SPEC,
8686        crate::common::RW,
8687    > {
8688        crate::common::RegisterField::<
8689            14,
8690            0x1,
8691            1,
8692            0,
8693            p20pfs::Isel,
8694            p20pfs::Isel,
8695            P20Pfs_SPEC,
8696            crate::common::RW,
8697        >::from_register(self, 0)
8698    }
8699
8700    #[doc = "Analog Input Enable"]
8701    #[inline(always)]
8702    pub fn asel(
8703        self,
8704    ) -> crate::common::RegisterField<
8705        15,
8706        0x1,
8707        1,
8708        0,
8709        p20pfs::Asel,
8710        p20pfs::Asel,
8711        P20Pfs_SPEC,
8712        crate::common::RW,
8713    > {
8714        crate::common::RegisterField::<
8715            15,
8716            0x1,
8717            1,
8718            0,
8719            p20pfs::Asel,
8720            p20pfs::Asel,
8721            P20Pfs_SPEC,
8722            crate::common::RW,
8723        >::from_register(self, 0)
8724    }
8725
8726    #[doc = "Port Mode Control"]
8727    #[inline(always)]
8728    pub fn pmr(
8729        self,
8730    ) -> crate::common::RegisterField<
8731        16,
8732        0x1,
8733        1,
8734        0,
8735        p20pfs::Pmr,
8736        p20pfs::Pmr,
8737        P20Pfs_SPEC,
8738        crate::common::RW,
8739    > {
8740        crate::common::RegisterField::<
8741            16,
8742            0x1,
8743            1,
8744            0,
8745            p20pfs::Pmr,
8746            p20pfs::Pmr,
8747            P20Pfs_SPEC,
8748            crate::common::RW,
8749        >::from_register(self, 0)
8750    }
8751
8752    #[doc = "Peripheral Select"]
8753    #[inline(always)]
8754    pub fn psel(
8755        self,
8756    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P20Pfs_SPEC, crate::common::RW> {
8757        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P20Pfs_SPEC,crate::common::RW>::from_register(self,0)
8758    }
8759}
8760impl ::core::default::Default for P20Pfs {
8761    #[inline(always)]
8762    fn default() -> P20Pfs {
8763        <crate::RegValueT<P20Pfs_SPEC> as RegisterValue<_>>::new(0)
8764    }
8765}
8766pub mod p20pfs {
8767
8768    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8769    pub struct Podr_SPEC;
8770    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
8771    impl Podr {
8772        #[doc = "Output low"]
8773        pub const _0: Self = Self::new(0);
8774
8775        #[doc = "Output high"]
8776        pub const _1: Self = Self::new(1);
8777    }
8778    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8779    pub struct Pidr_SPEC;
8780    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
8781    impl Pidr {
8782        #[doc = "Low level"]
8783        pub const _0: Self = Self::new(0);
8784
8785        #[doc = "High level"]
8786        pub const _1: Self = Self::new(1);
8787    }
8788    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8789    pub struct Pdr_SPEC;
8790    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
8791    impl Pdr {
8792        #[doc = "Input (functions as an input pin)"]
8793        pub const _0: Self = Self::new(0);
8794
8795        #[doc = "Output (functions as an output pin)"]
8796        pub const _1: Self = Self::new(1);
8797    }
8798    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8799    pub struct Pcr_SPEC;
8800    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
8801    impl Pcr {
8802        #[doc = "Disable input pull-up"]
8803        pub const _0: Self = Self::new(0);
8804
8805        #[doc = "Enable input pull-up"]
8806        pub const _1: Self = Self::new(1);
8807    }
8808    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8809    pub struct Ncodr_SPEC;
8810    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
8811    impl Ncodr {
8812        #[doc = "Output CMOS"]
8813        pub const _0: Self = Self::new(0);
8814
8815        #[doc = "Output NMOS open-drain"]
8816        pub const _1: Self = Self::new(1);
8817    }
8818    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8819    pub struct Dscr_SPEC;
8820    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
8821    impl Dscr {
8822        #[doc = "Low drive"]
8823        pub const _00: Self = Self::new(0);
8824
8825        #[doc = "Middle drive"]
8826        pub const _01: Self = Self::new(1);
8827
8828        #[doc = "Setting prohibited"]
8829        pub const _10: Self = Self::new(2);
8830
8831        #[doc = "High drive"]
8832        pub const _11: Self = Self::new(3);
8833    }
8834    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8835    pub struct Eofr_SPEC;
8836    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
8837    impl Eofr {
8838        #[doc = "Don\'t care"]
8839        pub const _00: Self = Self::new(0);
8840
8841        #[doc = "Detect rising edge"]
8842        pub const _01: Self = Self::new(1);
8843
8844        #[doc = "Detect falling edge"]
8845        pub const _10: Self = Self::new(2);
8846
8847        #[doc = "Detect both edges"]
8848        pub const _11: Self = Self::new(3);
8849    }
8850    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8851    pub struct Isel_SPEC;
8852    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
8853    impl Isel {
8854        #[doc = "Do not use as IRQn input pin"]
8855        pub const _0: Self = Self::new(0);
8856
8857        #[doc = "Use as IRQn input pin"]
8858        pub const _1: Self = Self::new(1);
8859    }
8860    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8861    pub struct Asel_SPEC;
8862    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
8863    impl Asel {
8864        #[doc = "Do not use as analog pin"]
8865        pub const _0: Self = Self::new(0);
8866
8867        #[doc = "Use as analog pin"]
8868        pub const _1: Self = Self::new(1);
8869    }
8870    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8871    pub struct Pmr_SPEC;
8872    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
8873    impl Pmr {
8874        #[doc = "Use as general I/O pin"]
8875        pub const _0: Self = Self::new(0);
8876
8877        #[doc = "Use as I/O port for peripheral functions"]
8878        pub const _1: Self = Self::new(1);
8879    }
8880}
8881#[doc(hidden)]
8882#[derive(Copy, Clone, Eq, PartialEq)]
8883pub struct P20PfsHa_SPEC;
8884impl crate::sealed::RegSpec for P20PfsHa_SPEC {
8885    type DataType = u16;
8886}
8887
8888#[doc = "Port 20%s Pin Function Select Register"]
8889pub type P20PfsHa = crate::RegValueT<P20PfsHa_SPEC>;
8890
8891impl P20PfsHa {
8892    #[doc = "Port Output Data"]
8893    #[inline(always)]
8894    pub fn podr(
8895        self,
8896    ) -> crate::common::RegisterField<
8897        0,
8898        0x1,
8899        1,
8900        0,
8901        p20pfs_ha::Podr,
8902        p20pfs_ha::Podr,
8903        P20PfsHa_SPEC,
8904        crate::common::RW,
8905    > {
8906        crate::common::RegisterField::<
8907            0,
8908            0x1,
8909            1,
8910            0,
8911            p20pfs_ha::Podr,
8912            p20pfs_ha::Podr,
8913            P20PfsHa_SPEC,
8914            crate::common::RW,
8915        >::from_register(self, 0)
8916    }
8917
8918    #[doc = "Port State"]
8919    #[inline(always)]
8920    pub fn pidr(
8921        self,
8922    ) -> crate::common::RegisterField<
8923        1,
8924        0x1,
8925        1,
8926        0,
8927        p20pfs_ha::Pidr,
8928        p20pfs_ha::Pidr,
8929        P20PfsHa_SPEC,
8930        crate::common::R,
8931    > {
8932        crate::common::RegisterField::<
8933            1,
8934            0x1,
8935            1,
8936            0,
8937            p20pfs_ha::Pidr,
8938            p20pfs_ha::Pidr,
8939            P20PfsHa_SPEC,
8940            crate::common::R,
8941        >::from_register(self, 0)
8942    }
8943
8944    #[doc = "Port Direction"]
8945    #[inline(always)]
8946    pub fn pdr(
8947        self,
8948    ) -> crate::common::RegisterField<
8949        2,
8950        0x1,
8951        1,
8952        0,
8953        p20pfs_ha::Pdr,
8954        p20pfs_ha::Pdr,
8955        P20PfsHa_SPEC,
8956        crate::common::RW,
8957    > {
8958        crate::common::RegisterField::<
8959            2,
8960            0x1,
8961            1,
8962            0,
8963            p20pfs_ha::Pdr,
8964            p20pfs_ha::Pdr,
8965            P20PfsHa_SPEC,
8966            crate::common::RW,
8967        >::from_register(self, 0)
8968    }
8969
8970    #[doc = "Pull-up Control"]
8971    #[inline(always)]
8972    pub fn pcr(
8973        self,
8974    ) -> crate::common::RegisterField<
8975        4,
8976        0x1,
8977        1,
8978        0,
8979        p20pfs_ha::Pcr,
8980        p20pfs_ha::Pcr,
8981        P20PfsHa_SPEC,
8982        crate::common::RW,
8983    > {
8984        crate::common::RegisterField::<
8985            4,
8986            0x1,
8987            1,
8988            0,
8989            p20pfs_ha::Pcr,
8990            p20pfs_ha::Pcr,
8991            P20PfsHa_SPEC,
8992            crate::common::RW,
8993        >::from_register(self, 0)
8994    }
8995
8996    #[doc = "N-Channel Open-Drain Control"]
8997    #[inline(always)]
8998    pub fn ncodr(
8999        self,
9000    ) -> crate::common::RegisterField<
9001        6,
9002        0x1,
9003        1,
9004        0,
9005        p20pfs_ha::Ncodr,
9006        p20pfs_ha::Ncodr,
9007        P20PfsHa_SPEC,
9008        crate::common::RW,
9009    > {
9010        crate::common::RegisterField::<
9011            6,
9012            0x1,
9013            1,
9014            0,
9015            p20pfs_ha::Ncodr,
9016            p20pfs_ha::Ncodr,
9017            P20PfsHa_SPEC,
9018            crate::common::RW,
9019        >::from_register(self, 0)
9020    }
9021
9022    #[doc = "Port Drive Capability"]
9023    #[inline(always)]
9024    pub fn dscr(
9025        self,
9026    ) -> crate::common::RegisterField<
9027        10,
9028        0x3,
9029        1,
9030        0,
9031        p20pfs_ha::Dscr,
9032        p20pfs_ha::Dscr,
9033        P20PfsHa_SPEC,
9034        crate::common::RW,
9035    > {
9036        crate::common::RegisterField::<
9037            10,
9038            0x3,
9039            1,
9040            0,
9041            p20pfs_ha::Dscr,
9042            p20pfs_ha::Dscr,
9043            P20PfsHa_SPEC,
9044            crate::common::RW,
9045        >::from_register(self, 0)
9046    }
9047
9048    #[doc = "Event on Falling/Event on Rising"]
9049    #[inline(always)]
9050    pub fn eofr(
9051        self,
9052    ) -> crate::common::RegisterField<
9053        12,
9054        0x3,
9055        1,
9056        0,
9057        p20pfs_ha::Eofr,
9058        p20pfs_ha::Eofr,
9059        P20PfsHa_SPEC,
9060        crate::common::RW,
9061    > {
9062        crate::common::RegisterField::<
9063            12,
9064            0x3,
9065            1,
9066            0,
9067            p20pfs_ha::Eofr,
9068            p20pfs_ha::Eofr,
9069            P20PfsHa_SPEC,
9070            crate::common::RW,
9071        >::from_register(self, 0)
9072    }
9073
9074    #[doc = "IRQ Input Enable"]
9075    #[inline(always)]
9076    pub fn isel(
9077        self,
9078    ) -> crate::common::RegisterField<
9079        14,
9080        0x1,
9081        1,
9082        0,
9083        p20pfs_ha::Isel,
9084        p20pfs_ha::Isel,
9085        P20PfsHa_SPEC,
9086        crate::common::RW,
9087    > {
9088        crate::common::RegisterField::<
9089            14,
9090            0x1,
9091            1,
9092            0,
9093            p20pfs_ha::Isel,
9094            p20pfs_ha::Isel,
9095            P20PfsHa_SPEC,
9096            crate::common::RW,
9097        >::from_register(self, 0)
9098    }
9099
9100    #[doc = "Analog Input Enable"]
9101    #[inline(always)]
9102    pub fn asel(
9103        self,
9104    ) -> crate::common::RegisterField<
9105        15,
9106        0x1,
9107        1,
9108        0,
9109        p20pfs_ha::Asel,
9110        p20pfs_ha::Asel,
9111        P20PfsHa_SPEC,
9112        crate::common::RW,
9113    > {
9114        crate::common::RegisterField::<
9115            15,
9116            0x1,
9117            1,
9118            0,
9119            p20pfs_ha::Asel,
9120            p20pfs_ha::Asel,
9121            P20PfsHa_SPEC,
9122            crate::common::RW,
9123        >::from_register(self, 0)
9124    }
9125}
9126impl ::core::default::Default for P20PfsHa {
9127    #[inline(always)]
9128    fn default() -> P20PfsHa {
9129        <crate::RegValueT<P20PfsHa_SPEC> as RegisterValue<_>>::new(0)
9130    }
9131}
9132pub mod p20pfs_ha {
9133
9134    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9135    pub struct Podr_SPEC;
9136    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9137    impl Podr {
9138        #[doc = "Output low"]
9139        pub const _0: Self = Self::new(0);
9140
9141        #[doc = "Output high"]
9142        pub const _1: Self = Self::new(1);
9143    }
9144    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9145    pub struct Pidr_SPEC;
9146    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9147    impl Pidr {
9148        #[doc = "Low level"]
9149        pub const _0: Self = Self::new(0);
9150
9151        #[doc = "High level"]
9152        pub const _1: Self = Self::new(1);
9153    }
9154    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9155    pub struct Pdr_SPEC;
9156    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9157    impl Pdr {
9158        #[doc = "Input (functions as an input pin)"]
9159        pub const _0: Self = Self::new(0);
9160
9161        #[doc = "Output (functions as an output pin)"]
9162        pub const _1: Self = Self::new(1);
9163    }
9164    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9165    pub struct Pcr_SPEC;
9166    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9167    impl Pcr {
9168        #[doc = "Disable input pull-up"]
9169        pub const _0: Self = Self::new(0);
9170
9171        #[doc = "Enable input pull-up"]
9172        pub const _1: Self = Self::new(1);
9173    }
9174    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9175    pub struct Ncodr_SPEC;
9176    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9177    impl Ncodr {
9178        #[doc = "Output CMOS"]
9179        pub const _0: Self = Self::new(0);
9180
9181        #[doc = "Output NMOS open-drain"]
9182        pub const _1: Self = Self::new(1);
9183    }
9184    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9185    pub struct Dscr_SPEC;
9186    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
9187    impl Dscr {
9188        #[doc = "Low drive"]
9189        pub const _00: Self = Self::new(0);
9190
9191        #[doc = "Middle drive"]
9192        pub const _01: Self = Self::new(1);
9193
9194        #[doc = "Setting prohibited"]
9195        pub const _10: Self = Self::new(2);
9196
9197        #[doc = "High drive"]
9198        pub const _11: Self = Self::new(3);
9199    }
9200    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9201    pub struct Eofr_SPEC;
9202    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
9203    impl Eofr {
9204        #[doc = "Don\'t care"]
9205        pub const _00: Self = Self::new(0);
9206
9207        #[doc = "Detect rising edge"]
9208        pub const _01: Self = Self::new(1);
9209
9210        #[doc = "Detect falling edge"]
9211        pub const _10: Self = Self::new(2);
9212
9213        #[doc = "Detect both edges"]
9214        pub const _11: Self = Self::new(3);
9215    }
9216    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9217    pub struct Isel_SPEC;
9218    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
9219    impl Isel {
9220        #[doc = "Do not use as IRQn input pin"]
9221        pub const _0: Self = Self::new(0);
9222
9223        #[doc = "Use as IRQn input pin"]
9224        pub const _1: Self = Self::new(1);
9225    }
9226    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9227    pub struct Asel_SPEC;
9228    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
9229    impl Asel {
9230        #[doc = "Do not use as analog pin"]
9231        pub const _0: Self = Self::new(0);
9232
9233        #[doc = "Use as analog pin"]
9234        pub const _1: Self = Self::new(1);
9235    }
9236}
9237#[doc(hidden)]
9238#[derive(Copy, Clone, Eq, PartialEq)]
9239pub struct P20PfsBy_SPEC;
9240impl crate::sealed::RegSpec for P20PfsBy_SPEC {
9241    type DataType = u8;
9242}
9243
9244#[doc = "Port 20%s Pin Function Select Register"]
9245pub type P20PfsBy = crate::RegValueT<P20PfsBy_SPEC>;
9246
9247impl P20PfsBy {
9248    #[doc = "Port Output Data"]
9249    #[inline(always)]
9250    pub fn podr(
9251        self,
9252    ) -> crate::common::RegisterField<
9253        0,
9254        0x1,
9255        1,
9256        0,
9257        p20pfs_by::Podr,
9258        p20pfs_by::Podr,
9259        P20PfsBy_SPEC,
9260        crate::common::RW,
9261    > {
9262        crate::common::RegisterField::<
9263            0,
9264            0x1,
9265            1,
9266            0,
9267            p20pfs_by::Podr,
9268            p20pfs_by::Podr,
9269            P20PfsBy_SPEC,
9270            crate::common::RW,
9271        >::from_register(self, 0)
9272    }
9273
9274    #[doc = "Port State"]
9275    #[inline(always)]
9276    pub fn pidr(
9277        self,
9278    ) -> crate::common::RegisterField<
9279        1,
9280        0x1,
9281        1,
9282        0,
9283        p20pfs_by::Pidr,
9284        p20pfs_by::Pidr,
9285        P20PfsBy_SPEC,
9286        crate::common::R,
9287    > {
9288        crate::common::RegisterField::<
9289            1,
9290            0x1,
9291            1,
9292            0,
9293            p20pfs_by::Pidr,
9294            p20pfs_by::Pidr,
9295            P20PfsBy_SPEC,
9296            crate::common::R,
9297        >::from_register(self, 0)
9298    }
9299
9300    #[doc = "Port Direction"]
9301    #[inline(always)]
9302    pub fn pdr(
9303        self,
9304    ) -> crate::common::RegisterField<
9305        2,
9306        0x1,
9307        1,
9308        0,
9309        p20pfs_by::Pdr,
9310        p20pfs_by::Pdr,
9311        P20PfsBy_SPEC,
9312        crate::common::RW,
9313    > {
9314        crate::common::RegisterField::<
9315            2,
9316            0x1,
9317            1,
9318            0,
9319            p20pfs_by::Pdr,
9320            p20pfs_by::Pdr,
9321            P20PfsBy_SPEC,
9322            crate::common::RW,
9323        >::from_register(self, 0)
9324    }
9325
9326    #[doc = "Pull-up Control"]
9327    #[inline(always)]
9328    pub fn pcr(
9329        self,
9330    ) -> crate::common::RegisterField<
9331        4,
9332        0x1,
9333        1,
9334        0,
9335        p20pfs_by::Pcr,
9336        p20pfs_by::Pcr,
9337        P20PfsBy_SPEC,
9338        crate::common::RW,
9339    > {
9340        crate::common::RegisterField::<
9341            4,
9342            0x1,
9343            1,
9344            0,
9345            p20pfs_by::Pcr,
9346            p20pfs_by::Pcr,
9347            P20PfsBy_SPEC,
9348            crate::common::RW,
9349        >::from_register(self, 0)
9350    }
9351
9352    #[doc = "N-Channel Open-Drain Control"]
9353    #[inline(always)]
9354    pub fn ncodr(
9355        self,
9356    ) -> crate::common::RegisterField<
9357        6,
9358        0x1,
9359        1,
9360        0,
9361        p20pfs_by::Ncodr,
9362        p20pfs_by::Ncodr,
9363        P20PfsBy_SPEC,
9364        crate::common::RW,
9365    > {
9366        crate::common::RegisterField::<
9367            6,
9368            0x1,
9369            1,
9370            0,
9371            p20pfs_by::Ncodr,
9372            p20pfs_by::Ncodr,
9373            P20PfsBy_SPEC,
9374            crate::common::RW,
9375        >::from_register(self, 0)
9376    }
9377}
9378impl ::core::default::Default for P20PfsBy {
9379    #[inline(always)]
9380    fn default() -> P20PfsBy {
9381        <crate::RegValueT<P20PfsBy_SPEC> as RegisterValue<_>>::new(0)
9382    }
9383}
9384pub mod p20pfs_by {
9385
9386    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9387    pub struct Podr_SPEC;
9388    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9389    impl Podr {
9390        #[doc = "Output low"]
9391        pub const _0: Self = Self::new(0);
9392
9393        #[doc = "Output high"]
9394        pub const _1: Self = Self::new(1);
9395    }
9396    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9397    pub struct Pidr_SPEC;
9398    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9399    impl Pidr {
9400        #[doc = "Low level"]
9401        pub const _0: Self = Self::new(0);
9402
9403        #[doc = "High level"]
9404        pub const _1: Self = Self::new(1);
9405    }
9406    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9407    pub struct Pdr_SPEC;
9408    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9409    impl Pdr {
9410        #[doc = "Input (functions as an input pin)"]
9411        pub const _0: Self = Self::new(0);
9412
9413        #[doc = "Output (functions as an output pin)"]
9414        pub const _1: Self = Self::new(1);
9415    }
9416    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9417    pub struct Pcr_SPEC;
9418    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9419    impl Pcr {
9420        #[doc = "Disable input pull-up"]
9421        pub const _0: Self = Self::new(0);
9422
9423        #[doc = "Enable input pull-up"]
9424        pub const _1: Self = Self::new(1);
9425    }
9426    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9427    pub struct Ncodr_SPEC;
9428    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9429    impl Ncodr {
9430        #[doc = "Output CMOS"]
9431        pub const _0: Self = Self::new(0);
9432
9433        #[doc = "Output NMOS open-drain"]
9434        pub const _1: Self = Self::new(1);
9435    }
9436}
9437#[doc(hidden)]
9438#[derive(Copy, Clone, Eq, PartialEq)]
9439pub struct P2Pfs_SPEC;
9440impl crate::sealed::RegSpec for P2Pfs_SPEC {
9441    type DataType = u32;
9442}
9443
9444#[doc = "Port 2%s Pin Function Select Register"]
9445pub type P2Pfs = crate::RegValueT<P2Pfs_SPEC>;
9446
9447impl P2Pfs {
9448    #[doc = "Port Output Data"]
9449    #[inline(always)]
9450    pub fn podr(
9451        self,
9452    ) -> crate::common::RegisterField<
9453        0,
9454        0x1,
9455        1,
9456        0,
9457        p2pfs::Podr,
9458        p2pfs::Podr,
9459        P2Pfs_SPEC,
9460        crate::common::RW,
9461    > {
9462        crate::common::RegisterField::<
9463            0,
9464            0x1,
9465            1,
9466            0,
9467            p2pfs::Podr,
9468            p2pfs::Podr,
9469            P2Pfs_SPEC,
9470            crate::common::RW,
9471        >::from_register(self, 0)
9472    }
9473
9474    #[doc = "Port State"]
9475    #[inline(always)]
9476    pub fn pidr(
9477        self,
9478    ) -> crate::common::RegisterField<
9479        1,
9480        0x1,
9481        1,
9482        0,
9483        p2pfs::Pidr,
9484        p2pfs::Pidr,
9485        P2Pfs_SPEC,
9486        crate::common::R,
9487    > {
9488        crate::common::RegisterField::<
9489            1,
9490            0x1,
9491            1,
9492            0,
9493            p2pfs::Pidr,
9494            p2pfs::Pidr,
9495            P2Pfs_SPEC,
9496            crate::common::R,
9497        >::from_register(self, 0)
9498    }
9499
9500    #[doc = "Port Direction"]
9501    #[inline(always)]
9502    pub fn pdr(
9503        self,
9504    ) -> crate::common::RegisterField<
9505        2,
9506        0x1,
9507        1,
9508        0,
9509        p2pfs::Pdr,
9510        p2pfs::Pdr,
9511        P2Pfs_SPEC,
9512        crate::common::RW,
9513    > {
9514        crate::common::RegisterField::<
9515            2,
9516            0x1,
9517            1,
9518            0,
9519            p2pfs::Pdr,
9520            p2pfs::Pdr,
9521            P2Pfs_SPEC,
9522            crate::common::RW,
9523        >::from_register(self, 0)
9524    }
9525
9526    #[doc = "Pull-up Control"]
9527    #[inline(always)]
9528    pub fn pcr(
9529        self,
9530    ) -> crate::common::RegisterField<
9531        4,
9532        0x1,
9533        1,
9534        0,
9535        p2pfs::Pcr,
9536        p2pfs::Pcr,
9537        P2Pfs_SPEC,
9538        crate::common::RW,
9539    > {
9540        crate::common::RegisterField::<
9541            4,
9542            0x1,
9543            1,
9544            0,
9545            p2pfs::Pcr,
9546            p2pfs::Pcr,
9547            P2Pfs_SPEC,
9548            crate::common::RW,
9549        >::from_register(self, 0)
9550    }
9551
9552    #[doc = "N-Channel Open-Drain Control"]
9553    #[inline(always)]
9554    pub fn ncodr(
9555        self,
9556    ) -> crate::common::RegisterField<
9557        6,
9558        0x1,
9559        1,
9560        0,
9561        p2pfs::Ncodr,
9562        p2pfs::Ncodr,
9563        P2Pfs_SPEC,
9564        crate::common::RW,
9565    > {
9566        crate::common::RegisterField::<
9567            6,
9568            0x1,
9569            1,
9570            0,
9571            p2pfs::Ncodr,
9572            p2pfs::Ncodr,
9573            P2Pfs_SPEC,
9574            crate::common::RW,
9575        >::from_register(self, 0)
9576    }
9577
9578    #[doc = "Port Drive Capability"]
9579    #[inline(always)]
9580    pub fn dscr(
9581        self,
9582    ) -> crate::common::RegisterField<
9583        10,
9584        0x3,
9585        1,
9586        0,
9587        p2pfs::Dscr,
9588        p2pfs::Dscr,
9589        P2Pfs_SPEC,
9590        crate::common::RW,
9591    > {
9592        crate::common::RegisterField::<
9593            10,
9594            0x3,
9595            1,
9596            0,
9597            p2pfs::Dscr,
9598            p2pfs::Dscr,
9599            P2Pfs_SPEC,
9600            crate::common::RW,
9601        >::from_register(self, 0)
9602    }
9603
9604    #[doc = "Event on Falling/Event on Rising"]
9605    #[inline(always)]
9606    pub fn eofr(
9607        self,
9608    ) -> crate::common::RegisterField<
9609        12,
9610        0x3,
9611        1,
9612        0,
9613        p2pfs::Eofr,
9614        p2pfs::Eofr,
9615        P2Pfs_SPEC,
9616        crate::common::RW,
9617    > {
9618        crate::common::RegisterField::<
9619            12,
9620            0x3,
9621            1,
9622            0,
9623            p2pfs::Eofr,
9624            p2pfs::Eofr,
9625            P2Pfs_SPEC,
9626            crate::common::RW,
9627        >::from_register(self, 0)
9628    }
9629
9630    #[doc = "IRQ Input Enable"]
9631    #[inline(always)]
9632    pub fn isel(
9633        self,
9634    ) -> crate::common::RegisterField<
9635        14,
9636        0x1,
9637        1,
9638        0,
9639        p2pfs::Isel,
9640        p2pfs::Isel,
9641        P2Pfs_SPEC,
9642        crate::common::RW,
9643    > {
9644        crate::common::RegisterField::<
9645            14,
9646            0x1,
9647            1,
9648            0,
9649            p2pfs::Isel,
9650            p2pfs::Isel,
9651            P2Pfs_SPEC,
9652            crate::common::RW,
9653        >::from_register(self, 0)
9654    }
9655
9656    #[doc = "Analog Input Enable"]
9657    #[inline(always)]
9658    pub fn asel(
9659        self,
9660    ) -> crate::common::RegisterField<
9661        15,
9662        0x1,
9663        1,
9664        0,
9665        p2pfs::Asel,
9666        p2pfs::Asel,
9667        P2Pfs_SPEC,
9668        crate::common::RW,
9669    > {
9670        crate::common::RegisterField::<
9671            15,
9672            0x1,
9673            1,
9674            0,
9675            p2pfs::Asel,
9676            p2pfs::Asel,
9677            P2Pfs_SPEC,
9678            crate::common::RW,
9679        >::from_register(self, 0)
9680    }
9681
9682    #[doc = "Port Mode Control"]
9683    #[inline(always)]
9684    pub fn pmr(
9685        self,
9686    ) -> crate::common::RegisterField<
9687        16,
9688        0x1,
9689        1,
9690        0,
9691        p2pfs::Pmr,
9692        p2pfs::Pmr,
9693        P2Pfs_SPEC,
9694        crate::common::RW,
9695    > {
9696        crate::common::RegisterField::<
9697            16,
9698            0x1,
9699            1,
9700            0,
9701            p2pfs::Pmr,
9702            p2pfs::Pmr,
9703            P2Pfs_SPEC,
9704            crate::common::RW,
9705        >::from_register(self, 0)
9706    }
9707
9708    #[doc = "Peripheral Select"]
9709    #[inline(always)]
9710    pub fn psel(
9711        self,
9712    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P2Pfs_SPEC, crate::common::RW> {
9713        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P2Pfs_SPEC,crate::common::RW>::from_register(self,0)
9714    }
9715}
9716impl ::core::default::Default for P2Pfs {
9717    #[inline(always)]
9718    fn default() -> P2Pfs {
9719        <crate::RegValueT<P2Pfs_SPEC> as RegisterValue<_>>::new(0)
9720    }
9721}
9722pub mod p2pfs {
9723
9724    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9725    pub struct Podr_SPEC;
9726    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
9727    impl Podr {
9728        #[doc = "Output low"]
9729        pub const _0: Self = Self::new(0);
9730
9731        #[doc = "Output high"]
9732        pub const _1: Self = Self::new(1);
9733    }
9734    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9735    pub struct Pidr_SPEC;
9736    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
9737    impl Pidr {
9738        #[doc = "Low level"]
9739        pub const _0: Self = Self::new(0);
9740
9741        #[doc = "High level"]
9742        pub const _1: Self = Self::new(1);
9743    }
9744    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9745    pub struct Pdr_SPEC;
9746    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
9747    impl Pdr {
9748        #[doc = "Input (functions as an input pin)"]
9749        pub const _0: Self = Self::new(0);
9750
9751        #[doc = "Output (functions as an output pin)"]
9752        pub const _1: Self = Self::new(1);
9753    }
9754    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9755    pub struct Pcr_SPEC;
9756    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
9757    impl Pcr {
9758        #[doc = "Disable input pull-up"]
9759        pub const _0: Self = Self::new(0);
9760
9761        #[doc = "Enable input pull-up"]
9762        pub const _1: Self = Self::new(1);
9763    }
9764    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9765    pub struct Ncodr_SPEC;
9766    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
9767    impl Ncodr {
9768        #[doc = "Output CMOS"]
9769        pub const _0: Self = Self::new(0);
9770
9771        #[doc = "Output NMOS open-drain"]
9772        pub const _1: Self = Self::new(1);
9773    }
9774    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9775    pub struct Dscr_SPEC;
9776    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
9777    impl Dscr {
9778        #[doc = "Low drive"]
9779        pub const _00: Self = Self::new(0);
9780
9781        #[doc = "Middle drive"]
9782        pub const _01: Self = Self::new(1);
9783
9784        #[doc = "Setting prohibited"]
9785        pub const _10: Self = Self::new(2);
9786
9787        #[doc = "High drive"]
9788        pub const _11: Self = Self::new(3);
9789    }
9790    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9791    pub struct Eofr_SPEC;
9792    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
9793    impl Eofr {
9794        #[doc = "Don\'t care"]
9795        pub const _00: Self = Self::new(0);
9796
9797        #[doc = "Detect rising edge"]
9798        pub const _01: Self = Self::new(1);
9799
9800        #[doc = "Detect falling edge"]
9801        pub const _10: Self = Self::new(2);
9802
9803        #[doc = "Detect both edges"]
9804        pub const _11: Self = Self::new(3);
9805    }
9806    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9807    pub struct Isel_SPEC;
9808    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
9809    impl Isel {
9810        #[doc = "Do not use as IRQn input pin"]
9811        pub const _0: Self = Self::new(0);
9812
9813        #[doc = "Use as IRQn input pin"]
9814        pub const _1: Self = Self::new(1);
9815    }
9816    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9817    pub struct Asel_SPEC;
9818    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
9819    impl Asel {
9820        #[doc = "Do not use as analog pin"]
9821        pub const _0: Self = Self::new(0);
9822
9823        #[doc = "Use as analog pin"]
9824        pub const _1: Self = Self::new(1);
9825    }
9826    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9827    pub struct Pmr_SPEC;
9828    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
9829    impl Pmr {
9830        #[doc = "Use as general I/O pin"]
9831        pub const _0: Self = Self::new(0);
9832
9833        #[doc = "Use as I/O port for peripheral functions"]
9834        pub const _1: Self = Self::new(1);
9835    }
9836}
9837#[doc(hidden)]
9838#[derive(Copy, Clone, Eq, PartialEq)]
9839pub struct P2PfsHa_SPEC;
9840impl crate::sealed::RegSpec for P2PfsHa_SPEC {
9841    type DataType = u16;
9842}
9843
9844#[doc = "Port 2%s Pin Function Select Register"]
9845pub type P2PfsHa = crate::RegValueT<P2PfsHa_SPEC>;
9846
9847impl P2PfsHa {
9848    #[doc = "Port Output Data"]
9849    #[inline(always)]
9850    pub fn podr(
9851        self,
9852    ) -> crate::common::RegisterField<
9853        0,
9854        0x1,
9855        1,
9856        0,
9857        p2pfs_ha::Podr,
9858        p2pfs_ha::Podr,
9859        P2PfsHa_SPEC,
9860        crate::common::RW,
9861    > {
9862        crate::common::RegisterField::<
9863            0,
9864            0x1,
9865            1,
9866            0,
9867            p2pfs_ha::Podr,
9868            p2pfs_ha::Podr,
9869            P2PfsHa_SPEC,
9870            crate::common::RW,
9871        >::from_register(self, 0)
9872    }
9873
9874    #[doc = "Port State"]
9875    #[inline(always)]
9876    pub fn pidr(
9877        self,
9878    ) -> crate::common::RegisterField<
9879        1,
9880        0x1,
9881        1,
9882        0,
9883        p2pfs_ha::Pidr,
9884        p2pfs_ha::Pidr,
9885        P2PfsHa_SPEC,
9886        crate::common::R,
9887    > {
9888        crate::common::RegisterField::<
9889            1,
9890            0x1,
9891            1,
9892            0,
9893            p2pfs_ha::Pidr,
9894            p2pfs_ha::Pidr,
9895            P2PfsHa_SPEC,
9896            crate::common::R,
9897        >::from_register(self, 0)
9898    }
9899
9900    #[doc = "Port Direction"]
9901    #[inline(always)]
9902    pub fn pdr(
9903        self,
9904    ) -> crate::common::RegisterField<
9905        2,
9906        0x1,
9907        1,
9908        0,
9909        p2pfs_ha::Pdr,
9910        p2pfs_ha::Pdr,
9911        P2PfsHa_SPEC,
9912        crate::common::RW,
9913    > {
9914        crate::common::RegisterField::<
9915            2,
9916            0x1,
9917            1,
9918            0,
9919            p2pfs_ha::Pdr,
9920            p2pfs_ha::Pdr,
9921            P2PfsHa_SPEC,
9922            crate::common::RW,
9923        >::from_register(self, 0)
9924    }
9925
9926    #[doc = "Pull-up Control"]
9927    #[inline(always)]
9928    pub fn pcr(
9929        self,
9930    ) -> crate::common::RegisterField<
9931        4,
9932        0x1,
9933        1,
9934        0,
9935        p2pfs_ha::Pcr,
9936        p2pfs_ha::Pcr,
9937        P2PfsHa_SPEC,
9938        crate::common::RW,
9939    > {
9940        crate::common::RegisterField::<
9941            4,
9942            0x1,
9943            1,
9944            0,
9945            p2pfs_ha::Pcr,
9946            p2pfs_ha::Pcr,
9947            P2PfsHa_SPEC,
9948            crate::common::RW,
9949        >::from_register(self, 0)
9950    }
9951
9952    #[doc = "N-Channel Open-Drain Control"]
9953    #[inline(always)]
9954    pub fn ncodr(
9955        self,
9956    ) -> crate::common::RegisterField<
9957        6,
9958        0x1,
9959        1,
9960        0,
9961        p2pfs_ha::Ncodr,
9962        p2pfs_ha::Ncodr,
9963        P2PfsHa_SPEC,
9964        crate::common::RW,
9965    > {
9966        crate::common::RegisterField::<
9967            6,
9968            0x1,
9969            1,
9970            0,
9971            p2pfs_ha::Ncodr,
9972            p2pfs_ha::Ncodr,
9973            P2PfsHa_SPEC,
9974            crate::common::RW,
9975        >::from_register(self, 0)
9976    }
9977
9978    #[doc = "Port Drive Capability"]
9979    #[inline(always)]
9980    pub fn dscr(
9981        self,
9982    ) -> crate::common::RegisterField<
9983        10,
9984        0x3,
9985        1,
9986        0,
9987        p2pfs_ha::Dscr,
9988        p2pfs_ha::Dscr,
9989        P2PfsHa_SPEC,
9990        crate::common::RW,
9991    > {
9992        crate::common::RegisterField::<
9993            10,
9994            0x3,
9995            1,
9996            0,
9997            p2pfs_ha::Dscr,
9998            p2pfs_ha::Dscr,
9999            P2PfsHa_SPEC,
10000            crate::common::RW,
10001        >::from_register(self, 0)
10002    }
10003
10004    #[doc = "Event on Falling/Event on Rising"]
10005    #[inline(always)]
10006    pub fn eofr(
10007        self,
10008    ) -> crate::common::RegisterField<
10009        12,
10010        0x3,
10011        1,
10012        0,
10013        p2pfs_ha::Eofr,
10014        p2pfs_ha::Eofr,
10015        P2PfsHa_SPEC,
10016        crate::common::RW,
10017    > {
10018        crate::common::RegisterField::<
10019            12,
10020            0x3,
10021            1,
10022            0,
10023            p2pfs_ha::Eofr,
10024            p2pfs_ha::Eofr,
10025            P2PfsHa_SPEC,
10026            crate::common::RW,
10027        >::from_register(self, 0)
10028    }
10029
10030    #[doc = "IRQ Input Enable"]
10031    #[inline(always)]
10032    pub fn isel(
10033        self,
10034    ) -> crate::common::RegisterField<
10035        14,
10036        0x1,
10037        1,
10038        0,
10039        p2pfs_ha::Isel,
10040        p2pfs_ha::Isel,
10041        P2PfsHa_SPEC,
10042        crate::common::RW,
10043    > {
10044        crate::common::RegisterField::<
10045            14,
10046            0x1,
10047            1,
10048            0,
10049            p2pfs_ha::Isel,
10050            p2pfs_ha::Isel,
10051            P2PfsHa_SPEC,
10052            crate::common::RW,
10053        >::from_register(self, 0)
10054    }
10055
10056    #[doc = "Analog Input Enable"]
10057    #[inline(always)]
10058    pub fn asel(
10059        self,
10060    ) -> crate::common::RegisterField<
10061        15,
10062        0x1,
10063        1,
10064        0,
10065        p2pfs_ha::Asel,
10066        p2pfs_ha::Asel,
10067        P2PfsHa_SPEC,
10068        crate::common::RW,
10069    > {
10070        crate::common::RegisterField::<
10071            15,
10072            0x1,
10073            1,
10074            0,
10075            p2pfs_ha::Asel,
10076            p2pfs_ha::Asel,
10077            P2PfsHa_SPEC,
10078            crate::common::RW,
10079        >::from_register(self, 0)
10080    }
10081}
10082impl ::core::default::Default for P2PfsHa {
10083    #[inline(always)]
10084    fn default() -> P2PfsHa {
10085        <crate::RegValueT<P2PfsHa_SPEC> as RegisterValue<_>>::new(0)
10086    }
10087}
10088pub mod p2pfs_ha {
10089
10090    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10091    pub struct Podr_SPEC;
10092    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10093    impl Podr {
10094        #[doc = "Output low"]
10095        pub const _0: Self = Self::new(0);
10096
10097        #[doc = "Output high"]
10098        pub const _1: Self = Self::new(1);
10099    }
10100    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10101    pub struct Pidr_SPEC;
10102    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10103    impl Pidr {
10104        #[doc = "Low level"]
10105        pub const _0: Self = Self::new(0);
10106
10107        #[doc = "High level"]
10108        pub const _1: Self = Self::new(1);
10109    }
10110    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10111    pub struct Pdr_SPEC;
10112    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10113    impl Pdr {
10114        #[doc = "Input (functions as an input pin)"]
10115        pub const _0: Self = Self::new(0);
10116
10117        #[doc = "Output (functions as an output pin)"]
10118        pub const _1: Self = Self::new(1);
10119    }
10120    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10121    pub struct Pcr_SPEC;
10122    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10123    impl Pcr {
10124        #[doc = "Disable input pull-up"]
10125        pub const _0: Self = Self::new(0);
10126
10127        #[doc = "Enable input pull-up"]
10128        pub const _1: Self = Self::new(1);
10129    }
10130    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10131    pub struct Ncodr_SPEC;
10132    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10133    impl Ncodr {
10134        #[doc = "Output CMOS"]
10135        pub const _0: Self = Self::new(0);
10136
10137        #[doc = "Output NMOS open-drain"]
10138        pub const _1: Self = Self::new(1);
10139    }
10140    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10141    pub struct Dscr_SPEC;
10142    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
10143    impl Dscr {
10144        #[doc = "Low drive"]
10145        pub const _00: Self = Self::new(0);
10146
10147        #[doc = "Middle drive"]
10148        pub const _01: Self = Self::new(1);
10149
10150        #[doc = "Setting prohibited"]
10151        pub const _10: Self = Self::new(2);
10152
10153        #[doc = "High drive"]
10154        pub const _11: Self = Self::new(3);
10155    }
10156    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10157    pub struct Eofr_SPEC;
10158    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
10159    impl Eofr {
10160        #[doc = "Don\'t care"]
10161        pub const _00: Self = Self::new(0);
10162
10163        #[doc = "Detect rising edge"]
10164        pub const _01: Self = Self::new(1);
10165
10166        #[doc = "Detect falling edge"]
10167        pub const _10: Self = Self::new(2);
10168
10169        #[doc = "Detect both edges"]
10170        pub const _11: Self = Self::new(3);
10171    }
10172    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10173    pub struct Isel_SPEC;
10174    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
10175    impl Isel {
10176        #[doc = "Do not use as IRQn input pin"]
10177        pub const _0: Self = Self::new(0);
10178
10179        #[doc = "Use as IRQn input pin"]
10180        pub const _1: Self = Self::new(1);
10181    }
10182    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10183    pub struct Asel_SPEC;
10184    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
10185    impl Asel {
10186        #[doc = "Do not use as analog pin"]
10187        pub const _0: Self = Self::new(0);
10188
10189        #[doc = "Use as analog pin"]
10190        pub const _1: Self = Self::new(1);
10191    }
10192}
10193#[doc(hidden)]
10194#[derive(Copy, Clone, Eq, PartialEq)]
10195pub struct P2PfsBy_SPEC;
10196impl crate::sealed::RegSpec for P2PfsBy_SPEC {
10197    type DataType = u8;
10198}
10199
10200#[doc = "Port 2%s Pin Function Select Register"]
10201pub type P2PfsBy = crate::RegValueT<P2PfsBy_SPEC>;
10202
10203impl P2PfsBy {
10204    #[doc = "Port Output Data"]
10205    #[inline(always)]
10206    pub fn podr(
10207        self,
10208    ) -> crate::common::RegisterField<
10209        0,
10210        0x1,
10211        1,
10212        0,
10213        p2pfs_by::Podr,
10214        p2pfs_by::Podr,
10215        P2PfsBy_SPEC,
10216        crate::common::RW,
10217    > {
10218        crate::common::RegisterField::<
10219            0,
10220            0x1,
10221            1,
10222            0,
10223            p2pfs_by::Podr,
10224            p2pfs_by::Podr,
10225            P2PfsBy_SPEC,
10226            crate::common::RW,
10227        >::from_register(self, 0)
10228    }
10229
10230    #[doc = "Port State"]
10231    #[inline(always)]
10232    pub fn pidr(
10233        self,
10234    ) -> crate::common::RegisterField<
10235        1,
10236        0x1,
10237        1,
10238        0,
10239        p2pfs_by::Pidr,
10240        p2pfs_by::Pidr,
10241        P2PfsBy_SPEC,
10242        crate::common::R,
10243    > {
10244        crate::common::RegisterField::<
10245            1,
10246            0x1,
10247            1,
10248            0,
10249            p2pfs_by::Pidr,
10250            p2pfs_by::Pidr,
10251            P2PfsBy_SPEC,
10252            crate::common::R,
10253        >::from_register(self, 0)
10254    }
10255
10256    #[doc = "Port Direction"]
10257    #[inline(always)]
10258    pub fn pdr(
10259        self,
10260    ) -> crate::common::RegisterField<
10261        2,
10262        0x1,
10263        1,
10264        0,
10265        p2pfs_by::Pdr,
10266        p2pfs_by::Pdr,
10267        P2PfsBy_SPEC,
10268        crate::common::RW,
10269    > {
10270        crate::common::RegisterField::<
10271            2,
10272            0x1,
10273            1,
10274            0,
10275            p2pfs_by::Pdr,
10276            p2pfs_by::Pdr,
10277            P2PfsBy_SPEC,
10278            crate::common::RW,
10279        >::from_register(self, 0)
10280    }
10281
10282    #[doc = "Pull-up Control"]
10283    #[inline(always)]
10284    pub fn pcr(
10285        self,
10286    ) -> crate::common::RegisterField<
10287        4,
10288        0x1,
10289        1,
10290        0,
10291        p2pfs_by::Pcr,
10292        p2pfs_by::Pcr,
10293        P2PfsBy_SPEC,
10294        crate::common::RW,
10295    > {
10296        crate::common::RegisterField::<
10297            4,
10298            0x1,
10299            1,
10300            0,
10301            p2pfs_by::Pcr,
10302            p2pfs_by::Pcr,
10303            P2PfsBy_SPEC,
10304            crate::common::RW,
10305        >::from_register(self, 0)
10306    }
10307
10308    #[doc = "N-Channel Open-Drain Control"]
10309    #[inline(always)]
10310    pub fn ncodr(
10311        self,
10312    ) -> crate::common::RegisterField<
10313        6,
10314        0x1,
10315        1,
10316        0,
10317        p2pfs_by::Ncodr,
10318        p2pfs_by::Ncodr,
10319        P2PfsBy_SPEC,
10320        crate::common::RW,
10321    > {
10322        crate::common::RegisterField::<
10323            6,
10324            0x1,
10325            1,
10326            0,
10327            p2pfs_by::Ncodr,
10328            p2pfs_by::Ncodr,
10329            P2PfsBy_SPEC,
10330            crate::common::RW,
10331        >::from_register(self, 0)
10332    }
10333}
10334impl ::core::default::Default for P2PfsBy {
10335    #[inline(always)]
10336    fn default() -> P2PfsBy {
10337        <crate::RegValueT<P2PfsBy_SPEC> as RegisterValue<_>>::new(0)
10338    }
10339}
10340pub mod p2pfs_by {
10341
10342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10343    pub struct Podr_SPEC;
10344    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10345    impl Podr {
10346        #[doc = "Output low"]
10347        pub const _0: Self = Self::new(0);
10348
10349        #[doc = "Output high"]
10350        pub const _1: Self = Self::new(1);
10351    }
10352    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10353    pub struct Pidr_SPEC;
10354    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10355    impl Pidr {
10356        #[doc = "Low level"]
10357        pub const _0: Self = Self::new(0);
10358
10359        #[doc = "High level"]
10360        pub const _1: Self = Self::new(1);
10361    }
10362    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10363    pub struct Pdr_SPEC;
10364    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10365    impl Pdr {
10366        #[doc = "Input (functions as an input pin)"]
10367        pub const _0: Self = Self::new(0);
10368
10369        #[doc = "Output (functions as an output pin)"]
10370        pub const _1: Self = Self::new(1);
10371    }
10372    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10373    pub struct Pcr_SPEC;
10374    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10375    impl Pcr {
10376        #[doc = "Disable input pull-up"]
10377        pub const _0: Self = Self::new(0);
10378
10379        #[doc = "Enable input pull-up"]
10380        pub const _1: Self = Self::new(1);
10381    }
10382    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10383    pub struct Ncodr_SPEC;
10384    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10385    impl Ncodr {
10386        #[doc = "Output CMOS"]
10387        pub const _0: Self = Self::new(0);
10388
10389        #[doc = "Output NMOS open-drain"]
10390        pub const _1: Self = Self::new(1);
10391    }
10392}
10393#[doc(hidden)]
10394#[derive(Copy, Clone, Eq, PartialEq)]
10395pub struct P300Pfs_SPEC;
10396impl crate::sealed::RegSpec for P300Pfs_SPEC {
10397    type DataType = u32;
10398}
10399
10400#[doc = "Port 300 Pin Function Select Register"]
10401pub type P300Pfs = crate::RegValueT<P300Pfs_SPEC>;
10402
10403impl P300Pfs {
10404    #[doc = "Port Output Data"]
10405    #[inline(always)]
10406    pub fn podr(
10407        self,
10408    ) -> crate::common::RegisterField<
10409        0,
10410        0x1,
10411        1,
10412        0,
10413        p300pfs::Podr,
10414        p300pfs::Podr,
10415        P300Pfs_SPEC,
10416        crate::common::RW,
10417    > {
10418        crate::common::RegisterField::<
10419            0,
10420            0x1,
10421            1,
10422            0,
10423            p300pfs::Podr,
10424            p300pfs::Podr,
10425            P300Pfs_SPEC,
10426            crate::common::RW,
10427        >::from_register(self, 0)
10428    }
10429
10430    #[doc = "Port State"]
10431    #[inline(always)]
10432    pub fn pidr(
10433        self,
10434    ) -> crate::common::RegisterField<
10435        1,
10436        0x1,
10437        1,
10438        0,
10439        p300pfs::Pidr,
10440        p300pfs::Pidr,
10441        P300Pfs_SPEC,
10442        crate::common::R,
10443    > {
10444        crate::common::RegisterField::<
10445            1,
10446            0x1,
10447            1,
10448            0,
10449            p300pfs::Pidr,
10450            p300pfs::Pidr,
10451            P300Pfs_SPEC,
10452            crate::common::R,
10453        >::from_register(self, 0)
10454    }
10455
10456    #[doc = "Port Direction"]
10457    #[inline(always)]
10458    pub fn pdr(
10459        self,
10460    ) -> crate::common::RegisterField<
10461        2,
10462        0x1,
10463        1,
10464        0,
10465        p300pfs::Pdr,
10466        p300pfs::Pdr,
10467        P300Pfs_SPEC,
10468        crate::common::RW,
10469    > {
10470        crate::common::RegisterField::<
10471            2,
10472            0x1,
10473            1,
10474            0,
10475            p300pfs::Pdr,
10476            p300pfs::Pdr,
10477            P300Pfs_SPEC,
10478            crate::common::RW,
10479        >::from_register(self, 0)
10480    }
10481
10482    #[doc = "Pull-up Control"]
10483    #[inline(always)]
10484    pub fn pcr(
10485        self,
10486    ) -> crate::common::RegisterField<
10487        4,
10488        0x1,
10489        1,
10490        0,
10491        p300pfs::Pcr,
10492        p300pfs::Pcr,
10493        P300Pfs_SPEC,
10494        crate::common::RW,
10495    > {
10496        crate::common::RegisterField::<
10497            4,
10498            0x1,
10499            1,
10500            0,
10501            p300pfs::Pcr,
10502            p300pfs::Pcr,
10503            P300Pfs_SPEC,
10504            crate::common::RW,
10505        >::from_register(self, 0)
10506    }
10507
10508    #[doc = "N-Channel Open-Drain Control"]
10509    #[inline(always)]
10510    pub fn ncodr(
10511        self,
10512    ) -> crate::common::RegisterField<
10513        6,
10514        0x1,
10515        1,
10516        0,
10517        p300pfs::Ncodr,
10518        p300pfs::Ncodr,
10519        P300Pfs_SPEC,
10520        crate::common::RW,
10521    > {
10522        crate::common::RegisterField::<
10523            6,
10524            0x1,
10525            1,
10526            0,
10527            p300pfs::Ncodr,
10528            p300pfs::Ncodr,
10529            P300Pfs_SPEC,
10530            crate::common::RW,
10531        >::from_register(self, 0)
10532    }
10533
10534    #[doc = "Port Drive Capability"]
10535    #[inline(always)]
10536    pub fn dscr(
10537        self,
10538    ) -> crate::common::RegisterField<
10539        10,
10540        0x3,
10541        1,
10542        0,
10543        p300pfs::Dscr,
10544        p300pfs::Dscr,
10545        P300Pfs_SPEC,
10546        crate::common::RW,
10547    > {
10548        crate::common::RegisterField::<
10549            10,
10550            0x3,
10551            1,
10552            0,
10553            p300pfs::Dscr,
10554            p300pfs::Dscr,
10555            P300Pfs_SPEC,
10556            crate::common::RW,
10557        >::from_register(self, 0)
10558    }
10559
10560    #[doc = "Event on Falling/Event on Rising"]
10561    #[inline(always)]
10562    pub fn eofr(
10563        self,
10564    ) -> crate::common::RegisterField<
10565        12,
10566        0x3,
10567        1,
10568        0,
10569        p300pfs::Eofr,
10570        p300pfs::Eofr,
10571        P300Pfs_SPEC,
10572        crate::common::RW,
10573    > {
10574        crate::common::RegisterField::<
10575            12,
10576            0x3,
10577            1,
10578            0,
10579            p300pfs::Eofr,
10580            p300pfs::Eofr,
10581            P300Pfs_SPEC,
10582            crate::common::RW,
10583        >::from_register(self, 0)
10584    }
10585
10586    #[doc = "IRQ Input Enable"]
10587    #[inline(always)]
10588    pub fn isel(
10589        self,
10590    ) -> crate::common::RegisterField<
10591        14,
10592        0x1,
10593        1,
10594        0,
10595        p300pfs::Isel,
10596        p300pfs::Isel,
10597        P300Pfs_SPEC,
10598        crate::common::RW,
10599    > {
10600        crate::common::RegisterField::<
10601            14,
10602            0x1,
10603            1,
10604            0,
10605            p300pfs::Isel,
10606            p300pfs::Isel,
10607            P300Pfs_SPEC,
10608            crate::common::RW,
10609        >::from_register(self, 0)
10610    }
10611
10612    #[doc = "Analog Input Enable"]
10613    #[inline(always)]
10614    pub fn asel(
10615        self,
10616    ) -> crate::common::RegisterField<
10617        15,
10618        0x1,
10619        1,
10620        0,
10621        p300pfs::Asel,
10622        p300pfs::Asel,
10623        P300Pfs_SPEC,
10624        crate::common::RW,
10625    > {
10626        crate::common::RegisterField::<
10627            15,
10628            0x1,
10629            1,
10630            0,
10631            p300pfs::Asel,
10632            p300pfs::Asel,
10633            P300Pfs_SPEC,
10634            crate::common::RW,
10635        >::from_register(self, 0)
10636    }
10637
10638    #[doc = "Port Mode Control"]
10639    #[inline(always)]
10640    pub fn pmr(
10641        self,
10642    ) -> crate::common::RegisterField<
10643        16,
10644        0x1,
10645        1,
10646        0,
10647        p300pfs::Pmr,
10648        p300pfs::Pmr,
10649        P300Pfs_SPEC,
10650        crate::common::RW,
10651    > {
10652        crate::common::RegisterField::<
10653            16,
10654            0x1,
10655            1,
10656            0,
10657            p300pfs::Pmr,
10658            p300pfs::Pmr,
10659            P300Pfs_SPEC,
10660            crate::common::RW,
10661        >::from_register(self, 0)
10662    }
10663
10664    #[doc = "Peripheral Select"]
10665    #[inline(always)]
10666    pub fn psel(
10667        self,
10668    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P300Pfs_SPEC, crate::common::RW> {
10669        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P300Pfs_SPEC,crate::common::RW>::from_register(self,0)
10670    }
10671}
10672impl ::core::default::Default for P300Pfs {
10673    #[inline(always)]
10674    fn default() -> P300Pfs {
10675        <crate::RegValueT<P300Pfs_SPEC> as RegisterValue<_>>::new(65552)
10676    }
10677}
10678pub mod p300pfs {
10679
10680    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10681    pub struct Podr_SPEC;
10682    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
10683    impl Podr {
10684        #[doc = "Output low"]
10685        pub const _0: Self = Self::new(0);
10686
10687        #[doc = "Output high"]
10688        pub const _1: Self = Self::new(1);
10689    }
10690    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10691    pub struct Pidr_SPEC;
10692    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
10693    impl Pidr {
10694        #[doc = "Low level"]
10695        pub const _0: Self = Self::new(0);
10696
10697        #[doc = "High level"]
10698        pub const _1: Self = Self::new(1);
10699    }
10700    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10701    pub struct Pdr_SPEC;
10702    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
10703    impl Pdr {
10704        #[doc = "Input (functions as an input pin)"]
10705        pub const _0: Self = Self::new(0);
10706
10707        #[doc = "Output (functions as an output pin)"]
10708        pub const _1: Self = Self::new(1);
10709    }
10710    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10711    pub struct Pcr_SPEC;
10712    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
10713    impl Pcr {
10714        #[doc = "Disable input pull-up"]
10715        pub const _0: Self = Self::new(0);
10716
10717        #[doc = "Enable input pull-up"]
10718        pub const _1: Self = Self::new(1);
10719    }
10720    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10721    pub struct Ncodr_SPEC;
10722    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
10723    impl Ncodr {
10724        #[doc = "Output CMOS"]
10725        pub const _0: Self = Self::new(0);
10726
10727        #[doc = "Output NMOS open-drain"]
10728        pub const _1: Self = Self::new(1);
10729    }
10730    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10731    pub struct Dscr_SPEC;
10732    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
10733    impl Dscr {
10734        #[doc = "Low drive"]
10735        pub const _00: Self = Self::new(0);
10736
10737        #[doc = "Middle drive"]
10738        pub const _01: Self = Self::new(1);
10739
10740        #[doc = "Setting prohibited"]
10741        pub const _10: Self = Self::new(2);
10742
10743        #[doc = "High drive"]
10744        pub const _11: Self = Self::new(3);
10745    }
10746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10747    pub struct Eofr_SPEC;
10748    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
10749    impl Eofr {
10750        #[doc = "Don\'t care"]
10751        pub const _00: Self = Self::new(0);
10752
10753        #[doc = "Detect rising edge"]
10754        pub const _01: Self = Self::new(1);
10755
10756        #[doc = "Detect falling edge"]
10757        pub const _10: Self = Self::new(2);
10758
10759        #[doc = "Detect both edges"]
10760        pub const _11: Self = Self::new(3);
10761    }
10762    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10763    pub struct Isel_SPEC;
10764    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
10765    impl Isel {
10766        #[doc = "Do not use as IRQn input pin"]
10767        pub const _0: Self = Self::new(0);
10768
10769        #[doc = "Use as IRQn input pin"]
10770        pub const _1: Self = Self::new(1);
10771    }
10772    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10773    pub struct Asel_SPEC;
10774    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
10775    impl Asel {
10776        #[doc = "Do not use as analog pin"]
10777        pub const _0: Self = Self::new(0);
10778
10779        #[doc = "Use as analog pin"]
10780        pub const _1: Self = Self::new(1);
10781    }
10782    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10783    pub struct Pmr_SPEC;
10784    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
10785    impl Pmr {
10786        #[doc = "Use as general I/O pin"]
10787        pub const _0: Self = Self::new(0);
10788
10789        #[doc = "Use as I/O port for peripheral functions"]
10790        pub const _1: Self = Self::new(1);
10791    }
10792}
10793#[doc(hidden)]
10794#[derive(Copy, Clone, Eq, PartialEq)]
10795pub struct P300PfsHa_SPEC;
10796impl crate::sealed::RegSpec for P300PfsHa_SPEC {
10797    type DataType = u16;
10798}
10799
10800#[doc = "Port 300 Pin Function Select Register"]
10801pub type P300PfsHa = crate::RegValueT<P300PfsHa_SPEC>;
10802
10803impl P300PfsHa {
10804    #[doc = "Port Output Data"]
10805    #[inline(always)]
10806    pub fn podr(
10807        self,
10808    ) -> crate::common::RegisterField<
10809        0,
10810        0x1,
10811        1,
10812        0,
10813        p300pfs_ha::Podr,
10814        p300pfs_ha::Podr,
10815        P300PfsHa_SPEC,
10816        crate::common::RW,
10817    > {
10818        crate::common::RegisterField::<
10819            0,
10820            0x1,
10821            1,
10822            0,
10823            p300pfs_ha::Podr,
10824            p300pfs_ha::Podr,
10825            P300PfsHa_SPEC,
10826            crate::common::RW,
10827        >::from_register(self, 0)
10828    }
10829
10830    #[doc = "Port State"]
10831    #[inline(always)]
10832    pub fn pidr(
10833        self,
10834    ) -> crate::common::RegisterField<
10835        1,
10836        0x1,
10837        1,
10838        0,
10839        p300pfs_ha::Pidr,
10840        p300pfs_ha::Pidr,
10841        P300PfsHa_SPEC,
10842        crate::common::R,
10843    > {
10844        crate::common::RegisterField::<
10845            1,
10846            0x1,
10847            1,
10848            0,
10849            p300pfs_ha::Pidr,
10850            p300pfs_ha::Pidr,
10851            P300PfsHa_SPEC,
10852            crate::common::R,
10853        >::from_register(self, 0)
10854    }
10855
10856    #[doc = "Port Direction"]
10857    #[inline(always)]
10858    pub fn pdr(
10859        self,
10860    ) -> crate::common::RegisterField<
10861        2,
10862        0x1,
10863        1,
10864        0,
10865        p300pfs_ha::Pdr,
10866        p300pfs_ha::Pdr,
10867        P300PfsHa_SPEC,
10868        crate::common::RW,
10869    > {
10870        crate::common::RegisterField::<
10871            2,
10872            0x1,
10873            1,
10874            0,
10875            p300pfs_ha::Pdr,
10876            p300pfs_ha::Pdr,
10877            P300PfsHa_SPEC,
10878            crate::common::RW,
10879        >::from_register(self, 0)
10880    }
10881
10882    #[doc = "Pull-up Control"]
10883    #[inline(always)]
10884    pub fn pcr(
10885        self,
10886    ) -> crate::common::RegisterField<
10887        4,
10888        0x1,
10889        1,
10890        0,
10891        p300pfs_ha::Pcr,
10892        p300pfs_ha::Pcr,
10893        P300PfsHa_SPEC,
10894        crate::common::RW,
10895    > {
10896        crate::common::RegisterField::<
10897            4,
10898            0x1,
10899            1,
10900            0,
10901            p300pfs_ha::Pcr,
10902            p300pfs_ha::Pcr,
10903            P300PfsHa_SPEC,
10904            crate::common::RW,
10905        >::from_register(self, 0)
10906    }
10907
10908    #[doc = "N-Channel Open-Drain Control"]
10909    #[inline(always)]
10910    pub fn ncodr(
10911        self,
10912    ) -> crate::common::RegisterField<
10913        6,
10914        0x1,
10915        1,
10916        0,
10917        p300pfs_ha::Ncodr,
10918        p300pfs_ha::Ncodr,
10919        P300PfsHa_SPEC,
10920        crate::common::RW,
10921    > {
10922        crate::common::RegisterField::<
10923            6,
10924            0x1,
10925            1,
10926            0,
10927            p300pfs_ha::Ncodr,
10928            p300pfs_ha::Ncodr,
10929            P300PfsHa_SPEC,
10930            crate::common::RW,
10931        >::from_register(self, 0)
10932    }
10933
10934    #[doc = "Port Drive Capability"]
10935    #[inline(always)]
10936    pub fn dscr(
10937        self,
10938    ) -> crate::common::RegisterField<
10939        10,
10940        0x3,
10941        1,
10942        0,
10943        p300pfs_ha::Dscr,
10944        p300pfs_ha::Dscr,
10945        P300PfsHa_SPEC,
10946        crate::common::RW,
10947    > {
10948        crate::common::RegisterField::<
10949            10,
10950            0x3,
10951            1,
10952            0,
10953            p300pfs_ha::Dscr,
10954            p300pfs_ha::Dscr,
10955            P300PfsHa_SPEC,
10956            crate::common::RW,
10957        >::from_register(self, 0)
10958    }
10959
10960    #[doc = "Event on Falling/Event on Rising"]
10961    #[inline(always)]
10962    pub fn eofr(
10963        self,
10964    ) -> crate::common::RegisterField<
10965        12,
10966        0x3,
10967        1,
10968        0,
10969        p300pfs_ha::Eofr,
10970        p300pfs_ha::Eofr,
10971        P300PfsHa_SPEC,
10972        crate::common::RW,
10973    > {
10974        crate::common::RegisterField::<
10975            12,
10976            0x3,
10977            1,
10978            0,
10979            p300pfs_ha::Eofr,
10980            p300pfs_ha::Eofr,
10981            P300PfsHa_SPEC,
10982            crate::common::RW,
10983        >::from_register(self, 0)
10984    }
10985
10986    #[doc = "IRQ Input Enable"]
10987    #[inline(always)]
10988    pub fn isel(
10989        self,
10990    ) -> crate::common::RegisterField<
10991        14,
10992        0x1,
10993        1,
10994        0,
10995        p300pfs_ha::Isel,
10996        p300pfs_ha::Isel,
10997        P300PfsHa_SPEC,
10998        crate::common::RW,
10999    > {
11000        crate::common::RegisterField::<
11001            14,
11002            0x1,
11003            1,
11004            0,
11005            p300pfs_ha::Isel,
11006            p300pfs_ha::Isel,
11007            P300PfsHa_SPEC,
11008            crate::common::RW,
11009        >::from_register(self, 0)
11010    }
11011
11012    #[doc = "Analog Input Enable"]
11013    #[inline(always)]
11014    pub fn asel(
11015        self,
11016    ) -> crate::common::RegisterField<
11017        15,
11018        0x1,
11019        1,
11020        0,
11021        p300pfs_ha::Asel,
11022        p300pfs_ha::Asel,
11023        P300PfsHa_SPEC,
11024        crate::common::RW,
11025    > {
11026        crate::common::RegisterField::<
11027            15,
11028            0x1,
11029            1,
11030            0,
11031            p300pfs_ha::Asel,
11032            p300pfs_ha::Asel,
11033            P300PfsHa_SPEC,
11034            crate::common::RW,
11035        >::from_register(self, 0)
11036    }
11037}
11038impl ::core::default::Default for P300PfsHa {
11039    #[inline(always)]
11040    fn default() -> P300PfsHa {
11041        <crate::RegValueT<P300PfsHa_SPEC> as RegisterValue<_>>::new(16)
11042    }
11043}
11044pub mod p300pfs_ha {
11045
11046    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11047    pub struct Podr_SPEC;
11048    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11049    impl Podr {
11050        #[doc = "Output low"]
11051        pub const _0: Self = Self::new(0);
11052
11053        #[doc = "Output high"]
11054        pub const _1: Self = Self::new(1);
11055    }
11056    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11057    pub struct Pidr_SPEC;
11058    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11059    impl Pidr {
11060        #[doc = "Low level"]
11061        pub const _0: Self = Self::new(0);
11062
11063        #[doc = "High level"]
11064        pub const _1: Self = Self::new(1);
11065    }
11066    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11067    pub struct Pdr_SPEC;
11068    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11069    impl Pdr {
11070        #[doc = "Input (functions as an input pin)"]
11071        pub const _0: Self = Self::new(0);
11072
11073        #[doc = "Output (functions as an output pin)"]
11074        pub const _1: Self = Self::new(1);
11075    }
11076    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11077    pub struct Pcr_SPEC;
11078    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11079    impl Pcr {
11080        #[doc = "Disable input pull-up"]
11081        pub const _0: Self = Self::new(0);
11082
11083        #[doc = "Enable input pull-up"]
11084        pub const _1: Self = Self::new(1);
11085    }
11086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11087    pub struct Ncodr_SPEC;
11088    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11089    impl Ncodr {
11090        #[doc = "Output CMOS"]
11091        pub const _0: Self = Self::new(0);
11092
11093        #[doc = "Output NMOS open-drain"]
11094        pub const _1: Self = Self::new(1);
11095    }
11096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11097    pub struct Dscr_SPEC;
11098    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
11099    impl Dscr {
11100        #[doc = "Low drive"]
11101        pub const _00: Self = Self::new(0);
11102
11103        #[doc = "Middle drive"]
11104        pub const _01: Self = Self::new(1);
11105
11106        #[doc = "Setting prohibited"]
11107        pub const _10: Self = Self::new(2);
11108
11109        #[doc = "High drive"]
11110        pub const _11: Self = Self::new(3);
11111    }
11112    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11113    pub struct Eofr_SPEC;
11114    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
11115    impl Eofr {
11116        #[doc = "Don\'t care"]
11117        pub const _00: Self = Self::new(0);
11118
11119        #[doc = "Detect rising edge"]
11120        pub const _01: Self = Self::new(1);
11121
11122        #[doc = "Detect falling edge"]
11123        pub const _10: Self = Self::new(2);
11124
11125        #[doc = "Detect both edges"]
11126        pub const _11: Self = Self::new(3);
11127    }
11128    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11129    pub struct Isel_SPEC;
11130    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
11131    impl Isel {
11132        #[doc = "Do not use as IRQn input pin"]
11133        pub const _0: Self = Self::new(0);
11134
11135        #[doc = "Use as IRQn input pin"]
11136        pub const _1: Self = Self::new(1);
11137    }
11138    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11139    pub struct Asel_SPEC;
11140    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
11141    impl Asel {
11142        #[doc = "Do not use as analog pin"]
11143        pub const _0: Self = Self::new(0);
11144
11145        #[doc = "Use as analog pin"]
11146        pub const _1: Self = Self::new(1);
11147    }
11148}
11149#[doc(hidden)]
11150#[derive(Copy, Clone, Eq, PartialEq)]
11151pub struct P300PfsBy_SPEC;
11152impl crate::sealed::RegSpec for P300PfsBy_SPEC {
11153    type DataType = u8;
11154}
11155
11156#[doc = "Port 300 Pin Function Select Register"]
11157pub type P300PfsBy = crate::RegValueT<P300PfsBy_SPEC>;
11158
11159impl P300PfsBy {
11160    #[doc = "Port Output Data"]
11161    #[inline(always)]
11162    pub fn podr(
11163        self,
11164    ) -> crate::common::RegisterField<
11165        0,
11166        0x1,
11167        1,
11168        0,
11169        p300pfs_by::Podr,
11170        p300pfs_by::Podr,
11171        P300PfsBy_SPEC,
11172        crate::common::RW,
11173    > {
11174        crate::common::RegisterField::<
11175            0,
11176            0x1,
11177            1,
11178            0,
11179            p300pfs_by::Podr,
11180            p300pfs_by::Podr,
11181            P300PfsBy_SPEC,
11182            crate::common::RW,
11183        >::from_register(self, 0)
11184    }
11185
11186    #[doc = "Port State"]
11187    #[inline(always)]
11188    pub fn pidr(
11189        self,
11190    ) -> crate::common::RegisterField<
11191        1,
11192        0x1,
11193        1,
11194        0,
11195        p300pfs_by::Pidr,
11196        p300pfs_by::Pidr,
11197        P300PfsBy_SPEC,
11198        crate::common::R,
11199    > {
11200        crate::common::RegisterField::<
11201            1,
11202            0x1,
11203            1,
11204            0,
11205            p300pfs_by::Pidr,
11206            p300pfs_by::Pidr,
11207            P300PfsBy_SPEC,
11208            crate::common::R,
11209        >::from_register(self, 0)
11210    }
11211
11212    #[doc = "Port Direction"]
11213    #[inline(always)]
11214    pub fn pdr(
11215        self,
11216    ) -> crate::common::RegisterField<
11217        2,
11218        0x1,
11219        1,
11220        0,
11221        p300pfs_by::Pdr,
11222        p300pfs_by::Pdr,
11223        P300PfsBy_SPEC,
11224        crate::common::RW,
11225    > {
11226        crate::common::RegisterField::<
11227            2,
11228            0x1,
11229            1,
11230            0,
11231            p300pfs_by::Pdr,
11232            p300pfs_by::Pdr,
11233            P300PfsBy_SPEC,
11234            crate::common::RW,
11235        >::from_register(self, 0)
11236    }
11237
11238    #[doc = "Pull-up Control"]
11239    #[inline(always)]
11240    pub fn pcr(
11241        self,
11242    ) -> crate::common::RegisterField<
11243        4,
11244        0x1,
11245        1,
11246        0,
11247        p300pfs_by::Pcr,
11248        p300pfs_by::Pcr,
11249        P300PfsBy_SPEC,
11250        crate::common::RW,
11251    > {
11252        crate::common::RegisterField::<
11253            4,
11254            0x1,
11255            1,
11256            0,
11257            p300pfs_by::Pcr,
11258            p300pfs_by::Pcr,
11259            P300PfsBy_SPEC,
11260            crate::common::RW,
11261        >::from_register(self, 0)
11262    }
11263
11264    #[doc = "N-Channel Open-Drain Control"]
11265    #[inline(always)]
11266    pub fn ncodr(
11267        self,
11268    ) -> crate::common::RegisterField<
11269        6,
11270        0x1,
11271        1,
11272        0,
11273        p300pfs_by::Ncodr,
11274        p300pfs_by::Ncodr,
11275        P300PfsBy_SPEC,
11276        crate::common::RW,
11277    > {
11278        crate::common::RegisterField::<
11279            6,
11280            0x1,
11281            1,
11282            0,
11283            p300pfs_by::Ncodr,
11284            p300pfs_by::Ncodr,
11285            P300PfsBy_SPEC,
11286            crate::common::RW,
11287        >::from_register(self, 0)
11288    }
11289}
11290impl ::core::default::Default for P300PfsBy {
11291    #[inline(always)]
11292    fn default() -> P300PfsBy {
11293        <crate::RegValueT<P300PfsBy_SPEC> as RegisterValue<_>>::new(16)
11294    }
11295}
11296pub mod p300pfs_by {
11297
11298    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11299    pub struct Podr_SPEC;
11300    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11301    impl Podr {
11302        #[doc = "Output low"]
11303        pub const _0: Self = Self::new(0);
11304
11305        #[doc = "Output high"]
11306        pub const _1: Self = Self::new(1);
11307    }
11308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11309    pub struct Pidr_SPEC;
11310    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11311    impl Pidr {
11312        #[doc = "Low level"]
11313        pub const _0: Self = Self::new(0);
11314
11315        #[doc = "High level"]
11316        pub const _1: Self = Self::new(1);
11317    }
11318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11319    pub struct Pdr_SPEC;
11320    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11321    impl Pdr {
11322        #[doc = "Input (functions as an input pin)"]
11323        pub const _0: Self = Self::new(0);
11324
11325        #[doc = "Output (functions as an output pin)"]
11326        pub const _1: Self = Self::new(1);
11327    }
11328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11329    pub struct Pcr_SPEC;
11330    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11331    impl Pcr {
11332        #[doc = "Disable input pull-up"]
11333        pub const _0: Self = Self::new(0);
11334
11335        #[doc = "Enable input pull-up"]
11336        pub const _1: Self = Self::new(1);
11337    }
11338    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11339    pub struct Ncodr_SPEC;
11340    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11341    impl Ncodr {
11342        #[doc = "Output CMOS"]
11343        pub const _0: Self = Self::new(0);
11344
11345        #[doc = "Output NMOS open-drain"]
11346        pub const _1: Self = Self::new(1);
11347    }
11348}
11349#[doc(hidden)]
11350#[derive(Copy, Clone, Eq, PartialEq)]
11351pub struct P30Pfs_SPEC;
11352impl crate::sealed::RegSpec for P30Pfs_SPEC {
11353    type DataType = u32;
11354}
11355
11356#[doc = "Port 30%s Pin Function Select Register"]
11357pub type P30Pfs = crate::RegValueT<P30Pfs_SPEC>;
11358
11359impl P30Pfs {
11360    #[doc = "Port Output Data"]
11361    #[inline(always)]
11362    pub fn podr(
11363        self,
11364    ) -> crate::common::RegisterField<
11365        0,
11366        0x1,
11367        1,
11368        0,
11369        p30pfs::Podr,
11370        p30pfs::Podr,
11371        P30Pfs_SPEC,
11372        crate::common::RW,
11373    > {
11374        crate::common::RegisterField::<
11375            0,
11376            0x1,
11377            1,
11378            0,
11379            p30pfs::Podr,
11380            p30pfs::Podr,
11381            P30Pfs_SPEC,
11382            crate::common::RW,
11383        >::from_register(self, 0)
11384    }
11385
11386    #[doc = "Port State"]
11387    #[inline(always)]
11388    pub fn pidr(
11389        self,
11390    ) -> crate::common::RegisterField<
11391        1,
11392        0x1,
11393        1,
11394        0,
11395        p30pfs::Pidr,
11396        p30pfs::Pidr,
11397        P30Pfs_SPEC,
11398        crate::common::R,
11399    > {
11400        crate::common::RegisterField::<
11401            1,
11402            0x1,
11403            1,
11404            0,
11405            p30pfs::Pidr,
11406            p30pfs::Pidr,
11407            P30Pfs_SPEC,
11408            crate::common::R,
11409        >::from_register(self, 0)
11410    }
11411
11412    #[doc = "Port Direction"]
11413    #[inline(always)]
11414    pub fn pdr(
11415        self,
11416    ) -> crate::common::RegisterField<
11417        2,
11418        0x1,
11419        1,
11420        0,
11421        p30pfs::Pdr,
11422        p30pfs::Pdr,
11423        P30Pfs_SPEC,
11424        crate::common::RW,
11425    > {
11426        crate::common::RegisterField::<
11427            2,
11428            0x1,
11429            1,
11430            0,
11431            p30pfs::Pdr,
11432            p30pfs::Pdr,
11433            P30Pfs_SPEC,
11434            crate::common::RW,
11435        >::from_register(self, 0)
11436    }
11437
11438    #[doc = "Pull-up Control"]
11439    #[inline(always)]
11440    pub fn pcr(
11441        self,
11442    ) -> crate::common::RegisterField<
11443        4,
11444        0x1,
11445        1,
11446        0,
11447        p30pfs::Pcr,
11448        p30pfs::Pcr,
11449        P30Pfs_SPEC,
11450        crate::common::RW,
11451    > {
11452        crate::common::RegisterField::<
11453            4,
11454            0x1,
11455            1,
11456            0,
11457            p30pfs::Pcr,
11458            p30pfs::Pcr,
11459            P30Pfs_SPEC,
11460            crate::common::RW,
11461        >::from_register(self, 0)
11462    }
11463
11464    #[doc = "N-Channel Open-Drain Control"]
11465    #[inline(always)]
11466    pub fn ncodr(
11467        self,
11468    ) -> crate::common::RegisterField<
11469        6,
11470        0x1,
11471        1,
11472        0,
11473        p30pfs::Ncodr,
11474        p30pfs::Ncodr,
11475        P30Pfs_SPEC,
11476        crate::common::RW,
11477    > {
11478        crate::common::RegisterField::<
11479            6,
11480            0x1,
11481            1,
11482            0,
11483            p30pfs::Ncodr,
11484            p30pfs::Ncodr,
11485            P30Pfs_SPEC,
11486            crate::common::RW,
11487        >::from_register(self, 0)
11488    }
11489
11490    #[doc = "Port Drive Capability"]
11491    #[inline(always)]
11492    pub fn dscr(
11493        self,
11494    ) -> crate::common::RegisterField<
11495        10,
11496        0x3,
11497        1,
11498        0,
11499        p30pfs::Dscr,
11500        p30pfs::Dscr,
11501        P30Pfs_SPEC,
11502        crate::common::RW,
11503    > {
11504        crate::common::RegisterField::<
11505            10,
11506            0x3,
11507            1,
11508            0,
11509            p30pfs::Dscr,
11510            p30pfs::Dscr,
11511            P30Pfs_SPEC,
11512            crate::common::RW,
11513        >::from_register(self, 0)
11514    }
11515
11516    #[doc = "Event on Falling/Event on Rising"]
11517    #[inline(always)]
11518    pub fn eofr(
11519        self,
11520    ) -> crate::common::RegisterField<
11521        12,
11522        0x3,
11523        1,
11524        0,
11525        p30pfs::Eofr,
11526        p30pfs::Eofr,
11527        P30Pfs_SPEC,
11528        crate::common::RW,
11529    > {
11530        crate::common::RegisterField::<
11531            12,
11532            0x3,
11533            1,
11534            0,
11535            p30pfs::Eofr,
11536            p30pfs::Eofr,
11537            P30Pfs_SPEC,
11538            crate::common::RW,
11539        >::from_register(self, 0)
11540    }
11541
11542    #[doc = "IRQ Input Enable"]
11543    #[inline(always)]
11544    pub fn isel(
11545        self,
11546    ) -> crate::common::RegisterField<
11547        14,
11548        0x1,
11549        1,
11550        0,
11551        p30pfs::Isel,
11552        p30pfs::Isel,
11553        P30Pfs_SPEC,
11554        crate::common::RW,
11555    > {
11556        crate::common::RegisterField::<
11557            14,
11558            0x1,
11559            1,
11560            0,
11561            p30pfs::Isel,
11562            p30pfs::Isel,
11563            P30Pfs_SPEC,
11564            crate::common::RW,
11565        >::from_register(self, 0)
11566    }
11567
11568    #[doc = "Analog Input Enable"]
11569    #[inline(always)]
11570    pub fn asel(
11571        self,
11572    ) -> crate::common::RegisterField<
11573        15,
11574        0x1,
11575        1,
11576        0,
11577        p30pfs::Asel,
11578        p30pfs::Asel,
11579        P30Pfs_SPEC,
11580        crate::common::RW,
11581    > {
11582        crate::common::RegisterField::<
11583            15,
11584            0x1,
11585            1,
11586            0,
11587            p30pfs::Asel,
11588            p30pfs::Asel,
11589            P30Pfs_SPEC,
11590            crate::common::RW,
11591        >::from_register(self, 0)
11592    }
11593
11594    #[doc = "Port Mode Control"]
11595    #[inline(always)]
11596    pub fn pmr(
11597        self,
11598    ) -> crate::common::RegisterField<
11599        16,
11600        0x1,
11601        1,
11602        0,
11603        p30pfs::Pmr,
11604        p30pfs::Pmr,
11605        P30Pfs_SPEC,
11606        crate::common::RW,
11607    > {
11608        crate::common::RegisterField::<
11609            16,
11610            0x1,
11611            1,
11612            0,
11613            p30pfs::Pmr,
11614            p30pfs::Pmr,
11615            P30Pfs_SPEC,
11616            crate::common::RW,
11617        >::from_register(self, 0)
11618    }
11619
11620    #[doc = "Peripheral Select"]
11621    #[inline(always)]
11622    pub fn psel(
11623        self,
11624    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P30Pfs_SPEC, crate::common::RW> {
11625        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P30Pfs_SPEC,crate::common::RW>::from_register(self,0)
11626    }
11627}
11628impl ::core::default::Default for P30Pfs {
11629    #[inline(always)]
11630    fn default() -> P30Pfs {
11631        <crate::RegValueT<P30Pfs_SPEC> as RegisterValue<_>>::new(0)
11632    }
11633}
11634pub mod p30pfs {
11635
11636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11637    pub struct Podr_SPEC;
11638    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
11639    impl Podr {
11640        #[doc = "Output low"]
11641        pub const _0: Self = Self::new(0);
11642
11643        #[doc = "Output high"]
11644        pub const _1: Self = Self::new(1);
11645    }
11646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11647    pub struct Pidr_SPEC;
11648    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
11649    impl Pidr {
11650        #[doc = "Low level"]
11651        pub const _0: Self = Self::new(0);
11652
11653        #[doc = "High level"]
11654        pub const _1: Self = Self::new(1);
11655    }
11656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11657    pub struct Pdr_SPEC;
11658    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
11659    impl Pdr {
11660        #[doc = "Input (functions as an input pin)"]
11661        pub const _0: Self = Self::new(0);
11662
11663        #[doc = "Output (functions as an output pin)"]
11664        pub const _1: Self = Self::new(1);
11665    }
11666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11667    pub struct Pcr_SPEC;
11668    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
11669    impl Pcr {
11670        #[doc = "Disable input pull-up"]
11671        pub const _0: Self = Self::new(0);
11672
11673        #[doc = "Enable input pull-up"]
11674        pub const _1: Self = Self::new(1);
11675    }
11676    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11677    pub struct Ncodr_SPEC;
11678    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
11679    impl Ncodr {
11680        #[doc = "Output CMOS"]
11681        pub const _0: Self = Self::new(0);
11682
11683        #[doc = "Output NMOS open-drain"]
11684        pub const _1: Self = Self::new(1);
11685    }
11686    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11687    pub struct Dscr_SPEC;
11688    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
11689    impl Dscr {
11690        #[doc = "Low drive"]
11691        pub const _00: Self = Self::new(0);
11692
11693        #[doc = "Middle drive"]
11694        pub const _01: Self = Self::new(1);
11695
11696        #[doc = "Setting prohibited"]
11697        pub const _10: Self = Self::new(2);
11698
11699        #[doc = "High drive"]
11700        pub const _11: Self = Self::new(3);
11701    }
11702    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11703    pub struct Eofr_SPEC;
11704    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
11705    impl Eofr {
11706        #[doc = "Don\'t care"]
11707        pub const _00: Self = Self::new(0);
11708
11709        #[doc = "Detect rising edge"]
11710        pub const _01: Self = Self::new(1);
11711
11712        #[doc = "Detect falling edge"]
11713        pub const _10: Self = Self::new(2);
11714
11715        #[doc = "Detect both edges"]
11716        pub const _11: Self = Self::new(3);
11717    }
11718    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11719    pub struct Isel_SPEC;
11720    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
11721    impl Isel {
11722        #[doc = "Do not use as IRQn input pin"]
11723        pub const _0: Self = Self::new(0);
11724
11725        #[doc = "Use as IRQn input pin"]
11726        pub const _1: Self = Self::new(1);
11727    }
11728    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11729    pub struct Asel_SPEC;
11730    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
11731    impl Asel {
11732        #[doc = "Do not use as analog pin"]
11733        pub const _0: Self = Self::new(0);
11734
11735        #[doc = "Use as analog pin"]
11736        pub const _1: Self = Self::new(1);
11737    }
11738    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
11739    pub struct Pmr_SPEC;
11740    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
11741    impl Pmr {
11742        #[doc = "Use as general I/O pin"]
11743        pub const _0: Self = Self::new(0);
11744
11745        #[doc = "Use as I/O port for peripheral functions"]
11746        pub const _1: Self = Self::new(1);
11747    }
11748}
11749#[doc(hidden)]
11750#[derive(Copy, Clone, Eq, PartialEq)]
11751pub struct P30PfsHa_SPEC;
11752impl crate::sealed::RegSpec for P30PfsHa_SPEC {
11753    type DataType = u16;
11754}
11755
11756#[doc = "Port 30%s Pin Function Select Register"]
11757pub type P30PfsHa = crate::RegValueT<P30PfsHa_SPEC>;
11758
11759impl P30PfsHa {
11760    #[doc = "Port Output Data"]
11761    #[inline(always)]
11762    pub fn podr(
11763        self,
11764    ) -> crate::common::RegisterField<
11765        0,
11766        0x1,
11767        1,
11768        0,
11769        p30pfs_ha::Podr,
11770        p30pfs_ha::Podr,
11771        P30PfsHa_SPEC,
11772        crate::common::RW,
11773    > {
11774        crate::common::RegisterField::<
11775            0,
11776            0x1,
11777            1,
11778            0,
11779            p30pfs_ha::Podr,
11780            p30pfs_ha::Podr,
11781            P30PfsHa_SPEC,
11782            crate::common::RW,
11783        >::from_register(self, 0)
11784    }
11785
11786    #[doc = "Port State"]
11787    #[inline(always)]
11788    pub fn pidr(
11789        self,
11790    ) -> crate::common::RegisterField<
11791        1,
11792        0x1,
11793        1,
11794        0,
11795        p30pfs_ha::Pidr,
11796        p30pfs_ha::Pidr,
11797        P30PfsHa_SPEC,
11798        crate::common::R,
11799    > {
11800        crate::common::RegisterField::<
11801            1,
11802            0x1,
11803            1,
11804            0,
11805            p30pfs_ha::Pidr,
11806            p30pfs_ha::Pidr,
11807            P30PfsHa_SPEC,
11808            crate::common::R,
11809        >::from_register(self, 0)
11810    }
11811
11812    #[doc = "Port Direction"]
11813    #[inline(always)]
11814    pub fn pdr(
11815        self,
11816    ) -> crate::common::RegisterField<
11817        2,
11818        0x1,
11819        1,
11820        0,
11821        p30pfs_ha::Pdr,
11822        p30pfs_ha::Pdr,
11823        P30PfsHa_SPEC,
11824        crate::common::RW,
11825    > {
11826        crate::common::RegisterField::<
11827            2,
11828            0x1,
11829            1,
11830            0,
11831            p30pfs_ha::Pdr,
11832            p30pfs_ha::Pdr,
11833            P30PfsHa_SPEC,
11834            crate::common::RW,
11835        >::from_register(self, 0)
11836    }
11837
11838    #[doc = "Pull-up Control"]
11839    #[inline(always)]
11840    pub fn pcr(
11841        self,
11842    ) -> crate::common::RegisterField<
11843        4,
11844        0x1,
11845        1,
11846        0,
11847        p30pfs_ha::Pcr,
11848        p30pfs_ha::Pcr,
11849        P30PfsHa_SPEC,
11850        crate::common::RW,
11851    > {
11852        crate::common::RegisterField::<
11853            4,
11854            0x1,
11855            1,
11856            0,
11857            p30pfs_ha::Pcr,
11858            p30pfs_ha::Pcr,
11859            P30PfsHa_SPEC,
11860            crate::common::RW,
11861        >::from_register(self, 0)
11862    }
11863
11864    #[doc = "N-Channel Open-Drain Control"]
11865    #[inline(always)]
11866    pub fn ncodr(
11867        self,
11868    ) -> crate::common::RegisterField<
11869        6,
11870        0x1,
11871        1,
11872        0,
11873        p30pfs_ha::Ncodr,
11874        p30pfs_ha::Ncodr,
11875        P30PfsHa_SPEC,
11876        crate::common::RW,
11877    > {
11878        crate::common::RegisterField::<
11879            6,
11880            0x1,
11881            1,
11882            0,
11883            p30pfs_ha::Ncodr,
11884            p30pfs_ha::Ncodr,
11885            P30PfsHa_SPEC,
11886            crate::common::RW,
11887        >::from_register(self, 0)
11888    }
11889
11890    #[doc = "Port Drive Capability"]
11891    #[inline(always)]
11892    pub fn dscr(
11893        self,
11894    ) -> crate::common::RegisterField<
11895        10,
11896        0x3,
11897        1,
11898        0,
11899        p30pfs_ha::Dscr,
11900        p30pfs_ha::Dscr,
11901        P30PfsHa_SPEC,
11902        crate::common::RW,
11903    > {
11904        crate::common::RegisterField::<
11905            10,
11906            0x3,
11907            1,
11908            0,
11909            p30pfs_ha::Dscr,
11910            p30pfs_ha::Dscr,
11911            P30PfsHa_SPEC,
11912            crate::common::RW,
11913        >::from_register(self, 0)
11914    }
11915
11916    #[doc = "Event on Falling/Event on Rising"]
11917    #[inline(always)]
11918    pub fn eofr(
11919        self,
11920    ) -> crate::common::RegisterField<
11921        12,
11922        0x3,
11923        1,
11924        0,
11925        p30pfs_ha::Eofr,
11926        p30pfs_ha::Eofr,
11927        P30PfsHa_SPEC,
11928        crate::common::RW,
11929    > {
11930        crate::common::RegisterField::<
11931            12,
11932            0x3,
11933            1,
11934            0,
11935            p30pfs_ha::Eofr,
11936            p30pfs_ha::Eofr,
11937            P30PfsHa_SPEC,
11938            crate::common::RW,
11939        >::from_register(self, 0)
11940    }
11941
11942    #[doc = "IRQ Input Enable"]
11943    #[inline(always)]
11944    pub fn isel(
11945        self,
11946    ) -> crate::common::RegisterField<
11947        14,
11948        0x1,
11949        1,
11950        0,
11951        p30pfs_ha::Isel,
11952        p30pfs_ha::Isel,
11953        P30PfsHa_SPEC,
11954        crate::common::RW,
11955    > {
11956        crate::common::RegisterField::<
11957            14,
11958            0x1,
11959            1,
11960            0,
11961            p30pfs_ha::Isel,
11962            p30pfs_ha::Isel,
11963            P30PfsHa_SPEC,
11964            crate::common::RW,
11965        >::from_register(self, 0)
11966    }
11967
11968    #[doc = "Analog Input Enable"]
11969    #[inline(always)]
11970    pub fn asel(
11971        self,
11972    ) -> crate::common::RegisterField<
11973        15,
11974        0x1,
11975        1,
11976        0,
11977        p30pfs_ha::Asel,
11978        p30pfs_ha::Asel,
11979        P30PfsHa_SPEC,
11980        crate::common::RW,
11981    > {
11982        crate::common::RegisterField::<
11983            15,
11984            0x1,
11985            1,
11986            0,
11987            p30pfs_ha::Asel,
11988            p30pfs_ha::Asel,
11989            P30PfsHa_SPEC,
11990            crate::common::RW,
11991        >::from_register(self, 0)
11992    }
11993}
11994impl ::core::default::Default for P30PfsHa {
11995    #[inline(always)]
11996    fn default() -> P30PfsHa {
11997        <crate::RegValueT<P30PfsHa_SPEC> as RegisterValue<_>>::new(0)
11998    }
11999}
12000pub mod p30pfs_ha {
12001
12002    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12003    pub struct Podr_SPEC;
12004    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12005    impl Podr {
12006        #[doc = "Output low"]
12007        pub const _0: Self = Self::new(0);
12008
12009        #[doc = "Output high"]
12010        pub const _1: Self = Self::new(1);
12011    }
12012    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12013    pub struct Pidr_SPEC;
12014    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12015    impl Pidr {
12016        #[doc = "Low level"]
12017        pub const _0: Self = Self::new(0);
12018
12019        #[doc = "High level"]
12020        pub const _1: Self = Self::new(1);
12021    }
12022    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12023    pub struct Pdr_SPEC;
12024    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12025    impl Pdr {
12026        #[doc = "Input (functions as an input pin)"]
12027        pub const _0: Self = Self::new(0);
12028
12029        #[doc = "Output (functions as an output pin)"]
12030        pub const _1: Self = Self::new(1);
12031    }
12032    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12033    pub struct Pcr_SPEC;
12034    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12035    impl Pcr {
12036        #[doc = "Disable input pull-up"]
12037        pub const _0: Self = Self::new(0);
12038
12039        #[doc = "Enable input pull-up"]
12040        pub const _1: Self = Self::new(1);
12041    }
12042    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12043    pub struct Ncodr_SPEC;
12044    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12045    impl Ncodr {
12046        #[doc = "Output CMOS"]
12047        pub const _0: Self = Self::new(0);
12048
12049        #[doc = "Output NMOS open-drain"]
12050        pub const _1: Self = Self::new(1);
12051    }
12052    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12053    pub struct Dscr_SPEC;
12054    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
12055    impl Dscr {
12056        #[doc = "Low drive"]
12057        pub const _00: Self = Self::new(0);
12058
12059        #[doc = "Middle drive"]
12060        pub const _01: Self = Self::new(1);
12061
12062        #[doc = "Setting prohibited"]
12063        pub const _10: Self = Self::new(2);
12064
12065        #[doc = "High drive"]
12066        pub const _11: Self = Self::new(3);
12067    }
12068    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12069    pub struct Eofr_SPEC;
12070    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
12071    impl Eofr {
12072        #[doc = "Don\'t care"]
12073        pub const _00: Self = Self::new(0);
12074
12075        #[doc = "Detect rising edge"]
12076        pub const _01: Self = Self::new(1);
12077
12078        #[doc = "Detect falling edge"]
12079        pub const _10: Self = Self::new(2);
12080
12081        #[doc = "Detect both edges"]
12082        pub const _11: Self = Self::new(3);
12083    }
12084    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12085    pub struct Isel_SPEC;
12086    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
12087    impl Isel {
12088        #[doc = "Do not use as IRQn input pin"]
12089        pub const _0: Self = Self::new(0);
12090
12091        #[doc = "Use as IRQn input pin"]
12092        pub const _1: Self = Self::new(1);
12093    }
12094    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12095    pub struct Asel_SPEC;
12096    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
12097    impl Asel {
12098        #[doc = "Do not use as analog pin"]
12099        pub const _0: Self = Self::new(0);
12100
12101        #[doc = "Use as analog pin"]
12102        pub const _1: Self = Self::new(1);
12103    }
12104}
12105#[doc(hidden)]
12106#[derive(Copy, Clone, Eq, PartialEq)]
12107pub struct P30PfsBy_SPEC;
12108impl crate::sealed::RegSpec for P30PfsBy_SPEC {
12109    type DataType = u8;
12110}
12111
12112#[doc = "Port 30%s Pin Function Select Register"]
12113pub type P30PfsBy = crate::RegValueT<P30PfsBy_SPEC>;
12114
12115impl P30PfsBy {
12116    #[doc = "Port Output Data"]
12117    #[inline(always)]
12118    pub fn podr(
12119        self,
12120    ) -> crate::common::RegisterField<
12121        0,
12122        0x1,
12123        1,
12124        0,
12125        p30pfs_by::Podr,
12126        p30pfs_by::Podr,
12127        P30PfsBy_SPEC,
12128        crate::common::RW,
12129    > {
12130        crate::common::RegisterField::<
12131            0,
12132            0x1,
12133            1,
12134            0,
12135            p30pfs_by::Podr,
12136            p30pfs_by::Podr,
12137            P30PfsBy_SPEC,
12138            crate::common::RW,
12139        >::from_register(self, 0)
12140    }
12141
12142    #[doc = "Port State"]
12143    #[inline(always)]
12144    pub fn pidr(
12145        self,
12146    ) -> crate::common::RegisterField<
12147        1,
12148        0x1,
12149        1,
12150        0,
12151        p30pfs_by::Pidr,
12152        p30pfs_by::Pidr,
12153        P30PfsBy_SPEC,
12154        crate::common::R,
12155    > {
12156        crate::common::RegisterField::<
12157            1,
12158            0x1,
12159            1,
12160            0,
12161            p30pfs_by::Pidr,
12162            p30pfs_by::Pidr,
12163            P30PfsBy_SPEC,
12164            crate::common::R,
12165        >::from_register(self, 0)
12166    }
12167
12168    #[doc = "Port Direction"]
12169    #[inline(always)]
12170    pub fn pdr(
12171        self,
12172    ) -> crate::common::RegisterField<
12173        2,
12174        0x1,
12175        1,
12176        0,
12177        p30pfs_by::Pdr,
12178        p30pfs_by::Pdr,
12179        P30PfsBy_SPEC,
12180        crate::common::RW,
12181    > {
12182        crate::common::RegisterField::<
12183            2,
12184            0x1,
12185            1,
12186            0,
12187            p30pfs_by::Pdr,
12188            p30pfs_by::Pdr,
12189            P30PfsBy_SPEC,
12190            crate::common::RW,
12191        >::from_register(self, 0)
12192    }
12193
12194    #[doc = "Pull-up Control"]
12195    #[inline(always)]
12196    pub fn pcr(
12197        self,
12198    ) -> crate::common::RegisterField<
12199        4,
12200        0x1,
12201        1,
12202        0,
12203        p30pfs_by::Pcr,
12204        p30pfs_by::Pcr,
12205        P30PfsBy_SPEC,
12206        crate::common::RW,
12207    > {
12208        crate::common::RegisterField::<
12209            4,
12210            0x1,
12211            1,
12212            0,
12213            p30pfs_by::Pcr,
12214            p30pfs_by::Pcr,
12215            P30PfsBy_SPEC,
12216            crate::common::RW,
12217        >::from_register(self, 0)
12218    }
12219
12220    #[doc = "N-Channel Open-Drain Control"]
12221    #[inline(always)]
12222    pub fn ncodr(
12223        self,
12224    ) -> crate::common::RegisterField<
12225        6,
12226        0x1,
12227        1,
12228        0,
12229        p30pfs_by::Ncodr,
12230        p30pfs_by::Ncodr,
12231        P30PfsBy_SPEC,
12232        crate::common::RW,
12233    > {
12234        crate::common::RegisterField::<
12235            6,
12236            0x1,
12237            1,
12238            0,
12239            p30pfs_by::Ncodr,
12240            p30pfs_by::Ncodr,
12241            P30PfsBy_SPEC,
12242            crate::common::RW,
12243        >::from_register(self, 0)
12244    }
12245}
12246impl ::core::default::Default for P30PfsBy {
12247    #[inline(always)]
12248    fn default() -> P30PfsBy {
12249        <crate::RegValueT<P30PfsBy_SPEC> as RegisterValue<_>>::new(0)
12250    }
12251}
12252pub mod p30pfs_by {
12253
12254    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12255    pub struct Podr_SPEC;
12256    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12257    impl Podr {
12258        #[doc = "Output low"]
12259        pub const _0: Self = Self::new(0);
12260
12261        #[doc = "Output high"]
12262        pub const _1: Self = Self::new(1);
12263    }
12264    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12265    pub struct Pidr_SPEC;
12266    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12267    impl Pidr {
12268        #[doc = "Low level"]
12269        pub const _0: Self = Self::new(0);
12270
12271        #[doc = "High level"]
12272        pub const _1: Self = Self::new(1);
12273    }
12274    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12275    pub struct Pdr_SPEC;
12276    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12277    impl Pdr {
12278        #[doc = "Input (functions as an input pin)"]
12279        pub const _0: Self = Self::new(0);
12280
12281        #[doc = "Output (functions as an output pin)"]
12282        pub const _1: Self = Self::new(1);
12283    }
12284    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12285    pub struct Pcr_SPEC;
12286    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12287    impl Pcr {
12288        #[doc = "Disable input pull-up"]
12289        pub const _0: Self = Self::new(0);
12290
12291        #[doc = "Enable input pull-up"]
12292        pub const _1: Self = Self::new(1);
12293    }
12294    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12295    pub struct Ncodr_SPEC;
12296    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12297    impl Ncodr {
12298        #[doc = "Output CMOS"]
12299        pub const _0: Self = Self::new(0);
12300
12301        #[doc = "Output NMOS open-drain"]
12302        pub const _1: Self = Self::new(1);
12303    }
12304}
12305#[doc(hidden)]
12306#[derive(Copy, Clone, Eq, PartialEq)]
12307pub struct P40Pfs_SPEC;
12308impl crate::sealed::RegSpec for P40Pfs_SPEC {
12309    type DataType = u32;
12310}
12311
12312#[doc = "Port 40%s Pin Function Select Register"]
12313pub type P40Pfs = crate::RegValueT<P40Pfs_SPEC>;
12314
12315impl P40Pfs {
12316    #[doc = "Port Output Data"]
12317    #[inline(always)]
12318    pub fn podr(
12319        self,
12320    ) -> crate::common::RegisterField<
12321        0,
12322        0x1,
12323        1,
12324        0,
12325        p40pfs::Podr,
12326        p40pfs::Podr,
12327        P40Pfs_SPEC,
12328        crate::common::RW,
12329    > {
12330        crate::common::RegisterField::<
12331            0,
12332            0x1,
12333            1,
12334            0,
12335            p40pfs::Podr,
12336            p40pfs::Podr,
12337            P40Pfs_SPEC,
12338            crate::common::RW,
12339        >::from_register(self, 0)
12340    }
12341
12342    #[doc = "Port State"]
12343    #[inline(always)]
12344    pub fn pidr(
12345        self,
12346    ) -> crate::common::RegisterField<
12347        1,
12348        0x1,
12349        1,
12350        0,
12351        p40pfs::Pidr,
12352        p40pfs::Pidr,
12353        P40Pfs_SPEC,
12354        crate::common::R,
12355    > {
12356        crate::common::RegisterField::<
12357            1,
12358            0x1,
12359            1,
12360            0,
12361            p40pfs::Pidr,
12362            p40pfs::Pidr,
12363            P40Pfs_SPEC,
12364            crate::common::R,
12365        >::from_register(self, 0)
12366    }
12367
12368    #[doc = "Port Direction"]
12369    #[inline(always)]
12370    pub fn pdr(
12371        self,
12372    ) -> crate::common::RegisterField<
12373        2,
12374        0x1,
12375        1,
12376        0,
12377        p40pfs::Pdr,
12378        p40pfs::Pdr,
12379        P40Pfs_SPEC,
12380        crate::common::RW,
12381    > {
12382        crate::common::RegisterField::<
12383            2,
12384            0x1,
12385            1,
12386            0,
12387            p40pfs::Pdr,
12388            p40pfs::Pdr,
12389            P40Pfs_SPEC,
12390            crate::common::RW,
12391        >::from_register(self, 0)
12392    }
12393
12394    #[doc = "Pull-up Control"]
12395    #[inline(always)]
12396    pub fn pcr(
12397        self,
12398    ) -> crate::common::RegisterField<
12399        4,
12400        0x1,
12401        1,
12402        0,
12403        p40pfs::Pcr,
12404        p40pfs::Pcr,
12405        P40Pfs_SPEC,
12406        crate::common::RW,
12407    > {
12408        crate::common::RegisterField::<
12409            4,
12410            0x1,
12411            1,
12412            0,
12413            p40pfs::Pcr,
12414            p40pfs::Pcr,
12415            P40Pfs_SPEC,
12416            crate::common::RW,
12417        >::from_register(self, 0)
12418    }
12419
12420    #[doc = "N-Channel Open-Drain Control"]
12421    #[inline(always)]
12422    pub fn ncodr(
12423        self,
12424    ) -> crate::common::RegisterField<
12425        6,
12426        0x1,
12427        1,
12428        0,
12429        p40pfs::Ncodr,
12430        p40pfs::Ncodr,
12431        P40Pfs_SPEC,
12432        crate::common::RW,
12433    > {
12434        crate::common::RegisterField::<
12435            6,
12436            0x1,
12437            1,
12438            0,
12439            p40pfs::Ncodr,
12440            p40pfs::Ncodr,
12441            P40Pfs_SPEC,
12442            crate::common::RW,
12443        >::from_register(self, 0)
12444    }
12445
12446    #[doc = "Port Drive Capability"]
12447    #[inline(always)]
12448    pub fn dscr(
12449        self,
12450    ) -> crate::common::RegisterField<
12451        10,
12452        0x3,
12453        1,
12454        0,
12455        p40pfs::Dscr,
12456        p40pfs::Dscr,
12457        P40Pfs_SPEC,
12458        crate::common::RW,
12459    > {
12460        crate::common::RegisterField::<
12461            10,
12462            0x3,
12463            1,
12464            0,
12465            p40pfs::Dscr,
12466            p40pfs::Dscr,
12467            P40Pfs_SPEC,
12468            crate::common::RW,
12469        >::from_register(self, 0)
12470    }
12471
12472    #[doc = "Event on Falling/Event on Rising"]
12473    #[inline(always)]
12474    pub fn eofr(
12475        self,
12476    ) -> crate::common::RegisterField<
12477        12,
12478        0x3,
12479        1,
12480        0,
12481        p40pfs::Eofr,
12482        p40pfs::Eofr,
12483        P40Pfs_SPEC,
12484        crate::common::RW,
12485    > {
12486        crate::common::RegisterField::<
12487            12,
12488            0x3,
12489            1,
12490            0,
12491            p40pfs::Eofr,
12492            p40pfs::Eofr,
12493            P40Pfs_SPEC,
12494            crate::common::RW,
12495        >::from_register(self, 0)
12496    }
12497
12498    #[doc = "IRQ Input Enable"]
12499    #[inline(always)]
12500    pub fn isel(
12501        self,
12502    ) -> crate::common::RegisterField<
12503        14,
12504        0x1,
12505        1,
12506        0,
12507        p40pfs::Isel,
12508        p40pfs::Isel,
12509        P40Pfs_SPEC,
12510        crate::common::RW,
12511    > {
12512        crate::common::RegisterField::<
12513            14,
12514            0x1,
12515            1,
12516            0,
12517            p40pfs::Isel,
12518            p40pfs::Isel,
12519            P40Pfs_SPEC,
12520            crate::common::RW,
12521        >::from_register(self, 0)
12522    }
12523
12524    #[doc = "Analog Input Enable"]
12525    #[inline(always)]
12526    pub fn asel(
12527        self,
12528    ) -> crate::common::RegisterField<
12529        15,
12530        0x1,
12531        1,
12532        0,
12533        p40pfs::Asel,
12534        p40pfs::Asel,
12535        P40Pfs_SPEC,
12536        crate::common::RW,
12537    > {
12538        crate::common::RegisterField::<
12539            15,
12540            0x1,
12541            1,
12542            0,
12543            p40pfs::Asel,
12544            p40pfs::Asel,
12545            P40Pfs_SPEC,
12546            crate::common::RW,
12547        >::from_register(self, 0)
12548    }
12549
12550    #[doc = "Port Mode Control"]
12551    #[inline(always)]
12552    pub fn pmr(
12553        self,
12554    ) -> crate::common::RegisterField<
12555        16,
12556        0x1,
12557        1,
12558        0,
12559        p40pfs::Pmr,
12560        p40pfs::Pmr,
12561        P40Pfs_SPEC,
12562        crate::common::RW,
12563    > {
12564        crate::common::RegisterField::<
12565            16,
12566            0x1,
12567            1,
12568            0,
12569            p40pfs::Pmr,
12570            p40pfs::Pmr,
12571            P40Pfs_SPEC,
12572            crate::common::RW,
12573        >::from_register(self, 0)
12574    }
12575
12576    #[doc = "Peripheral Select"]
12577    #[inline(always)]
12578    pub fn psel(
12579        self,
12580    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P40Pfs_SPEC, crate::common::RW> {
12581        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P40Pfs_SPEC,crate::common::RW>::from_register(self,0)
12582    }
12583}
12584impl ::core::default::Default for P40Pfs {
12585    #[inline(always)]
12586    fn default() -> P40Pfs {
12587        <crate::RegValueT<P40Pfs_SPEC> as RegisterValue<_>>::new(0)
12588    }
12589}
12590pub mod p40pfs {
12591
12592    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12593    pub struct Podr_SPEC;
12594    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12595    impl Podr {
12596        #[doc = "Output low"]
12597        pub const _0: Self = Self::new(0);
12598
12599        #[doc = "Output high"]
12600        pub const _1: Self = Self::new(1);
12601    }
12602    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12603    pub struct Pidr_SPEC;
12604    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12605    impl Pidr {
12606        #[doc = "Low level"]
12607        pub const _0: Self = Self::new(0);
12608
12609        #[doc = "High level"]
12610        pub const _1: Self = Self::new(1);
12611    }
12612    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12613    pub struct Pdr_SPEC;
12614    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12615    impl Pdr {
12616        #[doc = "Input (functions as an input pin)"]
12617        pub const _0: Self = Self::new(0);
12618
12619        #[doc = "Output (functions as an output pin)"]
12620        pub const _1: Self = Self::new(1);
12621    }
12622    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12623    pub struct Pcr_SPEC;
12624    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12625    impl Pcr {
12626        #[doc = "Disable input pull-up"]
12627        pub const _0: Self = Self::new(0);
12628
12629        #[doc = "Enable input pull-up"]
12630        pub const _1: Self = Self::new(1);
12631    }
12632    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12633    pub struct Ncodr_SPEC;
12634    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
12635    impl Ncodr {
12636        #[doc = "Output CMOS"]
12637        pub const _0: Self = Self::new(0);
12638
12639        #[doc = "Output NMOS open-drain"]
12640        pub const _1: Self = Self::new(1);
12641    }
12642    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12643    pub struct Dscr_SPEC;
12644    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
12645    impl Dscr {
12646        #[doc = "Low drive"]
12647        pub const _00: Self = Self::new(0);
12648
12649        #[doc = "Middle drive"]
12650        pub const _01: Self = Self::new(1);
12651
12652        #[doc = "Setting prohibited"]
12653        pub const _10: Self = Self::new(2);
12654
12655        #[doc = "High drive"]
12656        pub const _11: Self = Self::new(3);
12657    }
12658    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12659    pub struct Eofr_SPEC;
12660    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
12661    impl Eofr {
12662        #[doc = "Don\'t care"]
12663        pub const _00: Self = Self::new(0);
12664
12665        #[doc = "Detect rising edge"]
12666        pub const _01: Self = Self::new(1);
12667
12668        #[doc = "Detect falling edge"]
12669        pub const _10: Self = Self::new(2);
12670
12671        #[doc = "Detect both edges"]
12672        pub const _11: Self = Self::new(3);
12673    }
12674    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12675    pub struct Isel_SPEC;
12676    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
12677    impl Isel {
12678        #[doc = "Do not use as IRQn input pin"]
12679        pub const _0: Self = Self::new(0);
12680
12681        #[doc = "Use as IRQn input pin"]
12682        pub const _1: Self = Self::new(1);
12683    }
12684    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12685    pub struct Asel_SPEC;
12686    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
12687    impl Asel {
12688        #[doc = "Do not use as analog pin"]
12689        pub const _0: Self = Self::new(0);
12690
12691        #[doc = "Use as analog pin"]
12692        pub const _1: Self = Self::new(1);
12693    }
12694    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12695    pub struct Pmr_SPEC;
12696    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
12697    impl Pmr {
12698        #[doc = "Use as general I/O pin"]
12699        pub const _0: Self = Self::new(0);
12700
12701        #[doc = "Use as I/O port for peripheral functions"]
12702        pub const _1: Self = Self::new(1);
12703    }
12704}
12705#[doc(hidden)]
12706#[derive(Copy, Clone, Eq, PartialEq)]
12707pub struct P40PfsHa_SPEC;
12708impl crate::sealed::RegSpec for P40PfsHa_SPEC {
12709    type DataType = u16;
12710}
12711
12712#[doc = "Port 40%s Pin Function Select Register"]
12713pub type P40PfsHa = crate::RegValueT<P40PfsHa_SPEC>;
12714
12715impl P40PfsHa {
12716    #[doc = "Port Output Data"]
12717    #[inline(always)]
12718    pub fn podr(
12719        self,
12720    ) -> crate::common::RegisterField<
12721        0,
12722        0x1,
12723        1,
12724        0,
12725        p40pfs_ha::Podr,
12726        p40pfs_ha::Podr,
12727        P40PfsHa_SPEC,
12728        crate::common::RW,
12729    > {
12730        crate::common::RegisterField::<
12731            0,
12732            0x1,
12733            1,
12734            0,
12735            p40pfs_ha::Podr,
12736            p40pfs_ha::Podr,
12737            P40PfsHa_SPEC,
12738            crate::common::RW,
12739        >::from_register(self, 0)
12740    }
12741
12742    #[doc = "Port State"]
12743    #[inline(always)]
12744    pub fn pidr(
12745        self,
12746    ) -> crate::common::RegisterField<
12747        1,
12748        0x1,
12749        1,
12750        0,
12751        p40pfs_ha::Pidr,
12752        p40pfs_ha::Pidr,
12753        P40PfsHa_SPEC,
12754        crate::common::R,
12755    > {
12756        crate::common::RegisterField::<
12757            1,
12758            0x1,
12759            1,
12760            0,
12761            p40pfs_ha::Pidr,
12762            p40pfs_ha::Pidr,
12763            P40PfsHa_SPEC,
12764            crate::common::R,
12765        >::from_register(self, 0)
12766    }
12767
12768    #[doc = "Port Direction"]
12769    #[inline(always)]
12770    pub fn pdr(
12771        self,
12772    ) -> crate::common::RegisterField<
12773        2,
12774        0x1,
12775        1,
12776        0,
12777        p40pfs_ha::Pdr,
12778        p40pfs_ha::Pdr,
12779        P40PfsHa_SPEC,
12780        crate::common::RW,
12781    > {
12782        crate::common::RegisterField::<
12783            2,
12784            0x1,
12785            1,
12786            0,
12787            p40pfs_ha::Pdr,
12788            p40pfs_ha::Pdr,
12789            P40PfsHa_SPEC,
12790            crate::common::RW,
12791        >::from_register(self, 0)
12792    }
12793
12794    #[doc = "Pull-up Control"]
12795    #[inline(always)]
12796    pub fn pcr(
12797        self,
12798    ) -> crate::common::RegisterField<
12799        4,
12800        0x1,
12801        1,
12802        0,
12803        p40pfs_ha::Pcr,
12804        p40pfs_ha::Pcr,
12805        P40PfsHa_SPEC,
12806        crate::common::RW,
12807    > {
12808        crate::common::RegisterField::<
12809            4,
12810            0x1,
12811            1,
12812            0,
12813            p40pfs_ha::Pcr,
12814            p40pfs_ha::Pcr,
12815            P40PfsHa_SPEC,
12816            crate::common::RW,
12817        >::from_register(self, 0)
12818    }
12819
12820    #[doc = "N-Channel Open-Drain Control"]
12821    #[inline(always)]
12822    pub fn ncodr(
12823        self,
12824    ) -> crate::common::RegisterField<
12825        6,
12826        0x1,
12827        1,
12828        0,
12829        p40pfs_ha::Ncodr,
12830        p40pfs_ha::Ncodr,
12831        P40PfsHa_SPEC,
12832        crate::common::RW,
12833    > {
12834        crate::common::RegisterField::<
12835            6,
12836            0x1,
12837            1,
12838            0,
12839            p40pfs_ha::Ncodr,
12840            p40pfs_ha::Ncodr,
12841            P40PfsHa_SPEC,
12842            crate::common::RW,
12843        >::from_register(self, 0)
12844    }
12845
12846    #[doc = "Port Drive Capability"]
12847    #[inline(always)]
12848    pub fn dscr(
12849        self,
12850    ) -> crate::common::RegisterField<
12851        10,
12852        0x3,
12853        1,
12854        0,
12855        p40pfs_ha::Dscr,
12856        p40pfs_ha::Dscr,
12857        P40PfsHa_SPEC,
12858        crate::common::RW,
12859    > {
12860        crate::common::RegisterField::<
12861            10,
12862            0x3,
12863            1,
12864            0,
12865            p40pfs_ha::Dscr,
12866            p40pfs_ha::Dscr,
12867            P40PfsHa_SPEC,
12868            crate::common::RW,
12869        >::from_register(self, 0)
12870    }
12871
12872    #[doc = "Event on Falling/Event on Rising"]
12873    #[inline(always)]
12874    pub fn eofr(
12875        self,
12876    ) -> crate::common::RegisterField<
12877        12,
12878        0x3,
12879        1,
12880        0,
12881        p40pfs_ha::Eofr,
12882        p40pfs_ha::Eofr,
12883        P40PfsHa_SPEC,
12884        crate::common::RW,
12885    > {
12886        crate::common::RegisterField::<
12887            12,
12888            0x3,
12889            1,
12890            0,
12891            p40pfs_ha::Eofr,
12892            p40pfs_ha::Eofr,
12893            P40PfsHa_SPEC,
12894            crate::common::RW,
12895        >::from_register(self, 0)
12896    }
12897
12898    #[doc = "IRQ Input Enable"]
12899    #[inline(always)]
12900    pub fn isel(
12901        self,
12902    ) -> crate::common::RegisterField<
12903        14,
12904        0x1,
12905        1,
12906        0,
12907        p40pfs_ha::Isel,
12908        p40pfs_ha::Isel,
12909        P40PfsHa_SPEC,
12910        crate::common::RW,
12911    > {
12912        crate::common::RegisterField::<
12913            14,
12914            0x1,
12915            1,
12916            0,
12917            p40pfs_ha::Isel,
12918            p40pfs_ha::Isel,
12919            P40PfsHa_SPEC,
12920            crate::common::RW,
12921        >::from_register(self, 0)
12922    }
12923
12924    #[doc = "Analog Input Enable"]
12925    #[inline(always)]
12926    pub fn asel(
12927        self,
12928    ) -> crate::common::RegisterField<
12929        15,
12930        0x1,
12931        1,
12932        0,
12933        p40pfs_ha::Asel,
12934        p40pfs_ha::Asel,
12935        P40PfsHa_SPEC,
12936        crate::common::RW,
12937    > {
12938        crate::common::RegisterField::<
12939            15,
12940            0x1,
12941            1,
12942            0,
12943            p40pfs_ha::Asel,
12944            p40pfs_ha::Asel,
12945            P40PfsHa_SPEC,
12946            crate::common::RW,
12947        >::from_register(self, 0)
12948    }
12949}
12950impl ::core::default::Default for P40PfsHa {
12951    #[inline(always)]
12952    fn default() -> P40PfsHa {
12953        <crate::RegValueT<P40PfsHa_SPEC> as RegisterValue<_>>::new(0)
12954    }
12955}
12956pub mod p40pfs_ha {
12957
12958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12959    pub struct Podr_SPEC;
12960    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
12961    impl Podr {
12962        #[doc = "Output low"]
12963        pub const _0: Self = Self::new(0);
12964
12965        #[doc = "Output high"]
12966        pub const _1: Self = Self::new(1);
12967    }
12968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12969    pub struct Pidr_SPEC;
12970    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
12971    impl Pidr {
12972        #[doc = "Low level"]
12973        pub const _0: Self = Self::new(0);
12974
12975        #[doc = "High level"]
12976        pub const _1: Self = Self::new(1);
12977    }
12978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12979    pub struct Pdr_SPEC;
12980    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
12981    impl Pdr {
12982        #[doc = "Input (functions as an input pin)"]
12983        pub const _0: Self = Self::new(0);
12984
12985        #[doc = "Output (functions as an output pin)"]
12986        pub const _1: Self = Self::new(1);
12987    }
12988    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12989    pub struct Pcr_SPEC;
12990    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
12991    impl Pcr {
12992        #[doc = "Disable input pull-up"]
12993        pub const _0: Self = Self::new(0);
12994
12995        #[doc = "Enable input pull-up"]
12996        pub const _1: Self = Self::new(1);
12997    }
12998    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
12999    pub struct Ncodr_SPEC;
13000    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13001    impl Ncodr {
13002        #[doc = "Output CMOS"]
13003        pub const _0: Self = Self::new(0);
13004
13005        #[doc = "Output NMOS open-drain"]
13006        pub const _1: Self = Self::new(1);
13007    }
13008    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13009    pub struct Dscr_SPEC;
13010    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
13011    impl Dscr {
13012        #[doc = "Low drive"]
13013        pub const _00: Self = Self::new(0);
13014
13015        #[doc = "Middle drive"]
13016        pub const _01: Self = Self::new(1);
13017
13018        #[doc = "Setting prohibited"]
13019        pub const _10: Self = Self::new(2);
13020
13021        #[doc = "High drive"]
13022        pub const _11: Self = Self::new(3);
13023    }
13024    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13025    pub struct Eofr_SPEC;
13026    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
13027    impl Eofr {
13028        #[doc = "Don\'t care"]
13029        pub const _00: Self = Self::new(0);
13030
13031        #[doc = "Detect rising edge"]
13032        pub const _01: Self = Self::new(1);
13033
13034        #[doc = "Detect falling edge"]
13035        pub const _10: Self = Self::new(2);
13036
13037        #[doc = "Detect both edges"]
13038        pub const _11: Self = Self::new(3);
13039    }
13040    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13041    pub struct Isel_SPEC;
13042    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13043    impl Isel {
13044        #[doc = "Do not use as IRQn input pin"]
13045        pub const _0: Self = Self::new(0);
13046
13047        #[doc = "Use as IRQn input pin"]
13048        pub const _1: Self = Self::new(1);
13049    }
13050    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13051    pub struct Asel_SPEC;
13052    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
13053    impl Asel {
13054        #[doc = "Do not use as analog pin"]
13055        pub const _0: Self = Self::new(0);
13056
13057        #[doc = "Use as analog pin"]
13058        pub const _1: Self = Self::new(1);
13059    }
13060}
13061#[doc(hidden)]
13062#[derive(Copy, Clone, Eq, PartialEq)]
13063pub struct P40PfsBy_SPEC;
13064impl crate::sealed::RegSpec for P40PfsBy_SPEC {
13065    type DataType = u8;
13066}
13067
13068#[doc = "Port 40%s Pin Function Select Register"]
13069pub type P40PfsBy = crate::RegValueT<P40PfsBy_SPEC>;
13070
13071impl P40PfsBy {
13072    #[doc = "Port Output Data"]
13073    #[inline(always)]
13074    pub fn podr(
13075        self,
13076    ) -> crate::common::RegisterField<
13077        0,
13078        0x1,
13079        1,
13080        0,
13081        p40pfs_by::Podr,
13082        p40pfs_by::Podr,
13083        P40PfsBy_SPEC,
13084        crate::common::RW,
13085    > {
13086        crate::common::RegisterField::<
13087            0,
13088            0x1,
13089            1,
13090            0,
13091            p40pfs_by::Podr,
13092            p40pfs_by::Podr,
13093            P40PfsBy_SPEC,
13094            crate::common::RW,
13095        >::from_register(self, 0)
13096    }
13097
13098    #[doc = "Port State"]
13099    #[inline(always)]
13100    pub fn pidr(
13101        self,
13102    ) -> crate::common::RegisterField<
13103        1,
13104        0x1,
13105        1,
13106        0,
13107        p40pfs_by::Pidr,
13108        p40pfs_by::Pidr,
13109        P40PfsBy_SPEC,
13110        crate::common::R,
13111    > {
13112        crate::common::RegisterField::<
13113            1,
13114            0x1,
13115            1,
13116            0,
13117            p40pfs_by::Pidr,
13118            p40pfs_by::Pidr,
13119            P40PfsBy_SPEC,
13120            crate::common::R,
13121        >::from_register(self, 0)
13122    }
13123
13124    #[doc = "Port Direction"]
13125    #[inline(always)]
13126    pub fn pdr(
13127        self,
13128    ) -> crate::common::RegisterField<
13129        2,
13130        0x1,
13131        1,
13132        0,
13133        p40pfs_by::Pdr,
13134        p40pfs_by::Pdr,
13135        P40PfsBy_SPEC,
13136        crate::common::RW,
13137    > {
13138        crate::common::RegisterField::<
13139            2,
13140            0x1,
13141            1,
13142            0,
13143            p40pfs_by::Pdr,
13144            p40pfs_by::Pdr,
13145            P40PfsBy_SPEC,
13146            crate::common::RW,
13147        >::from_register(self, 0)
13148    }
13149
13150    #[doc = "Pull-up Control"]
13151    #[inline(always)]
13152    pub fn pcr(
13153        self,
13154    ) -> crate::common::RegisterField<
13155        4,
13156        0x1,
13157        1,
13158        0,
13159        p40pfs_by::Pcr,
13160        p40pfs_by::Pcr,
13161        P40PfsBy_SPEC,
13162        crate::common::RW,
13163    > {
13164        crate::common::RegisterField::<
13165            4,
13166            0x1,
13167            1,
13168            0,
13169            p40pfs_by::Pcr,
13170            p40pfs_by::Pcr,
13171            P40PfsBy_SPEC,
13172            crate::common::RW,
13173        >::from_register(self, 0)
13174    }
13175
13176    #[doc = "N-Channel Open-Drain Control"]
13177    #[inline(always)]
13178    pub fn ncodr(
13179        self,
13180    ) -> crate::common::RegisterField<
13181        6,
13182        0x1,
13183        1,
13184        0,
13185        p40pfs_by::Ncodr,
13186        p40pfs_by::Ncodr,
13187        P40PfsBy_SPEC,
13188        crate::common::RW,
13189    > {
13190        crate::common::RegisterField::<
13191            6,
13192            0x1,
13193            1,
13194            0,
13195            p40pfs_by::Ncodr,
13196            p40pfs_by::Ncodr,
13197            P40PfsBy_SPEC,
13198            crate::common::RW,
13199        >::from_register(self, 0)
13200    }
13201}
13202impl ::core::default::Default for P40PfsBy {
13203    #[inline(always)]
13204    fn default() -> P40PfsBy {
13205        <crate::RegValueT<P40PfsBy_SPEC> as RegisterValue<_>>::new(0)
13206    }
13207}
13208pub mod p40pfs_by {
13209
13210    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13211    pub struct Podr_SPEC;
13212    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13213    impl Podr {
13214        #[doc = "Output low"]
13215        pub const _0: Self = Self::new(0);
13216
13217        #[doc = "Output high"]
13218        pub const _1: Self = Self::new(1);
13219    }
13220    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13221    pub struct Pidr_SPEC;
13222    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13223    impl Pidr {
13224        #[doc = "Low level"]
13225        pub const _0: Self = Self::new(0);
13226
13227        #[doc = "High level"]
13228        pub const _1: Self = Self::new(1);
13229    }
13230    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13231    pub struct Pdr_SPEC;
13232    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13233    impl Pdr {
13234        #[doc = "Input (functions as an input pin)"]
13235        pub const _0: Self = Self::new(0);
13236
13237        #[doc = "Output (functions as an output pin)"]
13238        pub const _1: Self = Self::new(1);
13239    }
13240    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13241    pub struct Pcr_SPEC;
13242    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13243    impl Pcr {
13244        #[doc = "Disable input pull-up"]
13245        pub const _0: Self = Self::new(0);
13246
13247        #[doc = "Enable input pull-up"]
13248        pub const _1: Self = Self::new(1);
13249    }
13250    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13251    pub struct Ncodr_SPEC;
13252    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13253    impl Ncodr {
13254        #[doc = "Output CMOS"]
13255        pub const _0: Self = Self::new(0);
13256
13257        #[doc = "Output NMOS open-drain"]
13258        pub const _1: Self = Self::new(1);
13259    }
13260}
13261#[doc(hidden)]
13262#[derive(Copy, Clone, Eq, PartialEq)]
13263pub struct P4Pfs_SPEC;
13264impl crate::sealed::RegSpec for P4Pfs_SPEC {
13265    type DataType = u32;
13266}
13267
13268#[doc = "Port 4%s Pin Function Select Register"]
13269pub type P4Pfs = crate::RegValueT<P4Pfs_SPEC>;
13270
13271impl P4Pfs {
13272    #[doc = "Port Output Data"]
13273    #[inline(always)]
13274    pub fn podr(
13275        self,
13276    ) -> crate::common::RegisterField<
13277        0,
13278        0x1,
13279        1,
13280        0,
13281        p4pfs::Podr,
13282        p4pfs::Podr,
13283        P4Pfs_SPEC,
13284        crate::common::RW,
13285    > {
13286        crate::common::RegisterField::<
13287            0,
13288            0x1,
13289            1,
13290            0,
13291            p4pfs::Podr,
13292            p4pfs::Podr,
13293            P4Pfs_SPEC,
13294            crate::common::RW,
13295        >::from_register(self, 0)
13296    }
13297
13298    #[doc = "Port State"]
13299    #[inline(always)]
13300    pub fn pidr(
13301        self,
13302    ) -> crate::common::RegisterField<
13303        1,
13304        0x1,
13305        1,
13306        0,
13307        p4pfs::Pidr,
13308        p4pfs::Pidr,
13309        P4Pfs_SPEC,
13310        crate::common::R,
13311    > {
13312        crate::common::RegisterField::<
13313            1,
13314            0x1,
13315            1,
13316            0,
13317            p4pfs::Pidr,
13318            p4pfs::Pidr,
13319            P4Pfs_SPEC,
13320            crate::common::R,
13321        >::from_register(self, 0)
13322    }
13323
13324    #[doc = "Port Direction"]
13325    #[inline(always)]
13326    pub fn pdr(
13327        self,
13328    ) -> crate::common::RegisterField<
13329        2,
13330        0x1,
13331        1,
13332        0,
13333        p4pfs::Pdr,
13334        p4pfs::Pdr,
13335        P4Pfs_SPEC,
13336        crate::common::RW,
13337    > {
13338        crate::common::RegisterField::<
13339            2,
13340            0x1,
13341            1,
13342            0,
13343            p4pfs::Pdr,
13344            p4pfs::Pdr,
13345            P4Pfs_SPEC,
13346            crate::common::RW,
13347        >::from_register(self, 0)
13348    }
13349
13350    #[doc = "Pull-up Control"]
13351    #[inline(always)]
13352    pub fn pcr(
13353        self,
13354    ) -> crate::common::RegisterField<
13355        4,
13356        0x1,
13357        1,
13358        0,
13359        p4pfs::Pcr,
13360        p4pfs::Pcr,
13361        P4Pfs_SPEC,
13362        crate::common::RW,
13363    > {
13364        crate::common::RegisterField::<
13365            4,
13366            0x1,
13367            1,
13368            0,
13369            p4pfs::Pcr,
13370            p4pfs::Pcr,
13371            P4Pfs_SPEC,
13372            crate::common::RW,
13373        >::from_register(self, 0)
13374    }
13375
13376    #[doc = "N-Channel Open-Drain Control"]
13377    #[inline(always)]
13378    pub fn ncodr(
13379        self,
13380    ) -> crate::common::RegisterField<
13381        6,
13382        0x1,
13383        1,
13384        0,
13385        p4pfs::Ncodr,
13386        p4pfs::Ncodr,
13387        P4Pfs_SPEC,
13388        crate::common::RW,
13389    > {
13390        crate::common::RegisterField::<
13391            6,
13392            0x1,
13393            1,
13394            0,
13395            p4pfs::Ncodr,
13396            p4pfs::Ncodr,
13397            P4Pfs_SPEC,
13398            crate::common::RW,
13399        >::from_register(self, 0)
13400    }
13401
13402    #[doc = "Port Drive Capability"]
13403    #[inline(always)]
13404    pub fn dscr(
13405        self,
13406    ) -> crate::common::RegisterField<
13407        10,
13408        0x3,
13409        1,
13410        0,
13411        p4pfs::Dscr,
13412        p4pfs::Dscr,
13413        P4Pfs_SPEC,
13414        crate::common::RW,
13415    > {
13416        crate::common::RegisterField::<
13417            10,
13418            0x3,
13419            1,
13420            0,
13421            p4pfs::Dscr,
13422            p4pfs::Dscr,
13423            P4Pfs_SPEC,
13424            crate::common::RW,
13425        >::from_register(self, 0)
13426    }
13427
13428    #[doc = "Event on Falling/Event on Rising"]
13429    #[inline(always)]
13430    pub fn eofr(
13431        self,
13432    ) -> crate::common::RegisterField<
13433        12,
13434        0x3,
13435        1,
13436        0,
13437        p4pfs::Eofr,
13438        p4pfs::Eofr,
13439        P4Pfs_SPEC,
13440        crate::common::RW,
13441    > {
13442        crate::common::RegisterField::<
13443            12,
13444            0x3,
13445            1,
13446            0,
13447            p4pfs::Eofr,
13448            p4pfs::Eofr,
13449            P4Pfs_SPEC,
13450            crate::common::RW,
13451        >::from_register(self, 0)
13452    }
13453
13454    #[doc = "IRQ Input Enable"]
13455    #[inline(always)]
13456    pub fn isel(
13457        self,
13458    ) -> crate::common::RegisterField<
13459        14,
13460        0x1,
13461        1,
13462        0,
13463        p4pfs::Isel,
13464        p4pfs::Isel,
13465        P4Pfs_SPEC,
13466        crate::common::RW,
13467    > {
13468        crate::common::RegisterField::<
13469            14,
13470            0x1,
13471            1,
13472            0,
13473            p4pfs::Isel,
13474            p4pfs::Isel,
13475            P4Pfs_SPEC,
13476            crate::common::RW,
13477        >::from_register(self, 0)
13478    }
13479
13480    #[doc = "Analog Input Enable"]
13481    #[inline(always)]
13482    pub fn asel(
13483        self,
13484    ) -> crate::common::RegisterField<
13485        15,
13486        0x1,
13487        1,
13488        0,
13489        p4pfs::Asel,
13490        p4pfs::Asel,
13491        P4Pfs_SPEC,
13492        crate::common::RW,
13493    > {
13494        crate::common::RegisterField::<
13495            15,
13496            0x1,
13497            1,
13498            0,
13499            p4pfs::Asel,
13500            p4pfs::Asel,
13501            P4Pfs_SPEC,
13502            crate::common::RW,
13503        >::from_register(self, 0)
13504    }
13505
13506    #[doc = "Port Mode Control"]
13507    #[inline(always)]
13508    pub fn pmr(
13509        self,
13510    ) -> crate::common::RegisterField<
13511        16,
13512        0x1,
13513        1,
13514        0,
13515        p4pfs::Pmr,
13516        p4pfs::Pmr,
13517        P4Pfs_SPEC,
13518        crate::common::RW,
13519    > {
13520        crate::common::RegisterField::<
13521            16,
13522            0x1,
13523            1,
13524            0,
13525            p4pfs::Pmr,
13526            p4pfs::Pmr,
13527            P4Pfs_SPEC,
13528            crate::common::RW,
13529        >::from_register(self, 0)
13530    }
13531
13532    #[doc = "Peripheral Select"]
13533    #[inline(always)]
13534    pub fn psel(
13535        self,
13536    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P4Pfs_SPEC, crate::common::RW> {
13537        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P4Pfs_SPEC,crate::common::RW>::from_register(self,0)
13538    }
13539}
13540impl ::core::default::Default for P4Pfs {
13541    #[inline(always)]
13542    fn default() -> P4Pfs {
13543        <crate::RegValueT<P4Pfs_SPEC> as RegisterValue<_>>::new(0)
13544    }
13545}
13546pub mod p4pfs {
13547
13548    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13549    pub struct Podr_SPEC;
13550    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13551    impl Podr {
13552        #[doc = "Output low"]
13553        pub const _0: Self = Self::new(0);
13554
13555        #[doc = "Output high"]
13556        pub const _1: Self = Self::new(1);
13557    }
13558    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13559    pub struct Pidr_SPEC;
13560    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13561    impl Pidr {
13562        #[doc = "Low level"]
13563        pub const _0: Self = Self::new(0);
13564
13565        #[doc = "High level"]
13566        pub const _1: Self = Self::new(1);
13567    }
13568    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13569    pub struct Pdr_SPEC;
13570    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13571    impl Pdr {
13572        #[doc = "Input (functions as an input pin)"]
13573        pub const _0: Self = Self::new(0);
13574
13575        #[doc = "Output (functions as an output pin)"]
13576        pub const _1: Self = Self::new(1);
13577    }
13578    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13579    pub struct Pcr_SPEC;
13580    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13581    impl Pcr {
13582        #[doc = "Disable input pull-up"]
13583        pub const _0: Self = Self::new(0);
13584
13585        #[doc = "Enable input pull-up"]
13586        pub const _1: Self = Self::new(1);
13587    }
13588    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13589    pub struct Ncodr_SPEC;
13590    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13591    impl Ncodr {
13592        #[doc = "Output CMOS"]
13593        pub const _0: Self = Self::new(0);
13594
13595        #[doc = "Output NMOS open-drain"]
13596        pub const _1: Self = Self::new(1);
13597    }
13598    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13599    pub struct Dscr_SPEC;
13600    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
13601    impl Dscr {
13602        #[doc = "Low drive"]
13603        pub const _00: Self = Self::new(0);
13604
13605        #[doc = "Middle drive"]
13606        pub const _01: Self = Self::new(1);
13607
13608        #[doc = "Setting prohibited"]
13609        pub const _10: Self = Self::new(2);
13610
13611        #[doc = "High drive"]
13612        pub const _11: Self = Self::new(3);
13613    }
13614    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13615    pub struct Eofr_SPEC;
13616    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
13617    impl Eofr {
13618        #[doc = "Don\'t care"]
13619        pub const _00: Self = Self::new(0);
13620
13621        #[doc = "Detect rising edge"]
13622        pub const _01: Self = Self::new(1);
13623
13624        #[doc = "Detect falling edge"]
13625        pub const _10: Self = Self::new(2);
13626
13627        #[doc = "Detect both edges"]
13628        pub const _11: Self = Self::new(3);
13629    }
13630    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13631    pub struct Isel_SPEC;
13632    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13633    impl Isel {
13634        #[doc = "Do not use as IRQn input pin"]
13635        pub const _0: Self = Self::new(0);
13636
13637        #[doc = "Use as IRQn input pin"]
13638        pub const _1: Self = Self::new(1);
13639    }
13640    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13641    pub struct Asel_SPEC;
13642    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
13643    impl Asel {
13644        #[doc = "Do not use as analog pin"]
13645        pub const _0: Self = Self::new(0);
13646
13647        #[doc = "Use as analog pin"]
13648        pub const _1: Self = Self::new(1);
13649    }
13650    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13651    pub struct Pmr_SPEC;
13652    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
13653    impl Pmr {
13654        #[doc = "Use as general I/O pin"]
13655        pub const _0: Self = Self::new(0);
13656
13657        #[doc = "Use as I/O port for peripheral functions"]
13658        pub const _1: Self = Self::new(1);
13659    }
13660}
13661#[doc(hidden)]
13662#[derive(Copy, Clone, Eq, PartialEq)]
13663pub struct P4PfsHa_SPEC;
13664impl crate::sealed::RegSpec for P4PfsHa_SPEC {
13665    type DataType = u16;
13666}
13667
13668#[doc = "Port 4%s Pin Function Select Register"]
13669pub type P4PfsHa = crate::RegValueT<P4PfsHa_SPEC>;
13670
13671impl P4PfsHa {
13672    #[doc = "Port Output Data"]
13673    #[inline(always)]
13674    pub fn podr(
13675        self,
13676    ) -> crate::common::RegisterField<
13677        0,
13678        0x1,
13679        1,
13680        0,
13681        p4pfs_ha::Podr,
13682        p4pfs_ha::Podr,
13683        P4PfsHa_SPEC,
13684        crate::common::RW,
13685    > {
13686        crate::common::RegisterField::<
13687            0,
13688            0x1,
13689            1,
13690            0,
13691            p4pfs_ha::Podr,
13692            p4pfs_ha::Podr,
13693            P4PfsHa_SPEC,
13694            crate::common::RW,
13695        >::from_register(self, 0)
13696    }
13697
13698    #[doc = "Port State"]
13699    #[inline(always)]
13700    pub fn pidr(
13701        self,
13702    ) -> crate::common::RegisterField<
13703        1,
13704        0x1,
13705        1,
13706        0,
13707        p4pfs_ha::Pidr,
13708        p4pfs_ha::Pidr,
13709        P4PfsHa_SPEC,
13710        crate::common::R,
13711    > {
13712        crate::common::RegisterField::<
13713            1,
13714            0x1,
13715            1,
13716            0,
13717            p4pfs_ha::Pidr,
13718            p4pfs_ha::Pidr,
13719            P4PfsHa_SPEC,
13720            crate::common::R,
13721        >::from_register(self, 0)
13722    }
13723
13724    #[doc = "Port Direction"]
13725    #[inline(always)]
13726    pub fn pdr(
13727        self,
13728    ) -> crate::common::RegisterField<
13729        2,
13730        0x1,
13731        1,
13732        0,
13733        p4pfs_ha::Pdr,
13734        p4pfs_ha::Pdr,
13735        P4PfsHa_SPEC,
13736        crate::common::RW,
13737    > {
13738        crate::common::RegisterField::<
13739            2,
13740            0x1,
13741            1,
13742            0,
13743            p4pfs_ha::Pdr,
13744            p4pfs_ha::Pdr,
13745            P4PfsHa_SPEC,
13746            crate::common::RW,
13747        >::from_register(self, 0)
13748    }
13749
13750    #[doc = "Pull-up Control"]
13751    #[inline(always)]
13752    pub fn pcr(
13753        self,
13754    ) -> crate::common::RegisterField<
13755        4,
13756        0x1,
13757        1,
13758        0,
13759        p4pfs_ha::Pcr,
13760        p4pfs_ha::Pcr,
13761        P4PfsHa_SPEC,
13762        crate::common::RW,
13763    > {
13764        crate::common::RegisterField::<
13765            4,
13766            0x1,
13767            1,
13768            0,
13769            p4pfs_ha::Pcr,
13770            p4pfs_ha::Pcr,
13771            P4PfsHa_SPEC,
13772            crate::common::RW,
13773        >::from_register(self, 0)
13774    }
13775
13776    #[doc = "N-Channel Open-Drain Control"]
13777    #[inline(always)]
13778    pub fn ncodr(
13779        self,
13780    ) -> crate::common::RegisterField<
13781        6,
13782        0x1,
13783        1,
13784        0,
13785        p4pfs_ha::Ncodr,
13786        p4pfs_ha::Ncodr,
13787        P4PfsHa_SPEC,
13788        crate::common::RW,
13789    > {
13790        crate::common::RegisterField::<
13791            6,
13792            0x1,
13793            1,
13794            0,
13795            p4pfs_ha::Ncodr,
13796            p4pfs_ha::Ncodr,
13797            P4PfsHa_SPEC,
13798            crate::common::RW,
13799        >::from_register(self, 0)
13800    }
13801
13802    #[doc = "Port Drive Capability"]
13803    #[inline(always)]
13804    pub fn dscr(
13805        self,
13806    ) -> crate::common::RegisterField<
13807        10,
13808        0x3,
13809        1,
13810        0,
13811        p4pfs_ha::Dscr,
13812        p4pfs_ha::Dscr,
13813        P4PfsHa_SPEC,
13814        crate::common::RW,
13815    > {
13816        crate::common::RegisterField::<
13817            10,
13818            0x3,
13819            1,
13820            0,
13821            p4pfs_ha::Dscr,
13822            p4pfs_ha::Dscr,
13823            P4PfsHa_SPEC,
13824            crate::common::RW,
13825        >::from_register(self, 0)
13826    }
13827
13828    #[doc = "Event on Falling/Event on Rising"]
13829    #[inline(always)]
13830    pub fn eofr(
13831        self,
13832    ) -> crate::common::RegisterField<
13833        12,
13834        0x3,
13835        1,
13836        0,
13837        p4pfs_ha::Eofr,
13838        p4pfs_ha::Eofr,
13839        P4PfsHa_SPEC,
13840        crate::common::RW,
13841    > {
13842        crate::common::RegisterField::<
13843            12,
13844            0x3,
13845            1,
13846            0,
13847            p4pfs_ha::Eofr,
13848            p4pfs_ha::Eofr,
13849            P4PfsHa_SPEC,
13850            crate::common::RW,
13851        >::from_register(self, 0)
13852    }
13853
13854    #[doc = "IRQ Input Enable"]
13855    #[inline(always)]
13856    pub fn isel(
13857        self,
13858    ) -> crate::common::RegisterField<
13859        14,
13860        0x1,
13861        1,
13862        0,
13863        p4pfs_ha::Isel,
13864        p4pfs_ha::Isel,
13865        P4PfsHa_SPEC,
13866        crate::common::RW,
13867    > {
13868        crate::common::RegisterField::<
13869            14,
13870            0x1,
13871            1,
13872            0,
13873            p4pfs_ha::Isel,
13874            p4pfs_ha::Isel,
13875            P4PfsHa_SPEC,
13876            crate::common::RW,
13877        >::from_register(self, 0)
13878    }
13879
13880    #[doc = "Analog Input Enable"]
13881    #[inline(always)]
13882    pub fn asel(
13883        self,
13884    ) -> crate::common::RegisterField<
13885        15,
13886        0x1,
13887        1,
13888        0,
13889        p4pfs_ha::Asel,
13890        p4pfs_ha::Asel,
13891        P4PfsHa_SPEC,
13892        crate::common::RW,
13893    > {
13894        crate::common::RegisterField::<
13895            15,
13896            0x1,
13897            1,
13898            0,
13899            p4pfs_ha::Asel,
13900            p4pfs_ha::Asel,
13901            P4PfsHa_SPEC,
13902            crate::common::RW,
13903        >::from_register(self, 0)
13904    }
13905}
13906impl ::core::default::Default for P4PfsHa {
13907    #[inline(always)]
13908    fn default() -> P4PfsHa {
13909        <crate::RegValueT<P4PfsHa_SPEC> as RegisterValue<_>>::new(0)
13910    }
13911}
13912pub mod p4pfs_ha {
13913
13914    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13915    pub struct Podr_SPEC;
13916    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
13917    impl Podr {
13918        #[doc = "Output low"]
13919        pub const _0: Self = Self::new(0);
13920
13921        #[doc = "Output high"]
13922        pub const _1: Self = Self::new(1);
13923    }
13924    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13925    pub struct Pidr_SPEC;
13926    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
13927    impl Pidr {
13928        #[doc = "Low level"]
13929        pub const _0: Self = Self::new(0);
13930
13931        #[doc = "High level"]
13932        pub const _1: Self = Self::new(1);
13933    }
13934    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13935    pub struct Pdr_SPEC;
13936    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
13937    impl Pdr {
13938        #[doc = "Input (functions as an input pin)"]
13939        pub const _0: Self = Self::new(0);
13940
13941        #[doc = "Output (functions as an output pin)"]
13942        pub const _1: Self = Self::new(1);
13943    }
13944    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13945    pub struct Pcr_SPEC;
13946    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
13947    impl Pcr {
13948        #[doc = "Disable input pull-up"]
13949        pub const _0: Self = Self::new(0);
13950
13951        #[doc = "Enable input pull-up"]
13952        pub const _1: Self = Self::new(1);
13953    }
13954    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13955    pub struct Ncodr_SPEC;
13956    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
13957    impl Ncodr {
13958        #[doc = "Output CMOS"]
13959        pub const _0: Self = Self::new(0);
13960
13961        #[doc = "Output NMOS open-drain"]
13962        pub const _1: Self = Self::new(1);
13963    }
13964    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13965    pub struct Dscr_SPEC;
13966    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
13967    impl Dscr {
13968        #[doc = "Low drive"]
13969        pub const _00: Self = Self::new(0);
13970
13971        #[doc = "Middle drive"]
13972        pub const _01: Self = Self::new(1);
13973
13974        #[doc = "Setting prohibited"]
13975        pub const _10: Self = Self::new(2);
13976
13977        #[doc = "High drive"]
13978        pub const _11: Self = Self::new(3);
13979    }
13980    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13981    pub struct Eofr_SPEC;
13982    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
13983    impl Eofr {
13984        #[doc = "Don\'t care"]
13985        pub const _00: Self = Self::new(0);
13986
13987        #[doc = "Detect rising edge"]
13988        pub const _01: Self = Self::new(1);
13989
13990        #[doc = "Detect falling edge"]
13991        pub const _10: Self = Self::new(2);
13992
13993        #[doc = "Detect both edges"]
13994        pub const _11: Self = Self::new(3);
13995    }
13996    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
13997    pub struct Isel_SPEC;
13998    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
13999    impl Isel {
14000        #[doc = "Do not use as IRQn input pin"]
14001        pub const _0: Self = Self::new(0);
14002
14003        #[doc = "Use as IRQn input pin"]
14004        pub const _1: Self = Self::new(1);
14005    }
14006    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14007    pub struct Asel_SPEC;
14008    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
14009    impl Asel {
14010        #[doc = "Do not use as analog pin"]
14011        pub const _0: Self = Self::new(0);
14012
14013        #[doc = "Use as analog pin"]
14014        pub const _1: Self = Self::new(1);
14015    }
14016}
14017#[doc(hidden)]
14018#[derive(Copy, Clone, Eq, PartialEq)]
14019pub struct P4PfsBy_SPEC;
14020impl crate::sealed::RegSpec for P4PfsBy_SPEC {
14021    type DataType = u8;
14022}
14023
14024#[doc = "Port 4%s Pin Function Select Register"]
14025pub type P4PfsBy = crate::RegValueT<P4PfsBy_SPEC>;
14026
14027impl P4PfsBy {
14028    #[doc = "Port Output Data"]
14029    #[inline(always)]
14030    pub fn podr(
14031        self,
14032    ) -> crate::common::RegisterField<
14033        0,
14034        0x1,
14035        1,
14036        0,
14037        p4pfs_by::Podr,
14038        p4pfs_by::Podr,
14039        P4PfsBy_SPEC,
14040        crate::common::RW,
14041    > {
14042        crate::common::RegisterField::<
14043            0,
14044            0x1,
14045            1,
14046            0,
14047            p4pfs_by::Podr,
14048            p4pfs_by::Podr,
14049            P4PfsBy_SPEC,
14050            crate::common::RW,
14051        >::from_register(self, 0)
14052    }
14053
14054    #[doc = "Port State"]
14055    #[inline(always)]
14056    pub fn pidr(
14057        self,
14058    ) -> crate::common::RegisterField<
14059        1,
14060        0x1,
14061        1,
14062        0,
14063        p4pfs_by::Pidr,
14064        p4pfs_by::Pidr,
14065        P4PfsBy_SPEC,
14066        crate::common::R,
14067    > {
14068        crate::common::RegisterField::<
14069            1,
14070            0x1,
14071            1,
14072            0,
14073            p4pfs_by::Pidr,
14074            p4pfs_by::Pidr,
14075            P4PfsBy_SPEC,
14076            crate::common::R,
14077        >::from_register(self, 0)
14078    }
14079
14080    #[doc = "Port Direction"]
14081    #[inline(always)]
14082    pub fn pdr(
14083        self,
14084    ) -> crate::common::RegisterField<
14085        2,
14086        0x1,
14087        1,
14088        0,
14089        p4pfs_by::Pdr,
14090        p4pfs_by::Pdr,
14091        P4PfsBy_SPEC,
14092        crate::common::RW,
14093    > {
14094        crate::common::RegisterField::<
14095            2,
14096            0x1,
14097            1,
14098            0,
14099            p4pfs_by::Pdr,
14100            p4pfs_by::Pdr,
14101            P4PfsBy_SPEC,
14102            crate::common::RW,
14103        >::from_register(self, 0)
14104    }
14105
14106    #[doc = "Pull-up Control"]
14107    #[inline(always)]
14108    pub fn pcr(
14109        self,
14110    ) -> crate::common::RegisterField<
14111        4,
14112        0x1,
14113        1,
14114        0,
14115        p4pfs_by::Pcr,
14116        p4pfs_by::Pcr,
14117        P4PfsBy_SPEC,
14118        crate::common::RW,
14119    > {
14120        crate::common::RegisterField::<
14121            4,
14122            0x1,
14123            1,
14124            0,
14125            p4pfs_by::Pcr,
14126            p4pfs_by::Pcr,
14127            P4PfsBy_SPEC,
14128            crate::common::RW,
14129        >::from_register(self, 0)
14130    }
14131
14132    #[doc = "N-Channel Open-Drain Control"]
14133    #[inline(always)]
14134    pub fn ncodr(
14135        self,
14136    ) -> crate::common::RegisterField<
14137        6,
14138        0x1,
14139        1,
14140        0,
14141        p4pfs_by::Ncodr,
14142        p4pfs_by::Ncodr,
14143        P4PfsBy_SPEC,
14144        crate::common::RW,
14145    > {
14146        crate::common::RegisterField::<
14147            6,
14148            0x1,
14149            1,
14150            0,
14151            p4pfs_by::Ncodr,
14152            p4pfs_by::Ncodr,
14153            P4PfsBy_SPEC,
14154            crate::common::RW,
14155        >::from_register(self, 0)
14156    }
14157}
14158impl ::core::default::Default for P4PfsBy {
14159    #[inline(always)]
14160    fn default() -> P4PfsBy {
14161        <crate::RegValueT<P4PfsBy_SPEC> as RegisterValue<_>>::new(0)
14162    }
14163}
14164pub mod p4pfs_by {
14165
14166    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14167    pub struct Podr_SPEC;
14168    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
14169    impl Podr {
14170        #[doc = "Output low"]
14171        pub const _0: Self = Self::new(0);
14172
14173        #[doc = "Output high"]
14174        pub const _1: Self = Self::new(1);
14175    }
14176    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14177    pub struct Pidr_SPEC;
14178    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
14179    impl Pidr {
14180        #[doc = "Low level"]
14181        pub const _0: Self = Self::new(0);
14182
14183        #[doc = "High level"]
14184        pub const _1: Self = Self::new(1);
14185    }
14186    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14187    pub struct Pdr_SPEC;
14188    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
14189    impl Pdr {
14190        #[doc = "Input (functions as an input pin)"]
14191        pub const _0: Self = Self::new(0);
14192
14193        #[doc = "Output (functions as an output pin)"]
14194        pub const _1: Self = Self::new(1);
14195    }
14196    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14197    pub struct Pcr_SPEC;
14198    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
14199    impl Pcr {
14200        #[doc = "Disable input pull-up"]
14201        pub const _0: Self = Self::new(0);
14202
14203        #[doc = "Enable input pull-up"]
14204        pub const _1: Self = Self::new(1);
14205    }
14206    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14207    pub struct Ncodr_SPEC;
14208    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
14209    impl Ncodr {
14210        #[doc = "Output CMOS"]
14211        pub const _0: Self = Self::new(0);
14212
14213        #[doc = "Output NMOS open-drain"]
14214        pub const _1: Self = Self::new(1);
14215    }
14216}
14217#[doc(hidden)]
14218#[derive(Copy, Clone, Eq, PartialEq)]
14219pub struct P500Pfs_SPEC;
14220impl crate::sealed::RegSpec for P500Pfs_SPEC {
14221    type DataType = u32;
14222}
14223
14224#[doc = "Port 500 Pin Function Select Register"]
14225pub type P500Pfs = crate::RegValueT<P500Pfs_SPEC>;
14226
14227impl P500Pfs {
14228    #[doc = "Port Output Data"]
14229    #[inline(always)]
14230    pub fn podr(
14231        self,
14232    ) -> crate::common::RegisterField<
14233        0,
14234        0x1,
14235        1,
14236        0,
14237        p500pfs::Podr,
14238        p500pfs::Podr,
14239        P500Pfs_SPEC,
14240        crate::common::RW,
14241    > {
14242        crate::common::RegisterField::<
14243            0,
14244            0x1,
14245            1,
14246            0,
14247            p500pfs::Podr,
14248            p500pfs::Podr,
14249            P500Pfs_SPEC,
14250            crate::common::RW,
14251        >::from_register(self, 0)
14252    }
14253
14254    #[doc = "Port State"]
14255    #[inline(always)]
14256    pub fn pidr(
14257        self,
14258    ) -> crate::common::RegisterField<
14259        1,
14260        0x1,
14261        1,
14262        0,
14263        p500pfs::Pidr,
14264        p500pfs::Pidr,
14265        P500Pfs_SPEC,
14266        crate::common::R,
14267    > {
14268        crate::common::RegisterField::<
14269            1,
14270            0x1,
14271            1,
14272            0,
14273            p500pfs::Pidr,
14274            p500pfs::Pidr,
14275            P500Pfs_SPEC,
14276            crate::common::R,
14277        >::from_register(self, 0)
14278    }
14279
14280    #[doc = "Port Direction"]
14281    #[inline(always)]
14282    pub fn pdr(
14283        self,
14284    ) -> crate::common::RegisterField<
14285        2,
14286        0x1,
14287        1,
14288        0,
14289        p500pfs::Pdr,
14290        p500pfs::Pdr,
14291        P500Pfs_SPEC,
14292        crate::common::RW,
14293    > {
14294        crate::common::RegisterField::<
14295            2,
14296            0x1,
14297            1,
14298            0,
14299            p500pfs::Pdr,
14300            p500pfs::Pdr,
14301            P500Pfs_SPEC,
14302            crate::common::RW,
14303        >::from_register(self, 0)
14304    }
14305
14306    #[doc = "Pull-up Control"]
14307    #[inline(always)]
14308    pub fn pcr(
14309        self,
14310    ) -> crate::common::RegisterField<
14311        4,
14312        0x1,
14313        1,
14314        0,
14315        p500pfs::Pcr,
14316        p500pfs::Pcr,
14317        P500Pfs_SPEC,
14318        crate::common::RW,
14319    > {
14320        crate::common::RegisterField::<
14321            4,
14322            0x1,
14323            1,
14324            0,
14325            p500pfs::Pcr,
14326            p500pfs::Pcr,
14327            P500Pfs_SPEC,
14328            crate::common::RW,
14329        >::from_register(self, 0)
14330    }
14331
14332    #[doc = "N-Channel Open-Drain Control"]
14333    #[inline(always)]
14334    pub fn ncodr(
14335        self,
14336    ) -> crate::common::RegisterField<
14337        6,
14338        0x1,
14339        1,
14340        0,
14341        p500pfs::Ncodr,
14342        p500pfs::Ncodr,
14343        P500Pfs_SPEC,
14344        crate::common::RW,
14345    > {
14346        crate::common::RegisterField::<
14347            6,
14348            0x1,
14349            1,
14350            0,
14351            p500pfs::Ncodr,
14352            p500pfs::Ncodr,
14353            P500Pfs_SPEC,
14354            crate::common::RW,
14355        >::from_register(self, 0)
14356    }
14357
14358    #[doc = "Port Drive Capability"]
14359    #[inline(always)]
14360    pub fn dscr(
14361        self,
14362    ) -> crate::common::RegisterField<
14363        10,
14364        0x3,
14365        1,
14366        0,
14367        p500pfs::Dscr,
14368        p500pfs::Dscr,
14369        P500Pfs_SPEC,
14370        crate::common::RW,
14371    > {
14372        crate::common::RegisterField::<
14373            10,
14374            0x3,
14375            1,
14376            0,
14377            p500pfs::Dscr,
14378            p500pfs::Dscr,
14379            P500Pfs_SPEC,
14380            crate::common::RW,
14381        >::from_register(self, 0)
14382    }
14383
14384    #[doc = "Event on Falling/Event on Rising"]
14385    #[inline(always)]
14386    pub fn eofr(
14387        self,
14388    ) -> crate::common::RegisterField<
14389        12,
14390        0x3,
14391        1,
14392        0,
14393        p500pfs::Eofr,
14394        p500pfs::Eofr,
14395        P500Pfs_SPEC,
14396        crate::common::RW,
14397    > {
14398        crate::common::RegisterField::<
14399            12,
14400            0x3,
14401            1,
14402            0,
14403            p500pfs::Eofr,
14404            p500pfs::Eofr,
14405            P500Pfs_SPEC,
14406            crate::common::RW,
14407        >::from_register(self, 0)
14408    }
14409
14410    #[doc = "IRQ Input Enable"]
14411    #[inline(always)]
14412    pub fn isel(
14413        self,
14414    ) -> crate::common::RegisterField<
14415        14,
14416        0x1,
14417        1,
14418        0,
14419        p500pfs::Isel,
14420        p500pfs::Isel,
14421        P500Pfs_SPEC,
14422        crate::common::RW,
14423    > {
14424        crate::common::RegisterField::<
14425            14,
14426            0x1,
14427            1,
14428            0,
14429            p500pfs::Isel,
14430            p500pfs::Isel,
14431            P500Pfs_SPEC,
14432            crate::common::RW,
14433        >::from_register(self, 0)
14434    }
14435
14436    #[doc = "Analog Input Enable"]
14437    #[inline(always)]
14438    pub fn asel(
14439        self,
14440    ) -> crate::common::RegisterField<
14441        15,
14442        0x1,
14443        1,
14444        0,
14445        p500pfs::Asel,
14446        p500pfs::Asel,
14447        P500Pfs_SPEC,
14448        crate::common::RW,
14449    > {
14450        crate::common::RegisterField::<
14451            15,
14452            0x1,
14453            1,
14454            0,
14455            p500pfs::Asel,
14456            p500pfs::Asel,
14457            P500Pfs_SPEC,
14458            crate::common::RW,
14459        >::from_register(self, 0)
14460    }
14461
14462    #[doc = "Port Mode Control"]
14463    #[inline(always)]
14464    pub fn pmr(
14465        self,
14466    ) -> crate::common::RegisterField<
14467        16,
14468        0x1,
14469        1,
14470        0,
14471        p500pfs::Pmr,
14472        p500pfs::Pmr,
14473        P500Pfs_SPEC,
14474        crate::common::RW,
14475    > {
14476        crate::common::RegisterField::<
14477            16,
14478            0x1,
14479            1,
14480            0,
14481            p500pfs::Pmr,
14482            p500pfs::Pmr,
14483            P500Pfs_SPEC,
14484            crate::common::RW,
14485        >::from_register(self, 0)
14486    }
14487
14488    #[doc = "Peripheral Select"]
14489    #[inline(always)]
14490    pub fn psel(
14491        self,
14492    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P500Pfs_SPEC, crate::common::RW> {
14493        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P500Pfs_SPEC,crate::common::RW>::from_register(self,0)
14494    }
14495}
14496impl ::core::default::Default for P500Pfs {
14497    #[inline(always)]
14498    fn default() -> P500Pfs {
14499        <crate::RegValueT<P500Pfs_SPEC> as RegisterValue<_>>::new(0)
14500    }
14501}
14502pub mod p500pfs {
14503
14504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14505    pub struct Podr_SPEC;
14506    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
14507    impl Podr {
14508        #[doc = "Output low"]
14509        pub const _0: Self = Self::new(0);
14510
14511        #[doc = "Output high"]
14512        pub const _1: Self = Self::new(1);
14513    }
14514    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14515    pub struct Pidr_SPEC;
14516    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
14517    impl Pidr {
14518        #[doc = "Low level"]
14519        pub const _0: Self = Self::new(0);
14520
14521        #[doc = "High level"]
14522        pub const _1: Self = Self::new(1);
14523    }
14524    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14525    pub struct Pdr_SPEC;
14526    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
14527    impl Pdr {
14528        #[doc = "Input (functions as an input pin)"]
14529        pub const _0: Self = Self::new(0);
14530
14531        #[doc = "Output (functions as an output pin)"]
14532        pub const _1: Self = Self::new(1);
14533    }
14534    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14535    pub struct Pcr_SPEC;
14536    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
14537    impl Pcr {
14538        #[doc = "Disable input pull-up"]
14539        pub const _0: Self = Self::new(0);
14540
14541        #[doc = "Enable input pull-up"]
14542        pub const _1: Self = Self::new(1);
14543    }
14544    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14545    pub struct Ncodr_SPEC;
14546    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
14547    impl Ncodr {
14548        #[doc = "Output CMOS"]
14549        pub const _0: Self = Self::new(0);
14550
14551        #[doc = "Output NMOS open-drain"]
14552        pub const _1: Self = Self::new(1);
14553    }
14554    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14555    pub struct Dscr_SPEC;
14556    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
14557    impl Dscr {
14558        #[doc = "Low drive"]
14559        pub const _00: Self = Self::new(0);
14560
14561        #[doc = "Middle drive"]
14562        pub const _01: Self = Self::new(1);
14563
14564        #[doc = "Setting prohibited"]
14565        pub const _10: Self = Self::new(2);
14566
14567        #[doc = "High drive"]
14568        pub const _11: Self = Self::new(3);
14569    }
14570    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14571    pub struct Eofr_SPEC;
14572    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
14573    impl Eofr {
14574        #[doc = "Don\'t care"]
14575        pub const _00: Self = Self::new(0);
14576
14577        #[doc = "Detect rising edge"]
14578        pub const _01: Self = Self::new(1);
14579
14580        #[doc = "Detect falling edge"]
14581        pub const _10: Self = Self::new(2);
14582
14583        #[doc = "Detect both edges"]
14584        pub const _11: Self = Self::new(3);
14585    }
14586    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14587    pub struct Isel_SPEC;
14588    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
14589    impl Isel {
14590        #[doc = "Do not use as IRQn input pin"]
14591        pub const _0: Self = Self::new(0);
14592
14593        #[doc = "Use as IRQn input pin"]
14594        pub const _1: Self = Self::new(1);
14595    }
14596    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14597    pub struct Asel_SPEC;
14598    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
14599    impl Asel {
14600        #[doc = "Do not use as analog pin"]
14601        pub const _0: Self = Self::new(0);
14602
14603        #[doc = "Use as analog pin"]
14604        pub const _1: Self = Self::new(1);
14605    }
14606    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14607    pub struct Pmr_SPEC;
14608    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
14609    impl Pmr {
14610        #[doc = "Use as general I/O pin"]
14611        pub const _0: Self = Self::new(0);
14612
14613        #[doc = "Use as I/O port for peripheral functions"]
14614        pub const _1: Self = Self::new(1);
14615    }
14616}
14617#[doc(hidden)]
14618#[derive(Copy, Clone, Eq, PartialEq)]
14619pub struct P500PfsHa_SPEC;
14620impl crate::sealed::RegSpec for P500PfsHa_SPEC {
14621    type DataType = u16;
14622}
14623
14624#[doc = "Port 500 Pin Function Select Register"]
14625pub type P500PfsHa = crate::RegValueT<P500PfsHa_SPEC>;
14626
14627impl P500PfsHa {
14628    #[doc = "Port Output Data"]
14629    #[inline(always)]
14630    pub fn podr(
14631        self,
14632    ) -> crate::common::RegisterField<
14633        0,
14634        0x1,
14635        1,
14636        0,
14637        p500pfs_ha::Podr,
14638        p500pfs_ha::Podr,
14639        P500PfsHa_SPEC,
14640        crate::common::RW,
14641    > {
14642        crate::common::RegisterField::<
14643            0,
14644            0x1,
14645            1,
14646            0,
14647            p500pfs_ha::Podr,
14648            p500pfs_ha::Podr,
14649            P500PfsHa_SPEC,
14650            crate::common::RW,
14651        >::from_register(self, 0)
14652    }
14653
14654    #[doc = "Port State"]
14655    #[inline(always)]
14656    pub fn pidr(
14657        self,
14658    ) -> crate::common::RegisterField<
14659        1,
14660        0x1,
14661        1,
14662        0,
14663        p500pfs_ha::Pidr,
14664        p500pfs_ha::Pidr,
14665        P500PfsHa_SPEC,
14666        crate::common::R,
14667    > {
14668        crate::common::RegisterField::<
14669            1,
14670            0x1,
14671            1,
14672            0,
14673            p500pfs_ha::Pidr,
14674            p500pfs_ha::Pidr,
14675            P500PfsHa_SPEC,
14676            crate::common::R,
14677        >::from_register(self, 0)
14678    }
14679
14680    #[doc = "Port Direction"]
14681    #[inline(always)]
14682    pub fn pdr(
14683        self,
14684    ) -> crate::common::RegisterField<
14685        2,
14686        0x1,
14687        1,
14688        0,
14689        p500pfs_ha::Pdr,
14690        p500pfs_ha::Pdr,
14691        P500PfsHa_SPEC,
14692        crate::common::RW,
14693    > {
14694        crate::common::RegisterField::<
14695            2,
14696            0x1,
14697            1,
14698            0,
14699            p500pfs_ha::Pdr,
14700            p500pfs_ha::Pdr,
14701            P500PfsHa_SPEC,
14702            crate::common::RW,
14703        >::from_register(self, 0)
14704    }
14705
14706    #[doc = "Pull-up Control"]
14707    #[inline(always)]
14708    pub fn pcr(
14709        self,
14710    ) -> crate::common::RegisterField<
14711        4,
14712        0x1,
14713        1,
14714        0,
14715        p500pfs_ha::Pcr,
14716        p500pfs_ha::Pcr,
14717        P500PfsHa_SPEC,
14718        crate::common::RW,
14719    > {
14720        crate::common::RegisterField::<
14721            4,
14722            0x1,
14723            1,
14724            0,
14725            p500pfs_ha::Pcr,
14726            p500pfs_ha::Pcr,
14727            P500PfsHa_SPEC,
14728            crate::common::RW,
14729        >::from_register(self, 0)
14730    }
14731
14732    #[doc = "N-Channel Open-Drain Control"]
14733    #[inline(always)]
14734    pub fn ncodr(
14735        self,
14736    ) -> crate::common::RegisterField<
14737        6,
14738        0x1,
14739        1,
14740        0,
14741        p500pfs_ha::Ncodr,
14742        p500pfs_ha::Ncodr,
14743        P500PfsHa_SPEC,
14744        crate::common::RW,
14745    > {
14746        crate::common::RegisterField::<
14747            6,
14748            0x1,
14749            1,
14750            0,
14751            p500pfs_ha::Ncodr,
14752            p500pfs_ha::Ncodr,
14753            P500PfsHa_SPEC,
14754            crate::common::RW,
14755        >::from_register(self, 0)
14756    }
14757
14758    #[doc = "Port Drive Capability"]
14759    #[inline(always)]
14760    pub fn dscr(
14761        self,
14762    ) -> crate::common::RegisterField<
14763        10,
14764        0x3,
14765        1,
14766        0,
14767        p500pfs_ha::Dscr,
14768        p500pfs_ha::Dscr,
14769        P500PfsHa_SPEC,
14770        crate::common::RW,
14771    > {
14772        crate::common::RegisterField::<
14773            10,
14774            0x3,
14775            1,
14776            0,
14777            p500pfs_ha::Dscr,
14778            p500pfs_ha::Dscr,
14779            P500PfsHa_SPEC,
14780            crate::common::RW,
14781        >::from_register(self, 0)
14782    }
14783
14784    #[doc = "Event on Falling/Event on Rising"]
14785    #[inline(always)]
14786    pub fn eofr(
14787        self,
14788    ) -> crate::common::RegisterField<
14789        12,
14790        0x3,
14791        1,
14792        0,
14793        p500pfs_ha::Eofr,
14794        p500pfs_ha::Eofr,
14795        P500PfsHa_SPEC,
14796        crate::common::RW,
14797    > {
14798        crate::common::RegisterField::<
14799            12,
14800            0x3,
14801            1,
14802            0,
14803            p500pfs_ha::Eofr,
14804            p500pfs_ha::Eofr,
14805            P500PfsHa_SPEC,
14806            crate::common::RW,
14807        >::from_register(self, 0)
14808    }
14809
14810    #[doc = "IRQ Input Enable"]
14811    #[inline(always)]
14812    pub fn isel(
14813        self,
14814    ) -> crate::common::RegisterField<
14815        14,
14816        0x1,
14817        1,
14818        0,
14819        p500pfs_ha::Isel,
14820        p500pfs_ha::Isel,
14821        P500PfsHa_SPEC,
14822        crate::common::RW,
14823    > {
14824        crate::common::RegisterField::<
14825            14,
14826            0x1,
14827            1,
14828            0,
14829            p500pfs_ha::Isel,
14830            p500pfs_ha::Isel,
14831            P500PfsHa_SPEC,
14832            crate::common::RW,
14833        >::from_register(self, 0)
14834    }
14835
14836    #[doc = "Analog Input Enable"]
14837    #[inline(always)]
14838    pub fn asel(
14839        self,
14840    ) -> crate::common::RegisterField<
14841        15,
14842        0x1,
14843        1,
14844        0,
14845        p500pfs_ha::Asel,
14846        p500pfs_ha::Asel,
14847        P500PfsHa_SPEC,
14848        crate::common::RW,
14849    > {
14850        crate::common::RegisterField::<
14851            15,
14852            0x1,
14853            1,
14854            0,
14855            p500pfs_ha::Asel,
14856            p500pfs_ha::Asel,
14857            P500PfsHa_SPEC,
14858            crate::common::RW,
14859        >::from_register(self, 0)
14860    }
14861}
14862impl ::core::default::Default for P500PfsHa {
14863    #[inline(always)]
14864    fn default() -> P500PfsHa {
14865        <crate::RegValueT<P500PfsHa_SPEC> as RegisterValue<_>>::new(0)
14866    }
14867}
14868pub mod p500pfs_ha {
14869
14870    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14871    pub struct Podr_SPEC;
14872    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
14873    impl Podr {
14874        #[doc = "Output low"]
14875        pub const _0: Self = Self::new(0);
14876
14877        #[doc = "Output high"]
14878        pub const _1: Self = Self::new(1);
14879    }
14880    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14881    pub struct Pidr_SPEC;
14882    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
14883    impl Pidr {
14884        #[doc = "Low level"]
14885        pub const _0: Self = Self::new(0);
14886
14887        #[doc = "High level"]
14888        pub const _1: Self = Self::new(1);
14889    }
14890    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14891    pub struct Pdr_SPEC;
14892    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
14893    impl Pdr {
14894        #[doc = "Input (functions as an input pin)"]
14895        pub const _0: Self = Self::new(0);
14896
14897        #[doc = "Output (functions as an output pin)"]
14898        pub const _1: Self = Self::new(1);
14899    }
14900    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14901    pub struct Pcr_SPEC;
14902    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
14903    impl Pcr {
14904        #[doc = "Disable input pull-up"]
14905        pub const _0: Self = Self::new(0);
14906
14907        #[doc = "Enable input pull-up"]
14908        pub const _1: Self = Self::new(1);
14909    }
14910    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14911    pub struct Ncodr_SPEC;
14912    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
14913    impl Ncodr {
14914        #[doc = "Output CMOS"]
14915        pub const _0: Self = Self::new(0);
14916
14917        #[doc = "Output NMOS open-drain"]
14918        pub const _1: Self = Self::new(1);
14919    }
14920    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14921    pub struct Dscr_SPEC;
14922    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
14923    impl Dscr {
14924        #[doc = "Low drive"]
14925        pub const _00: Self = Self::new(0);
14926
14927        #[doc = "Middle drive"]
14928        pub const _01: Self = Self::new(1);
14929
14930        #[doc = "Setting prohibited"]
14931        pub const _10: Self = Self::new(2);
14932
14933        #[doc = "High drive"]
14934        pub const _11: Self = Self::new(3);
14935    }
14936    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14937    pub struct Eofr_SPEC;
14938    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
14939    impl Eofr {
14940        #[doc = "Don\'t care"]
14941        pub const _00: Self = Self::new(0);
14942
14943        #[doc = "Detect rising edge"]
14944        pub const _01: Self = Self::new(1);
14945
14946        #[doc = "Detect falling edge"]
14947        pub const _10: Self = Self::new(2);
14948
14949        #[doc = "Detect both edges"]
14950        pub const _11: Self = Self::new(3);
14951    }
14952    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14953    pub struct Isel_SPEC;
14954    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
14955    impl Isel {
14956        #[doc = "Do not use as IRQn input pin"]
14957        pub const _0: Self = Self::new(0);
14958
14959        #[doc = "Use as IRQn input pin"]
14960        pub const _1: Self = Self::new(1);
14961    }
14962    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
14963    pub struct Asel_SPEC;
14964    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
14965    impl Asel {
14966        #[doc = "Do not use as analog pin"]
14967        pub const _0: Self = Self::new(0);
14968
14969        #[doc = "Use as analog pin"]
14970        pub const _1: Self = Self::new(1);
14971    }
14972}
14973#[doc(hidden)]
14974#[derive(Copy, Clone, Eq, PartialEq)]
14975pub struct P500PfsBy_SPEC;
14976impl crate::sealed::RegSpec for P500PfsBy_SPEC {
14977    type DataType = u8;
14978}
14979
14980#[doc = "Port 500 Pin Function Select Register"]
14981pub type P500PfsBy = crate::RegValueT<P500PfsBy_SPEC>;
14982
14983impl P500PfsBy {
14984    #[doc = "Port Output Data"]
14985    #[inline(always)]
14986    pub fn podr(
14987        self,
14988    ) -> crate::common::RegisterField<
14989        0,
14990        0x1,
14991        1,
14992        0,
14993        p500pfs_by::Podr,
14994        p500pfs_by::Podr,
14995        P500PfsBy_SPEC,
14996        crate::common::RW,
14997    > {
14998        crate::common::RegisterField::<
14999            0,
15000            0x1,
15001            1,
15002            0,
15003            p500pfs_by::Podr,
15004            p500pfs_by::Podr,
15005            P500PfsBy_SPEC,
15006            crate::common::RW,
15007        >::from_register(self, 0)
15008    }
15009
15010    #[doc = "Port State"]
15011    #[inline(always)]
15012    pub fn pidr(
15013        self,
15014    ) -> crate::common::RegisterField<
15015        1,
15016        0x1,
15017        1,
15018        0,
15019        p500pfs_by::Pidr,
15020        p500pfs_by::Pidr,
15021        P500PfsBy_SPEC,
15022        crate::common::R,
15023    > {
15024        crate::common::RegisterField::<
15025            1,
15026            0x1,
15027            1,
15028            0,
15029            p500pfs_by::Pidr,
15030            p500pfs_by::Pidr,
15031            P500PfsBy_SPEC,
15032            crate::common::R,
15033        >::from_register(self, 0)
15034    }
15035
15036    #[doc = "Port Direction"]
15037    #[inline(always)]
15038    pub fn pdr(
15039        self,
15040    ) -> crate::common::RegisterField<
15041        2,
15042        0x1,
15043        1,
15044        0,
15045        p500pfs_by::Pdr,
15046        p500pfs_by::Pdr,
15047        P500PfsBy_SPEC,
15048        crate::common::RW,
15049    > {
15050        crate::common::RegisterField::<
15051            2,
15052            0x1,
15053            1,
15054            0,
15055            p500pfs_by::Pdr,
15056            p500pfs_by::Pdr,
15057            P500PfsBy_SPEC,
15058            crate::common::RW,
15059        >::from_register(self, 0)
15060    }
15061
15062    #[doc = "Pull-up Control"]
15063    #[inline(always)]
15064    pub fn pcr(
15065        self,
15066    ) -> crate::common::RegisterField<
15067        4,
15068        0x1,
15069        1,
15070        0,
15071        p500pfs_by::Pcr,
15072        p500pfs_by::Pcr,
15073        P500PfsBy_SPEC,
15074        crate::common::RW,
15075    > {
15076        crate::common::RegisterField::<
15077            4,
15078            0x1,
15079            1,
15080            0,
15081            p500pfs_by::Pcr,
15082            p500pfs_by::Pcr,
15083            P500PfsBy_SPEC,
15084            crate::common::RW,
15085        >::from_register(self, 0)
15086    }
15087
15088    #[doc = "N-Channel Open-Drain Control"]
15089    #[inline(always)]
15090    pub fn ncodr(
15091        self,
15092    ) -> crate::common::RegisterField<
15093        6,
15094        0x1,
15095        1,
15096        0,
15097        p500pfs_by::Ncodr,
15098        p500pfs_by::Ncodr,
15099        P500PfsBy_SPEC,
15100        crate::common::RW,
15101    > {
15102        crate::common::RegisterField::<
15103            6,
15104            0x1,
15105            1,
15106            0,
15107            p500pfs_by::Ncodr,
15108            p500pfs_by::Ncodr,
15109            P500PfsBy_SPEC,
15110            crate::common::RW,
15111        >::from_register(self, 0)
15112    }
15113}
15114impl ::core::default::Default for P500PfsBy {
15115    #[inline(always)]
15116    fn default() -> P500PfsBy {
15117        <crate::RegValueT<P500PfsBy_SPEC> as RegisterValue<_>>::new(0)
15118    }
15119}
15120pub mod p500pfs_by {
15121
15122    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15123    pub struct Podr_SPEC;
15124    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
15125    impl Podr {
15126        #[doc = "Output low"]
15127        pub const _0: Self = Self::new(0);
15128
15129        #[doc = "Output high"]
15130        pub const _1: Self = Self::new(1);
15131    }
15132    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15133    pub struct Pidr_SPEC;
15134    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
15135    impl Pidr {
15136        #[doc = "Low level"]
15137        pub const _0: Self = Self::new(0);
15138
15139        #[doc = "High level"]
15140        pub const _1: Self = Self::new(1);
15141    }
15142    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15143    pub struct Pdr_SPEC;
15144    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
15145    impl Pdr {
15146        #[doc = "Input (functions as an input pin)"]
15147        pub const _0: Self = Self::new(0);
15148
15149        #[doc = "Output (functions as an output pin)"]
15150        pub const _1: Self = Self::new(1);
15151    }
15152    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15153    pub struct Pcr_SPEC;
15154    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
15155    impl Pcr {
15156        #[doc = "Disable input pull-up"]
15157        pub const _0: Self = Self::new(0);
15158
15159        #[doc = "Enable input pull-up"]
15160        pub const _1: Self = Self::new(1);
15161    }
15162    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15163    pub struct Ncodr_SPEC;
15164    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
15165    impl Ncodr {
15166        #[doc = "Output CMOS"]
15167        pub const _0: Self = Self::new(0);
15168
15169        #[doc = "Output NMOS open-drain"]
15170        pub const _1: Self = Self::new(1);
15171    }
15172}
15173#[doc(hidden)]
15174#[derive(Copy, Clone, Eq, PartialEq)]
15175pub struct P80Pfs_SPEC;
15176impl crate::sealed::RegSpec for P80Pfs_SPEC {
15177    type DataType = u32;
15178}
15179
15180#[doc = "Port 80%s Pin Function Select Register"]
15181pub type P80Pfs = crate::RegValueT<P80Pfs_SPEC>;
15182
15183impl P80Pfs {
15184    #[doc = "Port Output Data"]
15185    #[inline(always)]
15186    pub fn podr(
15187        self,
15188    ) -> crate::common::RegisterField<
15189        0,
15190        0x1,
15191        1,
15192        0,
15193        p80pfs::Podr,
15194        p80pfs::Podr,
15195        P80Pfs_SPEC,
15196        crate::common::RW,
15197    > {
15198        crate::common::RegisterField::<
15199            0,
15200            0x1,
15201            1,
15202            0,
15203            p80pfs::Podr,
15204            p80pfs::Podr,
15205            P80Pfs_SPEC,
15206            crate::common::RW,
15207        >::from_register(self, 0)
15208    }
15209
15210    #[doc = "Port State"]
15211    #[inline(always)]
15212    pub fn pidr(
15213        self,
15214    ) -> crate::common::RegisterField<
15215        1,
15216        0x1,
15217        1,
15218        0,
15219        p80pfs::Pidr,
15220        p80pfs::Pidr,
15221        P80Pfs_SPEC,
15222        crate::common::R,
15223    > {
15224        crate::common::RegisterField::<
15225            1,
15226            0x1,
15227            1,
15228            0,
15229            p80pfs::Pidr,
15230            p80pfs::Pidr,
15231            P80Pfs_SPEC,
15232            crate::common::R,
15233        >::from_register(self, 0)
15234    }
15235
15236    #[doc = "Port Direction"]
15237    #[inline(always)]
15238    pub fn pdr(
15239        self,
15240    ) -> crate::common::RegisterField<
15241        2,
15242        0x1,
15243        1,
15244        0,
15245        p80pfs::Pdr,
15246        p80pfs::Pdr,
15247        P80Pfs_SPEC,
15248        crate::common::RW,
15249    > {
15250        crate::common::RegisterField::<
15251            2,
15252            0x1,
15253            1,
15254            0,
15255            p80pfs::Pdr,
15256            p80pfs::Pdr,
15257            P80Pfs_SPEC,
15258            crate::common::RW,
15259        >::from_register(self, 0)
15260    }
15261
15262    #[doc = "Pull-up Control"]
15263    #[inline(always)]
15264    pub fn pcr(
15265        self,
15266    ) -> crate::common::RegisterField<
15267        4,
15268        0x1,
15269        1,
15270        0,
15271        p80pfs::Pcr,
15272        p80pfs::Pcr,
15273        P80Pfs_SPEC,
15274        crate::common::RW,
15275    > {
15276        crate::common::RegisterField::<
15277            4,
15278            0x1,
15279            1,
15280            0,
15281            p80pfs::Pcr,
15282            p80pfs::Pcr,
15283            P80Pfs_SPEC,
15284            crate::common::RW,
15285        >::from_register(self, 0)
15286    }
15287
15288    #[doc = "N-Channel Open-Drain Control"]
15289    #[inline(always)]
15290    pub fn ncodr(
15291        self,
15292    ) -> crate::common::RegisterField<
15293        6,
15294        0x1,
15295        1,
15296        0,
15297        p80pfs::Ncodr,
15298        p80pfs::Ncodr,
15299        P80Pfs_SPEC,
15300        crate::common::RW,
15301    > {
15302        crate::common::RegisterField::<
15303            6,
15304            0x1,
15305            1,
15306            0,
15307            p80pfs::Ncodr,
15308            p80pfs::Ncodr,
15309            P80Pfs_SPEC,
15310            crate::common::RW,
15311        >::from_register(self, 0)
15312    }
15313
15314    #[doc = "Port Drive Capability"]
15315    #[inline(always)]
15316    pub fn dscr(
15317        self,
15318    ) -> crate::common::RegisterField<
15319        10,
15320        0x3,
15321        1,
15322        0,
15323        p80pfs::Dscr,
15324        p80pfs::Dscr,
15325        P80Pfs_SPEC,
15326        crate::common::RW,
15327    > {
15328        crate::common::RegisterField::<
15329            10,
15330            0x3,
15331            1,
15332            0,
15333            p80pfs::Dscr,
15334            p80pfs::Dscr,
15335            P80Pfs_SPEC,
15336            crate::common::RW,
15337        >::from_register(self, 0)
15338    }
15339
15340    #[doc = "Event on Falling/Event on Rising"]
15341    #[inline(always)]
15342    pub fn eofr(
15343        self,
15344    ) -> crate::common::RegisterField<
15345        12,
15346        0x3,
15347        1,
15348        0,
15349        p80pfs::Eofr,
15350        p80pfs::Eofr,
15351        P80Pfs_SPEC,
15352        crate::common::RW,
15353    > {
15354        crate::common::RegisterField::<
15355            12,
15356            0x3,
15357            1,
15358            0,
15359            p80pfs::Eofr,
15360            p80pfs::Eofr,
15361            P80Pfs_SPEC,
15362            crate::common::RW,
15363        >::from_register(self, 0)
15364    }
15365
15366    #[doc = "IRQ Input Enable"]
15367    #[inline(always)]
15368    pub fn isel(
15369        self,
15370    ) -> crate::common::RegisterField<
15371        14,
15372        0x1,
15373        1,
15374        0,
15375        p80pfs::Isel,
15376        p80pfs::Isel,
15377        P80Pfs_SPEC,
15378        crate::common::RW,
15379    > {
15380        crate::common::RegisterField::<
15381            14,
15382            0x1,
15383            1,
15384            0,
15385            p80pfs::Isel,
15386            p80pfs::Isel,
15387            P80Pfs_SPEC,
15388            crate::common::RW,
15389        >::from_register(self, 0)
15390    }
15391
15392    #[doc = "Analog Input Enable"]
15393    #[inline(always)]
15394    pub fn asel(
15395        self,
15396    ) -> crate::common::RegisterField<
15397        15,
15398        0x1,
15399        1,
15400        0,
15401        p80pfs::Asel,
15402        p80pfs::Asel,
15403        P80Pfs_SPEC,
15404        crate::common::RW,
15405    > {
15406        crate::common::RegisterField::<
15407            15,
15408            0x1,
15409            1,
15410            0,
15411            p80pfs::Asel,
15412            p80pfs::Asel,
15413            P80Pfs_SPEC,
15414            crate::common::RW,
15415        >::from_register(self, 0)
15416    }
15417
15418    #[doc = "Port Mode Control"]
15419    #[inline(always)]
15420    pub fn pmr(
15421        self,
15422    ) -> crate::common::RegisterField<
15423        16,
15424        0x1,
15425        1,
15426        0,
15427        p80pfs::Pmr,
15428        p80pfs::Pmr,
15429        P80Pfs_SPEC,
15430        crate::common::RW,
15431    > {
15432        crate::common::RegisterField::<
15433            16,
15434            0x1,
15435            1,
15436            0,
15437            p80pfs::Pmr,
15438            p80pfs::Pmr,
15439            P80Pfs_SPEC,
15440            crate::common::RW,
15441        >::from_register(self, 0)
15442    }
15443
15444    #[doc = "Peripheral Select"]
15445    #[inline(always)]
15446    pub fn psel(
15447        self,
15448    ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P80Pfs_SPEC, crate::common::RW> {
15449        crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P80Pfs_SPEC,crate::common::RW>::from_register(self,0)
15450    }
15451}
15452impl ::core::default::Default for P80Pfs {
15453    #[inline(always)]
15454    fn default() -> P80Pfs {
15455        <crate::RegValueT<P80Pfs_SPEC> as RegisterValue<_>>::new(0)
15456    }
15457}
15458pub mod p80pfs {
15459
15460    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15461    pub struct Podr_SPEC;
15462    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
15463    impl Podr {
15464        #[doc = "Output low"]
15465        pub const _0: Self = Self::new(0);
15466
15467        #[doc = "Output high"]
15468        pub const _1: Self = Self::new(1);
15469    }
15470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15471    pub struct Pidr_SPEC;
15472    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
15473    impl Pidr {
15474        #[doc = "Low level"]
15475        pub const _0: Self = Self::new(0);
15476
15477        #[doc = "High level"]
15478        pub const _1: Self = Self::new(1);
15479    }
15480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15481    pub struct Pdr_SPEC;
15482    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
15483    impl Pdr {
15484        #[doc = "Input (functions as an input pin)"]
15485        pub const _0: Self = Self::new(0);
15486
15487        #[doc = "Output (functions as an output pin)"]
15488        pub const _1: Self = Self::new(1);
15489    }
15490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15491    pub struct Pcr_SPEC;
15492    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
15493    impl Pcr {
15494        #[doc = "Disable input pull-up"]
15495        pub const _0: Self = Self::new(0);
15496
15497        #[doc = "Enable input pull-up"]
15498        pub const _1: Self = Self::new(1);
15499    }
15500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15501    pub struct Ncodr_SPEC;
15502    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
15503    impl Ncodr {
15504        #[doc = "Output CMOS"]
15505        pub const _0: Self = Self::new(0);
15506
15507        #[doc = "Output NMOS open-drain"]
15508        pub const _1: Self = Self::new(1);
15509    }
15510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15511    pub struct Dscr_SPEC;
15512    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
15513    impl Dscr {
15514        #[doc = "Low drive"]
15515        pub const _00: Self = Self::new(0);
15516
15517        #[doc = "Middle drive"]
15518        pub const _01: Self = Self::new(1);
15519
15520        #[doc = "Setting prohibited"]
15521        pub const _10: Self = Self::new(2);
15522
15523        #[doc = "High drive"]
15524        pub const _11: Self = Self::new(3);
15525    }
15526    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15527    pub struct Eofr_SPEC;
15528    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
15529    impl Eofr {
15530        #[doc = "Don\'t care"]
15531        pub const _00: Self = Self::new(0);
15532
15533        #[doc = "Detect rising edge"]
15534        pub const _01: Self = Self::new(1);
15535
15536        #[doc = "Detect falling edge"]
15537        pub const _10: Self = Self::new(2);
15538
15539        #[doc = "Detect both edges"]
15540        pub const _11: Self = Self::new(3);
15541    }
15542    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15543    pub struct Isel_SPEC;
15544    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
15545    impl Isel {
15546        #[doc = "Do not use as IRQn input pin"]
15547        pub const _0: Self = Self::new(0);
15548
15549        #[doc = "Use as IRQn input pin"]
15550        pub const _1: Self = Self::new(1);
15551    }
15552    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15553    pub struct Asel_SPEC;
15554    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
15555    impl Asel {
15556        #[doc = "Do not use as analog pin"]
15557        pub const _0: Self = Self::new(0);
15558
15559        #[doc = "Use as analog pin"]
15560        pub const _1: Self = Self::new(1);
15561    }
15562    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15563    pub struct Pmr_SPEC;
15564    pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
15565    impl Pmr {
15566        #[doc = "Use as general I/O pin"]
15567        pub const _0: Self = Self::new(0);
15568
15569        #[doc = "Use as I/O port for peripheral functions"]
15570        pub const _1: Self = Self::new(1);
15571    }
15572}
15573#[doc(hidden)]
15574#[derive(Copy, Clone, Eq, PartialEq)]
15575pub struct P80PfsHa_SPEC;
15576impl crate::sealed::RegSpec for P80PfsHa_SPEC {
15577    type DataType = u16;
15578}
15579
15580#[doc = "Port 80%s Pin Function Select Register"]
15581pub type P80PfsHa = crate::RegValueT<P80PfsHa_SPEC>;
15582
15583impl P80PfsHa {
15584    #[doc = "Port Output Data"]
15585    #[inline(always)]
15586    pub fn podr(
15587        self,
15588    ) -> crate::common::RegisterField<
15589        0,
15590        0x1,
15591        1,
15592        0,
15593        p80pfs_ha::Podr,
15594        p80pfs_ha::Podr,
15595        P80PfsHa_SPEC,
15596        crate::common::RW,
15597    > {
15598        crate::common::RegisterField::<
15599            0,
15600            0x1,
15601            1,
15602            0,
15603            p80pfs_ha::Podr,
15604            p80pfs_ha::Podr,
15605            P80PfsHa_SPEC,
15606            crate::common::RW,
15607        >::from_register(self, 0)
15608    }
15609
15610    #[doc = "Port State"]
15611    #[inline(always)]
15612    pub fn pidr(
15613        self,
15614    ) -> crate::common::RegisterField<
15615        1,
15616        0x1,
15617        1,
15618        0,
15619        p80pfs_ha::Pidr,
15620        p80pfs_ha::Pidr,
15621        P80PfsHa_SPEC,
15622        crate::common::R,
15623    > {
15624        crate::common::RegisterField::<
15625            1,
15626            0x1,
15627            1,
15628            0,
15629            p80pfs_ha::Pidr,
15630            p80pfs_ha::Pidr,
15631            P80PfsHa_SPEC,
15632            crate::common::R,
15633        >::from_register(self, 0)
15634    }
15635
15636    #[doc = "Port Direction"]
15637    #[inline(always)]
15638    pub fn pdr(
15639        self,
15640    ) -> crate::common::RegisterField<
15641        2,
15642        0x1,
15643        1,
15644        0,
15645        p80pfs_ha::Pdr,
15646        p80pfs_ha::Pdr,
15647        P80PfsHa_SPEC,
15648        crate::common::RW,
15649    > {
15650        crate::common::RegisterField::<
15651            2,
15652            0x1,
15653            1,
15654            0,
15655            p80pfs_ha::Pdr,
15656            p80pfs_ha::Pdr,
15657            P80PfsHa_SPEC,
15658            crate::common::RW,
15659        >::from_register(self, 0)
15660    }
15661
15662    #[doc = "Pull-up Control"]
15663    #[inline(always)]
15664    pub fn pcr(
15665        self,
15666    ) -> crate::common::RegisterField<
15667        4,
15668        0x1,
15669        1,
15670        0,
15671        p80pfs_ha::Pcr,
15672        p80pfs_ha::Pcr,
15673        P80PfsHa_SPEC,
15674        crate::common::RW,
15675    > {
15676        crate::common::RegisterField::<
15677            4,
15678            0x1,
15679            1,
15680            0,
15681            p80pfs_ha::Pcr,
15682            p80pfs_ha::Pcr,
15683            P80PfsHa_SPEC,
15684            crate::common::RW,
15685        >::from_register(self, 0)
15686    }
15687
15688    #[doc = "N-Channel Open-Drain Control"]
15689    #[inline(always)]
15690    pub fn ncodr(
15691        self,
15692    ) -> crate::common::RegisterField<
15693        6,
15694        0x1,
15695        1,
15696        0,
15697        p80pfs_ha::Ncodr,
15698        p80pfs_ha::Ncodr,
15699        P80PfsHa_SPEC,
15700        crate::common::RW,
15701    > {
15702        crate::common::RegisterField::<
15703            6,
15704            0x1,
15705            1,
15706            0,
15707            p80pfs_ha::Ncodr,
15708            p80pfs_ha::Ncodr,
15709            P80PfsHa_SPEC,
15710            crate::common::RW,
15711        >::from_register(self, 0)
15712    }
15713
15714    #[doc = "Port Drive Capability"]
15715    #[inline(always)]
15716    pub fn dscr(
15717        self,
15718    ) -> crate::common::RegisterField<
15719        10,
15720        0x3,
15721        1,
15722        0,
15723        p80pfs_ha::Dscr,
15724        p80pfs_ha::Dscr,
15725        P80PfsHa_SPEC,
15726        crate::common::RW,
15727    > {
15728        crate::common::RegisterField::<
15729            10,
15730            0x3,
15731            1,
15732            0,
15733            p80pfs_ha::Dscr,
15734            p80pfs_ha::Dscr,
15735            P80PfsHa_SPEC,
15736            crate::common::RW,
15737        >::from_register(self, 0)
15738    }
15739
15740    #[doc = "Event on Falling/Event on Rising"]
15741    #[inline(always)]
15742    pub fn eofr(
15743        self,
15744    ) -> crate::common::RegisterField<
15745        12,
15746        0x3,
15747        1,
15748        0,
15749        p80pfs_ha::Eofr,
15750        p80pfs_ha::Eofr,
15751        P80PfsHa_SPEC,
15752        crate::common::RW,
15753    > {
15754        crate::common::RegisterField::<
15755            12,
15756            0x3,
15757            1,
15758            0,
15759            p80pfs_ha::Eofr,
15760            p80pfs_ha::Eofr,
15761            P80PfsHa_SPEC,
15762            crate::common::RW,
15763        >::from_register(self, 0)
15764    }
15765
15766    #[doc = "IRQ Input Enable"]
15767    #[inline(always)]
15768    pub fn isel(
15769        self,
15770    ) -> crate::common::RegisterField<
15771        14,
15772        0x1,
15773        1,
15774        0,
15775        p80pfs_ha::Isel,
15776        p80pfs_ha::Isel,
15777        P80PfsHa_SPEC,
15778        crate::common::RW,
15779    > {
15780        crate::common::RegisterField::<
15781            14,
15782            0x1,
15783            1,
15784            0,
15785            p80pfs_ha::Isel,
15786            p80pfs_ha::Isel,
15787            P80PfsHa_SPEC,
15788            crate::common::RW,
15789        >::from_register(self, 0)
15790    }
15791
15792    #[doc = "Analog Input Enable"]
15793    #[inline(always)]
15794    pub fn asel(
15795        self,
15796    ) -> crate::common::RegisterField<
15797        15,
15798        0x1,
15799        1,
15800        0,
15801        p80pfs_ha::Asel,
15802        p80pfs_ha::Asel,
15803        P80PfsHa_SPEC,
15804        crate::common::RW,
15805    > {
15806        crate::common::RegisterField::<
15807            15,
15808            0x1,
15809            1,
15810            0,
15811            p80pfs_ha::Asel,
15812            p80pfs_ha::Asel,
15813            P80PfsHa_SPEC,
15814            crate::common::RW,
15815        >::from_register(self, 0)
15816    }
15817}
15818impl ::core::default::Default for P80PfsHa {
15819    #[inline(always)]
15820    fn default() -> P80PfsHa {
15821        <crate::RegValueT<P80PfsHa_SPEC> as RegisterValue<_>>::new(0)
15822    }
15823}
15824pub mod p80pfs_ha {
15825
15826    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15827    pub struct Podr_SPEC;
15828    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
15829    impl Podr {
15830        #[doc = "Output low"]
15831        pub const _0: Self = Self::new(0);
15832
15833        #[doc = "Output high"]
15834        pub const _1: Self = Self::new(1);
15835    }
15836    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15837    pub struct Pidr_SPEC;
15838    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
15839    impl Pidr {
15840        #[doc = "Low level"]
15841        pub const _0: Self = Self::new(0);
15842
15843        #[doc = "High level"]
15844        pub const _1: Self = Self::new(1);
15845    }
15846    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15847    pub struct Pdr_SPEC;
15848    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
15849    impl Pdr {
15850        #[doc = "Input (functions as an input pin)"]
15851        pub const _0: Self = Self::new(0);
15852
15853        #[doc = "Output (functions as an output pin)"]
15854        pub const _1: Self = Self::new(1);
15855    }
15856    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15857    pub struct Pcr_SPEC;
15858    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
15859    impl Pcr {
15860        #[doc = "Disable input pull-up"]
15861        pub const _0: Self = Self::new(0);
15862
15863        #[doc = "Enable input pull-up"]
15864        pub const _1: Self = Self::new(1);
15865    }
15866    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15867    pub struct Ncodr_SPEC;
15868    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
15869    impl Ncodr {
15870        #[doc = "Output CMOS"]
15871        pub const _0: Self = Self::new(0);
15872
15873        #[doc = "Output NMOS open-drain"]
15874        pub const _1: Self = Self::new(1);
15875    }
15876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15877    pub struct Dscr_SPEC;
15878    pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
15879    impl Dscr {
15880        #[doc = "Low drive"]
15881        pub const _00: Self = Self::new(0);
15882
15883        #[doc = "Middle drive"]
15884        pub const _01: Self = Self::new(1);
15885
15886        #[doc = "Setting prohibited"]
15887        pub const _10: Self = Self::new(2);
15888
15889        #[doc = "High drive"]
15890        pub const _11: Self = Self::new(3);
15891    }
15892    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15893    pub struct Eofr_SPEC;
15894    pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
15895    impl Eofr {
15896        #[doc = "Don\'t care"]
15897        pub const _00: Self = Self::new(0);
15898
15899        #[doc = "Detect rising edge"]
15900        pub const _01: Self = Self::new(1);
15901
15902        #[doc = "Detect falling edge"]
15903        pub const _10: Self = Self::new(2);
15904
15905        #[doc = "Detect both edges"]
15906        pub const _11: Self = Self::new(3);
15907    }
15908    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15909    pub struct Isel_SPEC;
15910    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
15911    impl Isel {
15912        #[doc = "Do not use as IRQn input pin"]
15913        pub const _0: Self = Self::new(0);
15914
15915        #[doc = "Use as IRQn input pin"]
15916        pub const _1: Self = Self::new(1);
15917    }
15918    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
15919    pub struct Asel_SPEC;
15920    pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
15921    impl Asel {
15922        #[doc = "Do not use as analog pin"]
15923        pub const _0: Self = Self::new(0);
15924
15925        #[doc = "Use as analog pin"]
15926        pub const _1: Self = Self::new(1);
15927    }
15928}
15929#[doc(hidden)]
15930#[derive(Copy, Clone, Eq, PartialEq)]
15931pub struct P80PfsBy_SPEC;
15932impl crate::sealed::RegSpec for P80PfsBy_SPEC {
15933    type DataType = u8;
15934}
15935
15936#[doc = "Port 80%s Pin Function Select Register"]
15937pub type P80PfsBy = crate::RegValueT<P80PfsBy_SPEC>;
15938
15939impl P80PfsBy {
15940    #[doc = "Port Output Data"]
15941    #[inline(always)]
15942    pub fn podr(
15943        self,
15944    ) -> crate::common::RegisterField<
15945        0,
15946        0x1,
15947        1,
15948        0,
15949        p80pfs_by::Podr,
15950        p80pfs_by::Podr,
15951        P80PfsBy_SPEC,
15952        crate::common::RW,
15953    > {
15954        crate::common::RegisterField::<
15955            0,
15956            0x1,
15957            1,
15958            0,
15959            p80pfs_by::Podr,
15960            p80pfs_by::Podr,
15961            P80PfsBy_SPEC,
15962            crate::common::RW,
15963        >::from_register(self, 0)
15964    }
15965
15966    #[doc = "Port State"]
15967    #[inline(always)]
15968    pub fn pidr(
15969        self,
15970    ) -> crate::common::RegisterField<
15971        1,
15972        0x1,
15973        1,
15974        0,
15975        p80pfs_by::Pidr,
15976        p80pfs_by::Pidr,
15977        P80PfsBy_SPEC,
15978        crate::common::R,
15979    > {
15980        crate::common::RegisterField::<
15981            1,
15982            0x1,
15983            1,
15984            0,
15985            p80pfs_by::Pidr,
15986            p80pfs_by::Pidr,
15987            P80PfsBy_SPEC,
15988            crate::common::R,
15989        >::from_register(self, 0)
15990    }
15991
15992    #[doc = "Port Direction"]
15993    #[inline(always)]
15994    pub fn pdr(
15995        self,
15996    ) -> crate::common::RegisterField<
15997        2,
15998        0x1,
15999        1,
16000        0,
16001        p80pfs_by::Pdr,
16002        p80pfs_by::Pdr,
16003        P80PfsBy_SPEC,
16004        crate::common::RW,
16005    > {
16006        crate::common::RegisterField::<
16007            2,
16008            0x1,
16009            1,
16010            0,
16011            p80pfs_by::Pdr,
16012            p80pfs_by::Pdr,
16013            P80PfsBy_SPEC,
16014            crate::common::RW,
16015        >::from_register(self, 0)
16016    }
16017
16018    #[doc = "Pull-up Control"]
16019    #[inline(always)]
16020    pub fn pcr(
16021        self,
16022    ) -> crate::common::RegisterField<
16023        4,
16024        0x1,
16025        1,
16026        0,
16027        p80pfs_by::Pcr,
16028        p80pfs_by::Pcr,
16029        P80PfsBy_SPEC,
16030        crate::common::RW,
16031    > {
16032        crate::common::RegisterField::<
16033            4,
16034            0x1,
16035            1,
16036            0,
16037            p80pfs_by::Pcr,
16038            p80pfs_by::Pcr,
16039            P80PfsBy_SPEC,
16040            crate::common::RW,
16041        >::from_register(self, 0)
16042    }
16043
16044    #[doc = "N-Channel Open-Drain Control"]
16045    #[inline(always)]
16046    pub fn ncodr(
16047        self,
16048    ) -> crate::common::RegisterField<
16049        6,
16050        0x1,
16051        1,
16052        0,
16053        p80pfs_by::Ncodr,
16054        p80pfs_by::Ncodr,
16055        P80PfsBy_SPEC,
16056        crate::common::RW,
16057    > {
16058        crate::common::RegisterField::<
16059            6,
16060            0x1,
16061            1,
16062            0,
16063            p80pfs_by::Ncodr,
16064            p80pfs_by::Ncodr,
16065            P80PfsBy_SPEC,
16066            crate::common::RW,
16067        >::from_register(self, 0)
16068    }
16069}
16070impl ::core::default::Default for P80PfsBy {
16071    #[inline(always)]
16072    fn default() -> P80PfsBy {
16073        <crate::RegValueT<P80PfsBy_SPEC> as RegisterValue<_>>::new(0)
16074    }
16075}
16076pub mod p80pfs_by {
16077
16078    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16079    pub struct Podr_SPEC;
16080    pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
16081    impl Podr {
16082        #[doc = "Output low"]
16083        pub const _0: Self = Self::new(0);
16084
16085        #[doc = "Output high"]
16086        pub const _1: Self = Self::new(1);
16087    }
16088    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16089    pub struct Pidr_SPEC;
16090    pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
16091    impl Pidr {
16092        #[doc = "Low level"]
16093        pub const _0: Self = Self::new(0);
16094
16095        #[doc = "High level"]
16096        pub const _1: Self = Self::new(1);
16097    }
16098    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16099    pub struct Pdr_SPEC;
16100    pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
16101    impl Pdr {
16102        #[doc = "Input (functions as an input pin)"]
16103        pub const _0: Self = Self::new(0);
16104
16105        #[doc = "Output (functions as an output pin)"]
16106        pub const _1: Self = Self::new(1);
16107    }
16108    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16109    pub struct Pcr_SPEC;
16110    pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
16111    impl Pcr {
16112        #[doc = "Disable input pull-up"]
16113        pub const _0: Self = Self::new(0);
16114
16115        #[doc = "Enable input pull-up"]
16116        pub const _1: Self = Self::new(1);
16117    }
16118    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16119    pub struct Ncodr_SPEC;
16120    pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
16121    impl Ncodr {
16122        #[doc = "Output CMOS"]
16123        pub const _0: Self = Self::new(0);
16124
16125        #[doc = "Output NMOS open-drain"]
16126        pub const _1: Self = Self::new(1);
16127    }
16128}
16129#[doc(hidden)]
16130#[derive(Copy, Clone, Eq, PartialEq)]
16131pub struct Pwpr_SPEC;
16132impl crate::sealed::RegSpec for Pwpr_SPEC {
16133    type DataType = u8;
16134}
16135
16136#[doc = "Write-Protect Register"]
16137pub type Pwpr = crate::RegValueT<Pwpr_SPEC>;
16138
16139impl Pwpr {
16140    #[doc = "PmnPFS Register Write Enable"]
16141    #[inline(always)]
16142    pub fn pfswe(
16143        self,
16144    ) -> crate::common::RegisterField<
16145        6,
16146        0x1,
16147        1,
16148        0,
16149        pwpr::Pfswe,
16150        pwpr::Pfswe,
16151        Pwpr_SPEC,
16152        crate::common::RW,
16153    > {
16154        crate::common::RegisterField::<
16155            6,
16156            0x1,
16157            1,
16158            0,
16159            pwpr::Pfswe,
16160            pwpr::Pfswe,
16161            Pwpr_SPEC,
16162            crate::common::RW,
16163        >::from_register(self, 0)
16164    }
16165
16166    #[doc = "PFSWE Bit Write Disable"]
16167    #[inline(always)]
16168    pub fn b0wi(
16169        self,
16170    ) -> crate::common::RegisterField<
16171        7,
16172        0x1,
16173        1,
16174        0,
16175        pwpr::B0Wi,
16176        pwpr::B0Wi,
16177        Pwpr_SPEC,
16178        crate::common::RW,
16179    > {
16180        crate::common::RegisterField::<
16181            7,
16182            0x1,
16183            1,
16184            0,
16185            pwpr::B0Wi,
16186            pwpr::B0Wi,
16187            Pwpr_SPEC,
16188            crate::common::RW,
16189        >::from_register(self, 0)
16190    }
16191}
16192impl ::core::default::Default for Pwpr {
16193    #[inline(always)]
16194    fn default() -> Pwpr {
16195        <crate::RegValueT<Pwpr_SPEC> as RegisterValue<_>>::new(128)
16196    }
16197}
16198pub mod pwpr {
16199
16200    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16201    pub struct Pfswe_SPEC;
16202    pub type Pfswe = crate::EnumBitfieldStruct<u8, Pfswe_SPEC>;
16203    impl Pfswe {
16204        #[doc = "Writing to the PmnPFS register is disabled"]
16205        pub const _0: Self = Self::new(0);
16206
16207        #[doc = "Writing to the PmnPFS register is enabled"]
16208        pub const _1: Self = Self::new(1);
16209    }
16210    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16211    pub struct B0Wi_SPEC;
16212    pub type B0Wi = crate::EnumBitfieldStruct<u8, B0Wi_SPEC>;
16213    impl B0Wi {
16214        #[doc = "Writing to the PFSWE bit is enabled"]
16215        pub const _0: Self = Self::new(0);
16216
16217        #[doc = "Writing to the PFSWE bit is disabled"]
16218        pub const _1: Self = Self::new(1);
16219    }
16220}
16221#[doc(hidden)]
16222#[derive(Copy, Clone, Eq, PartialEq)]
16223pub struct Pwprs_SPEC;
16224impl crate::sealed::RegSpec for Pwprs_SPEC {
16225    type DataType = u8;
16226}
16227
16228#[doc = "Write-Protect Register for Secure"]
16229pub type Pwprs = crate::RegValueT<Pwprs_SPEC>;
16230
16231impl Pwprs {
16232    #[doc = "PmnPFS Register Write Enable"]
16233    #[inline(always)]
16234    pub fn pfswe(
16235        self,
16236    ) -> crate::common::RegisterField<
16237        6,
16238        0x1,
16239        1,
16240        0,
16241        pwprs::Pfswe,
16242        pwprs::Pfswe,
16243        Pwprs_SPEC,
16244        crate::common::RW,
16245    > {
16246        crate::common::RegisterField::<
16247            6,
16248            0x1,
16249            1,
16250            0,
16251            pwprs::Pfswe,
16252            pwprs::Pfswe,
16253            Pwprs_SPEC,
16254            crate::common::RW,
16255        >::from_register(self, 0)
16256    }
16257
16258    #[doc = "PFSWE Bit Write Disable"]
16259    #[inline(always)]
16260    pub fn b0wi(
16261        self,
16262    ) -> crate::common::RegisterField<
16263        7,
16264        0x1,
16265        1,
16266        0,
16267        pwprs::B0Wi,
16268        pwprs::B0Wi,
16269        Pwprs_SPEC,
16270        crate::common::RW,
16271    > {
16272        crate::common::RegisterField::<
16273            7,
16274            0x1,
16275            1,
16276            0,
16277            pwprs::B0Wi,
16278            pwprs::B0Wi,
16279            Pwprs_SPEC,
16280            crate::common::RW,
16281        >::from_register(self, 0)
16282    }
16283}
16284impl ::core::default::Default for Pwprs {
16285    #[inline(always)]
16286    fn default() -> Pwprs {
16287        <crate::RegValueT<Pwprs_SPEC> as RegisterValue<_>>::new(128)
16288    }
16289}
16290pub mod pwprs {
16291
16292    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16293    pub struct Pfswe_SPEC;
16294    pub type Pfswe = crate::EnumBitfieldStruct<u8, Pfswe_SPEC>;
16295    impl Pfswe {
16296        #[doc = "Disable writes to the PmnPFS register"]
16297        pub const _0: Self = Self::new(0);
16298
16299        #[doc = "Enable writes to the PmnPFS register"]
16300        pub const _1: Self = Self::new(1);
16301    }
16302    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16303    pub struct B0Wi_SPEC;
16304    pub type B0Wi = crate::EnumBitfieldStruct<u8, B0Wi_SPEC>;
16305    impl B0Wi {
16306        #[doc = "Enable writes the PFSWE bit"]
16307        pub const _0: Self = Self::new(0);
16308
16309        #[doc = "Disable writes to the PFSWE bit"]
16310        pub const _1: Self = Self::new(1);
16311    }
16312}
16313#[doc(hidden)]
16314#[derive(Copy, Clone, Eq, PartialEq)]
16315pub struct Pfi3C_SPEC;
16316impl crate::sealed::RegSpec for Pfi3C_SPEC {
16317    type DataType = u8;
16318}
16319
16320#[doc = "RI3C Slope Control Register"]
16321pub type Pfi3C = crate::RegValueT<Pfi3C_SPEC>;
16322
16323impl Pfi3C {
16324    #[doc = "I3C mode slope control bit"]
16325    #[inline(always)]
16326    pub fn i3cslope0(
16327        self,
16328    ) -> crate::common::RegisterField<
16329        0,
16330        0x1,
16331        1,
16332        0,
16333        pfi3c::I3Cslope0,
16334        pfi3c::I3Cslope0,
16335        Pfi3C_SPEC,
16336        crate::common::RW,
16337    > {
16338        crate::common::RegisterField::<
16339            0,
16340            0x1,
16341            1,
16342            0,
16343            pfi3c::I3Cslope0,
16344            pfi3c::I3Cslope0,
16345            Pfi3C_SPEC,
16346            crate::common::RW,
16347        >::from_register(self, 0)
16348    }
16349}
16350impl ::core::default::Default for Pfi3C {
16351    #[inline(always)]
16352    fn default() -> Pfi3C {
16353        <crate::RegValueT<Pfi3C_SPEC> as RegisterValue<_>>::new(0)
16354    }
16355}
16356pub mod pfi3c {
16357
16358    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16359    pub struct I3Cslope0_SPEC;
16360    pub type I3Cslope0 = crate::EnumBitfieldStruct<u8, I3Cslope0_SPEC>;
16361    impl I3Cslope0 {
16362        #[doc = "I3C mode slope control disable"]
16363        pub const _0: Self = Self::new(0);
16364
16365        #[doc = "I3C mode slope control enable"]
16366        pub const _1: Self = Self::new(1);
16367    }
16368}
16369#[doc(hidden)]
16370#[derive(Copy, Clone, Eq, PartialEq)]
16371pub struct Psar_SPEC;
16372impl crate::sealed::RegSpec for Psar_SPEC {
16373    type DataType = u16;
16374}
16375
16376#[doc = "Port Security Attribution register"]
16377pub type Psar = crate::RegValueT<Psar_SPEC>;
16378
16379impl Psar {
16380    #[doc = "Pmn Security Attribution"]
16381    #[inline(always)]
16382    pub fn pmnsa(
16383        self,
16384    ) -> crate::common::RegisterField<
16385        0,
16386        0xffff,
16387        1,
16388        0,
16389        psar::Pmnsa,
16390        psar::Pmnsa,
16391        Psar_SPEC,
16392        crate::common::RW,
16393    > {
16394        crate::common::RegisterField::<
16395            0,
16396            0xffff,
16397            1,
16398            0,
16399            psar::Pmnsa,
16400            psar::Pmnsa,
16401            Psar_SPEC,
16402            crate::common::RW,
16403        >::from_register(self, 0)
16404    }
16405}
16406impl ::core::default::Default for Psar {
16407    #[inline(always)]
16408    fn default() -> Psar {
16409        <crate::RegValueT<Psar_SPEC> as RegisterValue<_>>::new(65535)
16410    }
16411}
16412pub mod psar {
16413
16414    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16415    pub struct Pmnsa_SPEC;
16416    pub type Pmnsa = crate::EnumBitfieldStruct<u8, Pmnsa_SPEC>;
16417    impl Pmnsa {
16418        #[doc = "Secure"]
16419        pub const _0: Self = Self::new(0);
16420
16421        #[doc = "Non Secure"]
16422        pub const _1: Self = Self::new(1);
16423    }
16424}
16425#[doc(hidden)]
16426#[derive(Copy, Clone, Eq, PartialEq)]
16427pub struct P8Sar_SPEC;
16428impl crate::sealed::RegSpec for P8Sar_SPEC {
16429    type DataType = u16;
16430}
16431
16432#[doc = "Port Security Attribution register"]
16433pub type P8Sar = crate::RegValueT<P8Sar_SPEC>;
16434
16435impl P8Sar {
16436    #[doc = "Pmn Security Attribution"]
16437    #[inline(always)]
16438    pub fn pmnsa(
16439        self,
16440    ) -> crate::common::RegisterField<
16441        0,
16442        0xffff,
16443        1,
16444        0,
16445        p8sar::Pmnsa,
16446        p8sar::Pmnsa,
16447        P8Sar_SPEC,
16448        crate::common::RW,
16449    > {
16450        crate::common::RegisterField::<
16451            0,
16452            0xffff,
16453            1,
16454            0,
16455            p8sar::Pmnsa,
16456            p8sar::Pmnsa,
16457            P8Sar_SPEC,
16458            crate::common::RW,
16459        >::from_register(self, 0)
16460    }
16461}
16462impl ::core::default::Default for P8Sar {
16463    #[inline(always)]
16464    fn default() -> P8Sar {
16465        <crate::RegValueT<P8Sar_SPEC> as RegisterValue<_>>::new(65535)
16466    }
16467}
16468pub mod p8sar {
16469
16470    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
16471    pub struct Pmnsa_SPEC;
16472    pub type Pmnsa = crate::EnumBitfieldStruct<u8, Pmnsa_SPEC>;
16473    impl Pmnsa {
16474        #[doc = "Secure"]
16475        pub const _0: Self = Self::new(0);
16476
16477        #[doc = "Non Secure"]
16478        pub const _1: Self = Self::new(1);
16479    }
16480}
ra4e2_pac/pfs.rs

ra4e2_pac/
pfs.rs
