ra4e2_pac/
usbfs.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.30.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:05:15 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"USB 2.0 Full-Speed Module"]
28unsafe impl ::core::marker::Send for super::Usbfs {}
29unsafe impl ::core::marker::Sync for super::Usbfs {}
30impl super::Usbfs {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "System Configuration Control Register"]
38    #[inline(always)]
39    pub const fn syscfg(
40        &self,
41    ) -> &'static crate::common::Reg<self::Syscfg_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Syscfg_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "System Configuration Status Register 0"]
50    #[inline(always)]
51    pub const fn syssts0(
52        &self,
53    ) -> &'static crate::common::Reg<self::Syssts0_SPEC, crate::common::R> {
54        unsafe {
55            crate::common::Reg::<self::Syssts0_SPEC, crate::common::R>::from_ptr(
56                self._svd2pac_as_ptr().add(4usize),
57            )
58        }
59    }
60
61    #[doc = "Device State Control Register 0"]
62    #[inline(always)]
63    pub const fn dvstctr0(
64        &self,
65    ) -> &'static crate::common::Reg<self::Dvstctr0_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Dvstctr0_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(8usize),
69            )
70        }
71    }
72
73    #[doc = "CFIFO Port Register"]
74    #[inline(always)]
75    pub const fn cfifo(&self) -> &'static crate::common::Reg<self::Cfifo_SPEC, crate::common::RW> {
76        unsafe {
77            crate::common::Reg::<self::Cfifo_SPEC, crate::common::RW>::from_ptr(
78                self._svd2pac_as_ptr().add(20usize),
79            )
80        }
81    }
82
83    #[doc = "CFIFO Port Register"]
84    #[inline(always)]
85    pub const fn cfifol(
86        &self,
87    ) -> &'static crate::common::Reg<self::Cfifol_SPEC, crate::common::RW> {
88        unsafe {
89            crate::common::Reg::<self::Cfifol_SPEC, crate::common::RW>::from_ptr(
90                self._svd2pac_as_ptr().add(20usize),
91            )
92        }
93    }
94
95    #[doc = "CFIFO Port Select Register"]
96    #[inline(always)]
97    pub const fn cfifosel(
98        &self,
99    ) -> &'static crate::common::Reg<self::Cfifosel_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Cfifosel_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(32usize),
103            )
104        }
105    }
106
107    #[doc = "CFIFO Port Control Register"]
108    #[inline(always)]
109    pub const fn cfifoctr(
110        &self,
111    ) -> &'static crate::common::Reg<self::Cfifoctr_SPEC, crate::common::RW> {
112        unsafe {
113            crate::common::Reg::<self::Cfifoctr_SPEC, crate::common::RW>::from_ptr(
114                self._svd2pac_as_ptr().add(34usize),
115            )
116        }
117    }
118
119    #[doc = "Interrupt Enable Register 0"]
120    #[inline(always)]
121    pub const fn intenb0(
122        &self,
123    ) -> &'static crate::common::Reg<self::Intenb0_SPEC, crate::common::RW> {
124        unsafe {
125            crate::common::Reg::<self::Intenb0_SPEC, crate::common::RW>::from_ptr(
126                self._svd2pac_as_ptr().add(48usize),
127            )
128        }
129    }
130
131    #[doc = "BRDY Interrupt Enable Register"]
132    #[inline(always)]
133    pub const fn brdyenb(
134        &self,
135    ) -> &'static crate::common::Reg<self::Brdyenb_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::Brdyenb_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(54usize),
139            )
140        }
141    }
142
143    #[doc = "NRDY Interrupt Enable Register"]
144    #[inline(always)]
145    pub const fn nrdyenb(
146        &self,
147    ) -> &'static crate::common::Reg<self::Nrdyenb_SPEC, crate::common::RW> {
148        unsafe {
149            crate::common::Reg::<self::Nrdyenb_SPEC, crate::common::RW>::from_ptr(
150                self._svd2pac_as_ptr().add(56usize),
151            )
152        }
153    }
154
155    #[doc = "BEMP Interrupt Enable Register"]
156    #[inline(always)]
157    pub const fn bempenb(
158        &self,
159    ) -> &'static crate::common::Reg<self::Bempenb_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Bempenb_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(58usize),
163            )
164        }
165    }
166
167    #[doc = "SOF Output Configuration Register"]
168    #[inline(always)]
169    pub const fn sofcfg(
170        &self,
171    ) -> &'static crate::common::Reg<self::Sofcfg_SPEC, crate::common::RW> {
172        unsafe {
173            crate::common::Reg::<self::Sofcfg_SPEC, crate::common::RW>::from_ptr(
174                self._svd2pac_as_ptr().add(60usize),
175            )
176        }
177    }
178
179    #[doc = "Interrupt Status Register 0"]
180    #[inline(always)]
181    pub const fn intsts0(
182        &self,
183    ) -> &'static crate::common::Reg<self::Intsts0_SPEC, crate::common::RW> {
184        unsafe {
185            crate::common::Reg::<self::Intsts0_SPEC, crate::common::RW>::from_ptr(
186                self._svd2pac_as_ptr().add(64usize),
187            )
188        }
189    }
190
191    #[doc = "BRDY Interrupt Status Register"]
192    #[inline(always)]
193    pub const fn brdysts(
194        &self,
195    ) -> &'static crate::common::Reg<self::Brdysts_SPEC, crate::common::RW> {
196        unsafe {
197            crate::common::Reg::<self::Brdysts_SPEC, crate::common::RW>::from_ptr(
198                self._svd2pac_as_ptr().add(70usize),
199            )
200        }
201    }
202
203    #[doc = "NRDY Interrupt Status Register"]
204    #[inline(always)]
205    pub const fn nrdysts(
206        &self,
207    ) -> &'static crate::common::Reg<self::Nrdysts_SPEC, crate::common::RW> {
208        unsafe {
209            crate::common::Reg::<self::Nrdysts_SPEC, crate::common::RW>::from_ptr(
210                self._svd2pac_as_ptr().add(72usize),
211            )
212        }
213    }
214
215    #[doc = "BEMP Interrupt Status Register"]
216    #[inline(always)]
217    pub const fn bempsts(
218        &self,
219    ) -> &'static crate::common::Reg<self::Bempsts_SPEC, crate::common::RW> {
220        unsafe {
221            crate::common::Reg::<self::Bempsts_SPEC, crate::common::RW>::from_ptr(
222                self._svd2pac_as_ptr().add(74usize),
223            )
224        }
225    }
226
227    #[doc = "Frame Number Register"]
228    #[inline(always)]
229    pub const fn frmnum(&self) -> &'static crate::common::Reg<self::Frmnum_SPEC, crate::common::R> {
230        unsafe {
231            crate::common::Reg::<self::Frmnum_SPEC, crate::common::R>::from_ptr(
232                self._svd2pac_as_ptr().add(76usize),
233            )
234        }
235    }
236
237    #[doc = "Device State Change Register"]
238    #[inline(always)]
239    pub const fn dvchgr(
240        &self,
241    ) -> &'static crate::common::Reg<self::Dvchgr_SPEC, crate::common::RW> {
242        unsafe {
243            crate::common::Reg::<self::Dvchgr_SPEC, crate::common::RW>::from_ptr(
244                self._svd2pac_as_ptr().add(78usize),
245            )
246        }
247    }
248
249    #[doc = "USB Address Register"]
250    #[inline(always)]
251    pub const fn usbaddr(
252        &self,
253    ) -> &'static crate::common::Reg<self::Usbaddr_SPEC, crate::common::RW> {
254        unsafe {
255            crate::common::Reg::<self::Usbaddr_SPEC, crate::common::RW>::from_ptr(
256                self._svd2pac_as_ptr().add(80usize),
257            )
258        }
259    }
260
261    #[doc = "USB Request Type Register"]
262    #[inline(always)]
263    pub const fn usbreq(&self) -> &'static crate::common::Reg<self::Usbreq_SPEC, crate::common::R> {
264        unsafe {
265            crate::common::Reg::<self::Usbreq_SPEC, crate::common::R>::from_ptr(
266                self._svd2pac_as_ptr().add(84usize),
267            )
268        }
269    }
270
271    #[doc = "USB Request Value Register"]
272    #[inline(always)]
273    pub const fn usbval(&self) -> &'static crate::common::Reg<self::Usbval_SPEC, crate::common::R> {
274        unsafe {
275            crate::common::Reg::<self::Usbval_SPEC, crate::common::R>::from_ptr(
276                self._svd2pac_as_ptr().add(86usize),
277            )
278        }
279    }
280
281    #[doc = "USB Request Index Register"]
282    #[inline(always)]
283    pub const fn usbindx(
284        &self,
285    ) -> &'static crate::common::Reg<self::Usbindx_SPEC, crate::common::R> {
286        unsafe {
287            crate::common::Reg::<self::Usbindx_SPEC, crate::common::R>::from_ptr(
288                self._svd2pac_as_ptr().add(88usize),
289            )
290        }
291    }
292
293    #[doc = "USB Request Length Register"]
294    #[inline(always)]
295    pub const fn usbleng(
296        &self,
297    ) -> &'static crate::common::Reg<self::Usbleng_SPEC, crate::common::R> {
298        unsafe {
299            crate::common::Reg::<self::Usbleng_SPEC, crate::common::R>::from_ptr(
300                self._svd2pac_as_ptr().add(90usize),
301            )
302        }
303    }
304
305    #[doc = "DCP Configuration Register"]
306    #[inline(always)]
307    pub const fn dcpcfg(
308        &self,
309    ) -> &'static crate::common::Reg<self::Dcpcfg_SPEC, crate::common::RW> {
310        unsafe {
311            crate::common::Reg::<self::Dcpcfg_SPEC, crate::common::RW>::from_ptr(
312                self._svd2pac_as_ptr().add(92usize),
313            )
314        }
315    }
316
317    #[doc = "DCP Maximum Packet Size Register"]
318    #[inline(always)]
319    pub const fn dcpmaxp(
320        &self,
321    ) -> &'static crate::common::Reg<self::Dcpmaxp_SPEC, crate::common::RW> {
322        unsafe {
323            crate::common::Reg::<self::Dcpmaxp_SPEC, crate::common::RW>::from_ptr(
324                self._svd2pac_as_ptr().add(94usize),
325            )
326        }
327    }
328
329    #[doc = "DCP Control Register"]
330    #[inline(always)]
331    pub const fn dcpctr(
332        &self,
333    ) -> &'static crate::common::Reg<self::Dcpctr_SPEC, crate::common::RW> {
334        unsafe {
335            crate::common::Reg::<self::Dcpctr_SPEC, crate::common::RW>::from_ptr(
336                self._svd2pac_as_ptr().add(96usize),
337            )
338        }
339    }
340
341    #[doc = "Pipe Window Select Register"]
342    #[inline(always)]
343    pub const fn pipesel(
344        &self,
345    ) -> &'static crate::common::Reg<self::Pipesel_SPEC, crate::common::RW> {
346        unsafe {
347            crate::common::Reg::<self::Pipesel_SPEC, crate::common::RW>::from_ptr(
348                self._svd2pac_as_ptr().add(100usize),
349            )
350        }
351    }
352
353    #[doc = "Pipe Configuration Register"]
354    #[inline(always)]
355    pub const fn pipecfg(
356        &self,
357    ) -> &'static crate::common::Reg<self::Pipecfg_SPEC, crate::common::RW> {
358        unsafe {
359            crate::common::Reg::<self::Pipecfg_SPEC, crate::common::RW>::from_ptr(
360                self._svd2pac_as_ptr().add(104usize),
361            )
362        }
363    }
364
365    #[doc = "Pipe Maximum Packet Size Register"]
366    #[inline(always)]
367    pub const fn pipemaxp(
368        &self,
369    ) -> &'static crate::common::Reg<self::Pipemaxp_SPEC, crate::common::RW> {
370        unsafe {
371            crate::common::Reg::<self::Pipemaxp_SPEC, crate::common::RW>::from_ptr(
372                self._svd2pac_as_ptr().add(108usize),
373            )
374        }
375    }
376
377    #[doc = "PIPE%s Control Registers"]
378    #[inline(always)]
379    pub const fn pipectr(
380        &self,
381    ) -> &'static crate::common::ClusterRegisterArray<
382        crate::common::Reg<self::Pipectr_SPEC, crate::common::RW>,
383        2,
384        0x2,
385    > {
386        unsafe {
387            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x7ausize))
388        }
389    }
390    #[inline(always)]
391    pub const fn pipe6ctr(
392        &self,
393    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
394        unsafe {
395            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
396                self._svd2pac_as_ptr().add(0x7ausize),
397            )
398        }
399    }
400    #[inline(always)]
401    pub const fn pipe7ctr(
402        &self,
403    ) -> &'static crate::common::Reg<self::Pipectr_SPEC, crate::common::RW> {
404        unsafe {
405            crate::common::Reg::<self::Pipectr_SPEC, crate::common::RW>::from_ptr(
406                self._svd2pac_as_ptr().add(0x7cusize),
407            )
408        }
409    }
410
411    #[doc = "PIPE%s Transaction Counter Enable Register"]
412    #[inline(always)]
413    pub const fn pipetre(
414        &self,
415    ) -> &'static crate::common::ClusterRegisterArray<
416        crate::common::Reg<self::Pipetre_SPEC, crate::common::RW>,
417        2,
418        0x4,
419    > {
420        unsafe {
421            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9cusize))
422        }
423    }
424    #[inline(always)]
425    pub const fn pipe4tre(
426        &self,
427    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
428        unsafe {
429            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
430                self._svd2pac_as_ptr().add(0x9cusize),
431            )
432        }
433    }
434    #[inline(always)]
435    pub const fn pipe5tre(
436        &self,
437    ) -> &'static crate::common::Reg<self::Pipetre_SPEC, crate::common::RW> {
438        unsafe {
439            crate::common::Reg::<self::Pipetre_SPEC, crate::common::RW>::from_ptr(
440                self._svd2pac_as_ptr().add(0xa0usize),
441            )
442        }
443    }
444
445    #[doc = "PIPE%s Transaction Counter Register"]
446    #[inline(always)]
447    pub const fn pipetrn(
448        &self,
449    ) -> &'static crate::common::ClusterRegisterArray<
450        crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW>,
451        2,
452        0x4,
453    > {
454        unsafe {
455            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x9eusize))
456        }
457    }
458    #[inline(always)]
459    pub const fn pipe4trn(
460        &self,
461    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
462        unsafe {
463            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
464                self._svd2pac_as_ptr().add(0x9eusize),
465            )
466        }
467    }
468    #[inline(always)]
469    pub const fn pipe5trn(
470        &self,
471    ) -> &'static crate::common::Reg<self::Pipetrn_SPEC, crate::common::RW> {
472        unsafe {
473            crate::common::Reg::<self::Pipetrn_SPEC, crate::common::RW>::from_ptr(
474                self._svd2pac_as_ptr().add(0xa2usize),
475            )
476        }
477    }
478
479    #[doc = "PHY Single-ended Receiver Control Register"]
480    #[inline(always)]
481    pub const fn physectrl(
482        &self,
483    ) -> &'static crate::common::Reg<self::Physectrl_SPEC, crate::common::RW> {
484        unsafe {
485            crate::common::Reg::<self::Physectrl_SPEC, crate::common::RW>::from_ptr(
486                self._svd2pac_as_ptr().add(244usize),
487            )
488        }
489    }
490
491    #[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
492    #[inline(always)]
493    pub const fn dpusr0r(
494        &self,
495    ) -> &'static crate::common::Reg<self::Dpusr0R_SPEC, crate::common::RW> {
496        unsafe {
497            crate::common::Reg::<self::Dpusr0R_SPEC, crate::common::RW>::from_ptr(
498                self._svd2pac_as_ptr().add(1024usize),
499            )
500        }
501    }
502
503    #[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
504    #[inline(always)]
505    pub const fn dpusr1r(
506        &self,
507    ) -> &'static crate::common::Reg<self::Dpusr1R_SPEC, crate::common::RW> {
508        unsafe {
509            crate::common::Reg::<self::Dpusr1R_SPEC, crate::common::RW>::from_ptr(
510                self._svd2pac_as_ptr().add(1028usize),
511            )
512        }
513    }
514}
515#[doc(hidden)]
516#[derive(Copy, Clone, Eq, PartialEq)]
517pub struct Syscfg_SPEC;
518impl crate::sealed::RegSpec for Syscfg_SPEC {
519    type DataType = u16;
520}
521
522#[doc = "System Configuration Control Register"]
523pub type Syscfg = crate::RegValueT<Syscfg_SPEC>;
524
525impl Syscfg {
526    #[doc = "USBFS Operation Enable"]
527    #[inline(always)]
528    pub fn usbe(
529        self,
530    ) -> crate::common::RegisterField<
531        0,
532        0x1,
533        1,
534        0,
535        syscfg::Usbe,
536        syscfg::Usbe,
537        Syscfg_SPEC,
538        crate::common::RW,
539    > {
540        crate::common::RegisterField::<
541            0,
542            0x1,
543            1,
544            0,
545            syscfg::Usbe,
546            syscfg::Usbe,
547            Syscfg_SPEC,
548            crate::common::RW,
549        >::from_register(self, 0)
550    }
551
552    #[doc = "D+ Line Resistor Control"]
553    #[inline(always)]
554    pub fn dprpu(
555        self,
556    ) -> crate::common::RegisterField<
557        4,
558        0x1,
559        1,
560        0,
561        syscfg::Dprpu,
562        syscfg::Dprpu,
563        Syscfg_SPEC,
564        crate::common::RW,
565    > {
566        crate::common::RegisterField::<
567            4,
568            0x1,
569            1,
570            0,
571            syscfg::Dprpu,
572            syscfg::Dprpu,
573            Syscfg_SPEC,
574            crate::common::RW,
575        >::from_register(self, 0)
576    }
577
578    #[doc = "USB Clock Enable"]
579    #[inline(always)]
580    pub fn scke(
581        self,
582    ) -> crate::common::RegisterField<
583        10,
584        0x1,
585        1,
586        0,
587        syscfg::Scke,
588        syscfg::Scke,
589        Syscfg_SPEC,
590        crate::common::RW,
591    > {
592        crate::common::RegisterField::<
593            10,
594            0x1,
595            1,
596            0,
597            syscfg::Scke,
598            syscfg::Scke,
599            Syscfg_SPEC,
600            crate::common::RW,
601        >::from_register(self, 0)
602    }
603}
604impl ::core::default::Default for Syscfg {
605    #[inline(always)]
606    fn default() -> Syscfg {
607        <crate::RegValueT<Syscfg_SPEC> as RegisterValue<_>>::new(0)
608    }
609}
610pub mod syscfg {
611
612    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
613    pub struct Usbe_SPEC;
614    pub type Usbe = crate::EnumBitfieldStruct<u8, Usbe_SPEC>;
615    impl Usbe {
616        #[doc = "Disable"]
617        pub const _0: Self = Self::new(0);
618
619        #[doc = "Enable"]
620        pub const _1: Self = Self::new(1);
621    }
622    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
623    pub struct Dprpu_SPEC;
624    pub type Dprpu = crate::EnumBitfieldStruct<u8, Dprpu_SPEC>;
625    impl Dprpu {
626        #[doc = "Disable line pull-up"]
627        pub const _0: Self = Self::new(0);
628
629        #[doc = "Enable line pull-up"]
630        pub const _1: Self = Self::new(1);
631    }
632    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
633    pub struct Scke_SPEC;
634    pub type Scke = crate::EnumBitfieldStruct<u8, Scke_SPEC>;
635    impl Scke {
636        #[doc = "Stop clock supply to the USBFS"]
637        pub const _0: Self = Self::new(0);
638
639        #[doc = "Enable clock supply to the USBFS"]
640        pub const _1: Self = Self::new(1);
641    }
642}
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Syssts0_SPEC;
646impl crate::sealed::RegSpec for Syssts0_SPEC {
647    type DataType = u16;
648}
649
650#[doc = "System Configuration Status Register 0"]
651pub type Syssts0 = crate::RegValueT<Syssts0_SPEC>;
652
653impl Syssts0 {
654    #[doc = "USB Data Line Status Monitor"]
655    #[inline(always)]
656    pub fn lnst(
657        self,
658    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Syssts0_SPEC, crate::common::R> {
659        crate::common::RegisterField::<0,0x3,1,0,u8,u8,Syssts0_SPEC,crate::common::R>::from_register(self,0)
660    }
661}
662impl ::core::default::Default for Syssts0 {
663    #[inline(always)]
664    fn default() -> Syssts0 {
665        <crate::RegValueT<Syssts0_SPEC> as RegisterValue<_>>::new(0)
666    }
667}
668
669#[doc(hidden)]
670#[derive(Copy, Clone, Eq, PartialEq)]
671pub struct Dvstctr0_SPEC;
672impl crate::sealed::RegSpec for Dvstctr0_SPEC {
673    type DataType = u16;
674}
675
676#[doc = "Device State Control Register 0"]
677pub type Dvstctr0 = crate::RegValueT<Dvstctr0_SPEC>;
678
679impl Dvstctr0 {
680    #[doc = "USB Bus Reset Status"]
681    #[inline(always)]
682    pub fn rhst(
683        self,
684    ) -> crate::common::RegisterField<
685        0,
686        0x7,
687        1,
688        0,
689        dvstctr0::Rhst,
690        dvstctr0::Rhst,
691        Dvstctr0_SPEC,
692        crate::common::R,
693    > {
694        crate::common::RegisterField::<
695            0,
696            0x7,
697            1,
698            0,
699            dvstctr0::Rhst,
700            dvstctr0::Rhst,
701            Dvstctr0_SPEC,
702            crate::common::R,
703        >::from_register(self, 0)
704    }
705
706    #[doc = "Wakeup Output"]
707    #[inline(always)]
708    pub fn wkup(
709        self,
710    ) -> crate::common::RegisterField<
711        8,
712        0x1,
713        1,
714        0,
715        dvstctr0::Wkup,
716        dvstctr0::Wkup,
717        Dvstctr0_SPEC,
718        crate::common::RW,
719    > {
720        crate::common::RegisterField::<
721            8,
722            0x1,
723            1,
724            0,
725            dvstctr0::Wkup,
726            dvstctr0::Wkup,
727            Dvstctr0_SPEC,
728            crate::common::RW,
729        >::from_register(self, 0)
730    }
731}
732impl ::core::default::Default for Dvstctr0 {
733    #[inline(always)]
734    fn default() -> Dvstctr0 {
735        <crate::RegValueT<Dvstctr0_SPEC> as RegisterValue<_>>::new(0)
736    }
737}
738pub mod dvstctr0 {
739
740    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
741    pub struct Rhst_SPEC;
742    pub type Rhst = crate::EnumBitfieldStruct<u8, Rhst_SPEC>;
743    impl Rhst {
744        #[doc = "Communication speed indeterminate"]
745        pub const _000: Self = Self::new(0);
746
747        #[doc = "USB bus reset in progress"]
748        pub const _001: Self = Self::new(1);
749
750        #[doc = "USB bus reset in progress or full-speed connection"]
751        pub const _010: Self = Self::new(2);
752    }
753    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
754    pub struct Wkup_SPEC;
755    pub type Wkup = crate::EnumBitfieldStruct<u8, Wkup_SPEC>;
756    impl Wkup {
757        #[doc = "Do not output remote wakeup signal"]
758        pub const _0: Self = Self::new(0);
759
760        #[doc = "Output remote wakeup signal"]
761        pub const _1: Self = Self::new(1);
762    }
763}
764#[doc(hidden)]
765#[derive(Copy, Clone, Eq, PartialEq)]
766pub struct Cfifo_SPEC;
767impl crate::sealed::RegSpec for Cfifo_SPEC {
768    type DataType = u16;
769}
770
771#[doc = "CFIFO Port Register"]
772pub type Cfifo = crate::RegValueT<Cfifo_SPEC>;
773
774impl Cfifo {
775    #[doc = "FIFO Port"]
776    #[inline(always)]
777    pub fn fifoport(
778        self,
779    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cfifo_SPEC, crate::common::RW>
780    {
781        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cfifo_SPEC,crate::common::RW>::from_register(self,0)
782    }
783}
784impl ::core::default::Default for Cfifo {
785    #[inline(always)]
786    fn default() -> Cfifo {
787        <crate::RegValueT<Cfifo_SPEC> as RegisterValue<_>>::new(0)
788    }
789}
790
791#[doc(hidden)]
792#[derive(Copy, Clone, Eq, PartialEq)]
793pub struct Cfifol_SPEC;
794impl crate::sealed::RegSpec for Cfifol_SPEC {
795    type DataType = u8;
796}
797
798#[doc = "CFIFO Port Register"]
799pub type Cfifol = crate::RegValueT<Cfifol_SPEC>;
800
801impl Cfifol {
802    #[doc = "FIFO Port"]
803    #[inline(always)]
804    pub fn fifoport(
805        self,
806    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Cfifol_SPEC, crate::common::RW> {
807        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Cfifol_SPEC,crate::common::RW>::from_register(self,0)
808    }
809}
810impl ::core::default::Default for Cfifol {
811    #[inline(always)]
812    fn default() -> Cfifol {
813        <crate::RegValueT<Cfifol_SPEC> as RegisterValue<_>>::new(0)
814    }
815}
816
817#[doc(hidden)]
818#[derive(Copy, Clone, Eq, PartialEq)]
819pub struct Cfifosel_SPEC;
820impl crate::sealed::RegSpec for Cfifosel_SPEC {
821    type DataType = u16;
822}
823
824#[doc = "CFIFO Port Select Register"]
825pub type Cfifosel = crate::RegValueT<Cfifosel_SPEC>;
826
827impl Cfifosel {
828    #[doc = "CFIFO Port Access Pipe Specification"]
829    #[inline(always)]
830    pub fn curpipe(
831        self,
832    ) -> crate::common::RegisterField<
833        0,
834        0xf,
835        1,
836        0,
837        cfifosel::Curpipe,
838        cfifosel::Curpipe,
839        Cfifosel_SPEC,
840        crate::common::RW,
841    > {
842        crate::common::RegisterField::<
843            0,
844            0xf,
845            1,
846            0,
847            cfifosel::Curpipe,
848            cfifosel::Curpipe,
849            Cfifosel_SPEC,
850            crate::common::RW,
851        >::from_register(self, 0)
852    }
853
854    #[doc = "CFIFO Port Access Direction When DCP Is Selected"]
855    #[inline(always)]
856    pub fn isel(
857        self,
858    ) -> crate::common::RegisterField<
859        5,
860        0x1,
861        1,
862        0,
863        cfifosel::Isel,
864        cfifosel::Isel,
865        Cfifosel_SPEC,
866        crate::common::RW,
867    > {
868        crate::common::RegisterField::<
869            5,
870            0x1,
871            1,
872            0,
873            cfifosel::Isel,
874            cfifosel::Isel,
875            Cfifosel_SPEC,
876            crate::common::RW,
877        >::from_register(self, 0)
878    }
879
880    #[doc = "CFIFO Port Endian Control"]
881    #[inline(always)]
882    pub fn bigend(
883        self,
884    ) -> crate::common::RegisterField<
885        8,
886        0x1,
887        1,
888        0,
889        cfifosel::Bigend,
890        cfifosel::Bigend,
891        Cfifosel_SPEC,
892        crate::common::RW,
893    > {
894        crate::common::RegisterField::<
895            8,
896            0x1,
897            1,
898            0,
899            cfifosel::Bigend,
900            cfifosel::Bigend,
901            Cfifosel_SPEC,
902            crate::common::RW,
903        >::from_register(self, 0)
904    }
905
906    #[doc = "CFIFO Port Access Bit Width"]
907    #[inline(always)]
908    pub fn mbw(
909        self,
910    ) -> crate::common::RegisterField<
911        10,
912        0x1,
913        1,
914        0,
915        cfifosel::Mbw,
916        cfifosel::Mbw,
917        Cfifosel_SPEC,
918        crate::common::RW,
919    > {
920        crate::common::RegisterField::<
921            10,
922            0x1,
923            1,
924            0,
925            cfifosel::Mbw,
926            cfifosel::Mbw,
927            Cfifosel_SPEC,
928            crate::common::RW,
929        >::from_register(self, 0)
930    }
931
932    #[doc = "Buffer Pointer Rewind"]
933    #[inline(always)]
934    pub fn rew(
935        self,
936    ) -> crate::common::RegisterField<
937        14,
938        0x1,
939        1,
940        0,
941        cfifosel::Rew,
942        cfifosel::Rew,
943        Cfifosel_SPEC,
944        crate::common::W,
945    > {
946        crate::common::RegisterField::<
947            14,
948            0x1,
949            1,
950            0,
951            cfifosel::Rew,
952            cfifosel::Rew,
953            Cfifosel_SPEC,
954            crate::common::W,
955        >::from_register(self, 0)
956    }
957
958    #[doc = "Read Count Mode"]
959    #[inline(always)]
960    pub fn rcnt(
961        self,
962    ) -> crate::common::RegisterField<
963        15,
964        0x1,
965        1,
966        0,
967        cfifosel::Rcnt,
968        cfifosel::Rcnt,
969        Cfifosel_SPEC,
970        crate::common::RW,
971    > {
972        crate::common::RegisterField::<
973            15,
974            0x1,
975            1,
976            0,
977            cfifosel::Rcnt,
978            cfifosel::Rcnt,
979            Cfifosel_SPEC,
980            crate::common::RW,
981        >::from_register(self, 0)
982    }
983}
984impl ::core::default::Default for Cfifosel {
985    #[inline(always)]
986    fn default() -> Cfifosel {
987        <crate::RegValueT<Cfifosel_SPEC> as RegisterValue<_>>::new(0)
988    }
989}
990pub mod cfifosel {
991
992    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
993    pub struct Curpipe_SPEC;
994    pub type Curpipe = crate::EnumBitfieldStruct<u8, Curpipe_SPEC>;
995    impl Curpipe {
996        #[doc = "Default Control Pipe"]
997        pub const _0_X_0: Self = Self::new(0);
998
999        #[doc = "Pipe 4"]
1000        pub const _0_X_4: Self = Self::new(4);
1001
1002        #[doc = "Pipe 5"]
1003        pub const _0_X_5: Self = Self::new(5);
1004
1005        #[doc = "Pipe 6"]
1006        pub const _0_X_6: Self = Self::new(6);
1007
1008        #[doc = "Pipe 7"]
1009        pub const _0_X_7: Self = Self::new(7);
1010    }
1011    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1012    pub struct Isel_SPEC;
1013    pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
1014    impl Isel {
1015        #[doc = "Select reading from the FIFO buffer"]
1016        pub const _0: Self = Self::new(0);
1017
1018        #[doc = "Select writing to the FIFO buffer"]
1019        pub const _1: Self = Self::new(1);
1020    }
1021    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1022    pub struct Bigend_SPEC;
1023    pub type Bigend = crate::EnumBitfieldStruct<u8, Bigend_SPEC>;
1024    impl Bigend {
1025        #[doc = "Little endian"]
1026        pub const _0: Self = Self::new(0);
1027
1028        #[doc = "Big endian"]
1029        pub const _1: Self = Self::new(1);
1030    }
1031    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1032    pub struct Mbw_SPEC;
1033    pub type Mbw = crate::EnumBitfieldStruct<u8, Mbw_SPEC>;
1034    impl Mbw {
1035        #[doc = "8-bit width"]
1036        pub const _0: Self = Self::new(0);
1037
1038        #[doc = "16-bit width"]
1039        pub const _1: Self = Self::new(1);
1040    }
1041    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1042    pub struct Rew_SPEC;
1043    pub type Rew = crate::EnumBitfieldStruct<u8, Rew_SPEC>;
1044    impl Rew {
1045        #[doc = "Do not rewind buffer pointer"]
1046        pub const _0: Self = Self::new(0);
1047
1048        #[doc = "Rewind buffer pointer"]
1049        pub const _1: Self = Self::new(1);
1050    }
1051    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1052    pub struct Rcnt_SPEC;
1053    pub type Rcnt = crate::EnumBitfieldStruct<u8, Rcnt_SPEC>;
1054    impl Rcnt {
1055        #[doc = "The DTLN\\[8:0\\] bits (CFIFOCTR.DTLN\\[8:0\\]) are cleared when all receive data is read from the CFIFO. In double buffer mode, the DTLN\\[8:0\\] value is cleared when all data is read from only a single plane."]
1056        pub const _0: Self = Self::new(0);
1057
1058        #[doc = "The DTLN\\[8:0\\] bits are decremented each time the receive data is read from the CFIFO."]
1059        pub const _1: Self = Self::new(1);
1060    }
1061}
1062#[doc(hidden)]
1063#[derive(Copy, Clone, Eq, PartialEq)]
1064pub struct Cfifoctr_SPEC;
1065impl crate::sealed::RegSpec for Cfifoctr_SPEC {
1066    type DataType = u16;
1067}
1068
1069#[doc = "CFIFO Port Control Register"]
1070pub type Cfifoctr = crate::RegValueT<Cfifoctr_SPEC>;
1071
1072impl Cfifoctr {
1073    #[doc = "Receive Data Length"]
1074    #[inline(always)]
1075    pub fn dtln(
1076        self,
1077    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cfifoctr_SPEC, crate::common::R>
1078    {
1079        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cfifoctr_SPEC,crate::common::R>::from_register(self,0)
1080    }
1081
1082    #[doc = "FIFO Port Ready"]
1083    #[inline(always)]
1084    pub fn frdy(
1085        self,
1086    ) -> crate::common::RegisterField<
1087        13,
1088        0x1,
1089        1,
1090        0,
1091        cfifoctr::Frdy,
1092        cfifoctr::Frdy,
1093        Cfifoctr_SPEC,
1094        crate::common::R,
1095    > {
1096        crate::common::RegisterField::<
1097            13,
1098            0x1,
1099            1,
1100            0,
1101            cfifoctr::Frdy,
1102            cfifoctr::Frdy,
1103            Cfifoctr_SPEC,
1104            crate::common::R,
1105        >::from_register(self, 0)
1106    }
1107
1108    #[doc = "CPU Buffer Clear"]
1109    #[inline(always)]
1110    pub fn bclr(
1111        self,
1112    ) -> crate::common::RegisterField<
1113        14,
1114        0x1,
1115        1,
1116        0,
1117        cfifoctr::Bclr,
1118        cfifoctr::Bclr,
1119        Cfifoctr_SPEC,
1120        crate::common::W,
1121    > {
1122        crate::common::RegisterField::<
1123            14,
1124            0x1,
1125            1,
1126            0,
1127            cfifoctr::Bclr,
1128            cfifoctr::Bclr,
1129            Cfifoctr_SPEC,
1130            crate::common::W,
1131        >::from_register(self, 0)
1132    }
1133
1134    #[doc = "Buffer Memory Valid Flag"]
1135    #[inline(always)]
1136    pub fn bval(
1137        self,
1138    ) -> crate::common::RegisterField<
1139        15,
1140        0x1,
1141        1,
1142        0,
1143        cfifoctr::Bval,
1144        cfifoctr::Bval,
1145        Cfifoctr_SPEC,
1146        crate::common::RW,
1147    > {
1148        crate::common::RegisterField::<
1149            15,
1150            0x1,
1151            1,
1152            0,
1153            cfifoctr::Bval,
1154            cfifoctr::Bval,
1155            Cfifoctr_SPEC,
1156            crate::common::RW,
1157        >::from_register(self, 0)
1158    }
1159}
1160impl ::core::default::Default for Cfifoctr {
1161    #[inline(always)]
1162    fn default() -> Cfifoctr {
1163        <crate::RegValueT<Cfifoctr_SPEC> as RegisterValue<_>>::new(0)
1164    }
1165}
1166pub mod cfifoctr {
1167
1168    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1169    pub struct Frdy_SPEC;
1170    pub type Frdy = crate::EnumBitfieldStruct<u8, Frdy_SPEC>;
1171    impl Frdy {
1172        #[doc = "FIFO port access disabled"]
1173        pub const _0: Self = Self::new(0);
1174
1175        #[doc = "FIFO port access enabled"]
1176        pub const _1: Self = Self::new(1);
1177    }
1178    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1179    pub struct Bclr_SPEC;
1180    pub type Bclr = crate::EnumBitfieldStruct<u8, Bclr_SPEC>;
1181    impl Bclr {
1182        #[doc = "No operation"]
1183        pub const _0: Self = Self::new(0);
1184
1185        #[doc = "Clear FIFO buffer on the CPU side"]
1186        pub const _1: Self = Self::new(1);
1187    }
1188    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1189    pub struct Bval_SPEC;
1190    pub type Bval = crate::EnumBitfieldStruct<u8, Bval_SPEC>;
1191    impl Bval {
1192        #[doc = "Invalid (writing 0 has no effect)"]
1193        pub const _0: Self = Self::new(0);
1194
1195        #[doc = "Writing ended"]
1196        pub const _1: Self = Self::new(1);
1197    }
1198}
1199#[doc(hidden)]
1200#[derive(Copy, Clone, Eq, PartialEq)]
1201pub struct Intenb0_SPEC;
1202impl crate::sealed::RegSpec for Intenb0_SPEC {
1203    type DataType = u16;
1204}
1205
1206#[doc = "Interrupt Enable Register 0"]
1207pub type Intenb0 = crate::RegValueT<Intenb0_SPEC>;
1208
1209impl Intenb0 {
1210    #[doc = "Buffer Ready Interrupt Enable"]
1211    #[inline(always)]
1212    pub fn brdye(
1213        self,
1214    ) -> crate::common::RegisterField<
1215        8,
1216        0x1,
1217        1,
1218        0,
1219        intenb0::Brdye,
1220        intenb0::Brdye,
1221        Intenb0_SPEC,
1222        crate::common::RW,
1223    > {
1224        crate::common::RegisterField::<
1225            8,
1226            0x1,
1227            1,
1228            0,
1229            intenb0::Brdye,
1230            intenb0::Brdye,
1231            Intenb0_SPEC,
1232            crate::common::RW,
1233        >::from_register(self, 0)
1234    }
1235
1236    #[doc = "Buffer Not Ready Response Interrupt Enable"]
1237    #[inline(always)]
1238    pub fn nrdye(
1239        self,
1240    ) -> crate::common::RegisterField<
1241        9,
1242        0x1,
1243        1,
1244        0,
1245        intenb0::Nrdye,
1246        intenb0::Nrdye,
1247        Intenb0_SPEC,
1248        crate::common::RW,
1249    > {
1250        crate::common::RegisterField::<
1251            9,
1252            0x1,
1253            1,
1254            0,
1255            intenb0::Nrdye,
1256            intenb0::Nrdye,
1257            Intenb0_SPEC,
1258            crate::common::RW,
1259        >::from_register(self, 0)
1260    }
1261
1262    #[doc = "Buffer Empty Interrupt Enable"]
1263    #[inline(always)]
1264    pub fn bempe(
1265        self,
1266    ) -> crate::common::RegisterField<
1267        10,
1268        0x1,
1269        1,
1270        0,
1271        intenb0::Bempe,
1272        intenb0::Bempe,
1273        Intenb0_SPEC,
1274        crate::common::RW,
1275    > {
1276        crate::common::RegisterField::<
1277            10,
1278            0x1,
1279            1,
1280            0,
1281            intenb0::Bempe,
1282            intenb0::Bempe,
1283            Intenb0_SPEC,
1284            crate::common::RW,
1285        >::from_register(self, 0)
1286    }
1287
1288    #[doc = "Control Transfer Stage Transition Interrupt Enable"]
1289    #[inline(always)]
1290    pub fn ctre(
1291        self,
1292    ) -> crate::common::RegisterField<
1293        11,
1294        0x1,
1295        1,
1296        0,
1297        intenb0::Ctre,
1298        intenb0::Ctre,
1299        Intenb0_SPEC,
1300        crate::common::RW,
1301    > {
1302        crate::common::RegisterField::<
1303            11,
1304            0x1,
1305            1,
1306            0,
1307            intenb0::Ctre,
1308            intenb0::Ctre,
1309            Intenb0_SPEC,
1310            crate::common::RW,
1311        >::from_register(self, 0)
1312    }
1313
1314    #[doc = "Device State Transition Interrupt Enable"]
1315    #[inline(always)]
1316    pub fn dvse(
1317        self,
1318    ) -> crate::common::RegisterField<
1319        12,
1320        0x1,
1321        1,
1322        0,
1323        intenb0::Dvse,
1324        intenb0::Dvse,
1325        Intenb0_SPEC,
1326        crate::common::RW,
1327    > {
1328        crate::common::RegisterField::<
1329            12,
1330            0x1,
1331            1,
1332            0,
1333            intenb0::Dvse,
1334            intenb0::Dvse,
1335            Intenb0_SPEC,
1336            crate::common::RW,
1337        >::from_register(self, 0)
1338    }
1339
1340    #[doc = "Frame Number Update Interrupt Enable"]
1341    #[inline(always)]
1342    pub fn sofe(
1343        self,
1344    ) -> crate::common::RegisterField<
1345        13,
1346        0x1,
1347        1,
1348        0,
1349        intenb0::Sofe,
1350        intenb0::Sofe,
1351        Intenb0_SPEC,
1352        crate::common::RW,
1353    > {
1354        crate::common::RegisterField::<
1355            13,
1356            0x1,
1357            1,
1358            0,
1359            intenb0::Sofe,
1360            intenb0::Sofe,
1361            Intenb0_SPEC,
1362            crate::common::RW,
1363        >::from_register(self, 0)
1364    }
1365
1366    #[doc = "Resume Interrupt Enable"]
1367    #[inline(always)]
1368    pub fn rsme(
1369        self,
1370    ) -> crate::common::RegisterField<
1371        14,
1372        0x1,
1373        1,
1374        0,
1375        intenb0::Rsme,
1376        intenb0::Rsme,
1377        Intenb0_SPEC,
1378        crate::common::RW,
1379    > {
1380        crate::common::RegisterField::<
1381            14,
1382            0x1,
1383            1,
1384            0,
1385            intenb0::Rsme,
1386            intenb0::Rsme,
1387            Intenb0_SPEC,
1388            crate::common::RW,
1389        >::from_register(self, 0)
1390    }
1391
1392    #[doc = "VBUS Interrupt Enable"]
1393    #[inline(always)]
1394    pub fn vbse(
1395        self,
1396    ) -> crate::common::RegisterField<
1397        15,
1398        0x1,
1399        1,
1400        0,
1401        intenb0::Vbse,
1402        intenb0::Vbse,
1403        Intenb0_SPEC,
1404        crate::common::RW,
1405    > {
1406        crate::common::RegisterField::<
1407            15,
1408            0x1,
1409            1,
1410            0,
1411            intenb0::Vbse,
1412            intenb0::Vbse,
1413            Intenb0_SPEC,
1414            crate::common::RW,
1415        >::from_register(self, 0)
1416    }
1417}
1418impl ::core::default::Default for Intenb0 {
1419    #[inline(always)]
1420    fn default() -> Intenb0 {
1421        <crate::RegValueT<Intenb0_SPEC> as RegisterValue<_>>::new(0)
1422    }
1423}
1424pub mod intenb0 {
1425
1426    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1427    pub struct Brdye_SPEC;
1428    pub type Brdye = crate::EnumBitfieldStruct<u8, Brdye_SPEC>;
1429    impl Brdye {
1430        #[doc = "Disable interrupt request"]
1431        pub const _0: Self = Self::new(0);
1432
1433        #[doc = "Enable interrupt request"]
1434        pub const _1: Self = Self::new(1);
1435    }
1436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1437    pub struct Nrdye_SPEC;
1438    pub type Nrdye = crate::EnumBitfieldStruct<u8, Nrdye_SPEC>;
1439    impl Nrdye {
1440        #[doc = "Disable interrupt request"]
1441        pub const _0: Self = Self::new(0);
1442
1443        #[doc = "Enable interrupt request"]
1444        pub const _1: Self = Self::new(1);
1445    }
1446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1447    pub struct Bempe_SPEC;
1448    pub type Bempe = crate::EnumBitfieldStruct<u8, Bempe_SPEC>;
1449    impl Bempe {
1450        #[doc = "Disable interrupt request"]
1451        pub const _0: Self = Self::new(0);
1452
1453        #[doc = "Enable interrupt request"]
1454        pub const _1: Self = Self::new(1);
1455    }
1456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1457    pub struct Ctre_SPEC;
1458    pub type Ctre = crate::EnumBitfieldStruct<u8, Ctre_SPEC>;
1459    impl Ctre {
1460        #[doc = "Disable interrupt request"]
1461        pub const _0: Self = Self::new(0);
1462
1463        #[doc = "Enable interrupt request"]
1464        pub const _1: Self = Self::new(1);
1465    }
1466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1467    pub struct Dvse_SPEC;
1468    pub type Dvse = crate::EnumBitfieldStruct<u8, Dvse_SPEC>;
1469    impl Dvse {
1470        #[doc = "Disable interrupt request"]
1471        pub const _0: Self = Self::new(0);
1472
1473        #[doc = "Enable interrupt request"]
1474        pub const _1: Self = Self::new(1);
1475    }
1476    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1477    pub struct Sofe_SPEC;
1478    pub type Sofe = crate::EnumBitfieldStruct<u8, Sofe_SPEC>;
1479    impl Sofe {
1480        #[doc = "Disable interrupt request"]
1481        pub const _0: Self = Self::new(0);
1482
1483        #[doc = "Enable interrupt request"]
1484        pub const _1: Self = Self::new(1);
1485    }
1486    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1487    pub struct Rsme_SPEC;
1488    pub type Rsme = crate::EnumBitfieldStruct<u8, Rsme_SPEC>;
1489    impl Rsme {
1490        #[doc = "Disable interrupt request"]
1491        pub const _0: Self = Self::new(0);
1492
1493        #[doc = "Enable interrupt request"]
1494        pub const _1: Self = Self::new(1);
1495    }
1496    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1497    pub struct Vbse_SPEC;
1498    pub type Vbse = crate::EnumBitfieldStruct<u8, Vbse_SPEC>;
1499    impl Vbse {
1500        #[doc = "Disable interrupt request"]
1501        pub const _0: Self = Self::new(0);
1502
1503        #[doc = "Enable interrupt request"]
1504        pub const _1: Self = Self::new(1);
1505    }
1506}
1507#[doc(hidden)]
1508#[derive(Copy, Clone, Eq, PartialEq)]
1509pub struct Brdyenb_SPEC;
1510impl crate::sealed::RegSpec for Brdyenb_SPEC {
1511    type DataType = u16;
1512}
1513
1514#[doc = "BRDY Interrupt Enable Register"]
1515pub type Brdyenb = crate::RegValueT<Brdyenb_SPEC>;
1516
1517impl Brdyenb {
1518    #[doc = "BRDY Interrupt Enable for Pipe 0"]
1519    #[inline(always)]
1520    pub fn pipe0brdye(
1521        self,
1522    ) -> crate::common::RegisterField<
1523        0,
1524        0x1,
1525        1,
1526        0,
1527        brdyenb::Pipe0Brdye,
1528        brdyenb::Pipe0Brdye,
1529        Brdyenb_SPEC,
1530        crate::common::RW,
1531    > {
1532        crate::common::RegisterField::<
1533            0,
1534            0x1,
1535            1,
1536            0,
1537            brdyenb::Pipe0Brdye,
1538            brdyenb::Pipe0Brdye,
1539            Brdyenb_SPEC,
1540            crate::common::RW,
1541        >::from_register(self, 0)
1542    }
1543
1544    #[doc = "BRDY Interrupt Enable for Pipe 4"]
1545    #[inline(always)]
1546    pub fn pipe4brdye(
1547        self,
1548    ) -> crate::common::RegisterField<
1549        4,
1550        0x1,
1551        1,
1552        0,
1553        brdyenb::Pipe4Brdye,
1554        brdyenb::Pipe4Brdye,
1555        Brdyenb_SPEC,
1556        crate::common::RW,
1557    > {
1558        crate::common::RegisterField::<
1559            4,
1560            0x1,
1561            1,
1562            0,
1563            brdyenb::Pipe4Brdye,
1564            brdyenb::Pipe4Brdye,
1565            Brdyenb_SPEC,
1566            crate::common::RW,
1567        >::from_register(self, 0)
1568    }
1569
1570    #[doc = "BRDY Interrupt Enable for Pipe 5"]
1571    #[inline(always)]
1572    pub fn pipe5brdye(
1573        self,
1574    ) -> crate::common::RegisterField<
1575        5,
1576        0x1,
1577        1,
1578        0,
1579        brdyenb::Pipe5Brdye,
1580        brdyenb::Pipe5Brdye,
1581        Brdyenb_SPEC,
1582        crate::common::RW,
1583    > {
1584        crate::common::RegisterField::<
1585            5,
1586            0x1,
1587            1,
1588            0,
1589            brdyenb::Pipe5Brdye,
1590            brdyenb::Pipe5Brdye,
1591            Brdyenb_SPEC,
1592            crate::common::RW,
1593        >::from_register(self, 0)
1594    }
1595
1596    #[doc = "BRDY Interrupt Enable for Pipe 6"]
1597    #[inline(always)]
1598    pub fn pipe6brdye(
1599        self,
1600    ) -> crate::common::RegisterField<
1601        6,
1602        0x1,
1603        1,
1604        0,
1605        brdyenb::Pipe6Brdye,
1606        brdyenb::Pipe6Brdye,
1607        Brdyenb_SPEC,
1608        crate::common::RW,
1609    > {
1610        crate::common::RegisterField::<
1611            6,
1612            0x1,
1613            1,
1614            0,
1615            brdyenb::Pipe6Brdye,
1616            brdyenb::Pipe6Brdye,
1617            Brdyenb_SPEC,
1618            crate::common::RW,
1619        >::from_register(self, 0)
1620    }
1621
1622    #[doc = "BRDY Interrupt Enable for Pipe 7"]
1623    #[inline(always)]
1624    pub fn pipe7brdye(
1625        self,
1626    ) -> crate::common::RegisterField<
1627        7,
1628        0x1,
1629        1,
1630        0,
1631        brdyenb::Pipe7Brdye,
1632        brdyenb::Pipe7Brdye,
1633        Brdyenb_SPEC,
1634        crate::common::RW,
1635    > {
1636        crate::common::RegisterField::<
1637            7,
1638            0x1,
1639            1,
1640            0,
1641            brdyenb::Pipe7Brdye,
1642            brdyenb::Pipe7Brdye,
1643            Brdyenb_SPEC,
1644            crate::common::RW,
1645        >::from_register(self, 0)
1646    }
1647}
1648impl ::core::default::Default for Brdyenb {
1649    #[inline(always)]
1650    fn default() -> Brdyenb {
1651        <crate::RegValueT<Brdyenb_SPEC> as RegisterValue<_>>::new(0)
1652    }
1653}
1654pub mod brdyenb {
1655
1656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1657    pub struct Pipe0Brdye_SPEC;
1658    pub type Pipe0Brdye = crate::EnumBitfieldStruct<u8, Pipe0Brdye_SPEC>;
1659    impl Pipe0Brdye {
1660        #[doc = "Disable interrupt request"]
1661        pub const _0: Self = Self::new(0);
1662
1663        #[doc = "Enable interrupt request"]
1664        pub const _1: Self = Self::new(1);
1665    }
1666    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1667    pub struct Pipe4Brdye_SPEC;
1668    pub type Pipe4Brdye = crate::EnumBitfieldStruct<u8, Pipe4Brdye_SPEC>;
1669    impl Pipe4Brdye {
1670        #[doc = "Disable interrupt request"]
1671        pub const _0: Self = Self::new(0);
1672
1673        #[doc = "Enable interrupt request"]
1674        pub const _1: Self = Self::new(1);
1675    }
1676    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1677    pub struct Pipe5Brdye_SPEC;
1678    pub type Pipe5Brdye = crate::EnumBitfieldStruct<u8, Pipe5Brdye_SPEC>;
1679    impl Pipe5Brdye {
1680        #[doc = "Disable interrupt request"]
1681        pub const _0: Self = Self::new(0);
1682
1683        #[doc = "Enable interrupt request"]
1684        pub const _1: Self = Self::new(1);
1685    }
1686    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1687    pub struct Pipe6Brdye_SPEC;
1688    pub type Pipe6Brdye = crate::EnumBitfieldStruct<u8, Pipe6Brdye_SPEC>;
1689    impl Pipe6Brdye {
1690        #[doc = "Disable interrupt request"]
1691        pub const _0: Self = Self::new(0);
1692
1693        #[doc = "Enable interrupt request"]
1694        pub const _1: Self = Self::new(1);
1695    }
1696    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1697    pub struct Pipe7Brdye_SPEC;
1698    pub type Pipe7Brdye = crate::EnumBitfieldStruct<u8, Pipe7Brdye_SPEC>;
1699    impl Pipe7Brdye {
1700        #[doc = "Disable interrupt request"]
1701        pub const _0: Self = Self::new(0);
1702
1703        #[doc = "Enable interrupt request"]
1704        pub const _1: Self = Self::new(1);
1705    }
1706}
1707#[doc(hidden)]
1708#[derive(Copy, Clone, Eq, PartialEq)]
1709pub struct Nrdyenb_SPEC;
1710impl crate::sealed::RegSpec for Nrdyenb_SPEC {
1711    type DataType = u16;
1712}
1713
1714#[doc = "NRDY Interrupt Enable Register"]
1715pub type Nrdyenb = crate::RegValueT<Nrdyenb_SPEC>;
1716
1717impl Nrdyenb {
1718    #[doc = "NRDY Interrupt Enable for Pipe 0"]
1719    #[inline(always)]
1720    pub fn pipe0nrdye(
1721        self,
1722    ) -> crate::common::RegisterField<
1723        0,
1724        0x1,
1725        1,
1726        0,
1727        nrdyenb::Pipe0Nrdye,
1728        nrdyenb::Pipe0Nrdye,
1729        Nrdyenb_SPEC,
1730        crate::common::RW,
1731    > {
1732        crate::common::RegisterField::<
1733            0,
1734            0x1,
1735            1,
1736            0,
1737            nrdyenb::Pipe0Nrdye,
1738            nrdyenb::Pipe0Nrdye,
1739            Nrdyenb_SPEC,
1740            crate::common::RW,
1741        >::from_register(self, 0)
1742    }
1743
1744    #[doc = "NRDY Interrupt Enable for Pipe 4"]
1745    #[inline(always)]
1746    pub fn pipe4nrdye(
1747        self,
1748    ) -> crate::common::RegisterField<
1749        4,
1750        0x1,
1751        1,
1752        0,
1753        nrdyenb::Pipe4Nrdye,
1754        nrdyenb::Pipe4Nrdye,
1755        Nrdyenb_SPEC,
1756        crate::common::RW,
1757    > {
1758        crate::common::RegisterField::<
1759            4,
1760            0x1,
1761            1,
1762            0,
1763            nrdyenb::Pipe4Nrdye,
1764            nrdyenb::Pipe4Nrdye,
1765            Nrdyenb_SPEC,
1766            crate::common::RW,
1767        >::from_register(self, 0)
1768    }
1769
1770    #[doc = "NRDY Interrupt Enable for Pipe 5"]
1771    #[inline(always)]
1772    pub fn pipe5nrdye(
1773        self,
1774    ) -> crate::common::RegisterField<
1775        5,
1776        0x1,
1777        1,
1778        0,
1779        nrdyenb::Pipe5Nrdye,
1780        nrdyenb::Pipe5Nrdye,
1781        Nrdyenb_SPEC,
1782        crate::common::RW,
1783    > {
1784        crate::common::RegisterField::<
1785            5,
1786            0x1,
1787            1,
1788            0,
1789            nrdyenb::Pipe5Nrdye,
1790            nrdyenb::Pipe5Nrdye,
1791            Nrdyenb_SPEC,
1792            crate::common::RW,
1793        >::from_register(self, 0)
1794    }
1795
1796    #[doc = "NRDY Interrupt Enable for Pipe 6"]
1797    #[inline(always)]
1798    pub fn pipe6nrdye(
1799        self,
1800    ) -> crate::common::RegisterField<
1801        6,
1802        0x1,
1803        1,
1804        0,
1805        nrdyenb::Pipe6Nrdye,
1806        nrdyenb::Pipe6Nrdye,
1807        Nrdyenb_SPEC,
1808        crate::common::RW,
1809    > {
1810        crate::common::RegisterField::<
1811            6,
1812            0x1,
1813            1,
1814            0,
1815            nrdyenb::Pipe6Nrdye,
1816            nrdyenb::Pipe6Nrdye,
1817            Nrdyenb_SPEC,
1818            crate::common::RW,
1819        >::from_register(self, 0)
1820    }
1821
1822    #[doc = "NRDY Interrupt Enable for Pipe 7"]
1823    #[inline(always)]
1824    pub fn pipe7nrdye(
1825        self,
1826    ) -> crate::common::RegisterField<
1827        7,
1828        0x1,
1829        1,
1830        0,
1831        nrdyenb::Pipe7Nrdye,
1832        nrdyenb::Pipe7Nrdye,
1833        Nrdyenb_SPEC,
1834        crate::common::RW,
1835    > {
1836        crate::common::RegisterField::<
1837            7,
1838            0x1,
1839            1,
1840            0,
1841            nrdyenb::Pipe7Nrdye,
1842            nrdyenb::Pipe7Nrdye,
1843            Nrdyenb_SPEC,
1844            crate::common::RW,
1845        >::from_register(self, 0)
1846    }
1847}
1848impl ::core::default::Default for Nrdyenb {
1849    #[inline(always)]
1850    fn default() -> Nrdyenb {
1851        <crate::RegValueT<Nrdyenb_SPEC> as RegisterValue<_>>::new(0)
1852    }
1853}
1854pub mod nrdyenb {
1855
1856    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1857    pub struct Pipe0Nrdye_SPEC;
1858    pub type Pipe0Nrdye = crate::EnumBitfieldStruct<u8, Pipe0Nrdye_SPEC>;
1859    impl Pipe0Nrdye {
1860        #[doc = "Disable interrupt request"]
1861        pub const _0: Self = Self::new(0);
1862
1863        #[doc = "Enable interrupt request"]
1864        pub const _1: Self = Self::new(1);
1865    }
1866    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1867    pub struct Pipe4Nrdye_SPEC;
1868    pub type Pipe4Nrdye = crate::EnumBitfieldStruct<u8, Pipe4Nrdye_SPEC>;
1869    impl Pipe4Nrdye {
1870        #[doc = "Disable interrupt request"]
1871        pub const _0: Self = Self::new(0);
1872
1873        #[doc = "Enable interrupt request"]
1874        pub const _1: Self = Self::new(1);
1875    }
1876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1877    pub struct Pipe5Nrdye_SPEC;
1878    pub type Pipe5Nrdye = crate::EnumBitfieldStruct<u8, Pipe5Nrdye_SPEC>;
1879    impl Pipe5Nrdye {
1880        #[doc = "Disable interrupt request"]
1881        pub const _0: Self = Self::new(0);
1882
1883        #[doc = "Enable interrupt request"]
1884        pub const _1: Self = Self::new(1);
1885    }
1886    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1887    pub struct Pipe6Nrdye_SPEC;
1888    pub type Pipe6Nrdye = crate::EnumBitfieldStruct<u8, Pipe6Nrdye_SPEC>;
1889    impl Pipe6Nrdye {
1890        #[doc = "Disable interrupt request"]
1891        pub const _0: Self = Self::new(0);
1892
1893        #[doc = "Enable interrupt request"]
1894        pub const _1: Self = Self::new(1);
1895    }
1896    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1897    pub struct Pipe7Nrdye_SPEC;
1898    pub type Pipe7Nrdye = crate::EnumBitfieldStruct<u8, Pipe7Nrdye_SPEC>;
1899    impl Pipe7Nrdye {
1900        #[doc = "Disable interrupt request"]
1901        pub const _0: Self = Self::new(0);
1902
1903        #[doc = "Enable interrupt request"]
1904        pub const _1: Self = Self::new(1);
1905    }
1906}
1907#[doc(hidden)]
1908#[derive(Copy, Clone, Eq, PartialEq)]
1909pub struct Bempenb_SPEC;
1910impl crate::sealed::RegSpec for Bempenb_SPEC {
1911    type DataType = u16;
1912}
1913
1914#[doc = "BEMP Interrupt Enable Register"]
1915pub type Bempenb = crate::RegValueT<Bempenb_SPEC>;
1916
1917impl Bempenb {
1918    #[doc = "BEMP Interrupt Enable for Pipe 0"]
1919    #[inline(always)]
1920    pub fn pipe0bempe(
1921        self,
1922    ) -> crate::common::RegisterField<
1923        0,
1924        0x1,
1925        1,
1926        0,
1927        bempenb::Pipe0Bempe,
1928        bempenb::Pipe0Bempe,
1929        Bempenb_SPEC,
1930        crate::common::RW,
1931    > {
1932        crate::common::RegisterField::<
1933            0,
1934            0x1,
1935            1,
1936            0,
1937            bempenb::Pipe0Bempe,
1938            bempenb::Pipe0Bempe,
1939            Bempenb_SPEC,
1940            crate::common::RW,
1941        >::from_register(self, 0)
1942    }
1943
1944    #[doc = "BEMP Interrupt Enable for Pipe 4"]
1945    #[inline(always)]
1946    pub fn pipe4bempe(
1947        self,
1948    ) -> crate::common::RegisterField<
1949        4,
1950        0x1,
1951        1,
1952        0,
1953        bempenb::Pipe4Bempe,
1954        bempenb::Pipe4Bempe,
1955        Bempenb_SPEC,
1956        crate::common::RW,
1957    > {
1958        crate::common::RegisterField::<
1959            4,
1960            0x1,
1961            1,
1962            0,
1963            bempenb::Pipe4Bempe,
1964            bempenb::Pipe4Bempe,
1965            Bempenb_SPEC,
1966            crate::common::RW,
1967        >::from_register(self, 0)
1968    }
1969
1970    #[doc = "BEMP Interrupt Enable for Pipe 5"]
1971    #[inline(always)]
1972    pub fn pipe5bempe(
1973        self,
1974    ) -> crate::common::RegisterField<
1975        5,
1976        0x1,
1977        1,
1978        0,
1979        bempenb::Pipe5Bempe,
1980        bempenb::Pipe5Bempe,
1981        Bempenb_SPEC,
1982        crate::common::RW,
1983    > {
1984        crate::common::RegisterField::<
1985            5,
1986            0x1,
1987            1,
1988            0,
1989            bempenb::Pipe5Bempe,
1990            bempenb::Pipe5Bempe,
1991            Bempenb_SPEC,
1992            crate::common::RW,
1993        >::from_register(self, 0)
1994    }
1995
1996    #[doc = "BEMP Interrupt Enable for Pipe 6"]
1997    #[inline(always)]
1998    pub fn pipe6bempe(
1999        self,
2000    ) -> crate::common::RegisterField<
2001        6,
2002        0x1,
2003        1,
2004        0,
2005        bempenb::Pipe6Bempe,
2006        bempenb::Pipe6Bempe,
2007        Bempenb_SPEC,
2008        crate::common::RW,
2009    > {
2010        crate::common::RegisterField::<
2011            6,
2012            0x1,
2013            1,
2014            0,
2015            bempenb::Pipe6Bempe,
2016            bempenb::Pipe6Bempe,
2017            Bempenb_SPEC,
2018            crate::common::RW,
2019        >::from_register(self, 0)
2020    }
2021
2022    #[doc = "BEMP Interrupt Enable for Pipe 7"]
2023    #[inline(always)]
2024    pub fn pipe7bempe(
2025        self,
2026    ) -> crate::common::RegisterField<
2027        7,
2028        0x1,
2029        1,
2030        0,
2031        bempenb::Pipe7Bempe,
2032        bempenb::Pipe7Bempe,
2033        Bempenb_SPEC,
2034        crate::common::RW,
2035    > {
2036        crate::common::RegisterField::<
2037            7,
2038            0x1,
2039            1,
2040            0,
2041            bempenb::Pipe7Bempe,
2042            bempenb::Pipe7Bempe,
2043            Bempenb_SPEC,
2044            crate::common::RW,
2045        >::from_register(self, 0)
2046    }
2047}
2048impl ::core::default::Default for Bempenb {
2049    #[inline(always)]
2050    fn default() -> Bempenb {
2051        <crate::RegValueT<Bempenb_SPEC> as RegisterValue<_>>::new(0)
2052    }
2053}
2054pub mod bempenb {
2055
2056    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2057    pub struct Pipe0Bempe_SPEC;
2058    pub type Pipe0Bempe = crate::EnumBitfieldStruct<u8, Pipe0Bempe_SPEC>;
2059    impl Pipe0Bempe {
2060        #[doc = "Disable interrupt request"]
2061        pub const _0: Self = Self::new(0);
2062
2063        #[doc = "Enable interrupt request"]
2064        pub const _1: Self = Self::new(1);
2065    }
2066    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2067    pub struct Pipe4Bempe_SPEC;
2068    pub type Pipe4Bempe = crate::EnumBitfieldStruct<u8, Pipe4Bempe_SPEC>;
2069    impl Pipe4Bempe {
2070        #[doc = "Disable interrupt request"]
2071        pub const _0: Self = Self::new(0);
2072
2073        #[doc = "Enable interrupt request"]
2074        pub const _1: Self = Self::new(1);
2075    }
2076    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2077    pub struct Pipe5Bempe_SPEC;
2078    pub type Pipe5Bempe = crate::EnumBitfieldStruct<u8, Pipe5Bempe_SPEC>;
2079    impl Pipe5Bempe {
2080        #[doc = "Disable interrupt request"]
2081        pub const _0: Self = Self::new(0);
2082
2083        #[doc = "Enable interrupt request"]
2084        pub const _1: Self = Self::new(1);
2085    }
2086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2087    pub struct Pipe6Bempe_SPEC;
2088    pub type Pipe6Bempe = crate::EnumBitfieldStruct<u8, Pipe6Bempe_SPEC>;
2089    impl Pipe6Bempe {
2090        #[doc = "Disable interrupt request"]
2091        pub const _0: Self = Self::new(0);
2092
2093        #[doc = "Enable interrupt request"]
2094        pub const _1: Self = Self::new(1);
2095    }
2096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2097    pub struct Pipe7Bempe_SPEC;
2098    pub type Pipe7Bempe = crate::EnumBitfieldStruct<u8, Pipe7Bempe_SPEC>;
2099    impl Pipe7Bempe {
2100        #[doc = "Disable interrupt request"]
2101        pub const _0: Self = Self::new(0);
2102
2103        #[doc = "Enable interrupt request"]
2104        pub const _1: Self = Self::new(1);
2105    }
2106}
2107#[doc(hidden)]
2108#[derive(Copy, Clone, Eq, PartialEq)]
2109pub struct Sofcfg_SPEC;
2110impl crate::sealed::RegSpec for Sofcfg_SPEC {
2111    type DataType = u16;
2112}
2113
2114#[doc = "SOF Output Configuration Register"]
2115pub type Sofcfg = crate::RegValueT<Sofcfg_SPEC>;
2116
2117impl Sofcfg {
2118    #[doc = "Edge Interrupt Output Status Monitor"]
2119    #[inline(always)]
2120    pub fn edgests(
2121        self,
2122    ) -> crate::common::RegisterFieldBool<4, 1, 0, Sofcfg_SPEC, crate::common::R> {
2123        crate::common::RegisterFieldBool::<4, 1, 0, Sofcfg_SPEC, crate::common::R>::from_register(
2124            self, 0,
2125        )
2126    }
2127
2128    #[doc = "BRDY Interrupt Status Clear Timing"]
2129    #[inline(always)]
2130    pub fn brdym(
2131        self,
2132    ) -> crate::common::RegisterField<
2133        6,
2134        0x1,
2135        1,
2136        0,
2137        sofcfg::Brdym,
2138        sofcfg::Brdym,
2139        Sofcfg_SPEC,
2140        crate::common::RW,
2141    > {
2142        crate::common::RegisterField::<
2143            6,
2144            0x1,
2145            1,
2146            0,
2147            sofcfg::Brdym,
2148            sofcfg::Brdym,
2149            Sofcfg_SPEC,
2150            crate::common::RW,
2151        >::from_register(self, 0)
2152    }
2153}
2154impl ::core::default::Default for Sofcfg {
2155    #[inline(always)]
2156    fn default() -> Sofcfg {
2157        <crate::RegValueT<Sofcfg_SPEC> as RegisterValue<_>>::new(0)
2158    }
2159}
2160pub mod sofcfg {
2161
2162    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2163    pub struct Brdym_SPEC;
2164    pub type Brdym = crate::EnumBitfieldStruct<u8, Brdym_SPEC>;
2165    impl Brdym {
2166        #[doc = "Clear BRDY flag by software"]
2167        pub const _0: Self = Self::new(0);
2168
2169        #[doc = "Clear BRDY flag by the USBFS through a data read from the FIFO buffer or data write to the FIFO buffer"]
2170        pub const _1: Self = Self::new(1);
2171    }
2172}
2173#[doc(hidden)]
2174#[derive(Copy, Clone, Eq, PartialEq)]
2175pub struct Intsts0_SPEC;
2176impl crate::sealed::RegSpec for Intsts0_SPEC {
2177    type DataType = u16;
2178}
2179
2180#[doc = "Interrupt Status Register 0"]
2181pub type Intsts0 = crate::RegValueT<Intsts0_SPEC>;
2182
2183impl Intsts0 {
2184    #[doc = "Control Transfer Stage"]
2185    #[inline(always)]
2186    pub fn ctsq(
2187        self,
2188    ) -> crate::common::RegisterField<
2189        0,
2190        0x7,
2191        1,
2192        0,
2193        intsts0::Ctsq,
2194        intsts0::Ctsq,
2195        Intsts0_SPEC,
2196        crate::common::R,
2197    > {
2198        crate::common::RegisterField::<
2199            0,
2200            0x7,
2201            1,
2202            0,
2203            intsts0::Ctsq,
2204            intsts0::Ctsq,
2205            Intsts0_SPEC,
2206            crate::common::R,
2207        >::from_register(self, 0)
2208    }
2209
2210    #[doc = "USB Request Reception"]
2211    #[inline(always)]
2212    pub fn valid(
2213        self,
2214    ) -> crate::common::RegisterField<
2215        3,
2216        0x1,
2217        1,
2218        0,
2219        intsts0::Valid,
2220        intsts0::Valid,
2221        Intsts0_SPEC,
2222        crate::common::RW,
2223    > {
2224        crate::common::RegisterField::<
2225            3,
2226            0x1,
2227            1,
2228            0,
2229            intsts0::Valid,
2230            intsts0::Valid,
2231            Intsts0_SPEC,
2232            crate::common::RW,
2233        >::from_register(self, 0)
2234    }
2235
2236    #[doc = "Device State"]
2237    #[inline(always)]
2238    pub fn dvsq(
2239        self,
2240    ) -> crate::common::RegisterField<
2241        4,
2242        0x7,
2243        1,
2244        0,
2245        intsts0::Dvsq,
2246        intsts0::Dvsq,
2247        Intsts0_SPEC,
2248        crate::common::R,
2249    > {
2250        crate::common::RegisterField::<
2251            4,
2252            0x7,
2253            1,
2254            0,
2255            intsts0::Dvsq,
2256            intsts0::Dvsq,
2257            Intsts0_SPEC,
2258            crate::common::R,
2259        >::from_register(self, 0)
2260    }
2261
2262    #[doc = "VBUS Input Status"]
2263    #[inline(always)]
2264    pub fn vbsts(
2265        self,
2266    ) -> crate::common::RegisterField<
2267        7,
2268        0x1,
2269        1,
2270        0,
2271        intsts0::Vbsts,
2272        intsts0::Vbsts,
2273        Intsts0_SPEC,
2274        crate::common::R,
2275    > {
2276        crate::common::RegisterField::<
2277            7,
2278            0x1,
2279            1,
2280            0,
2281            intsts0::Vbsts,
2282            intsts0::Vbsts,
2283            Intsts0_SPEC,
2284            crate::common::R,
2285        >::from_register(self, 0)
2286    }
2287
2288    #[doc = "Buffer Ready Interrupt Status"]
2289    #[inline(always)]
2290    pub fn brdy(
2291        self,
2292    ) -> crate::common::RegisterField<
2293        8,
2294        0x1,
2295        1,
2296        0,
2297        intsts0::Brdy,
2298        intsts0::Brdy,
2299        Intsts0_SPEC,
2300        crate::common::R,
2301    > {
2302        crate::common::RegisterField::<
2303            8,
2304            0x1,
2305            1,
2306            0,
2307            intsts0::Brdy,
2308            intsts0::Brdy,
2309            Intsts0_SPEC,
2310            crate::common::R,
2311        >::from_register(self, 0)
2312    }
2313
2314    #[doc = "Buffer Not Ready Interrupt Status"]
2315    #[inline(always)]
2316    pub fn nrdy(
2317        self,
2318    ) -> crate::common::RegisterField<
2319        9,
2320        0x1,
2321        1,
2322        0,
2323        intsts0::Nrdy,
2324        intsts0::Nrdy,
2325        Intsts0_SPEC,
2326        crate::common::R,
2327    > {
2328        crate::common::RegisterField::<
2329            9,
2330            0x1,
2331            1,
2332            0,
2333            intsts0::Nrdy,
2334            intsts0::Nrdy,
2335            Intsts0_SPEC,
2336            crate::common::R,
2337        >::from_register(self, 0)
2338    }
2339
2340    #[doc = "Buffer Empty Interrupt Status"]
2341    #[inline(always)]
2342    pub fn bemp(
2343        self,
2344    ) -> crate::common::RegisterField<
2345        10,
2346        0x1,
2347        1,
2348        0,
2349        intsts0::Bemp,
2350        intsts0::Bemp,
2351        Intsts0_SPEC,
2352        crate::common::R,
2353    > {
2354        crate::common::RegisterField::<
2355            10,
2356            0x1,
2357            1,
2358            0,
2359            intsts0::Bemp,
2360            intsts0::Bemp,
2361            Intsts0_SPEC,
2362            crate::common::R,
2363        >::from_register(self, 0)
2364    }
2365
2366    #[doc = "Control Transfer Stage Transition Interrupt Status"]
2367    #[inline(always)]
2368    pub fn ctrt(
2369        self,
2370    ) -> crate::common::RegisterField<
2371        11,
2372        0x1,
2373        1,
2374        0,
2375        intsts0::Ctrt,
2376        intsts0::Ctrt,
2377        Intsts0_SPEC,
2378        crate::common::RW,
2379    > {
2380        crate::common::RegisterField::<
2381            11,
2382            0x1,
2383            1,
2384            0,
2385            intsts0::Ctrt,
2386            intsts0::Ctrt,
2387            Intsts0_SPEC,
2388            crate::common::RW,
2389        >::from_register(self, 0)
2390    }
2391
2392    #[doc = "Device State Transition Interrupt Status"]
2393    #[inline(always)]
2394    pub fn dvst(
2395        self,
2396    ) -> crate::common::RegisterField<
2397        12,
2398        0x1,
2399        1,
2400        0,
2401        intsts0::Dvst,
2402        intsts0::Dvst,
2403        Intsts0_SPEC,
2404        crate::common::RW,
2405    > {
2406        crate::common::RegisterField::<
2407            12,
2408            0x1,
2409            1,
2410            0,
2411            intsts0::Dvst,
2412            intsts0::Dvst,
2413            Intsts0_SPEC,
2414            crate::common::RW,
2415        >::from_register(self, 0)
2416    }
2417
2418    #[doc = "Frame Number Refresh Interrupt Status"]
2419    #[inline(always)]
2420    pub fn sofr(
2421        self,
2422    ) -> crate::common::RegisterField<
2423        13,
2424        0x1,
2425        1,
2426        0,
2427        intsts0::Sofr,
2428        intsts0::Sofr,
2429        Intsts0_SPEC,
2430        crate::common::RW,
2431    > {
2432        crate::common::RegisterField::<
2433            13,
2434            0x1,
2435            1,
2436            0,
2437            intsts0::Sofr,
2438            intsts0::Sofr,
2439            Intsts0_SPEC,
2440            crate::common::RW,
2441        >::from_register(self, 0)
2442    }
2443
2444    #[doc = "Resume Interrupt Status"]
2445    #[inline(always)]
2446    pub fn resm(
2447        self,
2448    ) -> crate::common::RegisterField<
2449        14,
2450        0x1,
2451        1,
2452        0,
2453        intsts0::Resm,
2454        intsts0::Resm,
2455        Intsts0_SPEC,
2456        crate::common::RW,
2457    > {
2458        crate::common::RegisterField::<
2459            14,
2460            0x1,
2461            1,
2462            0,
2463            intsts0::Resm,
2464            intsts0::Resm,
2465            Intsts0_SPEC,
2466            crate::common::RW,
2467        >::from_register(self, 0)
2468    }
2469
2470    #[doc = "VBUS Interrupt Status"]
2471    #[inline(always)]
2472    pub fn vbint(
2473        self,
2474    ) -> crate::common::RegisterField<
2475        15,
2476        0x1,
2477        1,
2478        0,
2479        intsts0::Vbint,
2480        intsts0::Vbint,
2481        Intsts0_SPEC,
2482        crate::common::RW,
2483    > {
2484        crate::common::RegisterField::<
2485            15,
2486            0x1,
2487            1,
2488            0,
2489            intsts0::Vbint,
2490            intsts0::Vbint,
2491            Intsts0_SPEC,
2492            crate::common::RW,
2493        >::from_register(self, 0)
2494    }
2495}
2496impl ::core::default::Default for Intsts0 {
2497    #[inline(always)]
2498    fn default() -> Intsts0 {
2499        <crate::RegValueT<Intsts0_SPEC> as RegisterValue<_>>::new(0)
2500    }
2501}
2502pub mod intsts0 {
2503
2504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2505    pub struct Ctsq_SPEC;
2506    pub type Ctsq = crate::EnumBitfieldStruct<u8, Ctsq_SPEC>;
2507    impl Ctsq {
2508        #[doc = "Idle or setup stage"]
2509        pub const _000: Self = Self::new(0);
2510
2511        #[doc = "Control read data stage"]
2512        pub const _001: Self = Self::new(1);
2513
2514        #[doc = "Control read status stage"]
2515        pub const _010: Self = Self::new(2);
2516
2517        #[doc = "Control write data stage"]
2518        pub const _011: Self = Self::new(3);
2519
2520        #[doc = "Control write status stage"]
2521        pub const _100: Self = Self::new(4);
2522
2523        #[doc = "Control write (no data) status stage"]
2524        pub const _101: Self = Self::new(5);
2525
2526        #[doc = "Control transfer sequence error"]
2527        pub const _110: Self = Self::new(6);
2528    }
2529    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2530    pub struct Valid_SPEC;
2531    pub type Valid = crate::EnumBitfieldStruct<u8, Valid_SPEC>;
2532    impl Valid {
2533        #[doc = "Setup packet not received"]
2534        pub const _0: Self = Self::new(0);
2535
2536        #[doc = "Setup packet received"]
2537        pub const _1: Self = Self::new(1);
2538    }
2539    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2540    pub struct Dvsq_SPEC;
2541    pub type Dvsq = crate::EnumBitfieldStruct<u8, Dvsq_SPEC>;
2542    impl Dvsq {
2543        #[doc = "Powered state"]
2544        pub const _000: Self = Self::new(0);
2545
2546        #[doc = "Default state"]
2547        pub const _001: Self = Self::new(1);
2548
2549        #[doc = "Address state"]
2550        pub const _010: Self = Self::new(2);
2551
2552        #[doc = "Configured state"]
2553        pub const _011: Self = Self::new(3);
2554    }
2555    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2556    pub struct Vbsts_SPEC;
2557    pub type Vbsts = crate::EnumBitfieldStruct<u8, Vbsts_SPEC>;
2558    impl Vbsts {
2559        #[doc = "USB_VBUS pin is low"]
2560        pub const _0: Self = Self::new(0);
2561
2562        #[doc = "USB_VBUS pin is high"]
2563        pub const _1: Self = Self::new(1);
2564    }
2565    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2566    pub struct Brdy_SPEC;
2567    pub type Brdy = crate::EnumBitfieldStruct<u8, Brdy_SPEC>;
2568    impl Brdy {
2569        #[doc = "No BRDY interrupt occurred"]
2570        pub const _0: Self = Self::new(0);
2571
2572        #[doc = "BRDY interrupt occurred"]
2573        pub const _1: Self = Self::new(1);
2574    }
2575    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2576    pub struct Nrdy_SPEC;
2577    pub type Nrdy = crate::EnumBitfieldStruct<u8, Nrdy_SPEC>;
2578    impl Nrdy {
2579        #[doc = "No NRDY interrupt occurred"]
2580        pub const _0: Self = Self::new(0);
2581
2582        #[doc = "NRDY interrupt occurred"]
2583        pub const _1: Self = Self::new(1);
2584    }
2585    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2586    pub struct Bemp_SPEC;
2587    pub type Bemp = crate::EnumBitfieldStruct<u8, Bemp_SPEC>;
2588    impl Bemp {
2589        #[doc = "No BEMP interrupt occurred"]
2590        pub const _0: Self = Self::new(0);
2591
2592        #[doc = "BEMP interrupt occurred"]
2593        pub const _1: Self = Self::new(1);
2594    }
2595    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2596    pub struct Ctrt_SPEC;
2597    pub type Ctrt = crate::EnumBitfieldStruct<u8, Ctrt_SPEC>;
2598    impl Ctrt {
2599        #[doc = "No control transfer stage transition interrupt occurred"]
2600        pub const _0: Self = Self::new(0);
2601
2602        #[doc = "Control transfer stage transition interrupt occurred"]
2603        pub const _1: Self = Self::new(1);
2604    }
2605    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2606    pub struct Dvst_SPEC;
2607    pub type Dvst = crate::EnumBitfieldStruct<u8, Dvst_SPEC>;
2608    impl Dvst {
2609        #[doc = "No device state transition interrupt occurred"]
2610        pub const _0: Self = Self::new(0);
2611
2612        #[doc = "Device state transition interrupt occurred"]
2613        pub const _1: Self = Self::new(1);
2614    }
2615    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2616    pub struct Sofr_SPEC;
2617    pub type Sofr = crate::EnumBitfieldStruct<u8, Sofr_SPEC>;
2618    impl Sofr {
2619        #[doc = "No SOF interrupt occurred"]
2620        pub const _0: Self = Self::new(0);
2621
2622        #[doc = "SOF interrupt occurred"]
2623        pub const _1: Self = Self::new(1);
2624    }
2625    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2626    pub struct Resm_SPEC;
2627    pub type Resm = crate::EnumBitfieldStruct<u8, Resm_SPEC>;
2628    impl Resm {
2629        #[doc = "No resume interrupt occurred"]
2630        pub const _0: Self = Self::new(0);
2631
2632        #[doc = "Resume interrupt occurred"]
2633        pub const _1: Self = Self::new(1);
2634    }
2635    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2636    pub struct Vbint_SPEC;
2637    pub type Vbint = crate::EnumBitfieldStruct<u8, Vbint_SPEC>;
2638    impl Vbint {
2639        #[doc = "No VBUS interrupt occurred"]
2640        pub const _0: Self = Self::new(0);
2641
2642        #[doc = "VBUS interrupt occurred"]
2643        pub const _1: Self = Self::new(1);
2644    }
2645}
2646#[doc(hidden)]
2647#[derive(Copy, Clone, Eq, PartialEq)]
2648pub struct Brdysts_SPEC;
2649impl crate::sealed::RegSpec for Brdysts_SPEC {
2650    type DataType = u16;
2651}
2652
2653#[doc = "BRDY Interrupt Status Register"]
2654pub type Brdysts = crate::RegValueT<Brdysts_SPEC>;
2655
2656impl Brdysts {
2657    #[doc = "BRDY Interrupt Status for Pipe 0"]
2658    #[inline(always)]
2659    pub fn pipe0brdy(
2660        self,
2661    ) -> crate::common::RegisterField<
2662        0,
2663        0x1,
2664        1,
2665        0,
2666        brdysts::Pipe0Brdy,
2667        brdysts::Pipe0Brdy,
2668        Brdysts_SPEC,
2669        crate::common::RW,
2670    > {
2671        crate::common::RegisterField::<
2672            0,
2673            0x1,
2674            1,
2675            0,
2676            brdysts::Pipe0Brdy,
2677            brdysts::Pipe0Brdy,
2678            Brdysts_SPEC,
2679            crate::common::RW,
2680        >::from_register(self, 0)
2681    }
2682
2683    #[doc = "BRDY Interrupt Status for Pipe 4"]
2684    #[inline(always)]
2685    pub fn pipe4brdy(
2686        self,
2687    ) -> crate::common::RegisterField<
2688        4,
2689        0x1,
2690        1,
2691        0,
2692        brdysts::Pipe4Brdy,
2693        brdysts::Pipe4Brdy,
2694        Brdysts_SPEC,
2695        crate::common::RW,
2696    > {
2697        crate::common::RegisterField::<
2698            4,
2699            0x1,
2700            1,
2701            0,
2702            brdysts::Pipe4Brdy,
2703            brdysts::Pipe4Brdy,
2704            Brdysts_SPEC,
2705            crate::common::RW,
2706        >::from_register(self, 0)
2707    }
2708
2709    #[doc = "BRDY Interrupt Status for Pipe 5"]
2710    #[inline(always)]
2711    pub fn pipe5brdy(
2712        self,
2713    ) -> crate::common::RegisterField<
2714        5,
2715        0x1,
2716        1,
2717        0,
2718        brdysts::Pipe5Brdy,
2719        brdysts::Pipe5Brdy,
2720        Brdysts_SPEC,
2721        crate::common::RW,
2722    > {
2723        crate::common::RegisterField::<
2724            5,
2725            0x1,
2726            1,
2727            0,
2728            brdysts::Pipe5Brdy,
2729            brdysts::Pipe5Brdy,
2730            Brdysts_SPEC,
2731            crate::common::RW,
2732        >::from_register(self, 0)
2733    }
2734
2735    #[doc = "BRDY Interrupt Status for Pipe 6"]
2736    #[inline(always)]
2737    pub fn pipe6brdy(
2738        self,
2739    ) -> crate::common::RegisterField<
2740        6,
2741        0x1,
2742        1,
2743        0,
2744        brdysts::Pipe6Brdy,
2745        brdysts::Pipe6Brdy,
2746        Brdysts_SPEC,
2747        crate::common::RW,
2748    > {
2749        crate::common::RegisterField::<
2750            6,
2751            0x1,
2752            1,
2753            0,
2754            brdysts::Pipe6Brdy,
2755            brdysts::Pipe6Brdy,
2756            Brdysts_SPEC,
2757            crate::common::RW,
2758        >::from_register(self, 0)
2759    }
2760
2761    #[doc = "BRDY Interrupt Status for Pipe 7"]
2762    #[inline(always)]
2763    pub fn pipe7brdy(
2764        self,
2765    ) -> crate::common::RegisterField<
2766        7,
2767        0x1,
2768        1,
2769        0,
2770        brdysts::Pipe7Brdy,
2771        brdysts::Pipe7Brdy,
2772        Brdysts_SPEC,
2773        crate::common::RW,
2774    > {
2775        crate::common::RegisterField::<
2776            7,
2777            0x1,
2778            1,
2779            0,
2780            brdysts::Pipe7Brdy,
2781            brdysts::Pipe7Brdy,
2782            Brdysts_SPEC,
2783            crate::common::RW,
2784        >::from_register(self, 0)
2785    }
2786}
2787impl ::core::default::Default for Brdysts {
2788    #[inline(always)]
2789    fn default() -> Brdysts {
2790        <crate::RegValueT<Brdysts_SPEC> as RegisterValue<_>>::new(0)
2791    }
2792}
2793pub mod brdysts {
2794
2795    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2796    pub struct Pipe0Brdy_SPEC;
2797    pub type Pipe0Brdy = crate::EnumBitfieldStruct<u8, Pipe0Brdy_SPEC>;
2798    impl Pipe0Brdy {
2799        #[doc = "No BRDY interrupt occurred"]
2800        pub const _0: Self = Self::new(0);
2801
2802        #[doc = "BRDY interrupt occurred"]
2803        pub const _1: Self = Self::new(1);
2804    }
2805    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2806    pub struct Pipe4Brdy_SPEC;
2807    pub type Pipe4Brdy = crate::EnumBitfieldStruct<u8, Pipe4Brdy_SPEC>;
2808    impl Pipe4Brdy {
2809        #[doc = "No BRDY interrupt occurred"]
2810        pub const _0: Self = Self::new(0);
2811
2812        #[doc = "BRDY interrupt occurred"]
2813        pub const _1: Self = Self::new(1);
2814    }
2815    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2816    pub struct Pipe5Brdy_SPEC;
2817    pub type Pipe5Brdy = crate::EnumBitfieldStruct<u8, Pipe5Brdy_SPEC>;
2818    impl Pipe5Brdy {
2819        #[doc = "No BRDY interrupt occurred"]
2820        pub const _0: Self = Self::new(0);
2821
2822        #[doc = "BRDY interrupt occurred"]
2823        pub const _1: Self = Self::new(1);
2824    }
2825    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2826    pub struct Pipe6Brdy_SPEC;
2827    pub type Pipe6Brdy = crate::EnumBitfieldStruct<u8, Pipe6Brdy_SPEC>;
2828    impl Pipe6Brdy {
2829        #[doc = "No BRDY interrupt occurred"]
2830        pub const _0: Self = Self::new(0);
2831
2832        #[doc = "BRDY interrupt occurred"]
2833        pub const _1: Self = Self::new(1);
2834    }
2835    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2836    pub struct Pipe7Brdy_SPEC;
2837    pub type Pipe7Brdy = crate::EnumBitfieldStruct<u8, Pipe7Brdy_SPEC>;
2838    impl Pipe7Brdy {
2839        #[doc = "No BRDY interrupt occurred"]
2840        pub const _0: Self = Self::new(0);
2841
2842        #[doc = "BRDY interrupt occurred"]
2843        pub const _1: Self = Self::new(1);
2844    }
2845}
2846#[doc(hidden)]
2847#[derive(Copy, Clone, Eq, PartialEq)]
2848pub struct Nrdysts_SPEC;
2849impl crate::sealed::RegSpec for Nrdysts_SPEC {
2850    type DataType = u16;
2851}
2852
2853#[doc = "NRDY Interrupt Status Register"]
2854pub type Nrdysts = crate::RegValueT<Nrdysts_SPEC>;
2855
2856impl Nrdysts {
2857    #[doc = "NRDY Interrupt Status for Pipe 0"]
2858    #[inline(always)]
2859    pub fn pipe0nrdy(
2860        self,
2861    ) -> crate::common::RegisterField<
2862        0,
2863        0x1,
2864        1,
2865        0,
2866        nrdysts::Pipe0Nrdy,
2867        nrdysts::Pipe0Nrdy,
2868        Nrdysts_SPEC,
2869        crate::common::RW,
2870    > {
2871        crate::common::RegisterField::<
2872            0,
2873            0x1,
2874            1,
2875            0,
2876            nrdysts::Pipe0Nrdy,
2877            nrdysts::Pipe0Nrdy,
2878            Nrdysts_SPEC,
2879            crate::common::RW,
2880        >::from_register(self, 0)
2881    }
2882
2883    #[doc = "NRDY Interrupt Status for Pipe 4"]
2884    #[inline(always)]
2885    pub fn pipe4nrdy(
2886        self,
2887    ) -> crate::common::RegisterField<
2888        4,
2889        0x1,
2890        1,
2891        0,
2892        nrdysts::Pipe4Nrdy,
2893        nrdysts::Pipe4Nrdy,
2894        Nrdysts_SPEC,
2895        crate::common::RW,
2896    > {
2897        crate::common::RegisterField::<
2898            4,
2899            0x1,
2900            1,
2901            0,
2902            nrdysts::Pipe4Nrdy,
2903            nrdysts::Pipe4Nrdy,
2904            Nrdysts_SPEC,
2905            crate::common::RW,
2906        >::from_register(self, 0)
2907    }
2908
2909    #[doc = "NRDY Interrupt Status for Pipe 5"]
2910    #[inline(always)]
2911    pub fn pipe5nrdy(
2912        self,
2913    ) -> crate::common::RegisterField<
2914        5,
2915        0x1,
2916        1,
2917        0,
2918        nrdysts::Pipe5Nrdy,
2919        nrdysts::Pipe5Nrdy,
2920        Nrdysts_SPEC,
2921        crate::common::RW,
2922    > {
2923        crate::common::RegisterField::<
2924            5,
2925            0x1,
2926            1,
2927            0,
2928            nrdysts::Pipe5Nrdy,
2929            nrdysts::Pipe5Nrdy,
2930            Nrdysts_SPEC,
2931            crate::common::RW,
2932        >::from_register(self, 0)
2933    }
2934
2935    #[doc = "NRDY Interrupt Status for Pipe 6"]
2936    #[inline(always)]
2937    pub fn pipe6nrdy(
2938        self,
2939    ) -> crate::common::RegisterField<
2940        6,
2941        0x1,
2942        1,
2943        0,
2944        nrdysts::Pipe6Nrdy,
2945        nrdysts::Pipe6Nrdy,
2946        Nrdysts_SPEC,
2947        crate::common::RW,
2948    > {
2949        crate::common::RegisterField::<
2950            6,
2951            0x1,
2952            1,
2953            0,
2954            nrdysts::Pipe6Nrdy,
2955            nrdysts::Pipe6Nrdy,
2956            Nrdysts_SPEC,
2957            crate::common::RW,
2958        >::from_register(self, 0)
2959    }
2960
2961    #[doc = "NRDY Interrupt Status for Pipe 7"]
2962    #[inline(always)]
2963    pub fn pipe7nrdy(
2964        self,
2965    ) -> crate::common::RegisterField<
2966        7,
2967        0x1,
2968        1,
2969        0,
2970        nrdysts::Pipe7Nrdy,
2971        nrdysts::Pipe7Nrdy,
2972        Nrdysts_SPEC,
2973        crate::common::RW,
2974    > {
2975        crate::common::RegisterField::<
2976            7,
2977            0x1,
2978            1,
2979            0,
2980            nrdysts::Pipe7Nrdy,
2981            nrdysts::Pipe7Nrdy,
2982            Nrdysts_SPEC,
2983            crate::common::RW,
2984        >::from_register(self, 0)
2985    }
2986}
2987impl ::core::default::Default for Nrdysts {
2988    #[inline(always)]
2989    fn default() -> Nrdysts {
2990        <crate::RegValueT<Nrdysts_SPEC> as RegisterValue<_>>::new(0)
2991    }
2992}
2993pub mod nrdysts {
2994
2995    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2996    pub struct Pipe0Nrdy_SPEC;
2997    pub type Pipe0Nrdy = crate::EnumBitfieldStruct<u8, Pipe0Nrdy_SPEC>;
2998    impl Pipe0Nrdy {
2999        #[doc = "No NRDY interrupt occurred"]
3000        pub const _0: Self = Self::new(0);
3001
3002        #[doc = "NRDY interrupt occurred"]
3003        pub const _1: Self = Self::new(1);
3004    }
3005    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3006    pub struct Pipe4Nrdy_SPEC;
3007    pub type Pipe4Nrdy = crate::EnumBitfieldStruct<u8, Pipe4Nrdy_SPEC>;
3008    impl Pipe4Nrdy {
3009        #[doc = "No NRDY interrupt occurred"]
3010        pub const _0: Self = Self::new(0);
3011
3012        #[doc = "NRDY interrupt occurred"]
3013        pub const _1: Self = Self::new(1);
3014    }
3015    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3016    pub struct Pipe5Nrdy_SPEC;
3017    pub type Pipe5Nrdy = crate::EnumBitfieldStruct<u8, Pipe5Nrdy_SPEC>;
3018    impl Pipe5Nrdy {
3019        #[doc = "No NRDY interrupt occurred"]
3020        pub const _0: Self = Self::new(0);
3021
3022        #[doc = "NRDY interrupt occurred"]
3023        pub const _1: Self = Self::new(1);
3024    }
3025    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3026    pub struct Pipe6Nrdy_SPEC;
3027    pub type Pipe6Nrdy = crate::EnumBitfieldStruct<u8, Pipe6Nrdy_SPEC>;
3028    impl Pipe6Nrdy {
3029        #[doc = "No NRDY interrupt occurred"]
3030        pub const _0: Self = Self::new(0);
3031
3032        #[doc = "NRDY interrupt occurred"]
3033        pub const _1: Self = Self::new(1);
3034    }
3035    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3036    pub struct Pipe7Nrdy_SPEC;
3037    pub type Pipe7Nrdy = crate::EnumBitfieldStruct<u8, Pipe7Nrdy_SPEC>;
3038    impl Pipe7Nrdy {
3039        #[doc = "No NRDY interrupt occurred"]
3040        pub const _0: Self = Self::new(0);
3041
3042        #[doc = "NRDY interrupt occurred"]
3043        pub const _1: Self = Self::new(1);
3044    }
3045}
3046#[doc(hidden)]
3047#[derive(Copy, Clone, Eq, PartialEq)]
3048pub struct Bempsts_SPEC;
3049impl crate::sealed::RegSpec for Bempsts_SPEC {
3050    type DataType = u16;
3051}
3052
3053#[doc = "BEMP Interrupt Status Register"]
3054pub type Bempsts = crate::RegValueT<Bempsts_SPEC>;
3055
3056impl Bempsts {
3057    #[doc = "BEMP Interrupt Status for Pipe 0"]
3058    #[inline(always)]
3059    pub fn pipe0bemp(
3060        self,
3061    ) -> crate::common::RegisterField<
3062        0,
3063        0x1,
3064        1,
3065        0,
3066        bempsts::Pipe0Bemp,
3067        bempsts::Pipe0Bemp,
3068        Bempsts_SPEC,
3069        crate::common::RW,
3070    > {
3071        crate::common::RegisterField::<
3072            0,
3073            0x1,
3074            1,
3075            0,
3076            bempsts::Pipe0Bemp,
3077            bempsts::Pipe0Bemp,
3078            Bempsts_SPEC,
3079            crate::common::RW,
3080        >::from_register(self, 0)
3081    }
3082
3083    #[doc = "BEMP Interrupt Status for Pipe 4"]
3084    #[inline(always)]
3085    pub fn pipe4bemp(
3086        self,
3087    ) -> crate::common::RegisterField<
3088        4,
3089        0x1,
3090        1,
3091        0,
3092        bempsts::Pipe4Bemp,
3093        bempsts::Pipe4Bemp,
3094        Bempsts_SPEC,
3095        crate::common::RW,
3096    > {
3097        crate::common::RegisterField::<
3098            4,
3099            0x1,
3100            1,
3101            0,
3102            bempsts::Pipe4Bemp,
3103            bempsts::Pipe4Bemp,
3104            Bempsts_SPEC,
3105            crate::common::RW,
3106        >::from_register(self, 0)
3107    }
3108
3109    #[doc = "BEMP Interrupt Status for Pipe 5"]
3110    #[inline(always)]
3111    pub fn pipe5bemp(
3112        self,
3113    ) -> crate::common::RegisterField<
3114        5,
3115        0x1,
3116        1,
3117        0,
3118        bempsts::Pipe5Bemp,
3119        bempsts::Pipe5Bemp,
3120        Bempsts_SPEC,
3121        crate::common::RW,
3122    > {
3123        crate::common::RegisterField::<
3124            5,
3125            0x1,
3126            1,
3127            0,
3128            bempsts::Pipe5Bemp,
3129            bempsts::Pipe5Bemp,
3130            Bempsts_SPEC,
3131            crate::common::RW,
3132        >::from_register(self, 0)
3133    }
3134
3135    #[doc = "BEMP Interrupt Status for Pipe 6"]
3136    #[inline(always)]
3137    pub fn pipe6bemp(
3138        self,
3139    ) -> crate::common::RegisterField<
3140        6,
3141        0x1,
3142        1,
3143        0,
3144        bempsts::Pipe6Bemp,
3145        bempsts::Pipe6Bemp,
3146        Bempsts_SPEC,
3147        crate::common::RW,
3148    > {
3149        crate::common::RegisterField::<
3150            6,
3151            0x1,
3152            1,
3153            0,
3154            bempsts::Pipe6Bemp,
3155            bempsts::Pipe6Bemp,
3156            Bempsts_SPEC,
3157            crate::common::RW,
3158        >::from_register(self, 0)
3159    }
3160
3161    #[doc = "BEMP Interrupt Status for Pipe 7"]
3162    #[inline(always)]
3163    pub fn pipe7bemp(
3164        self,
3165    ) -> crate::common::RegisterField<
3166        7,
3167        0x1,
3168        1,
3169        0,
3170        bempsts::Pipe7Bemp,
3171        bempsts::Pipe7Bemp,
3172        Bempsts_SPEC,
3173        crate::common::RW,
3174    > {
3175        crate::common::RegisterField::<
3176            7,
3177            0x1,
3178            1,
3179            0,
3180            bempsts::Pipe7Bemp,
3181            bempsts::Pipe7Bemp,
3182            Bempsts_SPEC,
3183            crate::common::RW,
3184        >::from_register(self, 0)
3185    }
3186}
3187impl ::core::default::Default for Bempsts {
3188    #[inline(always)]
3189    fn default() -> Bempsts {
3190        <crate::RegValueT<Bempsts_SPEC> as RegisterValue<_>>::new(0)
3191    }
3192}
3193pub mod bempsts {
3194
3195    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3196    pub struct Pipe0Bemp_SPEC;
3197    pub type Pipe0Bemp = crate::EnumBitfieldStruct<u8, Pipe0Bemp_SPEC>;
3198    impl Pipe0Bemp {
3199        #[doc = "No BEMP interrupt occurred"]
3200        pub const _0: Self = Self::new(0);
3201
3202        #[doc = "BEMP interrupt occurred"]
3203        pub const _1: Self = Self::new(1);
3204    }
3205    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3206    pub struct Pipe4Bemp_SPEC;
3207    pub type Pipe4Bemp = crate::EnumBitfieldStruct<u8, Pipe4Bemp_SPEC>;
3208    impl Pipe4Bemp {
3209        #[doc = "No BEMP interrupt occurred"]
3210        pub const _0: Self = Self::new(0);
3211
3212        #[doc = "BEMP interrupt occurred"]
3213        pub const _1: Self = Self::new(1);
3214    }
3215    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3216    pub struct Pipe5Bemp_SPEC;
3217    pub type Pipe5Bemp = crate::EnumBitfieldStruct<u8, Pipe5Bemp_SPEC>;
3218    impl Pipe5Bemp {
3219        #[doc = "No BEMP interrupt occurred"]
3220        pub const _0: Self = Self::new(0);
3221
3222        #[doc = "BEMP interrupt occurred"]
3223        pub const _1: Self = Self::new(1);
3224    }
3225    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3226    pub struct Pipe6Bemp_SPEC;
3227    pub type Pipe6Bemp = crate::EnumBitfieldStruct<u8, Pipe6Bemp_SPEC>;
3228    impl Pipe6Bemp {
3229        #[doc = "No BEMP interrupt occurred"]
3230        pub const _0: Self = Self::new(0);
3231
3232        #[doc = "BEMP interrupt occurred"]
3233        pub const _1: Self = Self::new(1);
3234    }
3235    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3236    pub struct Pipe7Bemp_SPEC;
3237    pub type Pipe7Bemp = crate::EnumBitfieldStruct<u8, Pipe7Bemp_SPEC>;
3238    impl Pipe7Bemp {
3239        #[doc = "No BEMP interrupt occurred"]
3240        pub const _0: Self = Self::new(0);
3241
3242        #[doc = "BEMP interrupt occurred"]
3243        pub const _1: Self = Self::new(1);
3244    }
3245}
3246#[doc(hidden)]
3247#[derive(Copy, Clone, Eq, PartialEq)]
3248pub struct Frmnum_SPEC;
3249impl crate::sealed::RegSpec for Frmnum_SPEC {
3250    type DataType = u16;
3251}
3252
3253#[doc = "Frame Number Register"]
3254pub type Frmnum = crate::RegValueT<Frmnum_SPEC>;
3255
3256impl Frmnum {
3257    #[doc = "Frame Number"]
3258    #[inline(always)]
3259    pub fn frnm(
3260        self,
3261    ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Frmnum_SPEC, crate::common::R> {
3262        crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Frmnum_SPEC,crate::common::R>::from_register(self,0)
3263    }
3264}
3265impl ::core::default::Default for Frmnum {
3266    #[inline(always)]
3267    fn default() -> Frmnum {
3268        <crate::RegValueT<Frmnum_SPEC> as RegisterValue<_>>::new(0)
3269    }
3270}
3271
3272#[doc(hidden)]
3273#[derive(Copy, Clone, Eq, PartialEq)]
3274pub struct Dvchgr_SPEC;
3275impl crate::sealed::RegSpec for Dvchgr_SPEC {
3276    type DataType = u16;
3277}
3278
3279#[doc = "Device State Change Register"]
3280pub type Dvchgr = crate::RegValueT<Dvchgr_SPEC>;
3281
3282impl Dvchgr {
3283    #[doc = "Device State Change"]
3284    #[inline(always)]
3285    pub fn dvchg(
3286        self,
3287    ) -> crate::common::RegisterField<
3288        15,
3289        0x1,
3290        1,
3291        0,
3292        dvchgr::Dvchg,
3293        dvchgr::Dvchg,
3294        Dvchgr_SPEC,
3295        crate::common::RW,
3296    > {
3297        crate::common::RegisterField::<
3298            15,
3299            0x1,
3300            1,
3301            0,
3302            dvchgr::Dvchg,
3303            dvchgr::Dvchg,
3304            Dvchgr_SPEC,
3305            crate::common::RW,
3306        >::from_register(self, 0)
3307    }
3308}
3309impl ::core::default::Default for Dvchgr {
3310    #[inline(always)]
3311    fn default() -> Dvchgr {
3312        <crate::RegValueT<Dvchgr_SPEC> as RegisterValue<_>>::new(0)
3313    }
3314}
3315pub mod dvchgr {
3316
3317    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3318    pub struct Dvchg_SPEC;
3319    pub type Dvchg = crate::EnumBitfieldStruct<u8, Dvchg_SPEC>;
3320    impl Dvchg {
3321        #[doc = "Disable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
3322        pub const _0: Self = Self::new(0);
3323
3324        #[doc = "Enable writes to the USBADDR.STSRECOV\\[3:0\\] and USBADDR.USBADDR\\[6:0\\] bits"]
3325        pub const _1: Self = Self::new(1);
3326    }
3327}
3328#[doc(hidden)]
3329#[derive(Copy, Clone, Eq, PartialEq)]
3330pub struct Usbaddr_SPEC;
3331impl crate::sealed::RegSpec for Usbaddr_SPEC {
3332    type DataType = u16;
3333}
3334
3335#[doc = "USB Address Register"]
3336pub type Usbaddr = crate::RegValueT<Usbaddr_SPEC>;
3337
3338impl Usbaddr {
3339    #[doc = "USB Address"]
3340    #[inline(always)]
3341    pub fn usbaddr(
3342        self,
3343    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Usbaddr_SPEC, crate::common::RW> {
3344        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Usbaddr_SPEC,crate::common::RW>::from_register(self,0)
3345    }
3346
3347    #[doc = "Status Recovery"]
3348    #[inline(always)]
3349    pub fn stsrecov(
3350        self,
3351    ) -> crate::common::RegisterField<
3352        8,
3353        0xf,
3354        1,
3355        0,
3356        usbaddr::Stsrecov,
3357        usbaddr::Stsrecov,
3358        Usbaddr_SPEC,
3359        crate::common::RW,
3360    > {
3361        crate::common::RegisterField::<
3362            8,
3363            0xf,
3364            1,
3365            0,
3366            usbaddr::Stsrecov,
3367            usbaddr::Stsrecov,
3368            Usbaddr_SPEC,
3369            crate::common::RW,
3370        >::from_register(self, 0)
3371    }
3372}
3373impl ::core::default::Default for Usbaddr {
3374    #[inline(always)]
3375    fn default() -> Usbaddr {
3376        <crate::RegValueT<Usbaddr_SPEC> as RegisterValue<_>>::new(0)
3377    }
3378}
3379pub mod usbaddr {
3380
3381    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3382    pub struct Stsrecov_SPEC;
3383    pub type Stsrecov = crate::EnumBitfieldStruct<u8, Stsrecov_SPEC>;
3384    impl Stsrecov {
3385        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 001b (default state)"]
3386        pub const _0_X_9: Self = Self::new(9);
3387
3388        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 010b (address state)"]
3389        pub const _0_X_A: Self = Self::new(10);
3390
3391        #[doc = "Return to the full-speed state (bits DVSTCTR0.RHST\\[2:0\\] = 010b), bits INTSTS0.DVSQ\\[2:0\\] = 011b (configured state)"]
3392        pub const _0_X_B: Self = Self::new(11);
3393    }
3394}
3395#[doc(hidden)]
3396#[derive(Copy, Clone, Eq, PartialEq)]
3397pub struct Usbreq_SPEC;
3398impl crate::sealed::RegSpec for Usbreq_SPEC {
3399    type DataType = u16;
3400}
3401
3402#[doc = "USB Request Type Register"]
3403pub type Usbreq = crate::RegValueT<Usbreq_SPEC>;
3404
3405impl Usbreq {
3406    #[doc = "Request Type"]
3407    #[inline(always)]
3408    pub fn bmrequesttype(
3409        self,
3410    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::R> {
3411        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::R>::from_register(self,0)
3412    }
3413
3414    #[doc = "Request"]
3415    #[inline(always)]
3416    pub fn brequest(
3417        self,
3418    ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Usbreq_SPEC, crate::common::R> {
3419        crate::common::RegisterField::<8,0xff,1,0,u8,u8,Usbreq_SPEC,crate::common::R>::from_register(self,0)
3420    }
3421}
3422impl ::core::default::Default for Usbreq {
3423    #[inline(always)]
3424    fn default() -> Usbreq {
3425        <crate::RegValueT<Usbreq_SPEC> as RegisterValue<_>>::new(0)
3426    }
3427}
3428
3429#[doc(hidden)]
3430#[derive(Copy, Clone, Eq, PartialEq)]
3431pub struct Usbval_SPEC;
3432impl crate::sealed::RegSpec for Usbval_SPEC {
3433    type DataType = u16;
3434}
3435
3436#[doc = "USB Request Value Register"]
3437pub type Usbval = crate::RegValueT<Usbval_SPEC>;
3438
3439impl Usbval {
3440    #[doc = "Value"]
3441    #[inline(always)]
3442    pub fn wvalue(
3443        self,
3444    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbval_SPEC, crate::common::R>
3445    {
3446        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbval_SPEC,crate::common::R>::from_register(self,0)
3447    }
3448}
3449impl ::core::default::Default for Usbval {
3450    #[inline(always)]
3451    fn default() -> Usbval {
3452        <crate::RegValueT<Usbval_SPEC> as RegisterValue<_>>::new(0)
3453    }
3454}
3455
3456#[doc(hidden)]
3457#[derive(Copy, Clone, Eq, PartialEq)]
3458pub struct Usbindx_SPEC;
3459impl crate::sealed::RegSpec for Usbindx_SPEC {
3460    type DataType = u16;
3461}
3462
3463#[doc = "USB Request Index Register"]
3464pub type Usbindx = crate::RegValueT<Usbindx_SPEC>;
3465
3466impl Usbindx {
3467    #[doc = "Index"]
3468    #[inline(always)]
3469    pub fn windex(
3470        self,
3471    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbindx_SPEC, crate::common::R>
3472    {
3473        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbindx_SPEC,crate::common::R>::from_register(self,0)
3474    }
3475}
3476impl ::core::default::Default for Usbindx {
3477    #[inline(always)]
3478    fn default() -> Usbindx {
3479        <crate::RegValueT<Usbindx_SPEC> as RegisterValue<_>>::new(0)
3480    }
3481}
3482
3483#[doc(hidden)]
3484#[derive(Copy, Clone, Eq, PartialEq)]
3485pub struct Usbleng_SPEC;
3486impl crate::sealed::RegSpec for Usbleng_SPEC {
3487    type DataType = u16;
3488}
3489
3490#[doc = "USB Request Length Register"]
3491pub type Usbleng = crate::RegValueT<Usbleng_SPEC>;
3492
3493impl Usbleng {
3494    #[doc = "Length"]
3495    #[inline(always)]
3496    pub fn wlentuh(
3497        self,
3498    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Usbleng_SPEC, crate::common::R>
3499    {
3500        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Usbleng_SPEC,crate::common::R>::from_register(self,0)
3501    }
3502}
3503impl ::core::default::Default for Usbleng {
3504    #[inline(always)]
3505    fn default() -> Usbleng {
3506        <crate::RegValueT<Usbleng_SPEC> as RegisterValue<_>>::new(0)
3507    }
3508}
3509
3510#[doc(hidden)]
3511#[derive(Copy, Clone, Eq, PartialEq)]
3512pub struct Dcpcfg_SPEC;
3513impl crate::sealed::RegSpec for Dcpcfg_SPEC {
3514    type DataType = u16;
3515}
3516
3517#[doc = "DCP Configuration Register"]
3518pub type Dcpcfg = crate::RegValueT<Dcpcfg_SPEC>;
3519
3520impl Dcpcfg {
3521    #[doc = "Pipe Disabled at End of Transfer"]
3522    #[inline(always)]
3523    pub fn shtnak(
3524        self,
3525    ) -> crate::common::RegisterField<
3526        7,
3527        0x1,
3528        1,
3529        0,
3530        dcpcfg::Shtnak,
3531        dcpcfg::Shtnak,
3532        Dcpcfg_SPEC,
3533        crate::common::RW,
3534    > {
3535        crate::common::RegisterField::<
3536            7,
3537            0x1,
3538            1,
3539            0,
3540            dcpcfg::Shtnak,
3541            dcpcfg::Shtnak,
3542            Dcpcfg_SPEC,
3543            crate::common::RW,
3544        >::from_register(self, 0)
3545    }
3546}
3547impl ::core::default::Default for Dcpcfg {
3548    #[inline(always)]
3549    fn default() -> Dcpcfg {
3550        <crate::RegValueT<Dcpcfg_SPEC> as RegisterValue<_>>::new(0)
3551    }
3552}
3553pub mod dcpcfg {
3554
3555    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3556    pub struct Shtnak_SPEC;
3557    pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
3558    impl Shtnak {
3559        #[doc = "Keep pipe open after transfer ends"]
3560        pub const _0: Self = Self::new(0);
3561
3562        #[doc = "Disable pipe after transfer ends"]
3563        pub const _1: Self = Self::new(1);
3564    }
3565}
3566#[doc(hidden)]
3567#[derive(Copy, Clone, Eq, PartialEq)]
3568pub struct Dcpmaxp_SPEC;
3569impl crate::sealed::RegSpec for Dcpmaxp_SPEC {
3570    type DataType = u16;
3571}
3572
3573#[doc = "DCP Maximum Packet Size Register"]
3574pub type Dcpmaxp = crate::RegValueT<Dcpmaxp_SPEC>;
3575
3576impl Dcpmaxp {
3577    #[doc = "Maximum Packet Size"]
3578    #[inline(always)]
3579    pub fn mxps(
3580        self,
3581    ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Dcpmaxp_SPEC, crate::common::RW> {
3582        crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Dcpmaxp_SPEC,crate::common::RW>::from_register(self,0)
3583    }
3584}
3585impl ::core::default::Default for Dcpmaxp {
3586    #[inline(always)]
3587    fn default() -> Dcpmaxp {
3588        <crate::RegValueT<Dcpmaxp_SPEC> as RegisterValue<_>>::new(64)
3589    }
3590}
3591
3592#[doc(hidden)]
3593#[derive(Copy, Clone, Eq, PartialEq)]
3594pub struct Dcpctr_SPEC;
3595impl crate::sealed::RegSpec for Dcpctr_SPEC {
3596    type DataType = u16;
3597}
3598
3599#[doc = "DCP Control Register"]
3600pub type Dcpctr = crate::RegValueT<Dcpctr_SPEC>;
3601
3602impl Dcpctr {
3603    #[doc = "Response PID"]
3604    #[inline(always)]
3605    pub fn pid(
3606        self,
3607    ) -> crate::common::RegisterField<
3608        0,
3609        0x3,
3610        1,
3611        0,
3612        dcpctr::Pid,
3613        dcpctr::Pid,
3614        Dcpctr_SPEC,
3615        crate::common::RW,
3616    > {
3617        crate::common::RegisterField::<
3618            0,
3619            0x3,
3620            1,
3621            0,
3622            dcpctr::Pid,
3623            dcpctr::Pid,
3624            Dcpctr_SPEC,
3625            crate::common::RW,
3626        >::from_register(self, 0)
3627    }
3628
3629    #[doc = "Control Transfer End Enable"]
3630    #[inline(always)]
3631    pub fn ccpl(
3632        self,
3633    ) -> crate::common::RegisterField<
3634        2,
3635        0x1,
3636        1,
3637        0,
3638        dcpctr::Ccpl,
3639        dcpctr::Ccpl,
3640        Dcpctr_SPEC,
3641        crate::common::RW,
3642    > {
3643        crate::common::RegisterField::<
3644            2,
3645            0x1,
3646            1,
3647            0,
3648            dcpctr::Ccpl,
3649            dcpctr::Ccpl,
3650            Dcpctr_SPEC,
3651            crate::common::RW,
3652        >::from_register(self, 0)
3653    }
3654
3655    #[doc = "Pipe Busy"]
3656    #[inline(always)]
3657    pub fn pbusy(
3658        self,
3659    ) -> crate::common::RegisterField<
3660        5,
3661        0x1,
3662        1,
3663        0,
3664        dcpctr::Pbusy,
3665        dcpctr::Pbusy,
3666        Dcpctr_SPEC,
3667        crate::common::R,
3668    > {
3669        crate::common::RegisterField::<
3670            5,
3671            0x1,
3672            1,
3673            0,
3674            dcpctr::Pbusy,
3675            dcpctr::Pbusy,
3676            Dcpctr_SPEC,
3677            crate::common::R,
3678        >::from_register(self, 0)
3679    }
3680
3681    #[doc = "Sequence Toggle Bit Monitor"]
3682    #[inline(always)]
3683    pub fn sqmon(
3684        self,
3685    ) -> crate::common::RegisterField<
3686        6,
3687        0x1,
3688        1,
3689        0,
3690        dcpctr::Sqmon,
3691        dcpctr::Sqmon,
3692        Dcpctr_SPEC,
3693        crate::common::R,
3694    > {
3695        crate::common::RegisterField::<
3696            6,
3697            0x1,
3698            1,
3699            0,
3700            dcpctr::Sqmon,
3701            dcpctr::Sqmon,
3702            Dcpctr_SPEC,
3703            crate::common::R,
3704        >::from_register(self, 0)
3705    }
3706
3707    #[doc = "Sequence Toggle Bit Set"]
3708    #[inline(always)]
3709    pub fn sqset(
3710        self,
3711    ) -> crate::common::RegisterField<
3712        7,
3713        0x1,
3714        1,
3715        0,
3716        dcpctr::Sqset,
3717        dcpctr::Sqset,
3718        Dcpctr_SPEC,
3719        crate::common::RW,
3720    > {
3721        crate::common::RegisterField::<
3722            7,
3723            0x1,
3724            1,
3725            0,
3726            dcpctr::Sqset,
3727            dcpctr::Sqset,
3728            Dcpctr_SPEC,
3729            crate::common::RW,
3730        >::from_register(self, 0)
3731    }
3732
3733    #[doc = "Sequence Toggle Bit Clear"]
3734    #[inline(always)]
3735    pub fn sqclr(
3736        self,
3737    ) -> crate::common::RegisterField<
3738        8,
3739        0x1,
3740        1,
3741        0,
3742        dcpctr::Sqclr,
3743        dcpctr::Sqclr,
3744        Dcpctr_SPEC,
3745        crate::common::RW,
3746    > {
3747        crate::common::RegisterField::<
3748            8,
3749            0x1,
3750            1,
3751            0,
3752            dcpctr::Sqclr,
3753            dcpctr::Sqclr,
3754            Dcpctr_SPEC,
3755            crate::common::RW,
3756        >::from_register(self, 0)
3757    }
3758
3759    #[doc = "Buffer Status"]
3760    #[inline(always)]
3761    pub fn bsts(
3762        self,
3763    ) -> crate::common::RegisterField<
3764        15,
3765        0x1,
3766        1,
3767        0,
3768        dcpctr::Bsts,
3769        dcpctr::Bsts,
3770        Dcpctr_SPEC,
3771        crate::common::R,
3772    > {
3773        crate::common::RegisterField::<
3774            15,
3775            0x1,
3776            1,
3777            0,
3778            dcpctr::Bsts,
3779            dcpctr::Bsts,
3780            Dcpctr_SPEC,
3781            crate::common::R,
3782        >::from_register(self, 0)
3783    }
3784}
3785impl ::core::default::Default for Dcpctr {
3786    #[inline(always)]
3787    fn default() -> Dcpctr {
3788        <crate::RegValueT<Dcpctr_SPEC> as RegisterValue<_>>::new(64)
3789    }
3790}
3791pub mod dcpctr {
3792
3793    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3794    pub struct Pid_SPEC;
3795    pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
3796    impl Pid {
3797        #[doc = "NAK response"]
3798        pub const _00: Self = Self::new(0);
3799
3800        #[doc = "BUF response (depends on the buffer state)"]
3801        pub const _01: Self = Self::new(1);
3802
3803        #[doc = "STALL response"]
3804        pub const _10: Self = Self::new(2);
3805
3806        #[doc = "STALL response"]
3807        pub const _11: Self = Self::new(3);
3808    }
3809    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3810    pub struct Ccpl_SPEC;
3811    pub type Ccpl = crate::EnumBitfieldStruct<u8, Ccpl_SPEC>;
3812    impl Ccpl {
3813        #[doc = "Disable control transfer completion"]
3814        pub const _0: Self = Self::new(0);
3815
3816        #[doc = "Enable control transfer completion"]
3817        pub const _1: Self = Self::new(1);
3818    }
3819    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3820    pub struct Pbusy_SPEC;
3821    pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
3822    impl Pbusy {
3823        #[doc = "DCP not used for the USB bus"]
3824        pub const _0: Self = Self::new(0);
3825
3826        #[doc = "DCP in use for the USB bus"]
3827        pub const _1: Self = Self::new(1);
3828    }
3829    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3830    pub struct Sqmon_SPEC;
3831    pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
3832    impl Sqmon {
3833        #[doc = "DATA0"]
3834        pub const _0: Self = Self::new(0);
3835
3836        #[doc = "DATA1"]
3837        pub const _1: Self = Self::new(1);
3838    }
3839    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3840    pub struct Sqset_SPEC;
3841    pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
3842    impl Sqset {
3843        #[doc = "Invalid (writing 0 has no effect)"]
3844        pub const _0: Self = Self::new(0);
3845
3846        #[doc = "Set the expected value for the next transaction to DATA1"]
3847        pub const _1: Self = Self::new(1);
3848    }
3849    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3850    pub struct Sqclr_SPEC;
3851    pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
3852    impl Sqclr {
3853        #[doc = "Invalid (writing 0 has no effect)"]
3854        pub const _0: Self = Self::new(0);
3855
3856        #[doc = "Clear the expected value for the next transaction to DATA0"]
3857        pub const _1: Self = Self::new(1);
3858    }
3859    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3860    pub struct Bsts_SPEC;
3861    pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
3862    impl Bsts {
3863        #[doc = "Buffer access disabled"]
3864        pub const _0: Self = Self::new(0);
3865
3866        #[doc = "Buffer access enabled"]
3867        pub const _1: Self = Self::new(1);
3868    }
3869}
3870#[doc(hidden)]
3871#[derive(Copy, Clone, Eq, PartialEq)]
3872pub struct Pipesel_SPEC;
3873impl crate::sealed::RegSpec for Pipesel_SPEC {
3874    type DataType = u16;
3875}
3876
3877#[doc = "Pipe Window Select Register"]
3878pub type Pipesel = crate::RegValueT<Pipesel_SPEC>;
3879
3880impl Pipesel {
3881    #[doc = "Pipe Window Select"]
3882    #[inline(always)]
3883    pub fn pipesel(
3884        self,
3885    ) -> crate::common::RegisterField<
3886        0,
3887        0xf,
3888        1,
3889        0,
3890        pipesel::Pipesel,
3891        pipesel::Pipesel,
3892        Pipesel_SPEC,
3893        crate::common::RW,
3894    > {
3895        crate::common::RegisterField::<
3896            0,
3897            0xf,
3898            1,
3899            0,
3900            pipesel::Pipesel,
3901            pipesel::Pipesel,
3902            Pipesel_SPEC,
3903            crate::common::RW,
3904        >::from_register(self, 0)
3905    }
3906}
3907impl ::core::default::Default for Pipesel {
3908    #[inline(always)]
3909    fn default() -> Pipesel {
3910        <crate::RegValueT<Pipesel_SPEC> as RegisterValue<_>>::new(0)
3911    }
3912}
3913pub mod pipesel {
3914
3915    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3916    pub struct Pipesel_SPEC;
3917    pub type Pipesel = crate::EnumBitfieldStruct<u8, Pipesel_SPEC>;
3918    impl Pipesel {
3919        #[doc = "No pipe selected"]
3920        pub const _0_X_0: Self = Self::new(0);
3921
3922        #[doc = "Pipe 4"]
3923        pub const _0_X_4: Self = Self::new(4);
3924
3925        #[doc = "Pipe 5"]
3926        pub const _0_X_5: Self = Self::new(5);
3927
3928        #[doc = "Pipe 6"]
3929        pub const _0_X_6: Self = Self::new(6);
3930
3931        #[doc = "Pipe 7"]
3932        pub const _0_X_7: Self = Self::new(7);
3933    }
3934}
3935#[doc(hidden)]
3936#[derive(Copy, Clone, Eq, PartialEq)]
3937pub struct Pipecfg_SPEC;
3938impl crate::sealed::RegSpec for Pipecfg_SPEC {
3939    type DataType = u16;
3940}
3941
3942#[doc = "Pipe Configuration Register"]
3943pub type Pipecfg = crate::RegValueT<Pipecfg_SPEC>;
3944
3945impl Pipecfg {
3946    #[doc = "Endpoint Number"]
3947    #[inline(always)]
3948    pub fn epnum(
3949        self,
3950    ) -> crate::common::RegisterField<0, 0xf, 1, 0, u8, u8, Pipecfg_SPEC, crate::common::RW> {
3951        crate::common::RegisterField::<0,0xf,1,0,u8,u8,Pipecfg_SPEC,crate::common::RW>::from_register(self,0)
3952    }
3953
3954    #[doc = "Transfer Direction"]
3955    #[inline(always)]
3956    pub fn dir(
3957        self,
3958    ) -> crate::common::RegisterField<
3959        4,
3960        0x1,
3961        1,
3962        0,
3963        pipecfg::Dir,
3964        pipecfg::Dir,
3965        Pipecfg_SPEC,
3966        crate::common::RW,
3967    > {
3968        crate::common::RegisterField::<
3969            4,
3970            0x1,
3971            1,
3972            0,
3973            pipecfg::Dir,
3974            pipecfg::Dir,
3975            Pipecfg_SPEC,
3976            crate::common::RW,
3977        >::from_register(self, 0)
3978    }
3979
3980    #[doc = "Pipe Disabled at End of Transfer"]
3981    #[inline(always)]
3982    pub fn shtnak(
3983        self,
3984    ) -> crate::common::RegisterField<
3985        7,
3986        0x1,
3987        1,
3988        0,
3989        pipecfg::Shtnak,
3990        pipecfg::Shtnak,
3991        Pipecfg_SPEC,
3992        crate::common::RW,
3993    > {
3994        crate::common::RegisterField::<
3995            7,
3996            0x1,
3997            1,
3998            0,
3999            pipecfg::Shtnak,
4000            pipecfg::Shtnak,
4001            Pipecfg_SPEC,
4002            crate::common::RW,
4003        >::from_register(self, 0)
4004    }
4005
4006    #[doc = "Double Buffer Mode"]
4007    #[inline(always)]
4008    pub fn dblb(
4009        self,
4010    ) -> crate::common::RegisterField<
4011        9,
4012        0x1,
4013        1,
4014        0,
4015        pipecfg::Dblb,
4016        pipecfg::Dblb,
4017        Pipecfg_SPEC,
4018        crate::common::RW,
4019    > {
4020        crate::common::RegisterField::<
4021            9,
4022            0x1,
4023            1,
4024            0,
4025            pipecfg::Dblb,
4026            pipecfg::Dblb,
4027            Pipecfg_SPEC,
4028            crate::common::RW,
4029        >::from_register(self, 0)
4030    }
4031
4032    #[doc = "BRDY Interrupt Operation Specification"]
4033    #[inline(always)]
4034    pub fn bfre(
4035        self,
4036    ) -> crate::common::RegisterField<
4037        10,
4038        0x1,
4039        1,
4040        0,
4041        pipecfg::Bfre,
4042        pipecfg::Bfre,
4043        Pipecfg_SPEC,
4044        crate::common::RW,
4045    > {
4046        crate::common::RegisterField::<
4047            10,
4048            0x1,
4049            1,
4050            0,
4051            pipecfg::Bfre,
4052            pipecfg::Bfre,
4053            Pipecfg_SPEC,
4054            crate::common::RW,
4055        >::from_register(self, 0)
4056    }
4057
4058    #[doc = "Transfer Type"]
4059    #[inline(always)]
4060    pub fn r#type(
4061        self,
4062    ) -> crate::common::RegisterField<
4063        14,
4064        0x3,
4065        1,
4066        0,
4067        pipecfg::Type,
4068        pipecfg::Type,
4069        Pipecfg_SPEC,
4070        crate::common::RW,
4071    > {
4072        crate::common::RegisterField::<
4073            14,
4074            0x3,
4075            1,
4076            0,
4077            pipecfg::Type,
4078            pipecfg::Type,
4079            Pipecfg_SPEC,
4080            crate::common::RW,
4081        >::from_register(self, 0)
4082    }
4083}
4084impl ::core::default::Default for Pipecfg {
4085    #[inline(always)]
4086    fn default() -> Pipecfg {
4087        <crate::RegValueT<Pipecfg_SPEC> as RegisterValue<_>>::new(0)
4088    }
4089}
4090pub mod pipecfg {
4091
4092    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4093    pub struct Dir_SPEC;
4094    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
4095    impl Dir {
4096        #[doc = "Receiving direction"]
4097        pub const _0: Self = Self::new(0);
4098
4099        #[doc = "Transmitting direction"]
4100        pub const _1: Self = Self::new(1);
4101    }
4102    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4103    pub struct Shtnak_SPEC;
4104    pub type Shtnak = crate::EnumBitfieldStruct<u8, Shtnak_SPEC>;
4105    impl Shtnak {
4106        #[doc = "Continue pipe operation after transfer ends"]
4107        pub const _0: Self = Self::new(0);
4108
4109        #[doc = "Disable pipe after transfer ends"]
4110        pub const _1: Self = Self::new(1);
4111    }
4112    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4113    pub struct Dblb_SPEC;
4114    pub type Dblb = crate::EnumBitfieldStruct<u8, Dblb_SPEC>;
4115    impl Dblb {
4116        #[doc = "Single buffer"]
4117        pub const _0: Self = Self::new(0);
4118
4119        #[doc = "Double buffer"]
4120        pub const _1: Self = Self::new(1);
4121    }
4122    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4123    pub struct Bfre_SPEC;
4124    pub type Bfre = crate::EnumBitfieldStruct<u8, Bfre_SPEC>;
4125    impl Bfre {
4126        #[doc = "Generate BRDY interrupt on transmitting or receiving data"]
4127        pub const _0: Self = Self::new(0);
4128
4129        #[doc = "Generate BRDY interrupt on completion of reading data"]
4130        pub const _1: Self = Self::new(1);
4131    }
4132    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4133    pub struct Type_SPEC;
4134    pub type Type = crate::EnumBitfieldStruct<u8, Type_SPEC>;
4135    impl Type {
4136        #[doc = "Pipe not used"]
4137        pub const _00: Self = Self::new(0);
4138
4139        #[doc = "Pipes 4 and 5: Bulk transfer Pipes 6 and 7: Setting prohibited"]
4140        pub const _01: Self = Self::new(1);
4141
4142        #[doc = "Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Interrupt transfer"]
4143        pub const _10: Self = Self::new(2);
4144
4145        #[doc = "Pipes 4 and 5: Setting prohibited Pipes 6 and 7: Setting prohibited"]
4146        pub const _11: Self = Self::new(3);
4147    }
4148}
4149#[doc(hidden)]
4150#[derive(Copy, Clone, Eq, PartialEq)]
4151pub struct Pipemaxp_SPEC;
4152impl crate::sealed::RegSpec for Pipemaxp_SPEC {
4153    type DataType = u16;
4154}
4155
4156#[doc = "Pipe Maximum Packet Size Register"]
4157pub type Pipemaxp = crate::RegValueT<Pipemaxp_SPEC>;
4158
4159impl Pipemaxp {
4160    #[doc = "Maximum Packet Size"]
4161    #[inline(always)]
4162    pub fn mxps(
4163        self,
4164    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Pipemaxp_SPEC, crate::common::RW>
4165    {
4166        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Pipemaxp_SPEC,crate::common::RW>::from_register(self,0)
4167    }
4168}
4169impl ::core::default::Default for Pipemaxp {
4170    #[inline(always)]
4171    fn default() -> Pipemaxp {
4172        <crate::RegValueT<Pipemaxp_SPEC> as RegisterValue<_>>::new(0)
4173    }
4174}
4175
4176#[doc(hidden)]
4177#[derive(Copy, Clone, Eq, PartialEq)]
4178pub struct Pipectr_SPEC;
4179impl crate::sealed::RegSpec for Pipectr_SPEC {
4180    type DataType = u16;
4181}
4182
4183#[doc = "PIPE%s Control Registers"]
4184pub type Pipectr = crate::RegValueT<Pipectr_SPEC>;
4185
4186impl Pipectr {
4187    #[doc = "Response PID"]
4188    #[inline(always)]
4189    pub fn pid(
4190        self,
4191    ) -> crate::common::RegisterField<
4192        0,
4193        0x3,
4194        1,
4195        0,
4196        pipectr::Pid,
4197        pipectr::Pid,
4198        Pipectr_SPEC,
4199        crate::common::RW,
4200    > {
4201        crate::common::RegisterField::<
4202            0,
4203            0x3,
4204            1,
4205            0,
4206            pipectr::Pid,
4207            pipectr::Pid,
4208            Pipectr_SPEC,
4209            crate::common::RW,
4210        >::from_register(self, 0)
4211    }
4212
4213    #[doc = "Pipe Busy"]
4214    #[inline(always)]
4215    pub fn pbusy(
4216        self,
4217    ) -> crate::common::RegisterField<
4218        5,
4219        0x1,
4220        1,
4221        0,
4222        pipectr::Pbusy,
4223        pipectr::Pbusy,
4224        Pipectr_SPEC,
4225        crate::common::R,
4226    > {
4227        crate::common::RegisterField::<
4228            5,
4229            0x1,
4230            1,
4231            0,
4232            pipectr::Pbusy,
4233            pipectr::Pbusy,
4234            Pipectr_SPEC,
4235            crate::common::R,
4236        >::from_register(self, 0)
4237    }
4238
4239    #[doc = "Sequence Toggle Bit Confirmation"]
4240    #[inline(always)]
4241    pub fn sqmon(
4242        self,
4243    ) -> crate::common::RegisterField<
4244        6,
4245        0x1,
4246        1,
4247        0,
4248        pipectr::Sqmon,
4249        pipectr::Sqmon,
4250        Pipectr_SPEC,
4251        crate::common::R,
4252    > {
4253        crate::common::RegisterField::<
4254            6,
4255            0x1,
4256            1,
4257            0,
4258            pipectr::Sqmon,
4259            pipectr::Sqmon,
4260            Pipectr_SPEC,
4261            crate::common::R,
4262        >::from_register(self, 0)
4263    }
4264
4265    #[doc = "Sequence Toggle Bit Set"]
4266    #[inline(always)]
4267    pub fn sqset(
4268        self,
4269    ) -> crate::common::RegisterField<
4270        7,
4271        0x1,
4272        1,
4273        0,
4274        pipectr::Sqset,
4275        pipectr::Sqset,
4276        Pipectr_SPEC,
4277        crate::common::W,
4278    > {
4279        crate::common::RegisterField::<
4280            7,
4281            0x1,
4282            1,
4283            0,
4284            pipectr::Sqset,
4285            pipectr::Sqset,
4286            Pipectr_SPEC,
4287            crate::common::W,
4288        >::from_register(self, 0)
4289    }
4290
4291    #[doc = "Sequence Toggle Bit Clear"]
4292    #[inline(always)]
4293    pub fn sqclr(
4294        self,
4295    ) -> crate::common::RegisterField<
4296        8,
4297        0x1,
4298        1,
4299        0,
4300        pipectr::Sqclr,
4301        pipectr::Sqclr,
4302        Pipectr_SPEC,
4303        crate::common::W,
4304    > {
4305        crate::common::RegisterField::<
4306            8,
4307            0x1,
4308            1,
4309            0,
4310            pipectr::Sqclr,
4311            pipectr::Sqclr,
4312            Pipectr_SPEC,
4313            crate::common::W,
4314        >::from_register(self, 0)
4315    }
4316
4317    #[doc = "Auto Buffer Clear Mode"]
4318    #[inline(always)]
4319    pub fn aclrm(
4320        self,
4321    ) -> crate::common::RegisterField<
4322        9,
4323        0x1,
4324        1,
4325        0,
4326        pipectr::Aclrm,
4327        pipectr::Aclrm,
4328        Pipectr_SPEC,
4329        crate::common::RW,
4330    > {
4331        crate::common::RegisterField::<
4332            9,
4333            0x1,
4334            1,
4335            0,
4336            pipectr::Aclrm,
4337            pipectr::Aclrm,
4338            Pipectr_SPEC,
4339            crate::common::RW,
4340        >::from_register(self, 0)
4341    }
4342
4343    #[doc = "Buffer Status"]
4344    #[inline(always)]
4345    pub fn bsts(
4346        self,
4347    ) -> crate::common::RegisterField<
4348        15,
4349        0x1,
4350        1,
4351        0,
4352        pipectr::Bsts,
4353        pipectr::Bsts,
4354        Pipectr_SPEC,
4355        crate::common::R,
4356    > {
4357        crate::common::RegisterField::<
4358            15,
4359            0x1,
4360            1,
4361            0,
4362            pipectr::Bsts,
4363            pipectr::Bsts,
4364            Pipectr_SPEC,
4365            crate::common::R,
4366        >::from_register(self, 0)
4367    }
4368}
4369impl ::core::default::Default for Pipectr {
4370    #[inline(always)]
4371    fn default() -> Pipectr {
4372        <crate::RegValueT<Pipectr_SPEC> as RegisterValue<_>>::new(0)
4373    }
4374}
4375pub mod pipectr {
4376
4377    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4378    pub struct Pid_SPEC;
4379    pub type Pid = crate::EnumBitfieldStruct<u8, Pid_SPEC>;
4380    impl Pid {
4381        #[doc = "NAK response"]
4382        pub const _00: Self = Self::new(0);
4383
4384        #[doc = "BUF response (depends buffer state)"]
4385        pub const _01: Self = Self::new(1);
4386
4387        #[doc = "STALL response"]
4388        pub const _10: Self = Self::new(2);
4389
4390        #[doc = "STALL response"]
4391        pub const _11: Self = Self::new(3);
4392    }
4393    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4394    pub struct Pbusy_SPEC;
4395    pub type Pbusy = crate::EnumBitfieldStruct<u8, Pbusy_SPEC>;
4396    impl Pbusy {
4397        #[doc = "Pipe n not in use for the transaction"]
4398        pub const _0: Self = Self::new(0);
4399
4400        #[doc = "Pipe n in use for the transaction"]
4401        pub const _1: Self = Self::new(1);
4402    }
4403    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4404    pub struct Sqmon_SPEC;
4405    pub type Sqmon = crate::EnumBitfieldStruct<u8, Sqmon_SPEC>;
4406    impl Sqmon {
4407        #[doc = "DATA0"]
4408        pub const _0: Self = Self::new(0);
4409
4410        #[doc = "DATA1"]
4411        pub const _1: Self = Self::new(1);
4412    }
4413    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4414    pub struct Sqset_SPEC;
4415    pub type Sqset = crate::EnumBitfieldStruct<u8, Sqset_SPEC>;
4416    impl Sqset {
4417        #[doc = "Invalid (writing 0 has no effect)"]
4418        pub const _0: Self = Self::new(0);
4419
4420        #[doc = "Set the expected value for the next transaction to DATA0"]
4421        pub const _1: Self = Self::new(1);
4422    }
4423    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4424    pub struct Sqclr_SPEC;
4425    pub type Sqclr = crate::EnumBitfieldStruct<u8, Sqclr_SPEC>;
4426    impl Sqclr {
4427        #[doc = "Invalid (writing 0 has no effect)"]
4428        pub const _0: Self = Self::new(0);
4429
4430        #[doc = "Clear the expected value for the next transaction to DATA0"]
4431        pub const _1: Self = Self::new(1);
4432    }
4433    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4434    pub struct Aclrm_SPEC;
4435    pub type Aclrm = crate::EnumBitfieldStruct<u8, Aclrm_SPEC>;
4436    impl Aclrm {
4437        #[doc = "Disable"]
4438        pub const _0: Self = Self::new(0);
4439
4440        #[doc = "Enable (all buffers initialized)"]
4441        pub const _1: Self = Self::new(1);
4442    }
4443    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4444    pub struct Bsts_SPEC;
4445    pub type Bsts = crate::EnumBitfieldStruct<u8, Bsts_SPEC>;
4446    impl Bsts {
4447        #[doc = "Buffer access disabled"]
4448        pub const _0: Self = Self::new(0);
4449
4450        #[doc = "Buffer access enabled"]
4451        pub const _1: Self = Self::new(1);
4452    }
4453}
4454#[doc(hidden)]
4455#[derive(Copy, Clone, Eq, PartialEq)]
4456pub struct Pipetre_SPEC;
4457impl crate::sealed::RegSpec for Pipetre_SPEC {
4458    type DataType = u16;
4459}
4460
4461#[doc = "PIPE%s Transaction Counter Enable Register"]
4462pub type Pipetre = crate::RegValueT<Pipetre_SPEC>;
4463
4464impl Pipetre {
4465    #[doc = "Transaction Counter Clear"]
4466    #[inline(always)]
4467    pub fn trclr(
4468        self,
4469    ) -> crate::common::RegisterField<
4470        8,
4471        0x1,
4472        1,
4473        0,
4474        pipetre::Trclr,
4475        pipetre::Trclr,
4476        Pipetre_SPEC,
4477        crate::common::RW,
4478    > {
4479        crate::common::RegisterField::<
4480            8,
4481            0x1,
4482            1,
4483            0,
4484            pipetre::Trclr,
4485            pipetre::Trclr,
4486            Pipetre_SPEC,
4487            crate::common::RW,
4488        >::from_register(self, 0)
4489    }
4490
4491    #[doc = "Transaction Counter Enable"]
4492    #[inline(always)]
4493    pub fn trenb(
4494        self,
4495    ) -> crate::common::RegisterField<
4496        9,
4497        0x1,
4498        1,
4499        0,
4500        pipetre::Trenb,
4501        pipetre::Trenb,
4502        Pipetre_SPEC,
4503        crate::common::RW,
4504    > {
4505        crate::common::RegisterField::<
4506            9,
4507            0x1,
4508            1,
4509            0,
4510            pipetre::Trenb,
4511            pipetre::Trenb,
4512            Pipetre_SPEC,
4513            crate::common::RW,
4514        >::from_register(self, 0)
4515    }
4516}
4517impl ::core::default::Default for Pipetre {
4518    #[inline(always)]
4519    fn default() -> Pipetre {
4520        <crate::RegValueT<Pipetre_SPEC> as RegisterValue<_>>::new(0)
4521    }
4522}
4523pub mod pipetre {
4524
4525    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4526    pub struct Trclr_SPEC;
4527    pub type Trclr = crate::EnumBitfieldStruct<u8, Trclr_SPEC>;
4528    impl Trclr {
4529        #[doc = "Invalid (writing 0 has no effect)"]
4530        pub const _0: Self = Self::new(0);
4531
4532        #[doc = "Clear counter value"]
4533        pub const _1: Self = Self::new(1);
4534    }
4535    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4536    pub struct Trenb_SPEC;
4537    pub type Trenb = crate::EnumBitfieldStruct<u8, Trenb_SPEC>;
4538    impl Trenb {
4539        #[doc = "Disable transaction counter"]
4540        pub const _0: Self = Self::new(0);
4541
4542        #[doc = "Enable transaction counter"]
4543        pub const _1: Self = Self::new(1);
4544    }
4545}
4546#[doc(hidden)]
4547#[derive(Copy, Clone, Eq, PartialEq)]
4548pub struct Pipetrn_SPEC;
4549impl crate::sealed::RegSpec for Pipetrn_SPEC {
4550    type DataType = u16;
4551}
4552
4553#[doc = "PIPE%s Transaction Counter Register"]
4554pub type Pipetrn = crate::RegValueT<Pipetrn_SPEC>;
4555
4556impl Pipetrn {
4557    #[doc = "Transaction Counter"]
4558    #[inline(always)]
4559    pub fn trncnt(
4560        self,
4561    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Pipetrn_SPEC, crate::common::RW>
4562    {
4563        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Pipetrn_SPEC,crate::common::RW>::from_register(self,0)
4564    }
4565}
4566impl ::core::default::Default for Pipetrn {
4567    #[inline(always)]
4568    fn default() -> Pipetrn {
4569        <crate::RegValueT<Pipetrn_SPEC> as RegisterValue<_>>::new(0)
4570    }
4571}
4572
4573#[doc(hidden)]
4574#[derive(Copy, Clone, Eq, PartialEq)]
4575pub struct Physectrl_SPEC;
4576impl crate::sealed::RegSpec for Physectrl_SPEC {
4577    type DataType = u32;
4578}
4579
4580#[doc = "PHY Single-ended Receiver Control Register"]
4581pub type Physectrl = crate::RegValueT<Physectrl_SPEC>;
4582
4583impl Physectrl {
4584    #[doc = "Single-ended Receiver Enable"]
4585    #[inline(always)]
4586    pub fn cnen(
4587        self,
4588    ) -> crate::common::RegisterField<
4589        4,
4590        0x1,
4591        1,
4592        0,
4593        physectrl::Cnen,
4594        physectrl::Cnen,
4595        Physectrl_SPEC,
4596        crate::common::RW,
4597    > {
4598        crate::common::RegisterField::<
4599            4,
4600            0x1,
4601            1,
4602            0,
4603            physectrl::Cnen,
4604            physectrl::Cnen,
4605            Physectrl_SPEC,
4606            crate::common::RW,
4607        >::from_register(self, 0)
4608    }
4609}
4610impl ::core::default::Default for Physectrl {
4611    #[inline(always)]
4612    fn default() -> Physectrl {
4613        <crate::RegValueT<Physectrl_SPEC> as RegisterValue<_>>::new(0)
4614    }
4615}
4616pub mod physectrl {
4617
4618    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4619    pub struct Cnen_SPEC;
4620    pub type Cnen = crate::EnumBitfieldStruct<u8, Cnen_SPEC>;
4621    impl Cnen {
4622        #[doc = "Single-ended receiver operation is disabled"]
4623        pub const _0: Self = Self::new(0);
4624
4625        #[doc = "Single-ended receiver operation is enabled"]
4626        pub const _1: Self = Self::new(1);
4627    }
4628}
4629#[doc(hidden)]
4630#[derive(Copy, Clone, Eq, PartialEq)]
4631pub struct Dpusr0R_SPEC;
4632impl crate::sealed::RegSpec for Dpusr0R_SPEC {
4633    type DataType = u32;
4634}
4635
4636#[doc = "Deep Software Standby USB Transceiver Control/Pin Monitor Register"]
4637pub type Dpusr0R = crate::RegValueT<Dpusr0R_SPEC>;
4638
4639impl Dpusr0R {
4640    #[doc = "USB Single-ended Receiver Control"]
4641    #[inline(always)]
4642    pub fn srpc0(
4643        self,
4644    ) -> crate::common::RegisterField<
4645        0,
4646        0x1,
4647        1,
4648        0,
4649        dpusr0r::Srpc0,
4650        dpusr0r::Srpc0,
4651        Dpusr0R_SPEC,
4652        crate::common::RW,
4653    > {
4654        crate::common::RegisterField::<
4655            0,
4656            0x1,
4657            1,
4658            0,
4659            dpusr0r::Srpc0,
4660            dpusr0r::Srpc0,
4661            Dpusr0R_SPEC,
4662            crate::common::RW,
4663        >::from_register(self, 0)
4664    }
4665
4666    #[doc = "DP Pull-Up Resistor Control"]
4667    #[inline(always)]
4668    pub fn rpue0(
4669        self,
4670    ) -> crate::common::RegisterField<
4671        1,
4672        0x1,
4673        1,
4674        0,
4675        dpusr0r::Rpue0,
4676        dpusr0r::Rpue0,
4677        Dpusr0R_SPEC,
4678        crate::common::RW,
4679    > {
4680        crate::common::RegisterField::<
4681            1,
4682            0x1,
4683            1,
4684            0,
4685            dpusr0r::Rpue0,
4686            dpusr0r::Rpue0,
4687            Dpusr0R_SPEC,
4688            crate::common::RW,
4689        >::from_register(self, 0)
4690    }
4691
4692    #[doc = "USB Transceiver Output Fix"]
4693    #[inline(always)]
4694    pub fn fixphy0(
4695        self,
4696    ) -> crate::common::RegisterField<
4697        4,
4698        0x1,
4699        1,
4700        0,
4701        dpusr0r::Fixphy0,
4702        dpusr0r::Fixphy0,
4703        Dpusr0R_SPEC,
4704        crate::common::RW,
4705    > {
4706        crate::common::RegisterField::<
4707            4,
4708            0x1,
4709            1,
4710            0,
4711            dpusr0r::Fixphy0,
4712            dpusr0r::Fixphy0,
4713            Dpusr0R_SPEC,
4714            crate::common::RW,
4715        >::from_register(self, 0)
4716    }
4717
4718    #[doc = "USB D+ Input"]
4719    #[inline(always)]
4720    pub fn dp0(self) -> crate::common::RegisterFieldBool<16, 1, 0, Dpusr0R_SPEC, crate::common::R> {
4721        crate::common::RegisterFieldBool::<16, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
4722            self, 0,
4723        )
4724    }
4725
4726    #[doc = "USB D- Input"]
4727    #[inline(always)]
4728    pub fn dm0(self) -> crate::common::RegisterFieldBool<17, 1, 0, Dpusr0R_SPEC, crate::common::R> {
4729        crate::common::RegisterFieldBool::<17, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
4730            self, 0,
4731        )
4732    }
4733
4734    #[doc = "USB VBUS Input"]
4735    #[inline(always)]
4736    pub fn dvbsts0(
4737        self,
4738    ) -> crate::common::RegisterFieldBool<23, 1, 0, Dpusr0R_SPEC, crate::common::R> {
4739        crate::common::RegisterFieldBool::<23, 1, 0, Dpusr0R_SPEC, crate::common::R>::from_register(
4740            self, 0,
4741        )
4742    }
4743}
4744impl ::core::default::Default for Dpusr0R {
4745    #[inline(always)]
4746    fn default() -> Dpusr0R {
4747        <crate::RegValueT<Dpusr0R_SPEC> as RegisterValue<_>>::new(0)
4748    }
4749}
4750pub mod dpusr0r {
4751
4752    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4753    pub struct Srpc0_SPEC;
4754    pub type Srpc0 = crate::EnumBitfieldStruct<u8, Srpc0_SPEC>;
4755    impl Srpc0 {
4756        #[doc = "Disable input through DP and DM inputs"]
4757        pub const _0: Self = Self::new(0);
4758
4759        #[doc = "Enable input through DP and DM inputs"]
4760        pub const _1: Self = Self::new(1);
4761    }
4762    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4763    pub struct Rpue0_SPEC;
4764    pub type Rpue0 = crate::EnumBitfieldStruct<u8, Rpue0_SPEC>;
4765    impl Rpue0 {
4766        #[doc = "Disable DP pull-up resistor"]
4767        pub const _0: Self = Self::new(0);
4768
4769        #[doc = "Enable DP pull-up resistor"]
4770        pub const _1: Self = Self::new(1);
4771    }
4772    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4773    pub struct Fixphy0_SPEC;
4774    pub type Fixphy0 = crate::EnumBitfieldStruct<u8, Fixphy0_SPEC>;
4775    impl Fixphy0 {
4776        #[doc = "Fix outputs in Normal mode and on return from Deep Software Standby mode"]
4777        pub const _0: Self = Self::new(0);
4778
4779        #[doc = "Fix outputs on transition to Deep Software Standby mode"]
4780        pub const _1: Self = Self::new(1);
4781    }
4782}
4783#[doc(hidden)]
4784#[derive(Copy, Clone, Eq, PartialEq)]
4785pub struct Dpusr1R_SPEC;
4786impl crate::sealed::RegSpec for Dpusr1R_SPEC {
4787    type DataType = u32;
4788}
4789
4790#[doc = "Deep Software Standby USB Suspend/Resume Interrupt Register"]
4791pub type Dpusr1R = crate::RegValueT<Dpusr1R_SPEC>;
4792
4793impl Dpusr1R {
4794    #[doc = "USB DP Interrupt Enable/Clear"]
4795    #[inline(always)]
4796    pub fn dpinte0(
4797        self,
4798    ) -> crate::common::RegisterField<
4799        0,
4800        0x1,
4801        1,
4802        0,
4803        dpusr1r::Dpinte0,
4804        dpusr1r::Dpinte0,
4805        Dpusr1R_SPEC,
4806        crate::common::RW,
4807    > {
4808        crate::common::RegisterField::<
4809            0,
4810            0x1,
4811            1,
4812            0,
4813            dpusr1r::Dpinte0,
4814            dpusr1r::Dpinte0,
4815            Dpusr1R_SPEC,
4816            crate::common::RW,
4817        >::from_register(self, 0)
4818    }
4819
4820    #[doc = "USB DM Interrupt Enable/Clear"]
4821    #[inline(always)]
4822    pub fn dminte0(
4823        self,
4824    ) -> crate::common::RegisterField<
4825        1,
4826        0x1,
4827        1,
4828        0,
4829        dpusr1r::Dminte0,
4830        dpusr1r::Dminte0,
4831        Dpusr1R_SPEC,
4832        crate::common::RW,
4833    > {
4834        crate::common::RegisterField::<
4835            1,
4836            0x1,
4837            1,
4838            0,
4839            dpusr1r::Dminte0,
4840            dpusr1r::Dminte0,
4841            Dpusr1R_SPEC,
4842            crate::common::RW,
4843        >::from_register(self, 0)
4844    }
4845
4846    #[doc = "USB VBUS Interrupt Enable/Clear"]
4847    #[inline(always)]
4848    pub fn dvbse0(
4849        self,
4850    ) -> crate::common::RegisterField<
4851        7,
4852        0x1,
4853        1,
4854        0,
4855        dpusr1r::Dvbse0,
4856        dpusr1r::Dvbse0,
4857        Dpusr1R_SPEC,
4858        crate::common::RW,
4859    > {
4860        crate::common::RegisterField::<
4861            7,
4862            0x1,
4863            1,
4864            0,
4865            dpusr1r::Dvbse0,
4866            dpusr1r::Dvbse0,
4867            Dpusr1R_SPEC,
4868            crate::common::RW,
4869        >::from_register(self, 0)
4870    }
4871
4872    #[doc = "USB DP Interrupt Source Recovery"]
4873    #[inline(always)]
4874    pub fn dpint0(
4875        self,
4876    ) -> crate::common::RegisterField<
4877        16,
4878        0x1,
4879        1,
4880        0,
4881        dpusr1r::Dpint0,
4882        dpusr1r::Dpint0,
4883        Dpusr1R_SPEC,
4884        crate::common::R,
4885    > {
4886        crate::common::RegisterField::<
4887            16,
4888            0x1,
4889            1,
4890            0,
4891            dpusr1r::Dpint0,
4892            dpusr1r::Dpint0,
4893            Dpusr1R_SPEC,
4894            crate::common::R,
4895        >::from_register(self, 0)
4896    }
4897
4898    #[doc = "USB DM Interrupt Source Recovery"]
4899    #[inline(always)]
4900    pub fn dmint0(
4901        self,
4902    ) -> crate::common::RegisterField<
4903        17,
4904        0x1,
4905        1,
4906        0,
4907        dpusr1r::Dmint0,
4908        dpusr1r::Dmint0,
4909        Dpusr1R_SPEC,
4910        crate::common::R,
4911    > {
4912        crate::common::RegisterField::<
4913            17,
4914            0x1,
4915            1,
4916            0,
4917            dpusr1r::Dmint0,
4918            dpusr1r::Dmint0,
4919            Dpusr1R_SPEC,
4920            crate::common::R,
4921        >::from_register(self, 0)
4922    }
4923
4924    #[doc = "USB VBUS Interrupt Source Recovery"]
4925    #[inline(always)]
4926    pub fn dvbint0(
4927        self,
4928    ) -> crate::common::RegisterField<
4929        23,
4930        0x1,
4931        1,
4932        0,
4933        dpusr1r::Dvbint0,
4934        dpusr1r::Dvbint0,
4935        Dpusr1R_SPEC,
4936        crate::common::R,
4937    > {
4938        crate::common::RegisterField::<
4939            23,
4940            0x1,
4941            1,
4942            0,
4943            dpusr1r::Dvbint0,
4944            dpusr1r::Dvbint0,
4945            Dpusr1R_SPEC,
4946            crate::common::R,
4947        >::from_register(self, 0)
4948    }
4949}
4950impl ::core::default::Default for Dpusr1R {
4951    #[inline(always)]
4952    fn default() -> Dpusr1R {
4953        <crate::RegValueT<Dpusr1R_SPEC> as RegisterValue<_>>::new(0)
4954    }
4955}
4956pub mod dpusr1r {
4957
4958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4959    pub struct Dpinte0_SPEC;
4960    pub type Dpinte0 = crate::EnumBitfieldStruct<u8, Dpinte0_SPEC>;
4961    impl Dpinte0 {
4962        #[doc = "Disable recovery from Deep Software Standby mode by DP input"]
4963        pub const _0: Self = Self::new(0);
4964
4965        #[doc = "Enable recovery from Deep Software Standby mode by DP input"]
4966        pub const _1: Self = Self::new(1);
4967    }
4968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4969    pub struct Dminte0_SPEC;
4970    pub type Dminte0 = crate::EnumBitfieldStruct<u8, Dminte0_SPEC>;
4971    impl Dminte0 {
4972        #[doc = "Disable recovery from Deep Software Standby mode by DM input"]
4973        pub const _0: Self = Self::new(0);
4974
4975        #[doc = "Enable recovery from Deep Software Standby mode by DM input"]
4976        pub const _1: Self = Self::new(1);
4977    }
4978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4979    pub struct Dvbse0_SPEC;
4980    pub type Dvbse0 = crate::EnumBitfieldStruct<u8, Dvbse0_SPEC>;
4981    impl Dvbse0 {
4982        #[doc = "Disable recovery from Deep Software Standby mode by VBUS input"]
4983        pub const _0: Self = Self::new(0);
4984
4985        #[doc = "Enable recovery from Deep Software Standby mode by VBUS input"]
4986        pub const _1: Self = Self::new(1);
4987    }
4988    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4989    pub struct Dpint0_SPEC;
4990    pub type Dpint0 = crate::EnumBitfieldStruct<u8, Dpint0_SPEC>;
4991    impl Dpint0 {
4992        #[doc = "System has not recovered from Deep Software Standby mode"]
4993        pub const _0: Self = Self::new(0);
4994
4995        #[doc = "System recovered from Deep Software Standby mode because of DP"]
4996        pub const _1: Self = Self::new(1);
4997    }
4998    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4999    pub struct Dmint0_SPEC;
5000    pub type Dmint0 = crate::EnumBitfieldStruct<u8, Dmint0_SPEC>;
5001    impl Dmint0 {
5002        #[doc = "System has not recovered from Deep Software Standby mode"]
5003        pub const _0: Self = Self::new(0);
5004
5005        #[doc = "System recovered from Deep Software Standby mode because of DM input"]
5006        pub const _1: Self = Self::new(1);
5007    }
5008    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5009    pub struct Dvbint0_SPEC;
5010    pub type Dvbint0 = crate::EnumBitfieldStruct<u8, Dvbint0_SPEC>;
5011    impl Dvbint0 {
5012        #[doc = "System has not recovered from Deep Software Standby mode"]
5013        pub const _0: Self = Self::new(0);
5014
5015        #[doc = "System recovered from Deep Software Standby mode because of VBUS input"]
5016        pub const _1: Self = Self::new(1);
5017    }
5018}
ra4e2_pac/usbfs.rs

ra4e2_pac/
usbfs.rs
