1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Bus Control"]
28unsafe impl ::core::marker::Send for super::Bus {}
29unsafe impl ::core::marker::Sync for super::Bus {}
30impl super::Bus {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Slave Bus Control Register"]
38 #[inline(always)]
39 pub const fn busscntfhbiu(
40 &self,
41 ) -> &'static crate::common::Reg<self::Busscntfhbiu_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Busscntfhbiu_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(4352usize),
45 )
46 }
47 }
48
49 #[doc = "Slave Bus Control Register"]
50 #[inline(always)]
51 pub const fn busscntflbiu(
52 &self,
53 ) -> &'static crate::common::Reg<self::Busscntflbiu_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Busscntflbiu_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(4356usize),
57 )
58 }
59 }
60
61 #[doc = "Slave Bus Control Register"]
62 #[inline(always)]
63 pub const fn busscnts0biu(
64 &self,
65 ) -> &'static crate::common::Reg<self::Busscnts0Biu_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Busscnts0Biu_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(4368usize),
69 )
70 }
71 }
72
73 #[doc = "Slave Bus Control Register"]
74 #[inline(always)]
75 pub const fn busscntpsbiu(
76 &self,
77 ) -> &'static crate::common::Reg<self::Busscntpsbiu_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::Busscntpsbiu_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(4384usize),
81 )
82 }
83 }
84
85 #[doc = "Slave Bus Control Register"]
86 #[inline(always)]
87 pub const fn busscntplbiu(
88 &self,
89 ) -> &'static crate::common::Reg<self::Busscntplbiu_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Busscntplbiu_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(4400usize),
93 )
94 }
95 }
96
97 #[doc = "Slave Bus Control Register"]
98 #[inline(always)]
99 pub const fn busscntphbiu(
100 &self,
101 ) -> &'static crate::common::Reg<self::Busscntphbiu_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::Busscntphbiu_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(4404usize),
105 )
106 }
107 }
108
109 #[doc = "BUS Error Address Register"]
110 #[inline(always)]
111 pub const fn buserradd(
112 &self,
113 ) -> &'static crate::common::ClusterRegisterArray<
114 crate::common::Reg<self::Buserradd_SPEC, crate::common::R>,
115 3,
116 0x10,
117 > {
118 unsafe {
119 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1800usize))
120 }
121 }
122 #[inline(always)]
123 pub const fn bus1erradd(
124 &self,
125 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
126 unsafe {
127 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
128 self._svd2pac_as_ptr().add(0x1800usize),
129 )
130 }
131 }
132 #[inline(always)]
133 pub const fn bus2erradd(
134 &self,
135 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
136 unsafe {
137 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
138 self._svd2pac_as_ptr().add(0x1810usize),
139 )
140 }
141 }
142 #[inline(always)]
143 pub const fn bus3erradd(
144 &self,
145 ) -> &'static crate::common::Reg<self::Buserradd_SPEC, crate::common::R> {
146 unsafe {
147 crate::common::Reg::<self::Buserradd_SPEC, crate::common::R>::from_ptr(
148 self._svd2pac_as_ptr().add(0x1820usize),
149 )
150 }
151 }
152
153 #[doc = "BUS Error Read Write Register"]
154 #[inline(always)]
155 pub const fn buserrrw(
156 &self,
157 ) -> &'static crate::common::ClusterRegisterArray<
158 crate::common::Reg<self::Buserrrw_SPEC, crate::common::RW>,
159 3,
160 0x10,
161 > {
162 unsafe {
163 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1804usize))
164 }
165 }
166 #[inline(always)]
167 pub const fn bus1errrw(
168 &self,
169 ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::RW> {
170 unsafe {
171 crate::common::Reg::<self::Buserrrw_SPEC, crate::common::RW>::from_ptr(
172 self._svd2pac_as_ptr().add(0x1804usize),
173 )
174 }
175 }
176 #[inline(always)]
177 pub const fn bus2errrw(
178 &self,
179 ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::RW> {
180 unsafe {
181 crate::common::Reg::<self::Buserrrw_SPEC, crate::common::RW>::from_ptr(
182 self._svd2pac_as_ptr().add(0x1814usize),
183 )
184 }
185 }
186 #[inline(always)]
187 pub const fn bus3errrw(
188 &self,
189 ) -> &'static crate::common::Reg<self::Buserrrw_SPEC, crate::common::RW> {
190 unsafe {
191 crate::common::Reg::<self::Buserrrw_SPEC, crate::common::RW>::from_ptr(
192 self._svd2pac_as_ptr().add(0x1824usize),
193 )
194 }
195 }
196
197 #[doc = "BUS TZF Error Address Register"]
198 #[inline(always)]
199 pub const fn btzferradd(
200 &self,
201 ) -> &'static crate::common::ClusterRegisterArray<
202 crate::common::Reg<self::Btzferradd_SPEC, crate::common::R>,
203 3,
204 0x10,
205 > {
206 unsafe {
207 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1900usize))
208 }
209 }
210 #[inline(always)]
211 pub const fn btzf1erradd(
212 &self,
213 ) -> &'static crate::common::Reg<self::Btzferradd_SPEC, crate::common::R> {
214 unsafe {
215 crate::common::Reg::<self::Btzferradd_SPEC, crate::common::R>::from_ptr(
216 self._svd2pac_as_ptr().add(0x1900usize),
217 )
218 }
219 }
220 #[inline(always)]
221 pub const fn btzf2erradd(
222 &self,
223 ) -> &'static crate::common::Reg<self::Btzferradd_SPEC, crate::common::R> {
224 unsafe {
225 crate::common::Reg::<self::Btzferradd_SPEC, crate::common::R>::from_ptr(
226 self._svd2pac_as_ptr().add(0x1910usize),
227 )
228 }
229 }
230 #[inline(always)]
231 pub const fn btzf3erradd(
232 &self,
233 ) -> &'static crate::common::Reg<self::Btzferradd_SPEC, crate::common::R> {
234 unsafe {
235 crate::common::Reg::<self::Btzferradd_SPEC, crate::common::R>::from_ptr(
236 self._svd2pac_as_ptr().add(0x1920usize),
237 )
238 }
239 }
240
241 #[doc = "BUS TZF Error Read Write Register"]
242 #[inline(always)]
243 pub const fn btzferrrw(
244 &self,
245 ) -> &'static crate::common::ClusterRegisterArray<
246 crate::common::Reg<self::Btzferrrw_SPEC, crate::common::RW>,
247 3,
248 0x10,
249 > {
250 unsafe {
251 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1904usize))
252 }
253 }
254 #[inline(always)]
255 pub const fn btzf1errrw(
256 &self,
257 ) -> &'static crate::common::Reg<self::Btzferrrw_SPEC, crate::common::RW> {
258 unsafe {
259 crate::common::Reg::<self::Btzferrrw_SPEC, crate::common::RW>::from_ptr(
260 self._svd2pac_as_ptr().add(0x1904usize),
261 )
262 }
263 }
264 #[inline(always)]
265 pub const fn btzf2errrw(
266 &self,
267 ) -> &'static crate::common::Reg<self::Btzferrrw_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Btzferrrw_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(0x1914usize),
271 )
272 }
273 }
274 #[inline(always)]
275 pub const fn btzf3errrw(
276 &self,
277 ) -> &'static crate::common::Reg<self::Btzferrrw_SPEC, crate::common::RW> {
278 unsafe {
279 crate::common::Reg::<self::Btzferrrw_SPEC, crate::common::RW>::from_ptr(
280 self._svd2pac_as_ptr().add(0x1924usize),
281 )
282 }
283 }
284
285 #[doc = "BUS Error Status Register %s"]
286 #[inline(always)]
287 pub const fn buserrstat(
288 &self,
289 ) -> &'static crate::common::ClusterRegisterArray<
290 crate::common::Reg<self::Buserrstat_SPEC, crate::common::R>,
291 3,
292 0x10,
293 > {
294 unsafe {
295 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1a00usize))
296 }
297 }
298 #[inline(always)]
299 pub const fn bus1errstat(
300 &self,
301 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
302 unsafe {
303 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
304 self._svd2pac_as_ptr().add(0x1a00usize),
305 )
306 }
307 }
308 #[inline(always)]
309 pub const fn bus2errstat(
310 &self,
311 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
312 unsafe {
313 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
314 self._svd2pac_as_ptr().add(0x1a10usize),
315 )
316 }
317 }
318 #[inline(always)]
319 pub const fn bus3errstat(
320 &self,
321 ) -> &'static crate::common::Reg<self::Buserrstat_SPEC, crate::common::R> {
322 unsafe {
323 crate::common::Reg::<self::Buserrstat_SPEC, crate::common::R>::from_ptr(
324 self._svd2pac_as_ptr().add(0x1a20usize),
325 )
326 }
327 }
328
329 #[doc = "BUS Error Clear Register %s"]
330 #[inline(always)]
331 pub const fn buserrclr(
332 &self,
333 ) -> &'static crate::common::ClusterRegisterArray<
334 crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW>,
335 3,
336 0x10,
337 > {
338 unsafe {
339 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x1a08usize))
340 }
341 }
342 #[inline(always)]
343 pub const fn bus1errclr(
344 &self,
345 ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
346 unsafe {
347 crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
348 self._svd2pac_as_ptr().add(0x1a08usize),
349 )
350 }
351 }
352 #[inline(always)]
353 pub const fn bus2errclr(
354 &self,
355 ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(0x1a18usize),
359 )
360 }
361 }
362 #[inline(always)]
363 pub const fn bus3errclr(
364 &self,
365 ) -> &'static crate::common::Reg<self::Buserrclr_SPEC, crate::common::RW> {
366 unsafe {
367 crate::common::Reg::<self::Buserrclr_SPEC, crate::common::RW>::from_ptr(
368 self._svd2pac_as_ptr().add(0x1a28usize),
369 )
370 }
371 }
372
373 #[doc = "DMAC/DTC Error Status Register"]
374 #[inline(always)]
375 pub const fn dmacdtcerrstat(
376 &self,
377 ) -> &'static crate::common::Reg<self::Dmacdtcerrstat_SPEC, crate::common::R> {
378 unsafe {
379 crate::common::Reg::<self::Dmacdtcerrstat_SPEC, crate::common::R>::from_ptr(
380 self._svd2pac_as_ptr().add(6692usize),
381 )
382 }
383 }
384
385 #[doc = "DMAC/DTC Error Clear Register"]
386 #[inline(always)]
387 pub const fn dmacdtcerrclr(
388 &self,
389 ) -> &'static crate::common::Reg<self::Dmacdtcerrclr_SPEC, crate::common::RW> {
390 unsafe {
391 crate::common::Reg::<self::Dmacdtcerrclr_SPEC, crate::common::RW>::from_ptr(
392 self._svd2pac_as_ptr().add(6700usize),
393 )
394 }
395 }
396}
397#[doc(hidden)]
398#[derive(Copy, Clone, Eq, PartialEq)]
399pub struct Busscntfhbiu_SPEC;
400impl crate::sealed::RegSpec for Busscntfhbiu_SPEC {
401 type DataType = u16;
402}
403
404#[doc = "Slave Bus Control Register"]
405pub type Busscntfhbiu = crate::RegValueT<Busscntfhbiu_SPEC>;
406
407impl Busscntfhbiu {
408 #[doc = "Arbitration Select for two masters"]
409 #[inline(always)]
410 pub fn arbs(
411 self,
412 ) -> crate::common::RegisterField<
413 0,
414 0x3,
415 1,
416 0,
417 busscntfhbiu::Arbs,
418 busscntfhbiu::Arbs,
419 Busscntfhbiu_SPEC,
420 crate::common::RW,
421 > {
422 crate::common::RegisterField::<
423 0,
424 0x3,
425 1,
426 0,
427 busscntfhbiu::Arbs,
428 busscntfhbiu::Arbs,
429 Busscntfhbiu_SPEC,
430 crate::common::RW,
431 >::from_register(self, 0)
432 }
433}
434impl ::core::default::Default for Busscntfhbiu {
435 #[inline(always)]
436 fn default() -> Busscntfhbiu {
437 <crate::RegValueT<Busscntfhbiu_SPEC> as RegisterValue<_>>::new(0)
438 }
439}
440pub mod busscntfhbiu {
441
442 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
443 pub struct Arbs_SPEC;
444 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
445 impl Arbs {
446 #[doc = "DMAC/DTC > CPU"]
447 pub const _00: Self = Self::new(0);
448
449 #[doc = "DMAC/DTC ↔ CPU"]
450 pub const _01: Self = Self::new(1);
451 }
452}
453#[doc(hidden)]
454#[derive(Copy, Clone, Eq, PartialEq)]
455pub struct Busscntflbiu_SPEC;
456impl crate::sealed::RegSpec for Busscntflbiu_SPEC {
457 type DataType = u16;
458}
459
460#[doc = "Slave Bus Control Register"]
461pub type Busscntflbiu = crate::RegValueT<Busscntflbiu_SPEC>;
462
463impl Busscntflbiu {
464 #[doc = "Arbitration Select for two masters"]
465 #[inline(always)]
466 pub fn arbs(
467 self,
468 ) -> crate::common::RegisterField<
469 0,
470 0x3,
471 1,
472 0,
473 busscntflbiu::Arbs,
474 busscntflbiu::Arbs,
475 Busscntflbiu_SPEC,
476 crate::common::RW,
477 > {
478 crate::common::RegisterField::<
479 0,
480 0x3,
481 1,
482 0,
483 busscntflbiu::Arbs,
484 busscntflbiu::Arbs,
485 Busscntflbiu_SPEC,
486 crate::common::RW,
487 >::from_register(self, 0)
488 }
489}
490impl ::core::default::Default for Busscntflbiu {
491 #[inline(always)]
492 fn default() -> Busscntflbiu {
493 <crate::RegValueT<Busscntflbiu_SPEC> as RegisterValue<_>>::new(0)
494 }
495}
496pub mod busscntflbiu {
497
498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
499 pub struct Arbs_SPEC;
500 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
501 impl Arbs {
502 #[doc = "DMAC/DTC > CPU"]
503 pub const _00: Self = Self::new(0);
504
505 #[doc = "DMAC/DTC ↔ CPU"]
506 pub const _01: Self = Self::new(1);
507 }
508}
509#[doc(hidden)]
510#[derive(Copy, Clone, Eq, PartialEq)]
511pub struct Busscnts0Biu_SPEC;
512impl crate::sealed::RegSpec for Busscnts0Biu_SPEC {
513 type DataType = u16;
514}
515
516#[doc = "Slave Bus Control Register"]
517pub type Busscnts0Biu = crate::RegValueT<Busscnts0Biu_SPEC>;
518
519impl Busscnts0Biu {
520 #[doc = "Arbitration Select for two masters"]
521 #[inline(always)]
522 pub fn arbs(
523 self,
524 ) -> crate::common::RegisterField<
525 0,
526 0x3,
527 1,
528 0,
529 busscnts0biu::Arbs,
530 busscnts0biu::Arbs,
531 Busscnts0Biu_SPEC,
532 crate::common::RW,
533 > {
534 crate::common::RegisterField::<
535 0,
536 0x3,
537 1,
538 0,
539 busscnts0biu::Arbs,
540 busscnts0biu::Arbs,
541 Busscnts0Biu_SPEC,
542 crate::common::RW,
543 >::from_register(self, 0)
544 }
545}
546impl ::core::default::Default for Busscnts0Biu {
547 #[inline(always)]
548 fn default() -> Busscnts0Biu {
549 <crate::RegValueT<Busscnts0Biu_SPEC> as RegisterValue<_>>::new(0)
550 }
551}
552pub mod busscnts0biu {
553
554 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
555 pub struct Arbs_SPEC;
556 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
557 impl Arbs {
558 #[doc = "DMAC/DTC > CPU"]
559 pub const _00: Self = Self::new(0);
560
561 #[doc = "DMAC/DTC ↔ CPU"]
562 pub const _01: Self = Self::new(1);
563 }
564}
565#[doc(hidden)]
566#[derive(Copy, Clone, Eq, PartialEq)]
567pub struct Busscntpsbiu_SPEC;
568impl crate::sealed::RegSpec for Busscntpsbiu_SPEC {
569 type DataType = u16;
570}
571
572#[doc = "Slave Bus Control Register"]
573pub type Busscntpsbiu = crate::RegValueT<Busscntpsbiu_SPEC>;
574
575impl Busscntpsbiu {
576 #[doc = "Arbitration Select for two masters"]
577 #[inline(always)]
578 pub fn arbs(
579 self,
580 ) -> crate::common::RegisterField<
581 0,
582 0x1,
583 1,
584 0,
585 busscntpsbiu::Arbs,
586 busscntpsbiu::Arbs,
587 Busscntpsbiu_SPEC,
588 crate::common::RW,
589 > {
590 crate::common::RegisterField::<
591 0,
592 0x1,
593 1,
594 0,
595 busscntpsbiu::Arbs,
596 busscntpsbiu::Arbs,
597 Busscntpsbiu_SPEC,
598 crate::common::RW,
599 >::from_register(self, 0)
600 }
601}
602impl ::core::default::Default for Busscntpsbiu {
603 #[inline(always)]
604 fn default() -> Busscntpsbiu {
605 <crate::RegValueT<Busscntpsbiu_SPEC> as RegisterValue<_>>::new(0)
606 }
607}
608pub mod busscntpsbiu {
609
610 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
611 pub struct Arbs_SPEC;
612 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
613 impl Arbs {
614 #[doc = "DMAC/DTC > CPU"]
615 pub const _0: Self = Self::new(0);
616
617 #[doc = "DMAC/DTC ↔ CPU"]
618 pub const _1: Self = Self::new(1);
619 }
620}
621#[doc(hidden)]
622#[derive(Copy, Clone, Eq, PartialEq)]
623pub struct Busscntplbiu_SPEC;
624impl crate::sealed::RegSpec for Busscntplbiu_SPEC {
625 type DataType = u16;
626}
627
628#[doc = "Slave Bus Control Register"]
629pub type Busscntplbiu = crate::RegValueT<Busscntplbiu_SPEC>;
630
631impl Busscntplbiu {
632 #[doc = "Arbitration Select for two masters"]
633 #[inline(always)]
634 pub fn arbs(
635 self,
636 ) -> crate::common::RegisterField<
637 0,
638 0x1,
639 1,
640 0,
641 busscntplbiu::Arbs,
642 busscntplbiu::Arbs,
643 Busscntplbiu_SPEC,
644 crate::common::RW,
645 > {
646 crate::common::RegisterField::<
647 0,
648 0x1,
649 1,
650 0,
651 busscntplbiu::Arbs,
652 busscntplbiu::Arbs,
653 Busscntplbiu_SPEC,
654 crate::common::RW,
655 >::from_register(self, 0)
656 }
657}
658impl ::core::default::Default for Busscntplbiu {
659 #[inline(always)]
660 fn default() -> Busscntplbiu {
661 <crate::RegValueT<Busscntplbiu_SPEC> as RegisterValue<_>>::new(0)
662 }
663}
664pub mod busscntplbiu {
665
666 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
667 pub struct Arbs_SPEC;
668 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
669 impl Arbs {
670 #[doc = "DMAC/DTC > CPU"]
671 pub const _0: Self = Self::new(0);
672
673 #[doc = "DMAC/DTC ↔ CPU"]
674 pub const _1: Self = Self::new(1);
675 }
676}
677#[doc(hidden)]
678#[derive(Copy, Clone, Eq, PartialEq)]
679pub struct Busscntphbiu_SPEC;
680impl crate::sealed::RegSpec for Busscntphbiu_SPEC {
681 type DataType = u16;
682}
683
684#[doc = "Slave Bus Control Register"]
685pub type Busscntphbiu = crate::RegValueT<Busscntphbiu_SPEC>;
686
687impl Busscntphbiu {
688 #[doc = "Arbitration Select for two masters"]
689 #[inline(always)]
690 pub fn arbs(
691 self,
692 ) -> crate::common::RegisterField<
693 0,
694 0x1,
695 1,
696 0,
697 busscntphbiu::Arbs,
698 busscntphbiu::Arbs,
699 Busscntphbiu_SPEC,
700 crate::common::RW,
701 > {
702 crate::common::RegisterField::<
703 0,
704 0x1,
705 1,
706 0,
707 busscntphbiu::Arbs,
708 busscntphbiu::Arbs,
709 Busscntphbiu_SPEC,
710 crate::common::RW,
711 >::from_register(self, 0)
712 }
713}
714impl ::core::default::Default for Busscntphbiu {
715 #[inline(always)]
716 fn default() -> Busscntphbiu {
717 <crate::RegValueT<Busscntphbiu_SPEC> as RegisterValue<_>>::new(0)
718 }
719}
720pub mod busscntphbiu {
721
722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
723 pub struct Arbs_SPEC;
724 pub type Arbs = crate::EnumBitfieldStruct<u8, Arbs_SPEC>;
725 impl Arbs {
726 #[doc = "DMAC/DTC > CPU"]
727 pub const _0: Self = Self::new(0);
728
729 #[doc = "DMAC/DTC ↔ CPU"]
730 pub const _1: Self = Self::new(1);
731 }
732}
733#[doc(hidden)]
734#[derive(Copy, Clone, Eq, PartialEq)]
735pub struct Buserradd_SPEC;
736impl crate::sealed::RegSpec for Buserradd_SPEC {
737 type DataType = u32;
738}
739
740#[doc = "BUS Error Address Register"]
741pub type Buserradd = crate::RegValueT<Buserradd_SPEC>;
742
743impl Buserradd {
744 #[doc = "Bus Error Address"]
745 #[inline(always)]
746 pub fn berad(
747 self,
748 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Buserradd_SPEC, crate::common::R>
749 {
750 crate::common::RegisterField::<
751 0,
752 0xffffffff,
753 1,
754 0,
755 u32,
756 u32,
757 Buserradd_SPEC,
758 crate::common::R,
759 >::from_register(self, 0)
760 }
761}
762impl ::core::default::Default for Buserradd {
763 #[inline(always)]
764 fn default() -> Buserradd {
765 <crate::RegValueT<Buserradd_SPEC> as RegisterValue<_>>::new(0)
766 }
767}
768
769#[doc(hidden)]
770#[derive(Copy, Clone, Eq, PartialEq)]
771pub struct Buserrrw_SPEC;
772impl crate::sealed::RegSpec for Buserrrw_SPEC {
773 type DataType = u8;
774}
775
776#[doc = "BUS Error Read Write Register"]
777pub type Buserrrw = crate::RegValueT<Buserrrw_SPEC>;
778
779impl Buserrrw {
780 #[doc = "Error Access Read/Write Status"]
781 #[inline(always)]
782 pub fn rwstat(
783 self,
784 ) -> crate::common::RegisterField<
785 0,
786 0x1,
787 1,
788 0,
789 buserrrw::Rwstat,
790 buserrrw::Rwstat,
791 Buserrrw_SPEC,
792 crate::common::R,
793 > {
794 crate::common::RegisterField::<
795 0,
796 0x1,
797 1,
798 0,
799 buserrrw::Rwstat,
800 buserrrw::Rwstat,
801 Buserrrw_SPEC,
802 crate::common::R,
803 >::from_register(self, 0)
804 }
805}
806impl ::core::default::Default for Buserrrw {
807 #[inline(always)]
808 fn default() -> Buserrrw {
809 <crate::RegValueT<Buserrrw_SPEC> as RegisterValue<_>>::new(0)
810 }
811}
812pub mod buserrrw {
813
814 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
815 pub struct Rwstat_SPEC;
816 pub type Rwstat = crate::EnumBitfieldStruct<u8, Rwstat_SPEC>;
817 impl Rwstat {
818 #[doc = "Read access"]
819 pub const _0: Self = Self::new(0);
820
821 #[doc = "Write access"]
822 pub const _1: Self = Self::new(1);
823 }
824}
825#[doc(hidden)]
826#[derive(Copy, Clone, Eq, PartialEq)]
827pub struct Btzferradd_SPEC;
828impl crate::sealed::RegSpec for Btzferradd_SPEC {
829 type DataType = u32;
830}
831
832#[doc = "BUS TZF Error Address Register"]
833pub type Btzferradd = crate::RegValueT<Btzferradd_SPEC>;
834
835impl Btzferradd {
836 #[doc = "Bus TrustZone Filter Error Address"]
837 #[inline(always)]
838 pub fn btzferad(
839 self,
840 ) -> crate::common::RegisterField<
841 0,
842 0xffffffff,
843 1,
844 0,
845 u32,
846 u32,
847 Btzferradd_SPEC,
848 crate::common::R,
849 > {
850 crate::common::RegisterField::<
851 0,
852 0xffffffff,
853 1,
854 0,
855 u32,
856 u32,
857 Btzferradd_SPEC,
858 crate::common::R,
859 >::from_register(self, 0)
860 }
861}
862impl ::core::default::Default for Btzferradd {
863 #[inline(always)]
864 fn default() -> Btzferradd {
865 <crate::RegValueT<Btzferradd_SPEC> as RegisterValue<_>>::new(0)
866 }
867}
868
869#[doc(hidden)]
870#[derive(Copy, Clone, Eq, PartialEq)]
871pub struct Btzferrrw_SPEC;
872impl crate::sealed::RegSpec for Btzferrrw_SPEC {
873 type DataType = u8;
874}
875
876#[doc = "BUS TZF Error Read Write Register"]
877pub type Btzferrrw = crate::RegValueT<Btzferrrw_SPEC>;
878
879impl Btzferrrw {
880 #[doc = "TrustZone filter error access Read/Write Status"]
881 #[inline(always)]
882 pub fn trwstat(
883 self,
884 ) -> crate::common::RegisterField<
885 0,
886 0x1,
887 1,
888 0,
889 btzferrrw::Trwstat,
890 btzferrrw::Trwstat,
891 Btzferrrw_SPEC,
892 crate::common::R,
893 > {
894 crate::common::RegisterField::<
895 0,
896 0x1,
897 1,
898 0,
899 btzferrrw::Trwstat,
900 btzferrrw::Trwstat,
901 Btzferrrw_SPEC,
902 crate::common::R,
903 >::from_register(self, 0)
904 }
905}
906impl ::core::default::Default for Btzferrrw {
907 #[inline(always)]
908 fn default() -> Btzferrrw {
909 <crate::RegValueT<Btzferrrw_SPEC> as RegisterValue<_>>::new(0)
910 }
911}
912pub mod btzferrrw {
913
914 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
915 pub struct Trwstat_SPEC;
916 pub type Trwstat = crate::EnumBitfieldStruct<u8, Trwstat_SPEC>;
917 impl Trwstat {
918 #[doc = "Read access"]
919 pub const _0: Self = Self::new(0);
920
921 #[doc = "Write access"]
922 pub const _1: Self = Self::new(1);
923 }
924}
925#[doc(hidden)]
926#[derive(Copy, Clone, Eq, PartialEq)]
927pub struct Buserrstat_SPEC;
928impl crate::sealed::RegSpec for Buserrstat_SPEC {
929 type DataType = u8;
930}
931
932#[doc = "BUS Error Status Register %s"]
933pub type Buserrstat = crate::RegValueT<Buserrstat_SPEC>;
934
935impl Buserrstat {
936 #[doc = "Slave bus Error Status"]
937 #[inline(always)]
938 pub fn slerrstat(
939 self,
940 ) -> crate::common::RegisterField<
941 0,
942 0x1,
943 1,
944 0,
945 buserrstat::Slerrstat,
946 buserrstat::Slerrstat,
947 Buserrstat_SPEC,
948 crate::common::R,
949 > {
950 crate::common::RegisterField::<
951 0,
952 0x1,
953 1,
954 0,
955 buserrstat::Slerrstat,
956 buserrstat::Slerrstat,
957 Buserrstat_SPEC,
958 crate::common::R,
959 >::from_register(self, 0)
960 }
961
962 #[doc = "Slave TrustZone filter Error Status"]
963 #[inline(always)]
964 pub fn sterrstat(
965 self,
966 ) -> crate::common::RegisterField<
967 1,
968 0x1,
969 1,
970 0,
971 buserrstat::Sterrstat,
972 buserrstat::Sterrstat,
973 Buserrstat_SPEC,
974 crate::common::R,
975 > {
976 crate::common::RegisterField::<
977 1,
978 0x1,
979 1,
980 0,
981 buserrstat::Sterrstat,
982 buserrstat::Sterrstat,
983 Buserrstat_SPEC,
984 crate::common::R,
985 >::from_register(self, 0)
986 }
987
988 #[doc = "Master MPU Error Status"]
989 #[inline(always)]
990 pub fn mmerrstat(
991 self,
992 ) -> crate::common::RegisterField<
993 3,
994 0x1,
995 1,
996 0,
997 buserrstat::Mmerrstat,
998 buserrstat::Mmerrstat,
999 Buserrstat_SPEC,
1000 crate::common::R,
1001 > {
1002 crate::common::RegisterField::<
1003 3,
1004 0x1,
1005 1,
1006 0,
1007 buserrstat::Mmerrstat,
1008 buserrstat::Mmerrstat,
1009 Buserrstat_SPEC,
1010 crate::common::R,
1011 >::from_register(self, 0)
1012 }
1013
1014 #[doc = "Illegal address access Error Status"]
1015 #[inline(always)]
1016 pub fn ilerrstat(
1017 self,
1018 ) -> crate::common::RegisterField<
1019 4,
1020 0x1,
1021 1,
1022 0,
1023 buserrstat::Ilerrstat,
1024 buserrstat::Ilerrstat,
1025 Buserrstat_SPEC,
1026 crate::common::R,
1027 > {
1028 crate::common::RegisterField::<
1029 4,
1030 0x1,
1031 1,
1032 0,
1033 buserrstat::Ilerrstat,
1034 buserrstat::Ilerrstat,
1035 Buserrstat_SPEC,
1036 crate::common::R,
1037 >::from_register(self, 0)
1038 }
1039}
1040impl ::core::default::Default for Buserrstat {
1041 #[inline(always)]
1042 fn default() -> Buserrstat {
1043 <crate::RegValueT<Buserrstat_SPEC> as RegisterValue<_>>::new(0)
1044 }
1045}
1046pub mod buserrstat {
1047
1048 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1049 pub struct Slerrstat_SPEC;
1050 pub type Slerrstat = crate::EnumBitfieldStruct<u8, Slerrstat_SPEC>;
1051 impl Slerrstat {
1052 #[doc = "No error occurred"]
1053 pub const _0: Self = Self::new(0);
1054
1055 #[doc = "Error occurred"]
1056 pub const _1: Self = Self::new(1);
1057 }
1058 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1059 pub struct Sterrstat_SPEC;
1060 pub type Sterrstat = crate::EnumBitfieldStruct<u8, Sterrstat_SPEC>;
1061 impl Sterrstat {
1062 #[doc = "No error occurred"]
1063 pub const _0: Self = Self::new(0);
1064
1065 #[doc = "Error occurred"]
1066 pub const _1: Self = Self::new(1);
1067 }
1068 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1069 pub struct Mmerrstat_SPEC;
1070 pub type Mmerrstat = crate::EnumBitfieldStruct<u8, Mmerrstat_SPEC>;
1071 impl Mmerrstat {
1072 #[doc = "No error occurred"]
1073 pub const _0: Self = Self::new(0);
1074
1075 #[doc = "Error occurred"]
1076 pub const _1: Self = Self::new(1);
1077 }
1078 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1079 pub struct Ilerrstat_SPEC;
1080 pub type Ilerrstat = crate::EnumBitfieldStruct<u8, Ilerrstat_SPEC>;
1081 impl Ilerrstat {
1082 #[doc = "No error occurred"]
1083 pub const _0: Self = Self::new(0);
1084
1085 #[doc = "Error occurred"]
1086 pub const _1: Self = Self::new(1);
1087 }
1088}
1089#[doc(hidden)]
1090#[derive(Copy, Clone, Eq, PartialEq)]
1091pub struct Buserrclr_SPEC;
1092impl crate::sealed::RegSpec for Buserrclr_SPEC {
1093 type DataType = u8;
1094}
1095
1096#[doc = "BUS Error Clear Register %s"]
1097pub type Buserrclr = crate::RegValueT<Buserrclr_SPEC>;
1098
1099impl Buserrclr {
1100 #[doc = "Slave bus Error Clear"]
1101 #[inline(always)]
1102 pub fn slerrclr(
1103 self,
1104 ) -> crate::common::RegisterFieldBool<0, 1, 0, Buserrclr_SPEC, crate::common::RW> {
1105 crate::common::RegisterFieldBool::<0,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
1106 }
1107
1108 #[doc = "Slave TrustZone filter Error Clear"]
1109 #[inline(always)]
1110 pub fn sterrclr(
1111 self,
1112 ) -> crate::common::RegisterFieldBool<1, 1, 0, Buserrclr_SPEC, crate::common::RW> {
1113 crate::common::RegisterFieldBool::<1,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
1114 }
1115
1116 #[doc = "Master MPU Error Clear"]
1117 #[inline(always)]
1118 pub fn mmerrclr(
1119 self,
1120 ) -> crate::common::RegisterFieldBool<3, 1, 0, Buserrclr_SPEC, crate::common::RW> {
1121 crate::common::RegisterFieldBool::<3,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
1122 }
1123
1124 #[doc = "Illegal Address Access Error Clear"]
1125 #[inline(always)]
1126 pub fn ilerrclr(
1127 self,
1128 ) -> crate::common::RegisterFieldBool<4, 1, 0, Buserrclr_SPEC, crate::common::RW> {
1129 crate::common::RegisterFieldBool::<4,1,0,Buserrclr_SPEC,crate::common::RW>::from_register(self,0)
1130 }
1131}
1132impl ::core::default::Default for Buserrclr {
1133 #[inline(always)]
1134 fn default() -> Buserrclr {
1135 <crate::RegValueT<Buserrclr_SPEC> as RegisterValue<_>>::new(0)
1136 }
1137}
1138
1139#[doc(hidden)]
1140#[derive(Copy, Clone, Eq, PartialEq)]
1141pub struct Dmacdtcerrstat_SPEC;
1142impl crate::sealed::RegSpec for Dmacdtcerrstat_SPEC {
1143 type DataType = u8;
1144}
1145
1146#[doc = "DMAC/DTC Error Status Register"]
1147pub type Dmacdtcerrstat = crate::RegValueT<Dmacdtcerrstat_SPEC>;
1148
1149impl Dmacdtcerrstat {
1150 #[doc = "Master TrustZone Filter Error Status"]
1151 #[inline(always)]
1152 pub fn mterrstat(
1153 self,
1154 ) -> crate::common::RegisterField<
1155 0,
1156 0x1,
1157 1,
1158 0,
1159 dmacdtcerrstat::Mterrstat,
1160 dmacdtcerrstat::Mterrstat,
1161 Dmacdtcerrstat_SPEC,
1162 crate::common::R,
1163 > {
1164 crate::common::RegisterField::<
1165 0,
1166 0x1,
1167 1,
1168 0,
1169 dmacdtcerrstat::Mterrstat,
1170 dmacdtcerrstat::Mterrstat,
1171 Dmacdtcerrstat_SPEC,
1172 crate::common::R,
1173 >::from_register(self, 0)
1174 }
1175}
1176impl ::core::default::Default for Dmacdtcerrstat {
1177 #[inline(always)]
1178 fn default() -> Dmacdtcerrstat {
1179 <crate::RegValueT<Dmacdtcerrstat_SPEC> as RegisterValue<_>>::new(0)
1180 }
1181}
1182pub mod dmacdtcerrstat {
1183
1184 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1185 pub struct Mterrstat_SPEC;
1186 pub type Mterrstat = crate::EnumBitfieldStruct<u8, Mterrstat_SPEC>;
1187 impl Mterrstat {
1188 #[doc = "No error occurred"]
1189 pub const _0: Self = Self::new(0);
1190
1191 #[doc = "Error occurred"]
1192 pub const _1: Self = Self::new(1);
1193 }
1194}
1195#[doc(hidden)]
1196#[derive(Copy, Clone, Eq, PartialEq)]
1197pub struct Dmacdtcerrclr_SPEC;
1198impl crate::sealed::RegSpec for Dmacdtcerrclr_SPEC {
1199 type DataType = u8;
1200}
1201
1202#[doc = "DMAC/DTC Error Clear Register"]
1203pub type Dmacdtcerrclr = crate::RegValueT<Dmacdtcerrclr_SPEC>;
1204
1205impl Dmacdtcerrclr {
1206 #[doc = "Master TrustZone filter Error Clear"]
1207 #[inline(always)]
1208 pub fn mterrclr(
1209 self,
1210 ) -> crate::common::RegisterFieldBool<0, 1, 0, Dmacdtcerrclr_SPEC, crate::common::RW> {
1211 crate::common::RegisterFieldBool::<0,1,0,Dmacdtcerrclr_SPEC,crate::common::RW>::from_register(self,0)
1212 }
1213}
1214impl ::core::default::Default for Dmacdtcerrclr {
1215 #[inline(always)]
1216 fn default() -> Dmacdtcerrclr {
1217 <crate::RegValueT<Dmacdtcerrclr_SPEC> as RegisterValue<_>>::new(0)
1218 }
1219}