1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"System Control"]
28unsafe impl ::core::marker::Send for super::Sysc {}
29unsafe impl ::core::marker::Sync for super::Sysc {}
30impl super::Sysc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Standby Control Register"]
38 #[inline(always)]
39 pub const fn sbycr(&self) -> &'static crate::common::Reg<self::Sbycr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Sbycr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(12usize),
43 )
44 }
45 }
46
47 #[doc = "System Clock Division Control Register"]
48 #[inline(always)]
49 pub const fn sckdivcr(
50 &self,
51 ) -> &'static crate::common::Reg<self::Sckdivcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Sckdivcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(32usize),
55 )
56 }
57 }
58
59 #[doc = "System Clock Source Control Register"]
60 #[inline(always)]
61 pub const fn sckscr(
62 &self,
63 ) -> &'static crate::common::Reg<self::Sckscr_SPEC, crate::common::RW> {
64 unsafe {
65 crate::common::Reg::<self::Sckscr_SPEC, crate::common::RW>::from_ptr(
66 self._svd2pac_as_ptr().add(38usize),
67 )
68 }
69 }
70
71 #[doc = "PLL Clock Control Register"]
72 #[inline(always)]
73 pub const fn pllccr(
74 &self,
75 ) -> &'static crate::common::Reg<self::Pllccr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Pllccr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(40usize),
79 )
80 }
81 }
82
83 #[doc = "PLL Control Register"]
84 #[inline(always)]
85 pub const fn pllcr(&self) -> &'static crate::common::Reg<self::Pllcr_SPEC, crate::common::RW> {
86 unsafe {
87 crate::common::Reg::<self::Pllcr_SPEC, crate::common::RW>::from_ptr(
88 self._svd2pac_as_ptr().add(42usize),
89 )
90 }
91 }
92
93 #[doc = "Main Clock Oscillator Control Register"]
94 #[inline(always)]
95 pub const fn mosccr(
96 &self,
97 ) -> &'static crate::common::Reg<self::Mosccr_SPEC, crate::common::RW> {
98 unsafe {
99 crate::common::Reg::<self::Mosccr_SPEC, crate::common::RW>::from_ptr(
100 self._svd2pac_as_ptr().add(50usize),
101 )
102 }
103 }
104
105 #[doc = "High-Speed On-Chip Oscillator Control Register"]
106 #[inline(always)]
107 pub const fn hococr(
108 &self,
109 ) -> &'static crate::common::Reg<self::Hococr_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::Hococr_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(54usize),
113 )
114 }
115 }
116
117 #[doc = "High-Speed On-Chip Oscillator Control Register 2"]
118 #[inline(always)]
119 pub const fn hococr2(
120 &self,
121 ) -> &'static crate::common::Reg<self::Hococr2_SPEC, crate::common::RW> {
122 unsafe {
123 crate::common::Reg::<self::Hococr2_SPEC, crate::common::RW>::from_ptr(
124 self._svd2pac_as_ptr().add(55usize),
125 )
126 }
127 }
128
129 #[doc = "Middle-Speed On-Chip Oscillator Control Register"]
130 #[inline(always)]
131 pub const fn mococr(
132 &self,
133 ) -> &'static crate::common::Reg<self::Mococr_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::Mococr_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(56usize),
137 )
138 }
139 }
140
141 #[doc = "FLL Control Register1"]
142 #[inline(always)]
143 pub const fn fllcr1(
144 &self,
145 ) -> &'static crate::common::Reg<self::Fllcr1_SPEC, crate::common::RW> {
146 unsafe {
147 crate::common::Reg::<self::Fllcr1_SPEC, crate::common::RW>::from_ptr(
148 self._svd2pac_as_ptr().add(57usize),
149 )
150 }
151 }
152
153 #[doc = "FLL Control Register2"]
154 #[inline(always)]
155 pub const fn fllcr2(
156 &self,
157 ) -> &'static crate::common::Reg<self::Fllcr2_SPEC, crate::common::RW> {
158 unsafe {
159 crate::common::Reg::<self::Fllcr2_SPEC, crate::common::RW>::from_ptr(
160 self._svd2pac_as_ptr().add(58usize),
161 )
162 }
163 }
164
165 #[doc = "Oscillation Stabilization Flag Register"]
166 #[inline(always)]
167 pub const fn oscsf(&self) -> &'static crate::common::Reg<self::Oscsf_SPEC, crate::common::R> {
168 unsafe {
169 crate::common::Reg::<self::Oscsf_SPEC, crate::common::R>::from_ptr(
170 self._svd2pac_as_ptr().add(60usize),
171 )
172 }
173 }
174
175 #[doc = "Clock Out Control Register"]
176 #[inline(always)]
177 pub const fn ckocr(&self) -> &'static crate::common::Reg<self::Ckocr_SPEC, crate::common::RW> {
178 unsafe {
179 crate::common::Reg::<self::Ckocr_SPEC, crate::common::RW>::from_ptr(
180 self._svd2pac_as_ptr().add(62usize),
181 )
182 }
183 }
184
185 #[doc = "Oscillation Stop Detection Control Register"]
186 #[inline(always)]
187 pub const fn ostdcr(
188 &self,
189 ) -> &'static crate::common::Reg<self::Ostdcr_SPEC, crate::common::RW> {
190 unsafe {
191 crate::common::Reg::<self::Ostdcr_SPEC, crate::common::RW>::from_ptr(
192 self._svd2pac_as_ptr().add(64usize),
193 )
194 }
195 }
196
197 #[doc = "Oscillation Stop Detection Status Register"]
198 #[inline(always)]
199 pub const fn ostdsr(
200 &self,
201 ) -> &'static crate::common::Reg<self::Ostdsr_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Ostdsr_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(65usize),
205 )
206 }
207 }
208
209 #[doc = "MOCO User Trimming Control Register"]
210 #[inline(always)]
211 pub const fn mocoutcr(
212 &self,
213 ) -> &'static crate::common::Reg<self::Mocoutcr_SPEC, crate::common::RW> {
214 unsafe {
215 crate::common::Reg::<self::Mocoutcr_SPEC, crate::common::RW>::from_ptr(
216 self._svd2pac_as_ptr().add(97usize),
217 )
218 }
219 }
220
221 #[doc = "HOCO User Trimming Control Register"]
222 #[inline(always)]
223 pub const fn hocoutcr(
224 &self,
225 ) -> &'static crate::common::Reg<self::Hocoutcr_SPEC, crate::common::RW> {
226 unsafe {
227 crate::common::Reg::<self::Hocoutcr_SPEC, crate::common::RW>::from_ptr(
228 self._svd2pac_as_ptr().add(98usize),
229 )
230 }
231 }
232
233 #[doc = "USB Clock Division Control Register"]
234 #[inline(always)]
235 pub const fn usbckdivcr(
236 &self,
237 ) -> &'static crate::common::Reg<self::Usbckdivcr_SPEC, crate::common::RW> {
238 unsafe {
239 crate::common::Reg::<self::Usbckdivcr_SPEC, crate::common::RW>::from_ptr(
240 self._svd2pac_as_ptr().add(108usize),
241 )
242 }
243 }
244
245 #[doc = "CANFD Clock Division Control Register"]
246 #[inline(always)]
247 pub const fn canfdckdivcr(
248 &self,
249 ) -> &'static crate::common::Reg<self::Canfdckdivcr_SPEC, crate::common::RW> {
250 unsafe {
251 crate::common::Reg::<self::Canfdckdivcr_SPEC, crate::common::RW>::from_ptr(
252 self._svd2pac_as_ptr().add(110usize),
253 )
254 }
255 }
256
257 #[doc = "CEC Clock Division Control Register"]
258 #[inline(always)]
259 pub const fn cecckdivcr(
260 &self,
261 ) -> &'static crate::common::Reg<self::Cecckdivcr_SPEC, crate::common::RW> {
262 unsafe {
263 crate::common::Reg::<self::Cecckdivcr_SPEC, crate::common::RW>::from_ptr(
264 self._svd2pac_as_ptr().add(112usize),
265 )
266 }
267 }
268
269 #[doc = "I3C Clock Division Control Register"]
270 #[inline(always)]
271 pub const fn i3cckdivcr(
272 &self,
273 ) -> &'static crate::common::Reg<self::I3Cckdivcr_SPEC, crate::common::RW> {
274 unsafe {
275 crate::common::Reg::<self::I3Cckdivcr_SPEC, crate::common::RW>::from_ptr(
276 self._svd2pac_as_ptr().add(113usize),
277 )
278 }
279 }
280
281 #[doc = "USB Clock Control Register"]
282 #[inline(always)]
283 pub const fn usbckcr(
284 &self,
285 ) -> &'static crate::common::Reg<self::Usbckcr_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::Usbckcr_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(116usize),
289 )
290 }
291 }
292
293 #[doc = "CANFD Clock Control Register"]
294 #[inline(always)]
295 pub const fn canfdckcr(
296 &self,
297 ) -> &'static crate::common::Reg<self::Canfdckcr_SPEC, crate::common::RW> {
298 unsafe {
299 crate::common::Reg::<self::Canfdckcr_SPEC, crate::common::RW>::from_ptr(
300 self._svd2pac_as_ptr().add(118usize),
301 )
302 }
303 }
304
305 #[doc = "CEC Clock Control Register"]
306 #[inline(always)]
307 pub const fn cecckcr(
308 &self,
309 ) -> &'static crate::common::Reg<self::Cecckcr_SPEC, crate::common::RW> {
310 unsafe {
311 crate::common::Reg::<self::Cecckcr_SPEC, crate::common::RW>::from_ptr(
312 self._svd2pac_as_ptr().add(120usize),
313 )
314 }
315 }
316
317 #[doc = "I3C Clock Control Register"]
318 #[inline(always)]
319 pub const fn i3cckcr(
320 &self,
321 ) -> &'static crate::common::Reg<self::I3Cckcr_SPEC, crate::common::RW> {
322 unsafe {
323 crate::common::Reg::<self::I3Cckcr_SPEC, crate::common::RW>::from_ptr(
324 self._svd2pac_as_ptr().add(121usize),
325 )
326 }
327 }
328
329 #[doc = "Snooze Control Register"]
330 #[inline(always)]
331 pub const fn snzcr(&self) -> &'static crate::common::Reg<self::Snzcr_SPEC, crate::common::RW> {
332 unsafe {
333 crate::common::Reg::<self::Snzcr_SPEC, crate::common::RW>::from_ptr(
334 self._svd2pac_as_ptr().add(146usize),
335 )
336 }
337 }
338
339 #[doc = "Snooze End Control Register 0"]
340 #[inline(always)]
341 pub const fn snzedcr0(
342 &self,
343 ) -> &'static crate::common::Reg<self::Snzedcr0_SPEC, crate::common::RW> {
344 unsafe {
345 crate::common::Reg::<self::Snzedcr0_SPEC, crate::common::RW>::from_ptr(
346 self._svd2pac_as_ptr().add(148usize),
347 )
348 }
349 }
350
351 #[doc = "Snooze Request Control Register 0"]
352 #[inline(always)]
353 pub const fn snzreqcr0(
354 &self,
355 ) -> &'static crate::common::Reg<self::Snzreqcr0_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Snzreqcr0_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(152usize),
359 )
360 }
361 }
362
363 #[doc = "Operating Power Control Register"]
364 #[inline(always)]
365 pub const fn opccr(&self) -> &'static crate::common::Reg<self::Opccr_SPEC, crate::common::RW> {
366 unsafe {
367 crate::common::Reg::<self::Opccr_SPEC, crate::common::RW>::from_ptr(
368 self._svd2pac_as_ptr().add(160usize),
369 )
370 }
371 }
372
373 #[doc = "Main Clock Oscillator Wait Control Register"]
374 #[inline(always)]
375 pub const fn moscwtcr(
376 &self,
377 ) -> &'static crate::common::Reg<self::Moscwtcr_SPEC, crate::common::RW> {
378 unsafe {
379 crate::common::Reg::<self::Moscwtcr_SPEC, crate::common::RW>::from_ptr(
380 self._svd2pac_as_ptr().add(162usize),
381 )
382 }
383 }
384
385 #[doc = "Sub Operating Power Control Register"]
386 #[inline(always)]
387 pub const fn sopccr(
388 &self,
389 ) -> &'static crate::common::Reg<self::Sopccr_SPEC, crate::common::RW> {
390 unsafe {
391 crate::common::Reg::<self::Sopccr_SPEC, crate::common::RW>::from_ptr(
392 self._svd2pac_as_ptr().add(170usize),
393 )
394 }
395 }
396
397 #[doc = "Reset Status Register 1"]
398 #[inline(always)]
399 pub const fn rstsr1(
400 &self,
401 ) -> &'static crate::common::Reg<self::Rstsr1_SPEC, crate::common::RW> {
402 unsafe {
403 crate::common::Reg::<self::Rstsr1_SPEC, crate::common::RW>::from_ptr(
404 self._svd2pac_as_ptr().add(192usize),
405 )
406 }
407 }
408
409 #[doc = "Voltage Monitor 1 Circuit Control Register"]
410 #[inline(always)]
411 pub const fn lvd1cr1(
412 &self,
413 ) -> &'static crate::common::Reg<self::Lvd1Cr1_SPEC, crate::common::RW> {
414 unsafe {
415 crate::common::Reg::<self::Lvd1Cr1_SPEC, crate::common::RW>::from_ptr(
416 self._svd2pac_as_ptr().add(224usize),
417 )
418 }
419 }
420
421 #[doc = "Voltage Monitor 1 Circuit Status Register"]
422 #[inline(always)]
423 pub const fn lvd1sr(
424 &self,
425 ) -> &'static crate::common::Reg<self::Lvd1Sr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Lvd1Sr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(225usize),
429 )
430 }
431 }
432
433 #[doc = "Voltage Monitor 2 Circuit Control Register 1"]
434 #[inline(always)]
435 pub const fn lvd2cr1(
436 &self,
437 ) -> &'static crate::common::Reg<self::Lvd2Cr1_SPEC, crate::common::RW> {
438 unsafe {
439 crate::common::Reg::<self::Lvd2Cr1_SPEC, crate::common::RW>::from_ptr(
440 self._svd2pac_as_ptr().add(226usize),
441 )
442 }
443 }
444
445 #[doc = "Voltage Monitor 2 Circuit Status Register"]
446 #[inline(always)]
447 pub const fn lvd2sr(
448 &self,
449 ) -> &'static crate::common::Reg<self::Lvd2Sr_SPEC, crate::common::RW> {
450 unsafe {
451 crate::common::Reg::<self::Lvd2Sr_SPEC, crate::common::RW>::from_ptr(
452 self._svd2pac_as_ptr().add(227usize),
453 )
454 }
455 }
456
457 #[doc = "Clock Generation Function Security Attribute Register"]
458 #[inline(always)]
459 pub const fn cgfsar(
460 &self,
461 ) -> &'static crate::common::Reg<self::Cgfsar_SPEC, crate::common::RW> {
462 unsafe {
463 crate::common::Reg::<self::Cgfsar_SPEC, crate::common::RW>::from_ptr(
464 self._svd2pac_as_ptr().add(960usize),
465 )
466 }
467 }
468
469 #[doc = "Reset Security Attribution Register"]
470 #[inline(always)]
471 pub const fn rstsar(
472 &self,
473 ) -> &'static crate::common::Reg<self::Rstsar_SPEC, crate::common::RW> {
474 unsafe {
475 crate::common::Reg::<self::Rstsar_SPEC, crate::common::RW>::from_ptr(
476 self._svd2pac_as_ptr().add(964usize),
477 )
478 }
479 }
480
481 #[doc = "Low Power Mode Security Attribution Register"]
482 #[inline(always)]
483 pub const fn lpmsar(
484 &self,
485 ) -> &'static crate::common::Reg<self::Lpmsar_SPEC, crate::common::RW> {
486 unsafe {
487 crate::common::Reg::<self::Lpmsar_SPEC, crate::common::RW>::from_ptr(
488 self._svd2pac_as_ptr().add(968usize),
489 )
490 }
491 }
492
493 #[doc = "Low Voltage Detection Security Attribution Register"]
494 #[inline(always)]
495 pub const fn lvdsar(
496 &self,
497 ) -> &'static crate::common::Reg<self::Lvdsar_SPEC, crate::common::RW> {
498 unsafe {
499 crate::common::Reg::<self::Lvdsar_SPEC, crate::common::RW>::from_ptr(
500 self._svd2pac_as_ptr().add(972usize),
501 )
502 }
503 }
504
505 #[doc = "Deep Standby Interrupt Factor Security Attribution Register"]
506 #[inline(always)]
507 pub const fn dpfsar(
508 &self,
509 ) -> &'static crate::common::Reg<self::Dpfsar_SPEC, crate::common::RW> {
510 unsafe {
511 crate::common::Reg::<self::Dpfsar_SPEC, crate::common::RW>::from_ptr(
512 self._svd2pac_as_ptr().add(992usize),
513 )
514 }
515 }
516
517 #[doc = "Protect Register"]
518 #[inline(always)]
519 pub const fn prcr(&self) -> &'static crate::common::Reg<self::Prcr_SPEC, crate::common::RW> {
520 unsafe {
521 crate::common::Reg::<self::Prcr_SPEC, crate::common::RW>::from_ptr(
522 self._svd2pac_as_ptr().add(1022usize),
523 )
524 }
525 }
526
527 #[doc = "Deep Standby Control Register"]
528 #[inline(always)]
529 pub const fn dpsbycr(
530 &self,
531 ) -> &'static crate::common::Reg<self::Dpsbycr_SPEC, crate::common::RW> {
532 unsafe {
533 crate::common::Reg::<self::Dpsbycr_SPEC, crate::common::RW>::from_ptr(
534 self._svd2pac_as_ptr().add(1024usize),
535 )
536 }
537 }
538
539 #[doc = "Deep Standby Wait Control Register"]
540 #[inline(always)]
541 pub const fn dpswcr(
542 &self,
543 ) -> &'static crate::common::Reg<self::Dpswcr_SPEC, crate::common::RW> {
544 unsafe {
545 crate::common::Reg::<self::Dpswcr_SPEC, crate::common::RW>::from_ptr(
546 self._svd2pac_as_ptr().add(1025usize),
547 )
548 }
549 }
550
551 #[doc = "Deep Standby Interrupt Enable Register 0"]
552 #[inline(always)]
553 pub const fn dpsier0(
554 &self,
555 ) -> &'static crate::common::Reg<self::Dpsier0_SPEC, crate::common::RW> {
556 unsafe {
557 crate::common::Reg::<self::Dpsier0_SPEC, crate::common::RW>::from_ptr(
558 self._svd2pac_as_ptr().add(1026usize),
559 )
560 }
561 }
562
563 #[doc = "Deep Standby Interrupt Enable Register 1"]
564 #[inline(always)]
565 pub const fn dpsier1(
566 &self,
567 ) -> &'static crate::common::Reg<self::Dpsier1_SPEC, crate::common::RW> {
568 unsafe {
569 crate::common::Reg::<self::Dpsier1_SPEC, crate::common::RW>::from_ptr(
570 self._svd2pac_as_ptr().add(1027usize),
571 )
572 }
573 }
574
575 #[doc = "Deep Software Standby Interrupt Enable Register 2"]
576 #[inline(always)]
577 pub const fn dpsier2(
578 &self,
579 ) -> &'static crate::common::Reg<self::Dpsier2_SPEC, crate::common::RW> {
580 unsafe {
581 crate::common::Reg::<self::Dpsier2_SPEC, crate::common::RW>::from_ptr(
582 self._svd2pac_as_ptr().add(1028usize),
583 )
584 }
585 }
586
587 #[doc = "Deep Standby Interrupt Enable Register 3"]
588 #[inline(always)]
589 pub const fn dpsier3(
590 &self,
591 ) -> &'static crate::common::Reg<self::Dpsier3_SPEC, crate::common::RW> {
592 unsafe {
593 crate::common::Reg::<self::Dpsier3_SPEC, crate::common::RW>::from_ptr(
594 self._svd2pac_as_ptr().add(1029usize),
595 )
596 }
597 }
598
599 #[doc = "Deep Standby Interrupt Flag Register 0"]
600 #[inline(always)]
601 pub const fn dpsifr0(
602 &self,
603 ) -> &'static crate::common::Reg<self::Dpsifr0_SPEC, crate::common::RW> {
604 unsafe {
605 crate::common::Reg::<self::Dpsifr0_SPEC, crate::common::RW>::from_ptr(
606 self._svd2pac_as_ptr().add(1030usize),
607 )
608 }
609 }
610
611 #[doc = "Deep Standby Interrupt Flag Register 1"]
612 #[inline(always)]
613 pub const fn dpsifr1(
614 &self,
615 ) -> &'static crate::common::Reg<self::Dpsifr1_SPEC, crate::common::RW> {
616 unsafe {
617 crate::common::Reg::<self::Dpsifr1_SPEC, crate::common::RW>::from_ptr(
618 self._svd2pac_as_ptr().add(1031usize),
619 )
620 }
621 }
622
623 #[doc = "Deep Software Standby Interrupt Flag Register 2"]
624 #[inline(always)]
625 pub const fn dpsifr2(
626 &self,
627 ) -> &'static crate::common::Reg<self::Dpsifr2_SPEC, crate::common::RW> {
628 unsafe {
629 crate::common::Reg::<self::Dpsifr2_SPEC, crate::common::RW>::from_ptr(
630 self._svd2pac_as_ptr().add(1032usize),
631 )
632 }
633 }
634
635 #[doc = "Deep Standby Interrupt Flag Register 3"]
636 #[inline(always)]
637 pub const fn dpsifr3(
638 &self,
639 ) -> &'static crate::common::Reg<self::Dpsifr3_SPEC, crate::common::RW> {
640 unsafe {
641 crate::common::Reg::<self::Dpsifr3_SPEC, crate::common::RW>::from_ptr(
642 self._svd2pac_as_ptr().add(1033usize),
643 )
644 }
645 }
646
647 #[doc = "Deep Standby Interrupt Edge Register 0"]
648 #[inline(always)]
649 pub const fn dpsiegr0(
650 &self,
651 ) -> &'static crate::common::Reg<self::Dpsiegr0_SPEC, crate::common::RW> {
652 unsafe {
653 crate::common::Reg::<self::Dpsiegr0_SPEC, crate::common::RW>::from_ptr(
654 self._svd2pac_as_ptr().add(1034usize),
655 )
656 }
657 }
658
659 #[doc = "Deep Standby Interrupt Edge Register 1"]
660 #[inline(always)]
661 pub const fn dpsiegr1(
662 &self,
663 ) -> &'static crate::common::Reg<self::Dpsiegr1_SPEC, crate::common::RW> {
664 unsafe {
665 crate::common::Reg::<self::Dpsiegr1_SPEC, crate::common::RW>::from_ptr(
666 self._svd2pac_as_ptr().add(1035usize),
667 )
668 }
669 }
670
671 #[doc = "Deep Software Standby Interrupt Edge Register 2"]
672 #[inline(always)]
673 pub const fn dpsiegr2(
674 &self,
675 ) -> &'static crate::common::Reg<self::Dpsiegr2_SPEC, crate::common::RW> {
676 unsafe {
677 crate::common::Reg::<self::Dpsiegr2_SPEC, crate::common::RW>::from_ptr(
678 self._svd2pac_as_ptr().add(1036usize),
679 )
680 }
681 }
682
683 #[doc = "System Control OCD Control Register"]
684 #[inline(always)]
685 pub const fn syocdcr(
686 &self,
687 ) -> &'static crate::common::Reg<self::Syocdcr_SPEC, crate::common::RW> {
688 unsafe {
689 crate::common::Reg::<self::Syocdcr_SPEC, crate::common::RW>::from_ptr(
690 self._svd2pac_as_ptr().add(1038usize),
691 )
692 }
693 }
694
695 #[doc = "Reset Status Register 0"]
696 #[inline(always)]
697 pub const fn rstsr0(
698 &self,
699 ) -> &'static crate::common::Reg<self::Rstsr0_SPEC, crate::common::RW> {
700 unsafe {
701 crate::common::Reg::<self::Rstsr0_SPEC, crate::common::RW>::from_ptr(
702 self._svd2pac_as_ptr().add(1040usize),
703 )
704 }
705 }
706
707 #[doc = "Reset Status Register 2"]
708 #[inline(always)]
709 pub const fn rstsr2(
710 &self,
711 ) -> &'static crate::common::Reg<self::Rstsr2_SPEC, crate::common::RW> {
712 unsafe {
713 crate::common::Reg::<self::Rstsr2_SPEC, crate::common::RW>::from_ptr(
714 self._svd2pac_as_ptr().add(1041usize),
715 )
716 }
717 }
718
719 #[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
720 #[inline(always)]
721 pub const fn momcr(&self) -> &'static crate::common::Reg<self::Momcr_SPEC, crate::common::RW> {
722 unsafe {
723 crate::common::Reg::<self::Momcr_SPEC, crate::common::RW>::from_ptr(
724 self._svd2pac_as_ptr().add(1043usize),
725 )
726 }
727 }
728
729 #[doc = "Flash P/E Protect Register"]
730 #[inline(always)]
731 pub const fn fwepror(
732 &self,
733 ) -> &'static crate::common::Reg<self::Fwepror_SPEC, crate::common::RW> {
734 unsafe {
735 crate::common::Reg::<self::Fwepror_SPEC, crate::common::RW>::from_ptr(
736 self._svd2pac_as_ptr().add(1046usize),
737 )
738 }
739 }
740
741 #[doc = "Voltage Monitoring 1 Comparator Control Register"]
742 #[inline(always)]
743 pub const fn lvd1cmpcr(
744 &self,
745 ) -> &'static crate::common::Reg<self::Lvd1Cmpcr_SPEC, crate::common::RW> {
746 unsafe {
747 crate::common::Reg::<self::Lvd1Cmpcr_SPEC, crate::common::RW>::from_ptr(
748 self._svd2pac_as_ptr().add(1047usize),
749 )
750 }
751 }
752
753 #[doc = "Voltage Monitoring 2 Comparator Control Register"]
754 #[inline(always)]
755 pub const fn lvd2cmpcr(
756 &self,
757 ) -> &'static crate::common::Reg<self::Lvd2Cmpcr_SPEC, crate::common::RW> {
758 unsafe {
759 crate::common::Reg::<self::Lvd2Cmpcr_SPEC, crate::common::RW>::from_ptr(
760 self._svd2pac_as_ptr().add(1048usize),
761 )
762 }
763 }
764
765 #[doc = "Voltage Monitor 1 Circuit Control Register 0"]
766 #[inline(always)]
767 pub const fn lvd1cr0(
768 &self,
769 ) -> &'static crate::common::Reg<self::Lvd1Cr0_SPEC, crate::common::RW> {
770 unsafe {
771 crate::common::Reg::<self::Lvd1Cr0_SPEC, crate::common::RW>::from_ptr(
772 self._svd2pac_as_ptr().add(1050usize),
773 )
774 }
775 }
776
777 #[doc = "Voltage Monitor 2 Circuit Control Register 0"]
778 #[inline(always)]
779 pub const fn lvd2cr0(
780 &self,
781 ) -> &'static crate::common::Reg<self::Lvd2Cr0_SPEC, crate::common::RW> {
782 unsafe {
783 crate::common::Reg::<self::Lvd2Cr0_SPEC, crate::common::RW>::from_ptr(
784 self._svd2pac_as_ptr().add(1051usize),
785 )
786 }
787 }
788
789 #[doc = "Sub-Clock Oscillator Control Register"]
790 #[inline(always)]
791 pub const fn sosccr(
792 &self,
793 ) -> &'static crate::common::Reg<self::Sosccr_SPEC, crate::common::RW> {
794 unsafe {
795 crate::common::Reg::<self::Sosccr_SPEC, crate::common::RW>::from_ptr(
796 self._svd2pac_as_ptr().add(1152usize),
797 )
798 }
799 }
800
801 #[doc = "Sub-Clock Oscillator Mode Control Register"]
802 #[inline(always)]
803 pub const fn somcr(&self) -> &'static crate::common::Reg<self::Somcr_SPEC, crate::common::RW> {
804 unsafe {
805 crate::common::Reg::<self::Somcr_SPEC, crate::common::RW>::from_ptr(
806 self._svd2pac_as_ptr().add(1153usize),
807 )
808 }
809 }
810
811 #[doc = "Low-Speed On-Chip Oscillator Control Register"]
812 #[inline(always)]
813 pub const fn lococr(
814 &self,
815 ) -> &'static crate::common::Reg<self::Lococr_SPEC, crate::common::RW> {
816 unsafe {
817 crate::common::Reg::<self::Lococr_SPEC, crate::common::RW>::from_ptr(
818 self._svd2pac_as_ptr().add(1168usize),
819 )
820 }
821 }
822
823 #[doc = "LOCO User Trimming Control Register"]
824 #[inline(always)]
825 pub const fn locoutcr(
826 &self,
827 ) -> &'static crate::common::Reg<self::Locoutcr_SPEC, crate::common::RW> {
828 unsafe {
829 crate::common::Reg::<self::Locoutcr_SPEC, crate::common::RW>::from_ptr(
830 self._svd2pac_as_ptr().add(1170usize),
831 )
832 }
833 }
834}
835#[doc(hidden)]
836#[derive(Copy, Clone, Eq, PartialEq)]
837pub struct Sbycr_SPEC;
838impl crate::sealed::RegSpec for Sbycr_SPEC {
839 type DataType = u16;
840}
841
842#[doc = "Standby Control Register"]
843pub type Sbycr = crate::RegValueT<Sbycr_SPEC>;
844
845impl Sbycr {
846 #[doc = "Software Standby Mode Select"]
847 #[inline(always)]
848 pub fn ssby(
849 self,
850 ) -> crate::common::RegisterField<
851 15,
852 0x1,
853 1,
854 0,
855 sbycr::Ssby,
856 sbycr::Ssby,
857 Sbycr_SPEC,
858 crate::common::RW,
859 > {
860 crate::common::RegisterField::<
861 15,
862 0x1,
863 1,
864 0,
865 sbycr::Ssby,
866 sbycr::Ssby,
867 Sbycr_SPEC,
868 crate::common::RW,
869 >::from_register(self, 0)
870 }
871}
872impl ::core::default::Default for Sbycr {
873 #[inline(always)]
874 fn default() -> Sbycr {
875 <crate::RegValueT<Sbycr_SPEC> as RegisterValue<_>>::new(16384)
876 }
877}
878pub mod sbycr {
879
880 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
881 pub struct Ssby_SPEC;
882 pub type Ssby = crate::EnumBitfieldStruct<u8, Ssby_SPEC>;
883 impl Ssby {
884 #[doc = "Sleep mode"]
885 pub const _0: Self = Self::new(0);
886
887 #[doc = "Software Standby mode."]
888 pub const _1: Self = Self::new(1);
889 }
890}
891#[doc(hidden)]
892#[derive(Copy, Clone, Eq, PartialEq)]
893pub struct Sckdivcr_SPEC;
894impl crate::sealed::RegSpec for Sckdivcr_SPEC {
895 type DataType = u32;
896}
897
898#[doc = "System Clock Division Control Register"]
899pub type Sckdivcr = crate::RegValueT<Sckdivcr_SPEC>;
900
901impl Sckdivcr {
902 #[doc = "Peripheral Module Clock D (PCLKD) Select"]
903 #[inline(always)]
904 pub fn pckd(
905 self,
906 ) -> crate::common::RegisterField<
907 0,
908 0x7,
909 1,
910 0,
911 sckdivcr::Pckd,
912 sckdivcr::Pckd,
913 Sckdivcr_SPEC,
914 crate::common::RW,
915 > {
916 crate::common::RegisterField::<
917 0,
918 0x7,
919 1,
920 0,
921 sckdivcr::Pckd,
922 sckdivcr::Pckd,
923 Sckdivcr_SPEC,
924 crate::common::RW,
925 >::from_register(self, 0)
926 }
927
928 #[doc = "Peripheral Module Clock C (PCLKC) Select"]
929 #[inline(always)]
930 pub fn pckc(
931 self,
932 ) -> crate::common::RegisterField<
933 4,
934 0x7,
935 1,
936 0,
937 sckdivcr::Pckc,
938 sckdivcr::Pckc,
939 Sckdivcr_SPEC,
940 crate::common::RW,
941 > {
942 crate::common::RegisterField::<
943 4,
944 0x7,
945 1,
946 0,
947 sckdivcr::Pckc,
948 sckdivcr::Pckc,
949 Sckdivcr_SPEC,
950 crate::common::RW,
951 >::from_register(self, 0)
952 }
953
954 #[doc = "Peripheral Module Clock B (PCLKB) Select"]
955 #[inline(always)]
956 pub fn pckb(
957 self,
958 ) -> crate::common::RegisterField<
959 8,
960 0x7,
961 1,
962 0,
963 sckdivcr::Pckb,
964 sckdivcr::Pckb,
965 Sckdivcr_SPEC,
966 crate::common::RW,
967 > {
968 crate::common::RegisterField::<
969 8,
970 0x7,
971 1,
972 0,
973 sckdivcr::Pckb,
974 sckdivcr::Pckb,
975 Sckdivcr_SPEC,
976 crate::common::RW,
977 >::from_register(self, 0)
978 }
979
980 #[doc = "Peripheral Module Clock A (PCLKA) Select"]
981 #[inline(always)]
982 pub fn pcka(
983 self,
984 ) -> crate::common::RegisterField<
985 12,
986 0x7,
987 1,
988 0,
989 sckdivcr::Pcka,
990 sckdivcr::Pcka,
991 Sckdivcr_SPEC,
992 crate::common::RW,
993 > {
994 crate::common::RegisterField::<
995 12,
996 0x7,
997 1,
998 0,
999 sckdivcr::Pcka,
1000 sckdivcr::Pcka,
1001 Sckdivcr_SPEC,
1002 crate::common::RW,
1003 >::from_register(self, 0)
1004 }
1005
1006 #[doc = "System Clock (ICLK) Select"]
1007 #[inline(always)]
1008 pub fn ick(
1009 self,
1010 ) -> crate::common::RegisterField<
1011 24,
1012 0x7,
1013 1,
1014 0,
1015 sckdivcr::Ick,
1016 sckdivcr::Ick,
1017 Sckdivcr_SPEC,
1018 crate::common::RW,
1019 > {
1020 crate::common::RegisterField::<
1021 24,
1022 0x7,
1023 1,
1024 0,
1025 sckdivcr::Ick,
1026 sckdivcr::Ick,
1027 Sckdivcr_SPEC,
1028 crate::common::RW,
1029 >::from_register(self, 0)
1030 }
1031
1032 #[doc = "FlashIF Clock (FCLK) Select"]
1033 #[inline(always)]
1034 pub fn fck(
1035 self,
1036 ) -> crate::common::RegisterField<
1037 28,
1038 0x7,
1039 1,
1040 0,
1041 sckdivcr::Fck,
1042 sckdivcr::Fck,
1043 Sckdivcr_SPEC,
1044 crate::common::RW,
1045 > {
1046 crate::common::RegisterField::<
1047 28,
1048 0x7,
1049 1,
1050 0,
1051 sckdivcr::Fck,
1052 sckdivcr::Fck,
1053 Sckdivcr_SPEC,
1054 crate::common::RW,
1055 >::from_register(self, 0)
1056 }
1057}
1058impl ::core::default::Default for Sckdivcr {
1059 #[inline(always)]
1060 fn default() -> Sckdivcr {
1061 <crate::RegValueT<Sckdivcr_SPEC> as RegisterValue<_>>::new(570434082)
1062 }
1063}
1064pub mod sckdivcr {
1065
1066 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1067 pub struct Pckd_SPEC;
1068 pub type Pckd = crate::EnumBitfieldStruct<u8, Pckd_SPEC>;
1069 impl Pckd {
1070 #[doc = "x 1/1"]
1071 pub const _000: Self = Self::new(0);
1072
1073 #[doc = "x 1/2"]
1074 pub const _001: Self = Self::new(1);
1075
1076 #[doc = "x 1/4"]
1077 pub const _010: Self = Self::new(2);
1078
1079 #[doc = "x 1/8"]
1080 pub const _011: Self = Self::new(3);
1081
1082 #[doc = "x 1/16"]
1083 pub const _100: Self = Self::new(4);
1084
1085 #[doc = "x 1/32"]
1086 pub const _101: Self = Self::new(5);
1087
1088 #[doc = "x 1/64"]
1089 pub const _110: Self = Self::new(6);
1090 }
1091 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1092 pub struct Pckc_SPEC;
1093 pub type Pckc = crate::EnumBitfieldStruct<u8, Pckc_SPEC>;
1094 impl Pckc {
1095 #[doc = "x 1/1"]
1096 pub const _000: Self = Self::new(0);
1097
1098 #[doc = "x 1/2"]
1099 pub const _001: Self = Self::new(1);
1100
1101 #[doc = "x 1/4"]
1102 pub const _010: Self = Self::new(2);
1103
1104 #[doc = "x 1/8"]
1105 pub const _011: Self = Self::new(3);
1106
1107 #[doc = "x 1/16"]
1108 pub const _100: Self = Self::new(4);
1109
1110 #[doc = "x 1/32"]
1111 pub const _101: Self = Self::new(5);
1112
1113 #[doc = "x 1/64"]
1114 pub const _110: Self = Self::new(6);
1115 }
1116 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1117 pub struct Pckb_SPEC;
1118 pub type Pckb = crate::EnumBitfieldStruct<u8, Pckb_SPEC>;
1119 impl Pckb {
1120 #[doc = "x 1/1"]
1121 pub const _000: Self = Self::new(0);
1122
1123 #[doc = "x 1/2"]
1124 pub const _001: Self = Self::new(1);
1125
1126 #[doc = "x 1/4"]
1127 pub const _010: Self = Self::new(2);
1128
1129 #[doc = "x 1/8"]
1130 pub const _011: Self = Self::new(3);
1131
1132 #[doc = "x 1/16"]
1133 pub const _100: Self = Self::new(4);
1134
1135 #[doc = "x 1/32"]
1136 pub const _101: Self = Self::new(5);
1137
1138 #[doc = "x 1/64"]
1139 pub const _110: Self = Self::new(6);
1140 }
1141 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1142 pub struct Pcka_SPEC;
1143 pub type Pcka = crate::EnumBitfieldStruct<u8, Pcka_SPEC>;
1144 impl Pcka {
1145 #[doc = "x 1/1"]
1146 pub const _000: Self = Self::new(0);
1147
1148 #[doc = "x 1/2"]
1149 pub const _001: Self = Self::new(1);
1150
1151 #[doc = "x 1/4"]
1152 pub const _010: Self = Self::new(2);
1153
1154 #[doc = "x 1/8"]
1155 pub const _011: Self = Self::new(3);
1156
1157 #[doc = "x 1/16"]
1158 pub const _100: Self = Self::new(4);
1159
1160 #[doc = "x 1/32"]
1161 pub const _101: Self = Self::new(5);
1162
1163 #[doc = "x 1/64"]
1164 pub const _110: Self = Self::new(6);
1165 }
1166 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1167 pub struct Ick_SPEC;
1168 pub type Ick = crate::EnumBitfieldStruct<u8, Ick_SPEC>;
1169 impl Ick {
1170 #[doc = "x 1/1"]
1171 pub const _000: Self = Self::new(0);
1172
1173 #[doc = "x 1/2"]
1174 pub const _001: Self = Self::new(1);
1175
1176 #[doc = "x 1/4"]
1177 pub const _010: Self = Self::new(2);
1178
1179 #[doc = "x 1/8"]
1180 pub const _011: Self = Self::new(3);
1181
1182 #[doc = "x 1/16"]
1183 pub const _100: Self = Self::new(4);
1184
1185 #[doc = "x 1/32"]
1186 pub const _101: Self = Self::new(5);
1187
1188 #[doc = "x 1/64"]
1189 pub const _110: Self = Self::new(6);
1190 }
1191 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1192 pub struct Fck_SPEC;
1193 pub type Fck = crate::EnumBitfieldStruct<u8, Fck_SPEC>;
1194 impl Fck {
1195 #[doc = "x 1/1"]
1196 pub const _000: Self = Self::new(0);
1197
1198 #[doc = "x 1/2"]
1199 pub const _001: Self = Self::new(1);
1200
1201 #[doc = "x 1/4"]
1202 pub const _010: Self = Self::new(2);
1203
1204 #[doc = "x 1/8"]
1205 pub const _011: Self = Self::new(3);
1206
1207 #[doc = "x 1/16"]
1208 pub const _100: Self = Self::new(4);
1209
1210 #[doc = "x 1/32"]
1211 pub const _101: Self = Self::new(5);
1212
1213 #[doc = "x 1/64"]
1214 pub const _110: Self = Self::new(6);
1215 }
1216}
1217#[doc(hidden)]
1218#[derive(Copy, Clone, Eq, PartialEq)]
1219pub struct Sckscr_SPEC;
1220impl crate::sealed::RegSpec for Sckscr_SPEC {
1221 type DataType = u8;
1222}
1223
1224#[doc = "System Clock Source Control Register"]
1225pub type Sckscr = crate::RegValueT<Sckscr_SPEC>;
1226
1227impl Sckscr {
1228 #[doc = "Clock Source Select"]
1229 #[inline(always)]
1230 pub fn cksel(
1231 self,
1232 ) -> crate::common::RegisterField<
1233 0,
1234 0x7,
1235 1,
1236 0,
1237 sckscr::Cksel,
1238 sckscr::Cksel,
1239 Sckscr_SPEC,
1240 crate::common::RW,
1241 > {
1242 crate::common::RegisterField::<
1243 0,
1244 0x7,
1245 1,
1246 0,
1247 sckscr::Cksel,
1248 sckscr::Cksel,
1249 Sckscr_SPEC,
1250 crate::common::RW,
1251 >::from_register(self, 0)
1252 }
1253}
1254impl ::core::default::Default for Sckscr {
1255 #[inline(always)]
1256 fn default() -> Sckscr {
1257 <crate::RegValueT<Sckscr_SPEC> as RegisterValue<_>>::new(1)
1258 }
1259}
1260pub mod sckscr {
1261
1262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1263 pub struct Cksel_SPEC;
1264 pub type Cksel = crate::EnumBitfieldStruct<u8, Cksel_SPEC>;
1265 impl Cksel {
1266 #[doc = "HOCO"]
1267 pub const _000: Self = Self::new(0);
1268
1269 #[doc = "MOCO"]
1270 pub const _001: Self = Self::new(1);
1271
1272 #[doc = "LOCO"]
1273 pub const _010: Self = Self::new(2);
1274
1275 #[doc = "Main clock oscillator (MOSC)"]
1276 pub const _011: Self = Self::new(3);
1277
1278 #[doc = "Sub-clock oscillator (SOSC)"]
1279 pub const _100: Self = Self::new(4);
1280
1281 #[doc = "PLL"]
1282 pub const _101: Self = Self::new(5);
1283
1284 #[doc = "Setting prohibited"]
1285 pub const _110: Self = Self::new(6);
1286
1287 #[doc = "Setting prohibited"]
1288 pub const _111: Self = Self::new(7);
1289 }
1290}
1291#[doc(hidden)]
1292#[derive(Copy, Clone, Eq, PartialEq)]
1293pub struct Pllccr_SPEC;
1294impl crate::sealed::RegSpec for Pllccr_SPEC {
1295 type DataType = u16;
1296}
1297
1298#[doc = "PLL Clock Control Register"]
1299pub type Pllccr = crate::RegValueT<Pllccr_SPEC>;
1300
1301impl Pllccr {
1302 #[doc = "PLL Input Frequency Division Ratio Select"]
1303 #[inline(always)]
1304 pub fn plidiv(
1305 self,
1306 ) -> crate::common::RegisterField<
1307 0,
1308 0x3,
1309 1,
1310 0,
1311 pllccr::Plidiv,
1312 pllccr::Plidiv,
1313 Pllccr_SPEC,
1314 crate::common::RW,
1315 > {
1316 crate::common::RegisterField::<
1317 0,
1318 0x3,
1319 1,
1320 0,
1321 pllccr::Plidiv,
1322 pllccr::Plidiv,
1323 Pllccr_SPEC,
1324 crate::common::RW,
1325 >::from_register(self, 0)
1326 }
1327
1328 #[doc = "PLL Clock Source Select"]
1329 #[inline(always)]
1330 pub fn plsrcsel(
1331 self,
1332 ) -> crate::common::RegisterField<
1333 4,
1334 0x1,
1335 1,
1336 0,
1337 pllccr::Plsrcsel,
1338 pllccr::Plsrcsel,
1339 Pllccr_SPEC,
1340 crate::common::RW,
1341 > {
1342 crate::common::RegisterField::<
1343 4,
1344 0x1,
1345 1,
1346 0,
1347 pllccr::Plsrcsel,
1348 pllccr::Plsrcsel,
1349 Pllccr_SPEC,
1350 crate::common::RW,
1351 >::from_register(self, 0)
1352 }
1353
1354 #[doc = "PLL Frequency Multiplication Factor Select"]
1355 #[inline(always)]
1356 pub fn pllmul(
1357 self,
1358 ) -> crate::common::RegisterField<8, 0x3f, 1, 0, u8, u8, Pllccr_SPEC, crate::common::RW> {
1359 crate::common::RegisterField::<8,0x3f,1,0,u8,u8,Pllccr_SPEC,crate::common::RW>::from_register(self,0)
1360 }
1361}
1362impl ::core::default::Default for Pllccr {
1363 #[inline(always)]
1364 fn default() -> Pllccr {
1365 <crate::RegValueT<Pllccr_SPEC> as RegisterValue<_>>::new(4864)
1366 }
1367}
1368pub mod pllccr {
1369
1370 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1371 pub struct Plidiv_SPEC;
1372 pub type Plidiv = crate::EnumBitfieldStruct<u8, Plidiv_SPEC>;
1373 impl Plidiv {
1374 #[doc = "/1"]
1375 pub const _00: Self = Self::new(0);
1376
1377 #[doc = "/2"]
1378 pub const _01: Self = Self::new(1);
1379
1380 #[doc = "/3"]
1381 pub const _10: Self = Self::new(2);
1382 }
1383 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1384 pub struct Plsrcsel_SPEC;
1385 pub type Plsrcsel = crate::EnumBitfieldStruct<u8, Plsrcsel_SPEC>;
1386 impl Plsrcsel {
1387 #[doc = "Main clock oscillator"]
1388 pub const _0: Self = Self::new(0);
1389
1390 #[doc = "HOCO"]
1391 pub const _1: Self = Self::new(1);
1392 }
1393}
1394#[doc(hidden)]
1395#[derive(Copy, Clone, Eq, PartialEq)]
1396pub struct Pllcr_SPEC;
1397impl crate::sealed::RegSpec for Pllcr_SPEC {
1398 type DataType = u8;
1399}
1400
1401#[doc = "PLL Control Register"]
1402pub type Pllcr = crate::RegValueT<Pllcr_SPEC>;
1403
1404impl Pllcr {
1405 #[doc = "PLL Stop Control"]
1406 #[inline(always)]
1407 pub fn pllstp(
1408 self,
1409 ) -> crate::common::RegisterField<
1410 0,
1411 0x1,
1412 1,
1413 0,
1414 pllcr::Pllstp,
1415 pllcr::Pllstp,
1416 Pllcr_SPEC,
1417 crate::common::RW,
1418 > {
1419 crate::common::RegisterField::<
1420 0,
1421 0x1,
1422 1,
1423 0,
1424 pllcr::Pllstp,
1425 pllcr::Pllstp,
1426 Pllcr_SPEC,
1427 crate::common::RW,
1428 >::from_register(self, 0)
1429 }
1430}
1431impl ::core::default::Default for Pllcr {
1432 #[inline(always)]
1433 fn default() -> Pllcr {
1434 <crate::RegValueT<Pllcr_SPEC> as RegisterValue<_>>::new(1)
1435 }
1436}
1437pub mod pllcr {
1438
1439 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1440 pub struct Pllstp_SPEC;
1441 pub type Pllstp = crate::EnumBitfieldStruct<u8, Pllstp_SPEC>;
1442 impl Pllstp {
1443 #[doc = "PLL is operating"]
1444 pub const _0: Self = Self::new(0);
1445
1446 #[doc = "PLL is stopped."]
1447 pub const _1: Self = Self::new(1);
1448 }
1449}
1450#[doc(hidden)]
1451#[derive(Copy, Clone, Eq, PartialEq)]
1452pub struct Mosccr_SPEC;
1453impl crate::sealed::RegSpec for Mosccr_SPEC {
1454 type DataType = u8;
1455}
1456
1457#[doc = "Main Clock Oscillator Control Register"]
1458pub type Mosccr = crate::RegValueT<Mosccr_SPEC>;
1459
1460impl Mosccr {
1461 #[doc = "Main Clock Oscillator Stop"]
1462 #[inline(always)]
1463 pub fn mostp(
1464 self,
1465 ) -> crate::common::RegisterField<
1466 0,
1467 0x1,
1468 1,
1469 0,
1470 mosccr::Mostp,
1471 mosccr::Mostp,
1472 Mosccr_SPEC,
1473 crate::common::RW,
1474 > {
1475 crate::common::RegisterField::<
1476 0,
1477 0x1,
1478 1,
1479 0,
1480 mosccr::Mostp,
1481 mosccr::Mostp,
1482 Mosccr_SPEC,
1483 crate::common::RW,
1484 >::from_register(self, 0)
1485 }
1486}
1487impl ::core::default::Default for Mosccr {
1488 #[inline(always)]
1489 fn default() -> Mosccr {
1490 <crate::RegValueT<Mosccr_SPEC> as RegisterValue<_>>::new(1)
1491 }
1492}
1493pub mod mosccr {
1494
1495 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1496 pub struct Mostp_SPEC;
1497 pub type Mostp = crate::EnumBitfieldStruct<u8, Mostp_SPEC>;
1498 impl Mostp {
1499 #[doc = "Operate the main clock oscillator"]
1500 pub const _0: Self = Self::new(0);
1501
1502 #[doc = "Stop the main clock oscillator"]
1503 pub const _1: Self = Self::new(1);
1504 }
1505}
1506#[doc(hidden)]
1507#[derive(Copy, Clone, Eq, PartialEq)]
1508pub struct Hococr_SPEC;
1509impl crate::sealed::RegSpec for Hococr_SPEC {
1510 type DataType = u8;
1511}
1512
1513#[doc = "High-Speed On-Chip Oscillator Control Register"]
1514pub type Hococr = crate::RegValueT<Hococr_SPEC>;
1515
1516impl Hococr {
1517 #[doc = "HOCO Stop"]
1518 #[inline(always)]
1519 pub fn hcstp(
1520 self,
1521 ) -> crate::common::RegisterField<
1522 0,
1523 0x1,
1524 1,
1525 0,
1526 hococr::Hcstp,
1527 hococr::Hcstp,
1528 Hococr_SPEC,
1529 crate::common::RW,
1530 > {
1531 crate::common::RegisterField::<
1532 0,
1533 0x1,
1534 1,
1535 0,
1536 hococr::Hcstp,
1537 hococr::Hcstp,
1538 Hococr_SPEC,
1539 crate::common::RW,
1540 >::from_register(self, 0)
1541 }
1542}
1543impl ::core::default::Default for Hococr {
1544 #[inline(always)]
1545 fn default() -> Hococr {
1546 <crate::RegValueT<Hococr_SPEC> as RegisterValue<_>>::new(0)
1547 }
1548}
1549pub mod hococr {
1550
1551 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1552 pub struct Hcstp_SPEC;
1553 pub type Hcstp = crate::EnumBitfieldStruct<u8, Hcstp_SPEC>;
1554 impl Hcstp {
1555 #[doc = "Operate the HOCO clock"]
1556 pub const _0: Self = Self::new(0);
1557
1558 #[doc = "Stop the HOCO clock"]
1559 pub const _1: Self = Self::new(1);
1560 }
1561}
1562#[doc(hidden)]
1563#[derive(Copy, Clone, Eq, PartialEq)]
1564pub struct Hococr2_SPEC;
1565impl crate::sealed::RegSpec for Hococr2_SPEC {
1566 type DataType = u8;
1567}
1568
1569#[doc = "High-Speed On-Chip Oscillator Control Register 2"]
1570pub type Hococr2 = crate::RegValueT<Hococr2_SPEC>;
1571
1572impl Hococr2 {
1573 #[doc = "HOCO Frequency Setting 0"]
1574 #[inline(always)]
1575 pub fn hcfrq0(
1576 self,
1577 ) -> crate::common::RegisterField<
1578 0,
1579 0x3,
1580 1,
1581 0,
1582 hococr2::Hcfrq0,
1583 hococr2::Hcfrq0,
1584 Hococr2_SPEC,
1585 crate::common::RW,
1586 > {
1587 crate::common::RegisterField::<
1588 0,
1589 0x3,
1590 1,
1591 0,
1592 hococr2::Hcfrq0,
1593 hococr2::Hcfrq0,
1594 Hococr2_SPEC,
1595 crate::common::RW,
1596 >::from_register(self, 0)
1597 }
1598}
1599impl ::core::default::Default for Hococr2 {
1600 #[inline(always)]
1601 fn default() -> Hococr2 {
1602 <crate::RegValueT<Hococr2_SPEC> as RegisterValue<_>>::new(0)
1603 }
1604}
1605pub mod hococr2 {
1606
1607 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1608 pub struct Hcfrq0_SPEC;
1609 pub type Hcfrq0 = crate::EnumBitfieldStruct<u8, Hcfrq0_SPEC>;
1610 impl Hcfrq0 {
1611 #[doc = "16 MHz"]
1612 pub const _00: Self = Self::new(0);
1613
1614 #[doc = "18 MHz"]
1615 pub const _01: Self = Self::new(1);
1616
1617 #[doc = "20 MHz"]
1618 pub const _10: Self = Self::new(2);
1619
1620 #[doc = "Setting prohibited"]
1621 pub const _11: Self = Self::new(3);
1622 }
1623}
1624#[doc(hidden)]
1625#[derive(Copy, Clone, Eq, PartialEq)]
1626pub struct Mococr_SPEC;
1627impl crate::sealed::RegSpec for Mococr_SPEC {
1628 type DataType = u8;
1629}
1630
1631#[doc = "Middle-Speed On-Chip Oscillator Control Register"]
1632pub type Mococr = crate::RegValueT<Mococr_SPEC>;
1633
1634impl Mococr {
1635 #[doc = "MOCO Stop"]
1636 #[inline(always)]
1637 pub fn mcstp(
1638 self,
1639 ) -> crate::common::RegisterField<
1640 0,
1641 0x1,
1642 1,
1643 0,
1644 mococr::Mcstp,
1645 mococr::Mcstp,
1646 Mococr_SPEC,
1647 crate::common::RW,
1648 > {
1649 crate::common::RegisterField::<
1650 0,
1651 0x1,
1652 1,
1653 0,
1654 mococr::Mcstp,
1655 mococr::Mcstp,
1656 Mococr_SPEC,
1657 crate::common::RW,
1658 >::from_register(self, 0)
1659 }
1660}
1661impl ::core::default::Default for Mococr {
1662 #[inline(always)]
1663 fn default() -> Mococr {
1664 <crate::RegValueT<Mococr_SPEC> as RegisterValue<_>>::new(0)
1665 }
1666}
1667pub mod mococr {
1668
1669 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1670 pub struct Mcstp_SPEC;
1671 pub type Mcstp = crate::EnumBitfieldStruct<u8, Mcstp_SPEC>;
1672 impl Mcstp {
1673 #[doc = "MOCO clock is operating"]
1674 pub const _0: Self = Self::new(0);
1675
1676 #[doc = "MOCO clock is stopped"]
1677 pub const _1: Self = Self::new(1);
1678 }
1679}
1680#[doc(hidden)]
1681#[derive(Copy, Clone, Eq, PartialEq)]
1682pub struct Fllcr1_SPEC;
1683impl crate::sealed::RegSpec for Fllcr1_SPEC {
1684 type DataType = u8;
1685}
1686
1687#[doc = "FLL Control Register1"]
1688pub type Fllcr1 = crate::RegValueT<Fllcr1_SPEC>;
1689
1690impl Fllcr1 {
1691 #[doc = "FLL Enable"]
1692 #[inline(always)]
1693 pub fn fllen(
1694 self,
1695 ) -> crate::common::RegisterField<
1696 0,
1697 0x1,
1698 1,
1699 0,
1700 fllcr1::Fllen,
1701 fllcr1::Fllen,
1702 Fllcr1_SPEC,
1703 crate::common::RW,
1704 > {
1705 crate::common::RegisterField::<
1706 0,
1707 0x1,
1708 1,
1709 0,
1710 fllcr1::Fllen,
1711 fllcr1::Fllen,
1712 Fllcr1_SPEC,
1713 crate::common::RW,
1714 >::from_register(self, 0)
1715 }
1716}
1717impl ::core::default::Default for Fllcr1 {
1718 #[inline(always)]
1719 fn default() -> Fllcr1 {
1720 <crate::RegValueT<Fllcr1_SPEC> as RegisterValue<_>>::new(0)
1721 }
1722}
1723pub mod fllcr1 {
1724
1725 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1726 pub struct Fllen_SPEC;
1727 pub type Fllen = crate::EnumBitfieldStruct<u8, Fllen_SPEC>;
1728 impl Fllen {
1729 #[doc = "FLL function is disabled"]
1730 pub const _0: Self = Self::new(0);
1731
1732 #[doc = "FLL function is enabled."]
1733 pub const _1: Self = Self::new(1);
1734 }
1735}
1736#[doc(hidden)]
1737#[derive(Copy, Clone, Eq, PartialEq)]
1738pub struct Fllcr2_SPEC;
1739impl crate::sealed::RegSpec for Fllcr2_SPEC {
1740 type DataType = u16;
1741}
1742
1743#[doc = "FLL Control Register2"]
1744pub type Fllcr2 = crate::RegValueT<Fllcr2_SPEC>;
1745
1746impl Fllcr2 {
1747 #[doc = "FLL Multiplication Control"]
1748 #[inline(always)]
1749 pub fn fllcntl(
1750 self,
1751 ) -> crate::common::RegisterField<0, 0x7ff, 1, 0, u16, u16, Fllcr2_SPEC, crate::common::RW>
1752 {
1753 crate::common::RegisterField::<0,0x7ff,1,0,u16,u16,Fllcr2_SPEC,crate::common::RW>::from_register(self,0)
1754 }
1755}
1756impl ::core::default::Default for Fllcr2 {
1757 #[inline(always)]
1758 fn default() -> Fllcr2 {
1759 <crate::RegValueT<Fllcr2_SPEC> as RegisterValue<_>>::new(0)
1760 }
1761}
1762
1763#[doc(hidden)]
1764#[derive(Copy, Clone, Eq, PartialEq)]
1765pub struct Oscsf_SPEC;
1766impl crate::sealed::RegSpec for Oscsf_SPEC {
1767 type DataType = u8;
1768}
1769
1770#[doc = "Oscillation Stabilization Flag Register"]
1771pub type Oscsf = crate::RegValueT<Oscsf_SPEC>;
1772
1773impl Oscsf {
1774 #[doc = "HOCO Clock Oscillation Stabilization Flag"]
1775 #[inline(always)]
1776 pub fn hocosf(
1777 self,
1778 ) -> crate::common::RegisterField<
1779 0,
1780 0x1,
1781 1,
1782 0,
1783 oscsf::Hocosf,
1784 oscsf::Hocosf,
1785 Oscsf_SPEC,
1786 crate::common::R,
1787 > {
1788 crate::common::RegisterField::<
1789 0,
1790 0x1,
1791 1,
1792 0,
1793 oscsf::Hocosf,
1794 oscsf::Hocosf,
1795 Oscsf_SPEC,
1796 crate::common::R,
1797 >::from_register(self, 0)
1798 }
1799
1800 #[doc = "Main Clock Oscillation Stabilization Flag"]
1801 #[inline(always)]
1802 pub fn moscsf(
1803 self,
1804 ) -> crate::common::RegisterField<
1805 3,
1806 0x1,
1807 1,
1808 0,
1809 oscsf::Moscsf,
1810 oscsf::Moscsf,
1811 Oscsf_SPEC,
1812 crate::common::R,
1813 > {
1814 crate::common::RegisterField::<
1815 3,
1816 0x1,
1817 1,
1818 0,
1819 oscsf::Moscsf,
1820 oscsf::Moscsf,
1821 Oscsf_SPEC,
1822 crate::common::R,
1823 >::from_register(self, 0)
1824 }
1825
1826 #[doc = "PLL Clock Oscillation Stabilization Flag"]
1827 #[inline(always)]
1828 pub fn pllsf(
1829 self,
1830 ) -> crate::common::RegisterField<
1831 5,
1832 0x1,
1833 1,
1834 0,
1835 oscsf::Pllsf,
1836 oscsf::Pllsf,
1837 Oscsf_SPEC,
1838 crate::common::R,
1839 > {
1840 crate::common::RegisterField::<
1841 5,
1842 0x1,
1843 1,
1844 0,
1845 oscsf::Pllsf,
1846 oscsf::Pllsf,
1847 Oscsf_SPEC,
1848 crate::common::R,
1849 >::from_register(self, 0)
1850 }
1851}
1852impl ::core::default::Default for Oscsf {
1853 #[inline(always)]
1854 fn default() -> Oscsf {
1855 <crate::RegValueT<Oscsf_SPEC> as RegisterValue<_>>::new(0)
1856 }
1857}
1858pub mod oscsf {
1859
1860 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1861 pub struct Hocosf_SPEC;
1862 pub type Hocosf = crate::EnumBitfieldStruct<u8, Hocosf_SPEC>;
1863 impl Hocosf {
1864 #[doc = "The HOCO clock is stopped or is not yet stable"]
1865 pub const _0: Self = Self::new(0);
1866
1867 #[doc = "The HOCO clock is stable, so is available for use as the system clock"]
1868 pub const _1: Self = Self::new(1);
1869 }
1870 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1871 pub struct Moscsf_SPEC;
1872 pub type Moscsf = crate::EnumBitfieldStruct<u8, Moscsf_SPEC>;
1873 impl Moscsf {
1874 #[doc = "The main clock oscillator is stopped (MOSTP = 1) or is not yet stable"]
1875 pub const _0: Self = Self::new(0);
1876
1877 #[doc = "The main clock oscillator is stable, so is available for use as the system clock"]
1878 pub const _1: Self = Self::new(1);
1879 }
1880 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1881 pub struct Pllsf_SPEC;
1882 pub type Pllsf = crate::EnumBitfieldStruct<u8, Pllsf_SPEC>;
1883 impl Pllsf {
1884 #[doc = "The PLL clock is stopped, or oscillation of the PLL clock is not stable yet"]
1885 pub const _0: Self = Self::new(0);
1886
1887 #[doc = "The PLL clock is stable, so is available for use as the system clock"]
1888 pub const _1: Self = Self::new(1);
1889 }
1890}
1891#[doc(hidden)]
1892#[derive(Copy, Clone, Eq, PartialEq)]
1893pub struct Ckocr_SPEC;
1894impl crate::sealed::RegSpec for Ckocr_SPEC {
1895 type DataType = u8;
1896}
1897
1898#[doc = "Clock Out Control Register"]
1899pub type Ckocr = crate::RegValueT<Ckocr_SPEC>;
1900
1901impl Ckocr {
1902 #[doc = "Clock Out Source Select"]
1903 #[inline(always)]
1904 pub fn ckosel(
1905 self,
1906 ) -> crate::common::RegisterField<
1907 0,
1908 0x7,
1909 1,
1910 0,
1911 ckocr::Ckosel,
1912 ckocr::Ckosel,
1913 Ckocr_SPEC,
1914 crate::common::RW,
1915 > {
1916 crate::common::RegisterField::<
1917 0,
1918 0x7,
1919 1,
1920 0,
1921 ckocr::Ckosel,
1922 ckocr::Ckosel,
1923 Ckocr_SPEC,
1924 crate::common::RW,
1925 >::from_register(self, 0)
1926 }
1927
1928 #[doc = "Clock Output Frequency Division Ratio"]
1929 #[inline(always)]
1930 pub fn ckodiv(
1931 self,
1932 ) -> crate::common::RegisterField<
1933 4,
1934 0x7,
1935 1,
1936 0,
1937 ckocr::Ckodiv,
1938 ckocr::Ckodiv,
1939 Ckocr_SPEC,
1940 crate::common::RW,
1941 > {
1942 crate::common::RegisterField::<
1943 4,
1944 0x7,
1945 1,
1946 0,
1947 ckocr::Ckodiv,
1948 ckocr::Ckodiv,
1949 Ckocr_SPEC,
1950 crate::common::RW,
1951 >::from_register(self, 0)
1952 }
1953
1954 #[doc = "Clock Out Enable"]
1955 #[inline(always)]
1956 pub fn ckoen(
1957 self,
1958 ) -> crate::common::RegisterField<
1959 7,
1960 0x1,
1961 1,
1962 0,
1963 ckocr::Ckoen,
1964 ckocr::Ckoen,
1965 Ckocr_SPEC,
1966 crate::common::RW,
1967 > {
1968 crate::common::RegisterField::<
1969 7,
1970 0x1,
1971 1,
1972 0,
1973 ckocr::Ckoen,
1974 ckocr::Ckoen,
1975 Ckocr_SPEC,
1976 crate::common::RW,
1977 >::from_register(self, 0)
1978 }
1979}
1980impl ::core::default::Default for Ckocr {
1981 #[inline(always)]
1982 fn default() -> Ckocr {
1983 <crate::RegValueT<Ckocr_SPEC> as RegisterValue<_>>::new(0)
1984 }
1985}
1986pub mod ckocr {
1987
1988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1989 pub struct Ckosel_SPEC;
1990 pub type Ckosel = crate::EnumBitfieldStruct<u8, Ckosel_SPEC>;
1991 impl Ckosel {
1992 #[doc = "HOCO (value after reset)"]
1993 pub const _000: Self = Self::new(0);
1994
1995 #[doc = "MOCO"]
1996 pub const _001: Self = Self::new(1);
1997
1998 #[doc = "LOCO"]
1999 pub const _010: Self = Self::new(2);
2000
2001 #[doc = "MOSC"]
2002 pub const _011: Self = Self::new(3);
2003
2004 #[doc = "SOSC"]
2005 pub const _100: Self = Self::new(4);
2006
2007 #[doc = "Setting prohibited"]
2008 pub const _101: Self = Self::new(5);
2009 }
2010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2011 pub struct Ckodiv_SPEC;
2012 pub type Ckodiv = crate::EnumBitfieldStruct<u8, Ckodiv_SPEC>;
2013 impl Ckodiv {
2014 #[doc = "x 1/1"]
2015 pub const _000: Self = Self::new(0);
2016
2017 #[doc = "x 1/2"]
2018 pub const _001: Self = Self::new(1);
2019
2020 #[doc = "x 1/4"]
2021 pub const _010: Self = Self::new(2);
2022
2023 #[doc = "x 1/8"]
2024 pub const _011: Self = Self::new(3);
2025
2026 #[doc = "x 1/16"]
2027 pub const _100: Self = Self::new(4);
2028
2029 #[doc = "x 1/32"]
2030 pub const _101: Self = Self::new(5);
2031
2032 #[doc = "x 1/64"]
2033 pub const _110: Self = Self::new(6);
2034
2035 #[doc = "x 1/128"]
2036 pub const _111: Self = Self::new(7);
2037 }
2038 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2039 pub struct Ckoen_SPEC;
2040 pub type Ckoen = crate::EnumBitfieldStruct<u8, Ckoen_SPEC>;
2041 impl Ckoen {
2042 #[doc = "Disable clock out"]
2043 pub const _0: Self = Self::new(0);
2044
2045 #[doc = "Enable clock out"]
2046 pub const _1: Self = Self::new(1);
2047 }
2048}
2049#[doc(hidden)]
2050#[derive(Copy, Clone, Eq, PartialEq)]
2051pub struct Ostdcr_SPEC;
2052impl crate::sealed::RegSpec for Ostdcr_SPEC {
2053 type DataType = u8;
2054}
2055
2056#[doc = "Oscillation Stop Detection Control Register"]
2057pub type Ostdcr = crate::RegValueT<Ostdcr_SPEC>;
2058
2059impl Ostdcr {
2060 #[doc = "Oscillation Stop Detection Interrupt Enable"]
2061 #[inline(always)]
2062 pub fn ostdie(
2063 self,
2064 ) -> crate::common::RegisterField<
2065 0,
2066 0x1,
2067 1,
2068 0,
2069 ostdcr::Ostdie,
2070 ostdcr::Ostdie,
2071 Ostdcr_SPEC,
2072 crate::common::RW,
2073 > {
2074 crate::common::RegisterField::<
2075 0,
2076 0x1,
2077 1,
2078 0,
2079 ostdcr::Ostdie,
2080 ostdcr::Ostdie,
2081 Ostdcr_SPEC,
2082 crate::common::RW,
2083 >::from_register(self, 0)
2084 }
2085
2086 #[doc = "Oscillation Stop Detection Function Enable"]
2087 #[inline(always)]
2088 pub fn ostde(
2089 self,
2090 ) -> crate::common::RegisterField<
2091 7,
2092 0x1,
2093 1,
2094 0,
2095 ostdcr::Ostde,
2096 ostdcr::Ostde,
2097 Ostdcr_SPEC,
2098 crate::common::RW,
2099 > {
2100 crate::common::RegisterField::<
2101 7,
2102 0x1,
2103 1,
2104 0,
2105 ostdcr::Ostde,
2106 ostdcr::Ostde,
2107 Ostdcr_SPEC,
2108 crate::common::RW,
2109 >::from_register(self, 0)
2110 }
2111}
2112impl ::core::default::Default for Ostdcr {
2113 #[inline(always)]
2114 fn default() -> Ostdcr {
2115 <crate::RegValueT<Ostdcr_SPEC> as RegisterValue<_>>::new(0)
2116 }
2117}
2118pub mod ostdcr {
2119
2120 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2121 pub struct Ostdie_SPEC;
2122 pub type Ostdie = crate::EnumBitfieldStruct<u8, Ostdie_SPEC>;
2123 impl Ostdie {
2124 #[doc = "Disable oscillation stop detection interrupt (do not notify the POEG)"]
2125 pub const _0: Self = Self::new(0);
2126
2127 #[doc = "Enable oscillation stop detection interrupt (notify the POEG)"]
2128 pub const _1: Self = Self::new(1);
2129 }
2130 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2131 pub struct Ostde_SPEC;
2132 pub type Ostde = crate::EnumBitfieldStruct<u8, Ostde_SPEC>;
2133 impl Ostde {
2134 #[doc = "Disable oscillation stop detection function"]
2135 pub const _0: Self = Self::new(0);
2136
2137 #[doc = "Enable oscillation stop detection function"]
2138 pub const _1: Self = Self::new(1);
2139 }
2140}
2141#[doc(hidden)]
2142#[derive(Copy, Clone, Eq, PartialEq)]
2143pub struct Ostdsr_SPEC;
2144impl crate::sealed::RegSpec for Ostdsr_SPEC {
2145 type DataType = u8;
2146}
2147
2148#[doc = "Oscillation Stop Detection Status Register"]
2149pub type Ostdsr = crate::RegValueT<Ostdsr_SPEC>;
2150
2151impl Ostdsr {
2152 #[doc = "Oscillation Stop Detection Flag"]
2153 #[inline(always)]
2154 pub fn ostdf(
2155 self,
2156 ) -> crate::common::RegisterField<
2157 0,
2158 0x1,
2159 1,
2160 0,
2161 ostdsr::Ostdf,
2162 ostdsr::Ostdf,
2163 Ostdsr_SPEC,
2164 crate::common::RW,
2165 > {
2166 crate::common::RegisterField::<
2167 0,
2168 0x1,
2169 1,
2170 0,
2171 ostdsr::Ostdf,
2172 ostdsr::Ostdf,
2173 Ostdsr_SPEC,
2174 crate::common::RW,
2175 >::from_register(self, 0)
2176 }
2177}
2178impl ::core::default::Default for Ostdsr {
2179 #[inline(always)]
2180 fn default() -> Ostdsr {
2181 <crate::RegValueT<Ostdsr_SPEC> as RegisterValue<_>>::new(0)
2182 }
2183}
2184pub mod ostdsr {
2185
2186 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2187 pub struct Ostdf_SPEC;
2188 pub type Ostdf = crate::EnumBitfieldStruct<u8, Ostdf_SPEC>;
2189 impl Ostdf {
2190 #[doc = "Main clock oscillation stop not detected"]
2191 pub const _0: Self = Self::new(0);
2192
2193 #[doc = "Main clock oscillation stop detected"]
2194 pub const _1: Self = Self::new(1);
2195 }
2196}
2197#[doc(hidden)]
2198#[derive(Copy, Clone, Eq, PartialEq)]
2199pub struct Mocoutcr_SPEC;
2200impl crate::sealed::RegSpec for Mocoutcr_SPEC {
2201 type DataType = u8;
2202}
2203
2204#[doc = "MOCO User Trimming Control Register"]
2205pub type Mocoutcr = crate::RegValueT<Mocoutcr_SPEC>;
2206
2207impl Mocoutcr {
2208 #[doc = "MOCO User Trimming"]
2209 #[inline(always)]
2210 pub fn mocoutrm(
2211 self,
2212 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Mocoutcr_SPEC, crate::common::RW> {
2213 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Mocoutcr_SPEC,crate::common::RW>::from_register(self,0)
2214 }
2215}
2216impl ::core::default::Default for Mocoutcr {
2217 #[inline(always)]
2218 fn default() -> Mocoutcr {
2219 <crate::RegValueT<Mocoutcr_SPEC> as RegisterValue<_>>::new(0)
2220 }
2221}
2222
2223#[doc(hidden)]
2224#[derive(Copy, Clone, Eq, PartialEq)]
2225pub struct Hocoutcr_SPEC;
2226impl crate::sealed::RegSpec for Hocoutcr_SPEC {
2227 type DataType = u8;
2228}
2229
2230#[doc = "HOCO User Trimming Control Register"]
2231pub type Hocoutcr = crate::RegValueT<Hocoutcr_SPEC>;
2232
2233impl Hocoutcr {
2234 #[doc = "HOCO User Trimming"]
2235 #[inline(always)]
2236 pub fn hocoutrm(
2237 self,
2238 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Hocoutcr_SPEC, crate::common::RW> {
2239 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Hocoutcr_SPEC,crate::common::RW>::from_register(self,0)
2240 }
2241}
2242impl ::core::default::Default for Hocoutcr {
2243 #[inline(always)]
2244 fn default() -> Hocoutcr {
2245 <crate::RegValueT<Hocoutcr_SPEC> as RegisterValue<_>>::new(0)
2246 }
2247}
2248
2249#[doc(hidden)]
2250#[derive(Copy, Clone, Eq, PartialEq)]
2251pub struct Usbckdivcr_SPEC;
2252impl crate::sealed::RegSpec for Usbckdivcr_SPEC {
2253 type DataType = u8;
2254}
2255
2256#[doc = "USB Clock Division Control Register"]
2257pub type Usbckdivcr = crate::RegValueT<Usbckdivcr_SPEC>;
2258
2259impl Usbckdivcr {
2260 #[doc = "USB Clock (USBCLK) Division Select"]
2261 #[inline(always)]
2262 pub fn usbckdiv(
2263 self,
2264 ) -> crate::common::RegisterField<
2265 0,
2266 0x7,
2267 1,
2268 0,
2269 usbckdivcr::Usbckdiv,
2270 usbckdivcr::Usbckdiv,
2271 Usbckdivcr_SPEC,
2272 crate::common::RW,
2273 > {
2274 crate::common::RegisterField::<
2275 0,
2276 0x7,
2277 1,
2278 0,
2279 usbckdivcr::Usbckdiv,
2280 usbckdivcr::Usbckdiv,
2281 Usbckdivcr_SPEC,
2282 crate::common::RW,
2283 >::from_register(self, 0)
2284 }
2285}
2286impl ::core::default::Default for Usbckdivcr {
2287 #[inline(always)]
2288 fn default() -> Usbckdivcr {
2289 <crate::RegValueT<Usbckdivcr_SPEC> as RegisterValue<_>>::new(0)
2290 }
2291}
2292pub mod usbckdivcr {
2293
2294 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2295 pub struct Usbckdiv_SPEC;
2296 pub type Usbckdiv = crate::EnumBitfieldStruct<u8, Usbckdiv_SPEC>;
2297 impl Usbckdiv {
2298 #[doc = "∕ 4"]
2299 pub const _010: Self = Self::new(2);
2300
2301 #[doc = "∕ 3"]
2302 pub const _101: Self = Self::new(5);
2303
2304 #[doc = "∕ 5"]
2305 pub const _110: Self = Self::new(6);
2306 }
2307}
2308#[doc(hidden)]
2309#[derive(Copy, Clone, Eq, PartialEq)]
2310pub struct Canfdckdivcr_SPEC;
2311impl crate::sealed::RegSpec for Canfdckdivcr_SPEC {
2312 type DataType = u8;
2313}
2314
2315#[doc = "CANFD Clock Division Control Register"]
2316pub type Canfdckdivcr = crate::RegValueT<Canfdckdivcr_SPEC>;
2317
2318impl Canfdckdivcr {
2319 #[doc = "CANFD clock (CANFDCLK) Division Select"]
2320 #[inline(always)]
2321 pub fn canfdckdiv(
2322 self,
2323 ) -> crate::common::RegisterField<
2324 0,
2325 0x7,
2326 1,
2327 0,
2328 canfdckdivcr::Canfdckdiv,
2329 canfdckdivcr::Canfdckdiv,
2330 Canfdckdivcr_SPEC,
2331 crate::common::RW,
2332 > {
2333 crate::common::RegisterField::<
2334 0,
2335 0x7,
2336 1,
2337 0,
2338 canfdckdivcr::Canfdckdiv,
2339 canfdckdivcr::Canfdckdiv,
2340 Canfdckdivcr_SPEC,
2341 crate::common::RW,
2342 >::from_register(self, 0)
2343 }
2344}
2345impl ::core::default::Default for Canfdckdivcr {
2346 #[inline(always)]
2347 fn default() -> Canfdckdivcr {
2348 <crate::RegValueT<Canfdckdivcr_SPEC> as RegisterValue<_>>::new(0)
2349 }
2350}
2351pub mod canfdckdivcr {
2352
2353 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2354 pub struct Canfdckdiv_SPEC;
2355 pub type Canfdckdiv = crate::EnumBitfieldStruct<u8, Canfdckdiv_SPEC>;
2356 impl Canfdckdiv {
2357 #[doc = "/1 (value after reset) /2 /4 /6 /8 /3 /5"]
2358 pub const _000: Self = Self::new(0);
2359 }
2360}
2361#[doc(hidden)]
2362#[derive(Copy, Clone, Eq, PartialEq)]
2363pub struct Cecckdivcr_SPEC;
2364impl crate::sealed::RegSpec for Cecckdivcr_SPEC {
2365 type DataType = u8;
2366}
2367
2368#[doc = "CEC Clock Division Control Register"]
2369pub type Cecckdivcr = crate::RegValueT<Cecckdivcr_SPEC>;
2370
2371impl Cecckdivcr {
2372 #[doc = "CEC clock (CECCLK) Division Select"]
2373 #[inline(always)]
2374 pub fn cecckdiv(
2375 self,
2376 ) -> crate::common::RegisterField<
2377 0,
2378 0x7,
2379 1,
2380 0,
2381 cecckdivcr::Cecckdiv,
2382 cecckdivcr::Cecckdiv,
2383 Cecckdivcr_SPEC,
2384 crate::common::RW,
2385 > {
2386 crate::common::RegisterField::<
2387 0,
2388 0x7,
2389 1,
2390 0,
2391 cecckdivcr::Cecckdiv,
2392 cecckdivcr::Cecckdiv,
2393 Cecckdivcr_SPEC,
2394 crate::common::RW,
2395 >::from_register(self, 0)
2396 }
2397}
2398impl ::core::default::Default for Cecckdivcr {
2399 #[inline(always)]
2400 fn default() -> Cecckdivcr {
2401 <crate::RegValueT<Cecckdivcr_SPEC> as RegisterValue<_>>::new(1)
2402 }
2403}
2404pub mod cecckdivcr {
2405
2406 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2407 pub struct Cecckdiv_SPEC;
2408 pub type Cecckdiv = crate::EnumBitfieldStruct<u8, Cecckdiv_SPEC>;
2409 impl Cecckdiv {
2410 #[doc = "/1 (value after reset)"]
2411 pub const _000: Self = Self::new(0);
2412
2413 #[doc = "/2"]
2414 pub const _001: Self = Self::new(1);
2415 }
2416}
2417#[doc(hidden)]
2418#[derive(Copy, Clone, Eq, PartialEq)]
2419pub struct I3Cckdivcr_SPEC;
2420impl crate::sealed::RegSpec for I3Cckdivcr_SPEC {
2421 type DataType = u8;
2422}
2423
2424#[doc = "I3C Clock Division Control Register"]
2425pub type I3Cckdivcr = crate::RegValueT<I3Cckdivcr_SPEC>;
2426
2427impl I3Cckdivcr {
2428 #[doc = "I3C clock (I3CCLK) division select"]
2429 #[inline(always)]
2430 pub fn i3cckdiv(
2431 self,
2432 ) -> crate::common::RegisterField<
2433 0,
2434 0x7,
2435 1,
2436 0,
2437 i3cckdivcr::I3Cckdiv,
2438 i3cckdivcr::I3Cckdiv,
2439 I3Cckdivcr_SPEC,
2440 crate::common::RW,
2441 > {
2442 crate::common::RegisterField::<
2443 0,
2444 0x7,
2445 1,
2446 0,
2447 i3cckdivcr::I3Cckdiv,
2448 i3cckdivcr::I3Cckdiv,
2449 I3Cckdivcr_SPEC,
2450 crate::common::RW,
2451 >::from_register(self, 0)
2452 }
2453}
2454impl ::core::default::Default for I3Cckdivcr {
2455 #[inline(always)]
2456 fn default() -> I3Cckdivcr {
2457 <crate::RegValueT<I3Cckdivcr_SPEC> as RegisterValue<_>>::new(0)
2458 }
2459}
2460pub mod i3cckdivcr {
2461
2462 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2463 pub struct I3Cckdiv_SPEC;
2464 pub type I3Cckdiv = crate::EnumBitfieldStruct<u8, I3Cckdiv_SPEC>;
2465 impl I3Cckdiv {
2466 #[doc = "/1 (value after reset)"]
2467 pub const _000: Self = Self::new(0);
2468
2469 #[doc = "/2"]
2470 pub const _001: Self = Self::new(1);
2471
2472 #[doc = "/4"]
2473 pub const _010: Self = Self::new(2);
2474
2475 #[doc = "/6"]
2476 pub const _011: Self = Self::new(3);
2477
2478 #[doc = "/8"]
2479 pub const _100: Self = Self::new(4);
2480 }
2481}
2482#[doc(hidden)]
2483#[derive(Copy, Clone, Eq, PartialEq)]
2484pub struct Usbckcr_SPEC;
2485impl crate::sealed::RegSpec for Usbckcr_SPEC {
2486 type DataType = u8;
2487}
2488
2489#[doc = "USB Clock Control Register"]
2490pub type Usbckcr = crate::RegValueT<Usbckcr_SPEC>;
2491
2492impl Usbckcr {
2493 #[doc = "USB Clock (USBCLK) Source Select"]
2494 #[inline(always)]
2495 pub fn usbcksel(
2496 self,
2497 ) -> crate::common::RegisterField<
2498 0,
2499 0x7,
2500 1,
2501 0,
2502 usbckcr::Usbcksel,
2503 usbckcr::Usbcksel,
2504 Usbckcr_SPEC,
2505 crate::common::RW,
2506 > {
2507 crate::common::RegisterField::<
2508 0,
2509 0x7,
2510 1,
2511 0,
2512 usbckcr::Usbcksel,
2513 usbckcr::Usbcksel,
2514 Usbckcr_SPEC,
2515 crate::common::RW,
2516 >::from_register(self, 0)
2517 }
2518
2519 #[doc = "USB Clock (USBCLK) Switching Request"]
2520 #[inline(always)]
2521 pub fn usbcksreq(
2522 self,
2523 ) -> crate::common::RegisterField<
2524 6,
2525 0x1,
2526 1,
2527 0,
2528 usbckcr::Usbcksreq,
2529 usbckcr::Usbcksreq,
2530 Usbckcr_SPEC,
2531 crate::common::RW,
2532 > {
2533 crate::common::RegisterField::<
2534 6,
2535 0x1,
2536 1,
2537 0,
2538 usbckcr::Usbcksreq,
2539 usbckcr::Usbcksreq,
2540 Usbckcr_SPEC,
2541 crate::common::RW,
2542 >::from_register(self, 0)
2543 }
2544
2545 #[doc = "USB Clock (USBCLK) Switching Ready state flag"]
2546 #[inline(always)]
2547 pub fn usbcksrdy(
2548 self,
2549 ) -> crate::common::RegisterField<
2550 7,
2551 0x1,
2552 1,
2553 0,
2554 usbckcr::Usbcksrdy,
2555 usbckcr::Usbcksrdy,
2556 Usbckcr_SPEC,
2557 crate::common::R,
2558 > {
2559 crate::common::RegisterField::<
2560 7,
2561 0x1,
2562 1,
2563 0,
2564 usbckcr::Usbcksrdy,
2565 usbckcr::Usbcksrdy,
2566 Usbckcr_SPEC,
2567 crate::common::R,
2568 >::from_register(self, 0)
2569 }
2570}
2571impl ::core::default::Default for Usbckcr {
2572 #[inline(always)]
2573 fn default() -> Usbckcr {
2574 <crate::RegValueT<Usbckcr_SPEC> as RegisterValue<_>>::new(1)
2575 }
2576}
2577pub mod usbckcr {
2578
2579 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2580 pub struct Usbcksel_SPEC;
2581 pub type Usbcksel = crate::EnumBitfieldStruct<u8, Usbcksel_SPEC>;
2582 impl Usbcksel {
2583 #[doc = "PLL"]
2584 pub const _101: Self = Self::new(5);
2585 }
2586 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2587 pub struct Usbcksreq_SPEC;
2588 pub type Usbcksreq = crate::EnumBitfieldStruct<u8, Usbcksreq_SPEC>;
2589 impl Usbcksreq {
2590 #[doc = "No request"]
2591 pub const _0: Self = Self::new(0);
2592
2593 #[doc = "Request switching."]
2594 pub const _1: Self = Self::new(1);
2595 }
2596 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2597 pub struct Usbcksrdy_SPEC;
2598 pub type Usbcksrdy = crate::EnumBitfieldStruct<u8, Usbcksrdy_SPEC>;
2599 impl Usbcksrdy {
2600 #[doc = "Impossible to Switch"]
2601 pub const _0: Self = Self::new(0);
2602
2603 #[doc = "Possible to Switch"]
2604 pub const _1: Self = Self::new(1);
2605 }
2606}
2607#[doc(hidden)]
2608#[derive(Copy, Clone, Eq, PartialEq)]
2609pub struct Canfdckcr_SPEC;
2610impl crate::sealed::RegSpec for Canfdckcr_SPEC {
2611 type DataType = u8;
2612}
2613
2614#[doc = "CANFD Clock Control Register"]
2615pub type Canfdckcr = crate::RegValueT<Canfdckcr_SPEC>;
2616
2617impl Canfdckcr {
2618 #[doc = "CANFD clock (CANFDCLK) Source Select"]
2619 #[inline(always)]
2620 pub fn canfdcksel(
2621 self,
2622 ) -> crate::common::RegisterField<
2623 0,
2624 0x7,
2625 1,
2626 0,
2627 canfdckcr::Canfdcksel,
2628 canfdckcr::Canfdcksel,
2629 Canfdckcr_SPEC,
2630 crate::common::RW,
2631 > {
2632 crate::common::RegisterField::<
2633 0,
2634 0x7,
2635 1,
2636 0,
2637 canfdckcr::Canfdcksel,
2638 canfdckcr::Canfdcksel,
2639 Canfdckcr_SPEC,
2640 crate::common::RW,
2641 >::from_register(self, 0)
2642 }
2643
2644 #[doc = "CANFD clock (CANFDCLK) Switching Request"]
2645 #[inline(always)]
2646 pub fn canfdcksreq(
2647 self,
2648 ) -> crate::common::RegisterField<
2649 6,
2650 0x1,
2651 1,
2652 0,
2653 canfdckcr::Canfdcksreq,
2654 canfdckcr::Canfdcksreq,
2655 Canfdckcr_SPEC,
2656 crate::common::RW,
2657 > {
2658 crate::common::RegisterField::<
2659 6,
2660 0x1,
2661 1,
2662 0,
2663 canfdckcr::Canfdcksreq,
2664 canfdckcr::Canfdcksreq,
2665 Canfdckcr_SPEC,
2666 crate::common::RW,
2667 >::from_register(self, 0)
2668 }
2669
2670 #[doc = "CANFD clock (CANFDCLK) Switching Ready state flag"]
2671 #[inline(always)]
2672 pub fn canfdcksrdy(
2673 self,
2674 ) -> crate::common::RegisterField<
2675 7,
2676 0x1,
2677 1,
2678 0,
2679 canfdckcr::Canfdcksrdy,
2680 canfdckcr::Canfdcksrdy,
2681 Canfdckcr_SPEC,
2682 crate::common::R,
2683 > {
2684 crate::common::RegisterField::<
2685 7,
2686 0x1,
2687 1,
2688 0,
2689 canfdckcr::Canfdcksrdy,
2690 canfdckcr::Canfdcksrdy,
2691 Canfdckcr_SPEC,
2692 crate::common::R,
2693 >::from_register(self, 0)
2694 }
2695}
2696impl ::core::default::Default for Canfdckcr {
2697 #[inline(always)]
2698 fn default() -> Canfdckcr {
2699 <crate::RegValueT<Canfdckcr_SPEC> as RegisterValue<_>>::new(1)
2700 }
2701}
2702pub mod canfdckcr {
2703
2704 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2705 pub struct Canfdcksel_SPEC;
2706 pub type Canfdcksel = crate::EnumBitfieldStruct<u8, Canfdcksel_SPEC>;
2707 impl Canfdcksel {
2708 #[doc = "PLL"]
2709 pub const _101: Self = Self::new(5);
2710 }
2711 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2712 pub struct Canfdcksreq_SPEC;
2713 pub type Canfdcksreq = crate::EnumBitfieldStruct<u8, Canfdcksreq_SPEC>;
2714 impl Canfdcksreq {
2715 #[doc = "No request"]
2716 pub const _0: Self = Self::new(0);
2717
2718 #[doc = "Request switching"]
2719 pub const _1: Self = Self::new(1);
2720 }
2721 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2722 pub struct Canfdcksrdy_SPEC;
2723 pub type Canfdcksrdy = crate::EnumBitfieldStruct<u8, Canfdcksrdy_SPEC>;
2724 impl Canfdcksrdy {
2725 #[doc = "Impossible to Switch"]
2726 pub const _0: Self = Self::new(0);
2727
2728 #[doc = "Possible to Switch"]
2729 pub const _1: Self = Self::new(1);
2730 }
2731}
2732#[doc(hidden)]
2733#[derive(Copy, Clone, Eq, PartialEq)]
2734pub struct Cecckcr_SPEC;
2735impl crate::sealed::RegSpec for Cecckcr_SPEC {
2736 type DataType = u8;
2737}
2738
2739#[doc = "CEC Clock Control Register"]
2740pub type Cecckcr = crate::RegValueT<Cecckcr_SPEC>;
2741
2742impl Cecckcr {
2743 #[doc = "CEC clock (CECCLK) Source Select"]
2744 #[inline(always)]
2745 pub fn ceccksel(
2746 self,
2747 ) -> crate::common::RegisterField<
2748 0,
2749 0x7,
2750 1,
2751 0,
2752 cecckcr::Ceccksel,
2753 cecckcr::Ceccksel,
2754 Cecckcr_SPEC,
2755 crate::common::RW,
2756 > {
2757 crate::common::RegisterField::<
2758 0,
2759 0x7,
2760 1,
2761 0,
2762 cecckcr::Ceccksel,
2763 cecckcr::Ceccksel,
2764 Cecckcr_SPEC,
2765 crate::common::RW,
2766 >::from_register(self, 0)
2767 }
2768
2769 #[doc = "CEC clock (CECCLK) Switching Request"]
2770 #[inline(always)]
2771 pub fn ceccksreq(
2772 self,
2773 ) -> crate::common::RegisterField<
2774 6,
2775 0x1,
2776 1,
2777 0,
2778 cecckcr::Ceccksreq,
2779 cecckcr::Ceccksreq,
2780 Cecckcr_SPEC,
2781 crate::common::RW,
2782 > {
2783 crate::common::RegisterField::<
2784 6,
2785 0x1,
2786 1,
2787 0,
2788 cecckcr::Ceccksreq,
2789 cecckcr::Ceccksreq,
2790 Cecckcr_SPEC,
2791 crate::common::RW,
2792 >::from_register(self, 0)
2793 }
2794
2795 #[doc = "CEC clock (CECCLK) Switching Ready state flag"]
2796 #[inline(always)]
2797 pub fn ceccksrdy(
2798 self,
2799 ) -> crate::common::RegisterField<
2800 7,
2801 0x1,
2802 1,
2803 0,
2804 cecckcr::Ceccksrdy,
2805 cecckcr::Ceccksrdy,
2806 Cecckcr_SPEC,
2807 crate::common::R,
2808 > {
2809 crate::common::RegisterField::<
2810 7,
2811 0x1,
2812 1,
2813 0,
2814 cecckcr::Ceccksrdy,
2815 cecckcr::Ceccksrdy,
2816 Cecckcr_SPEC,
2817 crate::common::R,
2818 >::from_register(self, 0)
2819 }
2820}
2821impl ::core::default::Default for Cecckcr {
2822 #[inline(always)]
2823 fn default() -> Cecckcr {
2824 <crate::RegValueT<Cecckcr_SPEC> as RegisterValue<_>>::new(1)
2825 }
2826}
2827pub mod cecckcr {
2828
2829 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2830 pub struct Ceccksel_SPEC;
2831 pub type Ceccksel = crate::EnumBitfieldStruct<u8, Ceccksel_SPEC>;
2832 impl Ceccksel {
2833 #[doc = "Main clock oscillator"]
2834 pub const _011: Self = Self::new(3);
2835
2836 #[doc = "Sub-clock oscillator"]
2837 pub const _100: Self = Self::new(4);
2838 }
2839 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2840 pub struct Ceccksreq_SPEC;
2841 pub type Ceccksreq = crate::EnumBitfieldStruct<u8, Ceccksreq_SPEC>;
2842 impl Ceccksreq {
2843 #[doc = "No request"]
2844 pub const _0: Self = Self::new(0);
2845
2846 #[doc = "Request switching"]
2847 pub const _1: Self = Self::new(1);
2848 }
2849 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2850 pub struct Ceccksrdy_SPEC;
2851 pub type Ceccksrdy = crate::EnumBitfieldStruct<u8, Ceccksrdy_SPEC>;
2852 impl Ceccksrdy {
2853 #[doc = "Impossible to Switch"]
2854 pub const _0: Self = Self::new(0);
2855
2856 #[doc = "Possible to Switch"]
2857 pub const _1: Self = Self::new(1);
2858 }
2859}
2860#[doc(hidden)]
2861#[derive(Copy, Clone, Eq, PartialEq)]
2862pub struct I3Cckcr_SPEC;
2863impl crate::sealed::RegSpec for I3Cckcr_SPEC {
2864 type DataType = u8;
2865}
2866
2867#[doc = "I3C Clock Control Register"]
2868pub type I3Cckcr = crate::RegValueT<I3Cckcr_SPEC>;
2869
2870impl I3Cckcr {
2871 #[doc = "I3C clock (I3CCLK) source select"]
2872 #[inline(always)]
2873 pub fn i3ccksel(
2874 self,
2875 ) -> crate::common::RegisterField<
2876 0,
2877 0x7,
2878 1,
2879 0,
2880 i3cckcr::I3Ccksel,
2881 i3cckcr::I3Ccksel,
2882 I3Cckcr_SPEC,
2883 crate::common::RW,
2884 > {
2885 crate::common::RegisterField::<
2886 0,
2887 0x7,
2888 1,
2889 0,
2890 i3cckcr::I3Ccksel,
2891 i3cckcr::I3Ccksel,
2892 I3Cckcr_SPEC,
2893 crate::common::RW,
2894 >::from_register(self, 0)
2895 }
2896
2897 #[doc = "I3C clock (I3CCLK) switching request"]
2898 #[inline(always)]
2899 pub fn i3ccksreq(
2900 self,
2901 ) -> crate::common::RegisterField<
2902 6,
2903 0x1,
2904 1,
2905 0,
2906 i3cckcr::I3Ccksreq,
2907 i3cckcr::I3Ccksreq,
2908 I3Cckcr_SPEC,
2909 crate::common::RW,
2910 > {
2911 crate::common::RegisterField::<
2912 6,
2913 0x1,
2914 1,
2915 0,
2916 i3cckcr::I3Ccksreq,
2917 i3cckcr::I3Ccksreq,
2918 I3Cckcr_SPEC,
2919 crate::common::RW,
2920 >::from_register(self, 0)
2921 }
2922
2923 #[doc = "I3C clock (I3CCLK) switching ready state flag"]
2924 #[inline(always)]
2925 pub fn i3ccksrdy(
2926 self,
2927 ) -> crate::common::RegisterField<
2928 7,
2929 0x1,
2930 1,
2931 0,
2932 i3cckcr::I3Ccksrdy,
2933 i3cckcr::I3Ccksrdy,
2934 I3Cckcr_SPEC,
2935 crate::common::R,
2936 > {
2937 crate::common::RegisterField::<
2938 7,
2939 0x1,
2940 1,
2941 0,
2942 i3cckcr::I3Ccksrdy,
2943 i3cckcr::I3Ccksrdy,
2944 I3Cckcr_SPEC,
2945 crate::common::R,
2946 >::from_register(self, 0)
2947 }
2948}
2949impl ::core::default::Default for I3Cckcr {
2950 #[inline(always)]
2951 fn default() -> I3Cckcr {
2952 <crate::RegValueT<I3Cckcr_SPEC> as RegisterValue<_>>::new(0)
2953 }
2954}
2955pub mod i3cckcr {
2956
2957 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2958 pub struct I3Ccksel_SPEC;
2959 pub type I3Ccksel = crate::EnumBitfieldStruct<u8, I3Ccksel_SPEC>;
2960 impl I3Ccksel {
2961 #[doc = "HOCO"]
2962 pub const _000: Self = Self::new(0);
2963
2964 #[doc = "MOCO (value after reset)"]
2965 pub const _001: Self = Self::new(1);
2966
2967 #[doc = "LOCO"]
2968 pub const _010: Self = Self::new(2);
2969
2970 #[doc = "Main clock oscillator"]
2971 pub const _011: Self = Self::new(3);
2972
2973 #[doc = "Sub-clock oscillator"]
2974 pub const _100: Self = Self::new(4);
2975
2976 #[doc = "PLL"]
2977 pub const _101: Self = Self::new(5);
2978 }
2979 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2980 pub struct I3Ccksreq_SPEC;
2981 pub type I3Ccksreq = crate::EnumBitfieldStruct<u8, I3Ccksreq_SPEC>;
2982 impl I3Ccksreq {
2983 #[doc = "No request"]
2984 pub const _0: Self = Self::new(0);
2985
2986 #[doc = "Request switching"]
2987 pub const _1: Self = Self::new(1);
2988 }
2989 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2990 pub struct I3Ccksrdy_SPEC;
2991 pub type I3Ccksrdy = crate::EnumBitfieldStruct<u8, I3Ccksrdy_SPEC>;
2992 impl I3Ccksrdy {
2993 #[doc = "Impossible to Switch"]
2994 pub const _0: Self = Self::new(0);
2995
2996 #[doc = "Possible to Switch"]
2997 pub const _1: Self = Self::new(1);
2998 }
2999}
3000#[doc(hidden)]
3001#[derive(Copy, Clone, Eq, PartialEq)]
3002pub struct Snzcr_SPEC;
3003impl crate::sealed::RegSpec for Snzcr_SPEC {
3004 type DataType = u8;
3005}
3006
3007#[doc = "Snooze Control Register"]
3008pub type Snzcr = crate::RegValueT<Snzcr_SPEC>;
3009
3010impl Snzcr {
3011 #[doc = "RXD0 Snooze Request Enable"]
3012 #[inline(always)]
3013 pub fn rxdreqen(
3014 self,
3015 ) -> crate::common::RegisterField<
3016 0,
3017 0x1,
3018 1,
3019 0,
3020 snzcr::Rxdreqen,
3021 snzcr::Rxdreqen,
3022 Snzcr_SPEC,
3023 crate::common::RW,
3024 > {
3025 crate::common::RegisterField::<
3026 0,
3027 0x1,
3028 1,
3029 0,
3030 snzcr::Rxdreqen,
3031 snzcr::Rxdreqen,
3032 Snzcr_SPEC,
3033 crate::common::RW,
3034 >::from_register(self, 0)
3035 }
3036
3037 #[doc = "DTC Enable in Snooze mode"]
3038 #[inline(always)]
3039 pub fn snzdtcen(
3040 self,
3041 ) -> crate::common::RegisterField<
3042 1,
3043 0x1,
3044 1,
3045 0,
3046 snzcr::Snzdtcen,
3047 snzcr::Snzdtcen,
3048 Snzcr_SPEC,
3049 crate::common::RW,
3050 > {
3051 crate::common::RegisterField::<
3052 1,
3053 0x1,
3054 1,
3055 0,
3056 snzcr::Snzdtcen,
3057 snzcr::Snzdtcen,
3058 Snzcr_SPEC,
3059 crate::common::RW,
3060 >::from_register(self, 0)
3061 }
3062
3063 #[doc = "Snooze mode Enable"]
3064 #[inline(always)]
3065 pub fn snze(
3066 self,
3067 ) -> crate::common::RegisterField<
3068 7,
3069 0x1,
3070 1,
3071 0,
3072 snzcr::Snze,
3073 snzcr::Snze,
3074 Snzcr_SPEC,
3075 crate::common::RW,
3076 > {
3077 crate::common::RegisterField::<
3078 7,
3079 0x1,
3080 1,
3081 0,
3082 snzcr::Snze,
3083 snzcr::Snze,
3084 Snzcr_SPEC,
3085 crate::common::RW,
3086 >::from_register(self, 0)
3087 }
3088}
3089impl ::core::default::Default for Snzcr {
3090 #[inline(always)]
3091 fn default() -> Snzcr {
3092 <crate::RegValueT<Snzcr_SPEC> as RegisterValue<_>>::new(0)
3093 }
3094}
3095pub mod snzcr {
3096
3097 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3098 pub struct Rxdreqen_SPEC;
3099 pub type Rxdreqen = crate::EnumBitfieldStruct<u8, Rxdreqen_SPEC>;
3100 impl Rxdreqen {
3101 #[doc = "Ignore RXD0 falling edge in Software Standby mode"]
3102 pub const _0: Self = Self::new(0);
3103
3104 #[doc = "Detect RXD0 falling edge in Software Standby mode"]
3105 pub const _1: Self = Self::new(1);
3106 }
3107 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3108 pub struct Snzdtcen_SPEC;
3109 pub type Snzdtcen = crate::EnumBitfieldStruct<u8, Snzdtcen_SPEC>;
3110 impl Snzdtcen {
3111 #[doc = "Disable DTC operation"]
3112 pub const _0: Self = Self::new(0);
3113
3114 #[doc = "Enable DTC operation"]
3115 pub const _1: Self = Self::new(1);
3116 }
3117 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3118 pub struct Snze_SPEC;
3119 pub type Snze = crate::EnumBitfieldStruct<u8, Snze_SPEC>;
3120 impl Snze {
3121 #[doc = "Disable Snooze mode"]
3122 pub const _0: Self = Self::new(0);
3123
3124 #[doc = "Enable Snooze mode"]
3125 pub const _1: Self = Self::new(1);
3126 }
3127}
3128#[doc(hidden)]
3129#[derive(Copy, Clone, Eq, PartialEq)]
3130pub struct Snzedcr0_SPEC;
3131impl crate::sealed::RegSpec for Snzedcr0_SPEC {
3132 type DataType = u8;
3133}
3134
3135#[doc = "Snooze End Control Register 0"]
3136pub type Snzedcr0 = crate::RegValueT<Snzedcr0_SPEC>;
3137
3138impl Snzedcr0 {
3139 #[doc = "AGT1 Underflow Snooze End Enable"]
3140 #[inline(always)]
3141 pub fn agtunfed(
3142 self,
3143 ) -> crate::common::RegisterField<
3144 0,
3145 0x1,
3146 1,
3147 0,
3148 snzedcr0::Agtunfed,
3149 snzedcr0::Agtunfed,
3150 Snzedcr0_SPEC,
3151 crate::common::RW,
3152 > {
3153 crate::common::RegisterField::<
3154 0,
3155 0x1,
3156 1,
3157 0,
3158 snzedcr0::Agtunfed,
3159 snzedcr0::Agtunfed,
3160 Snzedcr0_SPEC,
3161 crate::common::RW,
3162 >::from_register(self, 0)
3163 }
3164
3165 #[doc = "Last DTC Transmission Completion Snooze End Enable"]
3166 #[inline(always)]
3167 pub fn dtczred(
3168 self,
3169 ) -> crate::common::RegisterField<
3170 1,
3171 0x1,
3172 1,
3173 0,
3174 snzedcr0::Dtczred,
3175 snzedcr0::Dtczred,
3176 Snzedcr0_SPEC,
3177 crate::common::RW,
3178 > {
3179 crate::common::RegisterField::<
3180 1,
3181 0x1,
3182 1,
3183 0,
3184 snzedcr0::Dtczred,
3185 snzedcr0::Dtczred,
3186 Snzedcr0_SPEC,
3187 crate::common::RW,
3188 >::from_register(self, 0)
3189 }
3190
3191 #[doc = "Not Last DTC Transmission Completion Snooze End Enable"]
3192 #[inline(always)]
3193 pub fn dtcnzred(
3194 self,
3195 ) -> crate::common::RegisterField<
3196 2,
3197 0x1,
3198 1,
3199 0,
3200 snzedcr0::Dtcnzred,
3201 snzedcr0::Dtcnzred,
3202 Snzedcr0_SPEC,
3203 crate::common::RW,
3204 > {
3205 crate::common::RegisterField::<
3206 2,
3207 0x1,
3208 1,
3209 0,
3210 snzedcr0::Dtcnzred,
3211 snzedcr0::Dtcnzred,
3212 Snzedcr0_SPEC,
3213 crate::common::RW,
3214 >::from_register(self, 0)
3215 }
3216
3217 #[doc = "ADC120 Compare Match Snooze End Enable"]
3218 #[inline(always)]
3219 pub fn ad0mated(
3220 self,
3221 ) -> crate::common::RegisterField<
3222 3,
3223 0x1,
3224 1,
3225 0,
3226 snzedcr0::Ad0Mated,
3227 snzedcr0::Ad0Mated,
3228 Snzedcr0_SPEC,
3229 crate::common::RW,
3230 > {
3231 crate::common::RegisterField::<
3232 3,
3233 0x1,
3234 1,
3235 0,
3236 snzedcr0::Ad0Mated,
3237 snzedcr0::Ad0Mated,
3238 Snzedcr0_SPEC,
3239 crate::common::RW,
3240 >::from_register(self, 0)
3241 }
3242
3243 #[doc = "ADC120 Compare Mismatch Snooze End Enable"]
3244 #[inline(always)]
3245 pub fn ad0umted(
3246 self,
3247 ) -> crate::common::RegisterField<
3248 4,
3249 0x1,
3250 1,
3251 0,
3252 snzedcr0::Ad0Umted,
3253 snzedcr0::Ad0Umted,
3254 Snzedcr0_SPEC,
3255 crate::common::RW,
3256 > {
3257 crate::common::RegisterField::<
3258 4,
3259 0x1,
3260 1,
3261 0,
3262 snzedcr0::Ad0Umted,
3263 snzedcr0::Ad0Umted,
3264 Snzedcr0_SPEC,
3265 crate::common::RW,
3266 >::from_register(self, 0)
3267 }
3268
3269 #[doc = "SCI0 Address Mismatch Snooze End Enable"]
3270 #[inline(always)]
3271 pub fn sci0umted(
3272 self,
3273 ) -> crate::common::RegisterField<
3274 7,
3275 0x1,
3276 1,
3277 0,
3278 snzedcr0::Sci0Umted,
3279 snzedcr0::Sci0Umted,
3280 Snzedcr0_SPEC,
3281 crate::common::RW,
3282 > {
3283 crate::common::RegisterField::<
3284 7,
3285 0x1,
3286 1,
3287 0,
3288 snzedcr0::Sci0Umted,
3289 snzedcr0::Sci0Umted,
3290 Snzedcr0_SPEC,
3291 crate::common::RW,
3292 >::from_register(self, 0)
3293 }
3294}
3295impl ::core::default::Default for Snzedcr0 {
3296 #[inline(always)]
3297 fn default() -> Snzedcr0 {
3298 <crate::RegValueT<Snzedcr0_SPEC> as RegisterValue<_>>::new(0)
3299 }
3300}
3301pub mod snzedcr0 {
3302
3303 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3304 pub struct Agtunfed_SPEC;
3305 pub type Agtunfed = crate::EnumBitfieldStruct<u8, Agtunfed_SPEC>;
3306 impl Agtunfed {
3307 #[doc = "Disable the snooze end request"]
3308 pub const _0: Self = Self::new(0);
3309
3310 #[doc = "Enable the snooze end request"]
3311 pub const _1: Self = Self::new(1);
3312 }
3313 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3314 pub struct Dtczred_SPEC;
3315 pub type Dtczred = crate::EnumBitfieldStruct<u8, Dtczred_SPEC>;
3316 impl Dtczred {
3317 #[doc = "Disable the snooze end request"]
3318 pub const _0: Self = Self::new(0);
3319
3320 #[doc = "Enable the snooze end request"]
3321 pub const _1: Self = Self::new(1);
3322 }
3323 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3324 pub struct Dtcnzred_SPEC;
3325 pub type Dtcnzred = crate::EnumBitfieldStruct<u8, Dtcnzred_SPEC>;
3326 impl Dtcnzred {
3327 #[doc = "Disable the snooze end request"]
3328 pub const _0: Self = Self::new(0);
3329
3330 #[doc = "Enable the snooze end request"]
3331 pub const _1: Self = Self::new(1);
3332 }
3333 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3334 pub struct Ad0Mated_SPEC;
3335 pub type Ad0Mated = crate::EnumBitfieldStruct<u8, Ad0Mated_SPEC>;
3336 impl Ad0Mated {
3337 #[doc = "Disable the snooze end request"]
3338 pub const _0: Self = Self::new(0);
3339
3340 #[doc = "Enable the snooze end request"]
3341 pub const _1: Self = Self::new(1);
3342 }
3343 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3344 pub struct Ad0Umted_SPEC;
3345 pub type Ad0Umted = crate::EnumBitfieldStruct<u8, Ad0Umted_SPEC>;
3346 impl Ad0Umted {
3347 #[doc = "Disable the snooze end request"]
3348 pub const _0: Self = Self::new(0);
3349
3350 #[doc = "Enable the snooze end request"]
3351 pub const _1: Self = Self::new(1);
3352 }
3353 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3354 pub struct Sci0Umted_SPEC;
3355 pub type Sci0Umted = crate::EnumBitfieldStruct<u8, Sci0Umted_SPEC>;
3356 impl Sci0Umted {
3357 #[doc = "Disable the snooze end request"]
3358 pub const _0: Self = Self::new(0);
3359
3360 #[doc = "Enable the snooze end request"]
3361 pub const _1: Self = Self::new(1);
3362 }
3363}
3364#[doc(hidden)]
3365#[derive(Copy, Clone, Eq, PartialEq)]
3366pub struct Snzreqcr0_SPEC;
3367impl crate::sealed::RegSpec for Snzreqcr0_SPEC {
3368 type DataType = u32;
3369}
3370
3371#[doc = "Snooze Request Control Register 0"]
3372pub type Snzreqcr0 = crate::RegValueT<Snzreqcr0_SPEC>;
3373
3374impl Snzreqcr0 {
3375 #[doc = "Enable IRQ0 pin snooze request"]
3376 #[inline(always)]
3377 pub fn snzreqen0(
3378 self,
3379 ) -> crate::common::RegisterField<
3380 0,
3381 0x1,
3382 1,
3383 0,
3384 snzreqcr0::Snzreqen0,
3385 snzreqcr0::Snzreqen0,
3386 Snzreqcr0_SPEC,
3387 crate::common::RW,
3388 > {
3389 crate::common::RegisterField::<
3390 0,
3391 0x1,
3392 1,
3393 0,
3394 snzreqcr0::Snzreqen0,
3395 snzreqcr0::Snzreqen0,
3396 Snzreqcr0_SPEC,
3397 crate::common::RW,
3398 >::from_register(self, 0)
3399 }
3400
3401 #[doc = "Enable IRQ1 pin snooze request"]
3402 #[inline(always)]
3403 pub fn snzreqen1(
3404 self,
3405 ) -> crate::common::RegisterField<
3406 1,
3407 0x1,
3408 1,
3409 0,
3410 snzreqcr0::Snzreqen1,
3411 snzreqcr0::Snzreqen1,
3412 Snzreqcr0_SPEC,
3413 crate::common::RW,
3414 > {
3415 crate::common::RegisterField::<
3416 1,
3417 0x1,
3418 1,
3419 0,
3420 snzreqcr0::Snzreqen1,
3421 snzreqcr0::Snzreqen1,
3422 Snzreqcr0_SPEC,
3423 crate::common::RW,
3424 >::from_register(self, 0)
3425 }
3426
3427 #[doc = "Enable IRQ2 pin snooze request"]
3428 #[inline(always)]
3429 pub fn snzreqen2(
3430 self,
3431 ) -> crate::common::RegisterField<
3432 2,
3433 0x1,
3434 1,
3435 0,
3436 snzreqcr0::Snzreqen2,
3437 snzreqcr0::Snzreqen2,
3438 Snzreqcr0_SPEC,
3439 crate::common::RW,
3440 > {
3441 crate::common::RegisterField::<
3442 2,
3443 0x1,
3444 1,
3445 0,
3446 snzreqcr0::Snzreqen2,
3447 snzreqcr0::Snzreqen2,
3448 Snzreqcr0_SPEC,
3449 crate::common::RW,
3450 >::from_register(self, 0)
3451 }
3452
3453 #[doc = "Enable IRQ3 pin snooze request"]
3454 #[inline(always)]
3455 pub fn snzreqen3(
3456 self,
3457 ) -> crate::common::RegisterField<
3458 3,
3459 0x1,
3460 1,
3461 0,
3462 snzreqcr0::Snzreqen3,
3463 snzreqcr0::Snzreqen3,
3464 Snzreqcr0_SPEC,
3465 crate::common::RW,
3466 > {
3467 crate::common::RegisterField::<
3468 3,
3469 0x1,
3470 1,
3471 0,
3472 snzreqcr0::Snzreqen3,
3473 snzreqcr0::Snzreqen3,
3474 Snzreqcr0_SPEC,
3475 crate::common::RW,
3476 >::from_register(self, 0)
3477 }
3478
3479 #[doc = "Enable IRQ4 pin snooze request"]
3480 #[inline(always)]
3481 pub fn snzreqen4(
3482 self,
3483 ) -> crate::common::RegisterField<
3484 4,
3485 0x1,
3486 1,
3487 0,
3488 snzreqcr0::Snzreqen4,
3489 snzreqcr0::Snzreqen4,
3490 Snzreqcr0_SPEC,
3491 crate::common::RW,
3492 > {
3493 crate::common::RegisterField::<
3494 4,
3495 0x1,
3496 1,
3497 0,
3498 snzreqcr0::Snzreqen4,
3499 snzreqcr0::Snzreqen4,
3500 Snzreqcr0_SPEC,
3501 crate::common::RW,
3502 >::from_register(self, 0)
3503 }
3504
3505 #[doc = "Enable IRQ5 pin snooze request"]
3506 #[inline(always)]
3507 pub fn snzreqen5(
3508 self,
3509 ) -> crate::common::RegisterField<
3510 5,
3511 0x1,
3512 1,
3513 0,
3514 snzreqcr0::Snzreqen5,
3515 snzreqcr0::Snzreqen5,
3516 Snzreqcr0_SPEC,
3517 crate::common::RW,
3518 > {
3519 crate::common::RegisterField::<
3520 5,
3521 0x1,
3522 1,
3523 0,
3524 snzreqcr0::Snzreqen5,
3525 snzreqcr0::Snzreqen5,
3526 Snzreqcr0_SPEC,
3527 crate::common::RW,
3528 >::from_register(self, 0)
3529 }
3530
3531 #[doc = "Enable IRQ6 pin snooze request"]
3532 #[inline(always)]
3533 pub fn snzreqen6(
3534 self,
3535 ) -> crate::common::RegisterField<
3536 6,
3537 0x1,
3538 1,
3539 0,
3540 snzreqcr0::Snzreqen6,
3541 snzreqcr0::Snzreqen6,
3542 Snzreqcr0_SPEC,
3543 crate::common::RW,
3544 > {
3545 crate::common::RegisterField::<
3546 6,
3547 0x1,
3548 1,
3549 0,
3550 snzreqcr0::Snzreqen6,
3551 snzreqcr0::Snzreqen6,
3552 Snzreqcr0_SPEC,
3553 crate::common::RW,
3554 >::from_register(self, 0)
3555 }
3556
3557 #[doc = "Enable IRQ7 pin snooze request"]
3558 #[inline(always)]
3559 pub fn snzreqen7(
3560 self,
3561 ) -> crate::common::RegisterField<
3562 7,
3563 0x1,
3564 1,
3565 0,
3566 snzreqcr0::Snzreqen7,
3567 snzreqcr0::Snzreqen7,
3568 Snzreqcr0_SPEC,
3569 crate::common::RW,
3570 > {
3571 crate::common::RegisterField::<
3572 7,
3573 0x1,
3574 1,
3575 0,
3576 snzreqcr0::Snzreqen7,
3577 snzreqcr0::Snzreqen7,
3578 Snzreqcr0_SPEC,
3579 crate::common::RW,
3580 >::from_register(self, 0)
3581 }
3582
3583 #[doc = "Enable IRQ8 pin snooze request"]
3584 #[inline(always)]
3585 pub fn snzreqen8(
3586 self,
3587 ) -> crate::common::RegisterField<
3588 8,
3589 0x1,
3590 1,
3591 0,
3592 snzreqcr0::Snzreqen8,
3593 snzreqcr0::Snzreqen8,
3594 Snzreqcr0_SPEC,
3595 crate::common::RW,
3596 > {
3597 crate::common::RegisterField::<
3598 8,
3599 0x1,
3600 1,
3601 0,
3602 snzreqcr0::Snzreqen8,
3603 snzreqcr0::Snzreqen8,
3604 Snzreqcr0_SPEC,
3605 crate::common::RW,
3606 >::from_register(self, 0)
3607 }
3608
3609 #[doc = "Enable IRQ9 pin snooze request"]
3610 #[inline(always)]
3611 pub fn snzreqen9(
3612 self,
3613 ) -> crate::common::RegisterField<
3614 9,
3615 0x1,
3616 1,
3617 0,
3618 snzreqcr0::Snzreqen9,
3619 snzreqcr0::Snzreqen9,
3620 Snzreqcr0_SPEC,
3621 crate::common::RW,
3622 > {
3623 crate::common::RegisterField::<
3624 9,
3625 0x1,
3626 1,
3627 0,
3628 snzreqcr0::Snzreqen9,
3629 snzreqcr0::Snzreqen9,
3630 Snzreqcr0_SPEC,
3631 crate::common::RW,
3632 >::from_register(self, 0)
3633 }
3634
3635 #[doc = "Enable IRQ10 pin snooze request"]
3636 #[inline(always)]
3637 pub fn snzreqen10(
3638 self,
3639 ) -> crate::common::RegisterField<
3640 10,
3641 0x1,
3642 1,
3643 0,
3644 snzreqcr0::Snzreqen10,
3645 snzreqcr0::Snzreqen10,
3646 Snzreqcr0_SPEC,
3647 crate::common::RW,
3648 > {
3649 crate::common::RegisterField::<
3650 10,
3651 0x1,
3652 1,
3653 0,
3654 snzreqcr0::Snzreqen10,
3655 snzreqcr0::Snzreqen10,
3656 Snzreqcr0_SPEC,
3657 crate::common::RW,
3658 >::from_register(self, 0)
3659 }
3660
3661 #[doc = "Enable IRQ11 pin snooze request"]
3662 #[inline(always)]
3663 pub fn snzreqen11(
3664 self,
3665 ) -> crate::common::RegisterField<
3666 11,
3667 0x1,
3668 1,
3669 0,
3670 snzreqcr0::Snzreqen11,
3671 snzreqcr0::Snzreqen11,
3672 Snzreqcr0_SPEC,
3673 crate::common::RW,
3674 > {
3675 crate::common::RegisterField::<
3676 11,
3677 0x1,
3678 1,
3679 0,
3680 snzreqcr0::Snzreqen11,
3681 snzreqcr0::Snzreqen11,
3682 Snzreqcr0_SPEC,
3683 crate::common::RW,
3684 >::from_register(self, 0)
3685 }
3686
3687 #[doc = "Enable IRQ12 pin snooze request"]
3688 #[inline(always)]
3689 pub fn snzreqen12(
3690 self,
3691 ) -> crate::common::RegisterField<
3692 12,
3693 0x1,
3694 1,
3695 0,
3696 snzreqcr0::Snzreqen12,
3697 snzreqcr0::Snzreqen12,
3698 Snzreqcr0_SPEC,
3699 crate::common::RW,
3700 > {
3701 crate::common::RegisterField::<
3702 12,
3703 0x1,
3704 1,
3705 0,
3706 snzreqcr0::Snzreqen12,
3707 snzreqcr0::Snzreqen12,
3708 Snzreqcr0_SPEC,
3709 crate::common::RW,
3710 >::from_register(self, 0)
3711 }
3712
3713 #[doc = "Enable IRQ13 pin snooze request"]
3714 #[inline(always)]
3715 pub fn snzreqen13(
3716 self,
3717 ) -> crate::common::RegisterField<
3718 13,
3719 0x1,
3720 1,
3721 0,
3722 snzreqcr0::Snzreqen13,
3723 snzreqcr0::Snzreqen13,
3724 Snzreqcr0_SPEC,
3725 crate::common::RW,
3726 > {
3727 crate::common::RegisterField::<
3728 13,
3729 0x1,
3730 1,
3731 0,
3732 snzreqcr0::Snzreqen13,
3733 snzreqcr0::Snzreqen13,
3734 Snzreqcr0_SPEC,
3735 crate::common::RW,
3736 >::from_register(self, 0)
3737 }
3738
3739 #[doc = "Enable IRQ14 pin snooze request"]
3740 #[inline(always)]
3741 pub fn snzreqen14(
3742 self,
3743 ) -> crate::common::RegisterField<
3744 14,
3745 0x1,
3746 1,
3747 0,
3748 snzreqcr0::Snzreqen14,
3749 snzreqcr0::Snzreqen14,
3750 Snzreqcr0_SPEC,
3751 crate::common::RW,
3752 > {
3753 crate::common::RegisterField::<
3754 14,
3755 0x1,
3756 1,
3757 0,
3758 snzreqcr0::Snzreqen14,
3759 snzreqcr0::Snzreqen14,
3760 Snzreqcr0_SPEC,
3761 crate::common::RW,
3762 >::from_register(self, 0)
3763 }
3764
3765 #[doc = "Enable RTC alarm snooze request"]
3766 #[inline(always)]
3767 pub fn snzreqen24(
3768 self,
3769 ) -> crate::common::RegisterField<
3770 24,
3771 0x1,
3772 1,
3773 0,
3774 snzreqcr0::Snzreqen24,
3775 snzreqcr0::Snzreqen24,
3776 Snzreqcr0_SPEC,
3777 crate::common::RW,
3778 > {
3779 crate::common::RegisterField::<
3780 24,
3781 0x1,
3782 1,
3783 0,
3784 snzreqcr0::Snzreqen24,
3785 snzreqcr0::Snzreqen24,
3786 Snzreqcr0_SPEC,
3787 crate::common::RW,
3788 >::from_register(self, 0)
3789 }
3790
3791 #[doc = "Enable RTC period snooze request"]
3792 #[inline(always)]
3793 pub fn snzreqen25(
3794 self,
3795 ) -> crate::common::RegisterField<
3796 25,
3797 0x1,
3798 1,
3799 0,
3800 snzreqcr0::Snzreqen25,
3801 snzreqcr0::Snzreqen25,
3802 Snzreqcr0_SPEC,
3803 crate::common::RW,
3804 > {
3805 crate::common::RegisterField::<
3806 25,
3807 0x1,
3808 1,
3809 0,
3810 snzreqcr0::Snzreqen25,
3811 snzreqcr0::Snzreqen25,
3812 Snzreqcr0_SPEC,
3813 crate::common::RW,
3814 >::from_register(self, 0)
3815 }
3816
3817 #[doc = "Enable AGT1 underflow snooze request"]
3818 #[inline(always)]
3819 pub fn snzreqen28(
3820 self,
3821 ) -> crate::common::RegisterField<
3822 28,
3823 0x1,
3824 1,
3825 0,
3826 snzreqcr0::Snzreqen28,
3827 snzreqcr0::Snzreqen28,
3828 Snzreqcr0_SPEC,
3829 crate::common::RW,
3830 > {
3831 crate::common::RegisterField::<
3832 28,
3833 0x1,
3834 1,
3835 0,
3836 snzreqcr0::Snzreqen28,
3837 snzreqcr0::Snzreqen28,
3838 Snzreqcr0_SPEC,
3839 crate::common::RW,
3840 >::from_register(self, 0)
3841 }
3842
3843 #[doc = "Enable AGT1 compare match A snooze request"]
3844 #[inline(always)]
3845 pub fn snzreqen29(
3846 self,
3847 ) -> crate::common::RegisterField<
3848 29,
3849 0x1,
3850 1,
3851 0,
3852 snzreqcr0::Snzreqen29,
3853 snzreqcr0::Snzreqen29,
3854 Snzreqcr0_SPEC,
3855 crate::common::RW,
3856 > {
3857 crate::common::RegisterField::<
3858 29,
3859 0x1,
3860 1,
3861 0,
3862 snzreqcr0::Snzreqen29,
3863 snzreqcr0::Snzreqen29,
3864 Snzreqcr0_SPEC,
3865 crate::common::RW,
3866 >::from_register(self, 0)
3867 }
3868
3869 #[doc = "Enable AGT1 compare match B snooze request"]
3870 #[inline(always)]
3871 pub fn snzreqen30(
3872 self,
3873 ) -> crate::common::RegisterField<
3874 30,
3875 0x1,
3876 1,
3877 0,
3878 snzreqcr0::Snzreqen30,
3879 snzreqcr0::Snzreqen30,
3880 Snzreqcr0_SPEC,
3881 crate::common::RW,
3882 > {
3883 crate::common::RegisterField::<
3884 30,
3885 0x1,
3886 1,
3887 0,
3888 snzreqcr0::Snzreqen30,
3889 snzreqcr0::Snzreqen30,
3890 Snzreqcr0_SPEC,
3891 crate::common::RW,
3892 >::from_register(self, 0)
3893 }
3894}
3895impl ::core::default::Default for Snzreqcr0 {
3896 #[inline(always)]
3897 fn default() -> Snzreqcr0 {
3898 <crate::RegValueT<Snzreqcr0_SPEC> as RegisterValue<_>>::new(0)
3899 }
3900}
3901pub mod snzreqcr0 {
3902
3903 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3904 pub struct Snzreqen0_SPEC;
3905 pub type Snzreqen0 = crate::EnumBitfieldStruct<u8, Snzreqen0_SPEC>;
3906 impl Snzreqen0 {
3907 #[doc = "Disable the snooze request"]
3908 pub const _0: Self = Self::new(0);
3909
3910 #[doc = "Enable the snooze request"]
3911 pub const _1: Self = Self::new(1);
3912 }
3913 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3914 pub struct Snzreqen1_SPEC;
3915 pub type Snzreqen1 = crate::EnumBitfieldStruct<u8, Snzreqen1_SPEC>;
3916 impl Snzreqen1 {
3917 #[doc = "Disable the snooze request"]
3918 pub const _0: Self = Self::new(0);
3919
3920 #[doc = "Enable the snooze request"]
3921 pub const _1: Self = Self::new(1);
3922 }
3923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3924 pub struct Snzreqen2_SPEC;
3925 pub type Snzreqen2 = crate::EnumBitfieldStruct<u8, Snzreqen2_SPEC>;
3926 impl Snzreqen2 {
3927 #[doc = "Disable the snooze request"]
3928 pub const _0: Self = Self::new(0);
3929
3930 #[doc = "Enable the snooze request"]
3931 pub const _1: Self = Self::new(1);
3932 }
3933 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3934 pub struct Snzreqen3_SPEC;
3935 pub type Snzreqen3 = crate::EnumBitfieldStruct<u8, Snzreqen3_SPEC>;
3936 impl Snzreqen3 {
3937 #[doc = "Disable the snooze request"]
3938 pub const _0: Self = Self::new(0);
3939
3940 #[doc = "Enable the snooze request"]
3941 pub const _1: Self = Self::new(1);
3942 }
3943 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3944 pub struct Snzreqen4_SPEC;
3945 pub type Snzreqen4 = crate::EnumBitfieldStruct<u8, Snzreqen4_SPEC>;
3946 impl Snzreqen4 {
3947 #[doc = "Disable the snooze request"]
3948 pub const _0: Self = Self::new(0);
3949
3950 #[doc = "Enable the snooze request"]
3951 pub const _1: Self = Self::new(1);
3952 }
3953 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3954 pub struct Snzreqen5_SPEC;
3955 pub type Snzreqen5 = crate::EnumBitfieldStruct<u8, Snzreqen5_SPEC>;
3956 impl Snzreqen5 {
3957 #[doc = "Disable the snooze request"]
3958 pub const _0: Self = Self::new(0);
3959
3960 #[doc = "Enable the snooze request"]
3961 pub const _1: Self = Self::new(1);
3962 }
3963 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3964 pub struct Snzreqen6_SPEC;
3965 pub type Snzreqen6 = crate::EnumBitfieldStruct<u8, Snzreqen6_SPEC>;
3966 impl Snzreqen6 {
3967 #[doc = "Disable the snooze request"]
3968 pub const _0: Self = Self::new(0);
3969
3970 #[doc = "Enable the snooze request"]
3971 pub const _1: Self = Self::new(1);
3972 }
3973 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3974 pub struct Snzreqen7_SPEC;
3975 pub type Snzreqen7 = crate::EnumBitfieldStruct<u8, Snzreqen7_SPEC>;
3976 impl Snzreqen7 {
3977 #[doc = "Disable the snooze request"]
3978 pub const _0: Self = Self::new(0);
3979
3980 #[doc = "Enable the snooze request"]
3981 pub const _1: Self = Self::new(1);
3982 }
3983 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3984 pub struct Snzreqen8_SPEC;
3985 pub type Snzreqen8 = crate::EnumBitfieldStruct<u8, Snzreqen8_SPEC>;
3986 impl Snzreqen8 {
3987 #[doc = "Disable the snooze request"]
3988 pub const _0: Self = Self::new(0);
3989
3990 #[doc = "Enable the snooze request"]
3991 pub const _1: Self = Self::new(1);
3992 }
3993 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3994 pub struct Snzreqen9_SPEC;
3995 pub type Snzreqen9 = crate::EnumBitfieldStruct<u8, Snzreqen9_SPEC>;
3996 impl Snzreqen9 {
3997 #[doc = "Disable the snooze request"]
3998 pub const _0: Self = Self::new(0);
3999
4000 #[doc = "Enable the snooze request"]
4001 pub const _1: Self = Self::new(1);
4002 }
4003 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4004 pub struct Snzreqen10_SPEC;
4005 pub type Snzreqen10 = crate::EnumBitfieldStruct<u8, Snzreqen10_SPEC>;
4006 impl Snzreqen10 {
4007 #[doc = "Disable the snooze request"]
4008 pub const _0: Self = Self::new(0);
4009
4010 #[doc = "Enable the snooze request"]
4011 pub const _1: Self = Self::new(1);
4012 }
4013 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4014 pub struct Snzreqen11_SPEC;
4015 pub type Snzreqen11 = crate::EnumBitfieldStruct<u8, Snzreqen11_SPEC>;
4016 impl Snzreqen11 {
4017 #[doc = "Disable the snooze request"]
4018 pub const _0: Self = Self::new(0);
4019
4020 #[doc = "Enable the snooze request"]
4021 pub const _1: Self = Self::new(1);
4022 }
4023 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4024 pub struct Snzreqen12_SPEC;
4025 pub type Snzreqen12 = crate::EnumBitfieldStruct<u8, Snzreqen12_SPEC>;
4026 impl Snzreqen12 {
4027 #[doc = "Disable the snooze request"]
4028 pub const _0: Self = Self::new(0);
4029
4030 #[doc = "Enable the snooze request"]
4031 pub const _1: Self = Self::new(1);
4032 }
4033 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4034 pub struct Snzreqen13_SPEC;
4035 pub type Snzreqen13 = crate::EnumBitfieldStruct<u8, Snzreqen13_SPEC>;
4036 impl Snzreqen13 {
4037 #[doc = "Disable the snooze request"]
4038 pub const _0: Self = Self::new(0);
4039
4040 #[doc = "Enable the snooze request"]
4041 pub const _1: Self = Self::new(1);
4042 }
4043 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4044 pub struct Snzreqen14_SPEC;
4045 pub type Snzreqen14 = crate::EnumBitfieldStruct<u8, Snzreqen14_SPEC>;
4046 impl Snzreqen14 {
4047 #[doc = "Disable the snooze request"]
4048 pub const _0: Self = Self::new(0);
4049
4050 #[doc = "Enable the snooze request"]
4051 pub const _1: Self = Self::new(1);
4052 }
4053 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4054 pub struct Snzreqen24_SPEC;
4055 pub type Snzreqen24 = crate::EnumBitfieldStruct<u8, Snzreqen24_SPEC>;
4056 impl Snzreqen24 {
4057 #[doc = "Disable the snooze request"]
4058 pub const _0: Self = Self::new(0);
4059
4060 #[doc = "Enable the snooze request"]
4061 pub const _1: Self = Self::new(1);
4062 }
4063 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4064 pub struct Snzreqen25_SPEC;
4065 pub type Snzreqen25 = crate::EnumBitfieldStruct<u8, Snzreqen25_SPEC>;
4066 impl Snzreqen25 {
4067 #[doc = "Disable the snooze request"]
4068 pub const _0: Self = Self::new(0);
4069
4070 #[doc = "Enable the snooze request"]
4071 pub const _1: Self = Self::new(1);
4072 }
4073 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4074 pub struct Snzreqen28_SPEC;
4075 pub type Snzreqen28 = crate::EnumBitfieldStruct<u8, Snzreqen28_SPEC>;
4076 impl Snzreqen28 {
4077 #[doc = "Disable the snooze request"]
4078 pub const _0: Self = Self::new(0);
4079
4080 #[doc = "Enable the snooze request"]
4081 pub const _1: Self = Self::new(1);
4082 }
4083 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4084 pub struct Snzreqen29_SPEC;
4085 pub type Snzreqen29 = crate::EnumBitfieldStruct<u8, Snzreqen29_SPEC>;
4086 impl Snzreqen29 {
4087 #[doc = "Disable the snooze request"]
4088 pub const _0: Self = Self::new(0);
4089
4090 #[doc = "Enable the snooze request"]
4091 pub const _1: Self = Self::new(1);
4092 }
4093 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4094 pub struct Snzreqen30_SPEC;
4095 pub type Snzreqen30 = crate::EnumBitfieldStruct<u8, Snzreqen30_SPEC>;
4096 impl Snzreqen30 {
4097 #[doc = "Disable the snooze request"]
4098 pub const _0: Self = Self::new(0);
4099
4100 #[doc = "Enable the snooze request"]
4101 pub const _1: Self = Self::new(1);
4102 }
4103}
4104#[doc(hidden)]
4105#[derive(Copy, Clone, Eq, PartialEq)]
4106pub struct Opccr_SPEC;
4107impl crate::sealed::RegSpec for Opccr_SPEC {
4108 type DataType = u8;
4109}
4110
4111#[doc = "Operating Power Control Register"]
4112pub type Opccr = crate::RegValueT<Opccr_SPEC>;
4113
4114impl Opccr {
4115 #[doc = "Operating Power Control Mode Select"]
4116 #[inline(always)]
4117 pub fn opcm(
4118 self,
4119 ) -> crate::common::RegisterField<
4120 0,
4121 0x3,
4122 1,
4123 0,
4124 opccr::Opcm,
4125 opccr::Opcm,
4126 Opccr_SPEC,
4127 crate::common::RW,
4128 > {
4129 crate::common::RegisterField::<
4130 0,
4131 0x3,
4132 1,
4133 0,
4134 opccr::Opcm,
4135 opccr::Opcm,
4136 Opccr_SPEC,
4137 crate::common::RW,
4138 >::from_register(self, 0)
4139 }
4140
4141 #[doc = "Operating Power Control Mode Transition Status Flag"]
4142 #[inline(always)]
4143 pub fn opcmtsf(
4144 self,
4145 ) -> crate::common::RegisterField<
4146 4,
4147 0x1,
4148 1,
4149 0,
4150 opccr::Opcmtsf,
4151 opccr::Opcmtsf,
4152 Opccr_SPEC,
4153 crate::common::R,
4154 > {
4155 crate::common::RegisterField::<
4156 4,
4157 0x1,
4158 1,
4159 0,
4160 opccr::Opcmtsf,
4161 opccr::Opcmtsf,
4162 Opccr_SPEC,
4163 crate::common::R,
4164 >::from_register(self, 0)
4165 }
4166}
4167impl ::core::default::Default for Opccr {
4168 #[inline(always)]
4169 fn default() -> Opccr {
4170 <crate::RegValueT<Opccr_SPEC> as RegisterValue<_>>::new(0)
4171 }
4172}
4173pub mod opccr {
4174
4175 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4176 pub struct Opcm_SPEC;
4177 pub type Opcm = crate::EnumBitfieldStruct<u8, Opcm_SPEC>;
4178 impl Opcm {
4179 #[doc = "High-speed mode"]
4180 pub const _00: Self = Self::new(0);
4181
4182 #[doc = "Setting prohibited"]
4183 pub const _01: Self = Self::new(1);
4184
4185 #[doc = "Setting prohibited"]
4186 pub const _10: Self = Self::new(2);
4187
4188 #[doc = "Low-speed mode"]
4189 pub const _11: Self = Self::new(3);
4190 }
4191 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4192 pub struct Opcmtsf_SPEC;
4193 pub type Opcmtsf = crate::EnumBitfieldStruct<u8, Opcmtsf_SPEC>;
4194 impl Opcmtsf {
4195 #[doc = "Transition completed"]
4196 pub const _0: Self = Self::new(0);
4197
4198 #[doc = "During transition"]
4199 pub const _1: Self = Self::new(1);
4200 }
4201}
4202#[doc(hidden)]
4203#[derive(Copy, Clone, Eq, PartialEq)]
4204pub struct Moscwtcr_SPEC;
4205impl crate::sealed::RegSpec for Moscwtcr_SPEC {
4206 type DataType = u8;
4207}
4208
4209#[doc = "Main Clock Oscillator Wait Control Register"]
4210pub type Moscwtcr = crate::RegValueT<Moscwtcr_SPEC>;
4211
4212impl Moscwtcr {
4213 #[doc = "Main Clock Oscillator Wait Time Setting"]
4214 #[inline(always)]
4215 pub fn msts(
4216 self,
4217 ) -> crate::common::RegisterField<
4218 0,
4219 0xf,
4220 1,
4221 0,
4222 moscwtcr::Msts,
4223 moscwtcr::Msts,
4224 Moscwtcr_SPEC,
4225 crate::common::RW,
4226 > {
4227 crate::common::RegisterField::<
4228 0,
4229 0xf,
4230 1,
4231 0,
4232 moscwtcr::Msts,
4233 moscwtcr::Msts,
4234 Moscwtcr_SPEC,
4235 crate::common::RW,
4236 >::from_register(self, 0)
4237 }
4238}
4239impl ::core::default::Default for Moscwtcr {
4240 #[inline(always)]
4241 fn default() -> Moscwtcr {
4242 <crate::RegValueT<Moscwtcr_SPEC> as RegisterValue<_>>::new(5)
4243 }
4244}
4245pub mod moscwtcr {
4246
4247 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4248 pub struct Msts_SPEC;
4249 pub type Msts = crate::EnumBitfieldStruct<u8, Msts_SPEC>;
4250 impl Msts {
4251 #[doc = "Wait time = 3 cycles (11.4 us)"]
4252 pub const _0_X_0: Self = Self::new(0);
4253
4254 #[doc = "Wait time = 35 cycles (133.5 us)"]
4255 pub const _0_X_1: Self = Self::new(1);
4256
4257 #[doc = "Wait time = 67 cycles (255.6 us)"]
4258 pub const _0_X_2: Self = Self::new(2);
4259
4260 #[doc = "Wait time = 131 cycles (499.7 us)"]
4261 pub const _0_X_3: Self = Self::new(3);
4262
4263 #[doc = "Wait time = 259 cycles (988.0 us)"]
4264 pub const _0_X_4: Self = Self::new(4);
4265
4266 #[doc = "Wait time = 547 cycles (2086.6 us)"]
4267 pub const _0_X_5: Self = Self::new(5);
4268
4269 #[doc = "Wait time = 1059 cycles (4039.8 us)"]
4270 pub const _0_X_6: Self = Self::new(6);
4271
4272 #[doc = "Wait time = 2147 cycles (8190.2 us)"]
4273 pub const _0_X_7: Self = Self::new(7);
4274
4275 #[doc = "Wait time = 4291 cycles (16368.9 us)"]
4276 pub const _0_X_8: Self = Self::new(8);
4277
4278 #[doc = "Wait time = 8163 cycles (31139.4 us)"]
4279 pub const _0_X_9: Self = Self::new(9);
4280 }
4281}
4282#[doc(hidden)]
4283#[derive(Copy, Clone, Eq, PartialEq)]
4284pub struct Sopccr_SPEC;
4285impl crate::sealed::RegSpec for Sopccr_SPEC {
4286 type DataType = u8;
4287}
4288
4289#[doc = "Sub Operating Power Control Register"]
4290pub type Sopccr = crate::RegValueT<Sopccr_SPEC>;
4291
4292impl Sopccr {
4293 #[doc = "Sub Operating Power Control Mode Select"]
4294 #[inline(always)]
4295 pub fn sopcm(
4296 self,
4297 ) -> crate::common::RegisterField<
4298 0,
4299 0x1,
4300 1,
4301 0,
4302 sopccr::Sopcm,
4303 sopccr::Sopcm,
4304 Sopccr_SPEC,
4305 crate::common::RW,
4306 > {
4307 crate::common::RegisterField::<
4308 0,
4309 0x1,
4310 1,
4311 0,
4312 sopccr::Sopcm,
4313 sopccr::Sopcm,
4314 Sopccr_SPEC,
4315 crate::common::RW,
4316 >::from_register(self, 0)
4317 }
4318
4319 #[doc = "Operating Power Control Mode Transition Status Flag"]
4320 #[inline(always)]
4321 pub fn sopcmtsf(
4322 self,
4323 ) -> crate::common::RegisterField<
4324 4,
4325 0x1,
4326 1,
4327 0,
4328 sopccr::Sopcmtsf,
4329 sopccr::Sopcmtsf,
4330 Sopccr_SPEC,
4331 crate::common::R,
4332 > {
4333 crate::common::RegisterField::<
4334 4,
4335 0x1,
4336 1,
4337 0,
4338 sopccr::Sopcmtsf,
4339 sopccr::Sopcmtsf,
4340 Sopccr_SPEC,
4341 crate::common::R,
4342 >::from_register(self, 0)
4343 }
4344}
4345impl ::core::default::Default for Sopccr {
4346 #[inline(always)]
4347 fn default() -> Sopccr {
4348 <crate::RegValueT<Sopccr_SPEC> as RegisterValue<_>>::new(0)
4349 }
4350}
4351pub mod sopccr {
4352
4353 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4354 pub struct Sopcm_SPEC;
4355 pub type Sopcm = crate::EnumBitfieldStruct<u8, Sopcm_SPEC>;
4356 impl Sopcm {
4357 #[doc = "Other than Subosc-speed mode"]
4358 pub const _0: Self = Self::new(0);
4359
4360 #[doc = "Subosc-speed mode"]
4361 pub const _1: Self = Self::new(1);
4362 }
4363 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4364 pub struct Sopcmtsf_SPEC;
4365 pub type Sopcmtsf = crate::EnumBitfieldStruct<u8, Sopcmtsf_SPEC>;
4366 impl Sopcmtsf {
4367 #[doc = "Transition completed"]
4368 pub const _0: Self = Self::new(0);
4369
4370 #[doc = "During transition"]
4371 pub const _1: Self = Self::new(1);
4372 }
4373}
4374#[doc(hidden)]
4375#[derive(Copy, Clone, Eq, PartialEq)]
4376pub struct Rstsr1_SPEC;
4377impl crate::sealed::RegSpec for Rstsr1_SPEC {
4378 type DataType = u16;
4379}
4380
4381#[doc = "Reset Status Register 1"]
4382pub type Rstsr1 = crate::RegValueT<Rstsr1_SPEC>;
4383
4384impl Rstsr1 {
4385 #[doc = "Independent Watchdog Timer Reset Detect Flag"]
4386 #[inline(always)]
4387 pub fn iwdtrf(
4388 self,
4389 ) -> crate::common::RegisterField<
4390 0,
4391 0x1,
4392 1,
4393 0,
4394 rstsr1::Iwdtrf,
4395 rstsr1::Iwdtrf,
4396 Rstsr1_SPEC,
4397 crate::common::RW,
4398 > {
4399 crate::common::RegisterField::<
4400 0,
4401 0x1,
4402 1,
4403 0,
4404 rstsr1::Iwdtrf,
4405 rstsr1::Iwdtrf,
4406 Rstsr1_SPEC,
4407 crate::common::RW,
4408 >::from_register(self, 0)
4409 }
4410
4411 #[doc = "Watchdog Timer Reset Detect Flag"]
4412 #[inline(always)]
4413 pub fn wdtrf(
4414 self,
4415 ) -> crate::common::RegisterField<
4416 1,
4417 0x1,
4418 1,
4419 0,
4420 rstsr1::Wdtrf,
4421 rstsr1::Wdtrf,
4422 Rstsr1_SPEC,
4423 crate::common::RW,
4424 > {
4425 crate::common::RegisterField::<
4426 1,
4427 0x1,
4428 1,
4429 0,
4430 rstsr1::Wdtrf,
4431 rstsr1::Wdtrf,
4432 Rstsr1_SPEC,
4433 crate::common::RW,
4434 >::from_register(self, 0)
4435 }
4436
4437 #[doc = "Software Reset Detect Flag"]
4438 #[inline(always)]
4439 pub fn swrf(
4440 self,
4441 ) -> crate::common::RegisterField<
4442 2,
4443 0x1,
4444 1,
4445 0,
4446 rstsr1::Swrf,
4447 rstsr1::Swrf,
4448 Rstsr1_SPEC,
4449 crate::common::RW,
4450 > {
4451 crate::common::RegisterField::<
4452 2,
4453 0x1,
4454 1,
4455 0,
4456 rstsr1::Swrf,
4457 rstsr1::Swrf,
4458 Rstsr1_SPEC,
4459 crate::common::RW,
4460 >::from_register(self, 0)
4461 }
4462
4463 #[doc = "SRAM Parity Error Reset Detect Flag"]
4464 #[inline(always)]
4465 pub fn rperf(
4466 self,
4467 ) -> crate::common::RegisterField<
4468 8,
4469 0x1,
4470 1,
4471 0,
4472 rstsr1::Rperf,
4473 rstsr1::Rperf,
4474 Rstsr1_SPEC,
4475 crate::common::RW,
4476 > {
4477 crate::common::RegisterField::<
4478 8,
4479 0x1,
4480 1,
4481 0,
4482 rstsr1::Rperf,
4483 rstsr1::Rperf,
4484 Rstsr1_SPEC,
4485 crate::common::RW,
4486 >::from_register(self, 0)
4487 }
4488
4489 #[doc = "SRAM ECC Error Reset Detect Flag"]
4490 #[inline(always)]
4491 pub fn reerf(
4492 self,
4493 ) -> crate::common::RegisterField<
4494 9,
4495 0x1,
4496 1,
4497 0,
4498 rstsr1::Reerf,
4499 rstsr1::Reerf,
4500 Rstsr1_SPEC,
4501 crate::common::RW,
4502 > {
4503 crate::common::RegisterField::<
4504 9,
4505 0x1,
4506 1,
4507 0,
4508 rstsr1::Reerf,
4509 rstsr1::Reerf,
4510 Rstsr1_SPEC,
4511 crate::common::RW,
4512 >::from_register(self, 0)
4513 }
4514
4515 #[doc = "Bus Master MPU Error Reset Detect Flag"]
4516 #[inline(always)]
4517 pub fn busmrf(
4518 self,
4519 ) -> crate::common::RegisterField<
4520 11,
4521 0x1,
4522 1,
4523 0,
4524 rstsr1::Busmrf,
4525 rstsr1::Busmrf,
4526 Rstsr1_SPEC,
4527 crate::common::RW,
4528 > {
4529 crate::common::RegisterField::<
4530 11,
4531 0x1,
4532 1,
4533 0,
4534 rstsr1::Busmrf,
4535 rstsr1::Busmrf,
4536 Rstsr1_SPEC,
4537 crate::common::RW,
4538 >::from_register(self, 0)
4539 }
4540
4541 #[doc = "TrustZone Error Reset Detect Flag"]
4542 #[inline(always)]
4543 pub fn tzerf(
4544 self,
4545 ) -> crate::common::RegisterField<
4546 13,
4547 0x1,
4548 1,
4549 0,
4550 rstsr1::Tzerf,
4551 rstsr1::Tzerf,
4552 Rstsr1_SPEC,
4553 crate::common::RW,
4554 > {
4555 crate::common::RegisterField::<
4556 13,
4557 0x1,
4558 1,
4559 0,
4560 rstsr1::Tzerf,
4561 rstsr1::Tzerf,
4562 Rstsr1_SPEC,
4563 crate::common::RW,
4564 >::from_register(self, 0)
4565 }
4566
4567 #[doc = "Cache Parity Error Reset Detect Flag"]
4568 #[inline(always)]
4569 pub fn cperf(
4570 self,
4571 ) -> crate::common::RegisterField<
4572 15,
4573 0x1,
4574 1,
4575 0,
4576 rstsr1::Cperf,
4577 rstsr1::Cperf,
4578 Rstsr1_SPEC,
4579 crate::common::RW,
4580 > {
4581 crate::common::RegisterField::<
4582 15,
4583 0x1,
4584 1,
4585 0,
4586 rstsr1::Cperf,
4587 rstsr1::Cperf,
4588 Rstsr1_SPEC,
4589 crate::common::RW,
4590 >::from_register(self, 0)
4591 }
4592}
4593impl ::core::default::Default for Rstsr1 {
4594 #[inline(always)]
4595 fn default() -> Rstsr1 {
4596 <crate::RegValueT<Rstsr1_SPEC> as RegisterValue<_>>::new(0)
4597 }
4598}
4599pub mod rstsr1 {
4600
4601 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4602 pub struct Iwdtrf_SPEC;
4603 pub type Iwdtrf = crate::EnumBitfieldStruct<u8, Iwdtrf_SPEC>;
4604 impl Iwdtrf {
4605 #[doc = "Independent watchdog timer reset not detected"]
4606 pub const _0: Self = Self::new(0);
4607
4608 #[doc = "Independent watchdog timer reset detected"]
4609 pub const _1: Self = Self::new(1);
4610 }
4611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4612 pub struct Wdtrf_SPEC;
4613 pub type Wdtrf = crate::EnumBitfieldStruct<u8, Wdtrf_SPEC>;
4614 impl Wdtrf {
4615 #[doc = "Watchdog timer reset not detected"]
4616 pub const _0: Self = Self::new(0);
4617
4618 #[doc = "Watchdog timer reset detected"]
4619 pub const _1: Self = Self::new(1);
4620 }
4621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4622 pub struct Swrf_SPEC;
4623 pub type Swrf = crate::EnumBitfieldStruct<u8, Swrf_SPEC>;
4624 impl Swrf {
4625 #[doc = "Software reset not detected"]
4626 pub const _0: Self = Self::new(0);
4627
4628 #[doc = "Software reset detected"]
4629 pub const _1: Self = Self::new(1);
4630 }
4631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4632 pub struct Rperf_SPEC;
4633 pub type Rperf = crate::EnumBitfieldStruct<u8, Rperf_SPEC>;
4634 impl Rperf {
4635 #[doc = "SRAM parity error reset not detected"]
4636 pub const _0: Self = Self::new(0);
4637
4638 #[doc = "SRAM parity error reset detected"]
4639 pub const _1: Self = Self::new(1);
4640 }
4641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4642 pub struct Reerf_SPEC;
4643 pub type Reerf = crate::EnumBitfieldStruct<u8, Reerf_SPEC>;
4644 impl Reerf {
4645 #[doc = "SRAM ECC error reset not detected"]
4646 pub const _0: Self = Self::new(0);
4647
4648 #[doc = "SRAM ECC error reset detected"]
4649 pub const _1: Self = Self::new(1);
4650 }
4651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4652 pub struct Busmrf_SPEC;
4653 pub type Busmrf = crate::EnumBitfieldStruct<u8, Busmrf_SPEC>;
4654 impl Busmrf {
4655 #[doc = "Bus master MPU error reset not detected"]
4656 pub const _0: Self = Self::new(0);
4657
4658 #[doc = "Bus master MPU error reset detected"]
4659 pub const _1: Self = Self::new(1);
4660 }
4661 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4662 pub struct Tzerf_SPEC;
4663 pub type Tzerf = crate::EnumBitfieldStruct<u8, Tzerf_SPEC>;
4664 impl Tzerf {
4665 #[doc = "TrustZone error reset not detected."]
4666 pub const _0: Self = Self::new(0);
4667
4668 #[doc = "TrustZone error reset detected."]
4669 pub const _1: Self = Self::new(1);
4670 }
4671 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4672 pub struct Cperf_SPEC;
4673 pub type Cperf = crate::EnumBitfieldStruct<u8, Cperf_SPEC>;
4674 impl Cperf {
4675 #[doc = "Cache Parity error reset not detected."]
4676 pub const _0: Self = Self::new(0);
4677
4678 #[doc = "Cache Parity error reset detected."]
4679 pub const _1: Self = Self::new(1);
4680 }
4681}
4682#[doc(hidden)]
4683#[derive(Copy, Clone, Eq, PartialEq)]
4684pub struct Lvd1Cr1_SPEC;
4685impl crate::sealed::RegSpec for Lvd1Cr1_SPEC {
4686 type DataType = u8;
4687}
4688
4689#[doc = "Voltage Monitor 1 Circuit Control Register"]
4690pub type Lvd1Cr1 = crate::RegValueT<Lvd1Cr1_SPEC>;
4691
4692impl Lvd1Cr1 {
4693 #[doc = "Voltage Monitor 1 Interrupt Generation Condition Select"]
4694 #[inline(always)]
4695 pub fn idtsel(
4696 self,
4697 ) -> crate::common::RegisterField<
4698 0,
4699 0x3,
4700 1,
4701 0,
4702 lvd1cr1::Idtsel,
4703 lvd1cr1::Idtsel,
4704 Lvd1Cr1_SPEC,
4705 crate::common::RW,
4706 > {
4707 crate::common::RegisterField::<
4708 0,
4709 0x3,
4710 1,
4711 0,
4712 lvd1cr1::Idtsel,
4713 lvd1cr1::Idtsel,
4714 Lvd1Cr1_SPEC,
4715 crate::common::RW,
4716 >::from_register(self, 0)
4717 }
4718
4719 #[doc = "Voltage Monitor 1 Interrupt Type Select"]
4720 #[inline(always)]
4721 pub fn irqsel(
4722 self,
4723 ) -> crate::common::RegisterField<
4724 2,
4725 0x1,
4726 1,
4727 0,
4728 lvd1cr1::Irqsel,
4729 lvd1cr1::Irqsel,
4730 Lvd1Cr1_SPEC,
4731 crate::common::RW,
4732 > {
4733 crate::common::RegisterField::<
4734 2,
4735 0x1,
4736 1,
4737 0,
4738 lvd1cr1::Irqsel,
4739 lvd1cr1::Irqsel,
4740 Lvd1Cr1_SPEC,
4741 crate::common::RW,
4742 >::from_register(self, 0)
4743 }
4744}
4745impl ::core::default::Default for Lvd1Cr1 {
4746 #[inline(always)]
4747 fn default() -> Lvd1Cr1 {
4748 <crate::RegValueT<Lvd1Cr1_SPEC> as RegisterValue<_>>::new(1)
4749 }
4750}
4751pub mod lvd1cr1 {
4752
4753 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4754 pub struct Idtsel_SPEC;
4755 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
4756 impl Idtsel {
4757 #[doc = "When VCC >= Vdet1 (rise) is detected"]
4758 pub const _00: Self = Self::new(0);
4759
4760 #[doc = "When VCC < Vdet1 (fall) is detected"]
4761 pub const _01: Self = Self::new(1);
4762
4763 #[doc = "When fall and rise are detected"]
4764 pub const _10: Self = Self::new(2);
4765
4766 #[doc = "Settings prohibited"]
4767 pub const _11: Self = Self::new(3);
4768 }
4769 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4770 pub struct Irqsel_SPEC;
4771 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
4772 impl Irqsel {
4773 #[doc = "Non-maskable interrupt"]
4774 pub const _0: Self = Self::new(0);
4775
4776 #[doc = "Maskable interrupt"]
4777 pub const _1: Self = Self::new(1);
4778 }
4779}
4780#[doc(hidden)]
4781#[derive(Copy, Clone, Eq, PartialEq)]
4782pub struct Lvd1Sr_SPEC;
4783impl crate::sealed::RegSpec for Lvd1Sr_SPEC {
4784 type DataType = u8;
4785}
4786
4787#[doc = "Voltage Monitor 1 Circuit Status Register"]
4788pub type Lvd1Sr = crate::RegValueT<Lvd1Sr_SPEC>;
4789
4790impl Lvd1Sr {
4791 #[doc = "Voltage Monitor 1 Voltage Variation Detection Flag"]
4792 #[inline(always)]
4793 pub fn det(
4794 self,
4795 ) -> crate::common::RegisterField<
4796 0,
4797 0x1,
4798 1,
4799 0,
4800 lvd1sr::Det,
4801 lvd1sr::Det,
4802 Lvd1Sr_SPEC,
4803 crate::common::RW,
4804 > {
4805 crate::common::RegisterField::<
4806 0,
4807 0x1,
4808 1,
4809 0,
4810 lvd1sr::Det,
4811 lvd1sr::Det,
4812 Lvd1Sr_SPEC,
4813 crate::common::RW,
4814 >::from_register(self, 0)
4815 }
4816
4817 #[doc = "Voltage Monitor 1 Signal Monitor Flag"]
4818 #[inline(always)]
4819 pub fn mon(
4820 self,
4821 ) -> crate::common::RegisterField<
4822 1,
4823 0x1,
4824 1,
4825 0,
4826 lvd1sr::Mon,
4827 lvd1sr::Mon,
4828 Lvd1Sr_SPEC,
4829 crate::common::R,
4830 > {
4831 crate::common::RegisterField::<
4832 1,
4833 0x1,
4834 1,
4835 0,
4836 lvd1sr::Mon,
4837 lvd1sr::Mon,
4838 Lvd1Sr_SPEC,
4839 crate::common::R,
4840 >::from_register(self, 0)
4841 }
4842}
4843impl ::core::default::Default for Lvd1Sr {
4844 #[inline(always)]
4845 fn default() -> Lvd1Sr {
4846 <crate::RegValueT<Lvd1Sr_SPEC> as RegisterValue<_>>::new(2)
4847 }
4848}
4849pub mod lvd1sr {
4850
4851 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4852 pub struct Det_SPEC;
4853 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
4854 impl Det {
4855 #[doc = "Not detected"]
4856 pub const _0: Self = Self::new(0);
4857
4858 #[doc = "Vdet1 crossing is detected"]
4859 pub const _1: Self = Self::new(1);
4860 }
4861 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4862 pub struct Mon_SPEC;
4863 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
4864 impl Mon {
4865 #[doc = "VCC < Vdet1"]
4866 pub const _0: Self = Self::new(0);
4867
4868 #[doc = "VCC >= Vdet1 or MON is disabled"]
4869 pub const _1: Self = Self::new(1);
4870 }
4871}
4872#[doc(hidden)]
4873#[derive(Copy, Clone, Eq, PartialEq)]
4874pub struct Lvd2Cr1_SPEC;
4875impl crate::sealed::RegSpec for Lvd2Cr1_SPEC {
4876 type DataType = u8;
4877}
4878
4879#[doc = "Voltage Monitor 2 Circuit Control Register 1"]
4880pub type Lvd2Cr1 = crate::RegValueT<Lvd2Cr1_SPEC>;
4881
4882impl Lvd2Cr1 {
4883 #[doc = "Voltage Monitor 2 Interrupt Generation Condition Select"]
4884 #[inline(always)]
4885 pub fn idtsel(
4886 self,
4887 ) -> crate::common::RegisterField<
4888 0,
4889 0x3,
4890 1,
4891 0,
4892 lvd2cr1::Idtsel,
4893 lvd2cr1::Idtsel,
4894 Lvd2Cr1_SPEC,
4895 crate::common::RW,
4896 > {
4897 crate::common::RegisterField::<
4898 0,
4899 0x3,
4900 1,
4901 0,
4902 lvd2cr1::Idtsel,
4903 lvd2cr1::Idtsel,
4904 Lvd2Cr1_SPEC,
4905 crate::common::RW,
4906 >::from_register(self, 0)
4907 }
4908
4909 #[doc = "Voltage Monitor 2 Interrupt Type Select"]
4910 #[inline(always)]
4911 pub fn irqsel(
4912 self,
4913 ) -> crate::common::RegisterField<
4914 2,
4915 0x1,
4916 1,
4917 0,
4918 lvd2cr1::Irqsel,
4919 lvd2cr1::Irqsel,
4920 Lvd2Cr1_SPEC,
4921 crate::common::RW,
4922 > {
4923 crate::common::RegisterField::<
4924 2,
4925 0x1,
4926 1,
4927 0,
4928 lvd2cr1::Irqsel,
4929 lvd2cr1::Irqsel,
4930 Lvd2Cr1_SPEC,
4931 crate::common::RW,
4932 >::from_register(self, 0)
4933 }
4934}
4935impl ::core::default::Default for Lvd2Cr1 {
4936 #[inline(always)]
4937 fn default() -> Lvd2Cr1 {
4938 <crate::RegValueT<Lvd2Cr1_SPEC> as RegisterValue<_>>::new(1)
4939 }
4940}
4941pub mod lvd2cr1 {
4942
4943 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4944 pub struct Idtsel_SPEC;
4945 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
4946 impl Idtsel {
4947 #[doc = "When VCC>= Vdet2 (rise) is detected"]
4948 pub const _00: Self = Self::new(0);
4949
4950 #[doc = "When VCC < Vdet2 (fall) is detected"]
4951 pub const _01: Self = Self::new(1);
4952
4953 #[doc = "When fall and rise are detected"]
4954 pub const _10: Self = Self::new(2);
4955
4956 #[doc = "Settings prohibited"]
4957 pub const _11: Self = Self::new(3);
4958 }
4959 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4960 pub struct Irqsel_SPEC;
4961 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
4962 impl Irqsel {
4963 #[doc = "Non-maskable interrupt"]
4964 pub const _0: Self = Self::new(0);
4965
4966 #[doc = "Maskable interrupt"]
4967 pub const _1: Self = Self::new(1);
4968 }
4969}
4970#[doc(hidden)]
4971#[derive(Copy, Clone, Eq, PartialEq)]
4972pub struct Lvd2Sr_SPEC;
4973impl crate::sealed::RegSpec for Lvd2Sr_SPEC {
4974 type DataType = u8;
4975}
4976
4977#[doc = "Voltage Monitor 2 Circuit Status Register"]
4978pub type Lvd2Sr = crate::RegValueT<Lvd2Sr_SPEC>;
4979
4980impl Lvd2Sr {
4981 #[doc = "Voltage Monitor 2 Voltage Variation Detection Flag"]
4982 #[inline(always)]
4983 pub fn det(
4984 self,
4985 ) -> crate::common::RegisterField<
4986 0,
4987 0x1,
4988 1,
4989 0,
4990 lvd2sr::Det,
4991 lvd2sr::Det,
4992 Lvd2Sr_SPEC,
4993 crate::common::RW,
4994 > {
4995 crate::common::RegisterField::<
4996 0,
4997 0x1,
4998 1,
4999 0,
5000 lvd2sr::Det,
5001 lvd2sr::Det,
5002 Lvd2Sr_SPEC,
5003 crate::common::RW,
5004 >::from_register(self, 0)
5005 }
5006
5007 #[doc = "Voltage Monitor 2 Signal Monitor Flag"]
5008 #[inline(always)]
5009 pub fn mon(
5010 self,
5011 ) -> crate::common::RegisterField<
5012 1,
5013 0x1,
5014 1,
5015 0,
5016 lvd2sr::Mon,
5017 lvd2sr::Mon,
5018 Lvd2Sr_SPEC,
5019 crate::common::R,
5020 > {
5021 crate::common::RegisterField::<
5022 1,
5023 0x1,
5024 1,
5025 0,
5026 lvd2sr::Mon,
5027 lvd2sr::Mon,
5028 Lvd2Sr_SPEC,
5029 crate::common::R,
5030 >::from_register(self, 0)
5031 }
5032}
5033impl ::core::default::Default for Lvd2Sr {
5034 #[inline(always)]
5035 fn default() -> Lvd2Sr {
5036 <crate::RegValueT<Lvd2Sr_SPEC> as RegisterValue<_>>::new(2)
5037 }
5038}
5039pub mod lvd2sr {
5040
5041 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5042 pub struct Det_SPEC;
5043 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
5044 impl Det {
5045 #[doc = "Not detected"]
5046 pub const _0: Self = Self::new(0);
5047
5048 #[doc = "Vdet2 crossing is detected"]
5049 pub const _1: Self = Self::new(1);
5050 }
5051 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5052 pub struct Mon_SPEC;
5053 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
5054 impl Mon {
5055 #[doc = "VCC < Vdet2"]
5056 pub const _0: Self = Self::new(0);
5057
5058 #[doc = "VCC>= Vdet2 or MON is disabled"]
5059 pub const _1: Self = Self::new(1);
5060 }
5061}
5062#[doc(hidden)]
5063#[derive(Copy, Clone, Eq, PartialEq)]
5064pub struct Cgfsar_SPEC;
5065impl crate::sealed::RegSpec for Cgfsar_SPEC {
5066 type DataType = u32;
5067}
5068
5069#[doc = "Clock Generation Function Security Attribute Register"]
5070pub type Cgfsar = crate::RegValueT<Cgfsar_SPEC>;
5071
5072impl Cgfsar {
5073 #[doc = "Non Secure Attribute bit 00"]
5074 #[inline(always)]
5075 pub fn nonsec00(
5076 self,
5077 ) -> crate::common::RegisterField<
5078 0,
5079 0x1,
5080 1,
5081 0,
5082 cgfsar::Nonsec00,
5083 cgfsar::Nonsec00,
5084 Cgfsar_SPEC,
5085 crate::common::RW,
5086 > {
5087 crate::common::RegisterField::<
5088 0,
5089 0x1,
5090 1,
5091 0,
5092 cgfsar::Nonsec00,
5093 cgfsar::Nonsec00,
5094 Cgfsar_SPEC,
5095 crate::common::RW,
5096 >::from_register(self, 0)
5097 }
5098
5099 #[doc = "Non Secure Attribute bit 02"]
5100 #[inline(always)]
5101 pub fn nonsec02(
5102 self,
5103 ) -> crate::common::RegisterField<
5104 2,
5105 0x1,
5106 1,
5107 0,
5108 cgfsar::Nonsec02,
5109 cgfsar::Nonsec02,
5110 Cgfsar_SPEC,
5111 crate::common::RW,
5112 > {
5113 crate::common::RegisterField::<
5114 2,
5115 0x1,
5116 1,
5117 0,
5118 cgfsar::Nonsec02,
5119 cgfsar::Nonsec02,
5120 Cgfsar_SPEC,
5121 crate::common::RW,
5122 >::from_register(self, 0)
5123 }
5124
5125 #[doc = "Non Secure Attribute bit 03"]
5126 #[inline(always)]
5127 pub fn nonsec03(
5128 self,
5129 ) -> crate::common::RegisterField<
5130 3,
5131 0x1,
5132 1,
5133 0,
5134 cgfsar::Nonsec03,
5135 cgfsar::Nonsec03,
5136 Cgfsar_SPEC,
5137 crate::common::RW,
5138 > {
5139 crate::common::RegisterField::<
5140 3,
5141 0x1,
5142 1,
5143 0,
5144 cgfsar::Nonsec03,
5145 cgfsar::Nonsec03,
5146 Cgfsar_SPEC,
5147 crate::common::RW,
5148 >::from_register(self, 0)
5149 }
5150
5151 #[doc = "Non Secure Attribute bit 04"]
5152 #[inline(always)]
5153 pub fn nonsec04(
5154 self,
5155 ) -> crate::common::RegisterField<
5156 4,
5157 0x1,
5158 1,
5159 0,
5160 cgfsar::Nonsec04,
5161 cgfsar::Nonsec04,
5162 Cgfsar_SPEC,
5163 crate::common::RW,
5164 > {
5165 crate::common::RegisterField::<
5166 4,
5167 0x1,
5168 1,
5169 0,
5170 cgfsar::Nonsec04,
5171 cgfsar::Nonsec04,
5172 Cgfsar_SPEC,
5173 crate::common::RW,
5174 >::from_register(self, 0)
5175 }
5176
5177 #[doc = "Non Secure Attribute bit 05"]
5178 #[inline(always)]
5179 pub fn nonsec05(
5180 self,
5181 ) -> crate::common::RegisterField<
5182 5,
5183 0x1,
5184 1,
5185 0,
5186 cgfsar::Nonsec05,
5187 cgfsar::Nonsec05,
5188 Cgfsar_SPEC,
5189 crate::common::RW,
5190 > {
5191 crate::common::RegisterField::<
5192 5,
5193 0x1,
5194 1,
5195 0,
5196 cgfsar::Nonsec05,
5197 cgfsar::Nonsec05,
5198 Cgfsar_SPEC,
5199 crate::common::RW,
5200 >::from_register(self, 0)
5201 }
5202
5203 #[doc = "Non Secure Attribute bit 06"]
5204 #[inline(always)]
5205 pub fn nonsec06(
5206 self,
5207 ) -> crate::common::RegisterField<
5208 6,
5209 0x1,
5210 1,
5211 0,
5212 cgfsar::Nonsec06,
5213 cgfsar::Nonsec06,
5214 Cgfsar_SPEC,
5215 crate::common::RW,
5216 > {
5217 crate::common::RegisterField::<
5218 6,
5219 0x1,
5220 1,
5221 0,
5222 cgfsar::Nonsec06,
5223 cgfsar::Nonsec06,
5224 Cgfsar_SPEC,
5225 crate::common::RW,
5226 >::from_register(self, 0)
5227 }
5228
5229 #[doc = "Non Secure Attribute bit 07"]
5230 #[inline(always)]
5231 pub fn nonsec07(
5232 self,
5233 ) -> crate::common::RegisterField<
5234 7,
5235 0x1,
5236 1,
5237 0,
5238 cgfsar::Nonsec07,
5239 cgfsar::Nonsec07,
5240 Cgfsar_SPEC,
5241 crate::common::RW,
5242 > {
5243 crate::common::RegisterField::<
5244 7,
5245 0x1,
5246 1,
5247 0,
5248 cgfsar::Nonsec07,
5249 cgfsar::Nonsec07,
5250 Cgfsar_SPEC,
5251 crate::common::RW,
5252 >::from_register(self, 0)
5253 }
5254
5255 #[doc = "Non Secure Attribute bit 08"]
5256 #[inline(always)]
5257 pub fn nonsec08(
5258 self,
5259 ) -> crate::common::RegisterField<
5260 8,
5261 0x1,
5262 1,
5263 0,
5264 cgfsar::Nonsec08,
5265 cgfsar::Nonsec08,
5266 Cgfsar_SPEC,
5267 crate::common::RW,
5268 > {
5269 crate::common::RegisterField::<
5270 8,
5271 0x1,
5272 1,
5273 0,
5274 cgfsar::Nonsec08,
5275 cgfsar::Nonsec08,
5276 Cgfsar_SPEC,
5277 crate::common::RW,
5278 >::from_register(self, 0)
5279 }
5280
5281 #[doc = "Non Secure Attribute bit 11"]
5282 #[inline(always)]
5283 pub fn nonsec11(
5284 self,
5285 ) -> crate::common::RegisterField<
5286 11,
5287 0x1,
5288 1,
5289 0,
5290 cgfsar::Nonsec11,
5291 cgfsar::Nonsec11,
5292 Cgfsar_SPEC,
5293 crate::common::RW,
5294 > {
5295 crate::common::RegisterField::<
5296 11,
5297 0x1,
5298 1,
5299 0,
5300 cgfsar::Nonsec11,
5301 cgfsar::Nonsec11,
5302 Cgfsar_SPEC,
5303 crate::common::RW,
5304 >::from_register(self, 0)
5305 }
5306
5307 #[doc = "Non Secure Attribute bit 16"]
5308 #[inline(always)]
5309 pub fn nonsec16(
5310 self,
5311 ) -> crate::common::RegisterField<
5312 16,
5313 0x1,
5314 1,
5315 0,
5316 cgfsar::Nonsec16,
5317 cgfsar::Nonsec16,
5318 Cgfsar_SPEC,
5319 crate::common::RW,
5320 > {
5321 crate::common::RegisterField::<
5322 16,
5323 0x1,
5324 1,
5325 0,
5326 cgfsar::Nonsec16,
5327 cgfsar::Nonsec16,
5328 Cgfsar_SPEC,
5329 crate::common::RW,
5330 >::from_register(self, 0)
5331 }
5332
5333 #[doc = "Non Secure Attribute bit 18"]
5334 #[inline(always)]
5335 pub fn nonsec18(
5336 self,
5337 ) -> crate::common::RegisterField<
5338 18,
5339 0x1,
5340 1,
5341 0,
5342 cgfsar::Nonsec18,
5343 cgfsar::Nonsec18,
5344 Cgfsar_SPEC,
5345 crate::common::RW,
5346 > {
5347 crate::common::RegisterField::<
5348 18,
5349 0x1,
5350 1,
5351 0,
5352 cgfsar::Nonsec18,
5353 cgfsar::Nonsec18,
5354 Cgfsar_SPEC,
5355 crate::common::RW,
5356 >::from_register(self, 0)
5357 }
5358
5359 #[doc = "Non Secure Attribute bit 20"]
5360 #[inline(always)]
5361 pub fn nonsec20(
5362 self,
5363 ) -> crate::common::RegisterField<
5364 20,
5365 0x1,
5366 1,
5367 0,
5368 cgfsar::Nonsec20,
5369 cgfsar::Nonsec20,
5370 Cgfsar_SPEC,
5371 crate::common::RW,
5372 > {
5373 crate::common::RegisterField::<
5374 20,
5375 0x1,
5376 1,
5377 0,
5378 cgfsar::Nonsec20,
5379 cgfsar::Nonsec20,
5380 Cgfsar_SPEC,
5381 crate::common::RW,
5382 >::from_register(self, 0)
5383 }
5384}
5385impl ::core::default::Default for Cgfsar {
5386 #[inline(always)]
5387 fn default() -> Cgfsar {
5388 <crate::RegValueT<Cgfsar_SPEC> as RegisterValue<_>>::new(4294967295)
5389 }
5390}
5391pub mod cgfsar {
5392
5393 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5394 pub struct Nonsec00_SPEC;
5395 pub type Nonsec00 = crate::EnumBitfieldStruct<u8, Nonsec00_SPEC>;
5396 impl Nonsec00 {
5397 #[doc = "Secure"]
5398 pub const _0: Self = Self::new(0);
5399
5400 #[doc = "Non Secure"]
5401 pub const _1: Self = Self::new(1);
5402 }
5403 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5404 pub struct Nonsec02_SPEC;
5405 pub type Nonsec02 = crate::EnumBitfieldStruct<u8, Nonsec02_SPEC>;
5406 impl Nonsec02 {
5407 #[doc = "Secure"]
5408 pub const _0: Self = Self::new(0);
5409
5410 #[doc = "Non Secure"]
5411 pub const _1: Self = Self::new(1);
5412 }
5413 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5414 pub struct Nonsec03_SPEC;
5415 pub type Nonsec03 = crate::EnumBitfieldStruct<u8, Nonsec03_SPEC>;
5416 impl Nonsec03 {
5417 #[doc = "Secure"]
5418 pub const _0: Self = Self::new(0);
5419
5420 #[doc = "Non Secure"]
5421 pub const _1: Self = Self::new(1);
5422 }
5423 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5424 pub struct Nonsec04_SPEC;
5425 pub type Nonsec04 = crate::EnumBitfieldStruct<u8, Nonsec04_SPEC>;
5426 impl Nonsec04 {
5427 #[doc = "Secure"]
5428 pub const _0: Self = Self::new(0);
5429
5430 #[doc = "Non Secure"]
5431 pub const _1: Self = Self::new(1);
5432 }
5433 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5434 pub struct Nonsec05_SPEC;
5435 pub type Nonsec05 = crate::EnumBitfieldStruct<u8, Nonsec05_SPEC>;
5436 impl Nonsec05 {
5437 #[doc = "Secure"]
5438 pub const _0: Self = Self::new(0);
5439
5440 #[doc = "Non Secure"]
5441 pub const _1: Self = Self::new(1);
5442 }
5443 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5444 pub struct Nonsec06_SPEC;
5445 pub type Nonsec06 = crate::EnumBitfieldStruct<u8, Nonsec06_SPEC>;
5446 impl Nonsec06 {
5447 #[doc = "Secure"]
5448 pub const _0: Self = Self::new(0);
5449
5450 #[doc = "Non Secure"]
5451 pub const _1: Self = Self::new(1);
5452 }
5453 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5454 pub struct Nonsec07_SPEC;
5455 pub type Nonsec07 = crate::EnumBitfieldStruct<u8, Nonsec07_SPEC>;
5456 impl Nonsec07 {
5457 #[doc = "Secure"]
5458 pub const _0: Self = Self::new(0);
5459
5460 #[doc = "Non Secure"]
5461 pub const _1: Self = Self::new(1);
5462 }
5463 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5464 pub struct Nonsec08_SPEC;
5465 pub type Nonsec08 = crate::EnumBitfieldStruct<u8, Nonsec08_SPEC>;
5466 impl Nonsec08 {
5467 #[doc = "Secure"]
5468 pub const _0: Self = Self::new(0);
5469
5470 #[doc = "Non Secure"]
5471 pub const _1: Self = Self::new(1);
5472 }
5473 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5474 pub struct Nonsec11_SPEC;
5475 pub type Nonsec11 = crate::EnumBitfieldStruct<u8, Nonsec11_SPEC>;
5476 impl Nonsec11 {
5477 #[doc = "Secure"]
5478 pub const _0: Self = Self::new(0);
5479
5480 #[doc = "Non Secure"]
5481 pub const _1: Self = Self::new(1);
5482 }
5483 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5484 pub struct Nonsec16_SPEC;
5485 pub type Nonsec16 = crate::EnumBitfieldStruct<u8, Nonsec16_SPEC>;
5486 impl Nonsec16 {
5487 #[doc = "Secure"]
5488 pub const _0: Self = Self::new(0);
5489
5490 #[doc = "Non Secure"]
5491 pub const _1: Self = Self::new(1);
5492 }
5493 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5494 pub struct Nonsec18_SPEC;
5495 pub type Nonsec18 = crate::EnumBitfieldStruct<u8, Nonsec18_SPEC>;
5496 impl Nonsec18 {
5497 #[doc = "Secure"]
5498 pub const _0: Self = Self::new(0);
5499
5500 #[doc = "Non Secure"]
5501 pub const _1: Self = Self::new(1);
5502 }
5503 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5504 pub struct Nonsec20_SPEC;
5505 pub type Nonsec20 = crate::EnumBitfieldStruct<u8, Nonsec20_SPEC>;
5506 impl Nonsec20 {
5507 #[doc = "Secure"]
5508 pub const _0: Self = Self::new(0);
5509
5510 #[doc = "Non Secure"]
5511 pub const _1: Self = Self::new(1);
5512 }
5513}
5514#[doc(hidden)]
5515#[derive(Copy, Clone, Eq, PartialEq)]
5516pub struct Rstsar_SPEC;
5517impl crate::sealed::RegSpec for Rstsar_SPEC {
5518 type DataType = u32;
5519}
5520
5521#[doc = "Reset Security Attribution Register"]
5522pub type Rstsar = crate::RegValueT<Rstsar_SPEC>;
5523
5524impl Rstsar {
5525 #[doc = "Non Secure Attribute bit 0"]
5526 #[inline(always)]
5527 pub fn nonsec0(
5528 self,
5529 ) -> crate::common::RegisterField<
5530 0,
5531 0x1,
5532 1,
5533 0,
5534 rstsar::Nonsec0,
5535 rstsar::Nonsec0,
5536 Rstsar_SPEC,
5537 crate::common::RW,
5538 > {
5539 crate::common::RegisterField::<
5540 0,
5541 0x1,
5542 1,
5543 0,
5544 rstsar::Nonsec0,
5545 rstsar::Nonsec0,
5546 Rstsar_SPEC,
5547 crate::common::RW,
5548 >::from_register(self, 0)
5549 }
5550
5551 #[doc = "Non Secure Attribute bit 1"]
5552 #[inline(always)]
5553 pub fn nonsec1(
5554 self,
5555 ) -> crate::common::RegisterField<
5556 1,
5557 0x1,
5558 1,
5559 0,
5560 rstsar::Nonsec1,
5561 rstsar::Nonsec1,
5562 Rstsar_SPEC,
5563 crate::common::RW,
5564 > {
5565 crate::common::RegisterField::<
5566 1,
5567 0x1,
5568 1,
5569 0,
5570 rstsar::Nonsec1,
5571 rstsar::Nonsec1,
5572 Rstsar_SPEC,
5573 crate::common::RW,
5574 >::from_register(self, 0)
5575 }
5576
5577 #[doc = "Non Secure Attribute bit 2"]
5578 #[inline(always)]
5579 pub fn nonsec2(
5580 self,
5581 ) -> crate::common::RegisterField<
5582 2,
5583 0x1,
5584 1,
5585 0,
5586 rstsar::Nonsec2,
5587 rstsar::Nonsec2,
5588 Rstsar_SPEC,
5589 crate::common::RW,
5590 > {
5591 crate::common::RegisterField::<
5592 2,
5593 0x1,
5594 1,
5595 0,
5596 rstsar::Nonsec2,
5597 rstsar::Nonsec2,
5598 Rstsar_SPEC,
5599 crate::common::RW,
5600 >::from_register(self, 0)
5601 }
5602}
5603impl ::core::default::Default for Rstsar {
5604 #[inline(always)]
5605 fn default() -> Rstsar {
5606 <crate::RegValueT<Rstsar_SPEC> as RegisterValue<_>>::new(4294967295)
5607 }
5608}
5609pub mod rstsar {
5610
5611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5612 pub struct Nonsec0_SPEC;
5613 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
5614 impl Nonsec0 {
5615 #[doc = "Secure"]
5616 pub const _0: Self = Self::new(0);
5617
5618 #[doc = "Non Secure"]
5619 pub const _1: Self = Self::new(1);
5620 }
5621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5622 pub struct Nonsec1_SPEC;
5623 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
5624 impl Nonsec1 {
5625 #[doc = "Secure"]
5626 pub const _0: Self = Self::new(0);
5627
5628 #[doc = "Non Secure"]
5629 pub const _1: Self = Self::new(1);
5630 }
5631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5632 pub struct Nonsec2_SPEC;
5633 pub type Nonsec2 = crate::EnumBitfieldStruct<u8, Nonsec2_SPEC>;
5634 impl Nonsec2 {
5635 #[doc = "Secure"]
5636 pub const _0: Self = Self::new(0);
5637
5638 #[doc = "Non Secure"]
5639 pub const _1: Self = Self::new(1);
5640 }
5641}
5642#[doc(hidden)]
5643#[derive(Copy, Clone, Eq, PartialEq)]
5644pub struct Lpmsar_SPEC;
5645impl crate::sealed::RegSpec for Lpmsar_SPEC {
5646 type DataType = u32;
5647}
5648
5649#[doc = "Low Power Mode Security Attribution Register"]
5650pub type Lpmsar = crate::RegValueT<Lpmsar_SPEC>;
5651
5652impl Lpmsar {
5653 #[doc = "Non Secure Attribute bit 0"]
5654 #[inline(always)]
5655 pub fn nonsec0(
5656 self,
5657 ) -> crate::common::RegisterField<
5658 0,
5659 0x1,
5660 1,
5661 0,
5662 lpmsar::Nonsec0,
5663 lpmsar::Nonsec0,
5664 Lpmsar_SPEC,
5665 crate::common::RW,
5666 > {
5667 crate::common::RegisterField::<
5668 0,
5669 0x1,
5670 1,
5671 0,
5672 lpmsar::Nonsec0,
5673 lpmsar::Nonsec0,
5674 Lpmsar_SPEC,
5675 crate::common::RW,
5676 >::from_register(self, 0)
5677 }
5678
5679 #[doc = "Non Secure Attribute bit 2"]
5680 #[inline(always)]
5681 pub fn nonsec2(
5682 self,
5683 ) -> crate::common::RegisterField<
5684 2,
5685 0x1,
5686 1,
5687 0,
5688 lpmsar::Nonsec2,
5689 lpmsar::Nonsec2,
5690 Lpmsar_SPEC,
5691 crate::common::RW,
5692 > {
5693 crate::common::RegisterField::<
5694 2,
5695 0x1,
5696 1,
5697 0,
5698 lpmsar::Nonsec2,
5699 lpmsar::Nonsec2,
5700 Lpmsar_SPEC,
5701 crate::common::RW,
5702 >::from_register(self, 0)
5703 }
5704
5705 #[doc = "Non Secure Attribute bit 4"]
5706 #[inline(always)]
5707 pub fn nonsec4(
5708 self,
5709 ) -> crate::common::RegisterField<
5710 4,
5711 0x1,
5712 1,
5713 0,
5714 lpmsar::Nonsec4,
5715 lpmsar::Nonsec4,
5716 Lpmsar_SPEC,
5717 crate::common::RW,
5718 > {
5719 crate::common::RegisterField::<
5720 4,
5721 0x1,
5722 1,
5723 0,
5724 lpmsar::Nonsec4,
5725 lpmsar::Nonsec4,
5726 Lpmsar_SPEC,
5727 crate::common::RW,
5728 >::from_register(self, 0)
5729 }
5730
5731 #[doc = "Non Secure Attribute bit 8"]
5732 #[inline(always)]
5733 pub fn nonsec8(
5734 self,
5735 ) -> crate::common::RegisterField<
5736 8,
5737 0x1,
5738 1,
5739 0,
5740 lpmsar::Nonsec8,
5741 lpmsar::Nonsec8,
5742 Lpmsar_SPEC,
5743 crate::common::RW,
5744 > {
5745 crate::common::RegisterField::<
5746 8,
5747 0x1,
5748 1,
5749 0,
5750 lpmsar::Nonsec8,
5751 lpmsar::Nonsec8,
5752 Lpmsar_SPEC,
5753 crate::common::RW,
5754 >::from_register(self, 0)
5755 }
5756
5757 #[doc = "Non Secure Attribute bit 9"]
5758 #[inline(always)]
5759 pub fn nonsec9(
5760 self,
5761 ) -> crate::common::RegisterField<
5762 9,
5763 0x1,
5764 1,
5765 0,
5766 lpmsar::Nonsec9,
5767 lpmsar::Nonsec9,
5768 Lpmsar_SPEC,
5769 crate::common::RW,
5770 > {
5771 crate::common::RegisterField::<
5772 9,
5773 0x1,
5774 1,
5775 0,
5776 lpmsar::Nonsec9,
5777 lpmsar::Nonsec9,
5778 Lpmsar_SPEC,
5779 crate::common::RW,
5780 >::from_register(self, 0)
5781 }
5782}
5783impl ::core::default::Default for Lpmsar {
5784 #[inline(always)]
5785 fn default() -> Lpmsar {
5786 <crate::RegValueT<Lpmsar_SPEC> as RegisterValue<_>>::new(4294967295)
5787 }
5788}
5789pub mod lpmsar {
5790
5791 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5792 pub struct Nonsec0_SPEC;
5793 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
5794 impl Nonsec0 {
5795 #[doc = "Secure"]
5796 pub const _0: Self = Self::new(0);
5797
5798 #[doc = "Non Secure"]
5799 pub const _1: Self = Self::new(1);
5800 }
5801 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5802 pub struct Nonsec2_SPEC;
5803 pub type Nonsec2 = crate::EnumBitfieldStruct<u8, Nonsec2_SPEC>;
5804 impl Nonsec2 {
5805 #[doc = "Secure"]
5806 pub const _0: Self = Self::new(0);
5807
5808 #[doc = "Non Secure"]
5809 pub const _1: Self = Self::new(1);
5810 }
5811 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5812 pub struct Nonsec4_SPEC;
5813 pub type Nonsec4 = crate::EnumBitfieldStruct<u8, Nonsec4_SPEC>;
5814 impl Nonsec4 {
5815 #[doc = "Secure"]
5816 pub const _0: Self = Self::new(0);
5817
5818 #[doc = "Non Secure"]
5819 pub const _1: Self = Self::new(1);
5820 }
5821 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5822 pub struct Nonsec8_SPEC;
5823 pub type Nonsec8 = crate::EnumBitfieldStruct<u8, Nonsec8_SPEC>;
5824 impl Nonsec8 {
5825 #[doc = "Secure"]
5826 pub const _0: Self = Self::new(0);
5827
5828 #[doc = "Non Secure"]
5829 pub const _1: Self = Self::new(1);
5830 }
5831 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5832 pub struct Nonsec9_SPEC;
5833 pub type Nonsec9 = crate::EnumBitfieldStruct<u8, Nonsec9_SPEC>;
5834 impl Nonsec9 {
5835 #[doc = "Secure"]
5836 pub const _0: Self = Self::new(0);
5837
5838 #[doc = "Non Secure"]
5839 pub const _1: Self = Self::new(1);
5840 }
5841}
5842#[doc(hidden)]
5843#[derive(Copy, Clone, Eq, PartialEq)]
5844pub struct Lvdsar_SPEC;
5845impl crate::sealed::RegSpec for Lvdsar_SPEC {
5846 type DataType = u32;
5847}
5848
5849#[doc = "Low Voltage Detection Security Attribution Register"]
5850pub type Lvdsar = crate::RegValueT<Lvdsar_SPEC>;
5851
5852impl Lvdsar {
5853 #[doc = "Non Secure Attribute bit 0"]
5854 #[inline(always)]
5855 pub fn nonsec0(
5856 self,
5857 ) -> crate::common::RegisterField<
5858 0,
5859 0x1,
5860 1,
5861 0,
5862 lvdsar::Nonsec0,
5863 lvdsar::Nonsec0,
5864 Lvdsar_SPEC,
5865 crate::common::RW,
5866 > {
5867 crate::common::RegisterField::<
5868 0,
5869 0x1,
5870 1,
5871 0,
5872 lvdsar::Nonsec0,
5873 lvdsar::Nonsec0,
5874 Lvdsar_SPEC,
5875 crate::common::RW,
5876 >::from_register(self, 0)
5877 }
5878
5879 #[doc = "Non Secure Attribute bit 1"]
5880 #[inline(always)]
5881 pub fn nonsec1(
5882 self,
5883 ) -> crate::common::RegisterField<
5884 1,
5885 0x1,
5886 1,
5887 0,
5888 lvdsar::Nonsec1,
5889 lvdsar::Nonsec1,
5890 Lvdsar_SPEC,
5891 crate::common::RW,
5892 > {
5893 crate::common::RegisterField::<
5894 1,
5895 0x1,
5896 1,
5897 0,
5898 lvdsar::Nonsec1,
5899 lvdsar::Nonsec1,
5900 Lvdsar_SPEC,
5901 crate::common::RW,
5902 >::from_register(self, 0)
5903 }
5904}
5905impl ::core::default::Default for Lvdsar {
5906 #[inline(always)]
5907 fn default() -> Lvdsar {
5908 <crate::RegValueT<Lvdsar_SPEC> as RegisterValue<_>>::new(4294967295)
5909 }
5910}
5911pub mod lvdsar {
5912
5913 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5914 pub struct Nonsec0_SPEC;
5915 pub type Nonsec0 = crate::EnumBitfieldStruct<u8, Nonsec0_SPEC>;
5916 impl Nonsec0 {
5917 #[doc = "Secure"]
5918 pub const _0: Self = Self::new(0);
5919
5920 #[doc = "Non Secure"]
5921 pub const _1: Self = Self::new(1);
5922 }
5923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5924 pub struct Nonsec1_SPEC;
5925 pub type Nonsec1 = crate::EnumBitfieldStruct<u8, Nonsec1_SPEC>;
5926 impl Nonsec1 {
5927 #[doc = "Secure"]
5928 pub const _0: Self = Self::new(0);
5929
5930 #[doc = "Non Secure"]
5931 pub const _1: Self = Self::new(1);
5932 }
5933}
5934#[doc(hidden)]
5935#[derive(Copy, Clone, Eq, PartialEq)]
5936pub struct Dpfsar_SPEC;
5937impl crate::sealed::RegSpec for Dpfsar_SPEC {
5938 type DataType = u32;
5939}
5940
5941#[doc = "Deep Standby Interrupt Factor Security Attribution Register"]
5942pub type Dpfsar = crate::RegValueT<Dpfsar_SPEC>;
5943
5944impl Dpfsar {
5945 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 0"]
5946 #[inline(always)]
5947 pub fn dpfsa0(
5948 self,
5949 ) -> crate::common::RegisterField<
5950 0,
5951 0x1,
5952 1,
5953 0,
5954 dpfsar::Dpfsa0,
5955 dpfsar::Dpfsa0,
5956 Dpfsar_SPEC,
5957 crate::common::RW,
5958 > {
5959 crate::common::RegisterField::<
5960 0,
5961 0x1,
5962 1,
5963 0,
5964 dpfsar::Dpfsa0,
5965 dpfsar::Dpfsa0,
5966 Dpfsar_SPEC,
5967 crate::common::RW,
5968 >::from_register(self, 0)
5969 }
5970
5971 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 1"]
5972 #[inline(always)]
5973 pub fn dpfsa1(
5974 self,
5975 ) -> crate::common::RegisterField<
5976 1,
5977 0x1,
5978 1,
5979 0,
5980 dpfsar::Dpfsa1,
5981 dpfsar::Dpfsa1,
5982 Dpfsar_SPEC,
5983 crate::common::RW,
5984 > {
5985 crate::common::RegisterField::<
5986 1,
5987 0x1,
5988 1,
5989 0,
5990 dpfsar::Dpfsa1,
5991 dpfsar::Dpfsa1,
5992 Dpfsar_SPEC,
5993 crate::common::RW,
5994 >::from_register(self, 0)
5995 }
5996
5997 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
5998 #[inline(always)]
5999 pub fn dpfsa04(
6000 self,
6001 ) -> crate::common::RegisterField<
6002 4,
6003 0x1,
6004 1,
6005 0,
6006 dpfsar::Dpfsa04,
6007 dpfsar::Dpfsa04,
6008 Dpfsar_SPEC,
6009 crate::common::RW,
6010 > {
6011 crate::common::RegisterField::<
6012 4,
6013 0x1,
6014 1,
6015 0,
6016 dpfsar::Dpfsa04,
6017 dpfsar::Dpfsa04,
6018 Dpfsar_SPEC,
6019 crate::common::RW,
6020 >::from_register(self, 0)
6021 }
6022
6023 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6024 #[inline(always)]
6025 pub fn dpfsa05(
6026 self,
6027 ) -> crate::common::RegisterField<
6028 5,
6029 0x1,
6030 1,
6031 0,
6032 dpfsar::Dpfsa05,
6033 dpfsar::Dpfsa05,
6034 Dpfsar_SPEC,
6035 crate::common::RW,
6036 > {
6037 crate::common::RegisterField::<
6038 5,
6039 0x1,
6040 1,
6041 0,
6042 dpfsar::Dpfsa05,
6043 dpfsar::Dpfsa05,
6044 Dpfsar_SPEC,
6045 crate::common::RW,
6046 >::from_register(self, 0)
6047 }
6048
6049 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6050 #[inline(always)]
6051 pub fn dpfsa06(
6052 self,
6053 ) -> crate::common::RegisterField<
6054 6,
6055 0x1,
6056 1,
6057 0,
6058 dpfsar::Dpfsa06,
6059 dpfsar::Dpfsa06,
6060 Dpfsar_SPEC,
6061 crate::common::RW,
6062 > {
6063 crate::common::RegisterField::<
6064 6,
6065 0x1,
6066 1,
6067 0,
6068 dpfsar::Dpfsa06,
6069 dpfsar::Dpfsa06,
6070 Dpfsar_SPEC,
6071 crate::common::RW,
6072 >::from_register(self, 0)
6073 }
6074
6075 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6076 #[inline(always)]
6077 pub fn dpfsa07(
6078 self,
6079 ) -> crate::common::RegisterField<
6080 7,
6081 0x1,
6082 1,
6083 0,
6084 dpfsar::Dpfsa07,
6085 dpfsar::Dpfsa07,
6086 Dpfsar_SPEC,
6087 crate::common::RW,
6088 > {
6089 crate::common::RegisterField::<
6090 7,
6091 0x1,
6092 1,
6093 0,
6094 dpfsar::Dpfsa07,
6095 dpfsar::Dpfsa07,
6096 Dpfsar_SPEC,
6097 crate::common::RW,
6098 >::from_register(self, 0)
6099 }
6100
6101 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6102 #[inline(always)]
6103 pub fn dpfsa08(
6104 self,
6105 ) -> crate::common::RegisterField<
6106 8,
6107 0x1,
6108 1,
6109 0,
6110 dpfsar::Dpfsa08,
6111 dpfsar::Dpfsa08,
6112 Dpfsar_SPEC,
6113 crate::common::RW,
6114 > {
6115 crate::common::RegisterField::<
6116 8,
6117 0x1,
6118 1,
6119 0,
6120 dpfsar::Dpfsa08,
6121 dpfsar::Dpfsa08,
6122 Dpfsar_SPEC,
6123 crate::common::RW,
6124 >::from_register(self, 0)
6125 }
6126
6127 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6128 #[inline(always)]
6129 pub fn dpfsa09(
6130 self,
6131 ) -> crate::common::RegisterField<
6132 9,
6133 0x1,
6134 1,
6135 0,
6136 dpfsar::Dpfsa09,
6137 dpfsar::Dpfsa09,
6138 Dpfsar_SPEC,
6139 crate::common::RW,
6140 > {
6141 crate::common::RegisterField::<
6142 9,
6143 0x1,
6144 1,
6145 0,
6146 dpfsar::Dpfsa09,
6147 dpfsar::Dpfsa09,
6148 Dpfsar_SPEC,
6149 crate::common::RW,
6150 >::from_register(self, 0)
6151 }
6152
6153 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6154 #[inline(always)]
6155 pub fn dpfsa10(
6156 self,
6157 ) -> crate::common::RegisterField<
6158 10,
6159 0x1,
6160 1,
6161 0,
6162 dpfsar::Dpfsa10,
6163 dpfsar::Dpfsa10,
6164 Dpfsar_SPEC,
6165 crate::common::RW,
6166 > {
6167 crate::common::RegisterField::<
6168 10,
6169 0x1,
6170 1,
6171 0,
6172 dpfsar::Dpfsa10,
6173 dpfsar::Dpfsa10,
6174 Dpfsar_SPEC,
6175 crate::common::RW,
6176 >::from_register(self, 0)
6177 }
6178
6179 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6180 #[inline(always)]
6181 pub fn dpfsa11(
6182 self,
6183 ) -> crate::common::RegisterField<
6184 11,
6185 0x1,
6186 1,
6187 0,
6188 dpfsar::Dpfsa11,
6189 dpfsar::Dpfsa11,
6190 Dpfsar_SPEC,
6191 crate::common::RW,
6192 > {
6193 crate::common::RegisterField::<
6194 11,
6195 0x1,
6196 1,
6197 0,
6198 dpfsar::Dpfsa11,
6199 dpfsar::Dpfsa11,
6200 Dpfsar_SPEC,
6201 crate::common::RW,
6202 >::from_register(self, 0)
6203 }
6204
6205 #[doc = "Deep Standby Interrupt Factor Security Attribute bit n (n = 4 to 12)"]
6206 #[inline(always)]
6207 pub fn dpfsa12(
6208 self,
6209 ) -> crate::common::RegisterField<
6210 12,
6211 0x1,
6212 1,
6213 0,
6214 dpfsar::Dpfsa12,
6215 dpfsar::Dpfsa12,
6216 Dpfsar_SPEC,
6217 crate::common::RW,
6218 > {
6219 crate::common::RegisterField::<
6220 12,
6221 0x1,
6222 1,
6223 0,
6224 dpfsar::Dpfsa12,
6225 dpfsar::Dpfsa12,
6226 Dpfsar_SPEC,
6227 crate::common::RW,
6228 >::from_register(self, 0)
6229 }
6230
6231 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 14"]
6232 #[inline(always)]
6233 pub fn dpfsa14(
6234 self,
6235 ) -> crate::common::RegisterField<
6236 14,
6237 0x1,
6238 1,
6239 0,
6240 dpfsar::Dpfsa14,
6241 dpfsar::Dpfsa14,
6242 Dpfsar_SPEC,
6243 crate::common::RW,
6244 > {
6245 crate::common::RegisterField::<
6246 14,
6247 0x1,
6248 1,
6249 0,
6250 dpfsar::Dpfsa14,
6251 dpfsar::Dpfsa14,
6252 Dpfsar_SPEC,
6253 crate::common::RW,
6254 >::from_register(self, 0)
6255 }
6256
6257 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 16"]
6258 #[inline(always)]
6259 pub fn dpfsa16(
6260 self,
6261 ) -> crate::common::RegisterField<
6262 16,
6263 0x1,
6264 1,
6265 0,
6266 dpfsar::Dpfsa16,
6267 dpfsar::Dpfsa16,
6268 Dpfsar_SPEC,
6269 crate::common::RW,
6270 > {
6271 crate::common::RegisterField::<
6272 16,
6273 0x1,
6274 1,
6275 0,
6276 dpfsar::Dpfsa16,
6277 dpfsar::Dpfsa16,
6278 Dpfsar_SPEC,
6279 crate::common::RW,
6280 >::from_register(self, 0)
6281 }
6282
6283 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 17"]
6284 #[inline(always)]
6285 pub fn dpfsa17(
6286 self,
6287 ) -> crate::common::RegisterField<
6288 17,
6289 0x1,
6290 1,
6291 0,
6292 dpfsar::Dpfsa17,
6293 dpfsar::Dpfsa17,
6294 Dpfsar_SPEC,
6295 crate::common::RW,
6296 > {
6297 crate::common::RegisterField::<
6298 17,
6299 0x1,
6300 1,
6301 0,
6302 dpfsar::Dpfsa17,
6303 dpfsar::Dpfsa17,
6304 Dpfsar_SPEC,
6305 crate::common::RW,
6306 >::from_register(self, 0)
6307 }
6308
6309 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 18"]
6310 #[inline(always)]
6311 pub fn dpfsa18(
6312 self,
6313 ) -> crate::common::RegisterField<
6314 18,
6315 0x1,
6316 1,
6317 0,
6318 dpfsar::Dpfsa18,
6319 dpfsar::Dpfsa18,
6320 Dpfsar_SPEC,
6321 crate::common::RW,
6322 > {
6323 crate::common::RegisterField::<
6324 18,
6325 0x1,
6326 1,
6327 0,
6328 dpfsar::Dpfsa18,
6329 dpfsar::Dpfsa18,
6330 Dpfsar_SPEC,
6331 crate::common::RW,
6332 >::from_register(self, 0)
6333 }
6334
6335 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 19"]
6336 #[inline(always)]
6337 pub fn dpfsa19(
6338 self,
6339 ) -> crate::common::RegisterField<
6340 19,
6341 0x1,
6342 1,
6343 0,
6344 dpfsar::Dpfsa19,
6345 dpfsar::Dpfsa19,
6346 Dpfsar_SPEC,
6347 crate::common::RW,
6348 > {
6349 crate::common::RegisterField::<
6350 19,
6351 0x1,
6352 1,
6353 0,
6354 dpfsar::Dpfsa19,
6355 dpfsar::Dpfsa19,
6356 Dpfsar_SPEC,
6357 crate::common::RW,
6358 >::from_register(self, 0)
6359 }
6360
6361 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 20"]
6362 #[inline(always)]
6363 pub fn dpfsa20(
6364 self,
6365 ) -> crate::common::RegisterField<
6366 20,
6367 0x1,
6368 1,
6369 0,
6370 dpfsar::Dpfsa20,
6371 dpfsar::Dpfsa20,
6372 Dpfsar_SPEC,
6373 crate::common::RW,
6374 > {
6375 crate::common::RegisterField::<
6376 20,
6377 0x1,
6378 1,
6379 0,
6380 dpfsar::Dpfsa20,
6381 dpfsar::Dpfsa20,
6382 Dpfsar_SPEC,
6383 crate::common::RW,
6384 >::from_register(self, 0)
6385 }
6386
6387 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 24"]
6388 #[inline(always)]
6389 pub fn dpfsa24(
6390 self,
6391 ) -> crate::common::RegisterField<
6392 24,
6393 0x1,
6394 1,
6395 0,
6396 dpfsar::Dpfsa24,
6397 dpfsar::Dpfsa24,
6398 Dpfsar_SPEC,
6399 crate::common::RW,
6400 > {
6401 crate::common::RegisterField::<
6402 24,
6403 0x1,
6404 1,
6405 0,
6406 dpfsar::Dpfsa24,
6407 dpfsar::Dpfsa24,
6408 Dpfsar_SPEC,
6409 crate::common::RW,
6410 >::from_register(self, 0)
6411 }
6412
6413 #[doc = "Deep Standby Interrupt Factor Security Attribute bit 26"]
6414 #[inline(always)]
6415 pub fn dpfsa26(
6416 self,
6417 ) -> crate::common::RegisterField<
6418 26,
6419 0x1,
6420 1,
6421 0,
6422 dpfsar::Dpfsa26,
6423 dpfsar::Dpfsa26,
6424 Dpfsar_SPEC,
6425 crate::common::RW,
6426 > {
6427 crate::common::RegisterField::<
6428 26,
6429 0x1,
6430 1,
6431 0,
6432 dpfsar::Dpfsa26,
6433 dpfsar::Dpfsa26,
6434 Dpfsar_SPEC,
6435 crate::common::RW,
6436 >::from_register(self, 0)
6437 }
6438}
6439impl ::core::default::Default for Dpfsar {
6440 #[inline(always)]
6441 fn default() -> Dpfsar {
6442 <crate::RegValueT<Dpfsar_SPEC> as RegisterValue<_>>::new(4294967295)
6443 }
6444}
6445pub mod dpfsar {
6446
6447 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6448 pub struct Dpfsa0_SPEC;
6449 pub type Dpfsa0 = crate::EnumBitfieldStruct<u8, Dpfsa0_SPEC>;
6450 impl Dpfsa0 {
6451 #[doc = "Secure"]
6452 pub const _0: Self = Self::new(0);
6453
6454 #[doc = "Non Secure"]
6455 pub const _1: Self = Self::new(1);
6456 }
6457 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6458 pub struct Dpfsa1_SPEC;
6459 pub type Dpfsa1 = crate::EnumBitfieldStruct<u8, Dpfsa1_SPEC>;
6460 impl Dpfsa1 {
6461 #[doc = "Secure"]
6462 pub const _0: Self = Self::new(0);
6463
6464 #[doc = "Non Secure"]
6465 pub const _1: Self = Self::new(1);
6466 }
6467 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6468 pub struct Dpfsa04_SPEC;
6469 pub type Dpfsa04 = crate::EnumBitfieldStruct<u8, Dpfsa04_SPEC>;
6470 impl Dpfsa04 {
6471 #[doc = "Secure"]
6472 pub const _0: Self = Self::new(0);
6473
6474 #[doc = "Non Secure"]
6475 pub const _1: Self = Self::new(1);
6476 }
6477 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6478 pub struct Dpfsa05_SPEC;
6479 pub type Dpfsa05 = crate::EnumBitfieldStruct<u8, Dpfsa05_SPEC>;
6480 impl Dpfsa05 {
6481 #[doc = "Secure"]
6482 pub const _0: Self = Self::new(0);
6483
6484 #[doc = "Non Secure"]
6485 pub const _1: Self = Self::new(1);
6486 }
6487 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6488 pub struct Dpfsa06_SPEC;
6489 pub type Dpfsa06 = crate::EnumBitfieldStruct<u8, Dpfsa06_SPEC>;
6490 impl Dpfsa06 {
6491 #[doc = "Secure"]
6492 pub const _0: Self = Self::new(0);
6493
6494 #[doc = "Non Secure"]
6495 pub const _1: Self = Self::new(1);
6496 }
6497 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6498 pub struct Dpfsa07_SPEC;
6499 pub type Dpfsa07 = crate::EnumBitfieldStruct<u8, Dpfsa07_SPEC>;
6500 impl Dpfsa07 {
6501 #[doc = "Secure"]
6502 pub const _0: Self = Self::new(0);
6503
6504 #[doc = "Non Secure"]
6505 pub const _1: Self = Self::new(1);
6506 }
6507 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6508 pub struct Dpfsa08_SPEC;
6509 pub type Dpfsa08 = crate::EnumBitfieldStruct<u8, Dpfsa08_SPEC>;
6510 impl Dpfsa08 {
6511 #[doc = "Secure"]
6512 pub const _0: Self = Self::new(0);
6513
6514 #[doc = "Non Secure"]
6515 pub const _1: Self = Self::new(1);
6516 }
6517 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6518 pub struct Dpfsa09_SPEC;
6519 pub type Dpfsa09 = crate::EnumBitfieldStruct<u8, Dpfsa09_SPEC>;
6520 impl Dpfsa09 {
6521 #[doc = "Secure"]
6522 pub const _0: Self = Self::new(0);
6523
6524 #[doc = "Non Secure"]
6525 pub const _1: Self = Self::new(1);
6526 }
6527 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6528 pub struct Dpfsa10_SPEC;
6529 pub type Dpfsa10 = crate::EnumBitfieldStruct<u8, Dpfsa10_SPEC>;
6530 impl Dpfsa10 {
6531 #[doc = "Secure"]
6532 pub const _0: Self = Self::new(0);
6533
6534 #[doc = "Non Secure"]
6535 pub const _1: Self = Self::new(1);
6536 }
6537 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6538 pub struct Dpfsa11_SPEC;
6539 pub type Dpfsa11 = crate::EnumBitfieldStruct<u8, Dpfsa11_SPEC>;
6540 impl Dpfsa11 {
6541 #[doc = "Secure"]
6542 pub const _0: Self = Self::new(0);
6543
6544 #[doc = "Non Secure"]
6545 pub const _1: Self = Self::new(1);
6546 }
6547 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6548 pub struct Dpfsa12_SPEC;
6549 pub type Dpfsa12 = crate::EnumBitfieldStruct<u8, Dpfsa12_SPEC>;
6550 impl Dpfsa12 {
6551 #[doc = "Secure"]
6552 pub const _0: Self = Self::new(0);
6553
6554 #[doc = "Non Secure"]
6555 pub const _1: Self = Self::new(1);
6556 }
6557 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6558 pub struct Dpfsa14_SPEC;
6559 pub type Dpfsa14 = crate::EnumBitfieldStruct<u8, Dpfsa14_SPEC>;
6560 impl Dpfsa14 {
6561 #[doc = "Secure"]
6562 pub const _0: Self = Self::new(0);
6563
6564 #[doc = "Non Secure"]
6565 pub const _1: Self = Self::new(1);
6566 }
6567 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6568 pub struct Dpfsa16_SPEC;
6569 pub type Dpfsa16 = crate::EnumBitfieldStruct<u8, Dpfsa16_SPEC>;
6570 impl Dpfsa16 {
6571 #[doc = "Secure"]
6572 pub const _0: Self = Self::new(0);
6573
6574 #[doc = "Non Secure"]
6575 pub const _1: Self = Self::new(1);
6576 }
6577 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6578 pub struct Dpfsa17_SPEC;
6579 pub type Dpfsa17 = crate::EnumBitfieldStruct<u8, Dpfsa17_SPEC>;
6580 impl Dpfsa17 {
6581 #[doc = "Secure"]
6582 pub const _0: Self = Self::new(0);
6583
6584 #[doc = "Non Secure"]
6585 pub const _1: Self = Self::new(1);
6586 }
6587 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6588 pub struct Dpfsa18_SPEC;
6589 pub type Dpfsa18 = crate::EnumBitfieldStruct<u8, Dpfsa18_SPEC>;
6590 impl Dpfsa18 {
6591 #[doc = "Secure"]
6592 pub const _0: Self = Self::new(0);
6593
6594 #[doc = "Non Secure"]
6595 pub const _1: Self = Self::new(1);
6596 }
6597 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6598 pub struct Dpfsa19_SPEC;
6599 pub type Dpfsa19 = crate::EnumBitfieldStruct<u8, Dpfsa19_SPEC>;
6600 impl Dpfsa19 {
6601 #[doc = "Secure"]
6602 pub const _0: Self = Self::new(0);
6603
6604 #[doc = "Non Secure"]
6605 pub const _1: Self = Self::new(1);
6606 }
6607 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6608 pub struct Dpfsa20_SPEC;
6609 pub type Dpfsa20 = crate::EnumBitfieldStruct<u8, Dpfsa20_SPEC>;
6610 impl Dpfsa20 {
6611 #[doc = "Secure"]
6612 pub const _0: Self = Self::new(0);
6613
6614 #[doc = "Non Secure"]
6615 pub const _1: Self = Self::new(1);
6616 }
6617 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6618 pub struct Dpfsa24_SPEC;
6619 pub type Dpfsa24 = crate::EnumBitfieldStruct<u8, Dpfsa24_SPEC>;
6620 impl Dpfsa24 {
6621 #[doc = "Secure"]
6622 pub const _0: Self = Self::new(0);
6623
6624 #[doc = "Non Secure"]
6625 pub const _1: Self = Self::new(1);
6626 }
6627 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6628 pub struct Dpfsa26_SPEC;
6629 pub type Dpfsa26 = crate::EnumBitfieldStruct<u8, Dpfsa26_SPEC>;
6630 impl Dpfsa26 {
6631 #[doc = "Secure"]
6632 pub const _0: Self = Self::new(0);
6633
6634 #[doc = "Non Secure"]
6635 pub const _1: Self = Self::new(1);
6636 }
6637}
6638#[doc(hidden)]
6639#[derive(Copy, Clone, Eq, PartialEq)]
6640pub struct Prcr_SPEC;
6641impl crate::sealed::RegSpec for Prcr_SPEC {
6642 type DataType = u16;
6643}
6644
6645#[doc = "Protect Register"]
6646pub type Prcr = crate::RegValueT<Prcr_SPEC>;
6647
6648impl Prcr {
6649 #[doc = "Enable writing to the registers related to the clock generation circuit"]
6650 #[inline(always)]
6651 pub fn prc0(
6652 self,
6653 ) -> crate::common::RegisterField<
6654 0,
6655 0x1,
6656 1,
6657 0,
6658 prcr::Prc0,
6659 prcr::Prc0,
6660 Prcr_SPEC,
6661 crate::common::RW,
6662 > {
6663 crate::common::RegisterField::<
6664 0,
6665 0x1,
6666 1,
6667 0,
6668 prcr::Prc0,
6669 prcr::Prc0,
6670 Prcr_SPEC,
6671 crate::common::RW,
6672 >::from_register(self, 0)
6673 }
6674
6675 #[doc = "Enable writing to the registers related to the low power modes"]
6676 #[inline(always)]
6677 pub fn prc1(
6678 self,
6679 ) -> crate::common::RegisterField<
6680 1,
6681 0x1,
6682 1,
6683 0,
6684 prcr::Prc1,
6685 prcr::Prc1,
6686 Prcr_SPEC,
6687 crate::common::RW,
6688 > {
6689 crate::common::RegisterField::<
6690 1,
6691 0x1,
6692 1,
6693 0,
6694 prcr::Prc1,
6695 prcr::Prc1,
6696 Prcr_SPEC,
6697 crate::common::RW,
6698 >::from_register(self, 0)
6699 }
6700
6701 #[doc = "Enable writing to the registers related to the LVD"]
6702 #[inline(always)]
6703 pub fn prc3(
6704 self,
6705 ) -> crate::common::RegisterField<
6706 3,
6707 0x1,
6708 1,
6709 0,
6710 prcr::Prc3,
6711 prcr::Prc3,
6712 Prcr_SPEC,
6713 crate::common::RW,
6714 > {
6715 crate::common::RegisterField::<
6716 3,
6717 0x1,
6718 1,
6719 0,
6720 prcr::Prc3,
6721 prcr::Prc3,
6722 Prcr_SPEC,
6723 crate::common::RW,
6724 >::from_register(self, 0)
6725 }
6726
6727 #[inline(always)]
6728 pub fn prc4(
6729 self,
6730 ) -> crate::common::RegisterField<
6731 4,
6732 0x1,
6733 1,
6734 0,
6735 prcr::Prc4,
6736 prcr::Prc4,
6737 Prcr_SPEC,
6738 crate::common::RW,
6739 > {
6740 crate::common::RegisterField::<
6741 4,
6742 0x1,
6743 1,
6744 0,
6745 prcr::Prc4,
6746 prcr::Prc4,
6747 Prcr_SPEC,
6748 crate::common::RW,
6749 >::from_register(self, 0)
6750 }
6751
6752 #[doc = "PRC Key Code"]
6753 #[inline(always)]
6754 pub fn prkey(
6755 self,
6756 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Prcr_SPEC, crate::common::W> {
6757 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Prcr_SPEC,crate::common::W>::from_register(self,0)
6758 }
6759}
6760impl ::core::default::Default for Prcr {
6761 #[inline(always)]
6762 fn default() -> Prcr {
6763 <crate::RegValueT<Prcr_SPEC> as RegisterValue<_>>::new(0)
6764 }
6765}
6766pub mod prcr {
6767
6768 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6769 pub struct Prc0_SPEC;
6770 pub type Prc0 = crate::EnumBitfieldStruct<u8, Prc0_SPEC>;
6771 impl Prc0 {
6772 #[doc = "Disable writes"]
6773 pub const _0: Self = Self::new(0);
6774
6775 #[doc = "Enable writes"]
6776 pub const _1: Self = Self::new(1);
6777 }
6778 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6779 pub struct Prc1_SPEC;
6780 pub type Prc1 = crate::EnumBitfieldStruct<u8, Prc1_SPEC>;
6781 impl Prc1 {
6782 #[doc = "Disable writes"]
6783 pub const _0: Self = Self::new(0);
6784
6785 #[doc = "Enable writes"]
6786 pub const _1: Self = Self::new(1);
6787 }
6788 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6789 pub struct Prc3_SPEC;
6790 pub type Prc3 = crate::EnumBitfieldStruct<u8, Prc3_SPEC>;
6791 impl Prc3 {
6792 #[doc = "Disable writes"]
6793 pub const _0: Self = Self::new(0);
6794
6795 #[doc = "Enable writes"]
6796 pub const _1: Self = Self::new(1);
6797 }
6798 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6799 pub struct Prc4_SPEC;
6800 pub type Prc4 = crate::EnumBitfieldStruct<u8, Prc4_SPEC>;
6801 impl Prc4 {
6802 #[doc = "Disable writes"]
6803 pub const _0: Self = Self::new(0);
6804
6805 #[doc = "Enable writes"]
6806 pub const _1: Self = Self::new(1);
6807 }
6808}
6809#[doc(hidden)]
6810#[derive(Copy, Clone, Eq, PartialEq)]
6811pub struct Dpsbycr_SPEC;
6812impl crate::sealed::RegSpec for Dpsbycr_SPEC {
6813 type DataType = u8;
6814}
6815
6816#[doc = "Deep Standby Control Register"]
6817pub type Dpsbycr = crate::RegValueT<Dpsbycr_SPEC>;
6818
6819impl Dpsbycr {
6820 #[doc = "Power-Supply Control"]
6821 #[inline(always)]
6822 pub fn deepcut(
6823 self,
6824 ) -> crate::common::RegisterField<
6825 0,
6826 0x3,
6827 1,
6828 0,
6829 dpsbycr::Deepcut,
6830 dpsbycr::Deepcut,
6831 Dpsbycr_SPEC,
6832 crate::common::RW,
6833 > {
6834 crate::common::RegisterField::<
6835 0,
6836 0x3,
6837 1,
6838 0,
6839 dpsbycr::Deepcut,
6840 dpsbycr::Deepcut,
6841 Dpsbycr_SPEC,
6842 crate::common::RW,
6843 >::from_register(self, 0)
6844 }
6845
6846 #[doc = "I/O Port Rentention"]
6847 #[inline(always)]
6848 pub fn iokeep(
6849 self,
6850 ) -> crate::common::RegisterField<
6851 6,
6852 0x1,
6853 1,
6854 0,
6855 dpsbycr::Iokeep,
6856 dpsbycr::Iokeep,
6857 Dpsbycr_SPEC,
6858 crate::common::RW,
6859 > {
6860 crate::common::RegisterField::<
6861 6,
6862 0x1,
6863 1,
6864 0,
6865 dpsbycr::Iokeep,
6866 dpsbycr::Iokeep,
6867 Dpsbycr_SPEC,
6868 crate::common::RW,
6869 >::from_register(self, 0)
6870 }
6871
6872 #[doc = "Deep Software Standby"]
6873 #[inline(always)]
6874 pub fn dpsby(
6875 self,
6876 ) -> crate::common::RegisterField<
6877 7,
6878 0x1,
6879 1,
6880 0,
6881 dpsbycr::Dpsby,
6882 dpsbycr::Dpsby,
6883 Dpsbycr_SPEC,
6884 crate::common::RW,
6885 > {
6886 crate::common::RegisterField::<
6887 7,
6888 0x1,
6889 1,
6890 0,
6891 dpsbycr::Dpsby,
6892 dpsbycr::Dpsby,
6893 Dpsbycr_SPEC,
6894 crate::common::RW,
6895 >::from_register(self, 0)
6896 }
6897}
6898impl ::core::default::Default for Dpsbycr {
6899 #[inline(always)]
6900 fn default() -> Dpsbycr {
6901 <crate::RegValueT<Dpsbycr_SPEC> as RegisterValue<_>>::new(1)
6902 }
6903}
6904pub mod dpsbycr {
6905
6906 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6907 pub struct Deepcut_SPEC;
6908 pub type Deepcut = crate::EnumBitfieldStruct<u8, Deepcut_SPEC>;
6909 impl Deepcut {
6910 #[doc = "Power to the standby RAM, Low-speed on-chip oscillator, AGTn (n = 0, 1), and USBFS resume detecting unit is supplied in Deep Software Standby mode."]
6911 pub const _00: Self = Self::new(0);
6912
6913 #[doc = "Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode."]
6914 pub const _01: Self = Self::new(1);
6915
6916 #[doc = "Setting prohibited"]
6917 pub const _10: Self = Self::new(2);
6918
6919 #[doc = "Power to the standby RAM, Low-speed on-chip oscillator, AGT, and USBFS resume detecting unit is not supplied in Deep Software Standby mode. In addition, LVD is disabled and the low power function in a power-on reset circuit is enabled."]
6920 pub const _11: Self = Self::new(3);
6921 }
6922 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6923 pub struct Iokeep_SPEC;
6924 pub type Iokeep = crate::EnumBitfieldStruct<u8, Iokeep_SPEC>;
6925 impl Iokeep {
6926 #[doc = "When the Deep Software Standby mode is canceled, the I/O ports are in the reset state."]
6927 pub const _0: Self = Self::new(0);
6928
6929 #[doc = "When the Deep Software Standby mode is canceled, the I/O ports are in the same state as in the Deep Software Standby mode."]
6930 pub const _1: Self = Self::new(1);
6931 }
6932 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6933 pub struct Dpsby_SPEC;
6934 pub type Dpsby = crate::EnumBitfieldStruct<u8, Dpsby_SPEC>;
6935 impl Dpsby {
6936 #[doc = "Sleep mode (SBYCR.SSBY=0) / Software Standby mode (SBYCR.SSBY=1)"]
6937 pub const _0: Self = Self::new(0);
6938
6939 #[doc = "Sleep mode (SBYCR.SSBY=0) / Deep Software Standby mode (SBYCR.SSBY=1)"]
6940 pub const _1: Self = Self::new(1);
6941 }
6942}
6943#[doc(hidden)]
6944#[derive(Copy, Clone, Eq, PartialEq)]
6945pub struct Dpswcr_SPEC;
6946impl crate::sealed::RegSpec for Dpswcr_SPEC {
6947 type DataType = u8;
6948}
6949
6950#[doc = "Deep Standby Wait Control Register"]
6951pub type Dpswcr = crate::RegValueT<Dpswcr_SPEC>;
6952
6953impl Dpswcr {
6954 #[doc = "Deep Software Wait Standby Time Setting Bit"]
6955 #[inline(always)]
6956 pub fn wtsts(
6957 self,
6958 ) -> crate::common::RegisterField<
6959 0,
6960 0x3f,
6961 1,
6962 0,
6963 dpswcr::Wtsts,
6964 dpswcr::Wtsts,
6965 Dpswcr_SPEC,
6966 crate::common::RW,
6967 > {
6968 crate::common::RegisterField::<
6969 0,
6970 0x3f,
6971 1,
6972 0,
6973 dpswcr::Wtsts,
6974 dpswcr::Wtsts,
6975 Dpswcr_SPEC,
6976 crate::common::RW,
6977 >::from_register(self, 0)
6978 }
6979}
6980impl ::core::default::Default for Dpswcr {
6981 #[inline(always)]
6982 fn default() -> Dpswcr {
6983 <crate::RegValueT<Dpswcr_SPEC> as RegisterValue<_>>::new(25)
6984 }
6985}
6986pub mod dpswcr {
6987
6988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6989 pub struct Wtsts_SPEC;
6990 pub type Wtsts = crate::EnumBitfieldStruct<u8, Wtsts_SPEC>;
6991 impl Wtsts {
6992 #[doc = "Wait cycle for fast recovery"]
6993 pub const _0_X_0_E: Self = Self::new(14);
6994
6995 #[doc = "Wait cycle for slow recovery"]
6996 pub const _0_X_19: Self = Self::new(25);
6997 }
6998}
6999#[doc(hidden)]
7000#[derive(Copy, Clone, Eq, PartialEq)]
7001pub struct Dpsier0_SPEC;
7002impl crate::sealed::RegSpec for Dpsier0_SPEC {
7003 type DataType = u8;
7004}
7005
7006#[doc = "Deep Standby Interrupt Enable Register 0"]
7007pub type Dpsier0 = crate::RegValueT<Dpsier0_SPEC>;
7008
7009impl Dpsier0 {
7010 #[doc = "IRQ0-DS Pin Enable"]
7011 #[inline(always)]
7012 pub fn dirq0e(
7013 self,
7014 ) -> crate::common::RegisterField<
7015 0,
7016 0x1,
7017 1,
7018 0,
7019 dpsier0::Dirq0E,
7020 dpsier0::Dirq0E,
7021 Dpsier0_SPEC,
7022 crate::common::RW,
7023 > {
7024 crate::common::RegisterField::<
7025 0,
7026 0x1,
7027 1,
7028 0,
7029 dpsier0::Dirq0E,
7030 dpsier0::Dirq0E,
7031 Dpsier0_SPEC,
7032 crate::common::RW,
7033 >::from_register(self, 0)
7034 }
7035
7036 #[doc = "IRQ1-DS Pin Enable"]
7037 #[inline(always)]
7038 pub fn dirq1e(
7039 self,
7040 ) -> crate::common::RegisterField<
7041 1,
7042 0x1,
7043 1,
7044 0,
7045 dpsier0::Dirq1E,
7046 dpsier0::Dirq1E,
7047 Dpsier0_SPEC,
7048 crate::common::RW,
7049 > {
7050 crate::common::RegisterField::<
7051 1,
7052 0x1,
7053 1,
7054 0,
7055 dpsier0::Dirq1E,
7056 dpsier0::Dirq1E,
7057 Dpsier0_SPEC,
7058 crate::common::RW,
7059 >::from_register(self, 0)
7060 }
7061
7062 #[doc = "IRQ4-DS Pin Enable"]
7063 #[inline(always)]
7064 pub fn dirq4e(
7065 self,
7066 ) -> crate::common::RegisterField<
7067 4,
7068 0x1,
7069 1,
7070 0,
7071 dpsier0::Dirq4E,
7072 dpsier0::Dirq4E,
7073 Dpsier0_SPEC,
7074 crate::common::RW,
7075 > {
7076 crate::common::RegisterField::<
7077 4,
7078 0x1,
7079 1,
7080 0,
7081 dpsier0::Dirq4E,
7082 dpsier0::Dirq4E,
7083 Dpsier0_SPEC,
7084 crate::common::RW,
7085 >::from_register(self, 0)
7086 }
7087
7088 #[doc = "IRQ5-DS Pin Enable"]
7089 #[inline(always)]
7090 pub fn dirq5e(
7091 self,
7092 ) -> crate::common::RegisterField<
7093 5,
7094 0x1,
7095 1,
7096 0,
7097 dpsier0::Dirq5E,
7098 dpsier0::Dirq5E,
7099 Dpsier0_SPEC,
7100 crate::common::RW,
7101 > {
7102 crate::common::RegisterField::<
7103 5,
7104 0x1,
7105 1,
7106 0,
7107 dpsier0::Dirq5E,
7108 dpsier0::Dirq5E,
7109 Dpsier0_SPEC,
7110 crate::common::RW,
7111 >::from_register(self, 0)
7112 }
7113
7114 #[doc = "IRQ6-DS Pin Enable"]
7115 #[inline(always)]
7116 pub fn dirq6e(
7117 self,
7118 ) -> crate::common::RegisterField<
7119 6,
7120 0x1,
7121 1,
7122 0,
7123 dpsier0::Dirq6E,
7124 dpsier0::Dirq6E,
7125 Dpsier0_SPEC,
7126 crate::common::RW,
7127 > {
7128 crate::common::RegisterField::<
7129 6,
7130 0x1,
7131 1,
7132 0,
7133 dpsier0::Dirq6E,
7134 dpsier0::Dirq6E,
7135 Dpsier0_SPEC,
7136 crate::common::RW,
7137 >::from_register(self, 0)
7138 }
7139
7140 #[doc = "IRQ7-DS Pin Enable"]
7141 #[inline(always)]
7142 pub fn dirq7e(
7143 self,
7144 ) -> crate::common::RegisterField<
7145 7,
7146 0x1,
7147 1,
7148 0,
7149 dpsier0::Dirq7E,
7150 dpsier0::Dirq7E,
7151 Dpsier0_SPEC,
7152 crate::common::RW,
7153 > {
7154 crate::common::RegisterField::<
7155 7,
7156 0x1,
7157 1,
7158 0,
7159 dpsier0::Dirq7E,
7160 dpsier0::Dirq7E,
7161 Dpsier0_SPEC,
7162 crate::common::RW,
7163 >::from_register(self, 0)
7164 }
7165}
7166impl ::core::default::Default for Dpsier0 {
7167 #[inline(always)]
7168 fn default() -> Dpsier0 {
7169 <crate::RegValueT<Dpsier0_SPEC> as RegisterValue<_>>::new(0)
7170 }
7171}
7172pub mod dpsier0 {
7173
7174 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7175 pub struct Dirq0E_SPEC;
7176 pub type Dirq0E = crate::EnumBitfieldStruct<u8, Dirq0E_SPEC>;
7177 impl Dirq0E {
7178 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7179 pub const _0: Self = Self::new(0);
7180
7181 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7182 pub const _1: Self = Self::new(1);
7183 }
7184 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7185 pub struct Dirq1E_SPEC;
7186 pub type Dirq1E = crate::EnumBitfieldStruct<u8, Dirq1E_SPEC>;
7187 impl Dirq1E {
7188 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7189 pub const _0: Self = Self::new(0);
7190
7191 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7192 pub const _1: Self = Self::new(1);
7193 }
7194 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7195 pub struct Dirq4E_SPEC;
7196 pub type Dirq4E = crate::EnumBitfieldStruct<u8, Dirq4E_SPEC>;
7197 impl Dirq4E {
7198 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7199 pub const _0: Self = Self::new(0);
7200
7201 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7202 pub const _1: Self = Self::new(1);
7203 }
7204 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7205 pub struct Dirq5E_SPEC;
7206 pub type Dirq5E = crate::EnumBitfieldStruct<u8, Dirq5E_SPEC>;
7207 impl Dirq5E {
7208 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7209 pub const _0: Self = Self::new(0);
7210
7211 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7212 pub const _1: Self = Self::new(1);
7213 }
7214 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7215 pub struct Dirq6E_SPEC;
7216 pub type Dirq6E = crate::EnumBitfieldStruct<u8, Dirq6E_SPEC>;
7217 impl Dirq6E {
7218 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7219 pub const _0: Self = Self::new(0);
7220
7221 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7222 pub const _1: Self = Self::new(1);
7223 }
7224 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7225 pub struct Dirq7E_SPEC;
7226 pub type Dirq7E = crate::EnumBitfieldStruct<u8, Dirq7E_SPEC>;
7227 impl Dirq7E {
7228 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7229 pub const _0: Self = Self::new(0);
7230
7231 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7232 pub const _1: Self = Self::new(1);
7233 }
7234}
7235#[doc(hidden)]
7236#[derive(Copy, Clone, Eq, PartialEq)]
7237pub struct Dpsier1_SPEC;
7238impl crate::sealed::RegSpec for Dpsier1_SPEC {
7239 type DataType = u8;
7240}
7241
7242#[doc = "Deep Standby Interrupt Enable Register 1"]
7243pub type Dpsier1 = crate::RegValueT<Dpsier1_SPEC>;
7244
7245impl Dpsier1 {
7246 #[doc = "IRQ8-DS Pin Enable"]
7247 #[inline(always)]
7248 pub fn dirq8e(
7249 self,
7250 ) -> crate::common::RegisterField<
7251 0,
7252 0x1,
7253 1,
7254 0,
7255 dpsier1::Dirq8E,
7256 dpsier1::Dirq8E,
7257 Dpsier1_SPEC,
7258 crate::common::RW,
7259 > {
7260 crate::common::RegisterField::<
7261 0,
7262 0x1,
7263 1,
7264 0,
7265 dpsier1::Dirq8E,
7266 dpsier1::Dirq8E,
7267 Dpsier1_SPEC,
7268 crate::common::RW,
7269 >::from_register(self, 0)
7270 }
7271
7272 #[doc = "IRQ9-DS Pin Enable"]
7273 #[inline(always)]
7274 pub fn dirq9e(
7275 self,
7276 ) -> crate::common::RegisterField<
7277 1,
7278 0x1,
7279 1,
7280 0,
7281 dpsier1::Dirq9E,
7282 dpsier1::Dirq9E,
7283 Dpsier1_SPEC,
7284 crate::common::RW,
7285 > {
7286 crate::common::RegisterField::<
7287 1,
7288 0x1,
7289 1,
7290 0,
7291 dpsier1::Dirq9E,
7292 dpsier1::Dirq9E,
7293 Dpsier1_SPEC,
7294 crate::common::RW,
7295 >::from_register(self, 0)
7296 }
7297
7298 #[doc = "IRQ10-DS Pin Enable"]
7299 #[inline(always)]
7300 pub fn dirq10e(
7301 self,
7302 ) -> crate::common::RegisterField<
7303 2,
7304 0x1,
7305 1,
7306 0,
7307 dpsier1::Dirq10E,
7308 dpsier1::Dirq10E,
7309 Dpsier1_SPEC,
7310 crate::common::RW,
7311 > {
7312 crate::common::RegisterField::<
7313 2,
7314 0x1,
7315 1,
7316 0,
7317 dpsier1::Dirq10E,
7318 dpsier1::Dirq10E,
7319 Dpsier1_SPEC,
7320 crate::common::RW,
7321 >::from_register(self, 0)
7322 }
7323
7324 #[doc = "IRQ11-DS Pin Enable"]
7325 #[inline(always)]
7326 pub fn dirq11e(
7327 self,
7328 ) -> crate::common::RegisterField<
7329 3,
7330 0x1,
7331 1,
7332 0,
7333 dpsier1::Dirq11E,
7334 dpsier1::Dirq11E,
7335 Dpsier1_SPEC,
7336 crate::common::RW,
7337 > {
7338 crate::common::RegisterField::<
7339 3,
7340 0x1,
7341 1,
7342 0,
7343 dpsier1::Dirq11E,
7344 dpsier1::Dirq11E,
7345 Dpsier1_SPEC,
7346 crate::common::RW,
7347 >::from_register(self, 0)
7348 }
7349
7350 #[doc = "IRQ12-DS Pin Enable"]
7351 #[inline(always)]
7352 pub fn dirq12e(
7353 self,
7354 ) -> crate::common::RegisterField<
7355 4,
7356 0x1,
7357 1,
7358 0,
7359 dpsier1::Dirq12E,
7360 dpsier1::Dirq12E,
7361 Dpsier1_SPEC,
7362 crate::common::RW,
7363 > {
7364 crate::common::RegisterField::<
7365 4,
7366 0x1,
7367 1,
7368 0,
7369 dpsier1::Dirq12E,
7370 dpsier1::Dirq12E,
7371 Dpsier1_SPEC,
7372 crate::common::RW,
7373 >::from_register(self, 0)
7374 }
7375
7376 #[doc = "IRQ14-DS Pin Enable"]
7377 #[inline(always)]
7378 pub fn dirq14e(
7379 self,
7380 ) -> crate::common::RegisterField<
7381 6,
7382 0x1,
7383 1,
7384 0,
7385 dpsier1::Dirq14E,
7386 dpsier1::Dirq14E,
7387 Dpsier1_SPEC,
7388 crate::common::RW,
7389 > {
7390 crate::common::RegisterField::<
7391 6,
7392 0x1,
7393 1,
7394 0,
7395 dpsier1::Dirq14E,
7396 dpsier1::Dirq14E,
7397 Dpsier1_SPEC,
7398 crate::common::RW,
7399 >::from_register(self, 0)
7400 }
7401}
7402impl ::core::default::Default for Dpsier1 {
7403 #[inline(always)]
7404 fn default() -> Dpsier1 {
7405 <crate::RegValueT<Dpsier1_SPEC> as RegisterValue<_>>::new(0)
7406 }
7407}
7408pub mod dpsier1 {
7409
7410 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7411 pub struct Dirq8E_SPEC;
7412 pub type Dirq8E = crate::EnumBitfieldStruct<u8, Dirq8E_SPEC>;
7413 impl Dirq8E {
7414 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7415 pub const _0: Self = Self::new(0);
7416
7417 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7418 pub const _1: Self = Self::new(1);
7419 }
7420 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7421 pub struct Dirq9E_SPEC;
7422 pub type Dirq9E = crate::EnumBitfieldStruct<u8, Dirq9E_SPEC>;
7423 impl Dirq9E {
7424 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7425 pub const _0: Self = Self::new(0);
7426
7427 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7428 pub const _1: Self = Self::new(1);
7429 }
7430 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7431 pub struct Dirq10E_SPEC;
7432 pub type Dirq10E = crate::EnumBitfieldStruct<u8, Dirq10E_SPEC>;
7433 impl Dirq10E {
7434 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7435 pub const _0: Self = Self::new(0);
7436
7437 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7438 pub const _1: Self = Self::new(1);
7439 }
7440 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7441 pub struct Dirq11E_SPEC;
7442 pub type Dirq11E = crate::EnumBitfieldStruct<u8, Dirq11E_SPEC>;
7443 impl Dirq11E {
7444 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7445 pub const _0: Self = Self::new(0);
7446
7447 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7448 pub const _1: Self = Self::new(1);
7449 }
7450 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7451 pub struct Dirq12E_SPEC;
7452 pub type Dirq12E = crate::EnumBitfieldStruct<u8, Dirq12E_SPEC>;
7453 impl Dirq12E {
7454 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7455 pub const _0: Self = Self::new(0);
7456
7457 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7458 pub const _1: Self = Self::new(1);
7459 }
7460 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7461 pub struct Dirq14E_SPEC;
7462 pub type Dirq14E = crate::EnumBitfieldStruct<u8, Dirq14E_SPEC>;
7463 impl Dirq14E {
7464 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7465 pub const _0: Self = Self::new(0);
7466
7467 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7468 pub const _1: Self = Self::new(1);
7469 }
7470}
7471#[doc(hidden)]
7472#[derive(Copy, Clone, Eq, PartialEq)]
7473pub struct Dpsier2_SPEC;
7474impl crate::sealed::RegSpec for Dpsier2_SPEC {
7475 type DataType = u8;
7476}
7477
7478#[doc = "Deep Software Standby Interrupt Enable Register 2"]
7479pub type Dpsier2 = crate::RegValueT<Dpsier2_SPEC>;
7480
7481impl Dpsier2 {
7482 #[doc = "LVD1 Deep Software Standby Cancel Signal Enable"]
7483 #[inline(always)]
7484 pub fn dlvd1ie(
7485 self,
7486 ) -> crate::common::RegisterField<
7487 0,
7488 0x1,
7489 1,
7490 0,
7491 dpsier2::Dlvd1Ie,
7492 dpsier2::Dlvd1Ie,
7493 Dpsier2_SPEC,
7494 crate::common::RW,
7495 > {
7496 crate::common::RegisterField::<
7497 0,
7498 0x1,
7499 1,
7500 0,
7501 dpsier2::Dlvd1Ie,
7502 dpsier2::Dlvd1Ie,
7503 Dpsier2_SPEC,
7504 crate::common::RW,
7505 >::from_register(self, 0)
7506 }
7507
7508 #[doc = "LVD2 Deep Software Standby Cancel Signal Enable"]
7509 #[inline(always)]
7510 pub fn dlvd2ie(
7511 self,
7512 ) -> crate::common::RegisterField<
7513 1,
7514 0x1,
7515 1,
7516 0,
7517 dpsier2::Dlvd2Ie,
7518 dpsier2::Dlvd2Ie,
7519 Dpsier2_SPEC,
7520 crate::common::RW,
7521 > {
7522 crate::common::RegisterField::<
7523 1,
7524 0x1,
7525 1,
7526 0,
7527 dpsier2::Dlvd2Ie,
7528 dpsier2::Dlvd2Ie,
7529 Dpsier2_SPEC,
7530 crate::common::RW,
7531 >::from_register(self, 0)
7532 }
7533
7534 #[doc = "RTC Interval interrupt Deep Software Standby Cancel Signal Enable"]
7535 #[inline(always)]
7536 pub fn drtciie(
7537 self,
7538 ) -> crate::common::RegisterField<
7539 2,
7540 0x1,
7541 1,
7542 0,
7543 dpsier2::Drtciie,
7544 dpsier2::Drtciie,
7545 Dpsier2_SPEC,
7546 crate::common::RW,
7547 > {
7548 crate::common::RegisterField::<
7549 2,
7550 0x1,
7551 1,
7552 0,
7553 dpsier2::Drtciie,
7554 dpsier2::Drtciie,
7555 Dpsier2_SPEC,
7556 crate::common::RW,
7557 >::from_register(self, 0)
7558 }
7559
7560 #[doc = "RTC Alarm interrupt Deep Software Standby Cancel Signal Enable"]
7561 #[inline(always)]
7562 pub fn drtcaie(
7563 self,
7564 ) -> crate::common::RegisterField<
7565 3,
7566 0x1,
7567 1,
7568 0,
7569 dpsier2::Drtcaie,
7570 dpsier2::Drtcaie,
7571 Dpsier2_SPEC,
7572 crate::common::RW,
7573 > {
7574 crate::common::RegisterField::<
7575 3,
7576 0x1,
7577 1,
7578 0,
7579 dpsier2::Drtcaie,
7580 dpsier2::Drtcaie,
7581 Dpsier2_SPEC,
7582 crate::common::RW,
7583 >::from_register(self, 0)
7584 }
7585
7586 #[doc = "NMI Pin Enable"]
7587 #[inline(always)]
7588 pub fn dnmie(
7589 self,
7590 ) -> crate::common::RegisterField<
7591 4,
7592 0x1,
7593 1,
7594 0,
7595 dpsier2::Dnmie,
7596 dpsier2::Dnmie,
7597 Dpsier2_SPEC,
7598 crate::common::RW,
7599 > {
7600 crate::common::RegisterField::<
7601 4,
7602 0x1,
7603 1,
7604 0,
7605 dpsier2::Dnmie,
7606 dpsier2::Dnmie,
7607 Dpsier2_SPEC,
7608 crate::common::RW,
7609 >::from_register(self, 0)
7610 }
7611}
7612impl ::core::default::Default for Dpsier2 {
7613 #[inline(always)]
7614 fn default() -> Dpsier2 {
7615 <crate::RegValueT<Dpsier2_SPEC> as RegisterValue<_>>::new(0)
7616 }
7617}
7618pub mod dpsier2 {
7619
7620 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7621 pub struct Dlvd1Ie_SPEC;
7622 pub type Dlvd1Ie = crate::EnumBitfieldStruct<u8, Dlvd1Ie_SPEC>;
7623 impl Dlvd1Ie {
7624 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7625 pub const _0: Self = Self::new(0);
7626
7627 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7628 pub const _1: Self = Self::new(1);
7629 }
7630 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7631 pub struct Dlvd2Ie_SPEC;
7632 pub type Dlvd2Ie = crate::EnumBitfieldStruct<u8, Dlvd2Ie_SPEC>;
7633 impl Dlvd2Ie {
7634 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7635 pub const _0: Self = Self::new(0);
7636
7637 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7638 pub const _1: Self = Self::new(1);
7639 }
7640 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7641 pub struct Drtciie_SPEC;
7642 pub type Drtciie = crate::EnumBitfieldStruct<u8, Drtciie_SPEC>;
7643 impl Drtciie {
7644 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7645 pub const _0: Self = Self::new(0);
7646
7647 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7648 pub const _1: Self = Self::new(1);
7649 }
7650 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7651 pub struct Drtcaie_SPEC;
7652 pub type Drtcaie = crate::EnumBitfieldStruct<u8, Drtcaie_SPEC>;
7653 impl Drtcaie {
7654 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7655 pub const _0: Self = Self::new(0);
7656
7657 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7658 pub const _1: Self = Self::new(1);
7659 }
7660 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7661 pub struct Dnmie_SPEC;
7662 pub type Dnmie = crate::EnumBitfieldStruct<u8, Dnmie_SPEC>;
7663 impl Dnmie {
7664 #[doc = "Cancelling Deep Software Standby mode is disabled"]
7665 pub const _0: Self = Self::new(0);
7666
7667 #[doc = "Cancelling Deep Software Standby mode is enabled"]
7668 pub const _1: Self = Self::new(1);
7669 }
7670}
7671#[doc(hidden)]
7672#[derive(Copy, Clone, Eq, PartialEq)]
7673pub struct Dpsier3_SPEC;
7674impl crate::sealed::RegSpec for Dpsier3_SPEC {
7675 type DataType = u8;
7676}
7677
7678#[doc = "Deep Standby Interrupt Enable Register 3"]
7679pub type Dpsier3 = crate::RegValueT<Dpsier3_SPEC>;
7680
7681impl Dpsier3 {
7682 #[doc = "USBFS0 Suspend/Resume Deep Standby Cancel Signal Enable"]
7683 #[inline(always)]
7684 pub fn dusbfs0ie(
7685 self,
7686 ) -> crate::common::RegisterField<
7687 0,
7688 0x1,
7689 1,
7690 0,
7691 dpsier3::Dusbfs0Ie,
7692 dpsier3::Dusbfs0Ie,
7693 Dpsier3_SPEC,
7694 crate::common::RW,
7695 > {
7696 crate::common::RegisterField::<
7697 0,
7698 0x1,
7699 1,
7700 0,
7701 dpsier3::Dusbfs0Ie,
7702 dpsier3::Dusbfs0Ie,
7703 Dpsier3_SPEC,
7704 crate::common::RW,
7705 >::from_register(self, 0)
7706 }
7707
7708 #[doc = "AGT1 Underflow Deep Standby Cancel Signal Enable"]
7709 #[inline(always)]
7710 pub fn dagt1ie(
7711 self,
7712 ) -> crate::common::RegisterField<
7713 2,
7714 0x1,
7715 1,
7716 0,
7717 dpsier3::Dagt1Ie,
7718 dpsier3::Dagt1Ie,
7719 Dpsier3_SPEC,
7720 crate::common::RW,
7721 > {
7722 crate::common::RegisterField::<
7723 2,
7724 0x1,
7725 1,
7726 0,
7727 dpsier3::Dagt1Ie,
7728 dpsier3::Dagt1Ie,
7729 Dpsier3_SPEC,
7730 crate::common::RW,
7731 >::from_register(self, 0)
7732 }
7733}
7734impl ::core::default::Default for Dpsier3 {
7735 #[inline(always)]
7736 fn default() -> Dpsier3 {
7737 <crate::RegValueT<Dpsier3_SPEC> as RegisterValue<_>>::new(0)
7738 }
7739}
7740pub mod dpsier3 {
7741
7742 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7743 pub struct Dusbfs0Ie_SPEC;
7744 pub type Dusbfs0Ie = crate::EnumBitfieldStruct<u8, Dusbfs0Ie_SPEC>;
7745 impl Dusbfs0Ie {
7746 #[doc = "Cancelling deep standby mode is disabled"]
7747 pub const _0: Self = Self::new(0);
7748
7749 #[doc = "Cancelling deep standby mode is enabled"]
7750 pub const _1: Self = Self::new(1);
7751 }
7752 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7753 pub struct Dagt1Ie_SPEC;
7754 pub type Dagt1Ie = crate::EnumBitfieldStruct<u8, Dagt1Ie_SPEC>;
7755 impl Dagt1Ie {
7756 #[doc = "Cancelling deep standby mode is disabled"]
7757 pub const _0: Self = Self::new(0);
7758
7759 #[doc = "Cancelling deep standby mode is enabled"]
7760 pub const _1: Self = Self::new(1);
7761 }
7762}
7763#[doc(hidden)]
7764#[derive(Copy, Clone, Eq, PartialEq)]
7765pub struct Dpsifr0_SPEC;
7766impl crate::sealed::RegSpec for Dpsifr0_SPEC {
7767 type DataType = u8;
7768}
7769
7770#[doc = "Deep Standby Interrupt Flag Register 0"]
7771pub type Dpsifr0 = crate::RegValueT<Dpsifr0_SPEC>;
7772
7773impl Dpsifr0 {
7774 #[doc = "IRQ0-DS Pin Deep Standby Cancel Flag"]
7775 #[inline(always)]
7776 pub fn dirq0f(
7777 self,
7778 ) -> crate::common::RegisterField<
7779 0,
7780 0x1,
7781 1,
7782 0,
7783 dpsifr0::Dirq0F,
7784 dpsifr0::Dirq0F,
7785 Dpsifr0_SPEC,
7786 crate::common::RW,
7787 > {
7788 crate::common::RegisterField::<
7789 0,
7790 0x1,
7791 1,
7792 0,
7793 dpsifr0::Dirq0F,
7794 dpsifr0::Dirq0F,
7795 Dpsifr0_SPEC,
7796 crate::common::RW,
7797 >::from_register(self, 0)
7798 }
7799
7800 #[doc = "IRQ1-DS Pin Deep Standby Cancel Flag"]
7801 #[inline(always)]
7802 pub fn dirq1f(
7803 self,
7804 ) -> crate::common::RegisterField<
7805 1,
7806 0x1,
7807 1,
7808 0,
7809 dpsifr0::Dirq1F,
7810 dpsifr0::Dirq1F,
7811 Dpsifr0_SPEC,
7812 crate::common::RW,
7813 > {
7814 crate::common::RegisterField::<
7815 1,
7816 0x1,
7817 1,
7818 0,
7819 dpsifr0::Dirq1F,
7820 dpsifr0::Dirq1F,
7821 Dpsifr0_SPEC,
7822 crate::common::RW,
7823 >::from_register(self, 0)
7824 }
7825
7826 #[doc = "IRQ4-DS Pin Deep Standby Cancel Flag"]
7827 #[inline(always)]
7828 pub fn dirq4f(
7829 self,
7830 ) -> crate::common::RegisterField<
7831 4,
7832 0x1,
7833 1,
7834 0,
7835 dpsifr0::Dirq4F,
7836 dpsifr0::Dirq4F,
7837 Dpsifr0_SPEC,
7838 crate::common::RW,
7839 > {
7840 crate::common::RegisterField::<
7841 4,
7842 0x1,
7843 1,
7844 0,
7845 dpsifr0::Dirq4F,
7846 dpsifr0::Dirq4F,
7847 Dpsifr0_SPEC,
7848 crate::common::RW,
7849 >::from_register(self, 0)
7850 }
7851
7852 #[doc = "IRQ5-DS Pin Deep Standby Cancel Flag"]
7853 #[inline(always)]
7854 pub fn dirq5f(
7855 self,
7856 ) -> crate::common::RegisterField<
7857 5,
7858 0x1,
7859 1,
7860 0,
7861 dpsifr0::Dirq5F,
7862 dpsifr0::Dirq5F,
7863 Dpsifr0_SPEC,
7864 crate::common::RW,
7865 > {
7866 crate::common::RegisterField::<
7867 5,
7868 0x1,
7869 1,
7870 0,
7871 dpsifr0::Dirq5F,
7872 dpsifr0::Dirq5F,
7873 Dpsifr0_SPEC,
7874 crate::common::RW,
7875 >::from_register(self, 0)
7876 }
7877
7878 #[doc = "IRQ6-DS Pin Deep Standby Cancel Flag"]
7879 #[inline(always)]
7880 pub fn dirq6f(
7881 self,
7882 ) -> crate::common::RegisterField<
7883 6,
7884 0x1,
7885 1,
7886 0,
7887 dpsifr0::Dirq6F,
7888 dpsifr0::Dirq6F,
7889 Dpsifr0_SPEC,
7890 crate::common::RW,
7891 > {
7892 crate::common::RegisterField::<
7893 6,
7894 0x1,
7895 1,
7896 0,
7897 dpsifr0::Dirq6F,
7898 dpsifr0::Dirq6F,
7899 Dpsifr0_SPEC,
7900 crate::common::RW,
7901 >::from_register(self, 0)
7902 }
7903
7904 #[doc = "IRQ7-DS Pin Deep Standby Cancel Flag"]
7905 #[inline(always)]
7906 pub fn dirq7f(
7907 self,
7908 ) -> crate::common::RegisterField<
7909 7,
7910 0x1,
7911 1,
7912 0,
7913 dpsifr0::Dirq7F,
7914 dpsifr0::Dirq7F,
7915 Dpsifr0_SPEC,
7916 crate::common::RW,
7917 > {
7918 crate::common::RegisterField::<
7919 7,
7920 0x1,
7921 1,
7922 0,
7923 dpsifr0::Dirq7F,
7924 dpsifr0::Dirq7F,
7925 Dpsifr0_SPEC,
7926 crate::common::RW,
7927 >::from_register(self, 0)
7928 }
7929}
7930impl ::core::default::Default for Dpsifr0 {
7931 #[inline(always)]
7932 fn default() -> Dpsifr0 {
7933 <crate::RegValueT<Dpsifr0_SPEC> as RegisterValue<_>>::new(0)
7934 }
7935}
7936pub mod dpsifr0 {
7937
7938 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7939 pub struct Dirq0F_SPEC;
7940 pub type Dirq0F = crate::EnumBitfieldStruct<u8, Dirq0F_SPEC>;
7941 impl Dirq0F {
7942 #[doc = "The cancel request is not generated"]
7943 pub const _0: Self = Self::new(0);
7944
7945 #[doc = "The cancel request is generated"]
7946 pub const _1: Self = Self::new(1);
7947 }
7948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7949 pub struct Dirq1F_SPEC;
7950 pub type Dirq1F = crate::EnumBitfieldStruct<u8, Dirq1F_SPEC>;
7951 impl Dirq1F {
7952 #[doc = "The cancel request is not generated"]
7953 pub const _0: Self = Self::new(0);
7954
7955 #[doc = "The cancel request is generated"]
7956 pub const _1: Self = Self::new(1);
7957 }
7958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7959 pub struct Dirq4F_SPEC;
7960 pub type Dirq4F = crate::EnumBitfieldStruct<u8, Dirq4F_SPEC>;
7961 impl Dirq4F {
7962 #[doc = "The cancel request is not generated"]
7963 pub const _0: Self = Self::new(0);
7964
7965 #[doc = "The cancel request is generated"]
7966 pub const _1: Self = Self::new(1);
7967 }
7968 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7969 pub struct Dirq5F_SPEC;
7970 pub type Dirq5F = crate::EnumBitfieldStruct<u8, Dirq5F_SPEC>;
7971 impl Dirq5F {
7972 #[doc = "The cancel request is not generated"]
7973 pub const _0: Self = Self::new(0);
7974
7975 #[doc = "The cancel request is generated"]
7976 pub const _1: Self = Self::new(1);
7977 }
7978 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7979 pub struct Dirq6F_SPEC;
7980 pub type Dirq6F = crate::EnumBitfieldStruct<u8, Dirq6F_SPEC>;
7981 impl Dirq6F {
7982 #[doc = "The cancel request is not generated"]
7983 pub const _0: Self = Self::new(0);
7984
7985 #[doc = "The cancel request is generated"]
7986 pub const _1: Self = Self::new(1);
7987 }
7988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7989 pub struct Dirq7F_SPEC;
7990 pub type Dirq7F = crate::EnumBitfieldStruct<u8, Dirq7F_SPEC>;
7991 impl Dirq7F {
7992 #[doc = "The cancel request is not generated"]
7993 pub const _0: Self = Self::new(0);
7994
7995 #[doc = "The cancel request is generated"]
7996 pub const _1: Self = Self::new(1);
7997 }
7998}
7999#[doc(hidden)]
8000#[derive(Copy, Clone, Eq, PartialEq)]
8001pub struct Dpsifr1_SPEC;
8002impl crate::sealed::RegSpec for Dpsifr1_SPEC {
8003 type DataType = u8;
8004}
8005
8006#[doc = "Deep Standby Interrupt Flag Register 1"]
8007pub type Dpsifr1 = crate::RegValueT<Dpsifr1_SPEC>;
8008
8009impl Dpsifr1 {
8010 #[doc = "IRQ8-DS Pin Deep Standby Cancel Flag"]
8011 #[inline(always)]
8012 pub fn dirq8f(
8013 self,
8014 ) -> crate::common::RegisterField<
8015 0,
8016 0x1,
8017 1,
8018 0,
8019 dpsifr1::Dirq8F,
8020 dpsifr1::Dirq8F,
8021 Dpsifr1_SPEC,
8022 crate::common::RW,
8023 > {
8024 crate::common::RegisterField::<
8025 0,
8026 0x1,
8027 1,
8028 0,
8029 dpsifr1::Dirq8F,
8030 dpsifr1::Dirq8F,
8031 Dpsifr1_SPEC,
8032 crate::common::RW,
8033 >::from_register(self, 0)
8034 }
8035
8036 #[doc = "IRQ9-DS Pin Deep Standby Cancel Flag"]
8037 #[inline(always)]
8038 pub fn dirq9f(
8039 self,
8040 ) -> crate::common::RegisterField<
8041 1,
8042 0x1,
8043 1,
8044 0,
8045 dpsifr1::Dirq9F,
8046 dpsifr1::Dirq9F,
8047 Dpsifr1_SPEC,
8048 crate::common::RW,
8049 > {
8050 crate::common::RegisterField::<
8051 1,
8052 0x1,
8053 1,
8054 0,
8055 dpsifr1::Dirq9F,
8056 dpsifr1::Dirq9F,
8057 Dpsifr1_SPEC,
8058 crate::common::RW,
8059 >::from_register(self, 0)
8060 }
8061
8062 #[doc = "IRQ10-DS Pin Deep Standby Cancel Flag"]
8063 #[inline(always)]
8064 pub fn dirq10f(
8065 self,
8066 ) -> crate::common::RegisterField<
8067 2,
8068 0x1,
8069 1,
8070 0,
8071 dpsifr1::Dirq10F,
8072 dpsifr1::Dirq10F,
8073 Dpsifr1_SPEC,
8074 crate::common::RW,
8075 > {
8076 crate::common::RegisterField::<
8077 2,
8078 0x1,
8079 1,
8080 0,
8081 dpsifr1::Dirq10F,
8082 dpsifr1::Dirq10F,
8083 Dpsifr1_SPEC,
8084 crate::common::RW,
8085 >::from_register(self, 0)
8086 }
8087
8088 #[doc = "IRQ11-DS Pin Deep Standby Cancel Flag"]
8089 #[inline(always)]
8090 pub fn dirq11f(
8091 self,
8092 ) -> crate::common::RegisterField<
8093 3,
8094 0x1,
8095 1,
8096 0,
8097 dpsifr1::Dirq11F,
8098 dpsifr1::Dirq11F,
8099 Dpsifr1_SPEC,
8100 crate::common::RW,
8101 > {
8102 crate::common::RegisterField::<
8103 3,
8104 0x1,
8105 1,
8106 0,
8107 dpsifr1::Dirq11F,
8108 dpsifr1::Dirq11F,
8109 Dpsifr1_SPEC,
8110 crate::common::RW,
8111 >::from_register(self, 0)
8112 }
8113
8114 #[doc = "IRQ12-DS Pin Deep Standby Cancel Flag"]
8115 #[inline(always)]
8116 pub fn dirq12f(
8117 self,
8118 ) -> crate::common::RegisterField<
8119 4,
8120 0x1,
8121 1,
8122 0,
8123 dpsifr1::Dirq12F,
8124 dpsifr1::Dirq12F,
8125 Dpsifr1_SPEC,
8126 crate::common::RW,
8127 > {
8128 crate::common::RegisterField::<
8129 4,
8130 0x1,
8131 1,
8132 0,
8133 dpsifr1::Dirq12F,
8134 dpsifr1::Dirq12F,
8135 Dpsifr1_SPEC,
8136 crate::common::RW,
8137 >::from_register(self, 0)
8138 }
8139
8140 #[doc = "IRQ14-DS Pin Deep Standby Cancel Flag"]
8141 #[inline(always)]
8142 pub fn dirq14f(
8143 self,
8144 ) -> crate::common::RegisterField<
8145 6,
8146 0x1,
8147 1,
8148 0,
8149 dpsifr1::Dirq14F,
8150 dpsifr1::Dirq14F,
8151 Dpsifr1_SPEC,
8152 crate::common::RW,
8153 > {
8154 crate::common::RegisterField::<
8155 6,
8156 0x1,
8157 1,
8158 0,
8159 dpsifr1::Dirq14F,
8160 dpsifr1::Dirq14F,
8161 Dpsifr1_SPEC,
8162 crate::common::RW,
8163 >::from_register(self, 0)
8164 }
8165}
8166impl ::core::default::Default for Dpsifr1 {
8167 #[inline(always)]
8168 fn default() -> Dpsifr1 {
8169 <crate::RegValueT<Dpsifr1_SPEC> as RegisterValue<_>>::new(0)
8170 }
8171}
8172pub mod dpsifr1 {
8173
8174 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8175 pub struct Dirq8F_SPEC;
8176 pub type Dirq8F = crate::EnumBitfieldStruct<u8, Dirq8F_SPEC>;
8177 impl Dirq8F {
8178 #[doc = "The cancel request is not generated"]
8179 pub const _0: Self = Self::new(0);
8180
8181 #[doc = "The cancel request is generated"]
8182 pub const _1: Self = Self::new(1);
8183 }
8184 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8185 pub struct Dirq9F_SPEC;
8186 pub type Dirq9F = crate::EnumBitfieldStruct<u8, Dirq9F_SPEC>;
8187 impl Dirq9F {
8188 #[doc = "The cancel request is not generated"]
8189 pub const _0: Self = Self::new(0);
8190
8191 #[doc = "The cancel request is generated"]
8192 pub const _1: Self = Self::new(1);
8193 }
8194 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8195 pub struct Dirq10F_SPEC;
8196 pub type Dirq10F = crate::EnumBitfieldStruct<u8, Dirq10F_SPEC>;
8197 impl Dirq10F {
8198 #[doc = "The cancel request is not generated"]
8199 pub const _0: Self = Self::new(0);
8200
8201 #[doc = "The cancel request is generated"]
8202 pub const _1: Self = Self::new(1);
8203 }
8204 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8205 pub struct Dirq11F_SPEC;
8206 pub type Dirq11F = crate::EnumBitfieldStruct<u8, Dirq11F_SPEC>;
8207 impl Dirq11F {
8208 #[doc = "The cancel request is not generated"]
8209 pub const _0: Self = Self::new(0);
8210
8211 #[doc = "The cancel request is generated"]
8212 pub const _1: Self = Self::new(1);
8213 }
8214 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8215 pub struct Dirq12F_SPEC;
8216 pub type Dirq12F = crate::EnumBitfieldStruct<u8, Dirq12F_SPEC>;
8217 impl Dirq12F {
8218 #[doc = "The cancel request is not generated"]
8219 pub const _0: Self = Self::new(0);
8220
8221 #[doc = "The cancel request is generated"]
8222 pub const _1: Self = Self::new(1);
8223 }
8224 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8225 pub struct Dirq14F_SPEC;
8226 pub type Dirq14F = crate::EnumBitfieldStruct<u8, Dirq14F_SPEC>;
8227 impl Dirq14F {
8228 #[doc = "The cancel request is not generated"]
8229 pub const _0: Self = Self::new(0);
8230
8231 #[doc = "The cancel request is generated"]
8232 pub const _1: Self = Self::new(1);
8233 }
8234}
8235#[doc(hidden)]
8236#[derive(Copy, Clone, Eq, PartialEq)]
8237pub struct Dpsifr2_SPEC;
8238impl crate::sealed::RegSpec for Dpsifr2_SPEC {
8239 type DataType = u8;
8240}
8241
8242#[doc = "Deep Software Standby Interrupt Flag Register 2"]
8243pub type Dpsifr2 = crate::RegValueT<Dpsifr2_SPEC>;
8244
8245impl Dpsifr2 {
8246 #[doc = "LVD1 Deep Software Standby Cancel Flag"]
8247 #[inline(always)]
8248 pub fn dlvd1if(
8249 self,
8250 ) -> crate::common::RegisterField<
8251 0,
8252 0x1,
8253 1,
8254 0,
8255 dpsifr2::Dlvd1If,
8256 dpsifr2::Dlvd1If,
8257 Dpsifr2_SPEC,
8258 crate::common::RW,
8259 > {
8260 crate::common::RegisterField::<
8261 0,
8262 0x1,
8263 1,
8264 0,
8265 dpsifr2::Dlvd1If,
8266 dpsifr2::Dlvd1If,
8267 Dpsifr2_SPEC,
8268 crate::common::RW,
8269 >::from_register(self, 0)
8270 }
8271
8272 #[doc = "LVD2 Deep Software Standby Cancel Flag"]
8273 #[inline(always)]
8274 pub fn dlvd2if(
8275 self,
8276 ) -> crate::common::RegisterField<
8277 1,
8278 0x1,
8279 1,
8280 0,
8281 dpsifr2::Dlvd2If,
8282 dpsifr2::Dlvd2If,
8283 Dpsifr2_SPEC,
8284 crate::common::RW,
8285 > {
8286 crate::common::RegisterField::<
8287 1,
8288 0x1,
8289 1,
8290 0,
8291 dpsifr2::Dlvd2If,
8292 dpsifr2::Dlvd2If,
8293 Dpsifr2_SPEC,
8294 crate::common::RW,
8295 >::from_register(self, 0)
8296 }
8297
8298 #[doc = "RTC Interval Interrupt Deep Software Standby Cancel Flag"]
8299 #[inline(always)]
8300 pub fn drtciif(
8301 self,
8302 ) -> crate::common::RegisterField<
8303 2,
8304 0x1,
8305 1,
8306 0,
8307 dpsifr2::Drtciif,
8308 dpsifr2::Drtciif,
8309 Dpsifr2_SPEC,
8310 crate::common::RW,
8311 > {
8312 crate::common::RegisterField::<
8313 2,
8314 0x1,
8315 1,
8316 0,
8317 dpsifr2::Drtciif,
8318 dpsifr2::Drtciif,
8319 Dpsifr2_SPEC,
8320 crate::common::RW,
8321 >::from_register(self, 0)
8322 }
8323
8324 #[doc = "RTC Alarm Interrupt Deep Software Standby Cancel Flag"]
8325 #[inline(always)]
8326 pub fn drtcaif(
8327 self,
8328 ) -> crate::common::RegisterField<
8329 3,
8330 0x1,
8331 1,
8332 0,
8333 dpsifr2::Drtcaif,
8334 dpsifr2::Drtcaif,
8335 Dpsifr2_SPEC,
8336 crate::common::RW,
8337 > {
8338 crate::common::RegisterField::<
8339 3,
8340 0x1,
8341 1,
8342 0,
8343 dpsifr2::Drtcaif,
8344 dpsifr2::Drtcaif,
8345 Dpsifr2_SPEC,
8346 crate::common::RW,
8347 >::from_register(self, 0)
8348 }
8349
8350 #[doc = "NMI Pin Deep Software Standby Cancel Flag"]
8351 #[inline(always)]
8352 pub fn dnmif(
8353 self,
8354 ) -> crate::common::RegisterField<
8355 4,
8356 0x1,
8357 1,
8358 0,
8359 dpsifr2::Dnmif,
8360 dpsifr2::Dnmif,
8361 Dpsifr2_SPEC,
8362 crate::common::RW,
8363 > {
8364 crate::common::RegisterField::<
8365 4,
8366 0x1,
8367 1,
8368 0,
8369 dpsifr2::Dnmif,
8370 dpsifr2::Dnmif,
8371 Dpsifr2_SPEC,
8372 crate::common::RW,
8373 >::from_register(self, 0)
8374 }
8375}
8376impl ::core::default::Default for Dpsifr2 {
8377 #[inline(always)]
8378 fn default() -> Dpsifr2 {
8379 <crate::RegValueT<Dpsifr2_SPEC> as RegisterValue<_>>::new(0)
8380 }
8381}
8382pub mod dpsifr2 {
8383
8384 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8385 pub struct Dlvd1If_SPEC;
8386 pub type Dlvd1If = crate::EnumBitfieldStruct<u8, Dlvd1If_SPEC>;
8387 impl Dlvd1If {
8388 #[doc = "The cancel request is not generated"]
8389 pub const _0: Self = Self::new(0);
8390
8391 #[doc = "The cancel request is generated"]
8392 pub const _1: Self = Self::new(1);
8393 }
8394 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8395 pub struct Dlvd2If_SPEC;
8396 pub type Dlvd2If = crate::EnumBitfieldStruct<u8, Dlvd2If_SPEC>;
8397 impl Dlvd2If {
8398 #[doc = "The cancel request is not generated"]
8399 pub const _0: Self = Self::new(0);
8400
8401 #[doc = "The cancel request is generated"]
8402 pub const _1: Self = Self::new(1);
8403 }
8404 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8405 pub struct Drtciif_SPEC;
8406 pub type Drtciif = crate::EnumBitfieldStruct<u8, Drtciif_SPEC>;
8407 impl Drtciif {
8408 #[doc = "The cancel request is not generated"]
8409 pub const _0: Self = Self::new(0);
8410
8411 #[doc = "The cancel request is generated"]
8412 pub const _1: Self = Self::new(1);
8413 }
8414 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8415 pub struct Drtcaif_SPEC;
8416 pub type Drtcaif = crate::EnumBitfieldStruct<u8, Drtcaif_SPEC>;
8417 impl Drtcaif {
8418 #[doc = "The cancel request is not generated"]
8419 pub const _0: Self = Self::new(0);
8420
8421 #[doc = "The cancel request is generated"]
8422 pub const _1: Self = Self::new(1);
8423 }
8424 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8425 pub struct Dnmif_SPEC;
8426 pub type Dnmif = crate::EnumBitfieldStruct<u8, Dnmif_SPEC>;
8427 impl Dnmif {
8428 #[doc = "The cancel request is not generated"]
8429 pub const _0: Self = Self::new(0);
8430
8431 #[doc = "The cancel request is generated"]
8432 pub const _1: Self = Self::new(1);
8433 }
8434}
8435#[doc(hidden)]
8436#[derive(Copy, Clone, Eq, PartialEq)]
8437pub struct Dpsifr3_SPEC;
8438impl crate::sealed::RegSpec for Dpsifr3_SPEC {
8439 type DataType = u8;
8440}
8441
8442#[doc = "Deep Standby Interrupt Flag Register 3"]
8443pub type Dpsifr3 = crate::RegValueT<Dpsifr3_SPEC>;
8444
8445impl Dpsifr3 {
8446 #[doc = "USBFS0 Suspend/Resume Deep Standby Cancel Flag"]
8447 #[inline(always)]
8448 pub fn dusbfs0if(
8449 self,
8450 ) -> crate::common::RegisterField<
8451 0,
8452 0x1,
8453 1,
8454 0,
8455 dpsifr3::Dusbfs0If,
8456 dpsifr3::Dusbfs0If,
8457 Dpsifr3_SPEC,
8458 crate::common::RW,
8459 > {
8460 crate::common::RegisterField::<
8461 0,
8462 0x1,
8463 1,
8464 0,
8465 dpsifr3::Dusbfs0If,
8466 dpsifr3::Dusbfs0If,
8467 Dpsifr3_SPEC,
8468 crate::common::RW,
8469 >::from_register(self, 0)
8470 }
8471
8472 #[doc = "AGT1 Underflow Deep Standby Cancel Flag"]
8473 #[inline(always)]
8474 pub fn dagt1if(
8475 self,
8476 ) -> crate::common::RegisterField<
8477 2,
8478 0x1,
8479 1,
8480 0,
8481 dpsifr3::Dagt1If,
8482 dpsifr3::Dagt1If,
8483 Dpsifr3_SPEC,
8484 crate::common::RW,
8485 > {
8486 crate::common::RegisterField::<
8487 2,
8488 0x1,
8489 1,
8490 0,
8491 dpsifr3::Dagt1If,
8492 dpsifr3::Dagt1If,
8493 Dpsifr3_SPEC,
8494 crate::common::RW,
8495 >::from_register(self, 0)
8496 }
8497}
8498impl ::core::default::Default for Dpsifr3 {
8499 #[inline(always)]
8500 fn default() -> Dpsifr3 {
8501 <crate::RegValueT<Dpsifr3_SPEC> as RegisterValue<_>>::new(0)
8502 }
8503}
8504pub mod dpsifr3 {
8505
8506 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8507 pub struct Dusbfs0If_SPEC;
8508 pub type Dusbfs0If = crate::EnumBitfieldStruct<u8, Dusbfs0If_SPEC>;
8509 impl Dusbfs0If {
8510 #[doc = "The cancel request is not generated."]
8511 pub const _0: Self = Self::new(0);
8512
8513 #[doc = "The cancel request is generated."]
8514 pub const _1: Self = Self::new(1);
8515 }
8516 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8517 pub struct Dagt1If_SPEC;
8518 pub type Dagt1If = crate::EnumBitfieldStruct<u8, Dagt1If_SPEC>;
8519 impl Dagt1If {
8520 #[doc = "The cancel request is not generated."]
8521 pub const _0: Self = Self::new(0);
8522
8523 #[doc = "The cancel request is generated."]
8524 pub const _1: Self = Self::new(1);
8525 }
8526}
8527#[doc(hidden)]
8528#[derive(Copy, Clone, Eq, PartialEq)]
8529pub struct Dpsiegr0_SPEC;
8530impl crate::sealed::RegSpec for Dpsiegr0_SPEC {
8531 type DataType = u8;
8532}
8533
8534#[doc = "Deep Standby Interrupt Edge Register 0"]
8535pub type Dpsiegr0 = crate::RegValueT<Dpsiegr0_SPEC>;
8536
8537impl Dpsiegr0 {
8538 #[doc = "IRQ0-DS Pin Edge Select"]
8539 #[inline(always)]
8540 pub fn dirq0eg(
8541 self,
8542 ) -> crate::common::RegisterField<
8543 0,
8544 0x1,
8545 1,
8546 0,
8547 dpsiegr0::Dirq0Eg,
8548 dpsiegr0::Dirq0Eg,
8549 Dpsiegr0_SPEC,
8550 crate::common::RW,
8551 > {
8552 crate::common::RegisterField::<
8553 0,
8554 0x1,
8555 1,
8556 0,
8557 dpsiegr0::Dirq0Eg,
8558 dpsiegr0::Dirq0Eg,
8559 Dpsiegr0_SPEC,
8560 crate::common::RW,
8561 >::from_register(self, 0)
8562 }
8563
8564 #[doc = "IRQ1-DS Pin Edge Select"]
8565 #[inline(always)]
8566 pub fn dirq1eg(
8567 self,
8568 ) -> crate::common::RegisterField<
8569 1,
8570 0x1,
8571 1,
8572 0,
8573 dpsiegr0::Dirq1Eg,
8574 dpsiegr0::Dirq1Eg,
8575 Dpsiegr0_SPEC,
8576 crate::common::RW,
8577 > {
8578 crate::common::RegisterField::<
8579 1,
8580 0x1,
8581 1,
8582 0,
8583 dpsiegr0::Dirq1Eg,
8584 dpsiegr0::Dirq1Eg,
8585 Dpsiegr0_SPEC,
8586 crate::common::RW,
8587 >::from_register(self, 0)
8588 }
8589
8590 #[doc = "IRQ4-DS Pin Edge Select"]
8591 #[inline(always)]
8592 pub fn dirq4eg(
8593 self,
8594 ) -> crate::common::RegisterField<
8595 4,
8596 0x1,
8597 1,
8598 0,
8599 dpsiegr0::Dirq4Eg,
8600 dpsiegr0::Dirq4Eg,
8601 Dpsiegr0_SPEC,
8602 crate::common::RW,
8603 > {
8604 crate::common::RegisterField::<
8605 4,
8606 0x1,
8607 1,
8608 0,
8609 dpsiegr0::Dirq4Eg,
8610 dpsiegr0::Dirq4Eg,
8611 Dpsiegr0_SPEC,
8612 crate::common::RW,
8613 >::from_register(self, 0)
8614 }
8615
8616 #[doc = "IRQ5-DS Pin Edge Select"]
8617 #[inline(always)]
8618 pub fn dirq5eg(
8619 self,
8620 ) -> crate::common::RegisterField<
8621 5,
8622 0x1,
8623 1,
8624 0,
8625 dpsiegr0::Dirq5Eg,
8626 dpsiegr0::Dirq5Eg,
8627 Dpsiegr0_SPEC,
8628 crate::common::RW,
8629 > {
8630 crate::common::RegisterField::<
8631 5,
8632 0x1,
8633 1,
8634 0,
8635 dpsiegr0::Dirq5Eg,
8636 dpsiegr0::Dirq5Eg,
8637 Dpsiegr0_SPEC,
8638 crate::common::RW,
8639 >::from_register(self, 0)
8640 }
8641
8642 #[doc = "IRQ6-DS Pin Edge Select"]
8643 #[inline(always)]
8644 pub fn dirq6eg(
8645 self,
8646 ) -> crate::common::RegisterField<
8647 6,
8648 0x1,
8649 1,
8650 0,
8651 dpsiegr0::Dirq6Eg,
8652 dpsiegr0::Dirq6Eg,
8653 Dpsiegr0_SPEC,
8654 crate::common::RW,
8655 > {
8656 crate::common::RegisterField::<
8657 6,
8658 0x1,
8659 1,
8660 0,
8661 dpsiegr0::Dirq6Eg,
8662 dpsiegr0::Dirq6Eg,
8663 Dpsiegr0_SPEC,
8664 crate::common::RW,
8665 >::from_register(self, 0)
8666 }
8667
8668 #[doc = "IRQ7-DS Pin Edge Select"]
8669 #[inline(always)]
8670 pub fn dirq7eg(
8671 self,
8672 ) -> crate::common::RegisterField<
8673 7,
8674 0x1,
8675 1,
8676 0,
8677 dpsiegr0::Dirq7Eg,
8678 dpsiegr0::Dirq7Eg,
8679 Dpsiegr0_SPEC,
8680 crate::common::RW,
8681 > {
8682 crate::common::RegisterField::<
8683 7,
8684 0x1,
8685 1,
8686 0,
8687 dpsiegr0::Dirq7Eg,
8688 dpsiegr0::Dirq7Eg,
8689 Dpsiegr0_SPEC,
8690 crate::common::RW,
8691 >::from_register(self, 0)
8692 }
8693}
8694impl ::core::default::Default for Dpsiegr0 {
8695 #[inline(always)]
8696 fn default() -> Dpsiegr0 {
8697 <crate::RegValueT<Dpsiegr0_SPEC> as RegisterValue<_>>::new(0)
8698 }
8699}
8700pub mod dpsiegr0 {
8701
8702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8703 pub struct Dirq0Eg_SPEC;
8704 pub type Dirq0Eg = crate::EnumBitfieldStruct<u8, Dirq0Eg_SPEC>;
8705 impl Dirq0Eg {
8706 #[doc = "A cancel request is generated at a falling edge"]
8707 pub const _0: Self = Self::new(0);
8708
8709 #[doc = "A cancel request is generated at a rising edge"]
8710 pub const _1: Self = Self::new(1);
8711 }
8712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8713 pub struct Dirq1Eg_SPEC;
8714 pub type Dirq1Eg = crate::EnumBitfieldStruct<u8, Dirq1Eg_SPEC>;
8715 impl Dirq1Eg {
8716 #[doc = "A cancel request is generated at a falling edge"]
8717 pub const _0: Self = Self::new(0);
8718
8719 #[doc = "A cancel request is generated at a rising edge"]
8720 pub const _1: Self = Self::new(1);
8721 }
8722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8723 pub struct Dirq4Eg_SPEC;
8724 pub type Dirq4Eg = crate::EnumBitfieldStruct<u8, Dirq4Eg_SPEC>;
8725 impl Dirq4Eg {
8726 #[doc = "A cancel request is generated at a falling edge"]
8727 pub const _0: Self = Self::new(0);
8728
8729 #[doc = "A cancel request is generated at a rising edge"]
8730 pub const _1: Self = Self::new(1);
8731 }
8732 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8733 pub struct Dirq5Eg_SPEC;
8734 pub type Dirq5Eg = crate::EnumBitfieldStruct<u8, Dirq5Eg_SPEC>;
8735 impl Dirq5Eg {
8736 #[doc = "A cancel request is generated at a falling edge"]
8737 pub const _0: Self = Self::new(0);
8738
8739 #[doc = "A cancel request is generated at a rising edge"]
8740 pub const _1: Self = Self::new(1);
8741 }
8742 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8743 pub struct Dirq6Eg_SPEC;
8744 pub type Dirq6Eg = crate::EnumBitfieldStruct<u8, Dirq6Eg_SPEC>;
8745 impl Dirq6Eg {
8746 #[doc = "A cancel request is generated at a falling edge"]
8747 pub const _0: Self = Self::new(0);
8748
8749 #[doc = "A cancel request is generated at a rising edge"]
8750 pub const _1: Self = Self::new(1);
8751 }
8752 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8753 pub struct Dirq7Eg_SPEC;
8754 pub type Dirq7Eg = crate::EnumBitfieldStruct<u8, Dirq7Eg_SPEC>;
8755 impl Dirq7Eg {
8756 #[doc = "A cancel request is generated at a falling edge"]
8757 pub const _0: Self = Self::new(0);
8758
8759 #[doc = "A cancel request is generated at a rising edge"]
8760 pub const _1: Self = Self::new(1);
8761 }
8762}
8763#[doc(hidden)]
8764#[derive(Copy, Clone, Eq, PartialEq)]
8765pub struct Dpsiegr1_SPEC;
8766impl crate::sealed::RegSpec for Dpsiegr1_SPEC {
8767 type DataType = u8;
8768}
8769
8770#[doc = "Deep Standby Interrupt Edge Register 1"]
8771pub type Dpsiegr1 = crate::RegValueT<Dpsiegr1_SPEC>;
8772
8773impl Dpsiegr1 {
8774 #[doc = "IRQ8-DS Pin Edge Select"]
8775 #[inline(always)]
8776 pub fn dirq8eg(
8777 self,
8778 ) -> crate::common::RegisterField<
8779 0,
8780 0x1,
8781 1,
8782 0,
8783 dpsiegr1::Dirq8Eg,
8784 dpsiegr1::Dirq8Eg,
8785 Dpsiegr1_SPEC,
8786 crate::common::RW,
8787 > {
8788 crate::common::RegisterField::<
8789 0,
8790 0x1,
8791 1,
8792 0,
8793 dpsiegr1::Dirq8Eg,
8794 dpsiegr1::Dirq8Eg,
8795 Dpsiegr1_SPEC,
8796 crate::common::RW,
8797 >::from_register(self, 0)
8798 }
8799
8800 #[doc = "IRQ9-DS Pin Edge Select"]
8801 #[inline(always)]
8802 pub fn dirq9eg(
8803 self,
8804 ) -> crate::common::RegisterField<
8805 1,
8806 0x1,
8807 1,
8808 0,
8809 dpsiegr1::Dirq9Eg,
8810 dpsiegr1::Dirq9Eg,
8811 Dpsiegr1_SPEC,
8812 crate::common::RW,
8813 > {
8814 crate::common::RegisterField::<
8815 1,
8816 0x1,
8817 1,
8818 0,
8819 dpsiegr1::Dirq9Eg,
8820 dpsiegr1::Dirq9Eg,
8821 Dpsiegr1_SPEC,
8822 crate::common::RW,
8823 >::from_register(self, 0)
8824 }
8825
8826 #[doc = "IRQ10-DS Pin Edge Select"]
8827 #[inline(always)]
8828 pub fn dirq10eg(
8829 self,
8830 ) -> crate::common::RegisterField<
8831 2,
8832 0x1,
8833 1,
8834 0,
8835 dpsiegr1::Dirq10Eg,
8836 dpsiegr1::Dirq10Eg,
8837 Dpsiegr1_SPEC,
8838 crate::common::RW,
8839 > {
8840 crate::common::RegisterField::<
8841 2,
8842 0x1,
8843 1,
8844 0,
8845 dpsiegr1::Dirq10Eg,
8846 dpsiegr1::Dirq10Eg,
8847 Dpsiegr1_SPEC,
8848 crate::common::RW,
8849 >::from_register(self, 0)
8850 }
8851
8852 #[doc = "IRQ11-DS Pin Edge Select"]
8853 #[inline(always)]
8854 pub fn dirq11eg(
8855 self,
8856 ) -> crate::common::RegisterField<
8857 3,
8858 0x1,
8859 1,
8860 0,
8861 dpsiegr1::Dirq11Eg,
8862 dpsiegr1::Dirq11Eg,
8863 Dpsiegr1_SPEC,
8864 crate::common::RW,
8865 > {
8866 crate::common::RegisterField::<
8867 3,
8868 0x1,
8869 1,
8870 0,
8871 dpsiegr1::Dirq11Eg,
8872 dpsiegr1::Dirq11Eg,
8873 Dpsiegr1_SPEC,
8874 crate::common::RW,
8875 >::from_register(self, 0)
8876 }
8877
8878 #[doc = "IRQ12-DS Pin Edge Select"]
8879 #[inline(always)]
8880 pub fn dirq12eg(
8881 self,
8882 ) -> crate::common::RegisterField<
8883 4,
8884 0x1,
8885 1,
8886 0,
8887 dpsiegr1::Dirq12Eg,
8888 dpsiegr1::Dirq12Eg,
8889 Dpsiegr1_SPEC,
8890 crate::common::RW,
8891 > {
8892 crate::common::RegisterField::<
8893 4,
8894 0x1,
8895 1,
8896 0,
8897 dpsiegr1::Dirq12Eg,
8898 dpsiegr1::Dirq12Eg,
8899 Dpsiegr1_SPEC,
8900 crate::common::RW,
8901 >::from_register(self, 0)
8902 }
8903
8904 #[doc = "IRQ14-DS Pin Edge Select"]
8905 #[inline(always)]
8906 pub fn dirq14eg(
8907 self,
8908 ) -> crate::common::RegisterField<
8909 6,
8910 0x1,
8911 1,
8912 0,
8913 dpsiegr1::Dirq14Eg,
8914 dpsiegr1::Dirq14Eg,
8915 Dpsiegr1_SPEC,
8916 crate::common::RW,
8917 > {
8918 crate::common::RegisterField::<
8919 6,
8920 0x1,
8921 1,
8922 0,
8923 dpsiegr1::Dirq14Eg,
8924 dpsiegr1::Dirq14Eg,
8925 Dpsiegr1_SPEC,
8926 crate::common::RW,
8927 >::from_register(self, 0)
8928 }
8929}
8930impl ::core::default::Default for Dpsiegr1 {
8931 #[inline(always)]
8932 fn default() -> Dpsiegr1 {
8933 <crate::RegValueT<Dpsiegr1_SPEC> as RegisterValue<_>>::new(0)
8934 }
8935}
8936pub mod dpsiegr1 {
8937
8938 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8939 pub struct Dirq8Eg_SPEC;
8940 pub type Dirq8Eg = crate::EnumBitfieldStruct<u8, Dirq8Eg_SPEC>;
8941 impl Dirq8Eg {
8942 #[doc = "A cancel request is generated at a falling edge."]
8943 pub const _0: Self = Self::new(0);
8944
8945 #[doc = "A cancel request is generated at a rising edge."]
8946 pub const _1: Self = Self::new(1);
8947 }
8948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8949 pub struct Dirq9Eg_SPEC;
8950 pub type Dirq9Eg = crate::EnumBitfieldStruct<u8, Dirq9Eg_SPEC>;
8951 impl Dirq9Eg {
8952 #[doc = "A cancel request is generated at a falling edge."]
8953 pub const _0: Self = Self::new(0);
8954
8955 #[doc = "A cancel request is generated at a rising edge."]
8956 pub const _1: Self = Self::new(1);
8957 }
8958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8959 pub struct Dirq10Eg_SPEC;
8960 pub type Dirq10Eg = crate::EnumBitfieldStruct<u8, Dirq10Eg_SPEC>;
8961 impl Dirq10Eg {
8962 #[doc = "A cancel request is generated at a falling edge."]
8963 pub const _0: Self = Self::new(0);
8964
8965 #[doc = "A cancel request is generated at a rising edge"]
8966 pub const _1: Self = Self::new(1);
8967 }
8968 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8969 pub struct Dirq11Eg_SPEC;
8970 pub type Dirq11Eg = crate::EnumBitfieldStruct<u8, Dirq11Eg_SPEC>;
8971 impl Dirq11Eg {
8972 #[doc = "A cancel request is generated at a falling edge."]
8973 pub const _0: Self = Self::new(0);
8974
8975 #[doc = "A cancel request is generated at a rising edge."]
8976 pub const _1: Self = Self::new(1);
8977 }
8978 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8979 pub struct Dirq12Eg_SPEC;
8980 pub type Dirq12Eg = crate::EnumBitfieldStruct<u8, Dirq12Eg_SPEC>;
8981 impl Dirq12Eg {
8982 #[doc = "A cancel request is generated at a falling edge."]
8983 pub const _0: Self = Self::new(0);
8984
8985 #[doc = "A cancel request is generated at a rising edge."]
8986 pub const _1: Self = Self::new(1);
8987 }
8988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
8989 pub struct Dirq14Eg_SPEC;
8990 pub type Dirq14Eg = crate::EnumBitfieldStruct<u8, Dirq14Eg_SPEC>;
8991 impl Dirq14Eg {
8992 #[doc = "A cancel request is generated at a falling edge."]
8993 pub const _0: Self = Self::new(0);
8994
8995 #[doc = "A cancel request is generated at a rising edge."]
8996 pub const _1: Self = Self::new(1);
8997 }
8998}
8999#[doc(hidden)]
9000#[derive(Copy, Clone, Eq, PartialEq)]
9001pub struct Dpsiegr2_SPEC;
9002impl crate::sealed::RegSpec for Dpsiegr2_SPEC {
9003 type DataType = u8;
9004}
9005
9006#[doc = "Deep Software Standby Interrupt Edge Register 2"]
9007pub type Dpsiegr2 = crate::RegValueT<Dpsiegr2_SPEC>;
9008
9009impl Dpsiegr2 {
9010 #[doc = "LVD1 Edge Select"]
9011 #[inline(always)]
9012 pub fn dlvd1eg(
9013 self,
9014 ) -> crate::common::RegisterField<
9015 0,
9016 0x1,
9017 1,
9018 0,
9019 dpsiegr2::Dlvd1Eg,
9020 dpsiegr2::Dlvd1Eg,
9021 Dpsiegr2_SPEC,
9022 crate::common::RW,
9023 > {
9024 crate::common::RegisterField::<
9025 0,
9026 0x1,
9027 1,
9028 0,
9029 dpsiegr2::Dlvd1Eg,
9030 dpsiegr2::Dlvd1Eg,
9031 Dpsiegr2_SPEC,
9032 crate::common::RW,
9033 >::from_register(self, 0)
9034 }
9035
9036 #[doc = "LVD2 Edge Select"]
9037 #[inline(always)]
9038 pub fn dlvd2eg(
9039 self,
9040 ) -> crate::common::RegisterField<
9041 1,
9042 0x1,
9043 1,
9044 0,
9045 dpsiegr2::Dlvd2Eg,
9046 dpsiegr2::Dlvd2Eg,
9047 Dpsiegr2_SPEC,
9048 crate::common::RW,
9049 > {
9050 crate::common::RegisterField::<
9051 1,
9052 0x1,
9053 1,
9054 0,
9055 dpsiegr2::Dlvd2Eg,
9056 dpsiegr2::Dlvd2Eg,
9057 Dpsiegr2_SPEC,
9058 crate::common::RW,
9059 >::from_register(self, 0)
9060 }
9061
9062 #[doc = "NMI Pin Edge Select"]
9063 #[inline(always)]
9064 pub fn dnmieg(
9065 self,
9066 ) -> crate::common::RegisterField<
9067 4,
9068 0x1,
9069 1,
9070 0,
9071 dpsiegr2::Dnmieg,
9072 dpsiegr2::Dnmieg,
9073 Dpsiegr2_SPEC,
9074 crate::common::RW,
9075 > {
9076 crate::common::RegisterField::<
9077 4,
9078 0x1,
9079 1,
9080 0,
9081 dpsiegr2::Dnmieg,
9082 dpsiegr2::Dnmieg,
9083 Dpsiegr2_SPEC,
9084 crate::common::RW,
9085 >::from_register(self, 0)
9086 }
9087}
9088impl ::core::default::Default for Dpsiegr2 {
9089 #[inline(always)]
9090 fn default() -> Dpsiegr2 {
9091 <crate::RegValueT<Dpsiegr2_SPEC> as RegisterValue<_>>::new(0)
9092 }
9093}
9094pub mod dpsiegr2 {
9095
9096 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9097 pub struct Dlvd1Eg_SPEC;
9098 pub type Dlvd1Eg = crate::EnumBitfieldStruct<u8, Dlvd1Eg_SPEC>;
9099 impl Dlvd1Eg {
9100 #[doc = "A cancel request is generated when VCC < Vdet1 (fall) is detected"]
9101 pub const _0: Self = Self::new(0);
9102
9103 #[doc = "A cancel request is generated when VCC ≥ Vdet1 (rise) is detected"]
9104 pub const _1: Self = Self::new(1);
9105 }
9106 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9107 pub struct Dlvd2Eg_SPEC;
9108 pub type Dlvd2Eg = crate::EnumBitfieldStruct<u8, Dlvd2Eg_SPEC>;
9109 impl Dlvd2Eg {
9110 #[doc = "A cancel request is generated when VCC < Vdet2 (fall) is detected"]
9111 pub const _0: Self = Self::new(0);
9112
9113 #[doc = "A cancel request is generated when VCC ≥ Vdet2 (rise) is detected"]
9114 pub const _1: Self = Self::new(1);
9115 }
9116 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9117 pub struct Dnmieg_SPEC;
9118 pub type Dnmieg = crate::EnumBitfieldStruct<u8, Dnmieg_SPEC>;
9119 impl Dnmieg {
9120 #[doc = "A cancel request is generated at a falling edge"]
9121 pub const _0: Self = Self::new(0);
9122
9123 #[doc = "A cancel request is generated at a rising edge"]
9124 pub const _1: Self = Self::new(1);
9125 }
9126}
9127#[doc(hidden)]
9128#[derive(Copy, Clone, Eq, PartialEq)]
9129pub struct Syocdcr_SPEC;
9130impl crate::sealed::RegSpec for Syocdcr_SPEC {
9131 type DataType = u8;
9132}
9133
9134#[doc = "System Control OCD Control Register"]
9135pub type Syocdcr = crate::RegValueT<Syocdcr_SPEC>;
9136
9137impl Syocdcr {
9138 #[doc = "Deep Software Standby OCD flag"]
9139 #[inline(always)]
9140 pub fn docdf(
9141 self,
9142 ) -> crate::common::RegisterField<
9143 0,
9144 0x1,
9145 1,
9146 0,
9147 syocdcr::Docdf,
9148 syocdcr::Docdf,
9149 Syocdcr_SPEC,
9150 crate::common::RW,
9151 > {
9152 crate::common::RegisterField::<
9153 0,
9154 0x1,
9155 1,
9156 0,
9157 syocdcr::Docdf,
9158 syocdcr::Docdf,
9159 Syocdcr_SPEC,
9160 crate::common::RW,
9161 >::from_register(self, 0)
9162 }
9163
9164 #[doc = "Debugger Enable bit"]
9165 #[inline(always)]
9166 pub fn dbgen(
9167 self,
9168 ) -> crate::common::RegisterField<
9169 7,
9170 0x1,
9171 1,
9172 0,
9173 syocdcr::Dbgen,
9174 syocdcr::Dbgen,
9175 Syocdcr_SPEC,
9176 crate::common::RW,
9177 > {
9178 crate::common::RegisterField::<
9179 7,
9180 0x1,
9181 1,
9182 0,
9183 syocdcr::Dbgen,
9184 syocdcr::Dbgen,
9185 Syocdcr_SPEC,
9186 crate::common::RW,
9187 >::from_register(self, 0)
9188 }
9189}
9190impl ::core::default::Default for Syocdcr {
9191 #[inline(always)]
9192 fn default() -> Syocdcr {
9193 <crate::RegValueT<Syocdcr_SPEC> as RegisterValue<_>>::new(0)
9194 }
9195}
9196pub mod syocdcr {
9197
9198 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9199 pub struct Docdf_SPEC;
9200 pub type Docdf = crate::EnumBitfieldStruct<u8, Docdf_SPEC>;
9201 impl Docdf {
9202 #[doc = "DBIRQ is not generated"]
9203 pub const _0: Self = Self::new(0);
9204
9205 #[doc = "DBIRQ is generated"]
9206 pub const _1: Self = Self::new(1);
9207 }
9208 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9209 pub struct Dbgen_SPEC;
9210 pub type Dbgen = crate::EnumBitfieldStruct<u8, Dbgen_SPEC>;
9211 impl Dbgen {
9212 #[doc = "On-chip debugger is disabled"]
9213 pub const _0: Self = Self::new(0);
9214
9215 #[doc = "On-chip debugger is enabled"]
9216 pub const _1: Self = Self::new(1);
9217 }
9218}
9219#[doc(hidden)]
9220#[derive(Copy, Clone, Eq, PartialEq)]
9221pub struct Rstsr0_SPEC;
9222impl crate::sealed::RegSpec for Rstsr0_SPEC {
9223 type DataType = u8;
9224}
9225
9226#[doc = "Reset Status Register 0"]
9227pub type Rstsr0 = crate::RegValueT<Rstsr0_SPEC>;
9228
9229impl Rstsr0 {
9230 #[doc = "Power-On Reset Detect Flag"]
9231 #[inline(always)]
9232 pub fn porf(
9233 self,
9234 ) -> crate::common::RegisterField<
9235 0,
9236 0x1,
9237 1,
9238 0,
9239 rstsr0::Porf,
9240 rstsr0::Porf,
9241 Rstsr0_SPEC,
9242 crate::common::RW,
9243 > {
9244 crate::common::RegisterField::<
9245 0,
9246 0x1,
9247 1,
9248 0,
9249 rstsr0::Porf,
9250 rstsr0::Porf,
9251 Rstsr0_SPEC,
9252 crate::common::RW,
9253 >::from_register(self, 0)
9254 }
9255
9256 #[doc = "Voltage Monitor 0 Reset Detect Flag"]
9257 #[inline(always)]
9258 pub fn lvd0rf(
9259 self,
9260 ) -> crate::common::RegisterField<
9261 1,
9262 0x1,
9263 1,
9264 0,
9265 rstsr0::Lvd0Rf,
9266 rstsr0::Lvd0Rf,
9267 Rstsr0_SPEC,
9268 crate::common::RW,
9269 > {
9270 crate::common::RegisterField::<
9271 1,
9272 0x1,
9273 1,
9274 0,
9275 rstsr0::Lvd0Rf,
9276 rstsr0::Lvd0Rf,
9277 Rstsr0_SPEC,
9278 crate::common::RW,
9279 >::from_register(self, 0)
9280 }
9281
9282 #[doc = "Voltage Monitor 1 Reset Detect Flag"]
9283 #[inline(always)]
9284 pub fn lvd1rf(
9285 self,
9286 ) -> crate::common::RegisterField<
9287 2,
9288 0x1,
9289 1,
9290 0,
9291 rstsr0::Lvd1Rf,
9292 rstsr0::Lvd1Rf,
9293 Rstsr0_SPEC,
9294 crate::common::RW,
9295 > {
9296 crate::common::RegisterField::<
9297 2,
9298 0x1,
9299 1,
9300 0,
9301 rstsr0::Lvd1Rf,
9302 rstsr0::Lvd1Rf,
9303 Rstsr0_SPEC,
9304 crate::common::RW,
9305 >::from_register(self, 0)
9306 }
9307
9308 #[doc = "Voltage Monitor 2 Reset Detect Flag"]
9309 #[inline(always)]
9310 pub fn lvd2rf(
9311 self,
9312 ) -> crate::common::RegisterField<
9313 3,
9314 0x1,
9315 1,
9316 0,
9317 rstsr0::Lvd2Rf,
9318 rstsr0::Lvd2Rf,
9319 Rstsr0_SPEC,
9320 crate::common::RW,
9321 > {
9322 crate::common::RegisterField::<
9323 3,
9324 0x1,
9325 1,
9326 0,
9327 rstsr0::Lvd2Rf,
9328 rstsr0::Lvd2Rf,
9329 Rstsr0_SPEC,
9330 crate::common::RW,
9331 >::from_register(self, 0)
9332 }
9333
9334 #[doc = "Deep Software Standby Reset Detect Flag"]
9335 #[inline(always)]
9336 pub fn dpsrstf(
9337 self,
9338 ) -> crate::common::RegisterField<
9339 7,
9340 0x1,
9341 1,
9342 0,
9343 rstsr0::Dpsrstf,
9344 rstsr0::Dpsrstf,
9345 Rstsr0_SPEC,
9346 crate::common::RW,
9347 > {
9348 crate::common::RegisterField::<
9349 7,
9350 0x1,
9351 1,
9352 0,
9353 rstsr0::Dpsrstf,
9354 rstsr0::Dpsrstf,
9355 Rstsr0_SPEC,
9356 crate::common::RW,
9357 >::from_register(self, 0)
9358 }
9359}
9360impl ::core::default::Default for Rstsr0 {
9361 #[inline(always)]
9362 fn default() -> Rstsr0 {
9363 <crate::RegValueT<Rstsr0_SPEC> as RegisterValue<_>>::new(0)
9364 }
9365}
9366pub mod rstsr0 {
9367
9368 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9369 pub struct Porf_SPEC;
9370 pub type Porf = crate::EnumBitfieldStruct<u8, Porf_SPEC>;
9371 impl Porf {
9372 #[doc = "Power-on reset not detected"]
9373 pub const _0: Self = Self::new(0);
9374
9375 #[doc = "Power-on reset detected"]
9376 pub const _1: Self = Self::new(1);
9377 }
9378 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9379 pub struct Lvd0Rf_SPEC;
9380 pub type Lvd0Rf = crate::EnumBitfieldStruct<u8, Lvd0Rf_SPEC>;
9381 impl Lvd0Rf {
9382 #[doc = "Voltage monitor 0 reset not detected"]
9383 pub const _0: Self = Self::new(0);
9384
9385 #[doc = "Voltage monitor 0 reset detected"]
9386 pub const _1: Self = Self::new(1);
9387 }
9388 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9389 pub struct Lvd1Rf_SPEC;
9390 pub type Lvd1Rf = crate::EnumBitfieldStruct<u8, Lvd1Rf_SPEC>;
9391 impl Lvd1Rf {
9392 #[doc = "Voltage monitor 1 reset not detected"]
9393 pub const _0: Self = Self::new(0);
9394
9395 #[doc = "Voltage monitor 1 reset detected"]
9396 pub const _1: Self = Self::new(1);
9397 }
9398 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9399 pub struct Lvd2Rf_SPEC;
9400 pub type Lvd2Rf = crate::EnumBitfieldStruct<u8, Lvd2Rf_SPEC>;
9401 impl Lvd2Rf {
9402 #[doc = "Voltage monitor 2 reset not detected"]
9403 pub const _0: Self = Self::new(0);
9404
9405 #[doc = "Voltage monitor 2 reset detected"]
9406 pub const _1: Self = Self::new(1);
9407 }
9408 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9409 pub struct Dpsrstf_SPEC;
9410 pub type Dpsrstf = crate::EnumBitfieldStruct<u8, Dpsrstf_SPEC>;
9411 impl Dpsrstf {
9412 #[doc = "Deep software standby mode cancellation not requested by an interrupt."]
9413 pub const _0: Self = Self::new(0);
9414
9415 #[doc = "Deep software standby mode cancellation requested by an interrupt."]
9416 pub const _1: Self = Self::new(1);
9417 }
9418}
9419#[doc(hidden)]
9420#[derive(Copy, Clone, Eq, PartialEq)]
9421pub struct Rstsr2_SPEC;
9422impl crate::sealed::RegSpec for Rstsr2_SPEC {
9423 type DataType = u8;
9424}
9425
9426#[doc = "Reset Status Register 2"]
9427pub type Rstsr2 = crate::RegValueT<Rstsr2_SPEC>;
9428
9429impl Rstsr2 {
9430 #[doc = "Cold/Warm Start Determination Flag"]
9431 #[inline(always)]
9432 pub fn cwsf(
9433 self,
9434 ) -> crate::common::RegisterField<
9435 0,
9436 0x1,
9437 1,
9438 0,
9439 rstsr2::Cwsf,
9440 rstsr2::Cwsf,
9441 Rstsr2_SPEC,
9442 crate::common::RW,
9443 > {
9444 crate::common::RegisterField::<
9445 0,
9446 0x1,
9447 1,
9448 0,
9449 rstsr2::Cwsf,
9450 rstsr2::Cwsf,
9451 Rstsr2_SPEC,
9452 crate::common::RW,
9453 >::from_register(self, 0)
9454 }
9455}
9456impl ::core::default::Default for Rstsr2 {
9457 #[inline(always)]
9458 fn default() -> Rstsr2 {
9459 <crate::RegValueT<Rstsr2_SPEC> as RegisterValue<_>>::new(0)
9460 }
9461}
9462pub mod rstsr2 {
9463
9464 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9465 pub struct Cwsf_SPEC;
9466 pub type Cwsf = crate::EnumBitfieldStruct<u8, Cwsf_SPEC>;
9467 impl Cwsf {
9468 #[doc = "Cold start"]
9469 pub const _0: Self = Self::new(0);
9470
9471 #[doc = "Warm start"]
9472 pub const _1: Self = Self::new(1);
9473 }
9474}
9475#[doc(hidden)]
9476#[derive(Copy, Clone, Eq, PartialEq)]
9477pub struct Momcr_SPEC;
9478impl crate::sealed::RegSpec for Momcr_SPEC {
9479 type DataType = u8;
9480}
9481
9482#[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
9483pub type Momcr = crate::RegValueT<Momcr_SPEC>;
9484
9485impl Momcr {
9486 #[doc = "Main Clock Oscillator Drive Capability 0 Switching"]
9487 #[inline(always)]
9488 pub fn modrv(
9489 self,
9490 ) -> crate::common::RegisterField<
9491 4,
9492 0x3,
9493 1,
9494 0,
9495 momcr::Modrv,
9496 momcr::Modrv,
9497 Momcr_SPEC,
9498 crate::common::RW,
9499 > {
9500 crate::common::RegisterField::<
9501 4,
9502 0x3,
9503 1,
9504 0,
9505 momcr::Modrv,
9506 momcr::Modrv,
9507 Momcr_SPEC,
9508 crate::common::RW,
9509 >::from_register(self, 0)
9510 }
9511
9512 #[doc = "Main Clock Oscillator Switching"]
9513 #[inline(always)]
9514 pub fn mosel(
9515 self,
9516 ) -> crate::common::RegisterField<
9517 6,
9518 0x1,
9519 1,
9520 0,
9521 momcr::Mosel,
9522 momcr::Mosel,
9523 Momcr_SPEC,
9524 crate::common::RW,
9525 > {
9526 crate::common::RegisterField::<
9527 6,
9528 0x1,
9529 1,
9530 0,
9531 momcr::Mosel,
9532 momcr::Mosel,
9533 Momcr_SPEC,
9534 crate::common::RW,
9535 >::from_register(self, 0)
9536 }
9537}
9538impl ::core::default::Default for Momcr {
9539 #[inline(always)]
9540 fn default() -> Momcr {
9541 <crate::RegValueT<Momcr_SPEC> as RegisterValue<_>>::new(0)
9542 }
9543}
9544pub mod momcr {
9545
9546 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9547 pub struct Modrv_SPEC;
9548 pub type Modrv = crate::EnumBitfieldStruct<u8, Modrv_SPEC>;
9549 impl Modrv {
9550 #[doc = "20 MHz to 24 MHz"]
9551 pub const _00: Self = Self::new(0);
9552
9553 #[doc = "16 MHz to 20 MHz"]
9554 pub const _01: Self = Self::new(1);
9555
9556 #[doc = "8 MHz to 16 MHz"]
9557 pub const _10: Self = Self::new(2);
9558
9559 #[doc = "8 MHz"]
9560 pub const _11: Self = Self::new(3);
9561 }
9562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9563 pub struct Mosel_SPEC;
9564 pub type Mosel = crate::EnumBitfieldStruct<u8, Mosel_SPEC>;
9565 impl Mosel {
9566 #[doc = "Resonator"]
9567 pub const _0: Self = Self::new(0);
9568
9569 #[doc = "External clock input"]
9570 pub const _1: Self = Self::new(1);
9571 }
9572}
9573#[doc(hidden)]
9574#[derive(Copy, Clone, Eq, PartialEq)]
9575pub struct Fwepror_SPEC;
9576impl crate::sealed::RegSpec for Fwepror_SPEC {
9577 type DataType = u8;
9578}
9579
9580#[doc = "Flash P/E Protect Register"]
9581pub type Fwepror = crate::RegValueT<Fwepror_SPEC>;
9582
9583impl Fwepror {
9584 #[doc = "Flash Programming and Erasure"]
9585 #[inline(always)]
9586 pub fn flwe(
9587 self,
9588 ) -> crate::common::RegisterField<
9589 0,
9590 0x3,
9591 1,
9592 0,
9593 fwepror::Flwe,
9594 fwepror::Flwe,
9595 Fwepror_SPEC,
9596 crate::common::RW,
9597 > {
9598 crate::common::RegisterField::<
9599 0,
9600 0x3,
9601 1,
9602 0,
9603 fwepror::Flwe,
9604 fwepror::Flwe,
9605 Fwepror_SPEC,
9606 crate::common::RW,
9607 >::from_register(self, 0)
9608 }
9609}
9610impl ::core::default::Default for Fwepror {
9611 #[inline(always)]
9612 fn default() -> Fwepror {
9613 <crate::RegValueT<Fwepror_SPEC> as RegisterValue<_>>::new(2)
9614 }
9615}
9616pub mod fwepror {
9617
9618 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9619 pub struct Flwe_SPEC;
9620 pub type Flwe = crate::EnumBitfieldStruct<u8, Flwe_SPEC>;
9621 impl Flwe {
9622 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
9623 pub const _00: Self = Self::new(0);
9624
9625 #[doc = "Permits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
9626 pub const _01: Self = Self::new(1);
9627
9628 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
9629 pub const _10: Self = Self::new(2);
9630
9631 #[doc = "Prohibits Program, Block Erase, Multi Block Erase, Blank Check, and Configuration set command processing."]
9632 pub const _11: Self = Self::new(3);
9633 }
9634}
9635#[doc(hidden)]
9636#[derive(Copy, Clone, Eq, PartialEq)]
9637pub struct Lvd1Cmpcr_SPEC;
9638impl crate::sealed::RegSpec for Lvd1Cmpcr_SPEC {
9639 type DataType = u8;
9640}
9641
9642#[doc = "Voltage Monitoring 1 Comparator Control Register"]
9643pub type Lvd1Cmpcr = crate::RegValueT<Lvd1Cmpcr_SPEC>;
9644
9645impl Lvd1Cmpcr {
9646 #[doc = "Voltage Detection 1 Level Select (Standard voltage during drop in voltage)"]
9647 #[inline(always)]
9648 pub fn lvd1lvl(
9649 self,
9650 ) -> crate::common::RegisterField<
9651 0,
9652 0x1f,
9653 1,
9654 0,
9655 lvd1cmpcr::Lvd1Lvl,
9656 lvd1cmpcr::Lvd1Lvl,
9657 Lvd1Cmpcr_SPEC,
9658 crate::common::RW,
9659 > {
9660 crate::common::RegisterField::<
9661 0,
9662 0x1f,
9663 1,
9664 0,
9665 lvd1cmpcr::Lvd1Lvl,
9666 lvd1cmpcr::Lvd1Lvl,
9667 Lvd1Cmpcr_SPEC,
9668 crate::common::RW,
9669 >::from_register(self, 0)
9670 }
9671
9672 #[doc = "Voltage Detection 1 Enable"]
9673 #[inline(always)]
9674 pub fn lvd1e(
9675 self,
9676 ) -> crate::common::RegisterField<
9677 7,
9678 0x1,
9679 1,
9680 0,
9681 lvd1cmpcr::Lvd1E,
9682 lvd1cmpcr::Lvd1E,
9683 Lvd1Cmpcr_SPEC,
9684 crate::common::RW,
9685 > {
9686 crate::common::RegisterField::<
9687 7,
9688 0x1,
9689 1,
9690 0,
9691 lvd1cmpcr::Lvd1E,
9692 lvd1cmpcr::Lvd1E,
9693 Lvd1Cmpcr_SPEC,
9694 crate::common::RW,
9695 >::from_register(self, 0)
9696 }
9697}
9698impl ::core::default::Default for Lvd1Cmpcr {
9699 #[inline(always)]
9700 fn default() -> Lvd1Cmpcr {
9701 <crate::RegValueT<Lvd1Cmpcr_SPEC> as RegisterValue<_>>::new(19)
9702 }
9703}
9704pub mod lvd1cmpcr {
9705
9706 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9707 pub struct Lvd1Lvl_SPEC;
9708 pub type Lvd1Lvl = crate::EnumBitfieldStruct<u8, Lvd1Lvl_SPEC>;
9709 impl Lvd1Lvl {
9710 #[doc = "2.99 V (Vdet1_1)"]
9711 pub const _0_X_11: Self = Self::new(17);
9712
9713 #[doc = "2.92 V (Vdet1_2)"]
9714 pub const _0_X_12: Self = Self::new(18);
9715
9716 #[doc = "2.85 V (Vdet1_3)"]
9717 pub const _0_X_13: Self = Self::new(19);
9718 }
9719 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9720 pub struct Lvd1E_SPEC;
9721 pub type Lvd1E = crate::EnumBitfieldStruct<u8, Lvd1E_SPEC>;
9722 impl Lvd1E {
9723 #[doc = "Voltage detection 1 circuit disabled"]
9724 pub const _0: Self = Self::new(0);
9725
9726 #[doc = "Voltage detection 1 circuit enabled"]
9727 pub const _1: Self = Self::new(1);
9728 }
9729}
9730#[doc(hidden)]
9731#[derive(Copy, Clone, Eq, PartialEq)]
9732pub struct Lvd2Cmpcr_SPEC;
9733impl crate::sealed::RegSpec for Lvd2Cmpcr_SPEC {
9734 type DataType = u8;
9735}
9736
9737#[doc = "Voltage Monitoring 2 Comparator Control Register"]
9738pub type Lvd2Cmpcr = crate::RegValueT<Lvd2Cmpcr_SPEC>;
9739
9740impl Lvd2Cmpcr {
9741 #[doc = "Voltage Detection 2 Level Select (Standard voltage during drop in voltage)"]
9742 #[inline(always)]
9743 pub fn lvd2lvl(
9744 self,
9745 ) -> crate::common::RegisterField<
9746 0,
9747 0x7,
9748 1,
9749 0,
9750 lvd2cmpcr::Lvd2Lvl,
9751 lvd2cmpcr::Lvd2Lvl,
9752 Lvd2Cmpcr_SPEC,
9753 crate::common::RW,
9754 > {
9755 crate::common::RegisterField::<
9756 0,
9757 0x7,
9758 1,
9759 0,
9760 lvd2cmpcr::Lvd2Lvl,
9761 lvd2cmpcr::Lvd2Lvl,
9762 Lvd2Cmpcr_SPEC,
9763 crate::common::RW,
9764 >::from_register(self, 0)
9765 }
9766
9767 #[doc = "Voltage Detection 2 Enable"]
9768 #[inline(always)]
9769 pub fn lvd2e(
9770 self,
9771 ) -> crate::common::RegisterField<
9772 7,
9773 0x1,
9774 1,
9775 0,
9776 lvd2cmpcr::Lvd2E,
9777 lvd2cmpcr::Lvd2E,
9778 Lvd2Cmpcr_SPEC,
9779 crate::common::RW,
9780 > {
9781 crate::common::RegisterField::<
9782 7,
9783 0x1,
9784 1,
9785 0,
9786 lvd2cmpcr::Lvd2E,
9787 lvd2cmpcr::Lvd2E,
9788 Lvd2Cmpcr_SPEC,
9789 crate::common::RW,
9790 >::from_register(self, 0)
9791 }
9792}
9793impl ::core::default::Default for Lvd2Cmpcr {
9794 #[inline(always)]
9795 fn default() -> Lvd2Cmpcr {
9796 <crate::RegValueT<Lvd2Cmpcr_SPEC> as RegisterValue<_>>::new(7)
9797 }
9798}
9799pub mod lvd2cmpcr {
9800
9801 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9802 pub struct Lvd2Lvl_SPEC;
9803 pub type Lvd2Lvl = crate::EnumBitfieldStruct<u8, Lvd2Lvl_SPEC>;
9804 impl Lvd2Lvl {
9805 #[doc = "2.99 V (Vdet2_1)"]
9806 pub const _101: Self = Self::new(5);
9807
9808 #[doc = "2.92 V (Vdet2_2)"]
9809 pub const _110: Self = Self::new(6);
9810
9811 #[doc = "2.85 V (Vdet2_3)"]
9812 pub const _111: Self = Self::new(7);
9813 }
9814 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
9815 pub struct Lvd2E_SPEC;
9816 pub type Lvd2E = crate::EnumBitfieldStruct<u8, Lvd2E_SPEC>;
9817 impl Lvd2E {
9818 #[doc = "Voltage detection 2 circuit disabled"]
9819 pub const _0: Self = Self::new(0);
9820
9821 #[doc = "Voltage detection 2 circuit enabled"]
9822 pub const _1: Self = Self::new(1);
9823 }
9824}
9825#[doc(hidden)]
9826#[derive(Copy, Clone, Eq, PartialEq)]
9827pub struct Lvd1Cr0_SPEC;
9828impl crate::sealed::RegSpec for Lvd1Cr0_SPEC {
9829 type DataType = u8;
9830}
9831
9832#[doc = "Voltage Monitor 1 Circuit Control Register 0"]
9833pub type Lvd1Cr0 = crate::RegValueT<Lvd1Cr0_SPEC>;
9834
9835impl Lvd1Cr0 {
9836 #[doc = "Voltage Monitor 1 Interrupt/Reset Enable"]
9837 #[inline(always)]
9838 pub fn rie(
9839 self,
9840 ) -> crate::common::RegisterField<
9841 0,
9842 0x1,
9843 1,
9844 0,
9845 lvd1cr0::Rie,
9846 lvd1cr0::Rie,
9847 Lvd1Cr0_SPEC,
9848 crate::common::RW,
9849 > {
9850 crate::common::RegisterField::<
9851 0,
9852 0x1,
9853 1,
9854 0,
9855 lvd1cr0::Rie,
9856 lvd1cr0::Rie,
9857 Lvd1Cr0_SPEC,
9858 crate::common::RW,
9859 >::from_register(self, 0)
9860 }
9861
9862 #[doc = "Voltage monitor 1 Digital Filter Disabled Mode Select"]
9863 #[inline(always)]
9864 pub fn dfdis(
9865 self,
9866 ) -> crate::common::RegisterField<
9867 1,
9868 0x1,
9869 1,
9870 0,
9871 lvd1cr0::Dfdis,
9872 lvd1cr0::Dfdis,
9873 Lvd1Cr0_SPEC,
9874 crate::common::RW,
9875 > {
9876 crate::common::RegisterField::<
9877 1,
9878 0x1,
9879 1,
9880 0,
9881 lvd1cr0::Dfdis,
9882 lvd1cr0::Dfdis,
9883 Lvd1Cr0_SPEC,
9884 crate::common::RW,
9885 >::from_register(self, 0)
9886 }
9887
9888 #[doc = "Voltage Monitor 1 Circuit Comparison Result Output Enable"]
9889 #[inline(always)]
9890 pub fn cmpe(
9891 self,
9892 ) -> crate::common::RegisterField<
9893 2,
9894 0x1,
9895 1,
9896 0,
9897 lvd1cr0::Cmpe,
9898 lvd1cr0::Cmpe,
9899 Lvd1Cr0_SPEC,
9900 crate::common::RW,
9901 > {
9902 crate::common::RegisterField::<
9903 2,
9904 0x1,
9905 1,
9906 0,
9907 lvd1cr0::Cmpe,
9908 lvd1cr0::Cmpe,
9909 Lvd1Cr0_SPEC,
9910 crate::common::RW,
9911 >::from_register(self, 0)
9912 }
9913
9914 #[doc = "Sampling Clock Select"]
9915 #[inline(always)]
9916 pub fn fsamp(
9917 self,
9918 ) -> crate::common::RegisterField<
9919 4,
9920 0x3,
9921 1,
9922 0,
9923 lvd1cr0::Fsamp,
9924 lvd1cr0::Fsamp,
9925 Lvd1Cr0_SPEC,
9926 crate::common::RW,
9927 > {
9928 crate::common::RegisterField::<
9929 4,
9930 0x3,
9931 1,
9932 0,
9933 lvd1cr0::Fsamp,
9934 lvd1cr0::Fsamp,
9935 Lvd1Cr0_SPEC,
9936 crate::common::RW,
9937 >::from_register(self, 0)
9938 }
9939
9940 #[doc = "Voltage Monitor 1 Circuit Mode Select"]
9941 #[inline(always)]
9942 pub fn ri(
9943 self,
9944 ) -> crate::common::RegisterField<
9945 6,
9946 0x1,
9947 1,
9948 0,
9949 lvd1cr0::Ri,
9950 lvd1cr0::Ri,
9951 Lvd1Cr0_SPEC,
9952 crate::common::RW,
9953 > {
9954 crate::common::RegisterField::<
9955 6,
9956 0x1,
9957 1,
9958 0,
9959 lvd1cr0::Ri,
9960 lvd1cr0::Ri,
9961 Lvd1Cr0_SPEC,
9962 crate::common::RW,
9963 >::from_register(self, 0)
9964 }
9965
9966 #[doc = "Voltage Monitor 1 Reset Negate Select"]
9967 #[inline(always)]
9968 pub fn rn(
9969 self,
9970 ) -> crate::common::RegisterField<
9971 7,
9972 0x1,
9973 1,
9974 0,
9975 lvd1cr0::Rn,
9976 lvd1cr0::Rn,
9977 Lvd1Cr0_SPEC,
9978 crate::common::RW,
9979 > {
9980 crate::common::RegisterField::<
9981 7,
9982 0x1,
9983 1,
9984 0,
9985 lvd1cr0::Rn,
9986 lvd1cr0::Rn,
9987 Lvd1Cr0_SPEC,
9988 crate::common::RW,
9989 >::from_register(self, 0)
9990 }
9991}
9992impl ::core::default::Default for Lvd1Cr0 {
9993 #[inline(always)]
9994 fn default() -> Lvd1Cr0 {
9995 <crate::RegValueT<Lvd1Cr0_SPEC> as RegisterValue<_>>::new(130)
9996 }
9997}
9998pub mod lvd1cr0 {
9999
10000 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10001 pub struct Rie_SPEC;
10002 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
10003 impl Rie {
10004 #[doc = "Disable"]
10005 pub const _0: Self = Self::new(0);
10006
10007 #[doc = "Enable"]
10008 pub const _1: Self = Self::new(1);
10009 }
10010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10011 pub struct Dfdis_SPEC;
10012 pub type Dfdis = crate::EnumBitfieldStruct<u8, Dfdis_SPEC>;
10013 impl Dfdis {
10014 #[doc = "Enable the digital filter"]
10015 pub const _0: Self = Self::new(0);
10016
10017 #[doc = "Disable the digital filter"]
10018 pub const _1: Self = Self::new(1);
10019 }
10020 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10021 pub struct Cmpe_SPEC;
10022 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
10023 impl Cmpe {
10024 #[doc = "Disable voltage monitor 1 circuit comparison result output"]
10025 pub const _0: Self = Self::new(0);
10026
10027 #[doc = "Enable voltage monitor 1 circuit comparison result output"]
10028 pub const _1: Self = Self::new(1);
10029 }
10030 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10031 pub struct Fsamp_SPEC;
10032 pub type Fsamp = crate::EnumBitfieldStruct<u8, Fsamp_SPEC>;
10033 impl Fsamp {
10034 #[doc = "1/2 LOCO frequency"]
10035 pub const _00: Self = Self::new(0);
10036
10037 #[doc = "1/4 LOCO frequency"]
10038 pub const _01: Self = Self::new(1);
10039
10040 #[doc = "1/8 LOCO frequency"]
10041 pub const _10: Self = Self::new(2);
10042
10043 #[doc = "1/16 LOCO frequency"]
10044 pub const _11: Self = Self::new(3);
10045 }
10046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10047 pub struct Ri_SPEC;
10048 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
10049 impl Ri {
10050 #[doc = "Generate voltage monitor 1 interrupt on Vdet1 crossing"]
10051 pub const _0: Self = Self::new(0);
10052
10053 #[doc = "Enable voltage monitor 1 reset when the voltage falls to and below Vdet1"]
10054 pub const _1: Self = Self::new(1);
10055 }
10056 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10057 pub struct Rn_SPEC;
10058 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
10059 impl Rn {
10060 #[doc = "Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected"]
10061 pub const _0: Self = Self::new(0);
10062
10063 #[doc = "Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset"]
10064 pub const _1: Self = Self::new(1);
10065 }
10066}
10067#[doc(hidden)]
10068#[derive(Copy, Clone, Eq, PartialEq)]
10069pub struct Lvd2Cr0_SPEC;
10070impl crate::sealed::RegSpec for Lvd2Cr0_SPEC {
10071 type DataType = u8;
10072}
10073
10074#[doc = "Voltage Monitor 2 Circuit Control Register 0"]
10075pub type Lvd2Cr0 = crate::RegValueT<Lvd2Cr0_SPEC>;
10076
10077impl Lvd2Cr0 {
10078 #[doc = "Voltage Monitor 2 Interrupt/Reset Enable"]
10079 #[inline(always)]
10080 pub fn rie(
10081 self,
10082 ) -> crate::common::RegisterField<
10083 0,
10084 0x1,
10085 1,
10086 0,
10087 lvd2cr0::Rie,
10088 lvd2cr0::Rie,
10089 Lvd2Cr0_SPEC,
10090 crate::common::RW,
10091 > {
10092 crate::common::RegisterField::<
10093 0,
10094 0x1,
10095 1,
10096 0,
10097 lvd2cr0::Rie,
10098 lvd2cr0::Rie,
10099 Lvd2Cr0_SPEC,
10100 crate::common::RW,
10101 >::from_register(self, 0)
10102 }
10103
10104 #[doc = "Voltage monitor 2 Digital Filter Disabled Mode Select"]
10105 #[inline(always)]
10106 pub fn dfdis(
10107 self,
10108 ) -> crate::common::RegisterField<
10109 1,
10110 0x1,
10111 1,
10112 0,
10113 lvd2cr0::Dfdis,
10114 lvd2cr0::Dfdis,
10115 Lvd2Cr0_SPEC,
10116 crate::common::RW,
10117 > {
10118 crate::common::RegisterField::<
10119 1,
10120 0x1,
10121 1,
10122 0,
10123 lvd2cr0::Dfdis,
10124 lvd2cr0::Dfdis,
10125 Lvd2Cr0_SPEC,
10126 crate::common::RW,
10127 >::from_register(self, 0)
10128 }
10129
10130 #[doc = "Voltage Monitor 2 Circuit Comparison Result Output Enable"]
10131 #[inline(always)]
10132 pub fn cmpe(
10133 self,
10134 ) -> crate::common::RegisterField<
10135 2,
10136 0x1,
10137 1,
10138 0,
10139 lvd2cr0::Cmpe,
10140 lvd2cr0::Cmpe,
10141 Lvd2Cr0_SPEC,
10142 crate::common::RW,
10143 > {
10144 crate::common::RegisterField::<
10145 2,
10146 0x1,
10147 1,
10148 0,
10149 lvd2cr0::Cmpe,
10150 lvd2cr0::Cmpe,
10151 Lvd2Cr0_SPEC,
10152 crate::common::RW,
10153 >::from_register(self, 0)
10154 }
10155
10156 #[doc = "Sampling Clock Select"]
10157 #[inline(always)]
10158 pub fn fsamp(
10159 self,
10160 ) -> crate::common::RegisterField<
10161 4,
10162 0x3,
10163 1,
10164 0,
10165 lvd2cr0::Fsamp,
10166 lvd2cr0::Fsamp,
10167 Lvd2Cr0_SPEC,
10168 crate::common::RW,
10169 > {
10170 crate::common::RegisterField::<
10171 4,
10172 0x3,
10173 1,
10174 0,
10175 lvd2cr0::Fsamp,
10176 lvd2cr0::Fsamp,
10177 Lvd2Cr0_SPEC,
10178 crate::common::RW,
10179 >::from_register(self, 0)
10180 }
10181
10182 #[doc = "Voltage Monitor 2 Circuit Mode Select"]
10183 #[inline(always)]
10184 pub fn ri(
10185 self,
10186 ) -> crate::common::RegisterField<
10187 6,
10188 0x1,
10189 1,
10190 0,
10191 lvd2cr0::Ri,
10192 lvd2cr0::Ri,
10193 Lvd2Cr0_SPEC,
10194 crate::common::RW,
10195 > {
10196 crate::common::RegisterField::<
10197 6,
10198 0x1,
10199 1,
10200 0,
10201 lvd2cr0::Ri,
10202 lvd2cr0::Ri,
10203 Lvd2Cr0_SPEC,
10204 crate::common::RW,
10205 >::from_register(self, 0)
10206 }
10207
10208 #[doc = "Voltage Monitor 2 Reset Negate Select"]
10209 #[inline(always)]
10210 pub fn rn(
10211 self,
10212 ) -> crate::common::RegisterField<
10213 7,
10214 0x1,
10215 1,
10216 0,
10217 lvd2cr0::Rn,
10218 lvd2cr0::Rn,
10219 Lvd2Cr0_SPEC,
10220 crate::common::RW,
10221 > {
10222 crate::common::RegisterField::<
10223 7,
10224 0x1,
10225 1,
10226 0,
10227 lvd2cr0::Rn,
10228 lvd2cr0::Rn,
10229 Lvd2Cr0_SPEC,
10230 crate::common::RW,
10231 >::from_register(self, 0)
10232 }
10233}
10234impl ::core::default::Default for Lvd2Cr0 {
10235 #[inline(always)]
10236 fn default() -> Lvd2Cr0 {
10237 <crate::RegValueT<Lvd2Cr0_SPEC> as RegisterValue<_>>::new(130)
10238 }
10239}
10240pub mod lvd2cr0 {
10241
10242 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10243 pub struct Rie_SPEC;
10244 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
10245 impl Rie {
10246 #[doc = "Disable"]
10247 pub const _0: Self = Self::new(0);
10248
10249 #[doc = "Enable"]
10250 pub const _1: Self = Self::new(1);
10251 }
10252 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10253 pub struct Dfdis_SPEC;
10254 pub type Dfdis = crate::EnumBitfieldStruct<u8, Dfdis_SPEC>;
10255 impl Dfdis {
10256 #[doc = "Enable the digital filter"]
10257 pub const _0: Self = Self::new(0);
10258
10259 #[doc = "Disable the digital filter"]
10260 pub const _1: Self = Self::new(1);
10261 }
10262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10263 pub struct Cmpe_SPEC;
10264 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
10265 impl Cmpe {
10266 #[doc = "Disable voltage monitor 2 circuit comparison result output"]
10267 pub const _0: Self = Self::new(0);
10268
10269 #[doc = "Enable voltage monitor 2 circuit comparison result output"]
10270 pub const _1: Self = Self::new(1);
10271 }
10272 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10273 pub struct Fsamp_SPEC;
10274 pub type Fsamp = crate::EnumBitfieldStruct<u8, Fsamp_SPEC>;
10275 impl Fsamp {
10276 #[doc = "1/2 LOCO frequency"]
10277 pub const _00: Self = Self::new(0);
10278
10279 #[doc = "1/4 LOCO frequency"]
10280 pub const _01: Self = Self::new(1);
10281
10282 #[doc = "1/8 LOCO frequency"]
10283 pub const _10: Self = Self::new(2);
10284
10285 #[doc = "1/16 LOCO frequency"]
10286 pub const _11: Self = Self::new(3);
10287 }
10288 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10289 pub struct Ri_SPEC;
10290 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
10291 impl Ri {
10292 #[doc = "Generate voltage monitor 2 interrupt on Vdet2 crossing"]
10293 pub const _0: Self = Self::new(0);
10294
10295 #[doc = "Enable voltage monitor 2 reset when the voltage falls to and below Vdet2"]
10296 pub const _1: Self = Self::new(1);
10297 }
10298 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10299 pub struct Rn_SPEC;
10300 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
10301 impl Rn {
10302 #[doc = "Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected"]
10303 pub const _0: Self = Self::new(0);
10304
10305 #[doc = "Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset"]
10306 pub const _1: Self = Self::new(1);
10307 }
10308}
10309#[doc(hidden)]
10310#[derive(Copy, Clone, Eq, PartialEq)]
10311pub struct Sosccr_SPEC;
10312impl crate::sealed::RegSpec for Sosccr_SPEC {
10313 type DataType = u8;
10314}
10315
10316#[doc = "Sub-Clock Oscillator Control Register"]
10317pub type Sosccr = crate::RegValueT<Sosccr_SPEC>;
10318
10319impl Sosccr {
10320 #[doc = "Sub Clock Oscillator Stop"]
10321 #[inline(always)]
10322 pub fn sostp(
10323 self,
10324 ) -> crate::common::RegisterField<
10325 0,
10326 0x1,
10327 1,
10328 0,
10329 sosccr::Sostp,
10330 sosccr::Sostp,
10331 Sosccr_SPEC,
10332 crate::common::RW,
10333 > {
10334 crate::common::RegisterField::<
10335 0,
10336 0x1,
10337 1,
10338 0,
10339 sosccr::Sostp,
10340 sosccr::Sostp,
10341 Sosccr_SPEC,
10342 crate::common::RW,
10343 >::from_register(self, 0)
10344 }
10345}
10346impl ::core::default::Default for Sosccr {
10347 #[inline(always)]
10348 fn default() -> Sosccr {
10349 <crate::RegValueT<Sosccr_SPEC> as RegisterValue<_>>::new(0)
10350 }
10351}
10352pub mod sosccr {
10353
10354 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10355 pub struct Sostp_SPEC;
10356 pub type Sostp = crate::EnumBitfieldStruct<u8, Sostp_SPEC>;
10357 impl Sostp {
10358 #[doc = "Operate the sub-clock oscillator"]
10359 pub const _0: Self = Self::new(0);
10360
10361 #[doc = "Stop the sub-clock oscillator"]
10362 pub const _1: Self = Self::new(1);
10363 }
10364}
10365#[doc(hidden)]
10366#[derive(Copy, Clone, Eq, PartialEq)]
10367pub struct Somcr_SPEC;
10368impl crate::sealed::RegSpec for Somcr_SPEC {
10369 type DataType = u8;
10370}
10371
10372#[doc = "Sub-Clock Oscillator Mode Control Register"]
10373pub type Somcr = crate::RegValueT<Somcr_SPEC>;
10374
10375impl Somcr {
10376 #[doc = "Sub-Clock Oscillator Drive Capability Switching"]
10377 #[inline(always)]
10378 pub fn sodrv(
10379 self,
10380 ) -> crate::common::RegisterField<
10381 1,
10382 0x1,
10383 1,
10384 0,
10385 somcr::Sodrv,
10386 somcr::Sodrv,
10387 Somcr_SPEC,
10388 crate::common::RW,
10389 > {
10390 crate::common::RegisterField::<
10391 1,
10392 0x1,
10393 1,
10394 0,
10395 somcr::Sodrv,
10396 somcr::Sodrv,
10397 Somcr_SPEC,
10398 crate::common::RW,
10399 >::from_register(self, 0)
10400 }
10401}
10402impl ::core::default::Default for Somcr {
10403 #[inline(always)]
10404 fn default() -> Somcr {
10405 <crate::RegValueT<Somcr_SPEC> as RegisterValue<_>>::new(0)
10406 }
10407}
10408pub mod somcr {
10409
10410 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10411 pub struct Sodrv_SPEC;
10412 pub type Sodrv = crate::EnumBitfieldStruct<u8, Sodrv_SPEC>;
10413 impl Sodrv {
10414 #[doc = "Standard"]
10415 pub const _0: Self = Self::new(0);
10416
10417 #[doc = "Low"]
10418 pub const _1: Self = Self::new(1);
10419 }
10420}
10421#[doc(hidden)]
10422#[derive(Copy, Clone, Eq, PartialEq)]
10423pub struct Lococr_SPEC;
10424impl crate::sealed::RegSpec for Lococr_SPEC {
10425 type DataType = u8;
10426}
10427
10428#[doc = "Low-Speed On-Chip Oscillator Control Register"]
10429pub type Lococr = crate::RegValueT<Lococr_SPEC>;
10430
10431impl Lococr {
10432 #[doc = "LOCO Stop"]
10433 #[inline(always)]
10434 pub fn lcstp(
10435 self,
10436 ) -> crate::common::RegisterField<
10437 0,
10438 0x1,
10439 1,
10440 0,
10441 lococr::Lcstp,
10442 lococr::Lcstp,
10443 Lococr_SPEC,
10444 crate::common::RW,
10445 > {
10446 crate::common::RegisterField::<
10447 0,
10448 0x1,
10449 1,
10450 0,
10451 lococr::Lcstp,
10452 lococr::Lcstp,
10453 Lococr_SPEC,
10454 crate::common::RW,
10455 >::from_register(self, 0)
10456 }
10457}
10458impl ::core::default::Default for Lococr {
10459 #[inline(always)]
10460 fn default() -> Lococr {
10461 <crate::RegValueT<Lococr_SPEC> as RegisterValue<_>>::new(0)
10462 }
10463}
10464pub mod lococr {
10465
10466 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
10467 pub struct Lcstp_SPEC;
10468 pub type Lcstp = crate::EnumBitfieldStruct<u8, Lcstp_SPEC>;
10469 impl Lcstp {
10470 #[doc = "Operate the LOCO clock"]
10471 pub const _0: Self = Self::new(0);
10472
10473 #[doc = "Stop the LOCO clock"]
10474 pub const _1: Self = Self::new(1);
10475 }
10476}
10477#[doc(hidden)]
10478#[derive(Copy, Clone, Eq, PartialEq)]
10479pub struct Locoutcr_SPEC;
10480impl crate::sealed::RegSpec for Locoutcr_SPEC {
10481 type DataType = u8;
10482}
10483
10484#[doc = "LOCO User Trimming Control Register"]
10485pub type Locoutcr = crate::RegValueT<Locoutcr_SPEC>;
10486
10487impl Locoutcr {
10488 #[doc = "LOCO User Trimming"]
10489 #[inline(always)]
10490 pub fn locoutrm(
10491 self,
10492 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Locoutcr_SPEC, crate::common::RW> {
10493 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Locoutcr_SPEC,crate::common::RW>::from_register(self,0)
10494 }
10495}
10496impl ::core::default::Default for Locoutcr {
10497 #[inline(always)]
10498 fn default() -> Locoutcr {
10499 <crate::RegValueT<Locoutcr_SPEC> as RegisterValue<_>>::new(0)
10500 }
10501}