ra4e2_pac/
agtw0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.30.00, with svd2pac 0.4.0 on Sat, 12 Apr 2025 22:15:35 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Low Power Asynchronous General Purpose Timer 0"]
28unsafe impl ::core::marker::Send for super::Agtw0 {}
29unsafe impl ::core::marker::Sync for super::Agtw0 {}
30impl super::Agtw0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36    #[doc = "AGT Counter Register"]
37    #[inline(always)]
38    pub const fn agt(&self) -> &'static crate::common::Reg<self::Agt_SPEC, crate::common::RW> {
39        unsafe {
40            crate::common::Reg::<self::Agt_SPEC, crate::common::RW>::from_ptr(
41                self._svd2pac_as_ptr().add(0usize),
42            )
43        }
44    }
45
46    #[doc = "AGT CounterCompare Match A Register"]
47    #[inline(always)]
48    pub const fn agtcma(
49        &self,
50    ) -> &'static crate::common::Reg<self::Agtcma_SPEC, crate::common::RW> {
51        unsafe {
52            crate::common::Reg::<self::Agtcma_SPEC, crate::common::RW>::from_ptr(
53                self._svd2pac_as_ptr().add(4usize),
54            )
55        }
56    }
57
58    #[doc = "AGT CounterCompare Match B Register"]
59    #[inline(always)]
60    pub const fn agtcmb(
61        &self,
62    ) -> &'static crate::common::Reg<self::Agtcmb_SPEC, crate::common::RW> {
63        unsafe {
64            crate::common::Reg::<self::Agtcmb_SPEC, crate::common::RW>::from_ptr(
65                self._svd2pac_as_ptr().add(8usize),
66            )
67        }
68    }
69
70    #[doc = "AGT Control Register"]
71    #[inline(always)]
72    pub const fn agtcr(&self) -> &'static crate::common::Reg<self::Agtcr_SPEC, crate::common::RW> {
73        unsafe {
74            crate::common::Reg::<self::Agtcr_SPEC, crate::common::RW>::from_ptr(
75                self._svd2pac_as_ptr().add(12usize),
76            )
77        }
78    }
79
80    #[doc = "AGT Mode Register 1"]
81    #[inline(always)]
82    pub const fn agtmr1(
83        &self,
84    ) -> &'static crate::common::Reg<self::Agtmr1_SPEC, crate::common::RW> {
85        unsafe {
86            crate::common::Reg::<self::Agtmr1_SPEC, crate::common::RW>::from_ptr(
87                self._svd2pac_as_ptr().add(13usize),
88            )
89        }
90    }
91
92    #[doc = "AGT Mode Register 2"]
93    #[inline(always)]
94    pub const fn agtmr2(
95        &self,
96    ) -> &'static crate::common::Reg<self::Agtmr2_SPEC, crate::common::RW> {
97        unsafe {
98            crate::common::Reg::<self::Agtmr2_SPEC, crate::common::RW>::from_ptr(
99                self._svd2pac_as_ptr().add(14usize),
100            )
101        }
102    }
103
104    #[doc = "AGT I/O Control Register"]
105    #[inline(always)]
106    pub const fn agtioc(
107        &self,
108    ) -> &'static crate::common::Reg<self::Agtioc_SPEC, crate::common::RW> {
109        unsafe {
110            crate::common::Reg::<self::Agtioc_SPEC, crate::common::RW>::from_ptr(
111                self._svd2pac_as_ptr().add(16usize),
112            )
113        }
114    }
115
116    #[doc = "AGT Event Pin Select Register"]
117    #[inline(always)]
118    pub const fn agtisr(
119        &self,
120    ) -> &'static crate::common::Reg<self::Agtisr_SPEC, crate::common::RW> {
121        unsafe {
122            crate::common::Reg::<self::Agtisr_SPEC, crate::common::RW>::from_ptr(
123                self._svd2pac_as_ptr().add(17usize),
124            )
125        }
126    }
127
128    #[doc = "AGT Compare Match Function Select Register"]
129    #[inline(always)]
130    pub const fn agtcmsr(
131        &self,
132    ) -> &'static crate::common::Reg<self::Agtcmsr_SPEC, crate::common::RW> {
133        unsafe {
134            crate::common::Reg::<self::Agtcmsr_SPEC, crate::common::RW>::from_ptr(
135                self._svd2pac_as_ptr().add(18usize),
136            )
137        }
138    }
139
140    #[doc = "AGT Pin Select Register"]
141    #[inline(always)]
142    pub const fn agtiosel(
143        &self,
144    ) -> &'static crate::common::Reg<self::Agtiosel_SPEC, crate::common::RW> {
145        unsafe {
146            crate::common::Reg::<self::Agtiosel_SPEC, crate::common::RW>::from_ptr(
147                self._svd2pac_as_ptr().add(19usize),
148            )
149        }
150    }
151}
152#[doc(hidden)]
153#[derive(Copy, Clone, Eq, PartialEq)]
154pub struct Agt_SPEC;
155impl crate::sealed::RegSpec for Agt_SPEC {
156    type DataType = u32;
157}
158#[doc = "AGT Counter Register"]
159pub type Agt = crate::RegValueT<Agt_SPEC>;
160
161impl NoBitfieldReg<Agt_SPEC> for Agt {}
162impl ::core::default::Default for Agt {
163    #[inline(always)]
164    fn default() -> Agt {
165        <crate::RegValueT<Agt_SPEC> as RegisterValue<_>>::new(4294967295)
166    }
167}
168
169#[doc(hidden)]
170#[derive(Copy, Clone, Eq, PartialEq)]
171pub struct Agtcma_SPEC;
172impl crate::sealed::RegSpec for Agtcma_SPEC {
173    type DataType = u32;
174}
175#[doc = "AGT CounterCompare Match A Register"]
176pub type Agtcma = crate::RegValueT<Agtcma_SPEC>;
177
178impl NoBitfieldReg<Agtcma_SPEC> for Agtcma {}
179impl ::core::default::Default for Agtcma {
180    #[inline(always)]
181    fn default() -> Agtcma {
182        <crate::RegValueT<Agtcma_SPEC> as RegisterValue<_>>::new(4294967295)
183    }
184}
185
186#[doc(hidden)]
187#[derive(Copy, Clone, Eq, PartialEq)]
188pub struct Agtcmb_SPEC;
189impl crate::sealed::RegSpec for Agtcmb_SPEC {
190    type DataType = u32;
191}
192#[doc = "AGT CounterCompare Match B Register"]
193pub type Agtcmb = crate::RegValueT<Agtcmb_SPEC>;
194
195impl NoBitfieldReg<Agtcmb_SPEC> for Agtcmb {}
196impl ::core::default::Default for Agtcmb {
197    #[inline(always)]
198    fn default() -> Agtcmb {
199        <crate::RegValueT<Agtcmb_SPEC> as RegisterValue<_>>::new(4294967295)
200    }
201}
202
203#[doc(hidden)]
204#[derive(Copy, Clone, Eq, PartialEq)]
205pub struct Agtcr_SPEC;
206impl crate::sealed::RegSpec for Agtcr_SPEC {
207    type DataType = u8;
208}
209#[doc = "AGT Control Register"]
210pub type Agtcr = crate::RegValueT<Agtcr_SPEC>;
211
212impl Agtcr {
213    #[doc = "AGT Count Start"]
214    #[inline(always)]
215    pub fn tstart(
216        self,
217    ) -> crate::common::RegisterField<0, 0x1, 1, 0, agtcr::Tstart, Agtcr_SPEC, crate::common::RW>
218    {
219        crate::common::RegisterField::<0,0x1,1,0,agtcr::Tstart, Agtcr_SPEC,crate::common::RW>::from_register(self,0)
220    }
221    #[doc = "AGT Count Status Flag"]
222    #[inline(always)]
223    pub fn tcstf(
224        self,
225    ) -> crate::common::RegisterField<1, 0x1, 1, 0, agtcr::Tcstf, Agtcr_SPEC, crate::common::R>
226    {
227        crate::common::RegisterField::<1,0x1,1,0,agtcr::Tcstf, Agtcr_SPEC,crate::common::R>::from_register(self,0)
228    }
229    #[doc = "AGT Count Forced Stop"]
230    #[inline(always)]
231    pub fn tstop(
232        self,
233    ) -> crate::common::RegisterField<2, 0x1, 1, 0, agtcr::Tstop, Agtcr_SPEC, crate::common::W>
234    {
235        crate::common::RegisterField::<2,0x1,1,0,agtcr::Tstop, Agtcr_SPEC,crate::common::W>::from_register(self,0)
236    }
237    #[doc = "Active Edge Judgment Flag"]
238    #[inline(always)]
239    pub fn tedgf(
240        self,
241    ) -> crate::common::RegisterField<4, 0x1, 1, 0, agtcr::Tedgf, Agtcr_SPEC, crate::common::RW>
242    {
243        crate::common::RegisterField::<4,0x1,1,0,agtcr::Tedgf, Agtcr_SPEC,crate::common::RW>::from_register(self,0)
244    }
245    #[doc = "Underflow Flag"]
246    #[inline(always)]
247    pub fn tundf(
248        self,
249    ) -> crate::common::RegisterField<5, 0x1, 1, 0, agtcr::Tundf, Agtcr_SPEC, crate::common::RW>
250    {
251        crate::common::RegisterField::<5,0x1,1,0,agtcr::Tundf, Agtcr_SPEC,crate::common::RW>::from_register(self,0)
252    }
253    #[doc = "Compare Match A Flag"]
254    #[inline(always)]
255    pub fn tcmaf(
256        self,
257    ) -> crate::common::RegisterField<6, 0x1, 1, 0, agtcr::Tcmaf, Agtcr_SPEC, crate::common::RW>
258    {
259        crate::common::RegisterField::<6,0x1,1,0,agtcr::Tcmaf, Agtcr_SPEC,crate::common::RW>::from_register(self,0)
260    }
261    #[doc = "Compare Match B Flag"]
262    #[inline(always)]
263    pub fn tcmbf(
264        self,
265    ) -> crate::common::RegisterField<7, 0x1, 1, 0, agtcr::Tcmbf, Agtcr_SPEC, crate::common::RW>
266    {
267        crate::common::RegisterField::<7,0x1,1,0,agtcr::Tcmbf, Agtcr_SPEC,crate::common::RW>::from_register(self,0)
268    }
269}
270impl ::core::default::Default for Agtcr {
271    #[inline(always)]
272    fn default() -> Agtcr {
273        <crate::RegValueT<Agtcr_SPEC> as RegisterValue<_>>::new(0)
274    }
275}
276pub mod agtcr {
277
278    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
279    pub struct Tstart_SPEC;
280    pub type Tstart = crate::EnumBitfieldStruct<u8, Tstart_SPEC>;
281    impl Tstart {
282        #[doc = "Count stops"]
283        pub const _0: Self = Self::new(0);
284        #[doc = "Count starts"]
285        pub const _1: Self = Self::new(1);
286    }
287    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
288    pub struct Tcstf_SPEC;
289    pub type Tcstf = crate::EnumBitfieldStruct<u8, Tcstf_SPEC>;
290    impl Tcstf {
291        #[doc = "Count stopped"]
292        pub const _0: Self = Self::new(0);
293        #[doc = "Count in progress"]
294        pub const _1: Self = Self::new(1);
295    }
296    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
297    pub struct Tstop_SPEC;
298    pub type Tstop = crate::EnumBitfieldStruct<u8, Tstop_SPEC>;
299    impl Tstop {
300        #[doc = "Writing is invalid"]
301        pub const _0: Self = Self::new(0);
302        #[doc = "The count is forcibly stopped"]
303        pub const _1: Self = Self::new(1);
304    }
305    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
306    pub struct Tedgf_SPEC;
307    pub type Tedgf = crate::EnumBitfieldStruct<u8, Tedgf_SPEC>;
308    impl Tedgf {
309        #[doc = "No active edge received"]
310        pub const _0: Self = Self::new(0);
311        #[doc = "Active edge received"]
312        pub const _1: Self = Self::new(1);
313    }
314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
315    pub struct Tundf_SPEC;
316    pub type Tundf = crate::EnumBitfieldStruct<u8, Tundf_SPEC>;
317    impl Tundf {
318        #[doc = "No underflow"]
319        pub const _0: Self = Self::new(0);
320        #[doc = "Underflow"]
321        pub const _1: Self = Self::new(1);
322    }
323    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
324    pub struct Tcmaf_SPEC;
325    pub type Tcmaf = crate::EnumBitfieldStruct<u8, Tcmaf_SPEC>;
326    impl Tcmaf {
327        #[doc = "No match"]
328        pub const _0: Self = Self::new(0);
329        #[doc = "Match"]
330        pub const _1: Self = Self::new(1);
331    }
332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
333    pub struct Tcmbf_SPEC;
334    pub type Tcmbf = crate::EnumBitfieldStruct<u8, Tcmbf_SPEC>;
335    impl Tcmbf {
336        #[doc = "No match"]
337        pub const _0: Self = Self::new(0);
338        #[doc = "Match"]
339        pub const _1: Self = Self::new(1);
340    }
341}
342#[doc(hidden)]
343#[derive(Copy, Clone, Eq, PartialEq)]
344pub struct Agtmr1_SPEC;
345impl crate::sealed::RegSpec for Agtmr1_SPEC {
346    type DataType = u8;
347}
348#[doc = "AGT Mode Register 1"]
349pub type Agtmr1 = crate::RegValueT<Agtmr1_SPEC>;
350
351impl Agtmr1 {
352    #[doc = "Operating Mode"]
353    #[inline(always)]
354    pub fn tmod(
355        self,
356    ) -> crate::common::RegisterField<0, 0x7, 1, 0, agtmr1::Tmod, Agtmr1_SPEC, crate::common::RW>
357    {
358        crate::common::RegisterField::<0,0x7,1,0,agtmr1::Tmod, Agtmr1_SPEC,crate::common::RW>::from_register(self,0)
359    }
360    #[doc = "Edge Polarity"]
361    #[inline(always)]
362    pub fn tedgpl(
363        self,
364    ) -> crate::common::RegisterField<3, 0x1, 1, 0, agtmr1::Tedgpl, Agtmr1_SPEC, crate::common::RW>
365    {
366        crate::common::RegisterField::<3,0x1,1,0,agtmr1::Tedgpl, Agtmr1_SPEC,crate::common::RW>::from_register(self,0)
367    }
368    #[doc = "Count Source"]
369    #[inline(always)]
370    pub fn tck(
371        self,
372    ) -> crate::common::RegisterField<4, 0x7, 1, 0, agtmr1::Tck, Agtmr1_SPEC, crate::common::RW>
373    {
374        crate::common::RegisterField::<4,0x7,1,0,agtmr1::Tck, Agtmr1_SPEC,crate::common::RW>::from_register(self,0)
375    }
376}
377impl ::core::default::Default for Agtmr1 {
378    #[inline(always)]
379    fn default() -> Agtmr1 {
380        <crate::RegValueT<Agtmr1_SPEC> as RegisterValue<_>>::new(64)
381    }
382}
383pub mod agtmr1 {
384
385    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
386    pub struct Tmod_SPEC;
387    pub type Tmod = crate::EnumBitfieldStruct<u8, Tmod_SPEC>;
388    impl Tmod {
389        #[doc = "Timer mode"]
390        pub const _000: Self = Self::new(0);
391        #[doc = "Pulse output mode"]
392        pub const _001: Self = Self::new(1);
393        #[doc = "Event counter mode"]
394        pub const _010: Self = Self::new(2);
395        #[doc = "Pulse width measurement mode"]
396        pub const _011: Self = Self::new(3);
397        #[doc = "Pulse period measurement mode"]
398        pub const _100: Self = Self::new(4);
399        #[doc = "Setting prohibited"]
400        pub const OTHERS: Self = Self::new(0);
401    }
402    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
403    pub struct Tedgpl_SPEC;
404    pub type Tedgpl = crate::EnumBitfieldStruct<u8, Tedgpl_SPEC>;
405    impl Tedgpl {
406        #[doc = "Single-edge"]
407        pub const _0: Self = Self::new(0);
408        #[doc = "Both-edge"]
409        pub const _1: Self = Self::new(1);
410    }
411    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
412    pub struct Tck_SPEC;
413    pub type Tck = crate::EnumBitfieldStruct<u8, Tck_SPEC>;
414    impl Tck {
415        #[doc = "PCLKB"]
416        pub const _000: Self = Self::new(0);
417        #[doc = "PCLKB/8"]
418        pub const _001: Self = Self::new(1);
419        #[doc = "PCLKB/2"]
420        pub const _011: Self = Self::new(3);
421        #[doc = "Divided clock AGTLCLK specified by CKS\\[2:0\\] bits in the AGTMR2 register"]
422        pub const _100: Self = Self::new(4);
423        #[doc = "Underflow event signal from AGT0"]
424        pub const _101: Self = Self::new(5);
425        #[doc = "Divided clock AGTSCLK specified by CKS\\[2:0\\] bits in the AGTMR2 register"]
426        pub const _110: Self = Self::new(6);
427        #[doc = "Setting prohibited"]
428        pub const OTHERS: Self = Self::new(0);
429    }
430}
431#[doc(hidden)]
432#[derive(Copy, Clone, Eq, PartialEq)]
433pub struct Agtmr2_SPEC;
434impl crate::sealed::RegSpec for Agtmr2_SPEC {
435    type DataType = u8;
436}
437#[doc = "AGT Mode Register 2"]
438pub type Agtmr2 = crate::RegValueT<Agtmr2_SPEC>;
439
440impl Agtmr2 {
441    #[doc = "AGTLCLK or AGTSCLK Count Source Clock Frequency Division Ratio"]
442    #[inline(always)]
443    pub fn cks(
444        self,
445    ) -> crate::common::RegisterField<0, 0x7, 1, 0, agtmr2::Cks, Agtmr2_SPEC, crate::common::RW>
446    {
447        crate::common::RegisterField::<0,0x7,1,0,agtmr2::Cks, Agtmr2_SPEC,crate::common::RW>::from_register(self,0)
448    }
449    #[doc = "Low Power Mode"]
450    #[inline(always)]
451    pub fn lpm(
452        self,
453    ) -> crate::common::RegisterField<7, 0x1, 1, 0, agtmr2::Lpm, Agtmr2_SPEC, crate::common::RW>
454    {
455        crate::common::RegisterField::<7,0x1,1,0,agtmr2::Lpm, Agtmr2_SPEC,crate::common::RW>::from_register(self,0)
456    }
457}
458impl ::core::default::Default for Agtmr2 {
459    #[inline(always)]
460    fn default() -> Agtmr2 {
461        <crate::RegValueT<Agtmr2_SPEC> as RegisterValue<_>>::new(0)
462    }
463}
464pub mod agtmr2 {
465
466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
467    pub struct Cks_SPEC;
468    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
469    impl Cks {
470        #[doc = "1/1"]
471        pub const _000: Self = Self::new(0);
472        #[doc = "1/2"]
473        pub const _001: Self = Self::new(1);
474        #[doc = "1/4"]
475        pub const _010: Self = Self::new(2);
476        #[doc = "1/8"]
477        pub const _011: Self = Self::new(3);
478        #[doc = "1/16"]
479        pub const _100: Self = Self::new(4);
480        #[doc = "1/32"]
481        pub const _101: Self = Self::new(5);
482        #[doc = "1/64"]
483        pub const _110: Self = Self::new(6);
484        #[doc = "1/128"]
485        pub const _111: Self = Self::new(7);
486    }
487    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
488    pub struct Lpm_SPEC;
489    pub type Lpm = crate::EnumBitfieldStruct<u8, Lpm_SPEC>;
490    impl Lpm {
491        #[doc = "Normal mode"]
492        pub const _0: Self = Self::new(0);
493        #[doc = "Low power mode"]
494        pub const _1: Self = Self::new(1);
495    }
496}
497#[doc(hidden)]
498#[derive(Copy, Clone, Eq, PartialEq)]
499pub struct Agtioc_SPEC;
500impl crate::sealed::RegSpec for Agtioc_SPEC {
501    type DataType = u8;
502}
503#[doc = "AGT I/O Control Register"]
504pub type Agtioc = crate::RegValueT<Agtioc_SPEC>;
505
506impl Agtioc {
507    #[doc = "I/O Polarity Switch"]
508    #[inline(always)]
509    pub fn tedgsel(
510        self,
511    ) -> crate::common::RegisterFieldBool<0, 1, 0, Agtioc_SPEC, crate::common::RW> {
512        crate::common::RegisterFieldBool::<0, 1, 0, Agtioc_SPEC, crate::common::RW>::from_register(
513            self, 0,
514        )
515    }
516    #[doc = "AGTOn pin Output Enable"]
517    #[inline(always)]
518    pub fn toe(
519        self,
520    ) -> crate::common::RegisterField<2, 0x1, 1, 0, agtioc::Toe, Agtioc_SPEC, crate::common::RW>
521    {
522        crate::common::RegisterField::<2,0x1,1,0,agtioc::Toe, Agtioc_SPEC,crate::common::RW>::from_register(self,0)
523    }
524    #[doc = "Input Filter"]
525    #[inline(always)]
526    pub fn tipf(
527        self,
528    ) -> crate::common::RegisterField<4, 0x3, 1, 0, agtioc::Tipf, Agtioc_SPEC, crate::common::RW>
529    {
530        crate::common::RegisterField::<4,0x3,1,0,agtioc::Tipf, Agtioc_SPEC,crate::common::RW>::from_register(self,0)
531    }
532    #[doc = "Count Control"]
533    #[inline(always)]
534    pub fn tiogt(
535        self,
536    ) -> crate::common::RegisterField<6, 0x3, 1, 0, agtioc::Tiogt, Agtioc_SPEC, crate::common::RW>
537    {
538        crate::common::RegisterField::<6,0x3,1,0,agtioc::Tiogt, Agtioc_SPEC,crate::common::RW>::from_register(self,0)
539    }
540}
541impl ::core::default::Default for Agtioc {
542    #[inline(always)]
543    fn default() -> Agtioc {
544        <crate::RegValueT<Agtioc_SPEC> as RegisterValue<_>>::new(0)
545    }
546}
547pub mod agtioc {
548
549    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
550    pub struct Toe_SPEC;
551    pub type Toe = crate::EnumBitfieldStruct<u8, Toe_SPEC>;
552    impl Toe {
553        #[doc = "AGTOn pin output disabled"]
554        pub const _0: Self = Self::new(0);
555        #[doc = "AGTOn pin output enabled"]
556        pub const _1: Self = Self::new(1);
557    }
558    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
559    pub struct Tipf_SPEC;
560    pub type Tipf = crate::EnumBitfieldStruct<u8, Tipf_SPEC>;
561    impl Tipf {
562        #[doc = "No filter"]
563        pub const _00: Self = Self::new(0);
564        #[doc = "Filter sampled at PCLKB"]
565        pub const _01: Self = Self::new(1);
566        #[doc = "Filter sampled at PCLKB/8"]
567        pub const _10: Self = Self::new(2);
568        #[doc = "Filter sampled at PCLKB/32"]
569        pub const _11: Self = Self::new(3);
570    }
571    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
572    pub struct Tiogt_SPEC;
573    pub type Tiogt = crate::EnumBitfieldStruct<u8, Tiogt_SPEC>;
574    impl Tiogt {
575        #[doc = "Event is always counted"]
576        pub const _00: Self = Self::new(0);
577        #[doc = "Event is counted during polarity period specified for AGTEEn pin"]
578        pub const _01: Self = Self::new(1);
579        #[doc = "Setting prohibited"]
580        pub const OTHERS: Self = Self::new(0);
581    }
582}
583#[doc(hidden)]
584#[derive(Copy, Clone, Eq, PartialEq)]
585pub struct Agtisr_SPEC;
586impl crate::sealed::RegSpec for Agtisr_SPEC {
587    type DataType = u8;
588}
589#[doc = "AGT Event Pin Select Register"]
590pub type Agtisr = crate::RegValueT<Agtisr_SPEC>;
591
592impl Agtisr {
593    #[doc = "AGTEEn Polarity Selection"]
594    #[inline(always)]
595    pub fn eeps(
596        self,
597    ) -> crate::common::RegisterField<2, 0x1, 1, 0, agtisr::Eeps, Agtisr_SPEC, crate::common::RW>
598    {
599        crate::common::RegisterField::<2,0x1,1,0,agtisr::Eeps, Agtisr_SPEC,crate::common::RW>::from_register(self,0)
600    }
601}
602impl ::core::default::Default for Agtisr {
603    #[inline(always)]
604    fn default() -> Agtisr {
605        <crate::RegValueT<Agtisr_SPEC> as RegisterValue<_>>::new(0)
606    }
607}
608pub mod agtisr {
609
610    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
611    pub struct Eeps_SPEC;
612    pub type Eeps = crate::EnumBitfieldStruct<u8, Eeps_SPEC>;
613    impl Eeps {
614        #[doc = "An event is counted during the low-level period"]
615        pub const _0: Self = Self::new(0);
616        #[doc = "An event is counted during the high-level period"]
617        pub const _1: Self = Self::new(1);
618    }
619}
620#[doc(hidden)]
621#[derive(Copy, Clone, Eq, PartialEq)]
622pub struct Agtcmsr_SPEC;
623impl crate::sealed::RegSpec for Agtcmsr_SPEC {
624    type DataType = u8;
625}
626#[doc = "AGT Compare Match Function Select Register"]
627pub type Agtcmsr = crate::RegValueT<Agtcmsr_SPEC>;
628
629impl Agtcmsr {
630    #[doc = "AGT Compare Match A Register Enable"]
631    #[inline(always)]
632    pub fn tcmea(
633        self,
634    ) -> crate::common::RegisterField<0, 0x1, 1, 0, agtcmsr::Tcmea, Agtcmsr_SPEC, crate::common::RW>
635    {
636        crate::common::RegisterField::<0,0x1,1,0,agtcmsr::Tcmea, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
637    }
638    #[doc = "AGTOAn Pin Output Enable"]
639    #[inline(always)]
640    pub fn toea(
641        self,
642    ) -> crate::common::RegisterField<1, 0x1, 1, 0, agtcmsr::Toea, Agtcmsr_SPEC, crate::common::RW>
643    {
644        crate::common::RegisterField::<1,0x1,1,0,agtcmsr::Toea, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
645    }
646    #[doc = "AGTOAn Pin Polarity Select"]
647    #[inline(always)]
648    pub fn topola(
649        self,
650    ) -> crate::common::RegisterField<2, 0x1, 1, 0, agtcmsr::Topola, Agtcmsr_SPEC, crate::common::RW>
651    {
652        crate::common::RegisterField::<2,0x1,1,0,agtcmsr::Topola, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
653    }
654    #[doc = "AGT Compare Match B Register Enable"]
655    #[inline(always)]
656    pub fn tcmeb(
657        self,
658    ) -> crate::common::RegisterField<4, 0x1, 1, 0, agtcmsr::Tcmeb, Agtcmsr_SPEC, crate::common::RW>
659    {
660        crate::common::RegisterField::<4,0x1,1,0,agtcmsr::Tcmeb, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
661    }
662    #[doc = "AGTOBn Pin Output Enable"]
663    #[inline(always)]
664    pub fn toeb(
665        self,
666    ) -> crate::common::RegisterField<5, 0x1, 1, 0, agtcmsr::Toeb, Agtcmsr_SPEC, crate::common::RW>
667    {
668        crate::common::RegisterField::<5,0x1,1,0,agtcmsr::Toeb, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
669    }
670    #[doc = "AGTOBn Pin Polarity Select"]
671    #[inline(always)]
672    pub fn topolb(
673        self,
674    ) -> crate::common::RegisterField<6, 0x1, 1, 0, agtcmsr::Topolb, Agtcmsr_SPEC, crate::common::RW>
675    {
676        crate::common::RegisterField::<6,0x1,1,0,agtcmsr::Topolb, Agtcmsr_SPEC,crate::common::RW>::from_register(self,0)
677    }
678}
679impl ::core::default::Default for Agtcmsr {
680    #[inline(always)]
681    fn default() -> Agtcmsr {
682        <crate::RegValueT<Agtcmsr_SPEC> as RegisterValue<_>>::new(0)
683    }
684}
685pub mod agtcmsr {
686
687    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
688    pub struct Tcmea_SPEC;
689    pub type Tcmea = crate::EnumBitfieldStruct<u8, Tcmea_SPEC>;
690    impl Tcmea {
691        #[doc = "AGT Compare match A register disabled"]
692        pub const _0: Self = Self::new(0);
693        #[doc = "AGT Compare match A register enabled"]
694        pub const _1: Self = Self::new(1);
695    }
696    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
697    pub struct Toea_SPEC;
698    pub type Toea = crate::EnumBitfieldStruct<u8, Toea_SPEC>;
699    impl Toea {
700        #[doc = "AGTOAn pin output disabled"]
701        pub const _0: Self = Self::new(0);
702        #[doc = "AGTOAn pin output enabled"]
703        pub const _1: Self = Self::new(1);
704    }
705    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
706    pub struct Topola_SPEC;
707    pub type Topola = crate::EnumBitfieldStruct<u8, Topola_SPEC>;
708    impl Topola {
709        #[doc = "AGTOAn pin output is started on low. i.e. normal output"]
710        pub const _0: Self = Self::new(0);
711        #[doc = "AGTOAn pin output is started on high. i.e. inverted output"]
712        pub const _1: Self = Self::new(1);
713    }
714    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
715    pub struct Tcmeb_SPEC;
716    pub type Tcmeb = crate::EnumBitfieldStruct<u8, Tcmeb_SPEC>;
717    impl Tcmeb {
718        #[doc = "Compare match B register disabled"]
719        pub const _0: Self = Self::new(0);
720        #[doc = "Compare match B register enabled"]
721        pub const _1: Self = Self::new(1);
722    }
723    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
724    pub struct Toeb_SPEC;
725    pub type Toeb = crate::EnumBitfieldStruct<u8, Toeb_SPEC>;
726    impl Toeb {
727        #[doc = "AGTOBn pin output disabled"]
728        pub const _0: Self = Self::new(0);
729        #[doc = "AGTOBn pin output enabled"]
730        pub const _1: Self = Self::new(1);
731    }
732    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
733    pub struct Topolb_SPEC;
734    pub type Topolb = crate::EnumBitfieldStruct<u8, Topolb_SPEC>;
735    impl Topolb {
736        #[doc = "AGTOBn pin output is started on low. i.e. normal output"]
737        pub const _0: Self = Self::new(0);
738        #[doc = "AGTOBn pin output is started on high. i.e. inverted output"]
739        pub const _1: Self = Self::new(1);
740    }
741}
742#[doc(hidden)]
743#[derive(Copy, Clone, Eq, PartialEq)]
744pub struct Agtiosel_SPEC;
745impl crate::sealed::RegSpec for Agtiosel_SPEC {
746    type DataType = u8;
747}
748#[doc = "AGT Pin Select Register"]
749pub type Agtiosel = crate::RegValueT<Agtiosel_SPEC>;
750
751impl Agtiosel {
752    #[doc = "AGTIOn Pin Select"]
753    #[inline(always)]
754    pub fn sel(
755        self,
756    ) -> crate::common::RegisterField<0, 0x3, 1, 0, agtiosel::Sel, Agtiosel_SPEC, crate::common::RW>
757    {
758        crate::common::RegisterField::<0,0x3,1,0,agtiosel::Sel, Agtiosel_SPEC,crate::common::RW>::from_register(self,0)
759    }
760    #[doc = "AGTIOn Pin Input Enable"]
761    #[inline(always)]
762    pub fn ties(
763        self,
764    ) -> crate::common::RegisterField<4, 0x1, 1, 0, agtiosel::Ties, Agtiosel_SPEC, crate::common::RW>
765    {
766        crate::common::RegisterField::<4,0x1,1,0,agtiosel::Ties, Agtiosel_SPEC,crate::common::RW>::from_register(self,0)
767    }
768}
769impl ::core::default::Default for Agtiosel {
770    #[inline(always)]
771    fn default() -> Agtiosel {
772        <crate::RegValueT<Agtiosel_SPEC> as RegisterValue<_>>::new(0)
773    }
774}
775pub mod agtiosel {
776
777    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
778    pub struct Sel_SPEC;
779    pub type Sel = crate::EnumBitfieldStruct<u8, Sel_SPEC>;
780    impl Sel {
781        #[doc = "Select Pm/AGTIO as AGTIO. Pm/AGTIO can not be used as AGTIO input pin in Deep Software Standby mode. (m = 100, 301, and 407 (AGT0), m = P104, 207 and 400 (AGT1).)"]
782        pub const _00: Self = Self::new(0);
783        #[doc = "Setting prohibited"]
784        pub const _01: Self = Self::new(1);
785        #[doc = "Select P402/AGTIO as AGTIO. P402/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P402/AGTIOn is input only. It cannot be used for output."]
786        pub const _10: Self = Self::new(2);
787        #[doc = "Select P403/AGTIO as AGTIO. P403/AGTIO can be used as AGTIO input pin in Deep Software Standby mode. P403/AGTIOn is input only. It cannot be used for output."]
788        pub const _11: Self = Self::new(3);
789    }
790    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
791    pub struct Ties_SPEC;
792    pub type Ties = crate::EnumBitfieldStruct<u8, Ties_SPEC>;
793    impl Ties {
794        #[doc = "External event input is disabled during Software Standby mode"]
795        pub const _0: Self = Self::new(0);
796        #[doc = "External event input is enabled during Software Standby mode"]
797        pub const _1: Self = Self::new(1);
798    }
799}
ra4e2_pac/agtw0.rs

ra4e2_pac/
agtw0.rs
