ra4e2_pac/
gpt_ops.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.30.00, with svd2pac 0.4.0 on Sat, 12 Apr 2025 22:15:35 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Output Phase Switching Controller"]
28unsafe impl ::core::marker::Send for super::GptOps {}
29unsafe impl ::core::marker::Sync for super::GptOps {}
30impl super::GptOps {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36    #[doc = "Output Phase Switching Control Register"]
37    #[inline(always)]
38    pub const fn opscr(&self) -> &'static crate::common::Reg<self::Opscr_SPEC, crate::common::RW> {
39        unsafe {
40            crate::common::Reg::<self::Opscr_SPEC, crate::common::RW>::from_ptr(
41                self._svd2pac_as_ptr().add(0usize),
42            )
43        }
44    }
45}
46#[doc(hidden)]
47#[derive(Copy, Clone, Eq, PartialEq)]
48pub struct Opscr_SPEC;
49impl crate::sealed::RegSpec for Opscr_SPEC {
50    type DataType = u32;
51}
52#[doc = "Output Phase Switching Control Register"]
53pub type Opscr = crate::RegValueT<Opscr_SPEC>;
54
55impl Opscr {
56    #[doc = ""]
57    #[inline(always)]
58    pub fn uf(self) -> crate::common::RegisterFieldBool<0, 1, 0, Opscr_SPEC, crate::common::RW> {
59        crate::common::RegisterFieldBool::<0, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
60            self, 0,
61        )
62    }
63    #[doc = ""]
64    #[inline(always)]
65    pub fn vf(self) -> crate::common::RegisterFieldBool<1, 1, 0, Opscr_SPEC, crate::common::RW> {
66        crate::common::RegisterFieldBool::<1, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
67            self, 0,
68        )
69    }
70    #[doc = ""]
71    #[inline(always)]
72    pub fn wf(self) -> crate::common::RegisterFieldBool<2, 1, 0, Opscr_SPEC, crate::common::RW> {
73        crate::common::RegisterFieldBool::<2, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
74            self, 0,
75        )
76    }
77    #[doc = "Input U-Phase Monitor"]
78    #[inline(always)]
79    pub fn u(self) -> crate::common::RegisterFieldBool<4, 1, 0, Opscr_SPEC, crate::common::R> {
80        crate::common::RegisterFieldBool::<4, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
81            self, 0,
82        )
83    }
84    #[doc = "Input V-Phase Monitor"]
85    #[inline(always)]
86    pub fn v(self) -> crate::common::RegisterFieldBool<5, 1, 0, Opscr_SPEC, crate::common::R> {
87        crate::common::RegisterFieldBool::<5, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
88            self, 0,
89        )
90    }
91    #[doc = "Input W-Phase Monitor"]
92    #[inline(always)]
93    pub fn w(self) -> crate::common::RegisterFieldBool<6, 1, 0, Opscr_SPEC, crate::common::R> {
94        crate::common::RegisterFieldBool::<6, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
95            self, 0,
96        )
97    }
98    #[doc = "Output Phase Enable"]
99    #[inline(always)]
100    pub fn en(
101        self,
102    ) -> crate::common::RegisterField<8, 0x1, 1, 0, opscr::En, Opscr_SPEC, crate::common::RW> {
103        crate::common::RegisterField::<8,0x1,1,0,opscr::En, Opscr_SPEC,crate::common::RW>::from_register(self,0)
104    }
105    #[doc = "External Feedback Signal Enable"]
106    #[inline(always)]
107    pub fn fb(
108        self,
109    ) -> crate::common::RegisterField<16, 0x1, 1, 0, opscr::Fb, Opscr_SPEC, crate::common::RW> {
110        crate::common::RegisterField::<16,0x1,1,0,opscr::Fb, Opscr_SPEC,crate::common::RW>::from_register(self,0)
111    }
112    #[doc = "Positive-Phase Output (P) Control"]
113    #[inline(always)]
114    pub fn p(
115        self,
116    ) -> crate::common::RegisterField<17, 0x1, 1, 0, opscr::P, Opscr_SPEC, crate::common::RW> {
117        crate::common::RegisterField::<17,0x1,1,0,opscr::P, Opscr_SPEC,crate::common::RW>::from_register(self,0)
118    }
119    #[doc = "Negative-Phase Output (N) Control"]
120    #[inline(always)]
121    pub fn n(
122        self,
123    ) -> crate::common::RegisterField<18, 0x1, 1, 0, opscr::N, Opscr_SPEC, crate::common::RW> {
124        crate::common::RegisterField::<18,0x1,1,0,opscr::N, Opscr_SPEC,crate::common::RW>::from_register(self,0)
125    }
126    #[doc = "Output Phase Invert Control"]
127    #[inline(always)]
128    pub fn inv(
129        self,
130    ) -> crate::common::RegisterField<19, 0x1, 1, 0, opscr::Inv, Opscr_SPEC, crate::common::RW>
131    {
132        crate::common::RegisterField::<19,0x1,1,0,opscr::Inv, Opscr_SPEC,crate::common::RW>::from_register(self,0)
133    }
134    #[doc = "Output Phase Rotation Direction Reversal Control"]
135    #[inline(always)]
136    pub fn rv(
137        self,
138    ) -> crate::common::RegisterField<20, 0x1, 1, 0, opscr::Rv, Opscr_SPEC, crate::common::RW> {
139        crate::common::RegisterField::<20,0x1,1,0,opscr::Rv, Opscr_SPEC,crate::common::RW>::from_register(self,0)
140    }
141    #[doc = "Input Phase Alignment"]
142    #[inline(always)]
143    pub fn align(
144        self,
145    ) -> crate::common::RegisterField<21, 0x1, 1, 0, opscr::Align, Opscr_SPEC, crate::common::RW>
146    {
147        crate::common::RegisterField::<21,0x1,1,0,opscr::Align, Opscr_SPEC,crate::common::RW>::from_register(self,0)
148    }
149    #[doc = "Output Disabled Source Selection"]
150    #[inline(always)]
151    pub fn grp(
152        self,
153    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, Opscr_SPEC, crate::common::RW> {
154        crate::common::RegisterField::<24,0x3,1,0,u8, Opscr_SPEC,crate::common::RW>::from_register(self,0)
155    }
156    #[doc = "Group Output Disable Function"]
157    #[inline(always)]
158    pub fn godf(
159        self,
160    ) -> crate::common::RegisterField<26, 0x1, 1, 0, opscr::Godf, Opscr_SPEC, crate::common::RW>
161    {
162        crate::common::RegisterField::<26,0x1,1,0,opscr::Godf, Opscr_SPEC,crate::common::RW>::from_register(self,0)
163    }
164    #[doc = "External Input Noise Filter Enable"]
165    #[inline(always)]
166    pub fn nfen(
167        self,
168    ) -> crate::common::RegisterField<29, 0x1, 1, 0, opscr::Nfen, Opscr_SPEC, crate::common::RW>
169    {
170        crate::common::RegisterField::<29,0x1,1,0,opscr::Nfen, Opscr_SPEC,crate::common::RW>::from_register(self,0)
171    }
172    #[doc = "External Input Noise Filter Clock Selection"]
173    #[inline(always)]
174    pub fn nfcs(
175        self,
176    ) -> crate::common::RegisterField<30, 0x3, 1, 0, opscr::Nfcs, Opscr_SPEC, crate::common::RW>
177    {
178        crate::common::RegisterField::<30,0x3,1,0,opscr::Nfcs, Opscr_SPEC,crate::common::RW>::from_register(self,0)
179    }
180}
181impl ::core::default::Default for Opscr {
182    #[inline(always)]
183    fn default() -> Opscr {
184        <crate::RegValueT<Opscr_SPEC> as RegisterValue<_>>::new(0)
185    }
186}
187pub mod opscr {
188
189    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
190    pub struct En_SPEC;
191    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
192    impl En {
193        #[doc = "Do not output (Hi-Z external pin)"]
194        pub const _0: Self = Self::new(0);
195        #[doc = "Output"]
196        pub const _1: Self = Self::new(1);
197    }
198    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
199    pub struct Fb_SPEC;
200    pub type Fb = crate::EnumBitfieldStruct<u8, Fb_SPEC>;
201    impl Fb {
202        #[doc = "Select the external input"]
203        pub const _0: Self = Self::new(0);
204        #[doc = "Select the soft setting (OPSCR.UF, VF, WF)"]
205        pub const _1: Self = Self::new(1);
206    }
207    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
208    pub struct P_SPEC;
209    pub type P = crate::EnumBitfieldStruct<u8, P_SPEC>;
210    impl P {
211        #[doc = "Level signal output"]
212        pub const _0: Self = Self::new(0);
213        #[doc = "PWM signal output"]
214        pub const _1: Self = Self::new(1);
215    }
216    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
217    pub struct N_SPEC;
218    pub type N = crate::EnumBitfieldStruct<u8, N_SPEC>;
219    impl N {
220        #[doc = "Level signal output"]
221        pub const _0: Self = Self::new(0);
222        #[doc = "PWM signal output"]
223        pub const _1: Self = Self::new(1);
224    }
225    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
226    pub struct Inv_SPEC;
227    pub type Inv = crate::EnumBitfieldStruct<u8, Inv_SPEC>;
228    impl Inv {
229        #[doc = "Positive logic (active-high) output"]
230        pub const _0: Self = Self::new(0);
231        #[doc = "Negative logic (active-low) output"]
232        pub const _1: Self = Self::new(1);
233    }
234    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
235    pub struct Rv_SPEC;
236    pub type Rv = crate::EnumBitfieldStruct<u8, Rv_SPEC>;
237    impl Rv {
238        #[doc = "Positive rotation"]
239        pub const _0: Self = Self::new(0);
240        #[doc = "Reverse rotation"]
241        pub const _1: Self = Self::new(1);
242    }
243    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
244    pub struct Align_SPEC;
245    pub type Align = crate::EnumBitfieldStruct<u8, Align_SPEC>;
246    impl Align {
247        #[doc = "Input phase aligned to PCLKD"]
248        pub const _0: Self = Self::new(0);
249        #[doc = "Input phase aligned to the falling edge of PWM"]
250        pub const _1: Self = Self::new(1);
251    }
252    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
253    pub struct Godf_SPEC;
254    pub type Godf = crate::EnumBitfieldStruct<u8, Godf_SPEC>;
255    impl Godf {
256        #[doc = "This bit function is ignored"]
257        pub const _0: Self = Self::new(0);
258        #[doc = "Group disable clears the OPSCR.EN bit"]
259        pub const _1: Self = Self::new(1);
260    }
261    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
262    pub struct Nfen_SPEC;
263    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
264    impl Nfen {
265        #[doc = "Do not use a noise filter on the external input"]
266        pub const _0: Self = Self::new(0);
267        #[doc = "Use a noise filter on the external input"]
268        pub const _1: Self = Self::new(1);
269    }
270    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
271    pub struct Nfcs_SPEC;
272    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
273    impl Nfcs {
274        #[doc = "PCLKD/1"]
275        pub const _00: Self = Self::new(0);
276        #[doc = "PCLKD/4"]
277        pub const _01: Self = Self::new(1);
278        #[doc = "PCLKD/16"]
279        pub const _10: Self = Self::new(2);
280        #[doc = "PCLKD/64"]
281        pub const _11: Self = Self::new(3);
282    }
283}
ra4e2_pac/gpt_ops.rs

ra4e2_pac/
gpt_ops.rs
