ra2l1/iic0/
iccr1.rs

1#[doc = "Register `ICCR1` reader"]
2pub struct R(crate::R<ICCR1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ICCR1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ICCR1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ICCR1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ICCR1` writer"]
17pub struct W(crate::W<ICCR1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ICCR1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ICCR1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ICCR1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `SDAI` reader - SDA Line Monitor"]
38pub type SDAI_R = crate::BitReader<SDAI_A>;
39#[doc = "SDA Line Monitor\n\nValue on reset: 1"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41pub enum SDAI_A {
42    #[doc = "0: SDAn line is low"]
43    _0 = 0,
44    #[doc = "1: SDAn line is high"]
45    _1 = 1,
46}
47impl From<SDAI_A> for bool {
48    #[inline(always)]
49    fn from(variant: SDAI_A) -> Self {
50        variant as u8 != 0
51    }
52}
53impl SDAI_R {
54    #[doc = "Get enumerated values variant"]
55    #[inline(always)]
56    pub fn variant(&self) -> SDAI_A {
57        match self.bits {
58            false => SDAI_A::_0,
59            true => SDAI_A::_1,
60        }
61    }
62    #[doc = "Checks if the value of the field is `_0`"]
63    #[inline(always)]
64    pub fn is_0(&self) -> bool {
65        *self == SDAI_A::_0
66    }
67    #[doc = "Checks if the value of the field is `_1`"]
68    #[inline(always)]
69    pub fn is_1(&self) -> bool {
70        *self == SDAI_A::_1
71    }
72}
73#[doc = "Field `SCLI` reader - SCL Line Monitor"]
74pub type SCLI_R = crate::BitReader<SCLI_A>;
75#[doc = "SCL Line Monitor\n\nValue on reset: 1"]
76#[derive(Clone, Copy, Debug, PartialEq, Eq)]
77pub enum SCLI_A {
78    #[doc = "0: SCLn line is low"]
79    _0 = 0,
80    #[doc = "1: SCLn line is high"]
81    _1 = 1,
82}
83impl From<SCLI_A> for bool {
84    #[inline(always)]
85    fn from(variant: SCLI_A) -> Self {
86        variant as u8 != 0
87    }
88}
89impl SCLI_R {
90    #[doc = "Get enumerated values variant"]
91    #[inline(always)]
92    pub fn variant(&self) -> SCLI_A {
93        match self.bits {
94            false => SCLI_A::_0,
95            true => SCLI_A::_1,
96        }
97    }
98    #[doc = "Checks if the value of the field is `_0`"]
99    #[inline(always)]
100    pub fn is_0(&self) -> bool {
101        *self == SCLI_A::_0
102    }
103    #[doc = "Checks if the value of the field is `_1`"]
104    #[inline(always)]
105    pub fn is_1(&self) -> bool {
106        *self == SCLI_A::_1
107    }
108}
109#[doc = "Field `SDAO` reader - SDA Output Control/Monitor"]
110pub type SDAO_R = crate::BitReader<SDAO_A>;
111#[doc = "SDA Output Control/Monitor\n\nValue on reset: 1"]
112#[derive(Clone, Copy, Debug, PartialEq, Eq)]
113pub enum SDAO_A {
114    #[doc = "0: Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low"]
115    _0 = 0,
116    #[doc = "1: Read: IIC releases SDAn pin Write: IIC releases SDAn pin"]
117    _1 = 1,
118}
119impl From<SDAO_A> for bool {
120    #[inline(always)]
121    fn from(variant: SDAO_A) -> Self {
122        variant as u8 != 0
123    }
124}
125impl SDAO_R {
126    #[doc = "Get enumerated values variant"]
127    #[inline(always)]
128    pub fn variant(&self) -> SDAO_A {
129        match self.bits {
130            false => SDAO_A::_0,
131            true => SDAO_A::_1,
132        }
133    }
134    #[doc = "Checks if the value of the field is `_0`"]
135    #[inline(always)]
136    pub fn is_0(&self) -> bool {
137        *self == SDAO_A::_0
138    }
139    #[doc = "Checks if the value of the field is `_1`"]
140    #[inline(always)]
141    pub fn is_1(&self) -> bool {
142        *self == SDAO_A::_1
143    }
144}
145#[doc = "Field `SDAO` writer - SDA Output Control/Monitor"]
146pub type SDAO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SDAO_A, O>;
147impl<'a, const O: u8> SDAO_W<'a, O> {
148    #[doc = "Read: IIC drives SDAn pin low Write: IIC drives SDAn pin low"]
149    #[inline(always)]
150    pub fn _0(self) -> &'a mut W {
151        self.variant(SDAO_A::_0)
152    }
153    #[doc = "Read: IIC releases SDAn pin Write: IIC releases SDAn pin"]
154    #[inline(always)]
155    pub fn _1(self) -> &'a mut W {
156        self.variant(SDAO_A::_1)
157    }
158}
159#[doc = "Field `SCLO` reader - SCL Output Control/Monitor"]
160pub type SCLO_R = crate::BitReader<SCLO_A>;
161#[doc = "SCL Output Control/Monitor\n\nValue on reset: 1"]
162#[derive(Clone, Copy, Debug, PartialEq, Eq)]
163pub enum SCLO_A {
164    #[doc = "0: Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low"]
165    _0 = 0,
166    #[doc = "1: Read: IIC releases SCLn pin Write: IIC releases SCLn pin"]
167    _1 = 1,
168}
169impl From<SCLO_A> for bool {
170    #[inline(always)]
171    fn from(variant: SCLO_A) -> Self {
172        variant as u8 != 0
173    }
174}
175impl SCLO_R {
176    #[doc = "Get enumerated values variant"]
177    #[inline(always)]
178    pub fn variant(&self) -> SCLO_A {
179        match self.bits {
180            false => SCLO_A::_0,
181            true => SCLO_A::_1,
182        }
183    }
184    #[doc = "Checks if the value of the field is `_0`"]
185    #[inline(always)]
186    pub fn is_0(&self) -> bool {
187        *self == SCLO_A::_0
188    }
189    #[doc = "Checks if the value of the field is `_1`"]
190    #[inline(always)]
191    pub fn is_1(&self) -> bool {
192        *self == SCLO_A::_1
193    }
194}
195#[doc = "Field `SCLO` writer - SCL Output Control/Monitor"]
196pub type SCLO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SCLO_A, O>;
197impl<'a, const O: u8> SCLO_W<'a, O> {
198    #[doc = "Read: IIC drives SCLn pin low Write: IIC drives SCLn pin low"]
199    #[inline(always)]
200    pub fn _0(self) -> &'a mut W {
201        self.variant(SCLO_A::_0)
202    }
203    #[doc = "Read: IIC releases SCLn pin Write: IIC releases SCLn pin"]
204    #[inline(always)]
205    pub fn _1(self) -> &'a mut W {
206        self.variant(SCLO_A::_1)
207    }
208}
209#[doc = "SCLO/SDAO Write Protect\n\nValue on reset: 1"]
210#[derive(Clone, Copy, Debug, PartialEq, Eq)]
211pub enum SOWP_AW {
212    #[doc = "0: Write enable SCLO and SDAO bits"]
213    _0 = 0,
214    #[doc = "1: Write protect SCLO and SDAO bits"]
215    _1 = 1,
216}
217impl From<SOWP_AW> for bool {
218    #[inline(always)]
219    fn from(variant: SOWP_AW) -> Self {
220        variant as u8 != 0
221    }
222}
223#[doc = "Field `SOWP` writer - SCLO/SDAO Write Protect"]
224pub type SOWP_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, SOWP_AW, O>;
225impl<'a, const O: u8> SOWP_W<'a, O> {
226    #[doc = "Write enable SCLO and SDAO bits"]
227    #[inline(always)]
228    pub fn _0(self) -> &'a mut W {
229        self.variant(SOWP_AW::_0)
230    }
231    #[doc = "Write protect SCLO and SDAO bits"]
232    #[inline(always)]
233    pub fn _1(self) -> &'a mut W {
234        self.variant(SOWP_AW::_1)
235    }
236}
237#[doc = "Field `CLO` reader - Extra SCL Clock Cycle Output"]
238pub type CLO_R = crate::BitReader<CLO_A>;
239#[doc = "Extra SCL Clock Cycle Output\n\nValue on reset: 0"]
240#[derive(Clone, Copy, Debug, PartialEq, Eq)]
241pub enum CLO_A {
242    #[doc = "0: Do not output extra SCL clock cycle (default)"]
243    _0 = 0,
244    #[doc = "1: Output extra SCL clock cycle"]
245    _1 = 1,
246}
247impl From<CLO_A> for bool {
248    #[inline(always)]
249    fn from(variant: CLO_A) -> Self {
250        variant as u8 != 0
251    }
252}
253impl CLO_R {
254    #[doc = "Get enumerated values variant"]
255    #[inline(always)]
256    pub fn variant(&self) -> CLO_A {
257        match self.bits {
258            false => CLO_A::_0,
259            true => CLO_A::_1,
260        }
261    }
262    #[doc = "Checks if the value of the field is `_0`"]
263    #[inline(always)]
264    pub fn is_0(&self) -> bool {
265        *self == CLO_A::_0
266    }
267    #[doc = "Checks if the value of the field is `_1`"]
268    #[inline(always)]
269    pub fn is_1(&self) -> bool {
270        *self == CLO_A::_1
271    }
272}
273#[doc = "Field `CLO` writer - Extra SCL Clock Cycle Output"]
274pub type CLO_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, CLO_A, O>;
275impl<'a, const O: u8> CLO_W<'a, O> {
276    #[doc = "Do not output extra SCL clock cycle (default)"]
277    #[inline(always)]
278    pub fn _0(self) -> &'a mut W {
279        self.variant(CLO_A::_0)
280    }
281    #[doc = "Output extra SCL clock cycle"]
282    #[inline(always)]
283    pub fn _1(self) -> &'a mut W {
284        self.variant(CLO_A::_1)
285    }
286}
287#[doc = "Field `IICRST` reader - I2C Bus Interface Internal Reset"]
288pub type IICRST_R = crate::BitReader<IICRST_A>;
289#[doc = "I2C Bus Interface Internal Reset\n\nValue on reset: 0"]
290#[derive(Clone, Copy, Debug, PartialEq, Eq)]
291pub enum IICRST_A {
292    #[doc = "0: Release IIC reset or internal reset"]
293    _0 = 0,
294    #[doc = "1: Initiate IIC reset or internal reset"]
295    _1 = 1,
296}
297impl From<IICRST_A> for bool {
298    #[inline(always)]
299    fn from(variant: IICRST_A) -> Self {
300        variant as u8 != 0
301    }
302}
303impl IICRST_R {
304    #[doc = "Get enumerated values variant"]
305    #[inline(always)]
306    pub fn variant(&self) -> IICRST_A {
307        match self.bits {
308            false => IICRST_A::_0,
309            true => IICRST_A::_1,
310        }
311    }
312    #[doc = "Checks if the value of the field is `_0`"]
313    #[inline(always)]
314    pub fn is_0(&self) -> bool {
315        *self == IICRST_A::_0
316    }
317    #[doc = "Checks if the value of the field is `_1`"]
318    #[inline(always)]
319    pub fn is_1(&self) -> bool {
320        *self == IICRST_A::_1
321    }
322}
323#[doc = "Field `IICRST` writer - I2C Bus Interface Internal Reset"]
324pub type IICRST_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, IICRST_A, O>;
325impl<'a, const O: u8> IICRST_W<'a, O> {
326    #[doc = "Release IIC reset or internal reset"]
327    #[inline(always)]
328    pub fn _0(self) -> &'a mut W {
329        self.variant(IICRST_A::_0)
330    }
331    #[doc = "Initiate IIC reset or internal reset"]
332    #[inline(always)]
333    pub fn _1(self) -> &'a mut W {
334        self.variant(IICRST_A::_1)
335    }
336}
337#[doc = "Field `ICE` reader - I2C Bus Interface Enable"]
338pub type ICE_R = crate::BitReader<ICE_A>;
339#[doc = "I2C Bus Interface Enable\n\nValue on reset: 0"]
340#[derive(Clone, Copy, Debug, PartialEq, Eq)]
341pub enum ICE_A {
342    #[doc = "0: Disable (SCLn and SDAn pins in inactive state)"]
343    _0 = 0,
344    #[doc = "1: Enable (SCLn and SDAn pins in active state)"]
345    _1 = 1,
346}
347impl From<ICE_A> for bool {
348    #[inline(always)]
349    fn from(variant: ICE_A) -> Self {
350        variant as u8 != 0
351    }
352}
353impl ICE_R {
354    #[doc = "Get enumerated values variant"]
355    #[inline(always)]
356    pub fn variant(&self) -> ICE_A {
357        match self.bits {
358            false => ICE_A::_0,
359            true => ICE_A::_1,
360        }
361    }
362    #[doc = "Checks if the value of the field is `_0`"]
363    #[inline(always)]
364    pub fn is_0(&self) -> bool {
365        *self == ICE_A::_0
366    }
367    #[doc = "Checks if the value of the field is `_1`"]
368    #[inline(always)]
369    pub fn is_1(&self) -> bool {
370        *self == ICE_A::_1
371    }
372}
373#[doc = "Field `ICE` writer - I2C Bus Interface Enable"]
374pub type ICE_W<'a, const O: u8> = crate::BitWriter<'a, u8, ICCR1_SPEC, ICE_A, O>;
375impl<'a, const O: u8> ICE_W<'a, O> {
376    #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
377    #[inline(always)]
378    pub fn _0(self) -> &'a mut W {
379        self.variant(ICE_A::_0)
380    }
381    #[doc = "Enable (SCLn and SDAn pins in active state)"]
382    #[inline(always)]
383    pub fn _1(self) -> &'a mut W {
384        self.variant(ICE_A::_1)
385    }
386}
387impl R {
388    #[doc = "Bit 0 - SDA Line Monitor"]
389    #[inline(always)]
390    pub fn sdai(&self) -> SDAI_R {
391        SDAI_R::new((self.bits & 1) != 0)
392    }
393    #[doc = "Bit 1 - SCL Line Monitor"]
394    #[inline(always)]
395    pub fn scli(&self) -> SCLI_R {
396        SCLI_R::new(((self.bits >> 1) & 1) != 0)
397    }
398    #[doc = "Bit 2 - SDA Output Control/Monitor"]
399    #[inline(always)]
400    pub fn sdao(&self) -> SDAO_R {
401        SDAO_R::new(((self.bits >> 2) & 1) != 0)
402    }
403    #[doc = "Bit 3 - SCL Output Control/Monitor"]
404    #[inline(always)]
405    pub fn sclo(&self) -> SCLO_R {
406        SCLO_R::new(((self.bits >> 3) & 1) != 0)
407    }
408    #[doc = "Bit 5 - Extra SCL Clock Cycle Output"]
409    #[inline(always)]
410    pub fn clo(&self) -> CLO_R {
411        CLO_R::new(((self.bits >> 5) & 1) != 0)
412    }
413    #[doc = "Bit 6 - I2C Bus Interface Internal Reset"]
414    #[inline(always)]
415    pub fn iicrst(&self) -> IICRST_R {
416        IICRST_R::new(((self.bits >> 6) & 1) != 0)
417    }
418    #[doc = "Bit 7 - I2C Bus Interface Enable"]
419    #[inline(always)]
420    pub fn ice(&self) -> ICE_R {
421        ICE_R::new(((self.bits >> 7) & 1) != 0)
422    }
423}
424impl W {
425    #[doc = "Bit 2 - SDA Output Control/Monitor"]
426    #[inline(always)]
427    #[must_use]
428    pub fn sdao(&mut self) -> SDAO_W<2> {
429        SDAO_W::new(self)
430    }
431    #[doc = "Bit 3 - SCL Output Control/Monitor"]
432    #[inline(always)]
433    #[must_use]
434    pub fn sclo(&mut self) -> SCLO_W<3> {
435        SCLO_W::new(self)
436    }
437    #[doc = "Bit 4 - SCLO/SDAO Write Protect"]
438    #[inline(always)]
439    #[must_use]
440    pub fn sowp(&mut self) -> SOWP_W<4> {
441        SOWP_W::new(self)
442    }
443    #[doc = "Bit 5 - Extra SCL Clock Cycle Output"]
444    #[inline(always)]
445    #[must_use]
446    pub fn clo(&mut self) -> CLO_W<5> {
447        CLO_W::new(self)
448    }
449    #[doc = "Bit 6 - I2C Bus Interface Internal Reset"]
450    #[inline(always)]
451    #[must_use]
452    pub fn iicrst(&mut self) -> IICRST_W<6> {
453        IICRST_W::new(self)
454    }
455    #[doc = "Bit 7 - I2C Bus Interface Enable"]
456    #[inline(always)]
457    #[must_use]
458    pub fn ice(&mut self) -> ICE_W<7> {
459        ICE_W::new(self)
460    }
461    #[doc = "Writes raw bits to the register."]
462    #[inline(always)]
463    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
464        self.0.bits(bits);
465        self
466    }
467}
468#[doc = "I2C Bus Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [iccr1](index.html) module"]
469pub struct ICCR1_SPEC;
470impl crate::RegisterSpec for ICCR1_SPEC {
471    type Ux = u8;
472}
473#[doc = "`read()` method returns [iccr1::R](R) reader structure"]
474impl crate::Readable for ICCR1_SPEC {
475    type Reader = R;
476}
477#[doc = "`write(|w| ..)` method takes [iccr1::W](W) writer structure"]
478impl crate::Writable for ICCR1_SPEC {
479    type Writer = W;
480    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
481    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
482}
483#[doc = "`reset()` method sets ICCR1 to value 0x1f"]
484impl crate::Resettable for ICCR1_SPEC {
485    const RESET_VALUE: Self::Ux = 0x1f;
486}
ra2l1/iic0/iccr1.rs

ra2l1/iic0/
iccr1.rs
