1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"12-bit D/A converter"]
28unsafe impl ::core::marker::Send for super::Dac12 {}
29unsafe impl ::core::marker::Sync for super::Dac12 {}
30impl super::Dac12 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "D/A Data Register 0"]
38 #[inline(always)]
39 pub const fn dadr0(&self) -> &'static crate::common::Reg<self::Dadr0_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Dadr0_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "D/A Control Register"]
48 #[inline(always)]
49 pub const fn dacr(&self) -> &'static crate::common::Reg<self::Dacr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Dacr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "DADR0 Format Select Register"]
58 #[inline(always)]
59 pub const fn dadpr(&self) -> &'static crate::common::Reg<self::Dadpr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Dadpr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(5usize),
63 )
64 }
65 }
66
67 #[doc = "D/A A/D Synchronous Start Control Register"]
68 #[inline(always)]
69 pub const fn daadscr(
70 &self,
71 ) -> &'static crate::common::Reg<self::Daadscr_SPEC, crate::common::RW> {
72 unsafe {
73 crate::common::Reg::<self::Daadscr_SPEC, crate::common::RW>::from_ptr(
74 self._svd2pac_as_ptr().add(6usize),
75 )
76 }
77 }
78
79 #[doc = "D/A VREF Control Register"]
80 #[inline(always)]
81 pub const fn davrefcr(
82 &self,
83 ) -> &'static crate::common::Reg<self::Davrefcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Davrefcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(7usize),
87 )
88 }
89 }
90}
91#[doc(hidden)]
92#[derive(Copy, Clone, Eq, PartialEq)]
93pub struct Dadr0_SPEC;
94impl crate::sealed::RegSpec for Dadr0_SPEC {
95 type DataType = u16;
96}
97
98#[doc = "D/A Data Register 0"]
99pub type Dadr0 = crate::RegValueT<Dadr0_SPEC>;
100
101impl NoBitfieldReg<Dadr0_SPEC> for Dadr0 {}
102impl ::core::default::Default for Dadr0 {
103 #[inline(always)]
104 fn default() -> Dadr0 {
105 <crate::RegValueT<Dadr0_SPEC> as RegisterValue<_>>::new(0)
106 }
107}
108
109#[doc(hidden)]
110#[derive(Copy, Clone, Eq, PartialEq)]
111pub struct Dacr_SPEC;
112impl crate::sealed::RegSpec for Dacr_SPEC {
113 type DataType = u8;
114}
115
116#[doc = "D/A Control Register"]
117pub type Dacr = crate::RegValueT<Dacr_SPEC>;
118
119impl Dacr {
120 #[doc = "D/A Output Enable 0"]
121 #[inline(always)]
122 pub fn daoe0(
123 self,
124 ) -> crate::common::RegisterField<
125 6,
126 0x1,
127 1,
128 0,
129 dacr::Daoe0,
130 dacr::Daoe0,
131 Dacr_SPEC,
132 crate::common::RW,
133 > {
134 crate::common::RegisterField::<
135 6,
136 0x1,
137 1,
138 0,
139 dacr::Daoe0,
140 dacr::Daoe0,
141 Dacr_SPEC,
142 crate::common::RW,
143 >::from_register(self, 0)
144 }
145}
146impl ::core::default::Default for Dacr {
147 #[inline(always)]
148 fn default() -> Dacr {
149 <crate::RegValueT<Dacr_SPEC> as RegisterValue<_>>::new(31)
150 }
151}
152pub mod dacr {
153
154 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
155 pub struct Daoe0_SPEC;
156 pub type Daoe0 = crate::EnumBitfieldStruct<u8, Daoe0_SPEC>;
157 impl Daoe0 {
158 #[doc = "Disable analog output of channel 0 (DA0)"]
159 pub const _0: Self = Self::new(0);
160
161 #[doc = "Enable D/A conversion of channel 0 (DA0)"]
162 pub const _1: Self = Self::new(1);
163 }
164}
165#[doc(hidden)]
166#[derive(Copy, Clone, Eq, PartialEq)]
167pub struct Dadpr_SPEC;
168impl crate::sealed::RegSpec for Dadpr_SPEC {
169 type DataType = u8;
170}
171
172#[doc = "DADR0 Format Select Register"]
173pub type Dadpr = crate::RegValueT<Dadpr_SPEC>;
174
175impl Dadpr {
176 #[doc = "DADR0 Format Select"]
177 #[inline(always)]
178 pub fn dpsel(
179 self,
180 ) -> crate::common::RegisterField<
181 7,
182 0x1,
183 1,
184 0,
185 dadpr::Dpsel,
186 dadpr::Dpsel,
187 Dadpr_SPEC,
188 crate::common::RW,
189 > {
190 crate::common::RegisterField::<
191 7,
192 0x1,
193 1,
194 0,
195 dadpr::Dpsel,
196 dadpr::Dpsel,
197 Dadpr_SPEC,
198 crate::common::RW,
199 >::from_register(self, 0)
200 }
201}
202impl ::core::default::Default for Dadpr {
203 #[inline(always)]
204 fn default() -> Dadpr {
205 <crate::RegValueT<Dadpr_SPEC> as RegisterValue<_>>::new(0)
206 }
207}
208pub mod dadpr {
209
210 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
211 pub struct Dpsel_SPEC;
212 pub type Dpsel = crate::EnumBitfieldStruct<u8, Dpsel_SPEC>;
213 impl Dpsel {
214 #[doc = "Right-justified format"]
215 pub const _0: Self = Self::new(0);
216
217 #[doc = "Left-justified format"]
218 pub const _1: Self = Self::new(1);
219 }
220}
221#[doc(hidden)]
222#[derive(Copy, Clone, Eq, PartialEq)]
223pub struct Daadscr_SPEC;
224impl crate::sealed::RegSpec for Daadscr_SPEC {
225 type DataType = u8;
226}
227
228#[doc = "D/A A/D Synchronous Start Control Register"]
229pub type Daadscr = crate::RegValueT<Daadscr_SPEC>;
230
231impl Daadscr {
232 #[doc = "D/A A/D Synchronous Conversion"]
233 #[inline(always)]
234 pub fn daadst(
235 self,
236 ) -> crate::common::RegisterField<
237 7,
238 0x1,
239 1,
240 0,
241 daadscr::Daadst,
242 daadscr::Daadst,
243 Daadscr_SPEC,
244 crate::common::RW,
245 > {
246 crate::common::RegisterField::<
247 7,
248 0x1,
249 1,
250 0,
251 daadscr::Daadst,
252 daadscr::Daadst,
253 Daadscr_SPEC,
254 crate::common::RW,
255 >::from_register(self, 0)
256 }
257}
258impl ::core::default::Default for Daadscr {
259 #[inline(always)]
260 fn default() -> Daadscr {
261 <crate::RegValueT<Daadscr_SPEC> as RegisterValue<_>>::new(0)
262 }
263}
264pub mod daadscr {
265
266 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
267 pub struct Daadst_SPEC;
268 pub type Daadst = crate::EnumBitfieldStruct<u8, Daadst_SPEC>;
269 impl Daadst {
270 #[doc = "Do not synchronize DAC12 with ADC12 operation (disable interference reduction between D/A and A/D conversion)."]
271 pub const _0: Self = Self::new(0);
272
273 #[doc = "Synchronize DAC12 with ADC12 operation (enable interference reduction between D/A and A/D conversion)."]
274 pub const _1: Self = Self::new(1);
275 }
276}
277#[doc(hidden)]
278#[derive(Copy, Clone, Eq, PartialEq)]
279pub struct Davrefcr_SPEC;
280impl crate::sealed::RegSpec for Davrefcr_SPEC {
281 type DataType = u8;
282}
283
284#[doc = "D/A VREF Control Register"]
285pub type Davrefcr = crate::RegValueT<Davrefcr_SPEC>;
286
287impl Davrefcr {
288 #[doc = "D/A Reference Voltage Select"]
289 #[inline(always)]
290 pub fn r#ref(
291 self,
292 ) -> crate::common::RegisterField<
293 0,
294 0x1,
295 1,
296 0,
297 davrefcr::Ref,
298 davrefcr::Ref,
299 Davrefcr_SPEC,
300 crate::common::RW,
301 > {
302 crate::common::RegisterField::<
303 0,
304 0x1,
305 1,
306 0,
307 davrefcr::Ref,
308 davrefcr::Ref,
309 Davrefcr_SPEC,
310 crate::common::RW,
311 >::from_register(self, 0)
312 }
313}
314impl ::core::default::Default for Davrefcr {
315 #[inline(always)]
316 fn default() -> Davrefcr {
317 <crate::RegValueT<Davrefcr_SPEC> as RegisterValue<_>>::new(0)
318 }
319}
320pub mod davrefcr {
321
322 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
323 pub struct Ref_SPEC;
324 pub type Ref = crate::EnumBitfieldStruct<u8, Ref_SPEC>;
325 impl Ref {
326 #[doc = "No reference voltage selected."]
327 pub const _0: Self = Self::new(0);
328
329 #[doc = "AVCC0/AVSS0 selected."]
330 pub const _1: Self = Self::new(1);
331 }
332}