ra2e3_pac/
gpt_ops.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:02:40 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Output Phase Switching Controller"]
28unsafe impl ::core::marker::Send for super::GptOps {}
29unsafe impl ::core::marker::Sync for super::GptOps {}
30impl super::GptOps {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Output Phase Switching Control Register"]
38    #[inline(always)]
39    pub const fn opscr(&self) -> &'static crate::common::Reg<self::Opscr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Opscr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46}
47#[doc(hidden)]
48#[derive(Copy, Clone, Eq, PartialEq)]
49pub struct Opscr_SPEC;
50impl crate::sealed::RegSpec for Opscr_SPEC {
51    type DataType = u32;
52}
53
54#[doc = "Output Phase Switching Control Register"]
55pub type Opscr = crate::RegValueT<Opscr_SPEC>;
56
57impl Opscr {
58    #[inline(always)]
59    pub fn uf(self) -> crate::common::RegisterFieldBool<0, 1, 0, Opscr_SPEC, crate::common::RW> {
60        crate::common::RegisterFieldBool::<0, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
61            self, 0,
62        )
63    }
64
65    #[inline(always)]
66    pub fn vf(self) -> crate::common::RegisterFieldBool<1, 1, 0, Opscr_SPEC, crate::common::RW> {
67        crate::common::RegisterFieldBool::<1, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
68            self, 0,
69        )
70    }
71
72    #[inline(always)]
73    pub fn wf(self) -> crate::common::RegisterFieldBool<2, 1, 0, Opscr_SPEC, crate::common::RW> {
74        crate::common::RegisterFieldBool::<2, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
75            self, 0,
76        )
77    }
78
79    #[doc = "Input U-Phase Monitor"]
80    #[inline(always)]
81    pub fn u(self) -> crate::common::RegisterFieldBool<4, 1, 0, Opscr_SPEC, crate::common::R> {
82        crate::common::RegisterFieldBool::<4, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
83            self, 0,
84        )
85    }
86
87    #[doc = "Input V-Phase Monitor"]
88    #[inline(always)]
89    pub fn v(self) -> crate::common::RegisterFieldBool<5, 1, 0, Opscr_SPEC, crate::common::R> {
90        crate::common::RegisterFieldBool::<5, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
91            self, 0,
92        )
93    }
94
95    #[doc = "Input W-Phase Monitor"]
96    #[inline(always)]
97    pub fn w(self) -> crate::common::RegisterFieldBool<6, 1, 0, Opscr_SPEC, crate::common::R> {
98        crate::common::RegisterFieldBool::<6, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
99            self, 0,
100        )
101    }
102
103    #[doc = "Output Phase Enable"]
104    #[inline(always)]
105    pub fn en(
106        self,
107    ) -> crate::common::RegisterField<
108        8,
109        0x1,
110        1,
111        0,
112        opscr::En,
113        opscr::En,
114        Opscr_SPEC,
115        crate::common::RW,
116    > {
117        crate::common::RegisterField::<
118            8,
119            0x1,
120            1,
121            0,
122            opscr::En,
123            opscr::En,
124            Opscr_SPEC,
125            crate::common::RW,
126        >::from_register(self, 0)
127    }
128
129    #[doc = "External Feedback Signal Enable"]
130    #[inline(always)]
131    pub fn fb(
132        self,
133    ) -> crate::common::RegisterField<
134        16,
135        0x1,
136        1,
137        0,
138        opscr::Fb,
139        opscr::Fb,
140        Opscr_SPEC,
141        crate::common::RW,
142    > {
143        crate::common::RegisterField::<
144            16,
145            0x1,
146            1,
147            0,
148            opscr::Fb,
149            opscr::Fb,
150            Opscr_SPEC,
151            crate::common::RW,
152        >::from_register(self, 0)
153    }
154
155    #[doc = "Positive-Phase Output (P) Control"]
156    #[inline(always)]
157    pub fn p(
158        self,
159    ) -> crate::common::RegisterField<
160        17,
161        0x1,
162        1,
163        0,
164        opscr::P,
165        opscr::P,
166        Opscr_SPEC,
167        crate::common::RW,
168    > {
169        crate::common::RegisterField::<
170            17,
171            0x1,
172            1,
173            0,
174            opscr::P,
175            opscr::P,
176            Opscr_SPEC,
177            crate::common::RW,
178        >::from_register(self, 0)
179    }
180
181    #[doc = "Negative-Phase Output (N) Control"]
182    #[inline(always)]
183    pub fn n(
184        self,
185    ) -> crate::common::RegisterField<
186        18,
187        0x1,
188        1,
189        0,
190        opscr::N,
191        opscr::N,
192        Opscr_SPEC,
193        crate::common::RW,
194    > {
195        crate::common::RegisterField::<
196            18,
197            0x1,
198            1,
199            0,
200            opscr::N,
201            opscr::N,
202            Opscr_SPEC,
203            crate::common::RW,
204        >::from_register(self, 0)
205    }
206
207    #[doc = "Output Phase Invert Control"]
208    #[inline(always)]
209    pub fn inv(
210        self,
211    ) -> crate::common::RegisterField<
212        19,
213        0x1,
214        1,
215        0,
216        opscr::Inv,
217        opscr::Inv,
218        Opscr_SPEC,
219        crate::common::RW,
220    > {
221        crate::common::RegisterField::<
222            19,
223            0x1,
224            1,
225            0,
226            opscr::Inv,
227            opscr::Inv,
228            Opscr_SPEC,
229            crate::common::RW,
230        >::from_register(self, 0)
231    }
232
233    #[doc = "Output Phase Rotation Direction Reversal Control"]
234    #[inline(always)]
235    pub fn rv(
236        self,
237    ) -> crate::common::RegisterField<
238        20,
239        0x1,
240        1,
241        0,
242        opscr::Rv,
243        opscr::Rv,
244        Opscr_SPEC,
245        crate::common::RW,
246    > {
247        crate::common::RegisterField::<
248            20,
249            0x1,
250            1,
251            0,
252            opscr::Rv,
253            opscr::Rv,
254            Opscr_SPEC,
255            crate::common::RW,
256        >::from_register(self, 0)
257    }
258
259    #[doc = "Input Phase Alignment"]
260    #[inline(always)]
261    pub fn align(
262        self,
263    ) -> crate::common::RegisterField<
264        21,
265        0x1,
266        1,
267        0,
268        opscr::Align,
269        opscr::Align,
270        Opscr_SPEC,
271        crate::common::RW,
272    > {
273        crate::common::RegisterField::<
274            21,
275            0x1,
276            1,
277            0,
278            opscr::Align,
279            opscr::Align,
280            Opscr_SPEC,
281            crate::common::RW,
282        >::from_register(self, 0)
283    }
284
285    #[doc = "Output Disabled Source Selection"]
286    #[inline(always)]
287    pub fn grp(
288        self,
289    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, Opscr_SPEC, crate::common::RW> {
290        crate::common::RegisterField::<24,0x3,1,0,u8,u8,Opscr_SPEC,crate::common::RW>::from_register(self,0)
291    }
292
293    #[doc = "Group Output Disable Function"]
294    #[inline(always)]
295    pub fn godf(
296        self,
297    ) -> crate::common::RegisterField<
298        26,
299        0x1,
300        1,
301        0,
302        opscr::Godf,
303        opscr::Godf,
304        Opscr_SPEC,
305        crate::common::RW,
306    > {
307        crate::common::RegisterField::<
308            26,
309            0x1,
310            1,
311            0,
312            opscr::Godf,
313            opscr::Godf,
314            Opscr_SPEC,
315            crate::common::RW,
316        >::from_register(self, 0)
317    }
318}
319impl ::core::default::Default for Opscr {
320    #[inline(always)]
321    fn default() -> Opscr {
322        <crate::RegValueT<Opscr_SPEC> as RegisterValue<_>>::new(0)
323    }
324}
325pub mod opscr {
326
327    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
328    pub struct En_SPEC;
329    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
330    impl En {
331        #[doc = "Do not output (Hi-Z external pin)"]
332        pub const _0: Self = Self::new(0);
333
334        #[doc = "Output"]
335        pub const _1: Self = Self::new(1);
336    }
337    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
338    pub struct Fb_SPEC;
339    pub type Fb = crate::EnumBitfieldStruct<u8, Fb_SPEC>;
340    impl Fb {
341        #[doc = "Software settings are disabled (OPSCR.UF, VF, WF)"]
342        pub const _0: Self = Self::new(0);
343
344        #[doc = "Software settings are enabled (OPSCR.UF, VF, WF)"]
345        pub const _1: Self = Self::new(1);
346    }
347    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
348    pub struct P_SPEC;
349    pub type P = crate::EnumBitfieldStruct<u8, P_SPEC>;
350    impl P {
351        #[doc = "Level signal output"]
352        pub const _0: Self = Self::new(0);
353
354        #[doc = "PWM signal output"]
355        pub const _1: Self = Self::new(1);
356    }
357    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
358    pub struct N_SPEC;
359    pub type N = crate::EnumBitfieldStruct<u8, N_SPEC>;
360    impl N {
361        #[doc = "Level signal output"]
362        pub const _0: Self = Self::new(0);
363
364        #[doc = "PWM signal output"]
365        pub const _1: Self = Self::new(1);
366    }
367    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
368    pub struct Inv_SPEC;
369    pub type Inv = crate::EnumBitfieldStruct<u8, Inv_SPEC>;
370    impl Inv {
371        #[doc = "Positive logic (active-high) output"]
372        pub const _0: Self = Self::new(0);
373
374        #[doc = "Negative logic (active-low) output"]
375        pub const _1: Self = Self::new(1);
376    }
377    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
378    pub struct Rv_SPEC;
379    pub type Rv = crate::EnumBitfieldStruct<u8, Rv_SPEC>;
380    impl Rv {
381        #[doc = "Positive rotation"]
382        pub const _0: Self = Self::new(0);
383
384        #[doc = "Reverse rotation"]
385        pub const _1: Self = Self::new(1);
386    }
387    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
388    pub struct Align_SPEC;
389    pub type Align = crate::EnumBitfieldStruct<u8, Align_SPEC>;
390    impl Align {
391        #[doc = "Input phase aligned to PCLKD"]
392        pub const _0: Self = Self::new(0);
393
394        #[doc = "Input phase aligned to the falling edge of PWM"]
395        pub const _1: Self = Self::new(1);
396    }
397    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
398    pub struct Godf_SPEC;
399    pub type Godf = crate::EnumBitfieldStruct<u8, Godf_SPEC>;
400    impl Godf {
401        #[doc = "This bit function is ignored"]
402        pub const _0: Self = Self::new(0);
403
404        #[doc = "Group disable clears the OPSCR.EN bit"]
405        pub const _1: Self = Self::new(1);
406    }
407}
ra2e3_pac/gpt_ops.rs

ra2e3_pac/
gpt_ops.rs
