ra2e1/sci0/
smr_smci.rs

1#[doc = "Register `SMR_SMCI` reader"]
2pub struct R(crate::R<SMR_SMCI_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<SMR_SMCI_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<SMR_SMCI_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<SMR_SMCI_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `SMR_SMCI` writer"]
17pub struct W(crate::W<SMR_SMCI_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<SMR_SMCI_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<SMR_SMCI_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<SMR_SMCI_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CKS` reader - Clock Select"]
38pub type CKS_R = crate::FieldReader<u8, CKS_A>;
39#[doc = "Clock Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CKS_A {
43    #[doc = "0: PCLK clock (n = 0)"]
44    _00 = 0,
45    #[doc = "1: PCLK/4 clock (n = 1)"]
46    _01 = 1,
47    #[doc = "2: PCLK/16 clock (n = 2)"]
48    _10 = 2,
49    #[doc = "3: PCLK/64 clock (n = 3)"]
50    _11 = 3,
51}
52impl From<CKS_A> for u8 {
53    #[inline(always)]
54    fn from(variant: CKS_A) -> Self {
55        variant as _
56    }
57}
58impl CKS_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> CKS_A {
62        match self.bits {
63            0 => CKS_A::_00,
64            1 => CKS_A::_01,
65            2 => CKS_A::_10,
66            3 => CKS_A::_11,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_00`"]
71    #[inline(always)]
72    pub fn is_00(&self) -> bool {
73        *self == CKS_A::_00
74    }
75    #[doc = "Checks if the value of the field is `_01`"]
76    #[inline(always)]
77    pub fn is_01(&self) -> bool {
78        *self == CKS_A::_01
79    }
80    #[doc = "Checks if the value of the field is `_10`"]
81    #[inline(always)]
82    pub fn is_10(&self) -> bool {
83        *self == CKS_A::_10
84    }
85    #[doc = "Checks if the value of the field is `_11`"]
86    #[inline(always)]
87    pub fn is_11(&self) -> bool {
88        *self == CKS_A::_11
89    }
90}
91#[doc = "Field `CKS` writer - Clock Select"]
92pub type CKS_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, SMR_SMCI_SPEC, u8, CKS_A, 2, O>;
93impl<'a, const O: u8> CKS_W<'a, O> {
94    #[doc = "PCLK clock (n = 0)"]
95    #[inline(always)]
96    pub fn _00(self) -> &'a mut W {
97        self.variant(CKS_A::_00)
98    }
99    #[doc = "PCLK/4 clock (n = 1)"]
100    #[inline(always)]
101    pub fn _01(self) -> &'a mut W {
102        self.variant(CKS_A::_01)
103    }
104    #[doc = "PCLK/16 clock (n = 2)"]
105    #[inline(always)]
106    pub fn _10(self) -> &'a mut W {
107        self.variant(CKS_A::_10)
108    }
109    #[doc = "PCLK/64 clock (n = 3)"]
110    #[inline(always)]
111    pub fn _11(self) -> &'a mut W {
112        self.variant(CKS_A::_11)
113    }
114}
115#[doc = "Field `BCP` reader - Base Clock Pulse"]
116pub type BCP_R = crate::FieldReader<u8, u8>;
117#[doc = "Field `BCP` writer - Base Clock Pulse"]
118pub type BCP_W<'a, const O: u8> = crate::FieldWriter<'a, u8, SMR_SMCI_SPEC, u8, u8, 2, O>;
119#[doc = "Field `PM` reader - Parity Mode"]
120pub type PM_R = crate::BitReader<PM_A>;
121#[doc = "Parity Mode\n\nValue on reset: 0"]
122#[derive(Clone, Copy, Debug, PartialEq, Eq)]
123pub enum PM_A {
124    #[doc = "0: Even parity"]
125    _0 = 0,
126    #[doc = "1: Odd parity"]
127    _1 = 1,
128}
129impl From<PM_A> for bool {
130    #[inline(always)]
131    fn from(variant: PM_A) -> Self {
132        variant as u8 != 0
133    }
134}
135impl PM_R {
136    #[doc = "Get enumerated values variant"]
137    #[inline(always)]
138    pub fn variant(&self) -> PM_A {
139        match self.bits {
140            false => PM_A::_0,
141            true => PM_A::_1,
142        }
143    }
144    #[doc = "Checks if the value of the field is `_0`"]
145    #[inline(always)]
146    pub fn is_0(&self) -> bool {
147        *self == PM_A::_0
148    }
149    #[doc = "Checks if the value of the field is `_1`"]
150    #[inline(always)]
151    pub fn is_1(&self) -> bool {
152        *self == PM_A::_1
153    }
154}
155#[doc = "Field `PM` writer - Parity Mode"]
156pub type PM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SMCI_SPEC, PM_A, O>;
157impl<'a, const O: u8> PM_W<'a, O> {
158    #[doc = "Even parity"]
159    #[inline(always)]
160    pub fn _0(self) -> &'a mut W {
161        self.variant(PM_A::_0)
162    }
163    #[doc = "Odd parity"]
164    #[inline(always)]
165    pub fn _1(self) -> &'a mut W {
166        self.variant(PM_A::_1)
167    }
168}
169#[doc = "Field `PE` reader - Parity Enable"]
170pub type PE_R = crate::BitReader<bool>;
171#[doc = "Field `PE` writer - Parity Enable"]
172pub type PE_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SMCI_SPEC, bool, O>;
173#[doc = "Field `BLK` reader - Block Transfer Mode"]
174pub type BLK_R = crate::BitReader<BLK_A>;
175#[doc = "Block Transfer Mode\n\nValue on reset: 0"]
176#[derive(Clone, Copy, Debug, PartialEq, Eq)]
177pub enum BLK_A {
178    #[doc = "0: Normal mode operation"]
179    _0 = 0,
180    #[doc = "1: Block transfer mode operation"]
181    _1 = 1,
182}
183impl From<BLK_A> for bool {
184    #[inline(always)]
185    fn from(variant: BLK_A) -> Self {
186        variant as u8 != 0
187    }
188}
189impl BLK_R {
190    #[doc = "Get enumerated values variant"]
191    #[inline(always)]
192    pub fn variant(&self) -> BLK_A {
193        match self.bits {
194            false => BLK_A::_0,
195            true => BLK_A::_1,
196        }
197    }
198    #[doc = "Checks if the value of the field is `_0`"]
199    #[inline(always)]
200    pub fn is_0(&self) -> bool {
201        *self == BLK_A::_0
202    }
203    #[doc = "Checks if the value of the field is `_1`"]
204    #[inline(always)]
205    pub fn is_1(&self) -> bool {
206        *self == BLK_A::_1
207    }
208}
209#[doc = "Field `BLK` writer - Block Transfer Mode"]
210pub type BLK_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SMCI_SPEC, BLK_A, O>;
211impl<'a, const O: u8> BLK_W<'a, O> {
212    #[doc = "Normal mode operation"]
213    #[inline(always)]
214    pub fn _0(self) -> &'a mut W {
215        self.variant(BLK_A::_0)
216    }
217    #[doc = "Block transfer mode operation"]
218    #[inline(always)]
219    pub fn _1(self) -> &'a mut W {
220        self.variant(BLK_A::_1)
221    }
222}
223#[doc = "Field `GM` reader - GSM Mode"]
224pub type GM_R = crate::BitReader<GM_A>;
225#[doc = "GSM Mode\n\nValue on reset: 0"]
226#[derive(Clone, Copy, Debug, PartialEq, Eq)]
227pub enum GM_A {
228    #[doc = "0: Normal mode operation"]
229    _0 = 0,
230    #[doc = "1: GSM mode operation"]
231    _1 = 1,
232}
233impl From<GM_A> for bool {
234    #[inline(always)]
235    fn from(variant: GM_A) -> Self {
236        variant as u8 != 0
237    }
238}
239impl GM_R {
240    #[doc = "Get enumerated values variant"]
241    #[inline(always)]
242    pub fn variant(&self) -> GM_A {
243        match self.bits {
244            false => GM_A::_0,
245            true => GM_A::_1,
246        }
247    }
248    #[doc = "Checks if the value of the field is `_0`"]
249    #[inline(always)]
250    pub fn is_0(&self) -> bool {
251        *self == GM_A::_0
252    }
253    #[doc = "Checks if the value of the field is `_1`"]
254    #[inline(always)]
255    pub fn is_1(&self) -> bool {
256        *self == GM_A::_1
257    }
258}
259#[doc = "Field `GM` writer - GSM Mode"]
260pub type GM_W<'a, const O: u8> = crate::BitWriter<'a, u8, SMR_SMCI_SPEC, GM_A, O>;
261impl<'a, const O: u8> GM_W<'a, O> {
262    #[doc = "Normal mode operation"]
263    #[inline(always)]
264    pub fn _0(self) -> &'a mut W {
265        self.variant(GM_A::_0)
266    }
267    #[doc = "GSM mode operation"]
268    #[inline(always)]
269    pub fn _1(self) -> &'a mut W {
270        self.variant(GM_A::_1)
271    }
272}
273impl R {
274    #[doc = "Bits 0:1 - Clock Select"]
275    #[inline(always)]
276    pub fn cks(&self) -> CKS_R {
277        CKS_R::new(self.bits & 3)
278    }
279    #[doc = "Bits 2:3 - Base Clock Pulse"]
280    #[inline(always)]
281    pub fn bcp(&self) -> BCP_R {
282        BCP_R::new((self.bits >> 2) & 3)
283    }
284    #[doc = "Bit 4 - Parity Mode"]
285    #[inline(always)]
286    pub fn pm(&self) -> PM_R {
287        PM_R::new(((self.bits >> 4) & 1) != 0)
288    }
289    #[doc = "Bit 5 - Parity Enable"]
290    #[inline(always)]
291    pub fn pe(&self) -> PE_R {
292        PE_R::new(((self.bits >> 5) & 1) != 0)
293    }
294    #[doc = "Bit 6 - Block Transfer Mode"]
295    #[inline(always)]
296    pub fn blk(&self) -> BLK_R {
297        BLK_R::new(((self.bits >> 6) & 1) != 0)
298    }
299    #[doc = "Bit 7 - GSM Mode"]
300    #[inline(always)]
301    pub fn gm(&self) -> GM_R {
302        GM_R::new(((self.bits >> 7) & 1) != 0)
303    }
304}
305impl W {
306    #[doc = "Bits 0:1 - Clock Select"]
307    #[inline(always)]
308    #[must_use]
309    pub fn cks(&mut self) -> CKS_W<0> {
310        CKS_W::new(self)
311    }
312    #[doc = "Bits 2:3 - Base Clock Pulse"]
313    #[inline(always)]
314    #[must_use]
315    pub fn bcp(&mut self) -> BCP_W<2> {
316        BCP_W::new(self)
317    }
318    #[doc = "Bit 4 - Parity Mode"]
319    #[inline(always)]
320    #[must_use]
321    pub fn pm(&mut self) -> PM_W<4> {
322        PM_W::new(self)
323    }
324    #[doc = "Bit 5 - Parity Enable"]
325    #[inline(always)]
326    #[must_use]
327    pub fn pe(&mut self) -> PE_W<5> {
328        PE_W::new(self)
329    }
330    #[doc = "Bit 6 - Block Transfer Mode"]
331    #[inline(always)]
332    #[must_use]
333    pub fn blk(&mut self) -> BLK_W<6> {
334        BLK_W::new(self)
335    }
336    #[doc = "Bit 7 - GSM Mode"]
337    #[inline(always)]
338    #[must_use]
339    pub fn gm(&mut self) -> GM_W<7> {
340        GM_W::new(self)
341    }
342    #[doc = "Writes raw bits to the register."]
343    #[inline(always)]
344    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
345        self.0.bits(bits);
346        self
347    }
348}
349#[doc = "Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [smr_smci](index.html) module"]
350pub struct SMR_SMCI_SPEC;
351impl crate::RegisterSpec for SMR_SMCI_SPEC {
352    type Ux = u8;
353}
354#[doc = "`read()` method returns [smr_smci::R](R) reader structure"]
355impl crate::Readable for SMR_SMCI_SPEC {
356    type Reader = R;
357}
358#[doc = "`write(|w| ..)` method takes [smr_smci::W](W) writer structure"]
359impl crate::Writable for SMR_SMCI_SPEC {
360    type Writer = W;
361    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
362    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
363}
364#[doc = "`reset()` method sets SMR_SMCI to value 0"]
365impl crate::Resettable for SMR_SMCI_SPEC {
366    const RESET_VALUE: Self::Ux = 0;
367}
ra2e1/sci0/smr_smci.rs

ra2e1/sci0/
smr_smci.rs
