ra2e1/acmplp/
compfir.rs

1#[doc = "Register `COMPFIR` reader"]
2pub struct R(crate::R<COMPFIR_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<COMPFIR_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<COMPFIR_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<COMPFIR_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `COMPFIR` writer"]
17pub struct W(crate::W<COMPFIR_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<COMPFIR_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<COMPFIR_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<COMPFIR_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `C0FCK` reader - ACMPLP0 Filter Select"]
38pub type C0FCK_R = crate::FieldReader<u8, C0FCK_A>;
39#[doc = "ACMPLP0 Filter Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum C0FCK_A {
43    #[doc = "0: No Sampling (bypass)"]
44    _00 = 0,
45    #[doc = "1: Sampling at PCLKB"]
46    _01 = 1,
47    #[doc = "2: Sampling at PCLKB/8"]
48    _10 = 2,
49    #[doc = "3: Sampling at PCLKB/32"]
50    _11 = 3,
51}
52impl From<C0FCK_A> for u8 {
53    #[inline(always)]
54    fn from(variant: C0FCK_A) -> Self {
55        variant as _
56    }
57}
58impl C0FCK_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> C0FCK_A {
62        match self.bits {
63            0 => C0FCK_A::_00,
64            1 => C0FCK_A::_01,
65            2 => C0FCK_A::_10,
66            3 => C0FCK_A::_11,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `_00`"]
71    #[inline(always)]
72    pub fn is_00(&self) -> bool {
73        *self == C0FCK_A::_00
74    }
75    #[doc = "Checks if the value of the field is `_01`"]
76    #[inline(always)]
77    pub fn is_01(&self) -> bool {
78        *self == C0FCK_A::_01
79    }
80    #[doc = "Checks if the value of the field is `_10`"]
81    #[inline(always)]
82    pub fn is_10(&self) -> bool {
83        *self == C0FCK_A::_10
84    }
85    #[doc = "Checks if the value of the field is `_11`"]
86    #[inline(always)]
87    pub fn is_11(&self) -> bool {
88        *self == C0FCK_A::_11
89    }
90}
91#[doc = "Field `C0FCK` writer - ACMPLP0 Filter Select"]
92pub type C0FCK_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, COMPFIR_SPEC, u8, C0FCK_A, 2, O>;
93impl<'a, const O: u8> C0FCK_W<'a, O> {
94    #[doc = "No Sampling (bypass)"]
95    #[inline(always)]
96    pub fn _00(self) -> &'a mut W {
97        self.variant(C0FCK_A::_00)
98    }
99    #[doc = "Sampling at PCLKB"]
100    #[inline(always)]
101    pub fn _01(self) -> &'a mut W {
102        self.variant(C0FCK_A::_01)
103    }
104    #[doc = "Sampling at PCLKB/8"]
105    #[inline(always)]
106    pub fn _10(self) -> &'a mut W {
107        self.variant(C0FCK_A::_10)
108    }
109    #[doc = "Sampling at PCLKB/32"]
110    #[inline(always)]
111    pub fn _11(self) -> &'a mut W {
112        self.variant(C0FCK_A::_11)
113    }
114}
115#[doc = "Field `C0EPO` reader - ACMPLP0 Edge Polarity Switching"]
116pub type C0EPO_R = crate::BitReader<C0EPO_A>;
117#[doc = "ACMPLP0 Edge Polarity Switching\n\nValue on reset: 0"]
118#[derive(Clone, Copy, Debug, PartialEq, Eq)]
119pub enum C0EPO_A {
120    #[doc = "0: Interrupt and ELC event request on rising edge"]
121    _0 = 0,
122    #[doc = "1: Interrupt and ELC event request on falling edge"]
123    _1 = 1,
124}
125impl From<C0EPO_A> for bool {
126    #[inline(always)]
127    fn from(variant: C0EPO_A) -> Self {
128        variant as u8 != 0
129    }
130}
131impl C0EPO_R {
132    #[doc = "Get enumerated values variant"]
133    #[inline(always)]
134    pub fn variant(&self) -> C0EPO_A {
135        match self.bits {
136            false => C0EPO_A::_0,
137            true => C0EPO_A::_1,
138        }
139    }
140    #[doc = "Checks if the value of the field is `_0`"]
141    #[inline(always)]
142    pub fn is_0(&self) -> bool {
143        *self == C0EPO_A::_0
144    }
145    #[doc = "Checks if the value of the field is `_1`"]
146    #[inline(always)]
147    pub fn is_1(&self) -> bool {
148        *self == C0EPO_A::_1
149    }
150}
151#[doc = "Field `C0EPO` writer - ACMPLP0 Edge Polarity Switching"]
152pub type C0EPO_W<'a, const O: u8> = crate::BitWriter<'a, u8, COMPFIR_SPEC, C0EPO_A, O>;
153impl<'a, const O: u8> C0EPO_W<'a, O> {
154    #[doc = "Interrupt and ELC event request on rising edge"]
155    #[inline(always)]
156    pub fn _0(self) -> &'a mut W {
157        self.variant(C0EPO_A::_0)
158    }
159    #[doc = "Interrupt and ELC event request on falling edge"]
160    #[inline(always)]
161    pub fn _1(self) -> &'a mut W {
162        self.variant(C0EPO_A::_1)
163    }
164}
165#[doc = "Field `C0EDG` reader - ACMPLP0 Edge Detection Selection"]
166pub type C0EDG_R = crate::BitReader<C0EDG_A>;
167#[doc = "ACMPLP0 Edge Detection Selection\n\nValue on reset: 0"]
168#[derive(Clone, Copy, Debug, PartialEq, Eq)]
169pub enum C0EDG_A {
170    #[doc = "0: Interrupt and ELC event request by one-edge detection"]
171    _0 = 0,
172    #[doc = "1: Interrupt and ELC event request by both-edge detection"]
173    _1 = 1,
174}
175impl From<C0EDG_A> for bool {
176    #[inline(always)]
177    fn from(variant: C0EDG_A) -> Self {
178        variant as u8 != 0
179    }
180}
181impl C0EDG_R {
182    #[doc = "Get enumerated values variant"]
183    #[inline(always)]
184    pub fn variant(&self) -> C0EDG_A {
185        match self.bits {
186            false => C0EDG_A::_0,
187            true => C0EDG_A::_1,
188        }
189    }
190    #[doc = "Checks if the value of the field is `_0`"]
191    #[inline(always)]
192    pub fn is_0(&self) -> bool {
193        *self == C0EDG_A::_0
194    }
195    #[doc = "Checks if the value of the field is `_1`"]
196    #[inline(always)]
197    pub fn is_1(&self) -> bool {
198        *self == C0EDG_A::_1
199    }
200}
201#[doc = "Field `C0EDG` writer - ACMPLP0 Edge Detection Selection"]
202pub type C0EDG_W<'a, const O: u8> = crate::BitWriter<'a, u8, COMPFIR_SPEC, C0EDG_A, O>;
203impl<'a, const O: u8> C0EDG_W<'a, O> {
204    #[doc = "Interrupt and ELC event request by one-edge detection"]
205    #[inline(always)]
206    pub fn _0(self) -> &'a mut W {
207        self.variant(C0EDG_A::_0)
208    }
209    #[doc = "Interrupt and ELC event request by both-edge detection"]
210    #[inline(always)]
211    pub fn _1(self) -> &'a mut W {
212        self.variant(C0EDG_A::_1)
213    }
214}
215#[doc = "Field `C1FCK` reader - ACMPLP1 Filter Select"]
216pub type C1FCK_R = crate::FieldReader<u8, C1FCK_A>;
217#[doc = "ACMPLP1 Filter Select\n\nValue on reset: 0"]
218#[derive(Clone, Copy, Debug, PartialEq, Eq)]
219#[repr(u8)]
220pub enum C1FCK_A {
221    #[doc = "0: No Sampling (bypass)"]
222    _00 = 0,
223    #[doc = "1: Sampling at PCLKB"]
224    _01 = 1,
225    #[doc = "2: Sampling at PCLKB/8"]
226    _10 = 2,
227    #[doc = "3: Sampling at PCLKB/32"]
228    _11 = 3,
229}
230impl From<C1FCK_A> for u8 {
231    #[inline(always)]
232    fn from(variant: C1FCK_A) -> Self {
233        variant as _
234    }
235}
236impl C1FCK_R {
237    #[doc = "Get enumerated values variant"]
238    #[inline(always)]
239    pub fn variant(&self) -> C1FCK_A {
240        match self.bits {
241            0 => C1FCK_A::_00,
242            1 => C1FCK_A::_01,
243            2 => C1FCK_A::_10,
244            3 => C1FCK_A::_11,
245            _ => unreachable!(),
246        }
247    }
248    #[doc = "Checks if the value of the field is `_00`"]
249    #[inline(always)]
250    pub fn is_00(&self) -> bool {
251        *self == C1FCK_A::_00
252    }
253    #[doc = "Checks if the value of the field is `_01`"]
254    #[inline(always)]
255    pub fn is_01(&self) -> bool {
256        *self == C1FCK_A::_01
257    }
258    #[doc = "Checks if the value of the field is `_10`"]
259    #[inline(always)]
260    pub fn is_10(&self) -> bool {
261        *self == C1FCK_A::_10
262    }
263    #[doc = "Checks if the value of the field is `_11`"]
264    #[inline(always)]
265    pub fn is_11(&self) -> bool {
266        *self == C1FCK_A::_11
267    }
268}
269#[doc = "Field `C1FCK` writer - ACMPLP1 Filter Select"]
270pub type C1FCK_W<'a, const O: u8> = crate::FieldWriterSafe<'a, u8, COMPFIR_SPEC, u8, C1FCK_A, 2, O>;
271impl<'a, const O: u8> C1FCK_W<'a, O> {
272    #[doc = "No Sampling (bypass)"]
273    #[inline(always)]
274    pub fn _00(self) -> &'a mut W {
275        self.variant(C1FCK_A::_00)
276    }
277    #[doc = "Sampling at PCLKB"]
278    #[inline(always)]
279    pub fn _01(self) -> &'a mut W {
280        self.variant(C1FCK_A::_01)
281    }
282    #[doc = "Sampling at PCLKB/8"]
283    #[inline(always)]
284    pub fn _10(self) -> &'a mut W {
285        self.variant(C1FCK_A::_10)
286    }
287    #[doc = "Sampling at PCLKB/32"]
288    #[inline(always)]
289    pub fn _11(self) -> &'a mut W {
290        self.variant(C1FCK_A::_11)
291    }
292}
293#[doc = "Field `C1EPO` reader - ACMPLP1 Edge Polarity Switching"]
294pub type C1EPO_R = crate::BitReader<C1EPO_A>;
295#[doc = "ACMPLP1 Edge Polarity Switching\n\nValue on reset: 0"]
296#[derive(Clone, Copy, Debug, PartialEq, Eq)]
297pub enum C1EPO_A {
298    #[doc = "0: Interrupt and ELC event request on rising edge"]
299    _0 = 0,
300    #[doc = "1: Interrupt and ELC event request on falling edge"]
301    _1 = 1,
302}
303impl From<C1EPO_A> for bool {
304    #[inline(always)]
305    fn from(variant: C1EPO_A) -> Self {
306        variant as u8 != 0
307    }
308}
309impl C1EPO_R {
310    #[doc = "Get enumerated values variant"]
311    #[inline(always)]
312    pub fn variant(&self) -> C1EPO_A {
313        match self.bits {
314            false => C1EPO_A::_0,
315            true => C1EPO_A::_1,
316        }
317    }
318    #[doc = "Checks if the value of the field is `_0`"]
319    #[inline(always)]
320    pub fn is_0(&self) -> bool {
321        *self == C1EPO_A::_0
322    }
323    #[doc = "Checks if the value of the field is `_1`"]
324    #[inline(always)]
325    pub fn is_1(&self) -> bool {
326        *self == C1EPO_A::_1
327    }
328}
329#[doc = "Field `C1EPO` writer - ACMPLP1 Edge Polarity Switching"]
330pub type C1EPO_W<'a, const O: u8> = crate::BitWriter<'a, u8, COMPFIR_SPEC, C1EPO_A, O>;
331impl<'a, const O: u8> C1EPO_W<'a, O> {
332    #[doc = "Interrupt and ELC event request on rising edge"]
333    #[inline(always)]
334    pub fn _0(self) -> &'a mut W {
335        self.variant(C1EPO_A::_0)
336    }
337    #[doc = "Interrupt and ELC event request on falling edge"]
338    #[inline(always)]
339    pub fn _1(self) -> &'a mut W {
340        self.variant(C1EPO_A::_1)
341    }
342}
343#[doc = "Field `C1EDG` reader - ACMPLP1 Edge Detection Selection"]
344pub type C1EDG_R = crate::BitReader<C1EDG_A>;
345#[doc = "ACMPLP1 Edge Detection Selection\n\nValue on reset: 0"]
346#[derive(Clone, Copy, Debug, PartialEq, Eq)]
347pub enum C1EDG_A {
348    #[doc = "0: Interrupt and ELC event request by one-edge detection"]
349    _0 = 0,
350    #[doc = "1: Interrupt and ELC event request by both-edge detection"]
351    _1 = 1,
352}
353impl From<C1EDG_A> for bool {
354    #[inline(always)]
355    fn from(variant: C1EDG_A) -> Self {
356        variant as u8 != 0
357    }
358}
359impl C1EDG_R {
360    #[doc = "Get enumerated values variant"]
361    #[inline(always)]
362    pub fn variant(&self) -> C1EDG_A {
363        match self.bits {
364            false => C1EDG_A::_0,
365            true => C1EDG_A::_1,
366        }
367    }
368    #[doc = "Checks if the value of the field is `_0`"]
369    #[inline(always)]
370    pub fn is_0(&self) -> bool {
371        *self == C1EDG_A::_0
372    }
373    #[doc = "Checks if the value of the field is `_1`"]
374    #[inline(always)]
375    pub fn is_1(&self) -> bool {
376        *self == C1EDG_A::_1
377    }
378}
379#[doc = "Field `C1EDG` writer - ACMPLP1 Edge Detection Selection"]
380pub type C1EDG_W<'a, const O: u8> = crate::BitWriter<'a, u8, COMPFIR_SPEC, C1EDG_A, O>;
381impl<'a, const O: u8> C1EDG_W<'a, O> {
382    #[doc = "Interrupt and ELC event request by one-edge detection"]
383    #[inline(always)]
384    pub fn _0(self) -> &'a mut W {
385        self.variant(C1EDG_A::_0)
386    }
387    #[doc = "Interrupt and ELC event request by both-edge detection"]
388    #[inline(always)]
389    pub fn _1(self) -> &'a mut W {
390        self.variant(C1EDG_A::_1)
391    }
392}
393impl R {
394    #[doc = "Bits 0:1 - ACMPLP0 Filter Select"]
395    #[inline(always)]
396    pub fn c0fck(&self) -> C0FCK_R {
397        C0FCK_R::new(self.bits & 3)
398    }
399    #[doc = "Bit 2 - ACMPLP0 Edge Polarity Switching"]
400    #[inline(always)]
401    pub fn c0epo(&self) -> C0EPO_R {
402        C0EPO_R::new(((self.bits >> 2) & 1) != 0)
403    }
404    #[doc = "Bit 3 - ACMPLP0 Edge Detection Selection"]
405    #[inline(always)]
406    pub fn c0edg(&self) -> C0EDG_R {
407        C0EDG_R::new(((self.bits >> 3) & 1) != 0)
408    }
409    #[doc = "Bits 4:5 - ACMPLP1 Filter Select"]
410    #[inline(always)]
411    pub fn c1fck(&self) -> C1FCK_R {
412        C1FCK_R::new((self.bits >> 4) & 3)
413    }
414    #[doc = "Bit 6 - ACMPLP1 Edge Polarity Switching"]
415    #[inline(always)]
416    pub fn c1epo(&self) -> C1EPO_R {
417        C1EPO_R::new(((self.bits >> 6) & 1) != 0)
418    }
419    #[doc = "Bit 7 - ACMPLP1 Edge Detection Selection"]
420    #[inline(always)]
421    pub fn c1edg(&self) -> C1EDG_R {
422        C1EDG_R::new(((self.bits >> 7) & 1) != 0)
423    }
424}
425impl W {
426    #[doc = "Bits 0:1 - ACMPLP0 Filter Select"]
427    #[inline(always)]
428    #[must_use]
429    pub fn c0fck(&mut self) -> C0FCK_W<0> {
430        C0FCK_W::new(self)
431    }
432    #[doc = "Bit 2 - ACMPLP0 Edge Polarity Switching"]
433    #[inline(always)]
434    #[must_use]
435    pub fn c0epo(&mut self) -> C0EPO_W<2> {
436        C0EPO_W::new(self)
437    }
438    #[doc = "Bit 3 - ACMPLP0 Edge Detection Selection"]
439    #[inline(always)]
440    #[must_use]
441    pub fn c0edg(&mut self) -> C0EDG_W<3> {
442        C0EDG_W::new(self)
443    }
444    #[doc = "Bits 4:5 - ACMPLP1 Filter Select"]
445    #[inline(always)]
446    #[must_use]
447    pub fn c1fck(&mut self) -> C1FCK_W<4> {
448        C1FCK_W::new(self)
449    }
450    #[doc = "Bit 6 - ACMPLP1 Edge Polarity Switching"]
451    #[inline(always)]
452    #[must_use]
453    pub fn c1epo(&mut self) -> C1EPO_W<6> {
454        C1EPO_W::new(self)
455    }
456    #[doc = "Bit 7 - ACMPLP1 Edge Detection Selection"]
457    #[inline(always)]
458    #[must_use]
459    pub fn c1edg(&mut self) -> C1EDG_W<7> {
460        C1EDG_W::new(self)
461    }
462    #[doc = "Writes raw bits to the register."]
463    #[inline(always)]
464    pub unsafe fn bits(&mut self, bits: u8) -> &mut Self {
465        self.0.bits(bits);
466        self
467    }
468}
469#[doc = "ACMPLP Filter Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [compfir](index.html) module"]
470pub struct COMPFIR_SPEC;
471impl crate::RegisterSpec for COMPFIR_SPEC {
472    type Ux = u8;
473}
474#[doc = "`read()` method returns [compfir::R](R) reader structure"]
475impl crate::Readable for COMPFIR_SPEC {
476    type Reader = R;
477}
478#[doc = "`write(|w| ..)` method takes [compfir::W](W) writer structure"]
479impl crate::Writable for COMPFIR_SPEC {
480    type Writer = W;
481    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
482    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
483}
484#[doc = "`reset()` method sets COMPFIR to value 0"]
485impl crate::Resettable for COMPFIR_SPEC {
486    const RESET_VALUE: Self::Ux = 0;
487}
ra2e1/acmplp/compfir.rs

ra2e1/acmplp/
compfir.rs
