ra2e1_pac/
gpt_ops.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.51.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:43 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Output Phase Switching Controller"]
28unsafe impl ::core::marker::Send for super::GptOps {}
29unsafe impl ::core::marker::Sync for super::GptOps {}
30impl super::GptOps {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Output Phase Switching Control Register"]
38    #[inline(always)]
39    pub const fn opscr(&self) -> &'static crate::common::Reg<self::Opscr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Opscr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46}
47#[doc(hidden)]
48#[derive(Copy, Clone, Eq, PartialEq)]
49pub struct Opscr_SPEC;
50impl crate::sealed::RegSpec for Opscr_SPEC {
51    type DataType = u32;
52}
53
54#[doc = "Output Phase Switching Control Register"]
55pub type Opscr = crate::RegValueT<Opscr_SPEC>;
56
57impl Opscr {
58    #[doc = "Input U-Phase Monitor"]
59    #[inline(always)]
60    pub fn u(self) -> crate::common::RegisterFieldBool<4, 1, 0, Opscr_SPEC, crate::common::R> {
61        crate::common::RegisterFieldBool::<4, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
62            self, 0,
63        )
64    }
65
66    #[doc = "Input V-Phase Monitor"]
67    #[inline(always)]
68    pub fn v(self) -> crate::common::RegisterFieldBool<5, 1, 0, Opscr_SPEC, crate::common::R> {
69        crate::common::RegisterFieldBool::<5, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
70            self, 0,
71        )
72    }
73
74    #[doc = "Input W-Phase Monitor"]
75    #[inline(always)]
76    pub fn w(self) -> crate::common::RegisterFieldBool<6, 1, 0, Opscr_SPEC, crate::common::R> {
77        crate::common::RegisterFieldBool::<6, 1, 0, Opscr_SPEC, crate::common::R>::from_register(
78            self, 0,
79        )
80    }
81
82    #[doc = "Output Phase Enable"]
83    #[inline(always)]
84    pub fn en(
85        self,
86    ) -> crate::common::RegisterField<
87        8,
88        0x1,
89        1,
90        0,
91        opscr::En,
92        opscr::En,
93        Opscr_SPEC,
94        crate::common::RW,
95    > {
96        crate::common::RegisterField::<
97            8,
98            0x1,
99            1,
100            0,
101            opscr::En,
102            opscr::En,
103            Opscr_SPEC,
104            crate::common::RW,
105        >::from_register(self, 0)
106    }
107
108    #[doc = "External Feedback Signal Enable"]
109    #[inline(always)]
110    pub fn fb(
111        self,
112    ) -> crate::common::RegisterField<
113        16,
114        0x1,
115        1,
116        0,
117        opscr::Fb,
118        opscr::Fb,
119        Opscr_SPEC,
120        crate::common::RW,
121    > {
122        crate::common::RegisterField::<
123            16,
124            0x1,
125            1,
126            0,
127            opscr::Fb,
128            opscr::Fb,
129            Opscr_SPEC,
130            crate::common::RW,
131        >::from_register(self, 0)
132    }
133
134    #[doc = "Positive-Phase Output (P) Control"]
135    #[inline(always)]
136    pub fn p(
137        self,
138    ) -> crate::common::RegisterField<
139        17,
140        0x1,
141        1,
142        0,
143        opscr::P,
144        opscr::P,
145        Opscr_SPEC,
146        crate::common::RW,
147    > {
148        crate::common::RegisterField::<
149            17,
150            0x1,
151            1,
152            0,
153            opscr::P,
154            opscr::P,
155            Opscr_SPEC,
156            crate::common::RW,
157        >::from_register(self, 0)
158    }
159
160    #[doc = "Negative-Phase Output (N) Control"]
161    #[inline(always)]
162    pub fn n(
163        self,
164    ) -> crate::common::RegisterField<
165        18,
166        0x1,
167        1,
168        0,
169        opscr::N,
170        opscr::N,
171        Opscr_SPEC,
172        crate::common::RW,
173    > {
174        crate::common::RegisterField::<
175            18,
176            0x1,
177            1,
178            0,
179            opscr::N,
180            opscr::N,
181            Opscr_SPEC,
182            crate::common::RW,
183        >::from_register(self, 0)
184    }
185
186    #[doc = "Output Phase Invert Control"]
187    #[inline(always)]
188    pub fn inv(
189        self,
190    ) -> crate::common::RegisterField<
191        19,
192        0x1,
193        1,
194        0,
195        opscr::Inv,
196        opscr::Inv,
197        Opscr_SPEC,
198        crate::common::RW,
199    > {
200        crate::common::RegisterField::<
201            19,
202            0x1,
203            1,
204            0,
205            opscr::Inv,
206            opscr::Inv,
207            Opscr_SPEC,
208            crate::common::RW,
209        >::from_register(self, 0)
210    }
211
212    #[doc = "Output Phase Rotation Direction Reversal Control"]
213    #[inline(always)]
214    pub fn rv(
215        self,
216    ) -> crate::common::RegisterField<
217        20,
218        0x1,
219        1,
220        0,
221        opscr::Rv,
222        opscr::Rv,
223        Opscr_SPEC,
224        crate::common::RW,
225    > {
226        crate::common::RegisterField::<
227            20,
228            0x1,
229            1,
230            0,
231            opscr::Rv,
232            opscr::Rv,
233            Opscr_SPEC,
234            crate::common::RW,
235        >::from_register(self, 0)
236    }
237
238    #[doc = "Input Phase Alignment"]
239    #[inline(always)]
240    pub fn align(
241        self,
242    ) -> crate::common::RegisterField<
243        21,
244        0x1,
245        1,
246        0,
247        opscr::Align,
248        opscr::Align,
249        Opscr_SPEC,
250        crate::common::RW,
251    > {
252        crate::common::RegisterField::<
253            21,
254            0x1,
255            1,
256            0,
257            opscr::Align,
258            opscr::Align,
259            Opscr_SPEC,
260            crate::common::RW,
261        >::from_register(self, 0)
262    }
263
264    #[doc = "Group Output Disable Function"]
265    #[inline(always)]
266    pub fn godf(
267        self,
268    ) -> crate::common::RegisterField<
269        26,
270        0x1,
271        1,
272        0,
273        opscr::Godf,
274        opscr::Godf,
275        Opscr_SPEC,
276        crate::common::RW,
277    > {
278        crate::common::RegisterField::<
279            26,
280            0x1,
281            1,
282            0,
283            opscr::Godf,
284            opscr::Godf,
285            Opscr_SPEC,
286            crate::common::RW,
287        >::from_register(self, 0)
288    }
289
290    #[doc = "External Input Noise Filter Enable"]
291    #[inline(always)]
292    pub fn nfen(
293        self,
294    ) -> crate::common::RegisterField<
295        29,
296        0x1,
297        1,
298        0,
299        opscr::Nfen,
300        opscr::Nfen,
301        Opscr_SPEC,
302        crate::common::RW,
303    > {
304        crate::common::RegisterField::<
305            29,
306            0x1,
307            1,
308            0,
309            opscr::Nfen,
310            opscr::Nfen,
311            Opscr_SPEC,
312            crate::common::RW,
313        >::from_register(self, 0)
314    }
315
316    #[doc = "External Input Noise Filter Clock Selection"]
317    #[inline(always)]
318    pub fn nfcs(
319        self,
320    ) -> crate::common::RegisterField<
321        30,
322        0x3,
323        1,
324        0,
325        opscr::Nfcs,
326        opscr::Nfcs,
327        Opscr_SPEC,
328        crate::common::RW,
329    > {
330        crate::common::RegisterField::<
331            30,
332            0x3,
333            1,
334            0,
335            opscr::Nfcs,
336            opscr::Nfcs,
337            Opscr_SPEC,
338            crate::common::RW,
339        >::from_register(self, 0)
340    }
341}
342impl ::core::default::Default for Opscr {
343    #[inline(always)]
344    fn default() -> Opscr {
345        <crate::RegValueT<Opscr_SPEC> as RegisterValue<_>>::new(0)
346    }
347}
348pub mod opscr {
349
350    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
351    pub struct En_SPEC;
352    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
353    impl En {
354        #[doc = "Do not output (Hi-Z external pin)"]
355        pub const _0: Self = Self::new(0);
356
357        #[doc = "Output"]
358        pub const _1: Self = Self::new(1);
359    }
360    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
361    pub struct Fb_SPEC;
362    pub type Fb = crate::EnumBitfieldStruct<u8, Fb_SPEC>;
363    impl Fb {
364        #[doc = "Select the external input"]
365        pub const _0: Self = Self::new(0);
366
367        #[doc = "Select the soft setting (OPSCR., , )"]
368        pub const _1: Self = Self::new(1);
369    }
370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
371    pub struct P_SPEC;
372    pub type P = crate::EnumBitfieldStruct<u8, P_SPEC>;
373    impl P {
374        #[doc = "Level signal output"]
375        pub const _0: Self = Self::new(0);
376
377        #[doc = "PWM signal output"]
378        pub const _1: Self = Self::new(1);
379    }
380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
381    pub struct N_SPEC;
382    pub type N = crate::EnumBitfieldStruct<u8, N_SPEC>;
383    impl N {
384        #[doc = "Level signal output"]
385        pub const _0: Self = Self::new(0);
386
387        #[doc = "PWM signal output"]
388        pub const _1: Self = Self::new(1);
389    }
390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
391    pub struct Inv_SPEC;
392    pub type Inv = crate::EnumBitfieldStruct<u8, Inv_SPEC>;
393    impl Inv {
394        #[doc = "Positive logic (active-high) output"]
395        pub const _0: Self = Self::new(0);
396
397        #[doc = "Negative logic (active-low) output"]
398        pub const _1: Self = Self::new(1);
399    }
400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
401    pub struct Rv_SPEC;
402    pub type Rv = crate::EnumBitfieldStruct<u8, Rv_SPEC>;
403    impl Rv {
404        #[doc = "Positive rotation"]
405        pub const _0: Self = Self::new(0);
406
407        #[doc = "Reverse rotation"]
408        pub const _1: Self = Self::new(1);
409    }
410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
411    pub struct Align_SPEC;
412    pub type Align = crate::EnumBitfieldStruct<u8, Align_SPEC>;
413    impl Align {
414        #[doc = "Input phase aligned to PCLKD"]
415        pub const _0: Self = Self::new(0);
416
417        #[doc = "Input phase aligned to the falling edge of PWM"]
418        pub const _1: Self = Self::new(1);
419    }
420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
421    pub struct Godf_SPEC;
422    pub type Godf = crate::EnumBitfieldStruct<u8, Godf_SPEC>;
423    impl Godf {
424        #[doc = "This bit function is ignored"]
425        pub const _0: Self = Self::new(0);
426
427        #[doc = "Group disable clears the OPSCR.EN bit"]
428        pub const _1: Self = Self::new(1);
429    }
430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
431    pub struct Nfen_SPEC;
432    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
433    impl Nfen {
434        #[doc = "Do not use a noise filter on the external input"]
435        pub const _0: Self = Self::new(0);
436
437        #[doc = "Use a noise filter on the external input"]
438        pub const _1: Self = Self::new(1);
439    }
440    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
441    pub struct Nfcs_SPEC;
442    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
443    impl Nfcs {
444        #[doc = "PCLKD/1"]
445        pub const _00: Self = Self::new(0);
446
447        #[doc = "PCLKD/4"]
448        pub const _01: Self = Self::new(1);
449
450        #[doc = "PCLKD/16"]
451        pub const _10: Self = Self::new(2);
452
453        #[doc = "PCLKD/64"]
454        pub const _11: Self = Self::new(3);
455    }
456}
ra2e1_pac/gpt_ops.rs

ra2e1_pac/
gpt_ops.rs
