1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"General PWM 16-bit Timer 4"]
28unsafe impl ::core::marker::Send for super::Gpt164 {}
29unsafe impl ::core::marker::Sync for super::Gpt164 {}
30impl super::Gpt164 {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "General PWM Timer Write-Protection Register"]
38 #[inline(always)]
39 pub const fn gtwp(&self) -> &'static crate::common::Reg<self::Gtwp_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Gtwp_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "General PWM Timer Software Start Register"]
48 #[inline(always)]
49 pub const fn gtstr(&self) -> &'static crate::common::Reg<self::Gtstr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Gtstr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(4usize),
53 )
54 }
55 }
56
57 #[doc = "General PWM Timer Software Stop Register"]
58 #[inline(always)]
59 pub const fn gtstp(&self) -> &'static crate::common::Reg<self::Gtstp_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Gtstp_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(8usize),
63 )
64 }
65 }
66
67 #[doc = "General PWM Timer Software Clear Register"]
68 #[inline(always)]
69 pub const fn gtclr(&self) -> &'static crate::common::Reg<self::Gtclr_SPEC, crate::common::W> {
70 unsafe {
71 crate::common::Reg::<self::Gtclr_SPEC, crate::common::W>::from_ptr(
72 self._svd2pac_as_ptr().add(12usize),
73 )
74 }
75 }
76
77 #[doc = "General PWM Timer Start Source Select Register"]
78 #[inline(always)]
79 pub const fn gtssr(&self) -> &'static crate::common::Reg<self::Gtssr_SPEC, crate::common::RW> {
80 unsafe {
81 crate::common::Reg::<self::Gtssr_SPEC, crate::common::RW>::from_ptr(
82 self._svd2pac_as_ptr().add(16usize),
83 )
84 }
85 }
86
87 #[doc = "General PWM Timer Stop Source Select Register"]
88 #[inline(always)]
89 pub const fn gtpsr(&self) -> &'static crate::common::Reg<self::Gtpsr_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Gtpsr_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(20usize),
93 )
94 }
95 }
96
97 #[doc = "General PWM Timer Clear Source Select Register"]
98 #[inline(always)]
99 pub const fn gtcsr(&self) -> &'static crate::common::Reg<self::Gtcsr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Gtcsr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(24usize),
103 )
104 }
105 }
106
107 #[doc = "General PWM Timer Up Count Source Select Register"]
108 #[inline(always)]
109 pub const fn gtupsr(
110 &self,
111 ) -> &'static crate::common::Reg<self::Gtupsr_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Gtupsr_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(28usize),
115 )
116 }
117 }
118
119 #[doc = "General PWM Timer Down Count Source Select Register"]
120 #[inline(always)]
121 pub const fn gtdnsr(
122 &self,
123 ) -> &'static crate::common::Reg<self::Gtdnsr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Gtdnsr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(32usize),
127 )
128 }
129 }
130
131 #[doc = "General PWM Timer Input Capture Source Select Register A"]
132 #[inline(always)]
133 pub const fn gticasr(
134 &self,
135 ) -> &'static crate::common::Reg<self::Gticasr_SPEC, crate::common::RW> {
136 unsafe {
137 crate::common::Reg::<self::Gticasr_SPEC, crate::common::RW>::from_ptr(
138 self._svd2pac_as_ptr().add(36usize),
139 )
140 }
141 }
142
143 #[doc = "General PWM Timer Input Capture Source Select Register B"]
144 #[inline(always)]
145 pub const fn gticbsr(
146 &self,
147 ) -> &'static crate::common::Reg<self::Gticbsr_SPEC, crate::common::RW> {
148 unsafe {
149 crate::common::Reg::<self::Gticbsr_SPEC, crate::common::RW>::from_ptr(
150 self._svd2pac_as_ptr().add(40usize),
151 )
152 }
153 }
154
155 #[doc = "General PWM Timer Control Register"]
156 #[inline(always)]
157 pub const fn gtcr(&self) -> &'static crate::common::Reg<self::Gtcr_SPEC, crate::common::RW> {
158 unsafe {
159 crate::common::Reg::<self::Gtcr_SPEC, crate::common::RW>::from_ptr(
160 self._svd2pac_as_ptr().add(44usize),
161 )
162 }
163 }
164
165 #[doc = "General PWM Timer Count Direction and Duty Setting Register"]
166 #[inline(always)]
167 pub const fn gtuddtyc(
168 &self,
169 ) -> &'static crate::common::Reg<self::Gtuddtyc_SPEC, crate::common::RW> {
170 unsafe {
171 crate::common::Reg::<self::Gtuddtyc_SPEC, crate::common::RW>::from_ptr(
172 self._svd2pac_as_ptr().add(48usize),
173 )
174 }
175 }
176
177 #[doc = "General PWM Timer I/O Control Register"]
178 #[inline(always)]
179 pub const fn gtior(&self) -> &'static crate::common::Reg<self::Gtior_SPEC, crate::common::RW> {
180 unsafe {
181 crate::common::Reg::<self::Gtior_SPEC, crate::common::RW>::from_ptr(
182 self._svd2pac_as_ptr().add(52usize),
183 )
184 }
185 }
186
187 #[doc = "General PWM Timer Interrupt Output Setting Register"]
188 #[inline(always)]
189 pub const fn gtintad(
190 &self,
191 ) -> &'static crate::common::Reg<self::Gtintad_SPEC, crate::common::RW> {
192 unsafe {
193 crate::common::Reg::<self::Gtintad_SPEC, crate::common::RW>::from_ptr(
194 self._svd2pac_as_ptr().add(56usize),
195 )
196 }
197 }
198
199 #[doc = "General PWM Timer Status Register"]
200 #[inline(always)]
201 pub const fn gtst(&self) -> &'static crate::common::Reg<self::Gtst_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Gtst_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(60usize),
205 )
206 }
207 }
208
209 #[doc = "General PWM Timer Buffer Enable Register"]
210 #[inline(always)]
211 pub const fn gtber(&self) -> &'static crate::common::Reg<self::Gtber_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Gtber_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(64usize),
215 )
216 }
217 }
218
219 #[doc = "General PWM Timer Counter"]
220 #[inline(always)]
221 pub const fn gtcnt(&self) -> &'static crate::common::Reg<self::Gtcnt_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::Gtcnt_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(72usize),
225 )
226 }
227 }
228
229 #[doc = "General PWM Timer Compare Capture Register A"]
230 #[inline(always)]
231 pub const fn gtccra(
232 &self,
233 ) -> &'static crate::common::Reg<self::Gtccra_SPEC, crate::common::RW> {
234 unsafe {
235 crate::common::Reg::<self::Gtccra_SPEC, crate::common::RW>::from_ptr(
236 self._svd2pac_as_ptr().add(76usize),
237 )
238 }
239 }
240
241 #[doc = "General PWM Timer Compare Capture Register B"]
242 #[inline(always)]
243 pub const fn gtccrb(
244 &self,
245 ) -> &'static crate::common::Reg<self::Gtccrb_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Gtccrb_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(80usize),
249 )
250 }
251 }
252
253 #[doc = "General PWM Timer Compare Capture Register C"]
254 #[inline(always)]
255 pub const fn gtccrc(
256 &self,
257 ) -> &'static crate::common::Reg<self::Gtccrc_SPEC, crate::common::RW> {
258 unsafe {
259 crate::common::Reg::<self::Gtccrc_SPEC, crate::common::RW>::from_ptr(
260 self._svd2pac_as_ptr().add(84usize),
261 )
262 }
263 }
264
265 #[doc = "General PWM Timer Compare Capture Register E"]
266 #[inline(always)]
267 pub const fn gtccre(
268 &self,
269 ) -> &'static crate::common::Reg<self::Gtccre_SPEC, crate::common::RW> {
270 unsafe {
271 crate::common::Reg::<self::Gtccre_SPEC, crate::common::RW>::from_ptr(
272 self._svd2pac_as_ptr().add(88usize),
273 )
274 }
275 }
276
277 #[doc = "General PWM Timer Compare Capture Register D"]
278 #[inline(always)]
279 pub const fn gtccrd(
280 &self,
281 ) -> &'static crate::common::Reg<self::Gtccrd_SPEC, crate::common::RW> {
282 unsafe {
283 crate::common::Reg::<self::Gtccrd_SPEC, crate::common::RW>::from_ptr(
284 self._svd2pac_as_ptr().add(92usize),
285 )
286 }
287 }
288
289 #[doc = "General PWM Timer Compare Capture Register F"]
290 #[inline(always)]
291 pub const fn gtccrf(
292 &self,
293 ) -> &'static crate::common::Reg<self::Gtccrf_SPEC, crate::common::RW> {
294 unsafe {
295 crate::common::Reg::<self::Gtccrf_SPEC, crate::common::RW>::from_ptr(
296 self._svd2pac_as_ptr().add(96usize),
297 )
298 }
299 }
300
301 #[doc = "General PWM Timer Cycle Setting Register"]
302 #[inline(always)]
303 pub const fn gtpr(&self) -> &'static crate::common::Reg<self::Gtpr_SPEC, crate::common::RW> {
304 unsafe {
305 crate::common::Reg::<self::Gtpr_SPEC, crate::common::RW>::from_ptr(
306 self._svd2pac_as_ptr().add(100usize),
307 )
308 }
309 }
310
311 #[doc = "General PWM Timer Cycle Setting Buffer Register"]
312 #[inline(always)]
313 pub const fn gtpbr(&self) -> &'static crate::common::Reg<self::Gtpbr_SPEC, crate::common::RW> {
314 unsafe {
315 crate::common::Reg::<self::Gtpbr_SPEC, crate::common::RW>::from_ptr(
316 self._svd2pac_as_ptr().add(104usize),
317 )
318 }
319 }
320
321 #[doc = "General PWM Timer Dead Time Control Register"]
322 #[inline(always)]
323 pub const fn gtdtcr(
324 &self,
325 ) -> &'static crate::common::Reg<self::Gtdtcr_SPEC, crate::common::RW> {
326 unsafe {
327 crate::common::Reg::<self::Gtdtcr_SPEC, crate::common::RW>::from_ptr(
328 self._svd2pac_as_ptr().add(136usize),
329 )
330 }
331 }
332
333 #[doc = "General PWM Timer Dead Time Value Register U"]
334 #[inline(always)]
335 pub const fn gtdvu(&self) -> &'static crate::common::Reg<self::Gtdvu_SPEC, crate::common::RW> {
336 unsafe {
337 crate::common::Reg::<self::Gtdvu_SPEC, crate::common::RW>::from_ptr(
338 self._svd2pac_as_ptr().add(140usize),
339 )
340 }
341 }
342}
343#[doc(hidden)]
344#[derive(Copy, Clone, Eq, PartialEq)]
345pub struct Gtwp_SPEC;
346impl crate::sealed::RegSpec for Gtwp_SPEC {
347 type DataType = u32;
348}
349
350#[doc = "General PWM Timer Write-Protection Register"]
351pub type Gtwp = crate::RegValueT<Gtwp_SPEC>;
352
353impl Gtwp {
354 #[doc = "Register Write Disable"]
355 #[inline(always)]
356 pub fn wp(
357 self,
358 ) -> crate::common::RegisterField<0, 0x1, 1, 0, gtwp::Wp, gtwp::Wp, Gtwp_SPEC, crate::common::RW>
359 {
360 crate::common::RegisterField::<0,0x1,1,0,gtwp::Wp,gtwp::Wp,Gtwp_SPEC,crate::common::RW>::from_register(self,0)
361 }
362
363 #[doc = "GTWP Key Code"]
364 #[inline(always)]
365 pub fn prkey(
366 self,
367 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Gtwp_SPEC, crate::common::W> {
368 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Gtwp_SPEC,crate::common::W>::from_register(self,0)
369 }
370}
371impl ::core::default::Default for Gtwp {
372 #[inline(always)]
373 fn default() -> Gtwp {
374 <crate::RegValueT<Gtwp_SPEC> as RegisterValue<_>>::new(0)
375 }
376}
377pub mod gtwp {
378
379 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
380 pub struct Wp_SPEC;
381 pub type Wp = crate::EnumBitfieldStruct<u8, Wp_SPEC>;
382 impl Wp {
383 #[doc = "Write to the register enabled"]
384 pub const _0: Self = Self::new(0);
385
386 #[doc = "Write to the register disabled"]
387 pub const _1: Self = Self::new(1);
388 }
389}
390#[doc(hidden)]
391#[derive(Copy, Clone, Eq, PartialEq)]
392pub struct Gtstr_SPEC;
393impl crate::sealed::RegSpec for Gtstr_SPEC {
394 type DataType = u32;
395}
396
397#[doc = "General PWM Timer Software Start Register"]
398pub type Gtstr = crate::RegValueT<Gtstr_SPEC>;
399
400impl Gtstr {
401 #[doc = "Channel 0 GTCNT Count Start"]
402 #[inline(always)]
403 pub fn cstrt0(
404 self,
405 ) -> crate::common::RegisterField<
406 0,
407 0x1,
408 1,
409 0,
410 gtstr::Cstrt0,
411 gtstr::Cstrt0,
412 Gtstr_SPEC,
413 crate::common::RW,
414 > {
415 crate::common::RegisterField::<
416 0,
417 0x1,
418 1,
419 0,
420 gtstr::Cstrt0,
421 gtstr::Cstrt0,
422 Gtstr_SPEC,
423 crate::common::RW,
424 >::from_register(self, 0)
425 }
426
427 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
428 #[inline(always)]
429 pub fn cstrt4(
430 self,
431 ) -> crate::common::RegisterField<
432 4,
433 0x1,
434 1,
435 0,
436 gtstr::Cstrt4,
437 gtstr::Cstrt4,
438 Gtstr_SPEC,
439 crate::common::RW,
440 > {
441 crate::common::RegisterField::<
442 4,
443 0x1,
444 1,
445 0,
446 gtstr::Cstrt4,
447 gtstr::Cstrt4,
448 Gtstr_SPEC,
449 crate::common::RW,
450 >::from_register(self, 0)
451 }
452
453 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
454 #[inline(always)]
455 pub fn cstrt5(
456 self,
457 ) -> crate::common::RegisterField<
458 5,
459 0x1,
460 1,
461 0,
462 gtstr::Cstrt5,
463 gtstr::Cstrt5,
464 Gtstr_SPEC,
465 crate::common::RW,
466 > {
467 crate::common::RegisterField::<
468 5,
469 0x1,
470 1,
471 0,
472 gtstr::Cstrt5,
473 gtstr::Cstrt5,
474 Gtstr_SPEC,
475 crate::common::RW,
476 >::from_register(self, 0)
477 }
478
479 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
480 #[inline(always)]
481 pub fn cstrt6(
482 self,
483 ) -> crate::common::RegisterField<
484 6,
485 0x1,
486 1,
487 0,
488 gtstr::Cstrt6,
489 gtstr::Cstrt6,
490 Gtstr_SPEC,
491 crate::common::RW,
492 > {
493 crate::common::RegisterField::<
494 6,
495 0x1,
496 1,
497 0,
498 gtstr::Cstrt6,
499 gtstr::Cstrt6,
500 Gtstr_SPEC,
501 crate::common::RW,
502 >::from_register(self, 0)
503 }
504
505 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
506 #[inline(always)]
507 pub fn cstrt7(
508 self,
509 ) -> crate::common::RegisterField<
510 7,
511 0x1,
512 1,
513 0,
514 gtstr::Cstrt7,
515 gtstr::Cstrt7,
516 Gtstr_SPEC,
517 crate::common::RW,
518 > {
519 crate::common::RegisterField::<
520 7,
521 0x1,
522 1,
523 0,
524 gtstr::Cstrt7,
525 gtstr::Cstrt7,
526 Gtstr_SPEC,
527 crate::common::RW,
528 >::from_register(self, 0)
529 }
530
531 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
532 #[inline(always)]
533 pub fn cstrt8(
534 self,
535 ) -> crate::common::RegisterField<
536 8,
537 0x1,
538 1,
539 0,
540 gtstr::Cstrt8,
541 gtstr::Cstrt8,
542 Gtstr_SPEC,
543 crate::common::RW,
544 > {
545 crate::common::RegisterField::<
546 8,
547 0x1,
548 1,
549 0,
550 gtstr::Cstrt8,
551 gtstr::Cstrt8,
552 Gtstr_SPEC,
553 crate::common::RW,
554 >::from_register(self, 0)
555 }
556
557 #[doc = "Channel n GTCNT Count Start (n is the same as the bit position value)"]
558 #[inline(always)]
559 pub fn cstrt9(
560 self,
561 ) -> crate::common::RegisterField<
562 9,
563 0x1,
564 1,
565 0,
566 gtstr::Cstrt9,
567 gtstr::Cstrt9,
568 Gtstr_SPEC,
569 crate::common::RW,
570 > {
571 crate::common::RegisterField::<
572 9,
573 0x1,
574 1,
575 0,
576 gtstr::Cstrt9,
577 gtstr::Cstrt9,
578 Gtstr_SPEC,
579 crate::common::RW,
580 >::from_register(self, 0)
581 }
582}
583impl ::core::default::Default for Gtstr {
584 #[inline(always)]
585 fn default() -> Gtstr {
586 <crate::RegValueT<Gtstr_SPEC> as RegisterValue<_>>::new(0)
587 }
588}
589pub mod gtstr {
590
591 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
592 pub struct Cstrt0_SPEC;
593 pub type Cstrt0 = crate::EnumBitfieldStruct<u8, Cstrt0_SPEC>;
594 impl Cstrt0 {
595 #[doc = "GTCNT counter is not started"]
596 pub const _0: Self = Self::new(0);
597
598 #[doc = "GTCNT counter is started"]
599 pub const _1: Self = Self::new(1);
600 }
601 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
602 pub struct Cstrt4_SPEC;
603 pub type Cstrt4 = crate::EnumBitfieldStruct<u8, Cstrt4_SPEC>;
604 impl Cstrt4 {
605 #[doc = "GTCNT counter is not started"]
606 pub const _0: Self = Self::new(0);
607
608 #[doc = "GTCNT counter is started"]
609 pub const _1: Self = Self::new(1);
610 }
611 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
612 pub struct Cstrt5_SPEC;
613 pub type Cstrt5 = crate::EnumBitfieldStruct<u8, Cstrt5_SPEC>;
614 impl Cstrt5 {
615 #[doc = "GTCNT counter is not started"]
616 pub const _0: Self = Self::new(0);
617
618 #[doc = "GTCNT counter is started"]
619 pub const _1: Self = Self::new(1);
620 }
621 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
622 pub struct Cstrt6_SPEC;
623 pub type Cstrt6 = crate::EnumBitfieldStruct<u8, Cstrt6_SPEC>;
624 impl Cstrt6 {
625 #[doc = "GTCNT counter is not started"]
626 pub const _0: Self = Self::new(0);
627
628 #[doc = "GTCNT counter is started"]
629 pub const _1: Self = Self::new(1);
630 }
631 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
632 pub struct Cstrt7_SPEC;
633 pub type Cstrt7 = crate::EnumBitfieldStruct<u8, Cstrt7_SPEC>;
634 impl Cstrt7 {
635 #[doc = "GTCNT counter is not started"]
636 pub const _0: Self = Self::new(0);
637
638 #[doc = "GTCNT counter is started"]
639 pub const _1: Self = Self::new(1);
640 }
641 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
642 pub struct Cstrt8_SPEC;
643 pub type Cstrt8 = crate::EnumBitfieldStruct<u8, Cstrt8_SPEC>;
644 impl Cstrt8 {
645 #[doc = "GTCNT counter is not started"]
646 pub const _0: Self = Self::new(0);
647
648 #[doc = "GTCNT counter is started"]
649 pub const _1: Self = Self::new(1);
650 }
651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
652 pub struct Cstrt9_SPEC;
653 pub type Cstrt9 = crate::EnumBitfieldStruct<u8, Cstrt9_SPEC>;
654 impl Cstrt9 {
655 #[doc = "GTCNT counter is not started"]
656 pub const _0: Self = Self::new(0);
657
658 #[doc = "GTCNT counter is started"]
659 pub const _1: Self = Self::new(1);
660 }
661}
662#[doc(hidden)]
663#[derive(Copy, Clone, Eq, PartialEq)]
664pub struct Gtstp_SPEC;
665impl crate::sealed::RegSpec for Gtstp_SPEC {
666 type DataType = u32;
667}
668
669#[doc = "General PWM Timer Software Stop Register"]
670pub type Gtstp = crate::RegValueT<Gtstp_SPEC>;
671
672impl Gtstp {
673 #[doc = "Channel 0 GTCNT Count Stop"]
674 #[inline(always)]
675 pub fn cstop0(
676 self,
677 ) -> crate::common::RegisterField<
678 0,
679 0x1,
680 1,
681 0,
682 gtstp::Cstop0,
683 gtstp::Cstop0,
684 Gtstp_SPEC,
685 crate::common::RW,
686 > {
687 crate::common::RegisterField::<
688 0,
689 0x1,
690 1,
691 0,
692 gtstp::Cstop0,
693 gtstp::Cstop0,
694 Gtstp_SPEC,
695 crate::common::RW,
696 >::from_register(self, 0)
697 }
698
699 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
700 #[inline(always)]
701 pub fn cstop4(
702 self,
703 ) -> crate::common::RegisterField<
704 4,
705 0x1,
706 1,
707 0,
708 gtstp::Cstop4,
709 gtstp::Cstop4,
710 Gtstp_SPEC,
711 crate::common::RW,
712 > {
713 crate::common::RegisterField::<
714 4,
715 0x1,
716 1,
717 0,
718 gtstp::Cstop4,
719 gtstp::Cstop4,
720 Gtstp_SPEC,
721 crate::common::RW,
722 >::from_register(self, 0)
723 }
724
725 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
726 #[inline(always)]
727 pub fn cstop5(
728 self,
729 ) -> crate::common::RegisterField<
730 5,
731 0x1,
732 1,
733 0,
734 gtstp::Cstop5,
735 gtstp::Cstop5,
736 Gtstp_SPEC,
737 crate::common::RW,
738 > {
739 crate::common::RegisterField::<
740 5,
741 0x1,
742 1,
743 0,
744 gtstp::Cstop5,
745 gtstp::Cstop5,
746 Gtstp_SPEC,
747 crate::common::RW,
748 >::from_register(self, 0)
749 }
750
751 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
752 #[inline(always)]
753 pub fn cstop6(
754 self,
755 ) -> crate::common::RegisterField<
756 6,
757 0x1,
758 1,
759 0,
760 gtstp::Cstop6,
761 gtstp::Cstop6,
762 Gtstp_SPEC,
763 crate::common::RW,
764 > {
765 crate::common::RegisterField::<
766 6,
767 0x1,
768 1,
769 0,
770 gtstp::Cstop6,
771 gtstp::Cstop6,
772 Gtstp_SPEC,
773 crate::common::RW,
774 >::from_register(self, 0)
775 }
776
777 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
778 #[inline(always)]
779 pub fn cstop7(
780 self,
781 ) -> crate::common::RegisterField<
782 7,
783 0x1,
784 1,
785 0,
786 gtstp::Cstop7,
787 gtstp::Cstop7,
788 Gtstp_SPEC,
789 crate::common::RW,
790 > {
791 crate::common::RegisterField::<
792 7,
793 0x1,
794 1,
795 0,
796 gtstp::Cstop7,
797 gtstp::Cstop7,
798 Gtstp_SPEC,
799 crate::common::RW,
800 >::from_register(self, 0)
801 }
802
803 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
804 #[inline(always)]
805 pub fn cstop8(
806 self,
807 ) -> crate::common::RegisterField<
808 8,
809 0x1,
810 1,
811 0,
812 gtstp::Cstop8,
813 gtstp::Cstop8,
814 Gtstp_SPEC,
815 crate::common::RW,
816 > {
817 crate::common::RegisterField::<
818 8,
819 0x1,
820 1,
821 0,
822 gtstp::Cstop8,
823 gtstp::Cstop8,
824 Gtstp_SPEC,
825 crate::common::RW,
826 >::from_register(self, 0)
827 }
828
829 #[doc = "Channel n GTCNT Count Stop (n is the same as the bit position value)"]
830 #[inline(always)]
831 pub fn cstop9(
832 self,
833 ) -> crate::common::RegisterField<
834 9,
835 0x1,
836 1,
837 0,
838 gtstp::Cstop9,
839 gtstp::Cstop9,
840 Gtstp_SPEC,
841 crate::common::RW,
842 > {
843 crate::common::RegisterField::<
844 9,
845 0x1,
846 1,
847 0,
848 gtstp::Cstop9,
849 gtstp::Cstop9,
850 Gtstp_SPEC,
851 crate::common::RW,
852 >::from_register(self, 0)
853 }
854}
855impl ::core::default::Default for Gtstp {
856 #[inline(always)]
857 fn default() -> Gtstp {
858 <crate::RegValueT<Gtstp_SPEC> as RegisterValue<_>>::new(4294967295)
859 }
860}
861pub mod gtstp {
862
863 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
864 pub struct Cstop0_SPEC;
865 pub type Cstop0 = crate::EnumBitfieldStruct<u8, Cstop0_SPEC>;
866 impl Cstop0 {
867 #[doc = "GTCNT counter is not stopped"]
868 pub const _0: Self = Self::new(0);
869
870 #[doc = "GTCNT counter is stopped"]
871 pub const _1: Self = Self::new(1);
872 }
873 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
874 pub struct Cstop4_SPEC;
875 pub type Cstop4 = crate::EnumBitfieldStruct<u8, Cstop4_SPEC>;
876 impl Cstop4 {
877 #[doc = "GTCNT counter is not stopped"]
878 pub const _0: Self = Self::new(0);
879
880 #[doc = "GTCNT counter is stopped"]
881 pub const _1: Self = Self::new(1);
882 }
883 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
884 pub struct Cstop5_SPEC;
885 pub type Cstop5 = crate::EnumBitfieldStruct<u8, Cstop5_SPEC>;
886 impl Cstop5 {
887 #[doc = "GTCNT counter is not stopped"]
888 pub const _0: Self = Self::new(0);
889
890 #[doc = "GTCNT counter is stopped"]
891 pub const _1: Self = Self::new(1);
892 }
893 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
894 pub struct Cstop6_SPEC;
895 pub type Cstop6 = crate::EnumBitfieldStruct<u8, Cstop6_SPEC>;
896 impl Cstop6 {
897 #[doc = "GTCNT counter is not stopped"]
898 pub const _0: Self = Self::new(0);
899
900 #[doc = "GTCNT counter is stopped"]
901 pub const _1: Self = Self::new(1);
902 }
903 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
904 pub struct Cstop7_SPEC;
905 pub type Cstop7 = crate::EnumBitfieldStruct<u8, Cstop7_SPEC>;
906 impl Cstop7 {
907 #[doc = "GTCNT counter is not stopped"]
908 pub const _0: Self = Self::new(0);
909
910 #[doc = "GTCNT counter is stopped"]
911 pub const _1: Self = Self::new(1);
912 }
913 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
914 pub struct Cstop8_SPEC;
915 pub type Cstop8 = crate::EnumBitfieldStruct<u8, Cstop8_SPEC>;
916 impl Cstop8 {
917 #[doc = "GTCNT counter is not stopped"]
918 pub const _0: Self = Self::new(0);
919
920 #[doc = "GTCNT counter is stopped"]
921 pub const _1: Self = Self::new(1);
922 }
923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
924 pub struct Cstop9_SPEC;
925 pub type Cstop9 = crate::EnumBitfieldStruct<u8, Cstop9_SPEC>;
926 impl Cstop9 {
927 #[doc = "GTCNT counter is not stopped"]
928 pub const _0: Self = Self::new(0);
929
930 #[doc = "GTCNT counter is stopped"]
931 pub const _1: Self = Self::new(1);
932 }
933}
934#[doc(hidden)]
935#[derive(Copy, Clone, Eq, PartialEq)]
936pub struct Gtclr_SPEC;
937impl crate::sealed::RegSpec for Gtclr_SPEC {
938 type DataType = u32;
939}
940
941#[doc = "General PWM Timer Software Clear Register"]
942pub type Gtclr = crate::RegValueT<Gtclr_SPEC>;
943
944impl Gtclr {
945 #[doc = "Channel 0 GTCNT Count Clear"]
946 #[inline(always)]
947 pub fn cclr0(
948 self,
949 ) -> crate::common::RegisterField<
950 0,
951 0x1,
952 1,
953 0,
954 gtclr::Cclr0,
955 gtclr::Cclr0,
956 Gtclr_SPEC,
957 crate::common::W,
958 > {
959 crate::common::RegisterField::<
960 0,
961 0x1,
962 1,
963 0,
964 gtclr::Cclr0,
965 gtclr::Cclr0,
966 Gtclr_SPEC,
967 crate::common::W,
968 >::from_register(self, 0)
969 }
970
971 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
972 #[inline(always)]
973 pub fn cclr4(
974 self,
975 ) -> crate::common::RegisterField<
976 4,
977 0x1,
978 1,
979 0,
980 gtclr::Cclr4,
981 gtclr::Cclr4,
982 Gtclr_SPEC,
983 crate::common::W,
984 > {
985 crate::common::RegisterField::<
986 4,
987 0x1,
988 1,
989 0,
990 gtclr::Cclr4,
991 gtclr::Cclr4,
992 Gtclr_SPEC,
993 crate::common::W,
994 >::from_register(self, 0)
995 }
996
997 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
998 #[inline(always)]
999 pub fn cclr5(
1000 self,
1001 ) -> crate::common::RegisterField<
1002 5,
1003 0x1,
1004 1,
1005 0,
1006 gtclr::Cclr5,
1007 gtclr::Cclr5,
1008 Gtclr_SPEC,
1009 crate::common::W,
1010 > {
1011 crate::common::RegisterField::<
1012 5,
1013 0x1,
1014 1,
1015 0,
1016 gtclr::Cclr5,
1017 gtclr::Cclr5,
1018 Gtclr_SPEC,
1019 crate::common::W,
1020 >::from_register(self, 0)
1021 }
1022
1023 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
1024 #[inline(always)]
1025 pub fn cclr6(
1026 self,
1027 ) -> crate::common::RegisterField<
1028 6,
1029 0x1,
1030 1,
1031 0,
1032 gtclr::Cclr6,
1033 gtclr::Cclr6,
1034 Gtclr_SPEC,
1035 crate::common::W,
1036 > {
1037 crate::common::RegisterField::<
1038 6,
1039 0x1,
1040 1,
1041 0,
1042 gtclr::Cclr6,
1043 gtclr::Cclr6,
1044 Gtclr_SPEC,
1045 crate::common::W,
1046 >::from_register(self, 0)
1047 }
1048
1049 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
1050 #[inline(always)]
1051 pub fn cclr7(
1052 self,
1053 ) -> crate::common::RegisterField<
1054 7,
1055 0x1,
1056 1,
1057 0,
1058 gtclr::Cclr7,
1059 gtclr::Cclr7,
1060 Gtclr_SPEC,
1061 crate::common::W,
1062 > {
1063 crate::common::RegisterField::<
1064 7,
1065 0x1,
1066 1,
1067 0,
1068 gtclr::Cclr7,
1069 gtclr::Cclr7,
1070 Gtclr_SPEC,
1071 crate::common::W,
1072 >::from_register(self, 0)
1073 }
1074
1075 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
1076 #[inline(always)]
1077 pub fn cclr8(
1078 self,
1079 ) -> crate::common::RegisterField<
1080 8,
1081 0x1,
1082 1,
1083 0,
1084 gtclr::Cclr8,
1085 gtclr::Cclr8,
1086 Gtclr_SPEC,
1087 crate::common::W,
1088 > {
1089 crate::common::RegisterField::<
1090 8,
1091 0x1,
1092 1,
1093 0,
1094 gtclr::Cclr8,
1095 gtclr::Cclr8,
1096 Gtclr_SPEC,
1097 crate::common::W,
1098 >::from_register(self, 0)
1099 }
1100
1101 #[doc = "Channel n GTCNT Count Clear (n is the same as the bit position value)"]
1102 #[inline(always)]
1103 pub fn cclr9(
1104 self,
1105 ) -> crate::common::RegisterField<
1106 9,
1107 0x1,
1108 1,
1109 0,
1110 gtclr::Cclr9,
1111 gtclr::Cclr9,
1112 Gtclr_SPEC,
1113 crate::common::W,
1114 > {
1115 crate::common::RegisterField::<
1116 9,
1117 0x1,
1118 1,
1119 0,
1120 gtclr::Cclr9,
1121 gtclr::Cclr9,
1122 Gtclr_SPEC,
1123 crate::common::W,
1124 >::from_register(self, 0)
1125 }
1126}
1127impl ::core::default::Default for Gtclr {
1128 #[inline(always)]
1129 fn default() -> Gtclr {
1130 <crate::RegValueT<Gtclr_SPEC> as RegisterValue<_>>::new(0)
1131 }
1132}
1133pub mod gtclr {
1134
1135 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1136 pub struct Cclr0_SPEC;
1137 pub type Cclr0 = crate::EnumBitfieldStruct<u8, Cclr0_SPEC>;
1138 impl Cclr0 {
1139 #[doc = "GTCNT counter is not cleared"]
1140 pub const _0: Self = Self::new(0);
1141
1142 #[doc = "GTCNT counter is cleared"]
1143 pub const _1: Self = Self::new(1);
1144 }
1145 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1146 pub struct Cclr4_SPEC;
1147 pub type Cclr4 = crate::EnumBitfieldStruct<u8, Cclr4_SPEC>;
1148 impl Cclr4 {
1149 #[doc = "GTCNT counter is not cleared"]
1150 pub const _0: Self = Self::new(0);
1151
1152 #[doc = "GTCNT counter is cleared"]
1153 pub const _1: Self = Self::new(1);
1154 }
1155 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1156 pub struct Cclr5_SPEC;
1157 pub type Cclr5 = crate::EnumBitfieldStruct<u8, Cclr5_SPEC>;
1158 impl Cclr5 {
1159 #[doc = "GTCNT counter is not cleared"]
1160 pub const _0: Self = Self::new(0);
1161
1162 #[doc = "GTCNT counter is cleared"]
1163 pub const _1: Self = Self::new(1);
1164 }
1165 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1166 pub struct Cclr6_SPEC;
1167 pub type Cclr6 = crate::EnumBitfieldStruct<u8, Cclr6_SPEC>;
1168 impl Cclr6 {
1169 #[doc = "GTCNT counter is not cleared"]
1170 pub const _0: Self = Self::new(0);
1171
1172 #[doc = "GTCNT counter is cleared"]
1173 pub const _1: Self = Self::new(1);
1174 }
1175 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1176 pub struct Cclr7_SPEC;
1177 pub type Cclr7 = crate::EnumBitfieldStruct<u8, Cclr7_SPEC>;
1178 impl Cclr7 {
1179 #[doc = "GTCNT counter is not cleared"]
1180 pub const _0: Self = Self::new(0);
1181
1182 #[doc = "GTCNT counter is cleared"]
1183 pub const _1: Self = Self::new(1);
1184 }
1185 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1186 pub struct Cclr8_SPEC;
1187 pub type Cclr8 = crate::EnumBitfieldStruct<u8, Cclr8_SPEC>;
1188 impl Cclr8 {
1189 #[doc = "GTCNT counter is not cleared"]
1190 pub const _0: Self = Self::new(0);
1191
1192 #[doc = "GTCNT counter is cleared"]
1193 pub const _1: Self = Self::new(1);
1194 }
1195 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1196 pub struct Cclr9_SPEC;
1197 pub type Cclr9 = crate::EnumBitfieldStruct<u8, Cclr9_SPEC>;
1198 impl Cclr9 {
1199 #[doc = "GTCNT counter is not cleared"]
1200 pub const _0: Self = Self::new(0);
1201
1202 #[doc = "GTCNT counter is cleared"]
1203 pub const _1: Self = Self::new(1);
1204 }
1205}
1206#[doc(hidden)]
1207#[derive(Copy, Clone, Eq, PartialEq)]
1208pub struct Gtssr_SPEC;
1209impl crate::sealed::RegSpec for Gtssr_SPEC {
1210 type DataType = u32;
1211}
1212
1213#[doc = "General PWM Timer Start Source Select Register"]
1214pub type Gtssr = crate::RegValueT<Gtssr_SPEC>;
1215
1216impl Gtssr {
1217 #[doc = "GTETRGA Pin Rising Input Source Counter Start Enable"]
1218 #[inline(always)]
1219 pub fn ssgtrgar(
1220 self,
1221 ) -> crate::common::RegisterField<
1222 0,
1223 0x1,
1224 1,
1225 0,
1226 gtssr::Ssgtrgar,
1227 gtssr::Ssgtrgar,
1228 Gtssr_SPEC,
1229 crate::common::RW,
1230 > {
1231 crate::common::RegisterField::<
1232 0,
1233 0x1,
1234 1,
1235 0,
1236 gtssr::Ssgtrgar,
1237 gtssr::Ssgtrgar,
1238 Gtssr_SPEC,
1239 crate::common::RW,
1240 >::from_register(self, 0)
1241 }
1242
1243 #[doc = "GTETRGA Pin Falling Input Source Counter Start Enable"]
1244 #[inline(always)]
1245 pub fn ssgtrgaf(
1246 self,
1247 ) -> crate::common::RegisterField<
1248 1,
1249 0x1,
1250 1,
1251 0,
1252 gtssr::Ssgtrgaf,
1253 gtssr::Ssgtrgaf,
1254 Gtssr_SPEC,
1255 crate::common::RW,
1256 > {
1257 crate::common::RegisterField::<
1258 1,
1259 0x1,
1260 1,
1261 0,
1262 gtssr::Ssgtrgaf,
1263 gtssr::Ssgtrgaf,
1264 Gtssr_SPEC,
1265 crate::common::RW,
1266 >::from_register(self, 0)
1267 }
1268
1269 #[doc = "GTETRGB Pin Rising Input Source Counter Start Enable"]
1270 #[inline(always)]
1271 pub fn ssgtrgbr(
1272 self,
1273 ) -> crate::common::RegisterField<
1274 2,
1275 0x1,
1276 1,
1277 0,
1278 gtssr::Ssgtrgbr,
1279 gtssr::Ssgtrgbr,
1280 Gtssr_SPEC,
1281 crate::common::RW,
1282 > {
1283 crate::common::RegisterField::<
1284 2,
1285 0x1,
1286 1,
1287 0,
1288 gtssr::Ssgtrgbr,
1289 gtssr::Ssgtrgbr,
1290 Gtssr_SPEC,
1291 crate::common::RW,
1292 >::from_register(self, 0)
1293 }
1294
1295 #[doc = "GTETRGB Pin Falling Input Source Counter Start Enable"]
1296 #[inline(always)]
1297 pub fn ssgtrgbf(
1298 self,
1299 ) -> crate::common::RegisterField<
1300 3,
1301 0x1,
1302 1,
1303 0,
1304 gtssr::Ssgtrgbf,
1305 gtssr::Ssgtrgbf,
1306 Gtssr_SPEC,
1307 crate::common::RW,
1308 > {
1309 crate::common::RegisterField::<
1310 3,
1311 0x1,
1312 1,
1313 0,
1314 gtssr::Ssgtrgbf,
1315 gtssr::Ssgtrgbf,
1316 Gtssr_SPEC,
1317 crate::common::RW,
1318 >::from_register(self, 0)
1319 }
1320
1321 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Start Enable"]
1322 #[inline(always)]
1323 pub fn sscarbl(
1324 self,
1325 ) -> crate::common::RegisterField<
1326 8,
1327 0x1,
1328 1,
1329 0,
1330 gtssr::Sscarbl,
1331 gtssr::Sscarbl,
1332 Gtssr_SPEC,
1333 crate::common::RW,
1334 > {
1335 crate::common::RegisterField::<
1336 8,
1337 0x1,
1338 1,
1339 0,
1340 gtssr::Sscarbl,
1341 gtssr::Sscarbl,
1342 Gtssr_SPEC,
1343 crate::common::RW,
1344 >::from_register(self, 0)
1345 }
1346
1347 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Start Enable"]
1348 #[inline(always)]
1349 pub fn sscarbh(
1350 self,
1351 ) -> crate::common::RegisterField<
1352 9,
1353 0x1,
1354 1,
1355 0,
1356 gtssr::Sscarbh,
1357 gtssr::Sscarbh,
1358 Gtssr_SPEC,
1359 crate::common::RW,
1360 > {
1361 crate::common::RegisterField::<
1362 9,
1363 0x1,
1364 1,
1365 0,
1366 gtssr::Sscarbh,
1367 gtssr::Sscarbh,
1368 Gtssr_SPEC,
1369 crate::common::RW,
1370 >::from_register(self, 0)
1371 }
1372
1373 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Start Enable"]
1374 #[inline(always)]
1375 pub fn sscafbl(
1376 self,
1377 ) -> crate::common::RegisterField<
1378 10,
1379 0x1,
1380 1,
1381 0,
1382 gtssr::Sscafbl,
1383 gtssr::Sscafbl,
1384 Gtssr_SPEC,
1385 crate::common::RW,
1386 > {
1387 crate::common::RegisterField::<
1388 10,
1389 0x1,
1390 1,
1391 0,
1392 gtssr::Sscafbl,
1393 gtssr::Sscafbl,
1394 Gtssr_SPEC,
1395 crate::common::RW,
1396 >::from_register(self, 0)
1397 }
1398
1399 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Start Enable"]
1400 #[inline(always)]
1401 pub fn sscafbh(
1402 self,
1403 ) -> crate::common::RegisterField<
1404 11,
1405 0x1,
1406 1,
1407 0,
1408 gtssr::Sscafbh,
1409 gtssr::Sscafbh,
1410 Gtssr_SPEC,
1411 crate::common::RW,
1412 > {
1413 crate::common::RegisterField::<
1414 11,
1415 0x1,
1416 1,
1417 0,
1418 gtssr::Sscafbh,
1419 gtssr::Sscafbh,
1420 Gtssr_SPEC,
1421 crate::common::RW,
1422 >::from_register(self, 0)
1423 }
1424
1425 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Start Enable"]
1426 #[inline(always)]
1427 pub fn sscbral(
1428 self,
1429 ) -> crate::common::RegisterField<
1430 12,
1431 0x1,
1432 1,
1433 0,
1434 gtssr::Sscbral,
1435 gtssr::Sscbral,
1436 Gtssr_SPEC,
1437 crate::common::RW,
1438 > {
1439 crate::common::RegisterField::<
1440 12,
1441 0x1,
1442 1,
1443 0,
1444 gtssr::Sscbral,
1445 gtssr::Sscbral,
1446 Gtssr_SPEC,
1447 crate::common::RW,
1448 >::from_register(self, 0)
1449 }
1450
1451 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Start Enable"]
1452 #[inline(always)]
1453 pub fn sscbrah(
1454 self,
1455 ) -> crate::common::RegisterField<
1456 13,
1457 0x1,
1458 1,
1459 0,
1460 gtssr::Sscbrah,
1461 gtssr::Sscbrah,
1462 Gtssr_SPEC,
1463 crate::common::RW,
1464 > {
1465 crate::common::RegisterField::<
1466 13,
1467 0x1,
1468 1,
1469 0,
1470 gtssr::Sscbrah,
1471 gtssr::Sscbrah,
1472 Gtssr_SPEC,
1473 crate::common::RW,
1474 >::from_register(self, 0)
1475 }
1476
1477 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Start Enable"]
1478 #[inline(always)]
1479 pub fn sscbfal(
1480 self,
1481 ) -> crate::common::RegisterField<
1482 14,
1483 0x1,
1484 1,
1485 0,
1486 gtssr::Sscbfal,
1487 gtssr::Sscbfal,
1488 Gtssr_SPEC,
1489 crate::common::RW,
1490 > {
1491 crate::common::RegisterField::<
1492 14,
1493 0x1,
1494 1,
1495 0,
1496 gtssr::Sscbfal,
1497 gtssr::Sscbfal,
1498 Gtssr_SPEC,
1499 crate::common::RW,
1500 >::from_register(self, 0)
1501 }
1502
1503 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Start Enable"]
1504 #[inline(always)]
1505 pub fn sscbfah(
1506 self,
1507 ) -> crate::common::RegisterField<
1508 15,
1509 0x1,
1510 1,
1511 0,
1512 gtssr::Sscbfah,
1513 gtssr::Sscbfah,
1514 Gtssr_SPEC,
1515 crate::common::RW,
1516 > {
1517 crate::common::RegisterField::<
1518 15,
1519 0x1,
1520 1,
1521 0,
1522 gtssr::Sscbfah,
1523 gtssr::Sscbfah,
1524 Gtssr_SPEC,
1525 crate::common::RW,
1526 >::from_register(self, 0)
1527 }
1528
1529 #[doc = "ELC_GPTA Event Source Counter Start Enable"]
1530 #[inline(always)]
1531 pub fn sselca(
1532 self,
1533 ) -> crate::common::RegisterField<
1534 16,
1535 0x1,
1536 1,
1537 0,
1538 gtssr::Sselca,
1539 gtssr::Sselca,
1540 Gtssr_SPEC,
1541 crate::common::RW,
1542 > {
1543 crate::common::RegisterField::<
1544 16,
1545 0x1,
1546 1,
1547 0,
1548 gtssr::Sselca,
1549 gtssr::Sselca,
1550 Gtssr_SPEC,
1551 crate::common::RW,
1552 >::from_register(self, 0)
1553 }
1554
1555 #[doc = "ELC_GPTB Event Source Counter Start Enable"]
1556 #[inline(always)]
1557 pub fn sselcb(
1558 self,
1559 ) -> crate::common::RegisterField<
1560 17,
1561 0x1,
1562 1,
1563 0,
1564 gtssr::Sselcb,
1565 gtssr::Sselcb,
1566 Gtssr_SPEC,
1567 crate::common::RW,
1568 > {
1569 crate::common::RegisterField::<
1570 17,
1571 0x1,
1572 1,
1573 0,
1574 gtssr::Sselcb,
1575 gtssr::Sselcb,
1576 Gtssr_SPEC,
1577 crate::common::RW,
1578 >::from_register(self, 0)
1579 }
1580
1581 #[doc = "ELC_GPTC Event Source Counter Start Enable"]
1582 #[inline(always)]
1583 pub fn sselcc(
1584 self,
1585 ) -> crate::common::RegisterField<
1586 18,
1587 0x1,
1588 1,
1589 0,
1590 gtssr::Sselcc,
1591 gtssr::Sselcc,
1592 Gtssr_SPEC,
1593 crate::common::RW,
1594 > {
1595 crate::common::RegisterField::<
1596 18,
1597 0x1,
1598 1,
1599 0,
1600 gtssr::Sselcc,
1601 gtssr::Sselcc,
1602 Gtssr_SPEC,
1603 crate::common::RW,
1604 >::from_register(self, 0)
1605 }
1606
1607 #[doc = "ELC_GPTD Event Source Counter Start Enable"]
1608 #[inline(always)]
1609 pub fn sselcd(
1610 self,
1611 ) -> crate::common::RegisterField<
1612 19,
1613 0x1,
1614 1,
1615 0,
1616 gtssr::Sselcd,
1617 gtssr::Sselcd,
1618 Gtssr_SPEC,
1619 crate::common::RW,
1620 > {
1621 crate::common::RegisterField::<
1622 19,
1623 0x1,
1624 1,
1625 0,
1626 gtssr::Sselcd,
1627 gtssr::Sselcd,
1628 Gtssr_SPEC,
1629 crate::common::RW,
1630 >::from_register(self, 0)
1631 }
1632
1633 #[doc = "Software Source Counter Start Enable"]
1634 #[inline(always)]
1635 pub fn cstrt(
1636 self,
1637 ) -> crate::common::RegisterField<
1638 31,
1639 0x1,
1640 1,
1641 0,
1642 gtssr::Cstrt,
1643 gtssr::Cstrt,
1644 Gtssr_SPEC,
1645 crate::common::RW,
1646 > {
1647 crate::common::RegisterField::<
1648 31,
1649 0x1,
1650 1,
1651 0,
1652 gtssr::Cstrt,
1653 gtssr::Cstrt,
1654 Gtssr_SPEC,
1655 crate::common::RW,
1656 >::from_register(self, 0)
1657 }
1658}
1659impl ::core::default::Default for Gtssr {
1660 #[inline(always)]
1661 fn default() -> Gtssr {
1662 <crate::RegValueT<Gtssr_SPEC> as RegisterValue<_>>::new(0)
1663 }
1664}
1665pub mod gtssr {
1666
1667 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1668 pub struct Ssgtrgar_SPEC;
1669 pub type Ssgtrgar = crate::EnumBitfieldStruct<u8, Ssgtrgar_SPEC>;
1670 impl Ssgtrgar {
1671 #[doc = "Counter start disabled on the rising edge of GTETRGA input"]
1672 pub const _0: Self = Self::new(0);
1673
1674 #[doc = "Counter start enabled on the rising edge of GTETRGA input"]
1675 pub const _1: Self = Self::new(1);
1676 }
1677 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1678 pub struct Ssgtrgaf_SPEC;
1679 pub type Ssgtrgaf = crate::EnumBitfieldStruct<u8, Ssgtrgaf_SPEC>;
1680 impl Ssgtrgaf {
1681 #[doc = "Counter start disabled on the falling edge of GTETRGA input"]
1682 pub const _0: Self = Self::new(0);
1683
1684 #[doc = "Counter start enabled on the falling edge of GTETRGA input"]
1685 pub const _1: Self = Self::new(1);
1686 }
1687 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1688 pub struct Ssgtrgbr_SPEC;
1689 pub type Ssgtrgbr = crate::EnumBitfieldStruct<u8, Ssgtrgbr_SPEC>;
1690 impl Ssgtrgbr {
1691 #[doc = "Counter start disabled on the rising edge of GTETRGB input"]
1692 pub const _0: Self = Self::new(0);
1693
1694 #[doc = "Counter start enabled on the rising edge of GTETRGB input"]
1695 pub const _1: Self = Self::new(1);
1696 }
1697 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1698 pub struct Ssgtrgbf_SPEC;
1699 pub type Ssgtrgbf = crate::EnumBitfieldStruct<u8, Ssgtrgbf_SPEC>;
1700 impl Ssgtrgbf {
1701 #[doc = "Counter start disabled on the falling edge of GTETRGB input"]
1702 pub const _0: Self = Self::new(0);
1703
1704 #[doc = "Counter start enabled on the falling edge of GTETRGB input"]
1705 pub const _1: Self = Self::new(1);
1706 }
1707 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1708 pub struct Sscarbl_SPEC;
1709 pub type Sscarbl = crate::EnumBitfieldStruct<u8, Sscarbl_SPEC>;
1710 impl Sscarbl {
1711 #[doc = "Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
1712 pub const _0: Self = Self::new(0);
1713
1714 #[doc = "Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
1715 pub const _1: Self = Self::new(1);
1716 }
1717 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1718 pub struct Sscarbh_SPEC;
1719 pub type Sscarbh = crate::EnumBitfieldStruct<u8, Sscarbh_SPEC>;
1720 impl Sscarbh {
1721 #[doc = "Counter start disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
1722 pub const _0: Self = Self::new(0);
1723
1724 #[doc = "Counter start enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
1725 pub const _1: Self = Self::new(1);
1726 }
1727 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1728 pub struct Sscafbl_SPEC;
1729 pub type Sscafbl = crate::EnumBitfieldStruct<u8, Sscafbl_SPEC>;
1730 impl Sscafbl {
1731 #[doc = "Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
1732 pub const _0: Self = Self::new(0);
1733
1734 #[doc = "Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
1735 pub const _1: Self = Self::new(1);
1736 }
1737 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1738 pub struct Sscafbh_SPEC;
1739 pub type Sscafbh = crate::EnumBitfieldStruct<u8, Sscafbh_SPEC>;
1740 impl Sscafbh {
1741 #[doc = "Counter start disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
1742 pub const _0: Self = Self::new(0);
1743
1744 #[doc = "Counter start enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
1745 pub const _1: Self = Self::new(1);
1746 }
1747 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1748 pub struct Sscbral_SPEC;
1749 pub type Sscbral = crate::EnumBitfieldStruct<u8, Sscbral_SPEC>;
1750 impl Sscbral {
1751 #[doc = "Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
1752 pub const _0: Self = Self::new(0);
1753
1754 #[doc = "Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
1755 pub const _1: Self = Self::new(1);
1756 }
1757 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1758 pub struct Sscbrah_SPEC;
1759 pub type Sscbrah = crate::EnumBitfieldStruct<u8, Sscbrah_SPEC>;
1760 impl Sscbrah {
1761 #[doc = "Counter start disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
1762 pub const _0: Self = Self::new(0);
1763
1764 #[doc = "Counter start enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
1765 pub const _1: Self = Self::new(1);
1766 }
1767 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1768 pub struct Sscbfal_SPEC;
1769 pub type Sscbfal = crate::EnumBitfieldStruct<u8, Sscbfal_SPEC>;
1770 impl Sscbfal {
1771 #[doc = "Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
1772 pub const _0: Self = Self::new(0);
1773
1774 #[doc = "Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
1775 pub const _1: Self = Self::new(1);
1776 }
1777 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1778 pub struct Sscbfah_SPEC;
1779 pub type Sscbfah = crate::EnumBitfieldStruct<u8, Sscbfah_SPEC>;
1780 impl Sscbfah {
1781 #[doc = "Counter start disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
1782 pub const _0: Self = Self::new(0);
1783
1784 #[doc = "Counter start enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
1785 pub const _1: Self = Self::new(1);
1786 }
1787 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1788 pub struct Sselca_SPEC;
1789 pub type Sselca = crate::EnumBitfieldStruct<u8, Sselca_SPEC>;
1790 impl Sselca {
1791 #[doc = "Counter start disabled at the ELC_GPTA input"]
1792 pub const _0: Self = Self::new(0);
1793
1794 #[doc = "Counter start enabled at the ELC_GPTA input"]
1795 pub const _1: Self = Self::new(1);
1796 }
1797 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1798 pub struct Sselcb_SPEC;
1799 pub type Sselcb = crate::EnumBitfieldStruct<u8, Sselcb_SPEC>;
1800 impl Sselcb {
1801 #[doc = "Counter start disabled at the ELC_GPTB input"]
1802 pub const _0: Self = Self::new(0);
1803
1804 #[doc = "Counter start enabled at the ELC_GPTB input"]
1805 pub const _1: Self = Self::new(1);
1806 }
1807 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1808 pub struct Sselcc_SPEC;
1809 pub type Sselcc = crate::EnumBitfieldStruct<u8, Sselcc_SPEC>;
1810 impl Sselcc {
1811 #[doc = "Counter start disabled at the ELC_GPTC input"]
1812 pub const _0: Self = Self::new(0);
1813
1814 #[doc = "Counter start enabled at the ELC_GPTC input"]
1815 pub const _1: Self = Self::new(1);
1816 }
1817 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1818 pub struct Sselcd_SPEC;
1819 pub type Sselcd = crate::EnumBitfieldStruct<u8, Sselcd_SPEC>;
1820 impl Sselcd {
1821 #[doc = "Counter start disabled at the ELC_GPTD input"]
1822 pub const _0: Self = Self::new(0);
1823
1824 #[doc = "Counter start enabled at the ELC_GPTD input"]
1825 pub const _1: Self = Self::new(1);
1826 }
1827 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1828 pub struct Cstrt_SPEC;
1829 pub type Cstrt = crate::EnumBitfieldStruct<u8, Cstrt_SPEC>;
1830 impl Cstrt {
1831 #[doc = "Counter start disabled by the GTSTR register"]
1832 pub const _0: Self = Self::new(0);
1833
1834 #[doc = "Counter start enabled by the GTSTR register"]
1835 pub const _1: Self = Self::new(1);
1836 }
1837}
1838#[doc(hidden)]
1839#[derive(Copy, Clone, Eq, PartialEq)]
1840pub struct Gtpsr_SPEC;
1841impl crate::sealed::RegSpec for Gtpsr_SPEC {
1842 type DataType = u32;
1843}
1844
1845#[doc = "General PWM Timer Stop Source Select Register"]
1846pub type Gtpsr = crate::RegValueT<Gtpsr_SPEC>;
1847
1848impl Gtpsr {
1849 #[doc = "GTETRGA Pin Rising Input Source Counter Stop Enable"]
1850 #[inline(always)]
1851 pub fn psgtrgar(
1852 self,
1853 ) -> crate::common::RegisterField<
1854 0,
1855 0x1,
1856 1,
1857 0,
1858 gtpsr::Psgtrgar,
1859 gtpsr::Psgtrgar,
1860 Gtpsr_SPEC,
1861 crate::common::RW,
1862 > {
1863 crate::common::RegisterField::<
1864 0,
1865 0x1,
1866 1,
1867 0,
1868 gtpsr::Psgtrgar,
1869 gtpsr::Psgtrgar,
1870 Gtpsr_SPEC,
1871 crate::common::RW,
1872 >::from_register(self, 0)
1873 }
1874
1875 #[doc = "GTETRGA Pin Falling Input Source Counter Stop Enable"]
1876 #[inline(always)]
1877 pub fn psgtrgaf(
1878 self,
1879 ) -> crate::common::RegisterField<
1880 1,
1881 0x1,
1882 1,
1883 0,
1884 gtpsr::Psgtrgaf,
1885 gtpsr::Psgtrgaf,
1886 Gtpsr_SPEC,
1887 crate::common::RW,
1888 > {
1889 crate::common::RegisterField::<
1890 1,
1891 0x1,
1892 1,
1893 0,
1894 gtpsr::Psgtrgaf,
1895 gtpsr::Psgtrgaf,
1896 Gtpsr_SPEC,
1897 crate::common::RW,
1898 >::from_register(self, 0)
1899 }
1900
1901 #[doc = "GTETRGB Pin Rising Input Source Counter Stop Enable"]
1902 #[inline(always)]
1903 pub fn psgtrgbr(
1904 self,
1905 ) -> crate::common::RegisterField<
1906 2,
1907 0x1,
1908 1,
1909 0,
1910 gtpsr::Psgtrgbr,
1911 gtpsr::Psgtrgbr,
1912 Gtpsr_SPEC,
1913 crate::common::RW,
1914 > {
1915 crate::common::RegisterField::<
1916 2,
1917 0x1,
1918 1,
1919 0,
1920 gtpsr::Psgtrgbr,
1921 gtpsr::Psgtrgbr,
1922 Gtpsr_SPEC,
1923 crate::common::RW,
1924 >::from_register(self, 0)
1925 }
1926
1927 #[doc = "GTETRGB Pin Falling Input Source Counter Stop Enable"]
1928 #[inline(always)]
1929 pub fn psgtrgbf(
1930 self,
1931 ) -> crate::common::RegisterField<
1932 3,
1933 0x1,
1934 1,
1935 0,
1936 gtpsr::Psgtrgbf,
1937 gtpsr::Psgtrgbf,
1938 Gtpsr_SPEC,
1939 crate::common::RW,
1940 > {
1941 crate::common::RegisterField::<
1942 3,
1943 0x1,
1944 1,
1945 0,
1946 gtpsr::Psgtrgbf,
1947 gtpsr::Psgtrgbf,
1948 Gtpsr_SPEC,
1949 crate::common::RW,
1950 >::from_register(self, 0)
1951 }
1952
1953 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Stop Enable"]
1954 #[inline(always)]
1955 pub fn pscarbl(
1956 self,
1957 ) -> crate::common::RegisterField<
1958 8,
1959 0x1,
1960 1,
1961 0,
1962 gtpsr::Pscarbl,
1963 gtpsr::Pscarbl,
1964 Gtpsr_SPEC,
1965 crate::common::RW,
1966 > {
1967 crate::common::RegisterField::<
1968 8,
1969 0x1,
1970 1,
1971 0,
1972 gtpsr::Pscarbl,
1973 gtpsr::Pscarbl,
1974 Gtpsr_SPEC,
1975 crate::common::RW,
1976 >::from_register(self, 0)
1977 }
1978
1979 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Stop Enable"]
1980 #[inline(always)]
1981 pub fn pscarbh(
1982 self,
1983 ) -> crate::common::RegisterField<
1984 9,
1985 0x1,
1986 1,
1987 0,
1988 gtpsr::Pscarbh,
1989 gtpsr::Pscarbh,
1990 Gtpsr_SPEC,
1991 crate::common::RW,
1992 > {
1993 crate::common::RegisterField::<
1994 9,
1995 0x1,
1996 1,
1997 0,
1998 gtpsr::Pscarbh,
1999 gtpsr::Pscarbh,
2000 Gtpsr_SPEC,
2001 crate::common::RW,
2002 >::from_register(self, 0)
2003 }
2004
2005 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Stop Enable"]
2006 #[inline(always)]
2007 pub fn pscafbl(
2008 self,
2009 ) -> crate::common::RegisterField<
2010 10,
2011 0x1,
2012 1,
2013 0,
2014 gtpsr::Pscafbl,
2015 gtpsr::Pscafbl,
2016 Gtpsr_SPEC,
2017 crate::common::RW,
2018 > {
2019 crate::common::RegisterField::<
2020 10,
2021 0x1,
2022 1,
2023 0,
2024 gtpsr::Pscafbl,
2025 gtpsr::Pscafbl,
2026 Gtpsr_SPEC,
2027 crate::common::RW,
2028 >::from_register(self, 0)
2029 }
2030
2031 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Stop Enable"]
2032 #[inline(always)]
2033 pub fn pscafbh(
2034 self,
2035 ) -> crate::common::RegisterField<
2036 11,
2037 0x1,
2038 1,
2039 0,
2040 gtpsr::Pscafbh,
2041 gtpsr::Pscafbh,
2042 Gtpsr_SPEC,
2043 crate::common::RW,
2044 > {
2045 crate::common::RegisterField::<
2046 11,
2047 0x1,
2048 1,
2049 0,
2050 gtpsr::Pscafbh,
2051 gtpsr::Pscafbh,
2052 Gtpsr_SPEC,
2053 crate::common::RW,
2054 >::from_register(self, 0)
2055 }
2056
2057 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Stop Enable"]
2058 #[inline(always)]
2059 pub fn pscbral(
2060 self,
2061 ) -> crate::common::RegisterField<
2062 12,
2063 0x1,
2064 1,
2065 0,
2066 gtpsr::Pscbral,
2067 gtpsr::Pscbral,
2068 Gtpsr_SPEC,
2069 crate::common::RW,
2070 > {
2071 crate::common::RegisterField::<
2072 12,
2073 0x1,
2074 1,
2075 0,
2076 gtpsr::Pscbral,
2077 gtpsr::Pscbral,
2078 Gtpsr_SPEC,
2079 crate::common::RW,
2080 >::from_register(self, 0)
2081 }
2082
2083 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Stop Enable"]
2084 #[inline(always)]
2085 pub fn pscbrah(
2086 self,
2087 ) -> crate::common::RegisterField<
2088 13,
2089 0x1,
2090 1,
2091 0,
2092 gtpsr::Pscbrah,
2093 gtpsr::Pscbrah,
2094 Gtpsr_SPEC,
2095 crate::common::RW,
2096 > {
2097 crate::common::RegisterField::<
2098 13,
2099 0x1,
2100 1,
2101 0,
2102 gtpsr::Pscbrah,
2103 gtpsr::Pscbrah,
2104 Gtpsr_SPEC,
2105 crate::common::RW,
2106 >::from_register(self, 0)
2107 }
2108
2109 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Stop Enable"]
2110 #[inline(always)]
2111 pub fn pscbfal(
2112 self,
2113 ) -> crate::common::RegisterField<
2114 14,
2115 0x1,
2116 1,
2117 0,
2118 gtpsr::Pscbfal,
2119 gtpsr::Pscbfal,
2120 Gtpsr_SPEC,
2121 crate::common::RW,
2122 > {
2123 crate::common::RegisterField::<
2124 14,
2125 0x1,
2126 1,
2127 0,
2128 gtpsr::Pscbfal,
2129 gtpsr::Pscbfal,
2130 Gtpsr_SPEC,
2131 crate::common::RW,
2132 >::from_register(self, 0)
2133 }
2134
2135 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Stop Enable"]
2136 #[inline(always)]
2137 pub fn pscbfah(
2138 self,
2139 ) -> crate::common::RegisterField<
2140 15,
2141 0x1,
2142 1,
2143 0,
2144 gtpsr::Pscbfah,
2145 gtpsr::Pscbfah,
2146 Gtpsr_SPEC,
2147 crate::common::RW,
2148 > {
2149 crate::common::RegisterField::<
2150 15,
2151 0x1,
2152 1,
2153 0,
2154 gtpsr::Pscbfah,
2155 gtpsr::Pscbfah,
2156 Gtpsr_SPEC,
2157 crate::common::RW,
2158 >::from_register(self, 0)
2159 }
2160
2161 #[doc = "ELC_GPTA Event Source Counter Stop Enable"]
2162 #[inline(always)]
2163 pub fn pselca(
2164 self,
2165 ) -> crate::common::RegisterField<
2166 16,
2167 0x1,
2168 1,
2169 0,
2170 gtpsr::Pselca,
2171 gtpsr::Pselca,
2172 Gtpsr_SPEC,
2173 crate::common::RW,
2174 > {
2175 crate::common::RegisterField::<
2176 16,
2177 0x1,
2178 1,
2179 0,
2180 gtpsr::Pselca,
2181 gtpsr::Pselca,
2182 Gtpsr_SPEC,
2183 crate::common::RW,
2184 >::from_register(self, 0)
2185 }
2186
2187 #[doc = "ELC_GPTB Event Source Counter Stop Enable"]
2188 #[inline(always)]
2189 pub fn pselcb(
2190 self,
2191 ) -> crate::common::RegisterField<
2192 17,
2193 0x1,
2194 1,
2195 0,
2196 gtpsr::Pselcb,
2197 gtpsr::Pselcb,
2198 Gtpsr_SPEC,
2199 crate::common::RW,
2200 > {
2201 crate::common::RegisterField::<
2202 17,
2203 0x1,
2204 1,
2205 0,
2206 gtpsr::Pselcb,
2207 gtpsr::Pselcb,
2208 Gtpsr_SPEC,
2209 crate::common::RW,
2210 >::from_register(self, 0)
2211 }
2212
2213 #[doc = "ELC_GPTC Event Source Counter Stop Enable"]
2214 #[inline(always)]
2215 pub fn pselcc(
2216 self,
2217 ) -> crate::common::RegisterField<
2218 18,
2219 0x1,
2220 1,
2221 0,
2222 gtpsr::Pselcc,
2223 gtpsr::Pselcc,
2224 Gtpsr_SPEC,
2225 crate::common::RW,
2226 > {
2227 crate::common::RegisterField::<
2228 18,
2229 0x1,
2230 1,
2231 0,
2232 gtpsr::Pselcc,
2233 gtpsr::Pselcc,
2234 Gtpsr_SPEC,
2235 crate::common::RW,
2236 >::from_register(self, 0)
2237 }
2238
2239 #[doc = "ELC_GPTD Event Source Counter Stop Enable"]
2240 #[inline(always)]
2241 pub fn pselcd(
2242 self,
2243 ) -> crate::common::RegisterField<
2244 19,
2245 0x1,
2246 1,
2247 0,
2248 gtpsr::Pselcd,
2249 gtpsr::Pselcd,
2250 Gtpsr_SPEC,
2251 crate::common::RW,
2252 > {
2253 crate::common::RegisterField::<
2254 19,
2255 0x1,
2256 1,
2257 0,
2258 gtpsr::Pselcd,
2259 gtpsr::Pselcd,
2260 Gtpsr_SPEC,
2261 crate::common::RW,
2262 >::from_register(self, 0)
2263 }
2264
2265 #[doc = "Software Source Counter Stop Enable"]
2266 #[inline(always)]
2267 pub fn cstop(
2268 self,
2269 ) -> crate::common::RegisterField<
2270 31,
2271 0x1,
2272 1,
2273 0,
2274 gtpsr::Cstop,
2275 gtpsr::Cstop,
2276 Gtpsr_SPEC,
2277 crate::common::RW,
2278 > {
2279 crate::common::RegisterField::<
2280 31,
2281 0x1,
2282 1,
2283 0,
2284 gtpsr::Cstop,
2285 gtpsr::Cstop,
2286 Gtpsr_SPEC,
2287 crate::common::RW,
2288 >::from_register(self, 0)
2289 }
2290}
2291impl ::core::default::Default for Gtpsr {
2292 #[inline(always)]
2293 fn default() -> Gtpsr {
2294 <crate::RegValueT<Gtpsr_SPEC> as RegisterValue<_>>::new(0)
2295 }
2296}
2297pub mod gtpsr {
2298
2299 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2300 pub struct Psgtrgar_SPEC;
2301 pub type Psgtrgar = crate::EnumBitfieldStruct<u8, Psgtrgar_SPEC>;
2302 impl Psgtrgar {
2303 #[doc = "Counter stop disabled on the rising edge of GTETRGA input"]
2304 pub const _0: Self = Self::new(0);
2305
2306 #[doc = "Counter stop enabled on the rising edge of GTETRGA input"]
2307 pub const _1: Self = Self::new(1);
2308 }
2309 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2310 pub struct Psgtrgaf_SPEC;
2311 pub type Psgtrgaf = crate::EnumBitfieldStruct<u8, Psgtrgaf_SPEC>;
2312 impl Psgtrgaf {
2313 #[doc = "Counter stop disabled on the falling edge of GTETRGA input"]
2314 pub const _0: Self = Self::new(0);
2315
2316 #[doc = "Counter stop enabled on the falling edge of GTETRGA input"]
2317 pub const _1: Self = Self::new(1);
2318 }
2319 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2320 pub struct Psgtrgbr_SPEC;
2321 pub type Psgtrgbr = crate::EnumBitfieldStruct<u8, Psgtrgbr_SPEC>;
2322 impl Psgtrgbr {
2323 #[doc = "Counter stop disabled on the rising edge of GTETRGB input"]
2324 pub const _0: Self = Self::new(0);
2325
2326 #[doc = "Counter stop enabled on the rising edge of GTETRGB input"]
2327 pub const _1: Self = Self::new(1);
2328 }
2329 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2330 pub struct Psgtrgbf_SPEC;
2331 pub type Psgtrgbf = crate::EnumBitfieldStruct<u8, Psgtrgbf_SPEC>;
2332 impl Psgtrgbf {
2333 #[doc = "Counter stop disabled on the falling edge of GTETRGB input"]
2334 pub const _0: Self = Self::new(0);
2335
2336 #[doc = "Counter stop enabled on the falling edge of GTETRGB input"]
2337 pub const _1: Self = Self::new(1);
2338 }
2339 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2340 pub struct Pscarbl_SPEC;
2341 pub type Pscarbl = crate::EnumBitfieldStruct<u8, Pscarbl_SPEC>;
2342 impl Pscarbl {
2343 #[doc = "Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2344 pub const _0: Self = Self::new(0);
2345
2346 #[doc = "Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2347 pub const _1: Self = Self::new(1);
2348 }
2349 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2350 pub struct Pscarbh_SPEC;
2351 pub type Pscarbh = crate::EnumBitfieldStruct<u8, Pscarbh_SPEC>;
2352 impl Pscarbh {
2353 #[doc = "Counter stop disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2354 pub const _0: Self = Self::new(0);
2355
2356 #[doc = "Counter stop enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2357 pub const _1: Self = Self::new(1);
2358 }
2359 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2360 pub struct Pscafbl_SPEC;
2361 pub type Pscafbl = crate::EnumBitfieldStruct<u8, Pscafbl_SPEC>;
2362 impl Pscafbl {
2363 #[doc = "Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2364 pub const _0: Self = Self::new(0);
2365
2366 #[doc = "Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2367 pub const _1: Self = Self::new(1);
2368 }
2369 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2370 pub struct Pscafbh_SPEC;
2371 pub type Pscafbh = crate::EnumBitfieldStruct<u8, Pscafbh_SPEC>;
2372 impl Pscafbh {
2373 #[doc = "Counter stop disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
2374 pub const _0: Self = Self::new(0);
2375
2376 #[doc = "Counter stop enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
2377 pub const _1: Self = Self::new(1);
2378 }
2379 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2380 pub struct Pscbral_SPEC;
2381 pub type Pscbral = crate::EnumBitfieldStruct<u8, Pscbral_SPEC>;
2382 impl Pscbral {
2383 #[doc = "Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
2384 pub const _0: Self = Self::new(0);
2385
2386 #[doc = "Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
2387 pub const _1: Self = Self::new(1);
2388 }
2389 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2390 pub struct Pscbrah_SPEC;
2391 pub type Pscbrah = crate::EnumBitfieldStruct<u8, Pscbrah_SPEC>;
2392 impl Pscbrah {
2393 #[doc = "Counter stop disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
2394 pub const _0: Self = Self::new(0);
2395
2396 #[doc = "Counter stop enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
2397 pub const _1: Self = Self::new(1);
2398 }
2399 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2400 pub struct Pscbfal_SPEC;
2401 pub type Pscbfal = crate::EnumBitfieldStruct<u8, Pscbfal_SPEC>;
2402 impl Pscbfal {
2403 #[doc = "Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
2404 pub const _0: Self = Self::new(0);
2405
2406 #[doc = "Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
2407 pub const _1: Self = Self::new(1);
2408 }
2409 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2410 pub struct Pscbfah_SPEC;
2411 pub type Pscbfah = crate::EnumBitfieldStruct<u8, Pscbfah_SPEC>;
2412 impl Pscbfah {
2413 #[doc = "Counter stop disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
2414 pub const _0: Self = Self::new(0);
2415
2416 #[doc = "Counter stop enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
2417 pub const _1: Self = Self::new(1);
2418 }
2419 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2420 pub struct Pselca_SPEC;
2421 pub type Pselca = crate::EnumBitfieldStruct<u8, Pselca_SPEC>;
2422 impl Pselca {
2423 #[doc = "Counter stop disabled at the ELC_GPTA input"]
2424 pub const _0: Self = Self::new(0);
2425
2426 #[doc = "Counter stop enabled at the ELC_GPTA input"]
2427 pub const _1: Self = Self::new(1);
2428 }
2429 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2430 pub struct Pselcb_SPEC;
2431 pub type Pselcb = crate::EnumBitfieldStruct<u8, Pselcb_SPEC>;
2432 impl Pselcb {
2433 #[doc = "Counter stop disabled at the ELC_GPTB input"]
2434 pub const _0: Self = Self::new(0);
2435
2436 #[doc = "Counter stop enabled at the ELC_GPTB input"]
2437 pub const _1: Self = Self::new(1);
2438 }
2439 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2440 pub struct Pselcc_SPEC;
2441 pub type Pselcc = crate::EnumBitfieldStruct<u8, Pselcc_SPEC>;
2442 impl Pselcc {
2443 #[doc = "Counter stop disabled at the ELC_GPTC input"]
2444 pub const _0: Self = Self::new(0);
2445
2446 #[doc = "Counter stop enabled at the ELC_GPTC input"]
2447 pub const _1: Self = Self::new(1);
2448 }
2449 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2450 pub struct Pselcd_SPEC;
2451 pub type Pselcd = crate::EnumBitfieldStruct<u8, Pselcd_SPEC>;
2452 impl Pselcd {
2453 #[doc = "Counter stop disabled at the ELC_GPTD input"]
2454 pub const _0: Self = Self::new(0);
2455
2456 #[doc = "Counter stop enabled at the ELC_GPTD input"]
2457 pub const _1: Self = Self::new(1);
2458 }
2459 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2460 pub struct Cstop_SPEC;
2461 pub type Cstop = crate::EnumBitfieldStruct<u8, Cstop_SPEC>;
2462 impl Cstop {
2463 #[doc = "Counter stop disabled by the GTSTP register"]
2464 pub const _0: Self = Self::new(0);
2465
2466 #[doc = "Counter stop enabled by the GTSTP register"]
2467 pub const _1: Self = Self::new(1);
2468 }
2469}
2470#[doc(hidden)]
2471#[derive(Copy, Clone, Eq, PartialEq)]
2472pub struct Gtcsr_SPEC;
2473impl crate::sealed::RegSpec for Gtcsr_SPEC {
2474 type DataType = u32;
2475}
2476
2477#[doc = "General PWM Timer Clear Source Select Register"]
2478pub type Gtcsr = crate::RegValueT<Gtcsr_SPEC>;
2479
2480impl Gtcsr {
2481 #[doc = "GTETRGA Pin Rising Input Source Counter Clear Enable"]
2482 #[inline(always)]
2483 pub fn csgtrgar(
2484 self,
2485 ) -> crate::common::RegisterField<
2486 0,
2487 0x1,
2488 1,
2489 0,
2490 gtcsr::Csgtrgar,
2491 gtcsr::Csgtrgar,
2492 Gtcsr_SPEC,
2493 crate::common::RW,
2494 > {
2495 crate::common::RegisterField::<
2496 0,
2497 0x1,
2498 1,
2499 0,
2500 gtcsr::Csgtrgar,
2501 gtcsr::Csgtrgar,
2502 Gtcsr_SPEC,
2503 crate::common::RW,
2504 >::from_register(self, 0)
2505 }
2506
2507 #[doc = "GTETRGA Pin Falling Input Source Counter Clear Enable"]
2508 #[inline(always)]
2509 pub fn csgtrgaf(
2510 self,
2511 ) -> crate::common::RegisterField<
2512 1,
2513 0x1,
2514 1,
2515 0,
2516 gtcsr::Csgtrgaf,
2517 gtcsr::Csgtrgaf,
2518 Gtcsr_SPEC,
2519 crate::common::RW,
2520 > {
2521 crate::common::RegisterField::<
2522 1,
2523 0x1,
2524 1,
2525 0,
2526 gtcsr::Csgtrgaf,
2527 gtcsr::Csgtrgaf,
2528 Gtcsr_SPEC,
2529 crate::common::RW,
2530 >::from_register(self, 0)
2531 }
2532
2533 #[doc = "GTETRGB Pin Rising Input Source Counter Clear Enable"]
2534 #[inline(always)]
2535 pub fn csgtrgbr(
2536 self,
2537 ) -> crate::common::RegisterField<
2538 2,
2539 0x1,
2540 1,
2541 0,
2542 gtcsr::Csgtrgbr,
2543 gtcsr::Csgtrgbr,
2544 Gtcsr_SPEC,
2545 crate::common::RW,
2546 > {
2547 crate::common::RegisterField::<
2548 2,
2549 0x1,
2550 1,
2551 0,
2552 gtcsr::Csgtrgbr,
2553 gtcsr::Csgtrgbr,
2554 Gtcsr_SPEC,
2555 crate::common::RW,
2556 >::from_register(self, 0)
2557 }
2558
2559 #[doc = "GTETRGB Pin Falling Input Source Counter Clear Enable"]
2560 #[inline(always)]
2561 pub fn csgtrgbf(
2562 self,
2563 ) -> crate::common::RegisterField<
2564 3,
2565 0x1,
2566 1,
2567 0,
2568 gtcsr::Csgtrgbf,
2569 gtcsr::Csgtrgbf,
2570 Gtcsr_SPEC,
2571 crate::common::RW,
2572 > {
2573 crate::common::RegisterField::<
2574 3,
2575 0x1,
2576 1,
2577 0,
2578 gtcsr::Csgtrgbf,
2579 gtcsr::Csgtrgbf,
2580 Gtcsr_SPEC,
2581 crate::common::RW,
2582 >::from_register(self, 0)
2583 }
2584
2585 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Clear Enable"]
2586 #[inline(always)]
2587 pub fn cscarbl(
2588 self,
2589 ) -> crate::common::RegisterField<
2590 8,
2591 0x1,
2592 1,
2593 0,
2594 gtcsr::Cscarbl,
2595 gtcsr::Cscarbl,
2596 Gtcsr_SPEC,
2597 crate::common::RW,
2598 > {
2599 crate::common::RegisterField::<
2600 8,
2601 0x1,
2602 1,
2603 0,
2604 gtcsr::Cscarbl,
2605 gtcsr::Cscarbl,
2606 Gtcsr_SPEC,
2607 crate::common::RW,
2608 >::from_register(self, 0)
2609 }
2610
2611 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Clear Enable"]
2612 #[inline(always)]
2613 pub fn cscarbh(
2614 self,
2615 ) -> crate::common::RegisterField<
2616 9,
2617 0x1,
2618 1,
2619 0,
2620 gtcsr::Cscarbh,
2621 gtcsr::Cscarbh,
2622 Gtcsr_SPEC,
2623 crate::common::RW,
2624 > {
2625 crate::common::RegisterField::<
2626 9,
2627 0x1,
2628 1,
2629 0,
2630 gtcsr::Cscarbh,
2631 gtcsr::Cscarbh,
2632 Gtcsr_SPEC,
2633 crate::common::RW,
2634 >::from_register(self, 0)
2635 }
2636
2637 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Clear Enable"]
2638 #[inline(always)]
2639 pub fn cscafbl(
2640 self,
2641 ) -> crate::common::RegisterField<
2642 10,
2643 0x1,
2644 1,
2645 0,
2646 gtcsr::Cscafbl,
2647 gtcsr::Cscafbl,
2648 Gtcsr_SPEC,
2649 crate::common::RW,
2650 > {
2651 crate::common::RegisterField::<
2652 10,
2653 0x1,
2654 1,
2655 0,
2656 gtcsr::Cscafbl,
2657 gtcsr::Cscafbl,
2658 Gtcsr_SPEC,
2659 crate::common::RW,
2660 >::from_register(self, 0)
2661 }
2662
2663 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Clear Enable"]
2664 #[inline(always)]
2665 pub fn cscafbh(
2666 self,
2667 ) -> crate::common::RegisterField<
2668 11,
2669 0x1,
2670 1,
2671 0,
2672 gtcsr::Cscafbh,
2673 gtcsr::Cscafbh,
2674 Gtcsr_SPEC,
2675 crate::common::RW,
2676 > {
2677 crate::common::RegisterField::<
2678 11,
2679 0x1,
2680 1,
2681 0,
2682 gtcsr::Cscafbh,
2683 gtcsr::Cscafbh,
2684 Gtcsr_SPEC,
2685 crate::common::RW,
2686 >::from_register(self, 0)
2687 }
2688
2689 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Clear Enable"]
2690 #[inline(always)]
2691 pub fn cscbral(
2692 self,
2693 ) -> crate::common::RegisterField<
2694 12,
2695 0x1,
2696 1,
2697 0,
2698 gtcsr::Cscbral,
2699 gtcsr::Cscbral,
2700 Gtcsr_SPEC,
2701 crate::common::RW,
2702 > {
2703 crate::common::RegisterField::<
2704 12,
2705 0x1,
2706 1,
2707 0,
2708 gtcsr::Cscbral,
2709 gtcsr::Cscbral,
2710 Gtcsr_SPEC,
2711 crate::common::RW,
2712 >::from_register(self, 0)
2713 }
2714
2715 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Clear Enable"]
2716 #[inline(always)]
2717 pub fn cscbrah(
2718 self,
2719 ) -> crate::common::RegisterField<
2720 13,
2721 0x1,
2722 1,
2723 0,
2724 gtcsr::Cscbrah,
2725 gtcsr::Cscbrah,
2726 Gtcsr_SPEC,
2727 crate::common::RW,
2728 > {
2729 crate::common::RegisterField::<
2730 13,
2731 0x1,
2732 1,
2733 0,
2734 gtcsr::Cscbrah,
2735 gtcsr::Cscbrah,
2736 Gtcsr_SPEC,
2737 crate::common::RW,
2738 >::from_register(self, 0)
2739 }
2740
2741 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Clear Enable"]
2742 #[inline(always)]
2743 pub fn cscbfal(
2744 self,
2745 ) -> crate::common::RegisterField<
2746 14,
2747 0x1,
2748 1,
2749 0,
2750 gtcsr::Cscbfal,
2751 gtcsr::Cscbfal,
2752 Gtcsr_SPEC,
2753 crate::common::RW,
2754 > {
2755 crate::common::RegisterField::<
2756 14,
2757 0x1,
2758 1,
2759 0,
2760 gtcsr::Cscbfal,
2761 gtcsr::Cscbfal,
2762 Gtcsr_SPEC,
2763 crate::common::RW,
2764 >::from_register(self, 0)
2765 }
2766
2767 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Clear Enable"]
2768 #[inline(always)]
2769 pub fn cscbfah(
2770 self,
2771 ) -> crate::common::RegisterField<
2772 15,
2773 0x1,
2774 1,
2775 0,
2776 gtcsr::Cscbfah,
2777 gtcsr::Cscbfah,
2778 Gtcsr_SPEC,
2779 crate::common::RW,
2780 > {
2781 crate::common::RegisterField::<
2782 15,
2783 0x1,
2784 1,
2785 0,
2786 gtcsr::Cscbfah,
2787 gtcsr::Cscbfah,
2788 Gtcsr_SPEC,
2789 crate::common::RW,
2790 >::from_register(self, 0)
2791 }
2792
2793 #[doc = "ELC_GPTA Event Source Counter Clear Enable"]
2794 #[inline(always)]
2795 pub fn cselca(
2796 self,
2797 ) -> crate::common::RegisterField<
2798 16,
2799 0x1,
2800 1,
2801 0,
2802 gtcsr::Cselca,
2803 gtcsr::Cselca,
2804 Gtcsr_SPEC,
2805 crate::common::RW,
2806 > {
2807 crate::common::RegisterField::<
2808 16,
2809 0x1,
2810 1,
2811 0,
2812 gtcsr::Cselca,
2813 gtcsr::Cselca,
2814 Gtcsr_SPEC,
2815 crate::common::RW,
2816 >::from_register(self, 0)
2817 }
2818
2819 #[doc = "ELC_GPTB Event Source Counter Clear Enable"]
2820 #[inline(always)]
2821 pub fn cselcb(
2822 self,
2823 ) -> crate::common::RegisterField<
2824 17,
2825 0x1,
2826 1,
2827 0,
2828 gtcsr::Cselcb,
2829 gtcsr::Cselcb,
2830 Gtcsr_SPEC,
2831 crate::common::RW,
2832 > {
2833 crate::common::RegisterField::<
2834 17,
2835 0x1,
2836 1,
2837 0,
2838 gtcsr::Cselcb,
2839 gtcsr::Cselcb,
2840 Gtcsr_SPEC,
2841 crate::common::RW,
2842 >::from_register(self, 0)
2843 }
2844
2845 #[doc = "ELC_GPTC Event Source Counter Clear Enable"]
2846 #[inline(always)]
2847 pub fn cselcc(
2848 self,
2849 ) -> crate::common::RegisterField<
2850 18,
2851 0x1,
2852 1,
2853 0,
2854 gtcsr::Cselcc,
2855 gtcsr::Cselcc,
2856 Gtcsr_SPEC,
2857 crate::common::RW,
2858 > {
2859 crate::common::RegisterField::<
2860 18,
2861 0x1,
2862 1,
2863 0,
2864 gtcsr::Cselcc,
2865 gtcsr::Cselcc,
2866 Gtcsr_SPEC,
2867 crate::common::RW,
2868 >::from_register(self, 0)
2869 }
2870
2871 #[doc = "ELC_GPTD Event Source Counter Clear Enable"]
2872 #[inline(always)]
2873 pub fn cselcd(
2874 self,
2875 ) -> crate::common::RegisterField<
2876 19,
2877 0x1,
2878 1,
2879 0,
2880 gtcsr::Cselcd,
2881 gtcsr::Cselcd,
2882 Gtcsr_SPEC,
2883 crate::common::RW,
2884 > {
2885 crate::common::RegisterField::<
2886 19,
2887 0x1,
2888 1,
2889 0,
2890 gtcsr::Cselcd,
2891 gtcsr::Cselcd,
2892 Gtcsr_SPEC,
2893 crate::common::RW,
2894 >::from_register(self, 0)
2895 }
2896
2897 #[doc = "Software Source Counter Clear Enable"]
2898 #[inline(always)]
2899 pub fn cclr(
2900 self,
2901 ) -> crate::common::RegisterField<
2902 31,
2903 0x1,
2904 1,
2905 0,
2906 gtcsr::Cclr,
2907 gtcsr::Cclr,
2908 Gtcsr_SPEC,
2909 crate::common::RW,
2910 > {
2911 crate::common::RegisterField::<
2912 31,
2913 0x1,
2914 1,
2915 0,
2916 gtcsr::Cclr,
2917 gtcsr::Cclr,
2918 Gtcsr_SPEC,
2919 crate::common::RW,
2920 >::from_register(self, 0)
2921 }
2922}
2923impl ::core::default::Default for Gtcsr {
2924 #[inline(always)]
2925 fn default() -> Gtcsr {
2926 <crate::RegValueT<Gtcsr_SPEC> as RegisterValue<_>>::new(0)
2927 }
2928}
2929pub mod gtcsr {
2930
2931 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2932 pub struct Csgtrgar_SPEC;
2933 pub type Csgtrgar = crate::EnumBitfieldStruct<u8, Csgtrgar_SPEC>;
2934 impl Csgtrgar {
2935 #[doc = "Counter clear disabled on the rising edge of GTETRGA input"]
2936 pub const _0: Self = Self::new(0);
2937
2938 #[doc = "Counter clear enabled on the rising edge of GTETRGA input"]
2939 pub const _1: Self = Self::new(1);
2940 }
2941 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2942 pub struct Csgtrgaf_SPEC;
2943 pub type Csgtrgaf = crate::EnumBitfieldStruct<u8, Csgtrgaf_SPEC>;
2944 impl Csgtrgaf {
2945 #[doc = "Counter clear disabled on the falling edge of GTETRGA input"]
2946 pub const _0: Self = Self::new(0);
2947
2948 #[doc = "Counter clear enabled on the falling edge of GTETRGA input"]
2949 pub const _1: Self = Self::new(1);
2950 }
2951 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2952 pub struct Csgtrgbr_SPEC;
2953 pub type Csgtrgbr = crate::EnumBitfieldStruct<u8, Csgtrgbr_SPEC>;
2954 impl Csgtrgbr {
2955 #[doc = "Disable counter clear on the rising edge of GTETRGB input"]
2956 pub const _0: Self = Self::new(0);
2957
2958 #[doc = "Enable counter clear on the rising edge of GTETRGB input"]
2959 pub const _1: Self = Self::new(1);
2960 }
2961 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2962 pub struct Csgtrgbf_SPEC;
2963 pub type Csgtrgbf = crate::EnumBitfieldStruct<u8, Csgtrgbf_SPEC>;
2964 impl Csgtrgbf {
2965 #[doc = "Counter clear disabled on the falling edge of GTETRGB input"]
2966 pub const _0: Self = Self::new(0);
2967
2968 #[doc = "Counter clear enabled on the falling edge of GTETRGB input"]
2969 pub const _1: Self = Self::new(1);
2970 }
2971 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2972 pub struct Cscarbl_SPEC;
2973 pub type Cscarbl = crate::EnumBitfieldStruct<u8, Cscarbl_SPEC>;
2974 impl Cscarbl {
2975 #[doc = "Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2976 pub const _0: Self = Self::new(0);
2977
2978 #[doc = "Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
2979 pub const _1: Self = Self::new(1);
2980 }
2981 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2982 pub struct Cscarbh_SPEC;
2983 pub type Cscarbh = crate::EnumBitfieldStruct<u8, Cscarbh_SPEC>;
2984 impl Cscarbh {
2985 #[doc = "Counter clear disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2986 pub const _0: Self = Self::new(0);
2987
2988 #[doc = "Counter clear enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
2989 pub const _1: Self = Self::new(1);
2990 }
2991 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2992 pub struct Cscafbl_SPEC;
2993 pub type Cscafbl = crate::EnumBitfieldStruct<u8, Cscafbl_SPEC>;
2994 impl Cscafbl {
2995 #[doc = "Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2996 pub const _0: Self = Self::new(0);
2997
2998 #[doc = "Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
2999 pub const _1: Self = Self::new(1);
3000 }
3001 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3002 pub struct Cscafbh_SPEC;
3003 pub type Cscafbh = crate::EnumBitfieldStruct<u8, Cscafbh_SPEC>;
3004 impl Cscafbh {
3005 #[doc = "Counter clear disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3006 pub const _0: Self = Self::new(0);
3007
3008 #[doc = "Counter clear enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3009 pub const _1: Self = Self::new(1);
3010 }
3011 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3012 pub struct Cscbral_SPEC;
3013 pub type Cscbral = crate::EnumBitfieldStruct<u8, Cscbral_SPEC>;
3014 impl Cscbral {
3015 #[doc = "Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3016 pub const _0: Self = Self::new(0);
3017
3018 #[doc = "Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3019 pub const _1: Self = Self::new(1);
3020 }
3021 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3022 pub struct Cscbrah_SPEC;
3023 pub type Cscbrah = crate::EnumBitfieldStruct<u8, Cscbrah_SPEC>;
3024 impl Cscbrah {
3025 #[doc = "Counter clear disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3026 pub const _0: Self = Self::new(0);
3027
3028 #[doc = "Counter clear enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3029 pub const _1: Self = Self::new(1);
3030 }
3031 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3032 pub struct Cscbfal_SPEC;
3033 pub type Cscbfal = crate::EnumBitfieldStruct<u8, Cscbfal_SPEC>;
3034 impl Cscbfal {
3035 #[doc = "Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3036 pub const _0: Self = Self::new(0);
3037
3038 #[doc = "Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3039 pub const _1: Self = Self::new(1);
3040 }
3041 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3042 pub struct Cscbfah_SPEC;
3043 pub type Cscbfah = crate::EnumBitfieldStruct<u8, Cscbfah_SPEC>;
3044 impl Cscbfah {
3045 #[doc = "Counter clear disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3046 pub const _0: Self = Self::new(0);
3047
3048 #[doc = "Counter clear enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3049 pub const _1: Self = Self::new(1);
3050 }
3051 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3052 pub struct Cselca_SPEC;
3053 pub type Cselca = crate::EnumBitfieldStruct<u8, Cselca_SPEC>;
3054 impl Cselca {
3055 #[doc = "Counter clear disabled at the ELC_GPTA input"]
3056 pub const _0: Self = Self::new(0);
3057
3058 #[doc = "Counter clear enabled at the ELC_GPTA input"]
3059 pub const _1: Self = Self::new(1);
3060 }
3061 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3062 pub struct Cselcb_SPEC;
3063 pub type Cselcb = crate::EnumBitfieldStruct<u8, Cselcb_SPEC>;
3064 impl Cselcb {
3065 #[doc = "Counter clear disabled at the ELC_GPTB input"]
3066 pub const _0: Self = Self::new(0);
3067
3068 #[doc = "Counter clear enabled at the ELC_GPTB input"]
3069 pub const _1: Self = Self::new(1);
3070 }
3071 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3072 pub struct Cselcc_SPEC;
3073 pub type Cselcc = crate::EnumBitfieldStruct<u8, Cselcc_SPEC>;
3074 impl Cselcc {
3075 #[doc = "Counter clear disabled at the ELC_GPTC input"]
3076 pub const _0: Self = Self::new(0);
3077
3078 #[doc = "Counter clear enabled at the ELC_GPTC input"]
3079 pub const _1: Self = Self::new(1);
3080 }
3081 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3082 pub struct Cselcd_SPEC;
3083 pub type Cselcd = crate::EnumBitfieldStruct<u8, Cselcd_SPEC>;
3084 impl Cselcd {
3085 #[doc = "Counter clear disabled at the ELC_GPTD input"]
3086 pub const _0: Self = Self::new(0);
3087
3088 #[doc = "Counter clear enabled at the ELC_GPTD input"]
3089 pub const _1: Self = Self::new(1);
3090 }
3091 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3092 pub struct Cclr_SPEC;
3093 pub type Cclr = crate::EnumBitfieldStruct<u8, Cclr_SPEC>;
3094 impl Cclr {
3095 #[doc = "Counter clear disabled by the GTCLR register"]
3096 pub const _0: Self = Self::new(0);
3097
3098 #[doc = "Counter clear enabled by the GTCLR register"]
3099 pub const _1: Self = Self::new(1);
3100 }
3101}
3102#[doc(hidden)]
3103#[derive(Copy, Clone, Eq, PartialEq)]
3104pub struct Gtupsr_SPEC;
3105impl crate::sealed::RegSpec for Gtupsr_SPEC {
3106 type DataType = u32;
3107}
3108
3109#[doc = "General PWM Timer Up Count Source Select Register"]
3110pub type Gtupsr = crate::RegValueT<Gtupsr_SPEC>;
3111
3112impl Gtupsr {
3113 #[doc = "GTETRGA Pin Rising Input Source Counter Count Up Enable"]
3114 #[inline(always)]
3115 pub fn usgtrgar(
3116 self,
3117 ) -> crate::common::RegisterField<
3118 0,
3119 0x1,
3120 1,
3121 0,
3122 gtupsr::Usgtrgar,
3123 gtupsr::Usgtrgar,
3124 Gtupsr_SPEC,
3125 crate::common::RW,
3126 > {
3127 crate::common::RegisterField::<
3128 0,
3129 0x1,
3130 1,
3131 0,
3132 gtupsr::Usgtrgar,
3133 gtupsr::Usgtrgar,
3134 Gtupsr_SPEC,
3135 crate::common::RW,
3136 >::from_register(self, 0)
3137 }
3138
3139 #[doc = "GTETRGA Pin Falling Input Source Counter Count Up Enable"]
3140 #[inline(always)]
3141 pub fn usgtrgaf(
3142 self,
3143 ) -> crate::common::RegisterField<
3144 1,
3145 0x1,
3146 1,
3147 0,
3148 gtupsr::Usgtrgaf,
3149 gtupsr::Usgtrgaf,
3150 Gtupsr_SPEC,
3151 crate::common::RW,
3152 > {
3153 crate::common::RegisterField::<
3154 1,
3155 0x1,
3156 1,
3157 0,
3158 gtupsr::Usgtrgaf,
3159 gtupsr::Usgtrgaf,
3160 Gtupsr_SPEC,
3161 crate::common::RW,
3162 >::from_register(self, 0)
3163 }
3164
3165 #[doc = "GTETRGB Pin Rising Input Source Counter Count Up Enable"]
3166 #[inline(always)]
3167 pub fn usgtrgbr(
3168 self,
3169 ) -> crate::common::RegisterField<
3170 2,
3171 0x1,
3172 1,
3173 0,
3174 gtupsr::Usgtrgbr,
3175 gtupsr::Usgtrgbr,
3176 Gtupsr_SPEC,
3177 crate::common::RW,
3178 > {
3179 crate::common::RegisterField::<
3180 2,
3181 0x1,
3182 1,
3183 0,
3184 gtupsr::Usgtrgbr,
3185 gtupsr::Usgtrgbr,
3186 Gtupsr_SPEC,
3187 crate::common::RW,
3188 >::from_register(self, 0)
3189 }
3190
3191 #[doc = "GTETRGB Pin Falling Input Source Counter Count Up Enable"]
3192 #[inline(always)]
3193 pub fn usgtrgbf(
3194 self,
3195 ) -> crate::common::RegisterField<
3196 3,
3197 0x1,
3198 1,
3199 0,
3200 gtupsr::Usgtrgbf,
3201 gtupsr::Usgtrgbf,
3202 Gtupsr_SPEC,
3203 crate::common::RW,
3204 > {
3205 crate::common::RegisterField::<
3206 3,
3207 0x1,
3208 1,
3209 0,
3210 gtupsr::Usgtrgbf,
3211 gtupsr::Usgtrgbf,
3212 Gtupsr_SPEC,
3213 crate::common::RW,
3214 >::from_register(self, 0)
3215 }
3216
3217 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Up Enable"]
3218 #[inline(always)]
3219 pub fn uscarbl(
3220 self,
3221 ) -> crate::common::RegisterField<
3222 8,
3223 0x1,
3224 1,
3225 0,
3226 gtupsr::Uscarbl,
3227 gtupsr::Uscarbl,
3228 Gtupsr_SPEC,
3229 crate::common::RW,
3230 > {
3231 crate::common::RegisterField::<
3232 8,
3233 0x1,
3234 1,
3235 0,
3236 gtupsr::Uscarbl,
3237 gtupsr::Uscarbl,
3238 Gtupsr_SPEC,
3239 crate::common::RW,
3240 >::from_register(self, 0)
3241 }
3242
3243 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Up Enable"]
3244 #[inline(always)]
3245 pub fn uscarbh(
3246 self,
3247 ) -> crate::common::RegisterField<
3248 9,
3249 0x1,
3250 1,
3251 0,
3252 gtupsr::Uscarbh,
3253 gtupsr::Uscarbh,
3254 Gtupsr_SPEC,
3255 crate::common::RW,
3256 > {
3257 crate::common::RegisterField::<
3258 9,
3259 0x1,
3260 1,
3261 0,
3262 gtupsr::Uscarbh,
3263 gtupsr::Uscarbh,
3264 Gtupsr_SPEC,
3265 crate::common::RW,
3266 >::from_register(self, 0)
3267 }
3268
3269 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Up Enable"]
3270 #[inline(always)]
3271 pub fn uscafbl(
3272 self,
3273 ) -> crate::common::RegisterField<
3274 10,
3275 0x1,
3276 1,
3277 0,
3278 gtupsr::Uscafbl,
3279 gtupsr::Uscafbl,
3280 Gtupsr_SPEC,
3281 crate::common::RW,
3282 > {
3283 crate::common::RegisterField::<
3284 10,
3285 0x1,
3286 1,
3287 0,
3288 gtupsr::Uscafbl,
3289 gtupsr::Uscafbl,
3290 Gtupsr_SPEC,
3291 crate::common::RW,
3292 >::from_register(self, 0)
3293 }
3294
3295 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Up Enable"]
3296 #[inline(always)]
3297 pub fn uscafbh(
3298 self,
3299 ) -> crate::common::RegisterField<
3300 11,
3301 0x1,
3302 1,
3303 0,
3304 gtupsr::Uscafbh,
3305 gtupsr::Uscafbh,
3306 Gtupsr_SPEC,
3307 crate::common::RW,
3308 > {
3309 crate::common::RegisterField::<
3310 11,
3311 0x1,
3312 1,
3313 0,
3314 gtupsr::Uscafbh,
3315 gtupsr::Uscafbh,
3316 Gtupsr_SPEC,
3317 crate::common::RW,
3318 >::from_register(self, 0)
3319 }
3320
3321 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Up Enable"]
3322 #[inline(always)]
3323 pub fn uscbral(
3324 self,
3325 ) -> crate::common::RegisterField<
3326 12,
3327 0x1,
3328 1,
3329 0,
3330 gtupsr::Uscbral,
3331 gtupsr::Uscbral,
3332 Gtupsr_SPEC,
3333 crate::common::RW,
3334 > {
3335 crate::common::RegisterField::<
3336 12,
3337 0x1,
3338 1,
3339 0,
3340 gtupsr::Uscbral,
3341 gtupsr::Uscbral,
3342 Gtupsr_SPEC,
3343 crate::common::RW,
3344 >::from_register(self, 0)
3345 }
3346
3347 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Up Enable"]
3348 #[inline(always)]
3349 pub fn uscbrah(
3350 self,
3351 ) -> crate::common::RegisterField<
3352 13,
3353 0x1,
3354 1,
3355 0,
3356 gtupsr::Uscbrah,
3357 gtupsr::Uscbrah,
3358 Gtupsr_SPEC,
3359 crate::common::RW,
3360 > {
3361 crate::common::RegisterField::<
3362 13,
3363 0x1,
3364 1,
3365 0,
3366 gtupsr::Uscbrah,
3367 gtupsr::Uscbrah,
3368 Gtupsr_SPEC,
3369 crate::common::RW,
3370 >::from_register(self, 0)
3371 }
3372
3373 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Up Enable"]
3374 #[inline(always)]
3375 pub fn uscbfal(
3376 self,
3377 ) -> crate::common::RegisterField<
3378 14,
3379 0x1,
3380 1,
3381 0,
3382 gtupsr::Uscbfal,
3383 gtupsr::Uscbfal,
3384 Gtupsr_SPEC,
3385 crate::common::RW,
3386 > {
3387 crate::common::RegisterField::<
3388 14,
3389 0x1,
3390 1,
3391 0,
3392 gtupsr::Uscbfal,
3393 gtupsr::Uscbfal,
3394 Gtupsr_SPEC,
3395 crate::common::RW,
3396 >::from_register(self, 0)
3397 }
3398
3399 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Up Enable"]
3400 #[inline(always)]
3401 pub fn uscbfah(
3402 self,
3403 ) -> crate::common::RegisterField<
3404 15,
3405 0x1,
3406 1,
3407 0,
3408 gtupsr::Uscbfah,
3409 gtupsr::Uscbfah,
3410 Gtupsr_SPEC,
3411 crate::common::RW,
3412 > {
3413 crate::common::RegisterField::<
3414 15,
3415 0x1,
3416 1,
3417 0,
3418 gtupsr::Uscbfah,
3419 gtupsr::Uscbfah,
3420 Gtupsr_SPEC,
3421 crate::common::RW,
3422 >::from_register(self, 0)
3423 }
3424
3425 #[doc = "ELC_GPTA Event Source Counter Count Up Enable"]
3426 #[inline(always)]
3427 pub fn uselca(
3428 self,
3429 ) -> crate::common::RegisterField<
3430 16,
3431 0x1,
3432 1,
3433 0,
3434 gtupsr::Uselca,
3435 gtupsr::Uselca,
3436 Gtupsr_SPEC,
3437 crate::common::RW,
3438 > {
3439 crate::common::RegisterField::<
3440 16,
3441 0x1,
3442 1,
3443 0,
3444 gtupsr::Uselca,
3445 gtupsr::Uselca,
3446 Gtupsr_SPEC,
3447 crate::common::RW,
3448 >::from_register(self, 0)
3449 }
3450
3451 #[doc = "ELC_GPTB Event Source Counter Count Up Enable"]
3452 #[inline(always)]
3453 pub fn uselcb(
3454 self,
3455 ) -> crate::common::RegisterField<
3456 17,
3457 0x1,
3458 1,
3459 0,
3460 gtupsr::Uselcb,
3461 gtupsr::Uselcb,
3462 Gtupsr_SPEC,
3463 crate::common::RW,
3464 > {
3465 crate::common::RegisterField::<
3466 17,
3467 0x1,
3468 1,
3469 0,
3470 gtupsr::Uselcb,
3471 gtupsr::Uselcb,
3472 Gtupsr_SPEC,
3473 crate::common::RW,
3474 >::from_register(self, 0)
3475 }
3476
3477 #[doc = "ELC_GPTC Event Source Counter Count Up Enable"]
3478 #[inline(always)]
3479 pub fn uselcc(
3480 self,
3481 ) -> crate::common::RegisterField<
3482 18,
3483 0x1,
3484 1,
3485 0,
3486 gtupsr::Uselcc,
3487 gtupsr::Uselcc,
3488 Gtupsr_SPEC,
3489 crate::common::RW,
3490 > {
3491 crate::common::RegisterField::<
3492 18,
3493 0x1,
3494 1,
3495 0,
3496 gtupsr::Uselcc,
3497 gtupsr::Uselcc,
3498 Gtupsr_SPEC,
3499 crate::common::RW,
3500 >::from_register(self, 0)
3501 }
3502
3503 #[doc = "ELC_GPTD Event Source Counter Count Up Enable"]
3504 #[inline(always)]
3505 pub fn uselcd(
3506 self,
3507 ) -> crate::common::RegisterField<
3508 19,
3509 0x1,
3510 1,
3511 0,
3512 gtupsr::Uselcd,
3513 gtupsr::Uselcd,
3514 Gtupsr_SPEC,
3515 crate::common::RW,
3516 > {
3517 crate::common::RegisterField::<
3518 19,
3519 0x1,
3520 1,
3521 0,
3522 gtupsr::Uselcd,
3523 gtupsr::Uselcd,
3524 Gtupsr_SPEC,
3525 crate::common::RW,
3526 >::from_register(self, 0)
3527 }
3528}
3529impl ::core::default::Default for Gtupsr {
3530 #[inline(always)]
3531 fn default() -> Gtupsr {
3532 <crate::RegValueT<Gtupsr_SPEC> as RegisterValue<_>>::new(0)
3533 }
3534}
3535pub mod gtupsr {
3536
3537 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3538 pub struct Usgtrgar_SPEC;
3539 pub type Usgtrgar = crate::EnumBitfieldStruct<u8, Usgtrgar_SPEC>;
3540 impl Usgtrgar {
3541 #[doc = "Counter count up disabled on the rising edge of GTETRGA input"]
3542 pub const _0: Self = Self::new(0);
3543
3544 #[doc = "Counter count up enabled on the rising edge of GTETRGA input"]
3545 pub const _1: Self = Self::new(1);
3546 }
3547 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3548 pub struct Usgtrgaf_SPEC;
3549 pub type Usgtrgaf = crate::EnumBitfieldStruct<u8, Usgtrgaf_SPEC>;
3550 impl Usgtrgaf {
3551 #[doc = "Counter count up disabled on the falling edge of GTETRGA input"]
3552 pub const _0: Self = Self::new(0);
3553
3554 #[doc = "Counter count up enabled on the falling edge of GTETRGA input"]
3555 pub const _1: Self = Self::new(1);
3556 }
3557 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3558 pub struct Usgtrgbr_SPEC;
3559 pub type Usgtrgbr = crate::EnumBitfieldStruct<u8, Usgtrgbr_SPEC>;
3560 impl Usgtrgbr {
3561 #[doc = "Counter count up disabled on the rising edge of GTETRGB input"]
3562 pub const _0: Self = Self::new(0);
3563
3564 #[doc = "Counter count up enabled on the rising edge of GTETRGB input"]
3565 pub const _1: Self = Self::new(1);
3566 }
3567 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3568 pub struct Usgtrgbf_SPEC;
3569 pub type Usgtrgbf = crate::EnumBitfieldStruct<u8, Usgtrgbf_SPEC>;
3570 impl Usgtrgbf {
3571 #[doc = "Counter count up disabled on the falling edge of GTETRGB input"]
3572 pub const _0: Self = Self::new(0);
3573
3574 #[doc = "Counter count up enabled on the falling edge of GTETRGB input"]
3575 pub const _1: Self = Self::new(1);
3576 }
3577 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3578 pub struct Uscarbl_SPEC;
3579 pub type Uscarbl = crate::EnumBitfieldStruct<u8, Uscarbl_SPEC>;
3580 impl Uscarbl {
3581 #[doc = "Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3582 pub const _0: Self = Self::new(0);
3583
3584 #[doc = "Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
3585 pub const _1: Self = Self::new(1);
3586 }
3587 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3588 pub struct Uscarbh_SPEC;
3589 pub type Uscarbh = crate::EnumBitfieldStruct<u8, Uscarbh_SPEC>;
3590 impl Uscarbh {
3591 #[doc = "Counter count up disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3592 pub const _0: Self = Self::new(0);
3593
3594 #[doc = "Counter count up enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
3595 pub const _1: Self = Self::new(1);
3596 }
3597 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3598 pub struct Uscafbl_SPEC;
3599 pub type Uscafbl = crate::EnumBitfieldStruct<u8, Uscafbl_SPEC>;
3600 impl Uscafbl {
3601 #[doc = "Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3602 pub const _0: Self = Self::new(0);
3603
3604 #[doc = "Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
3605 pub const _1: Self = Self::new(1);
3606 }
3607 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3608 pub struct Uscafbh_SPEC;
3609 pub type Uscafbh = crate::EnumBitfieldStruct<u8, Uscafbh_SPEC>;
3610 impl Uscafbh {
3611 #[doc = "Counter count up disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3612 pub const _0: Self = Self::new(0);
3613
3614 #[doc = "Counter count up enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
3615 pub const _1: Self = Self::new(1);
3616 }
3617 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3618 pub struct Uscbral_SPEC;
3619 pub type Uscbral = crate::EnumBitfieldStruct<u8, Uscbral_SPEC>;
3620 impl Uscbral {
3621 #[doc = "Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3622 pub const _0: Self = Self::new(0);
3623
3624 #[doc = "Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
3625 pub const _1: Self = Self::new(1);
3626 }
3627 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3628 pub struct Uscbrah_SPEC;
3629 pub type Uscbrah = crate::EnumBitfieldStruct<u8, Uscbrah_SPEC>;
3630 impl Uscbrah {
3631 #[doc = "Counter count up disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3632 pub const _0: Self = Self::new(0);
3633
3634 #[doc = "Counter count up enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
3635 pub const _1: Self = Self::new(1);
3636 }
3637 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3638 pub struct Uscbfal_SPEC;
3639 pub type Uscbfal = crate::EnumBitfieldStruct<u8, Uscbfal_SPEC>;
3640 impl Uscbfal {
3641 #[doc = "Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3642 pub const _0: Self = Self::new(0);
3643
3644 #[doc = "Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
3645 pub const _1: Self = Self::new(1);
3646 }
3647 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3648 pub struct Uscbfah_SPEC;
3649 pub type Uscbfah = crate::EnumBitfieldStruct<u8, Uscbfah_SPEC>;
3650 impl Uscbfah {
3651 #[doc = "Counter count up disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3652 pub const _0: Self = Self::new(0);
3653
3654 #[doc = "Counter count up enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
3655 pub const _1: Self = Self::new(1);
3656 }
3657 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3658 pub struct Uselca_SPEC;
3659 pub type Uselca = crate::EnumBitfieldStruct<u8, Uselca_SPEC>;
3660 impl Uselca {
3661 #[doc = "Counter count up disabled at the ELC_GPTA input"]
3662 pub const _0: Self = Self::new(0);
3663
3664 #[doc = "Counter count up enabled at the ELC_GPTA input"]
3665 pub const _1: Self = Self::new(1);
3666 }
3667 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3668 pub struct Uselcb_SPEC;
3669 pub type Uselcb = crate::EnumBitfieldStruct<u8, Uselcb_SPEC>;
3670 impl Uselcb {
3671 #[doc = "Counter count up disabled at the ELC_GPTB input"]
3672 pub const _0: Self = Self::new(0);
3673
3674 #[doc = "Counter count up enabled at the ELC_GPTB input"]
3675 pub const _1: Self = Self::new(1);
3676 }
3677 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3678 pub struct Uselcc_SPEC;
3679 pub type Uselcc = crate::EnumBitfieldStruct<u8, Uselcc_SPEC>;
3680 impl Uselcc {
3681 #[doc = "Counter count up disabled at the ELC_GPTC input"]
3682 pub const _0: Self = Self::new(0);
3683
3684 #[doc = "Counter count up enabled at the ELC_GPTC input"]
3685 pub const _1: Self = Self::new(1);
3686 }
3687 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3688 pub struct Uselcd_SPEC;
3689 pub type Uselcd = crate::EnumBitfieldStruct<u8, Uselcd_SPEC>;
3690 impl Uselcd {
3691 #[doc = "Counter count up disabled at the ELC_GPTD input"]
3692 pub const _0: Self = Self::new(0);
3693
3694 #[doc = "Counter count up enabled at the ELC_GPTD input"]
3695 pub const _1: Self = Self::new(1);
3696 }
3697}
3698#[doc(hidden)]
3699#[derive(Copy, Clone, Eq, PartialEq)]
3700pub struct Gtdnsr_SPEC;
3701impl crate::sealed::RegSpec for Gtdnsr_SPEC {
3702 type DataType = u32;
3703}
3704
3705#[doc = "General PWM Timer Down Count Source Select Register"]
3706pub type Gtdnsr = crate::RegValueT<Gtdnsr_SPEC>;
3707
3708impl Gtdnsr {
3709 #[doc = "GTETRGA Pin Rising Input Source Counter Count Down Enable"]
3710 #[inline(always)]
3711 pub fn dsgtrgar(
3712 self,
3713 ) -> crate::common::RegisterField<
3714 0,
3715 0x1,
3716 1,
3717 0,
3718 gtdnsr::Dsgtrgar,
3719 gtdnsr::Dsgtrgar,
3720 Gtdnsr_SPEC,
3721 crate::common::RW,
3722 > {
3723 crate::common::RegisterField::<
3724 0,
3725 0x1,
3726 1,
3727 0,
3728 gtdnsr::Dsgtrgar,
3729 gtdnsr::Dsgtrgar,
3730 Gtdnsr_SPEC,
3731 crate::common::RW,
3732 >::from_register(self, 0)
3733 }
3734
3735 #[doc = "GTETRGA Pin Falling Input Source Counter Count Down Enable"]
3736 #[inline(always)]
3737 pub fn dsgtrgaf(
3738 self,
3739 ) -> crate::common::RegisterField<
3740 1,
3741 0x1,
3742 1,
3743 0,
3744 gtdnsr::Dsgtrgaf,
3745 gtdnsr::Dsgtrgaf,
3746 Gtdnsr_SPEC,
3747 crate::common::RW,
3748 > {
3749 crate::common::RegisterField::<
3750 1,
3751 0x1,
3752 1,
3753 0,
3754 gtdnsr::Dsgtrgaf,
3755 gtdnsr::Dsgtrgaf,
3756 Gtdnsr_SPEC,
3757 crate::common::RW,
3758 >::from_register(self, 0)
3759 }
3760
3761 #[doc = "GTETRGB Pin Rising Input Source Counter Count Down Enable"]
3762 #[inline(always)]
3763 pub fn dsgtrgbr(
3764 self,
3765 ) -> crate::common::RegisterField<
3766 2,
3767 0x1,
3768 1,
3769 0,
3770 gtdnsr::Dsgtrgbr,
3771 gtdnsr::Dsgtrgbr,
3772 Gtdnsr_SPEC,
3773 crate::common::RW,
3774 > {
3775 crate::common::RegisterField::<
3776 2,
3777 0x1,
3778 1,
3779 0,
3780 gtdnsr::Dsgtrgbr,
3781 gtdnsr::Dsgtrgbr,
3782 Gtdnsr_SPEC,
3783 crate::common::RW,
3784 >::from_register(self, 0)
3785 }
3786
3787 #[doc = "GTETRGB Pin Falling Input Source Counter Count Down Enable"]
3788 #[inline(always)]
3789 pub fn dsgtrgbf(
3790 self,
3791 ) -> crate::common::RegisterField<
3792 3,
3793 0x1,
3794 1,
3795 0,
3796 gtdnsr::Dsgtrgbf,
3797 gtdnsr::Dsgtrgbf,
3798 Gtdnsr_SPEC,
3799 crate::common::RW,
3800 > {
3801 crate::common::RegisterField::<
3802 3,
3803 0x1,
3804 1,
3805 0,
3806 gtdnsr::Dsgtrgbf,
3807 gtdnsr::Dsgtrgbf,
3808 Gtdnsr_SPEC,
3809 crate::common::RW,
3810 >::from_register(self, 0)
3811 }
3812
3813 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source Counter Count Down Enable"]
3814 #[inline(always)]
3815 pub fn dscarbl(
3816 self,
3817 ) -> crate::common::RegisterField<
3818 8,
3819 0x1,
3820 1,
3821 0,
3822 gtdnsr::Dscarbl,
3823 gtdnsr::Dscarbl,
3824 Gtdnsr_SPEC,
3825 crate::common::RW,
3826 > {
3827 crate::common::RegisterField::<
3828 8,
3829 0x1,
3830 1,
3831 0,
3832 gtdnsr::Dscarbl,
3833 gtdnsr::Dscarbl,
3834 Gtdnsr_SPEC,
3835 crate::common::RW,
3836 >::from_register(self, 0)
3837 }
3838
3839 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source Counter Count Down Enable"]
3840 #[inline(always)]
3841 pub fn dscarbh(
3842 self,
3843 ) -> crate::common::RegisterField<
3844 9,
3845 0x1,
3846 1,
3847 0,
3848 gtdnsr::Dscarbh,
3849 gtdnsr::Dscarbh,
3850 Gtdnsr_SPEC,
3851 crate::common::RW,
3852 > {
3853 crate::common::RegisterField::<
3854 9,
3855 0x1,
3856 1,
3857 0,
3858 gtdnsr::Dscarbh,
3859 gtdnsr::Dscarbh,
3860 Gtdnsr_SPEC,
3861 crate::common::RW,
3862 >::from_register(self, 0)
3863 }
3864
3865 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source Counter Count Down Enable"]
3866 #[inline(always)]
3867 pub fn dscafbl(
3868 self,
3869 ) -> crate::common::RegisterField<
3870 10,
3871 0x1,
3872 1,
3873 0,
3874 gtdnsr::Dscafbl,
3875 gtdnsr::Dscafbl,
3876 Gtdnsr_SPEC,
3877 crate::common::RW,
3878 > {
3879 crate::common::RegisterField::<
3880 10,
3881 0x1,
3882 1,
3883 0,
3884 gtdnsr::Dscafbl,
3885 gtdnsr::Dscafbl,
3886 Gtdnsr_SPEC,
3887 crate::common::RW,
3888 >::from_register(self, 0)
3889 }
3890
3891 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source Counter Count Down Enable"]
3892 #[inline(always)]
3893 pub fn dscafbh(
3894 self,
3895 ) -> crate::common::RegisterField<
3896 11,
3897 0x1,
3898 1,
3899 0,
3900 gtdnsr::Dscafbh,
3901 gtdnsr::Dscafbh,
3902 Gtdnsr_SPEC,
3903 crate::common::RW,
3904 > {
3905 crate::common::RegisterField::<
3906 11,
3907 0x1,
3908 1,
3909 0,
3910 gtdnsr::Dscafbh,
3911 gtdnsr::Dscafbh,
3912 Gtdnsr_SPEC,
3913 crate::common::RW,
3914 >::from_register(self, 0)
3915 }
3916
3917 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source Counter Count Down Enable"]
3918 #[inline(always)]
3919 pub fn dscbral(
3920 self,
3921 ) -> crate::common::RegisterField<
3922 12,
3923 0x1,
3924 1,
3925 0,
3926 gtdnsr::Dscbral,
3927 gtdnsr::Dscbral,
3928 Gtdnsr_SPEC,
3929 crate::common::RW,
3930 > {
3931 crate::common::RegisterField::<
3932 12,
3933 0x1,
3934 1,
3935 0,
3936 gtdnsr::Dscbral,
3937 gtdnsr::Dscbral,
3938 Gtdnsr_SPEC,
3939 crate::common::RW,
3940 >::from_register(self, 0)
3941 }
3942
3943 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source Counter Count Down Enable"]
3944 #[inline(always)]
3945 pub fn dscbrah(
3946 self,
3947 ) -> crate::common::RegisterField<
3948 13,
3949 0x1,
3950 1,
3951 0,
3952 gtdnsr::Dscbrah,
3953 gtdnsr::Dscbrah,
3954 Gtdnsr_SPEC,
3955 crate::common::RW,
3956 > {
3957 crate::common::RegisterField::<
3958 13,
3959 0x1,
3960 1,
3961 0,
3962 gtdnsr::Dscbrah,
3963 gtdnsr::Dscbrah,
3964 Gtdnsr_SPEC,
3965 crate::common::RW,
3966 >::from_register(self, 0)
3967 }
3968
3969 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source Counter Count Down Enable"]
3970 #[inline(always)]
3971 pub fn dscbfal(
3972 self,
3973 ) -> crate::common::RegisterField<
3974 14,
3975 0x1,
3976 1,
3977 0,
3978 gtdnsr::Dscbfal,
3979 gtdnsr::Dscbfal,
3980 Gtdnsr_SPEC,
3981 crate::common::RW,
3982 > {
3983 crate::common::RegisterField::<
3984 14,
3985 0x1,
3986 1,
3987 0,
3988 gtdnsr::Dscbfal,
3989 gtdnsr::Dscbfal,
3990 Gtdnsr_SPEC,
3991 crate::common::RW,
3992 >::from_register(self, 0)
3993 }
3994
3995 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source Counter Count Down Enable"]
3996 #[inline(always)]
3997 pub fn dscbfah(
3998 self,
3999 ) -> crate::common::RegisterField<
4000 15,
4001 0x1,
4002 1,
4003 0,
4004 gtdnsr::Dscbfah,
4005 gtdnsr::Dscbfah,
4006 Gtdnsr_SPEC,
4007 crate::common::RW,
4008 > {
4009 crate::common::RegisterField::<
4010 15,
4011 0x1,
4012 1,
4013 0,
4014 gtdnsr::Dscbfah,
4015 gtdnsr::Dscbfah,
4016 Gtdnsr_SPEC,
4017 crate::common::RW,
4018 >::from_register(self, 0)
4019 }
4020
4021 #[doc = "ELC_GPTA Event Source Counter Count Down Enable"]
4022 #[inline(always)]
4023 pub fn dselca(
4024 self,
4025 ) -> crate::common::RegisterField<
4026 16,
4027 0x1,
4028 1,
4029 0,
4030 gtdnsr::Dselca,
4031 gtdnsr::Dselca,
4032 Gtdnsr_SPEC,
4033 crate::common::RW,
4034 > {
4035 crate::common::RegisterField::<
4036 16,
4037 0x1,
4038 1,
4039 0,
4040 gtdnsr::Dselca,
4041 gtdnsr::Dselca,
4042 Gtdnsr_SPEC,
4043 crate::common::RW,
4044 >::from_register(self, 0)
4045 }
4046
4047 #[doc = "ELC_GPTB Event Source Counter Count Down Enable"]
4048 #[inline(always)]
4049 pub fn dselcb(
4050 self,
4051 ) -> crate::common::RegisterField<
4052 17,
4053 0x1,
4054 1,
4055 0,
4056 gtdnsr::Dselcb,
4057 gtdnsr::Dselcb,
4058 Gtdnsr_SPEC,
4059 crate::common::RW,
4060 > {
4061 crate::common::RegisterField::<
4062 17,
4063 0x1,
4064 1,
4065 0,
4066 gtdnsr::Dselcb,
4067 gtdnsr::Dselcb,
4068 Gtdnsr_SPEC,
4069 crate::common::RW,
4070 >::from_register(self, 0)
4071 }
4072
4073 #[doc = "ELC_GPTC Event Source Counter Count Down Enable"]
4074 #[inline(always)]
4075 pub fn dselcc(
4076 self,
4077 ) -> crate::common::RegisterField<
4078 18,
4079 0x1,
4080 1,
4081 0,
4082 gtdnsr::Dselcc,
4083 gtdnsr::Dselcc,
4084 Gtdnsr_SPEC,
4085 crate::common::RW,
4086 > {
4087 crate::common::RegisterField::<
4088 18,
4089 0x1,
4090 1,
4091 0,
4092 gtdnsr::Dselcc,
4093 gtdnsr::Dselcc,
4094 Gtdnsr_SPEC,
4095 crate::common::RW,
4096 >::from_register(self, 0)
4097 }
4098
4099 #[doc = "ELC_GPTD Event Source Counter Count Down Enable"]
4100 #[inline(always)]
4101 pub fn dselcd(
4102 self,
4103 ) -> crate::common::RegisterField<
4104 19,
4105 0x1,
4106 1,
4107 0,
4108 gtdnsr::Dselcd,
4109 gtdnsr::Dselcd,
4110 Gtdnsr_SPEC,
4111 crate::common::RW,
4112 > {
4113 crate::common::RegisterField::<
4114 19,
4115 0x1,
4116 1,
4117 0,
4118 gtdnsr::Dselcd,
4119 gtdnsr::Dselcd,
4120 Gtdnsr_SPEC,
4121 crate::common::RW,
4122 >::from_register(self, 0)
4123 }
4124}
4125impl ::core::default::Default for Gtdnsr {
4126 #[inline(always)]
4127 fn default() -> Gtdnsr {
4128 <crate::RegValueT<Gtdnsr_SPEC> as RegisterValue<_>>::new(0)
4129 }
4130}
4131pub mod gtdnsr {
4132
4133 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4134 pub struct Dsgtrgar_SPEC;
4135 pub type Dsgtrgar = crate::EnumBitfieldStruct<u8, Dsgtrgar_SPEC>;
4136 impl Dsgtrgar {
4137 #[doc = "Counter count down disabled on the rising edge of GTETRGA input"]
4138 pub const _0: Self = Self::new(0);
4139
4140 #[doc = "Counter count down enabled on the rising edge of GTETRGA input"]
4141 pub const _1: Self = Self::new(1);
4142 }
4143 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4144 pub struct Dsgtrgaf_SPEC;
4145 pub type Dsgtrgaf = crate::EnumBitfieldStruct<u8, Dsgtrgaf_SPEC>;
4146 impl Dsgtrgaf {
4147 #[doc = "Counter count down disabled on the falling edge of GTETRGA input"]
4148 pub const _0: Self = Self::new(0);
4149
4150 #[doc = "Counter count down enabled on the falling edge of GTETRGA input"]
4151 pub const _1: Self = Self::new(1);
4152 }
4153 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4154 pub struct Dsgtrgbr_SPEC;
4155 pub type Dsgtrgbr = crate::EnumBitfieldStruct<u8, Dsgtrgbr_SPEC>;
4156 impl Dsgtrgbr {
4157 #[doc = "Counter count down disabled on the rising edge of GTETRGB input"]
4158 pub const _0: Self = Self::new(0);
4159
4160 #[doc = "Counter count down enabled on the rising edge of GTETRGB input"]
4161 pub const _1: Self = Self::new(1);
4162 }
4163 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4164 pub struct Dsgtrgbf_SPEC;
4165 pub type Dsgtrgbf = crate::EnumBitfieldStruct<u8, Dsgtrgbf_SPEC>;
4166 impl Dsgtrgbf {
4167 #[doc = "Counter count down disabled on the falling edge of GTETRGB input"]
4168 pub const _0: Self = Self::new(0);
4169
4170 #[doc = "Counter count down enabled on the falling edge of GTETRGB input"]
4171 pub const _1: Self = Self::new(1);
4172 }
4173 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4174 pub struct Dscarbl_SPEC;
4175 pub type Dscarbl = crate::EnumBitfieldStruct<u8, Dscarbl_SPEC>;
4176 impl Dscarbl {
4177 #[doc = "Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4178 pub const _0: Self = Self::new(0);
4179
4180 #[doc = "Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4181 pub const _1: Self = Self::new(1);
4182 }
4183 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4184 pub struct Dscarbh_SPEC;
4185 pub type Dscarbh = crate::EnumBitfieldStruct<u8, Dscarbh_SPEC>;
4186 impl Dscarbh {
4187 #[doc = "Counter count down disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4188 pub const _0: Self = Self::new(0);
4189
4190 #[doc = "Counter count down enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4191 pub const _1: Self = Self::new(1);
4192 }
4193 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4194 pub struct Dscafbl_SPEC;
4195 pub type Dscafbl = crate::EnumBitfieldStruct<u8, Dscafbl_SPEC>;
4196 impl Dscafbl {
4197 #[doc = "Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4198 pub const _0: Self = Self::new(0);
4199
4200 #[doc = "Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4201 pub const _1: Self = Self::new(1);
4202 }
4203 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4204 pub struct Dscafbh_SPEC;
4205 pub type Dscafbh = crate::EnumBitfieldStruct<u8, Dscafbh_SPEC>;
4206 impl Dscafbh {
4207 #[doc = "Counter count down disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4208 pub const _0: Self = Self::new(0);
4209
4210 #[doc = "Counter count down enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4211 pub const _1: Self = Self::new(1);
4212 }
4213 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4214 pub struct Dscbral_SPEC;
4215 pub type Dscbral = crate::EnumBitfieldStruct<u8, Dscbral_SPEC>;
4216 impl Dscbral {
4217 #[doc = "Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4218 pub const _0: Self = Self::new(0);
4219
4220 #[doc = "Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4221 pub const _1: Self = Self::new(1);
4222 }
4223 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4224 pub struct Dscbrah_SPEC;
4225 pub type Dscbrah = crate::EnumBitfieldStruct<u8, Dscbrah_SPEC>;
4226 impl Dscbrah {
4227 #[doc = "Counter count down disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4228 pub const _0: Self = Self::new(0);
4229
4230 #[doc = "Counter count down enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4231 pub const _1: Self = Self::new(1);
4232 }
4233 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4234 pub struct Dscbfal_SPEC;
4235 pub type Dscbfal = crate::EnumBitfieldStruct<u8, Dscbfal_SPEC>;
4236 impl Dscbfal {
4237 #[doc = "Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4238 pub const _0: Self = Self::new(0);
4239
4240 #[doc = "Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4241 pub const _1: Self = Self::new(1);
4242 }
4243 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4244 pub struct Dscbfah_SPEC;
4245 pub type Dscbfah = crate::EnumBitfieldStruct<u8, Dscbfah_SPEC>;
4246 impl Dscbfah {
4247 #[doc = "Counter count down disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4248 pub const _0: Self = Self::new(0);
4249
4250 #[doc = "Counter count down enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4251 pub const _1: Self = Self::new(1);
4252 }
4253 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4254 pub struct Dselca_SPEC;
4255 pub type Dselca = crate::EnumBitfieldStruct<u8, Dselca_SPEC>;
4256 impl Dselca {
4257 #[doc = "Counter count down disabled at the ELC_GPTA input"]
4258 pub const _0: Self = Self::new(0);
4259
4260 #[doc = "Counter count down enabled at the ELC_GPTA input"]
4261 pub const _1: Self = Self::new(1);
4262 }
4263 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4264 pub struct Dselcb_SPEC;
4265 pub type Dselcb = crate::EnumBitfieldStruct<u8, Dselcb_SPEC>;
4266 impl Dselcb {
4267 #[doc = "Counter count down disabled at the ELC_GPTB input"]
4268 pub const _0: Self = Self::new(0);
4269
4270 #[doc = "Counter count down enabled at the ELC_GPTB input"]
4271 pub const _1: Self = Self::new(1);
4272 }
4273 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4274 pub struct Dselcc_SPEC;
4275 pub type Dselcc = crate::EnumBitfieldStruct<u8, Dselcc_SPEC>;
4276 impl Dselcc {
4277 #[doc = "Counter count down disabled at the ELC_GPTC input"]
4278 pub const _0: Self = Self::new(0);
4279
4280 #[doc = "Counter count down enabled at the ELC_GPTC input"]
4281 pub const _1: Self = Self::new(1);
4282 }
4283 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4284 pub struct Dselcd_SPEC;
4285 pub type Dselcd = crate::EnumBitfieldStruct<u8, Dselcd_SPEC>;
4286 impl Dselcd {
4287 #[doc = "Counter count down disabled at the ELC_GPTD input"]
4288 pub const _0: Self = Self::new(0);
4289
4290 #[doc = "Counter count down enabled at the ELC_GPTD input"]
4291 pub const _1: Self = Self::new(1);
4292 }
4293}
4294#[doc(hidden)]
4295#[derive(Copy, Clone, Eq, PartialEq)]
4296pub struct Gticasr_SPEC;
4297impl crate::sealed::RegSpec for Gticasr_SPEC {
4298 type DataType = u32;
4299}
4300
4301#[doc = "General PWM Timer Input Capture Source Select Register A"]
4302pub type Gticasr = crate::RegValueT<Gticasr_SPEC>;
4303
4304impl Gticasr {
4305 #[doc = "GTETRGA Pin Rising Input Source GTCCRA Input Capture Enable"]
4306 #[inline(always)]
4307 pub fn asgtrgar(
4308 self,
4309 ) -> crate::common::RegisterField<
4310 0,
4311 0x1,
4312 1,
4313 0,
4314 gticasr::Asgtrgar,
4315 gticasr::Asgtrgar,
4316 Gticasr_SPEC,
4317 crate::common::RW,
4318 > {
4319 crate::common::RegisterField::<
4320 0,
4321 0x1,
4322 1,
4323 0,
4324 gticasr::Asgtrgar,
4325 gticasr::Asgtrgar,
4326 Gticasr_SPEC,
4327 crate::common::RW,
4328 >::from_register(self, 0)
4329 }
4330
4331 #[doc = "GTETRGA Pin Falling Input Source GTCCRA Input Capture Enable"]
4332 #[inline(always)]
4333 pub fn asgtrgaf(
4334 self,
4335 ) -> crate::common::RegisterField<
4336 1,
4337 0x1,
4338 1,
4339 0,
4340 gticasr::Asgtrgaf,
4341 gticasr::Asgtrgaf,
4342 Gticasr_SPEC,
4343 crate::common::RW,
4344 > {
4345 crate::common::RegisterField::<
4346 1,
4347 0x1,
4348 1,
4349 0,
4350 gticasr::Asgtrgaf,
4351 gticasr::Asgtrgaf,
4352 Gticasr_SPEC,
4353 crate::common::RW,
4354 >::from_register(self, 0)
4355 }
4356
4357 #[doc = "GTETRGB Pin Rising Input Source GTCCRA Input Capture Enable"]
4358 #[inline(always)]
4359 pub fn asgtrgbr(
4360 self,
4361 ) -> crate::common::RegisterField<
4362 2,
4363 0x1,
4364 1,
4365 0,
4366 gticasr::Asgtrgbr,
4367 gticasr::Asgtrgbr,
4368 Gticasr_SPEC,
4369 crate::common::RW,
4370 > {
4371 crate::common::RegisterField::<
4372 2,
4373 0x1,
4374 1,
4375 0,
4376 gticasr::Asgtrgbr,
4377 gticasr::Asgtrgbr,
4378 Gticasr_SPEC,
4379 crate::common::RW,
4380 >::from_register(self, 0)
4381 }
4382
4383 #[doc = "GTETRGB Pin Falling Input Source GTCCRA Input Capture Enable"]
4384 #[inline(always)]
4385 pub fn asgtrgbf(
4386 self,
4387 ) -> crate::common::RegisterField<
4388 3,
4389 0x1,
4390 1,
4391 0,
4392 gticasr::Asgtrgbf,
4393 gticasr::Asgtrgbf,
4394 Gticasr_SPEC,
4395 crate::common::RW,
4396 > {
4397 crate::common::RegisterField::<
4398 3,
4399 0x1,
4400 1,
4401 0,
4402 gticasr::Asgtrgbf,
4403 gticasr::Asgtrgbf,
4404 Gticasr_SPEC,
4405 crate::common::RW,
4406 >::from_register(self, 0)
4407 }
4408
4409 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable"]
4410 #[inline(always)]
4411 pub fn ascarbl(
4412 self,
4413 ) -> crate::common::RegisterField<
4414 8,
4415 0x1,
4416 1,
4417 0,
4418 gticasr::Ascarbl,
4419 gticasr::Ascarbl,
4420 Gticasr_SPEC,
4421 crate::common::RW,
4422 > {
4423 crate::common::RegisterField::<
4424 8,
4425 0x1,
4426 1,
4427 0,
4428 gticasr::Ascarbl,
4429 gticasr::Ascarbl,
4430 Gticasr_SPEC,
4431 crate::common::RW,
4432 >::from_register(self, 0)
4433 }
4434
4435 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRA Input Capture Enable"]
4436 #[inline(always)]
4437 pub fn ascarbh(
4438 self,
4439 ) -> crate::common::RegisterField<
4440 9,
4441 0x1,
4442 1,
4443 0,
4444 gticasr::Ascarbh,
4445 gticasr::Ascarbh,
4446 Gticasr_SPEC,
4447 crate::common::RW,
4448 > {
4449 crate::common::RegisterField::<
4450 9,
4451 0x1,
4452 1,
4453 0,
4454 gticasr::Ascarbh,
4455 gticasr::Ascarbh,
4456 Gticasr_SPEC,
4457 crate::common::RW,
4458 >::from_register(self, 0)
4459 }
4460
4461 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRA Input Capture Enable"]
4462 #[inline(always)]
4463 pub fn ascafbl(
4464 self,
4465 ) -> crate::common::RegisterField<
4466 10,
4467 0x1,
4468 1,
4469 0,
4470 gticasr::Ascafbl,
4471 gticasr::Ascafbl,
4472 Gticasr_SPEC,
4473 crate::common::RW,
4474 > {
4475 crate::common::RegisterField::<
4476 10,
4477 0x1,
4478 1,
4479 0,
4480 gticasr::Ascafbl,
4481 gticasr::Ascafbl,
4482 Gticasr_SPEC,
4483 crate::common::RW,
4484 >::from_register(self, 0)
4485 }
4486
4487 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRA Input Capture Enable"]
4488 #[inline(always)]
4489 pub fn ascafbh(
4490 self,
4491 ) -> crate::common::RegisterField<
4492 11,
4493 0x1,
4494 1,
4495 0,
4496 gticasr::Ascafbh,
4497 gticasr::Ascafbh,
4498 Gticasr_SPEC,
4499 crate::common::RW,
4500 > {
4501 crate::common::RegisterField::<
4502 11,
4503 0x1,
4504 1,
4505 0,
4506 gticasr::Ascafbh,
4507 gticasr::Ascafbh,
4508 Gticasr_SPEC,
4509 crate::common::RW,
4510 >::from_register(self, 0)
4511 }
4512
4513 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable"]
4514 #[inline(always)]
4515 pub fn ascbral(
4516 self,
4517 ) -> crate::common::RegisterField<
4518 12,
4519 0x1,
4520 1,
4521 0,
4522 gticasr::Ascbral,
4523 gticasr::Ascbral,
4524 Gticasr_SPEC,
4525 crate::common::RW,
4526 > {
4527 crate::common::RegisterField::<
4528 12,
4529 0x1,
4530 1,
4531 0,
4532 gticasr::Ascbral,
4533 gticasr::Ascbral,
4534 Gticasr_SPEC,
4535 crate::common::RW,
4536 >::from_register(self, 0)
4537 }
4538
4539 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRA Input Capture Enable"]
4540 #[inline(always)]
4541 pub fn ascbrah(
4542 self,
4543 ) -> crate::common::RegisterField<
4544 13,
4545 0x1,
4546 1,
4547 0,
4548 gticasr::Ascbrah,
4549 gticasr::Ascbrah,
4550 Gticasr_SPEC,
4551 crate::common::RW,
4552 > {
4553 crate::common::RegisterField::<
4554 13,
4555 0x1,
4556 1,
4557 0,
4558 gticasr::Ascbrah,
4559 gticasr::Ascbrah,
4560 Gticasr_SPEC,
4561 crate::common::RW,
4562 >::from_register(self, 0)
4563 }
4564
4565 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRA Input Capture Enable"]
4566 #[inline(always)]
4567 pub fn ascbfal(
4568 self,
4569 ) -> crate::common::RegisterField<
4570 14,
4571 0x1,
4572 1,
4573 0,
4574 gticasr::Ascbfal,
4575 gticasr::Ascbfal,
4576 Gticasr_SPEC,
4577 crate::common::RW,
4578 > {
4579 crate::common::RegisterField::<
4580 14,
4581 0x1,
4582 1,
4583 0,
4584 gticasr::Ascbfal,
4585 gticasr::Ascbfal,
4586 Gticasr_SPEC,
4587 crate::common::RW,
4588 >::from_register(self, 0)
4589 }
4590
4591 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRA Input Capture Enable"]
4592 #[inline(always)]
4593 pub fn ascbfah(
4594 self,
4595 ) -> crate::common::RegisterField<
4596 15,
4597 0x1,
4598 1,
4599 0,
4600 gticasr::Ascbfah,
4601 gticasr::Ascbfah,
4602 Gticasr_SPEC,
4603 crate::common::RW,
4604 > {
4605 crate::common::RegisterField::<
4606 15,
4607 0x1,
4608 1,
4609 0,
4610 gticasr::Ascbfah,
4611 gticasr::Ascbfah,
4612 Gticasr_SPEC,
4613 crate::common::RW,
4614 >::from_register(self, 0)
4615 }
4616
4617 #[doc = "ELC_GPTA Event Source GTCCRA Input Capture Enable"]
4618 #[inline(always)]
4619 pub fn aselca(
4620 self,
4621 ) -> crate::common::RegisterField<
4622 16,
4623 0x1,
4624 1,
4625 0,
4626 gticasr::Aselca,
4627 gticasr::Aselca,
4628 Gticasr_SPEC,
4629 crate::common::RW,
4630 > {
4631 crate::common::RegisterField::<
4632 16,
4633 0x1,
4634 1,
4635 0,
4636 gticasr::Aselca,
4637 gticasr::Aselca,
4638 Gticasr_SPEC,
4639 crate::common::RW,
4640 >::from_register(self, 0)
4641 }
4642
4643 #[doc = "ELC_GPTB Event Source GTCCRA Input Capture Enable"]
4644 #[inline(always)]
4645 pub fn aselcb(
4646 self,
4647 ) -> crate::common::RegisterField<
4648 17,
4649 0x1,
4650 1,
4651 0,
4652 gticasr::Aselcb,
4653 gticasr::Aselcb,
4654 Gticasr_SPEC,
4655 crate::common::RW,
4656 > {
4657 crate::common::RegisterField::<
4658 17,
4659 0x1,
4660 1,
4661 0,
4662 gticasr::Aselcb,
4663 gticasr::Aselcb,
4664 Gticasr_SPEC,
4665 crate::common::RW,
4666 >::from_register(self, 0)
4667 }
4668
4669 #[doc = "ELC_GPTC Event Source GTCCRA Input Capture Enable"]
4670 #[inline(always)]
4671 pub fn aselcc(
4672 self,
4673 ) -> crate::common::RegisterField<
4674 18,
4675 0x1,
4676 1,
4677 0,
4678 gticasr::Aselcc,
4679 gticasr::Aselcc,
4680 Gticasr_SPEC,
4681 crate::common::RW,
4682 > {
4683 crate::common::RegisterField::<
4684 18,
4685 0x1,
4686 1,
4687 0,
4688 gticasr::Aselcc,
4689 gticasr::Aselcc,
4690 Gticasr_SPEC,
4691 crate::common::RW,
4692 >::from_register(self, 0)
4693 }
4694
4695 #[doc = "ELC_GPTD Event Source GTCCRA Input Capture Enable"]
4696 #[inline(always)]
4697 pub fn aselcd(
4698 self,
4699 ) -> crate::common::RegisterField<
4700 19,
4701 0x1,
4702 1,
4703 0,
4704 gticasr::Aselcd,
4705 gticasr::Aselcd,
4706 Gticasr_SPEC,
4707 crate::common::RW,
4708 > {
4709 crate::common::RegisterField::<
4710 19,
4711 0x1,
4712 1,
4713 0,
4714 gticasr::Aselcd,
4715 gticasr::Aselcd,
4716 Gticasr_SPEC,
4717 crate::common::RW,
4718 >::from_register(self, 0)
4719 }
4720}
4721impl ::core::default::Default for Gticasr {
4722 #[inline(always)]
4723 fn default() -> Gticasr {
4724 <crate::RegValueT<Gticasr_SPEC> as RegisterValue<_>>::new(0)
4725 }
4726}
4727pub mod gticasr {
4728
4729 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4730 pub struct Asgtrgar_SPEC;
4731 pub type Asgtrgar = crate::EnumBitfieldStruct<u8, Asgtrgar_SPEC>;
4732 impl Asgtrgar {
4733 #[doc = "GTCCRA input capture disabled on the rising edge of GTETRGA input"]
4734 pub const _0: Self = Self::new(0);
4735
4736 #[doc = "GTCCRA input capture enabled on the rising edge of GTETRGA input"]
4737 pub const _1: Self = Self::new(1);
4738 }
4739 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4740 pub struct Asgtrgaf_SPEC;
4741 pub type Asgtrgaf = crate::EnumBitfieldStruct<u8, Asgtrgaf_SPEC>;
4742 impl Asgtrgaf {
4743 #[doc = "GTCCRA input capture disabled on the falling edge of GTETRGA input"]
4744 pub const _0: Self = Self::new(0);
4745
4746 #[doc = "GTCCRA input capture enabled on the falling edge of GTETRGA input"]
4747 pub const _1: Self = Self::new(1);
4748 }
4749 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4750 pub struct Asgtrgbr_SPEC;
4751 pub type Asgtrgbr = crate::EnumBitfieldStruct<u8, Asgtrgbr_SPEC>;
4752 impl Asgtrgbr {
4753 #[doc = "GTCCRA input capture disabled on the rising edge of GTETRGB input"]
4754 pub const _0: Self = Self::new(0);
4755
4756 #[doc = "GTCCRA input capture enabled on the rising edge of GTETRGB input"]
4757 pub const _1: Self = Self::new(1);
4758 }
4759 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4760 pub struct Asgtrgbf_SPEC;
4761 pub type Asgtrgbf = crate::EnumBitfieldStruct<u8, Asgtrgbf_SPEC>;
4762 impl Asgtrgbf {
4763 #[doc = "GTCCRA input capture disabled on the falling edge of GTETRGB input"]
4764 pub const _0: Self = Self::new(0);
4765
4766 #[doc = "GTCCRA input capture enabled on the falling edge of GTETRGB input"]
4767 pub const _1: Self = Self::new(1);
4768 }
4769 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4770 pub struct Ascarbl_SPEC;
4771 pub type Ascarbl = crate::EnumBitfieldStruct<u8, Ascarbl_SPEC>;
4772 impl Ascarbl {
4773 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4774 pub const _0: Self = Self::new(0);
4775
4776 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
4777 pub const _1: Self = Self::new(1);
4778 }
4779 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4780 pub struct Ascarbh_SPEC;
4781 pub type Ascarbh = crate::EnumBitfieldStruct<u8, Ascarbh_SPEC>;
4782 impl Ascarbh {
4783 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4784 pub const _0: Self = Self::new(0);
4785
4786 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
4787 pub const _1: Self = Self::new(1);
4788 }
4789 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4790 pub struct Ascafbl_SPEC;
4791 pub type Ascafbl = crate::EnumBitfieldStruct<u8, Ascafbl_SPEC>;
4792 impl Ascafbl {
4793 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4794 pub const _0: Self = Self::new(0);
4795
4796 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
4797 pub const _1: Self = Self::new(1);
4798 }
4799 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4800 pub struct Ascafbh_SPEC;
4801 pub type Ascafbh = crate::EnumBitfieldStruct<u8, Ascafbh_SPEC>;
4802 impl Ascafbh {
4803 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4804 pub const _0: Self = Self::new(0);
4805
4806 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
4807 pub const _1: Self = Self::new(1);
4808 }
4809 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4810 pub struct Ascbral_SPEC;
4811 pub type Ascbral = crate::EnumBitfieldStruct<u8, Ascbral_SPEC>;
4812 impl Ascbral {
4813 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4814 pub const _0: Self = Self::new(0);
4815
4816 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
4817 pub const _1: Self = Self::new(1);
4818 }
4819 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4820 pub struct Ascbrah_SPEC;
4821 pub type Ascbrah = crate::EnumBitfieldStruct<u8, Ascbrah_SPEC>;
4822 impl Ascbrah {
4823 #[doc = "GTCCRA input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4824 pub const _0: Self = Self::new(0);
4825
4826 #[doc = "GTCCRA input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
4827 pub const _1: Self = Self::new(1);
4828 }
4829 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4830 pub struct Ascbfal_SPEC;
4831 pub type Ascbfal = crate::EnumBitfieldStruct<u8, Ascbfal_SPEC>;
4832 impl Ascbfal {
4833 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4834 pub const _0: Self = Self::new(0);
4835
4836 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
4837 pub const _1: Self = Self::new(1);
4838 }
4839 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4840 pub struct Ascbfah_SPEC;
4841 pub type Ascbfah = crate::EnumBitfieldStruct<u8, Ascbfah_SPEC>;
4842 impl Ascbfah {
4843 #[doc = "GTCCRA input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4844 pub const _0: Self = Self::new(0);
4845
4846 #[doc = "GTCCRA input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
4847 pub const _1: Self = Self::new(1);
4848 }
4849 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4850 pub struct Aselca_SPEC;
4851 pub type Aselca = crate::EnumBitfieldStruct<u8, Aselca_SPEC>;
4852 impl Aselca {
4853 #[doc = "GTCCRA input capture disabled at the ELC_GPTA input"]
4854 pub const _0: Self = Self::new(0);
4855
4856 #[doc = "GTCCRA input capture enabled at the ELC_GPTA input"]
4857 pub const _1: Self = Self::new(1);
4858 }
4859 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4860 pub struct Aselcb_SPEC;
4861 pub type Aselcb = crate::EnumBitfieldStruct<u8, Aselcb_SPEC>;
4862 impl Aselcb {
4863 #[doc = "GTCCRA input capture disabled at the ELC_GPTB input"]
4864 pub const _0: Self = Self::new(0);
4865
4866 #[doc = "GTCCRA input capture enabled at the ELC_GPTB input"]
4867 pub const _1: Self = Self::new(1);
4868 }
4869 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4870 pub struct Aselcc_SPEC;
4871 pub type Aselcc = crate::EnumBitfieldStruct<u8, Aselcc_SPEC>;
4872 impl Aselcc {
4873 #[doc = "GTCCRA input capture disabled at the ELC_GPTC input"]
4874 pub const _0: Self = Self::new(0);
4875
4876 #[doc = "GTCCRA input capture enabled at the ELC_GPTC input"]
4877 pub const _1: Self = Self::new(1);
4878 }
4879 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4880 pub struct Aselcd_SPEC;
4881 pub type Aselcd = crate::EnumBitfieldStruct<u8, Aselcd_SPEC>;
4882 impl Aselcd {
4883 #[doc = "GTCCRA input capture disabled at the ELC_GPTD input"]
4884 pub const _0: Self = Self::new(0);
4885
4886 #[doc = "GTCCRA input capture enabled at the ELC_GPTD input"]
4887 pub const _1: Self = Self::new(1);
4888 }
4889}
4890#[doc(hidden)]
4891#[derive(Copy, Clone, Eq, PartialEq)]
4892pub struct Gticbsr_SPEC;
4893impl crate::sealed::RegSpec for Gticbsr_SPEC {
4894 type DataType = u32;
4895}
4896
4897#[doc = "General PWM Timer Input Capture Source Select Register B"]
4898pub type Gticbsr = crate::RegValueT<Gticbsr_SPEC>;
4899
4900impl Gticbsr {
4901 #[doc = "GTETRGA Pin Rising Input Source GTCCRB Input Capture Enable"]
4902 #[inline(always)]
4903 pub fn bsgtrgar(
4904 self,
4905 ) -> crate::common::RegisterField<
4906 0,
4907 0x1,
4908 1,
4909 0,
4910 gticbsr::Bsgtrgar,
4911 gticbsr::Bsgtrgar,
4912 Gticbsr_SPEC,
4913 crate::common::RW,
4914 > {
4915 crate::common::RegisterField::<
4916 0,
4917 0x1,
4918 1,
4919 0,
4920 gticbsr::Bsgtrgar,
4921 gticbsr::Bsgtrgar,
4922 Gticbsr_SPEC,
4923 crate::common::RW,
4924 >::from_register(self, 0)
4925 }
4926
4927 #[doc = "GTETRGA Pin Falling Input Source GTCCRB Input Capture Enable"]
4928 #[inline(always)]
4929 pub fn bsgtrgaf(
4930 self,
4931 ) -> crate::common::RegisterField<
4932 1,
4933 0x1,
4934 1,
4935 0,
4936 gticbsr::Bsgtrgaf,
4937 gticbsr::Bsgtrgaf,
4938 Gticbsr_SPEC,
4939 crate::common::RW,
4940 > {
4941 crate::common::RegisterField::<
4942 1,
4943 0x1,
4944 1,
4945 0,
4946 gticbsr::Bsgtrgaf,
4947 gticbsr::Bsgtrgaf,
4948 Gticbsr_SPEC,
4949 crate::common::RW,
4950 >::from_register(self, 0)
4951 }
4952
4953 #[doc = "GTETRGB Pin Rising Input Source GTCCRB Input Capture Enable"]
4954 #[inline(always)]
4955 pub fn bsgtrgbr(
4956 self,
4957 ) -> crate::common::RegisterField<
4958 2,
4959 0x1,
4960 1,
4961 0,
4962 gticbsr::Bsgtrgbr,
4963 gticbsr::Bsgtrgbr,
4964 Gticbsr_SPEC,
4965 crate::common::RW,
4966 > {
4967 crate::common::RegisterField::<
4968 2,
4969 0x1,
4970 1,
4971 0,
4972 gticbsr::Bsgtrgbr,
4973 gticbsr::Bsgtrgbr,
4974 Gticbsr_SPEC,
4975 crate::common::RW,
4976 >::from_register(self, 0)
4977 }
4978
4979 #[doc = "GTETRGB Pin Falling Input Source GTCCRB Input Capture Enable"]
4980 #[inline(always)]
4981 pub fn bsgtrgbf(
4982 self,
4983 ) -> crate::common::RegisterField<
4984 3,
4985 0x1,
4986 1,
4987 0,
4988 gticbsr::Bsgtrgbf,
4989 gticbsr::Bsgtrgbf,
4990 Gticbsr_SPEC,
4991 crate::common::RW,
4992 > {
4993 crate::common::RegisterField::<
4994 3,
4995 0x1,
4996 1,
4997 0,
4998 gticbsr::Bsgtrgbf,
4999 gticbsr::Bsgtrgbf,
5000 Gticbsr_SPEC,
5001 crate::common::RW,
5002 >::from_register(self, 0)
5003 }
5004
5005 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable"]
5006 #[inline(always)]
5007 pub fn bscarbl(
5008 self,
5009 ) -> crate::common::RegisterField<
5010 8,
5011 0x1,
5012 1,
5013 0,
5014 gticbsr::Bscarbl,
5015 gticbsr::Bscarbl,
5016 Gticbsr_SPEC,
5017 crate::common::RW,
5018 > {
5019 crate::common::RegisterField::<
5020 8,
5021 0x1,
5022 1,
5023 0,
5024 gticbsr::Bscarbl,
5025 gticbsr::Bscarbl,
5026 Gticbsr_SPEC,
5027 crate::common::RW,
5028 >::from_register(self, 0)
5029 }
5030
5031 #[doc = "GTIOCnA Pin Rising Input during GTIOCnB Value High Source GTCCRB Input Capture Enable"]
5032 #[inline(always)]
5033 pub fn bscarbh(
5034 self,
5035 ) -> crate::common::RegisterField<
5036 9,
5037 0x1,
5038 1,
5039 0,
5040 gticbsr::Bscarbh,
5041 gticbsr::Bscarbh,
5042 Gticbsr_SPEC,
5043 crate::common::RW,
5044 > {
5045 crate::common::RegisterField::<
5046 9,
5047 0x1,
5048 1,
5049 0,
5050 gticbsr::Bscarbh,
5051 gticbsr::Bscarbh,
5052 Gticbsr_SPEC,
5053 crate::common::RW,
5054 >::from_register(self, 0)
5055 }
5056
5057 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value Low Source GTCCRB Input Capture Enable"]
5058 #[inline(always)]
5059 pub fn bscafbl(
5060 self,
5061 ) -> crate::common::RegisterField<
5062 10,
5063 0x1,
5064 1,
5065 0,
5066 gticbsr::Bscafbl,
5067 gticbsr::Bscafbl,
5068 Gticbsr_SPEC,
5069 crate::common::RW,
5070 > {
5071 crate::common::RegisterField::<
5072 10,
5073 0x1,
5074 1,
5075 0,
5076 gticbsr::Bscafbl,
5077 gticbsr::Bscafbl,
5078 Gticbsr_SPEC,
5079 crate::common::RW,
5080 >::from_register(self, 0)
5081 }
5082
5083 #[doc = "GTIOCnA Pin Falling Input during GTIOCnB Value High Source GTCCRB Input Capture Enable"]
5084 #[inline(always)]
5085 pub fn bscafbh(
5086 self,
5087 ) -> crate::common::RegisterField<
5088 11,
5089 0x1,
5090 1,
5091 0,
5092 gticbsr::Bscafbh,
5093 gticbsr::Bscafbh,
5094 Gticbsr_SPEC,
5095 crate::common::RW,
5096 > {
5097 crate::common::RegisterField::<
5098 11,
5099 0x1,
5100 1,
5101 0,
5102 gticbsr::Bscafbh,
5103 gticbsr::Bscafbh,
5104 Gticbsr_SPEC,
5105 crate::common::RW,
5106 >::from_register(self, 0)
5107 }
5108
5109 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable"]
5110 #[inline(always)]
5111 pub fn bscbral(
5112 self,
5113 ) -> crate::common::RegisterField<
5114 12,
5115 0x1,
5116 1,
5117 0,
5118 gticbsr::Bscbral,
5119 gticbsr::Bscbral,
5120 Gticbsr_SPEC,
5121 crate::common::RW,
5122 > {
5123 crate::common::RegisterField::<
5124 12,
5125 0x1,
5126 1,
5127 0,
5128 gticbsr::Bscbral,
5129 gticbsr::Bscbral,
5130 Gticbsr_SPEC,
5131 crate::common::RW,
5132 >::from_register(self, 0)
5133 }
5134
5135 #[doc = "GTIOCnB Pin Rising Input during GTIOCnA Value High Source GTCCRB Input Capture Enable"]
5136 #[inline(always)]
5137 pub fn bscbrah(
5138 self,
5139 ) -> crate::common::RegisterField<
5140 13,
5141 0x1,
5142 1,
5143 0,
5144 gticbsr::Bscbrah,
5145 gticbsr::Bscbrah,
5146 Gticbsr_SPEC,
5147 crate::common::RW,
5148 > {
5149 crate::common::RegisterField::<
5150 13,
5151 0x1,
5152 1,
5153 0,
5154 gticbsr::Bscbrah,
5155 gticbsr::Bscbrah,
5156 Gticbsr_SPEC,
5157 crate::common::RW,
5158 >::from_register(self, 0)
5159 }
5160
5161 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value Low Source GTCCRB Input Capture Enable"]
5162 #[inline(always)]
5163 pub fn bscbfal(
5164 self,
5165 ) -> crate::common::RegisterField<
5166 14,
5167 0x1,
5168 1,
5169 0,
5170 gticbsr::Bscbfal,
5171 gticbsr::Bscbfal,
5172 Gticbsr_SPEC,
5173 crate::common::RW,
5174 > {
5175 crate::common::RegisterField::<
5176 14,
5177 0x1,
5178 1,
5179 0,
5180 gticbsr::Bscbfal,
5181 gticbsr::Bscbfal,
5182 Gticbsr_SPEC,
5183 crate::common::RW,
5184 >::from_register(self, 0)
5185 }
5186
5187 #[doc = "GTIOCnB Pin Falling Input during GTIOCnA Value High Source GTCCRB Input Capture Enable"]
5188 #[inline(always)]
5189 pub fn bscbfah(
5190 self,
5191 ) -> crate::common::RegisterField<
5192 15,
5193 0x1,
5194 1,
5195 0,
5196 gticbsr::Bscbfah,
5197 gticbsr::Bscbfah,
5198 Gticbsr_SPEC,
5199 crate::common::RW,
5200 > {
5201 crate::common::RegisterField::<
5202 15,
5203 0x1,
5204 1,
5205 0,
5206 gticbsr::Bscbfah,
5207 gticbsr::Bscbfah,
5208 Gticbsr_SPEC,
5209 crate::common::RW,
5210 >::from_register(self, 0)
5211 }
5212
5213 #[doc = "ELC_GPTA Event Source GTCCRB Input Capture Enable"]
5214 #[inline(always)]
5215 pub fn bselca(
5216 self,
5217 ) -> crate::common::RegisterField<
5218 16,
5219 0x1,
5220 1,
5221 0,
5222 gticbsr::Bselca,
5223 gticbsr::Bselca,
5224 Gticbsr_SPEC,
5225 crate::common::RW,
5226 > {
5227 crate::common::RegisterField::<
5228 16,
5229 0x1,
5230 1,
5231 0,
5232 gticbsr::Bselca,
5233 gticbsr::Bselca,
5234 Gticbsr_SPEC,
5235 crate::common::RW,
5236 >::from_register(self, 0)
5237 }
5238
5239 #[doc = "ELC_GPTB Event Source GTCCRB Input Capture Enable"]
5240 #[inline(always)]
5241 pub fn bselcb(
5242 self,
5243 ) -> crate::common::RegisterField<
5244 17,
5245 0x1,
5246 1,
5247 0,
5248 gticbsr::Bselcb,
5249 gticbsr::Bselcb,
5250 Gticbsr_SPEC,
5251 crate::common::RW,
5252 > {
5253 crate::common::RegisterField::<
5254 17,
5255 0x1,
5256 1,
5257 0,
5258 gticbsr::Bselcb,
5259 gticbsr::Bselcb,
5260 Gticbsr_SPEC,
5261 crate::common::RW,
5262 >::from_register(self, 0)
5263 }
5264
5265 #[doc = "ELC_GPTC Event Source GTCCRB Input Capture Enable"]
5266 #[inline(always)]
5267 pub fn bselcc(
5268 self,
5269 ) -> crate::common::RegisterField<
5270 18,
5271 0x1,
5272 1,
5273 0,
5274 gticbsr::Bselcc,
5275 gticbsr::Bselcc,
5276 Gticbsr_SPEC,
5277 crate::common::RW,
5278 > {
5279 crate::common::RegisterField::<
5280 18,
5281 0x1,
5282 1,
5283 0,
5284 gticbsr::Bselcc,
5285 gticbsr::Bselcc,
5286 Gticbsr_SPEC,
5287 crate::common::RW,
5288 >::from_register(self, 0)
5289 }
5290
5291 #[doc = "ELC_GPTD Event Source GTCCRB Input Capture Enable"]
5292 #[inline(always)]
5293 pub fn bselcd(
5294 self,
5295 ) -> crate::common::RegisterField<
5296 19,
5297 0x1,
5298 1,
5299 0,
5300 gticbsr::Bselcd,
5301 gticbsr::Bselcd,
5302 Gticbsr_SPEC,
5303 crate::common::RW,
5304 > {
5305 crate::common::RegisterField::<
5306 19,
5307 0x1,
5308 1,
5309 0,
5310 gticbsr::Bselcd,
5311 gticbsr::Bselcd,
5312 Gticbsr_SPEC,
5313 crate::common::RW,
5314 >::from_register(self, 0)
5315 }
5316}
5317impl ::core::default::Default for Gticbsr {
5318 #[inline(always)]
5319 fn default() -> Gticbsr {
5320 <crate::RegValueT<Gticbsr_SPEC> as RegisterValue<_>>::new(0)
5321 }
5322}
5323pub mod gticbsr {
5324
5325 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5326 pub struct Bsgtrgar_SPEC;
5327 pub type Bsgtrgar = crate::EnumBitfieldStruct<u8, Bsgtrgar_SPEC>;
5328 impl Bsgtrgar {
5329 #[doc = "GTCCRB input capture disabled on the rising edge of GTETRGA input"]
5330 pub const _0: Self = Self::new(0);
5331
5332 #[doc = "GTCCRB input capture enabled on the rising edge of GTETRGA input"]
5333 pub const _1: Self = Self::new(1);
5334 }
5335 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5336 pub struct Bsgtrgaf_SPEC;
5337 pub type Bsgtrgaf = crate::EnumBitfieldStruct<u8, Bsgtrgaf_SPEC>;
5338 impl Bsgtrgaf {
5339 #[doc = "GTCCRB input capture disabled on the falling edge of GTETRGA input"]
5340 pub const _0: Self = Self::new(0);
5341
5342 #[doc = "GTCCRB input capture enabled on the falling edge of GTETRGA input"]
5343 pub const _1: Self = Self::new(1);
5344 }
5345 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5346 pub struct Bsgtrgbr_SPEC;
5347 pub type Bsgtrgbr = crate::EnumBitfieldStruct<u8, Bsgtrgbr_SPEC>;
5348 impl Bsgtrgbr {
5349 #[doc = "GTCCRB input capture disabled on the rising edge of GTETRGB input"]
5350 pub const _0: Self = Self::new(0);
5351
5352 #[doc = "GTCCRB input capture enabled on the rising edge of GTETRGB input"]
5353 pub const _1: Self = Self::new(1);
5354 }
5355 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5356 pub struct Bsgtrgbf_SPEC;
5357 pub type Bsgtrgbf = crate::EnumBitfieldStruct<u8, Bsgtrgbf_SPEC>;
5358 impl Bsgtrgbf {
5359 #[doc = "GTCCRB input capture disabled on the falling edge of GTETRGB input"]
5360 pub const _0: Self = Self::new(0);
5361
5362 #[doc = "GTCCRB input capture enabled on the falling edge of GTETRGB input"]
5363 pub const _1: Self = Self::new(1);
5364 }
5365 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5366 pub struct Bscarbl_SPEC;
5367 pub type Bscarbl = crate::EnumBitfieldStruct<u8, Bscarbl_SPEC>;
5368 impl Bscarbl {
5369 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
5370 pub const _0: Self = Self::new(0);
5371
5372 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 0"]
5373 pub const _1: Self = Self::new(1);
5374 }
5375 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5376 pub struct Bscarbh_SPEC;
5377 pub type Bscarbh = crate::EnumBitfieldStruct<u8, Bscarbh_SPEC>;
5378 impl Bscarbh {
5379 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
5380 pub const _0: Self = Self::new(0);
5381
5382 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnA input when GTIOCnB input is 1"]
5383 pub const _1: Self = Self::new(1);
5384 }
5385 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5386 pub struct Bscafbl_SPEC;
5387 pub type Bscafbl = crate::EnumBitfieldStruct<u8, Bscafbl_SPEC>;
5388 impl Bscafbl {
5389 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
5390 pub const _0: Self = Self::new(0);
5391
5392 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 0"]
5393 pub const _1: Self = Self::new(1);
5394 }
5395 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5396 pub struct Bscafbh_SPEC;
5397 pub type Bscafbh = crate::EnumBitfieldStruct<u8, Bscafbh_SPEC>;
5398 impl Bscafbh {
5399 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
5400 pub const _0: Self = Self::new(0);
5401
5402 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnA input when GTIOCnB input is 1"]
5403 pub const _1: Self = Self::new(1);
5404 }
5405 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5406 pub struct Bscbral_SPEC;
5407 pub type Bscbral = crate::EnumBitfieldStruct<u8, Bscbral_SPEC>;
5408 impl Bscbral {
5409 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
5410 pub const _0: Self = Self::new(0);
5411
5412 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 0"]
5413 pub const _1: Self = Self::new(1);
5414 }
5415 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5416 pub struct Bscbrah_SPEC;
5417 pub type Bscbrah = crate::EnumBitfieldStruct<u8, Bscbrah_SPEC>;
5418 impl Bscbrah {
5419 #[doc = "GTCCRB input capture disabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
5420 pub const _0: Self = Self::new(0);
5421
5422 #[doc = "GTCCRB input capture enabled on the rising edge of GTIOCnB input when GTIOCnA input is 1"]
5423 pub const _1: Self = Self::new(1);
5424 }
5425 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5426 pub struct Bscbfal_SPEC;
5427 pub type Bscbfal = crate::EnumBitfieldStruct<u8, Bscbfal_SPEC>;
5428 impl Bscbfal {
5429 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
5430 pub const _0: Self = Self::new(0);
5431
5432 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 0"]
5433 pub const _1: Self = Self::new(1);
5434 }
5435 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5436 pub struct Bscbfah_SPEC;
5437 pub type Bscbfah = crate::EnumBitfieldStruct<u8, Bscbfah_SPEC>;
5438 impl Bscbfah {
5439 #[doc = "GTCCRB input capture disabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
5440 pub const _0: Self = Self::new(0);
5441
5442 #[doc = "GTCCRB input capture enabled on the falling edge of GTIOCnB input when GTIOCnA input is 1"]
5443 pub const _1: Self = Self::new(1);
5444 }
5445 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5446 pub struct Bselca_SPEC;
5447 pub type Bselca = crate::EnumBitfieldStruct<u8, Bselca_SPEC>;
5448 impl Bselca {
5449 #[doc = "GTCCRB input capture disabled at the ELC_GPTA input"]
5450 pub const _0: Self = Self::new(0);
5451
5452 #[doc = "GTCCRB input capture enabled at the ELC_GPTA input"]
5453 pub const _1: Self = Self::new(1);
5454 }
5455 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5456 pub struct Bselcb_SPEC;
5457 pub type Bselcb = crate::EnumBitfieldStruct<u8, Bselcb_SPEC>;
5458 impl Bselcb {
5459 #[doc = "GTCCRB input capture disabled at the ELC_GPTB input"]
5460 pub const _0: Self = Self::new(0);
5461
5462 #[doc = "GTCCRB input capture enabled at the ELC_GPTB input"]
5463 pub const _1: Self = Self::new(1);
5464 }
5465 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5466 pub struct Bselcc_SPEC;
5467 pub type Bselcc = crate::EnumBitfieldStruct<u8, Bselcc_SPEC>;
5468 impl Bselcc {
5469 #[doc = "GTCCRB input capture disabled at the ELC_GPTC input"]
5470 pub const _0: Self = Self::new(0);
5471
5472 #[doc = "GTCCRB input capture enabled at the ELC_GPTC input"]
5473 pub const _1: Self = Self::new(1);
5474 }
5475 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5476 pub struct Bselcd_SPEC;
5477 pub type Bselcd = crate::EnumBitfieldStruct<u8, Bselcd_SPEC>;
5478 impl Bselcd {
5479 #[doc = "GTCCRB input capture disabled at the ELC_GPTD input"]
5480 pub const _0: Self = Self::new(0);
5481
5482 #[doc = "GTCCRB input capture enabled at the ELC_GPTD input"]
5483 pub const _1: Self = Self::new(1);
5484 }
5485}
5486#[doc(hidden)]
5487#[derive(Copy, Clone, Eq, PartialEq)]
5488pub struct Gtcr_SPEC;
5489impl crate::sealed::RegSpec for Gtcr_SPEC {
5490 type DataType = u32;
5491}
5492
5493#[doc = "General PWM Timer Control Register"]
5494pub type Gtcr = crate::RegValueT<Gtcr_SPEC>;
5495
5496impl Gtcr {
5497 #[doc = "Count Start"]
5498 #[inline(always)]
5499 pub fn cst(
5500 self,
5501 ) -> crate::common::RegisterField<
5502 0,
5503 0x1,
5504 1,
5505 0,
5506 gtcr::Cst,
5507 gtcr::Cst,
5508 Gtcr_SPEC,
5509 crate::common::RW,
5510 > {
5511 crate::common::RegisterField::<
5512 0,
5513 0x1,
5514 1,
5515 0,
5516 gtcr::Cst,
5517 gtcr::Cst,
5518 Gtcr_SPEC,
5519 crate::common::RW,
5520 >::from_register(self, 0)
5521 }
5522
5523 #[doc = "Mode Select"]
5524 #[inline(always)]
5525 pub fn md(
5526 self,
5527 ) -> crate::common::RegisterField<16, 0x7, 1, 0, gtcr::Md, gtcr::Md, Gtcr_SPEC, crate::common::RW>
5528 {
5529 crate::common::RegisterField::<
5530 16,
5531 0x7,
5532 1,
5533 0,
5534 gtcr::Md,
5535 gtcr::Md,
5536 Gtcr_SPEC,
5537 crate::common::RW,
5538 >::from_register(self, 0)
5539 }
5540
5541 #[doc = "Timer Prescaler Select"]
5542 #[inline(always)]
5543 pub fn tpcs(
5544 self,
5545 ) -> crate::common::RegisterField<
5546 24,
5547 0x7,
5548 1,
5549 0,
5550 gtcr::Tpcs,
5551 gtcr::Tpcs,
5552 Gtcr_SPEC,
5553 crate::common::RW,
5554 > {
5555 crate::common::RegisterField::<
5556 24,
5557 0x7,
5558 1,
5559 0,
5560 gtcr::Tpcs,
5561 gtcr::Tpcs,
5562 Gtcr_SPEC,
5563 crate::common::RW,
5564 >::from_register(self, 0)
5565 }
5566}
5567impl ::core::default::Default for Gtcr {
5568 #[inline(always)]
5569 fn default() -> Gtcr {
5570 <crate::RegValueT<Gtcr_SPEC> as RegisterValue<_>>::new(0)
5571 }
5572}
5573pub mod gtcr {
5574
5575 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5576 pub struct Cst_SPEC;
5577 pub type Cst = crate::EnumBitfieldStruct<u8, Cst_SPEC>;
5578 impl Cst {
5579 #[doc = "Count operation is stopped"]
5580 pub const _0: Self = Self::new(0);
5581
5582 #[doc = "Count operation is performed"]
5583 pub const _1: Self = Self::new(1);
5584 }
5585 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5586 pub struct Md_SPEC;
5587 pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
5588 impl Md {
5589 #[doc = "Saw-wave PWM mode (single buffer or double buffer possible)"]
5590 pub const _000: Self = Self::new(0);
5591
5592 #[doc = "Saw-wave one-shot pulse mode (fixed buffer operation)"]
5593 pub const _001: Self = Self::new(1);
5594
5595 #[doc = "Setting prohibited"]
5596 pub const _010: Self = Self::new(2);
5597
5598 #[doc = "Setting prohibited"]
5599 pub const _011: Self = Self::new(3);
5600
5601 #[doc = "Triangle-wave PWM mode 1 (32-bit transfer at trough) (single buffer or double buffer is possible)"]
5602 pub const _100: Self = Self::new(4);
5603
5604 #[doc = "Triangle-wave PWM mode 2 (32-bit transfer at crest and trough) (single buffer or double buffer is possible)"]
5605 pub const _101: Self = Self::new(5);
5606
5607 #[doc = "Triangle-wave PWM mode 3 (64-bit transfer at trough) (fixed buffer operation)"]
5608 pub const _110: Self = Self::new(6);
5609
5610 #[doc = "Setting prohibited"]
5611 pub const _111: Self = Self::new(7);
5612 }
5613 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5614 pub struct Tpcs_SPEC;
5615 pub type Tpcs = crate::EnumBitfieldStruct<u8, Tpcs_SPEC>;
5616 impl Tpcs {
5617 #[doc = "PCLKD/1"]
5618 pub const _000: Self = Self::new(0);
5619
5620 #[doc = "PCLKD/4"]
5621 pub const _001: Self = Self::new(1);
5622
5623 #[doc = "PCLKD/16"]
5624 pub const _010: Self = Self::new(2);
5625
5626 #[doc = "PCLKD/64"]
5627 pub const _011: Self = Self::new(3);
5628
5629 #[doc = "PCLKD/256"]
5630 pub const _100: Self = Self::new(4);
5631
5632 #[doc = "PCLKD/1024"]
5633 pub const _101: Self = Self::new(5);
5634 }
5635}
5636#[doc(hidden)]
5637#[derive(Copy, Clone, Eq, PartialEq)]
5638pub struct Gtuddtyc_SPEC;
5639impl crate::sealed::RegSpec for Gtuddtyc_SPEC {
5640 type DataType = u32;
5641}
5642
5643#[doc = "General PWM Timer Count Direction and Duty Setting Register"]
5644pub type Gtuddtyc = crate::RegValueT<Gtuddtyc_SPEC>;
5645
5646impl Gtuddtyc {
5647 #[doc = "Count Direction Setting"]
5648 #[inline(always)]
5649 pub fn ud(
5650 self,
5651 ) -> crate::common::RegisterField<
5652 0,
5653 0x1,
5654 1,
5655 0,
5656 gtuddtyc::Ud,
5657 gtuddtyc::Ud,
5658 Gtuddtyc_SPEC,
5659 crate::common::RW,
5660 > {
5661 crate::common::RegisterField::<
5662 0,
5663 0x1,
5664 1,
5665 0,
5666 gtuddtyc::Ud,
5667 gtuddtyc::Ud,
5668 Gtuddtyc_SPEC,
5669 crate::common::RW,
5670 >::from_register(self, 0)
5671 }
5672
5673 #[doc = "Forcible Count Direction Setting"]
5674 #[inline(always)]
5675 pub fn udf(
5676 self,
5677 ) -> crate::common::RegisterField<
5678 1,
5679 0x1,
5680 1,
5681 0,
5682 gtuddtyc::Udf,
5683 gtuddtyc::Udf,
5684 Gtuddtyc_SPEC,
5685 crate::common::RW,
5686 > {
5687 crate::common::RegisterField::<
5688 1,
5689 0x1,
5690 1,
5691 0,
5692 gtuddtyc::Udf,
5693 gtuddtyc::Udf,
5694 Gtuddtyc_SPEC,
5695 crate::common::RW,
5696 >::from_register(self, 0)
5697 }
5698
5699 #[doc = "GTIOCnA Output Duty Setting"]
5700 #[inline(always)]
5701 pub fn oadty(
5702 self,
5703 ) -> crate::common::RegisterField<
5704 16,
5705 0x3,
5706 1,
5707 0,
5708 gtuddtyc::Oadty,
5709 gtuddtyc::Oadty,
5710 Gtuddtyc_SPEC,
5711 crate::common::RW,
5712 > {
5713 crate::common::RegisterField::<
5714 16,
5715 0x3,
5716 1,
5717 0,
5718 gtuddtyc::Oadty,
5719 gtuddtyc::Oadty,
5720 Gtuddtyc_SPEC,
5721 crate::common::RW,
5722 >::from_register(self, 0)
5723 }
5724
5725 #[doc = "Forcible GTIOCnA Output Duty Setting"]
5726 #[inline(always)]
5727 pub fn oadtyf(
5728 self,
5729 ) -> crate::common::RegisterField<
5730 18,
5731 0x1,
5732 1,
5733 0,
5734 gtuddtyc::Oadtyf,
5735 gtuddtyc::Oadtyf,
5736 Gtuddtyc_SPEC,
5737 crate::common::RW,
5738 > {
5739 crate::common::RegisterField::<
5740 18,
5741 0x1,
5742 1,
5743 0,
5744 gtuddtyc::Oadtyf,
5745 gtuddtyc::Oadtyf,
5746 Gtuddtyc_SPEC,
5747 crate::common::RW,
5748 >::from_register(self, 0)
5749 }
5750
5751 #[doc = "GTIOCnA Output Value Selecting after Releasing 0%/100% Duty Setting"]
5752 #[inline(always)]
5753 pub fn oadtyr(
5754 self,
5755 ) -> crate::common::RegisterField<
5756 19,
5757 0x1,
5758 1,
5759 0,
5760 gtuddtyc::Oadtyr,
5761 gtuddtyc::Oadtyr,
5762 Gtuddtyc_SPEC,
5763 crate::common::RW,
5764 > {
5765 crate::common::RegisterField::<
5766 19,
5767 0x1,
5768 1,
5769 0,
5770 gtuddtyc::Oadtyr,
5771 gtuddtyc::Oadtyr,
5772 Gtuddtyc_SPEC,
5773 crate::common::RW,
5774 >::from_register(self, 0)
5775 }
5776
5777 #[doc = "GTIOCnB Output Duty Setting"]
5778 #[inline(always)]
5779 pub fn obdty(
5780 self,
5781 ) -> crate::common::RegisterField<
5782 24,
5783 0x3,
5784 1,
5785 0,
5786 gtuddtyc::Obdty,
5787 gtuddtyc::Obdty,
5788 Gtuddtyc_SPEC,
5789 crate::common::RW,
5790 > {
5791 crate::common::RegisterField::<
5792 24,
5793 0x3,
5794 1,
5795 0,
5796 gtuddtyc::Obdty,
5797 gtuddtyc::Obdty,
5798 Gtuddtyc_SPEC,
5799 crate::common::RW,
5800 >::from_register(self, 0)
5801 }
5802
5803 #[doc = "Forcible GTIOCnB Output Duty Setting"]
5804 #[inline(always)]
5805 pub fn obdtyf(
5806 self,
5807 ) -> crate::common::RegisterField<
5808 26,
5809 0x1,
5810 1,
5811 0,
5812 gtuddtyc::Obdtyf,
5813 gtuddtyc::Obdtyf,
5814 Gtuddtyc_SPEC,
5815 crate::common::RW,
5816 > {
5817 crate::common::RegisterField::<
5818 26,
5819 0x1,
5820 1,
5821 0,
5822 gtuddtyc::Obdtyf,
5823 gtuddtyc::Obdtyf,
5824 Gtuddtyc_SPEC,
5825 crate::common::RW,
5826 >::from_register(self, 0)
5827 }
5828
5829 #[doc = "GTIOCnB Output Value Selecting after Releasing 0%/100% Duty Setting"]
5830 #[inline(always)]
5831 pub fn obdtyr(
5832 self,
5833 ) -> crate::common::RegisterField<
5834 27,
5835 0x1,
5836 1,
5837 0,
5838 gtuddtyc::Obdtyr,
5839 gtuddtyc::Obdtyr,
5840 Gtuddtyc_SPEC,
5841 crate::common::RW,
5842 > {
5843 crate::common::RegisterField::<
5844 27,
5845 0x1,
5846 1,
5847 0,
5848 gtuddtyc::Obdtyr,
5849 gtuddtyc::Obdtyr,
5850 Gtuddtyc_SPEC,
5851 crate::common::RW,
5852 >::from_register(self, 0)
5853 }
5854}
5855impl ::core::default::Default for Gtuddtyc {
5856 #[inline(always)]
5857 fn default() -> Gtuddtyc {
5858 <crate::RegValueT<Gtuddtyc_SPEC> as RegisterValue<_>>::new(1)
5859 }
5860}
5861pub mod gtuddtyc {
5862
5863 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5864 pub struct Ud_SPEC;
5865 pub type Ud = crate::EnumBitfieldStruct<u8, Ud_SPEC>;
5866 impl Ud {
5867 #[doc = "GTCNT counts down"]
5868 pub const _0: Self = Self::new(0);
5869
5870 #[doc = "GTCNT counts up"]
5871 pub const _1: Self = Self::new(1);
5872 }
5873 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5874 pub struct Udf_SPEC;
5875 pub type Udf = crate::EnumBitfieldStruct<u8, Udf_SPEC>;
5876 impl Udf {
5877 #[doc = "Not forcibly set"]
5878 pub const _0: Self = Self::new(0);
5879
5880 #[doc = "Forcibly set"]
5881 pub const _1: Self = Self::new(1);
5882 }
5883 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5884 pub struct Oadty_SPEC;
5885 pub type Oadty = crate::EnumBitfieldStruct<u8, Oadty_SPEC>;
5886 impl Oadty {
5887 #[doc = "GTIOCnA pin duty depends on the compare match"]
5888 pub const _00: Self = Self::new(0);
5889
5890 #[doc = "GTIOCnA pin duty depends on the compare match"]
5891 pub const _01: Self = Self::new(1);
5892
5893 #[doc = "GTIOCnA pin duty 0%"]
5894 pub const _10: Self = Self::new(2);
5895
5896 #[doc = "GTIOCnA pin duty 100%"]
5897 pub const _11: Self = Self::new(3);
5898 }
5899 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5900 pub struct Oadtyf_SPEC;
5901 pub type Oadtyf = crate::EnumBitfieldStruct<u8, Oadtyf_SPEC>;
5902 impl Oadtyf {
5903 #[doc = "Not forcibly set"]
5904 pub const _0: Self = Self::new(0);
5905
5906 #[doc = "Forcibly set"]
5907 pub const _1: Self = Self::new(1);
5908 }
5909 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5910 pub struct Oadtyr_SPEC;
5911 pub type Oadtyr = crate::EnumBitfieldStruct<u8, Oadtyr_SPEC>;
5912 impl Oadtyr {
5913 #[doc = "The function selected by the GTIOA\\[3:2\\] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting."]
5914 pub const _0: Self = Self::new(0);
5915
5916 #[doc = "The function selected by the GTIOA\\[3:2\\] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting."]
5917 pub const _1: Self = Self::new(1);
5918 }
5919 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5920 pub struct Obdty_SPEC;
5921 pub type Obdty = crate::EnumBitfieldStruct<u8, Obdty_SPEC>;
5922 impl Obdty {
5923 #[doc = "GTIOCnB pin duty depends on the compare match"]
5924 pub const _00: Self = Self::new(0);
5925
5926 #[doc = "GTIOCnB pin duty depends on the compare match"]
5927 pub const _01: Self = Self::new(1);
5928
5929 #[doc = "GTIOCnB pin duty 0%"]
5930 pub const _10: Self = Self::new(2);
5931
5932 #[doc = "GTIOCnB pin duty 100%"]
5933 pub const _11: Self = Self::new(3);
5934 }
5935 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5936 pub struct Obdtyf_SPEC;
5937 pub type Obdtyf = crate::EnumBitfieldStruct<u8, Obdtyf_SPEC>;
5938 impl Obdtyf {
5939 #[doc = "Not forcibly set"]
5940 pub const _0: Self = Self::new(0);
5941
5942 #[doc = "Forcibly set"]
5943 pub const _1: Self = Self::new(1);
5944 }
5945 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5946 pub struct Obdtyr_SPEC;
5947 pub type Obdtyr = crate::EnumBitfieldStruct<u8, Obdtyr_SPEC>;
5948 impl Obdtyr {
5949 #[doc = "The function selected by the GTIOB\\[3:2\\] bits is applied to the output value when the duty cycle is set after release from the 0 or 100% duty-cycle setting."]
5950 pub const _0: Self = Self::new(0);
5951
5952 #[doc = "The function selected by the GTIOB\\[3:2\\] bits is applied to the compare match output value which is masked after release from the 0 or 100% duty-cycle setting."]
5953 pub const _1: Self = Self::new(1);
5954 }
5955}
5956#[doc(hidden)]
5957#[derive(Copy, Clone, Eq, PartialEq)]
5958pub struct Gtior_SPEC;
5959impl crate::sealed::RegSpec for Gtior_SPEC {
5960 type DataType = u32;
5961}
5962
5963#[doc = "General PWM Timer I/O Control Register"]
5964pub type Gtior = crate::RegValueT<Gtior_SPEC>;
5965
5966impl Gtior {
5967 #[doc = "GTIOCnA Pin Function Select"]
5968 #[inline(always)]
5969 pub fn gtioa(
5970 self,
5971 ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Gtior_SPEC, crate::common::RW> {
5972 crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Gtior_SPEC,crate::common::RW>::from_register(self,0)
5973 }
5974
5975 #[doc = "GTIOCnA Pin Output Value Setting at the Count Stop"]
5976 #[inline(always)]
5977 pub fn oadflt(
5978 self,
5979 ) -> crate::common::RegisterField<
5980 6,
5981 0x1,
5982 1,
5983 0,
5984 gtior::Oadflt,
5985 gtior::Oadflt,
5986 Gtior_SPEC,
5987 crate::common::RW,
5988 > {
5989 crate::common::RegisterField::<
5990 6,
5991 0x1,
5992 1,
5993 0,
5994 gtior::Oadflt,
5995 gtior::Oadflt,
5996 Gtior_SPEC,
5997 crate::common::RW,
5998 >::from_register(self, 0)
5999 }
6000
6001 #[doc = "GTIOCnA Pin Output Setting at the Start/Stop Count"]
6002 #[inline(always)]
6003 pub fn oahld(
6004 self,
6005 ) -> crate::common::RegisterField<
6006 7,
6007 0x1,
6008 1,
6009 0,
6010 gtior::Oahld,
6011 gtior::Oahld,
6012 Gtior_SPEC,
6013 crate::common::RW,
6014 > {
6015 crate::common::RegisterField::<
6016 7,
6017 0x1,
6018 1,
6019 0,
6020 gtior::Oahld,
6021 gtior::Oahld,
6022 Gtior_SPEC,
6023 crate::common::RW,
6024 >::from_register(self, 0)
6025 }
6026
6027 #[doc = "GTIOCnA Pin Output Enable"]
6028 #[inline(always)]
6029 pub fn oae(
6030 self,
6031 ) -> crate::common::RegisterField<
6032 8,
6033 0x1,
6034 1,
6035 0,
6036 gtior::Oae,
6037 gtior::Oae,
6038 Gtior_SPEC,
6039 crate::common::RW,
6040 > {
6041 crate::common::RegisterField::<
6042 8,
6043 0x1,
6044 1,
6045 0,
6046 gtior::Oae,
6047 gtior::Oae,
6048 Gtior_SPEC,
6049 crate::common::RW,
6050 >::from_register(self, 0)
6051 }
6052
6053 #[doc = "GTIOCnA Pin Disable Value Setting"]
6054 #[inline(always)]
6055 pub fn oadf(
6056 self,
6057 ) -> crate::common::RegisterField<
6058 9,
6059 0x3,
6060 1,
6061 0,
6062 gtior::Oadf,
6063 gtior::Oadf,
6064 Gtior_SPEC,
6065 crate::common::RW,
6066 > {
6067 crate::common::RegisterField::<
6068 9,
6069 0x3,
6070 1,
6071 0,
6072 gtior::Oadf,
6073 gtior::Oadf,
6074 Gtior_SPEC,
6075 crate::common::RW,
6076 >::from_register(self, 0)
6077 }
6078
6079 #[doc = "Noise Filter A Enable"]
6080 #[inline(always)]
6081 pub fn nfaen(
6082 self,
6083 ) -> crate::common::RegisterField<
6084 13,
6085 0x1,
6086 1,
6087 0,
6088 gtior::Nfaen,
6089 gtior::Nfaen,
6090 Gtior_SPEC,
6091 crate::common::RW,
6092 > {
6093 crate::common::RegisterField::<
6094 13,
6095 0x1,
6096 1,
6097 0,
6098 gtior::Nfaen,
6099 gtior::Nfaen,
6100 Gtior_SPEC,
6101 crate::common::RW,
6102 >::from_register(self, 0)
6103 }
6104
6105 #[doc = "Noise Filter A Sampling Clock Select"]
6106 #[inline(always)]
6107 pub fn nfcsa(
6108 self,
6109 ) -> crate::common::RegisterField<
6110 14,
6111 0x3,
6112 1,
6113 0,
6114 gtior::Nfcsa,
6115 gtior::Nfcsa,
6116 Gtior_SPEC,
6117 crate::common::RW,
6118 > {
6119 crate::common::RegisterField::<
6120 14,
6121 0x3,
6122 1,
6123 0,
6124 gtior::Nfcsa,
6125 gtior::Nfcsa,
6126 Gtior_SPEC,
6127 crate::common::RW,
6128 >::from_register(self, 0)
6129 }
6130
6131 #[doc = "GTIOCnB Pin Function Select"]
6132 #[inline(always)]
6133 pub fn gtiob(
6134 self,
6135 ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, Gtior_SPEC, crate::common::RW> {
6136 crate::common::RegisterField::<16,0x1f,1,0,u8,u8,Gtior_SPEC,crate::common::RW>::from_register(self,0)
6137 }
6138
6139 #[doc = "GTIOCnB Pin Output Value Setting at the Count Stop"]
6140 #[inline(always)]
6141 pub fn obdflt(
6142 self,
6143 ) -> crate::common::RegisterField<
6144 22,
6145 0x1,
6146 1,
6147 0,
6148 gtior::Obdflt,
6149 gtior::Obdflt,
6150 Gtior_SPEC,
6151 crate::common::RW,
6152 > {
6153 crate::common::RegisterField::<
6154 22,
6155 0x1,
6156 1,
6157 0,
6158 gtior::Obdflt,
6159 gtior::Obdflt,
6160 Gtior_SPEC,
6161 crate::common::RW,
6162 >::from_register(self, 0)
6163 }
6164
6165 #[doc = "GTIOCnB Pin Output Setting at the Start/Stop Count"]
6166 #[inline(always)]
6167 pub fn obhld(
6168 self,
6169 ) -> crate::common::RegisterField<
6170 23,
6171 0x1,
6172 1,
6173 0,
6174 gtior::Obhld,
6175 gtior::Obhld,
6176 Gtior_SPEC,
6177 crate::common::RW,
6178 > {
6179 crate::common::RegisterField::<
6180 23,
6181 0x1,
6182 1,
6183 0,
6184 gtior::Obhld,
6185 gtior::Obhld,
6186 Gtior_SPEC,
6187 crate::common::RW,
6188 >::from_register(self, 0)
6189 }
6190
6191 #[doc = "GTIOCnB Pin Output Enable"]
6192 #[inline(always)]
6193 pub fn obe(
6194 self,
6195 ) -> crate::common::RegisterField<
6196 24,
6197 0x1,
6198 1,
6199 0,
6200 gtior::Obe,
6201 gtior::Obe,
6202 Gtior_SPEC,
6203 crate::common::RW,
6204 > {
6205 crate::common::RegisterField::<
6206 24,
6207 0x1,
6208 1,
6209 0,
6210 gtior::Obe,
6211 gtior::Obe,
6212 Gtior_SPEC,
6213 crate::common::RW,
6214 >::from_register(self, 0)
6215 }
6216
6217 #[doc = "GTIOCnB Pin Disable Value Setting"]
6218 #[inline(always)]
6219 pub fn obdf(
6220 self,
6221 ) -> crate::common::RegisterField<
6222 25,
6223 0x3,
6224 1,
6225 0,
6226 gtior::Obdf,
6227 gtior::Obdf,
6228 Gtior_SPEC,
6229 crate::common::RW,
6230 > {
6231 crate::common::RegisterField::<
6232 25,
6233 0x3,
6234 1,
6235 0,
6236 gtior::Obdf,
6237 gtior::Obdf,
6238 Gtior_SPEC,
6239 crate::common::RW,
6240 >::from_register(self, 0)
6241 }
6242
6243 #[doc = "Noise Filter B Enable"]
6244 #[inline(always)]
6245 pub fn nfben(
6246 self,
6247 ) -> crate::common::RegisterField<
6248 29,
6249 0x1,
6250 1,
6251 0,
6252 gtior::Nfben,
6253 gtior::Nfben,
6254 Gtior_SPEC,
6255 crate::common::RW,
6256 > {
6257 crate::common::RegisterField::<
6258 29,
6259 0x1,
6260 1,
6261 0,
6262 gtior::Nfben,
6263 gtior::Nfben,
6264 Gtior_SPEC,
6265 crate::common::RW,
6266 >::from_register(self, 0)
6267 }
6268
6269 #[doc = "Noise Filter B Sampling Clock Select"]
6270 #[inline(always)]
6271 pub fn nfcsb(
6272 self,
6273 ) -> crate::common::RegisterField<
6274 30,
6275 0x3,
6276 1,
6277 0,
6278 gtior::Nfcsb,
6279 gtior::Nfcsb,
6280 Gtior_SPEC,
6281 crate::common::RW,
6282 > {
6283 crate::common::RegisterField::<
6284 30,
6285 0x3,
6286 1,
6287 0,
6288 gtior::Nfcsb,
6289 gtior::Nfcsb,
6290 Gtior_SPEC,
6291 crate::common::RW,
6292 >::from_register(self, 0)
6293 }
6294}
6295impl ::core::default::Default for Gtior {
6296 #[inline(always)]
6297 fn default() -> Gtior {
6298 <crate::RegValueT<Gtior_SPEC> as RegisterValue<_>>::new(0)
6299 }
6300}
6301pub mod gtior {
6302
6303 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6304 pub struct Oadflt_SPEC;
6305 pub type Oadflt = crate::EnumBitfieldStruct<u8, Oadflt_SPEC>;
6306 impl Oadflt {
6307 #[doc = "The GTIOCnA pin outputs low when counting stops"]
6308 pub const _0: Self = Self::new(0);
6309
6310 #[doc = "The GTIOCnA pin outputs high when counting stops"]
6311 pub const _1: Self = Self::new(1);
6312 }
6313 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6314 pub struct Oahld_SPEC;
6315 pub type Oahld = crate::EnumBitfieldStruct<u8, Oahld_SPEC>;
6316 impl Oahld {
6317 #[doc = "The GTIOCnA pin output level at the start or stop of counting depends on the register setting"]
6318 pub const _0: Self = Self::new(0);
6319
6320 #[doc = "The GTIOCnA pin output level is retained at the start or stop of counting"]
6321 pub const _1: Self = Self::new(1);
6322 }
6323 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6324 pub struct Oae_SPEC;
6325 pub type Oae = crate::EnumBitfieldStruct<u8, Oae_SPEC>;
6326 impl Oae {
6327 #[doc = "Output is disabled"]
6328 pub const _0: Self = Self::new(0);
6329
6330 #[doc = "Output is enabled"]
6331 pub const _1: Self = Self::new(1);
6332 }
6333 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6334 pub struct Oadf_SPEC;
6335 pub type Oadf = crate::EnumBitfieldStruct<u8, Oadf_SPEC>;
6336 impl Oadf {
6337 #[doc = "None of the below options are specified"]
6338 pub const _00: Self = Self::new(0);
6339
6340 #[doc = "GTIOCnA pin is set to Hi-Z in response to controlling the output negation"]
6341 pub const _01: Self = Self::new(1);
6342
6343 #[doc = "GTIOCnA pin is set to 0 in response to controlling the output negation"]
6344 pub const _10: Self = Self::new(2);
6345
6346 #[doc = "GTIOCnA pin is set to 1 in response to controlling the output negation"]
6347 pub const _11: Self = Self::new(3);
6348 }
6349 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6350 pub struct Nfaen_SPEC;
6351 pub type Nfaen = crate::EnumBitfieldStruct<u8, Nfaen_SPEC>;
6352 impl Nfaen {
6353 #[doc = "The noise filter for the GTIOCnA pin is disabled"]
6354 pub const _0: Self = Self::new(0);
6355
6356 #[doc = "The noise filter for the GTIOCnA pin is enabled"]
6357 pub const _1: Self = Self::new(1);
6358 }
6359 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6360 pub struct Nfcsa_SPEC;
6361 pub type Nfcsa = crate::EnumBitfieldStruct<u8, Nfcsa_SPEC>;
6362 impl Nfcsa {
6363 #[doc = "PCLKD/1"]
6364 pub const _00: Self = Self::new(0);
6365
6366 #[doc = "PCLKD/4"]
6367 pub const _01: Self = Self::new(1);
6368
6369 #[doc = "PCLKD/16"]
6370 pub const _10: Self = Self::new(2);
6371
6372 #[doc = "PCLKD/64"]
6373 pub const _11: Self = Self::new(3);
6374 }
6375 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6376 pub struct Obdflt_SPEC;
6377 pub type Obdflt = crate::EnumBitfieldStruct<u8, Obdflt_SPEC>;
6378 impl Obdflt {
6379 #[doc = "The GTIOCnB pin outputs low when counting stops"]
6380 pub const _0: Self = Self::new(0);
6381
6382 #[doc = "The GTIOCnB pin outputs high when counting stops"]
6383 pub const _1: Self = Self::new(1);
6384 }
6385 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6386 pub struct Obhld_SPEC;
6387 pub type Obhld = crate::EnumBitfieldStruct<u8, Obhld_SPEC>;
6388 impl Obhld {
6389 #[doc = "The GTIOCnB pin output level at the start/stop of counting depends on the register setting"]
6390 pub const _0: Self = Self::new(0);
6391
6392 #[doc = "The GTIOCnB pin output level is retained at the start/stop of counting"]
6393 pub const _1: Self = Self::new(1);
6394 }
6395 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6396 pub struct Obe_SPEC;
6397 pub type Obe = crate::EnumBitfieldStruct<u8, Obe_SPEC>;
6398 impl Obe {
6399 #[doc = "Output is disabled"]
6400 pub const _0: Self = Self::new(0);
6401
6402 #[doc = "Output is enabled"]
6403 pub const _1: Self = Self::new(1);
6404 }
6405 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6406 pub struct Obdf_SPEC;
6407 pub type Obdf = crate::EnumBitfieldStruct<u8, Obdf_SPEC>;
6408 impl Obdf {
6409 #[doc = "None of the below options are specified"]
6410 pub const _00: Self = Self::new(0);
6411
6412 #[doc = "GTIOCnB pin is set to Hi-Z in response to controlling the output negation"]
6413 pub const _01: Self = Self::new(1);
6414
6415 #[doc = "GTIOCnB pin is set to 0 in response to controlling the output negation"]
6416 pub const _10: Self = Self::new(2);
6417
6418 #[doc = "GTIOCnB pin is set to 1 in response to controlling the output negation"]
6419 pub const _11: Self = Self::new(3);
6420 }
6421 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6422 pub struct Nfben_SPEC;
6423 pub type Nfben = crate::EnumBitfieldStruct<u8, Nfben_SPEC>;
6424 impl Nfben {
6425 #[doc = "The noise filter for the GTIOCnB pin is disabled"]
6426 pub const _0: Self = Self::new(0);
6427
6428 #[doc = "The noise filter for the GTIOCnB pin is enabled"]
6429 pub const _1: Self = Self::new(1);
6430 }
6431 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6432 pub struct Nfcsb_SPEC;
6433 pub type Nfcsb = crate::EnumBitfieldStruct<u8, Nfcsb_SPEC>;
6434 impl Nfcsb {
6435 #[doc = "PCLKD/1"]
6436 pub const _00: Self = Self::new(0);
6437
6438 #[doc = "PCLKD/4"]
6439 pub const _01: Self = Self::new(1);
6440
6441 #[doc = "PCLKD/16"]
6442 pub const _10: Self = Self::new(2);
6443
6444 #[doc = "PCLKD/64"]
6445 pub const _11: Self = Self::new(3);
6446 }
6447}
6448#[doc(hidden)]
6449#[derive(Copy, Clone, Eq, PartialEq)]
6450pub struct Gtintad_SPEC;
6451impl crate::sealed::RegSpec for Gtintad_SPEC {
6452 type DataType = u32;
6453}
6454
6455#[doc = "General PWM Timer Interrupt Output Setting Register"]
6456pub type Gtintad = crate::RegValueT<Gtintad_SPEC>;
6457
6458impl Gtintad {
6459 #[doc = "Output Disable Source Select"]
6460 #[inline(always)]
6461 pub fn grp(
6462 self,
6463 ) -> crate::common::RegisterField<
6464 24,
6465 0x3,
6466 1,
6467 0,
6468 gtintad::Grp,
6469 gtintad::Grp,
6470 Gtintad_SPEC,
6471 crate::common::RW,
6472 > {
6473 crate::common::RegisterField::<
6474 24,
6475 0x3,
6476 1,
6477 0,
6478 gtintad::Grp,
6479 gtintad::Grp,
6480 Gtintad_SPEC,
6481 crate::common::RW,
6482 >::from_register(self, 0)
6483 }
6484
6485 #[doc = "Same Time Output Level High Disable Request Enable"]
6486 #[inline(always)]
6487 pub fn grpabh(
6488 self,
6489 ) -> crate::common::RegisterField<
6490 29,
6491 0x1,
6492 1,
6493 0,
6494 gtintad::Grpabh,
6495 gtintad::Grpabh,
6496 Gtintad_SPEC,
6497 crate::common::RW,
6498 > {
6499 crate::common::RegisterField::<
6500 29,
6501 0x1,
6502 1,
6503 0,
6504 gtintad::Grpabh,
6505 gtintad::Grpabh,
6506 Gtintad_SPEC,
6507 crate::common::RW,
6508 >::from_register(self, 0)
6509 }
6510
6511 #[doc = "Same Time Output Level Low Disable Request Enable"]
6512 #[inline(always)]
6513 pub fn grpabl(
6514 self,
6515 ) -> crate::common::RegisterField<
6516 30,
6517 0x1,
6518 1,
6519 0,
6520 gtintad::Grpabl,
6521 gtintad::Grpabl,
6522 Gtintad_SPEC,
6523 crate::common::RW,
6524 > {
6525 crate::common::RegisterField::<
6526 30,
6527 0x1,
6528 1,
6529 0,
6530 gtintad::Grpabl,
6531 gtintad::Grpabl,
6532 Gtintad_SPEC,
6533 crate::common::RW,
6534 >::from_register(self, 0)
6535 }
6536}
6537impl ::core::default::Default for Gtintad {
6538 #[inline(always)]
6539 fn default() -> Gtintad {
6540 <crate::RegValueT<Gtintad_SPEC> as RegisterValue<_>>::new(0)
6541 }
6542}
6543pub mod gtintad {
6544
6545 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6546 pub struct Grp_SPEC;
6547 pub type Grp = crate::EnumBitfieldStruct<u8, Grp_SPEC>;
6548 impl Grp {
6549 #[doc = "Group A output disable source is selected Group B output disable source is selected Setting prohibited"]
6550 pub const _00: Self = Self::new(0);
6551 }
6552 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6553 pub struct Grpabh_SPEC;
6554 pub type Grpabh = crate::EnumBitfieldStruct<u8, Grpabh_SPEC>;
6555 impl Grpabh {
6556 #[doc = "Same time output level high disable request disabled"]
6557 pub const _0: Self = Self::new(0);
6558
6559 #[doc = "Same time output level high disable request enabled"]
6560 pub const _1: Self = Self::new(1);
6561 }
6562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6563 pub struct Grpabl_SPEC;
6564 pub type Grpabl = crate::EnumBitfieldStruct<u8, Grpabl_SPEC>;
6565 impl Grpabl {
6566 #[doc = "Same time output level low disable request disabled"]
6567 pub const _0: Self = Self::new(0);
6568
6569 #[doc = "Same time output level low disable request enabled"]
6570 pub const _1: Self = Self::new(1);
6571 }
6572}
6573#[doc(hidden)]
6574#[derive(Copy, Clone, Eq, PartialEq)]
6575pub struct Gtst_SPEC;
6576impl crate::sealed::RegSpec for Gtst_SPEC {
6577 type DataType = u32;
6578}
6579
6580#[doc = "General PWM Timer Status Register"]
6581pub type Gtst = crate::RegValueT<Gtst_SPEC>;
6582
6583impl Gtst {
6584 #[doc = "Input Capture/Compare Match Flag A"]
6585 #[inline(always)]
6586 pub fn tcfa(
6587 self,
6588 ) -> crate::common::RegisterField<
6589 0,
6590 0x1,
6591 1,
6592 0,
6593 gtst::Tcfa,
6594 gtst::Tcfa,
6595 Gtst_SPEC,
6596 crate::common::RW,
6597 > {
6598 crate::common::RegisterField::<
6599 0,
6600 0x1,
6601 1,
6602 0,
6603 gtst::Tcfa,
6604 gtst::Tcfa,
6605 Gtst_SPEC,
6606 crate::common::RW,
6607 >::from_register(self, 0)
6608 }
6609
6610 #[doc = "Input Capture/Compare Match Flag B"]
6611 #[inline(always)]
6612 pub fn tcfb(
6613 self,
6614 ) -> crate::common::RegisterField<
6615 1,
6616 0x1,
6617 1,
6618 0,
6619 gtst::Tcfb,
6620 gtst::Tcfb,
6621 Gtst_SPEC,
6622 crate::common::RW,
6623 > {
6624 crate::common::RegisterField::<
6625 1,
6626 0x1,
6627 1,
6628 0,
6629 gtst::Tcfb,
6630 gtst::Tcfb,
6631 Gtst_SPEC,
6632 crate::common::RW,
6633 >::from_register(self, 0)
6634 }
6635
6636 #[doc = "Input Compare Match Flag C"]
6637 #[inline(always)]
6638 pub fn tcfc(
6639 self,
6640 ) -> crate::common::RegisterField<
6641 2,
6642 0x1,
6643 1,
6644 0,
6645 gtst::Tcfc,
6646 gtst::Tcfc,
6647 Gtst_SPEC,
6648 crate::common::RW,
6649 > {
6650 crate::common::RegisterField::<
6651 2,
6652 0x1,
6653 1,
6654 0,
6655 gtst::Tcfc,
6656 gtst::Tcfc,
6657 Gtst_SPEC,
6658 crate::common::RW,
6659 >::from_register(self, 0)
6660 }
6661
6662 #[doc = "Input Compare Match Flag D"]
6663 #[inline(always)]
6664 pub fn tcfd(
6665 self,
6666 ) -> crate::common::RegisterField<
6667 3,
6668 0x1,
6669 1,
6670 0,
6671 gtst::Tcfd,
6672 gtst::Tcfd,
6673 Gtst_SPEC,
6674 crate::common::RW,
6675 > {
6676 crate::common::RegisterField::<
6677 3,
6678 0x1,
6679 1,
6680 0,
6681 gtst::Tcfd,
6682 gtst::Tcfd,
6683 Gtst_SPEC,
6684 crate::common::RW,
6685 >::from_register(self, 0)
6686 }
6687
6688 #[doc = "Input Compare Match Flag E"]
6689 #[inline(always)]
6690 pub fn tcfe(
6691 self,
6692 ) -> crate::common::RegisterField<
6693 4,
6694 0x1,
6695 1,
6696 0,
6697 gtst::Tcfe,
6698 gtst::Tcfe,
6699 Gtst_SPEC,
6700 crate::common::RW,
6701 > {
6702 crate::common::RegisterField::<
6703 4,
6704 0x1,
6705 1,
6706 0,
6707 gtst::Tcfe,
6708 gtst::Tcfe,
6709 Gtst_SPEC,
6710 crate::common::RW,
6711 >::from_register(self, 0)
6712 }
6713
6714 #[doc = "Input Compare Match Flag F"]
6715 #[inline(always)]
6716 pub fn tcff(
6717 self,
6718 ) -> crate::common::RegisterField<
6719 5,
6720 0x1,
6721 1,
6722 0,
6723 gtst::Tcff,
6724 gtst::Tcff,
6725 Gtst_SPEC,
6726 crate::common::RW,
6727 > {
6728 crate::common::RegisterField::<
6729 5,
6730 0x1,
6731 1,
6732 0,
6733 gtst::Tcff,
6734 gtst::Tcff,
6735 Gtst_SPEC,
6736 crate::common::RW,
6737 >::from_register(self, 0)
6738 }
6739
6740 #[doc = "Overflow Flag"]
6741 #[inline(always)]
6742 pub fn tcfpo(
6743 self,
6744 ) -> crate::common::RegisterField<
6745 6,
6746 0x1,
6747 1,
6748 0,
6749 gtst::Tcfpo,
6750 gtst::Tcfpo,
6751 Gtst_SPEC,
6752 crate::common::RW,
6753 > {
6754 crate::common::RegisterField::<
6755 6,
6756 0x1,
6757 1,
6758 0,
6759 gtst::Tcfpo,
6760 gtst::Tcfpo,
6761 Gtst_SPEC,
6762 crate::common::RW,
6763 >::from_register(self, 0)
6764 }
6765
6766 #[doc = "Underflow Flag"]
6767 #[inline(always)]
6768 pub fn tcfpu(
6769 self,
6770 ) -> crate::common::RegisterField<
6771 7,
6772 0x1,
6773 1,
6774 0,
6775 gtst::Tcfpu,
6776 gtst::Tcfpu,
6777 Gtst_SPEC,
6778 crate::common::RW,
6779 > {
6780 crate::common::RegisterField::<
6781 7,
6782 0x1,
6783 1,
6784 0,
6785 gtst::Tcfpu,
6786 gtst::Tcfpu,
6787 Gtst_SPEC,
6788 crate::common::RW,
6789 >::from_register(self, 0)
6790 }
6791
6792 #[doc = "Count Direction Flag"]
6793 #[inline(always)]
6794 pub fn tucf(
6795 self,
6796 ) -> crate::common::RegisterField<
6797 15,
6798 0x1,
6799 1,
6800 0,
6801 gtst::Tucf,
6802 gtst::Tucf,
6803 Gtst_SPEC,
6804 crate::common::R,
6805 > {
6806 crate::common::RegisterField::<
6807 15,
6808 0x1,
6809 1,
6810 0,
6811 gtst::Tucf,
6812 gtst::Tucf,
6813 Gtst_SPEC,
6814 crate::common::R,
6815 >::from_register(self, 0)
6816 }
6817
6818 #[doc = "Output Disable Flag"]
6819 #[inline(always)]
6820 pub fn odf(
6821 self,
6822 ) -> crate::common::RegisterField<
6823 24,
6824 0x1,
6825 1,
6826 0,
6827 gtst::Odf,
6828 gtst::Odf,
6829 Gtst_SPEC,
6830 crate::common::R,
6831 > {
6832 crate::common::RegisterField::<
6833 24,
6834 0x1,
6835 1,
6836 0,
6837 gtst::Odf,
6838 gtst::Odf,
6839 Gtst_SPEC,
6840 crate::common::R,
6841 >::from_register(self, 0)
6842 }
6843
6844 #[doc = "Same Time Output Level High Flag"]
6845 #[inline(always)]
6846 pub fn oabhf(
6847 self,
6848 ) -> crate::common::RegisterField<
6849 29,
6850 0x1,
6851 1,
6852 0,
6853 gtst::Oabhf,
6854 gtst::Oabhf,
6855 Gtst_SPEC,
6856 crate::common::R,
6857 > {
6858 crate::common::RegisterField::<
6859 29,
6860 0x1,
6861 1,
6862 0,
6863 gtst::Oabhf,
6864 gtst::Oabhf,
6865 Gtst_SPEC,
6866 crate::common::R,
6867 >::from_register(self, 0)
6868 }
6869
6870 #[doc = "Same Time Output Level Low Flag"]
6871 #[inline(always)]
6872 pub fn oablf(
6873 self,
6874 ) -> crate::common::RegisterField<
6875 30,
6876 0x1,
6877 1,
6878 0,
6879 gtst::Oablf,
6880 gtst::Oablf,
6881 Gtst_SPEC,
6882 crate::common::R,
6883 > {
6884 crate::common::RegisterField::<
6885 30,
6886 0x1,
6887 1,
6888 0,
6889 gtst::Oablf,
6890 gtst::Oablf,
6891 Gtst_SPEC,
6892 crate::common::R,
6893 >::from_register(self, 0)
6894 }
6895}
6896impl ::core::default::Default for Gtst {
6897 #[inline(always)]
6898 fn default() -> Gtst {
6899 <crate::RegValueT<Gtst_SPEC> as RegisterValue<_>>::new(32768)
6900 }
6901}
6902pub mod gtst {
6903
6904 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6905 pub struct Tcfa_SPEC;
6906 pub type Tcfa = crate::EnumBitfieldStruct<u8, Tcfa_SPEC>;
6907 impl Tcfa {
6908 #[doc = "No input capture/compare match of GTCCRA is generated"]
6909 pub const _0: Self = Self::new(0);
6910
6911 #[doc = "An input capture/compare match of GTCCRA is generated"]
6912 pub const _1: Self = Self::new(1);
6913 }
6914 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6915 pub struct Tcfb_SPEC;
6916 pub type Tcfb = crate::EnumBitfieldStruct<u8, Tcfb_SPEC>;
6917 impl Tcfb {
6918 #[doc = "No input capture/compare match of GTCCRB is generated"]
6919 pub const _0: Self = Self::new(0);
6920
6921 #[doc = "An input capture/compare match of GTCCRB is generated"]
6922 pub const _1: Self = Self::new(1);
6923 }
6924 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6925 pub struct Tcfc_SPEC;
6926 pub type Tcfc = crate::EnumBitfieldStruct<u8, Tcfc_SPEC>;
6927 impl Tcfc {
6928 #[doc = "No compare match of GTCCRC is generated"]
6929 pub const _0: Self = Self::new(0);
6930
6931 #[doc = "A compare match of GTCCRC is generated"]
6932 pub const _1: Self = Self::new(1);
6933 }
6934 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6935 pub struct Tcfd_SPEC;
6936 pub type Tcfd = crate::EnumBitfieldStruct<u8, Tcfd_SPEC>;
6937 impl Tcfd {
6938 #[doc = "No compare match of GTCCRD is generated"]
6939 pub const _0: Self = Self::new(0);
6940
6941 #[doc = "A compare match of GTCCRD is generated"]
6942 pub const _1: Self = Self::new(1);
6943 }
6944 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6945 pub struct Tcfe_SPEC;
6946 pub type Tcfe = crate::EnumBitfieldStruct<u8, Tcfe_SPEC>;
6947 impl Tcfe {
6948 #[doc = "No compare match of GTCCRE is generated"]
6949 pub const _0: Self = Self::new(0);
6950
6951 #[doc = "A compare match of GTCCRE is generated"]
6952 pub const _1: Self = Self::new(1);
6953 }
6954 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6955 pub struct Tcff_SPEC;
6956 pub type Tcff = crate::EnumBitfieldStruct<u8, Tcff_SPEC>;
6957 impl Tcff {
6958 #[doc = "No compare match of GTCCRF is generated"]
6959 pub const _0: Self = Self::new(0);
6960
6961 #[doc = "A compare match of GTCCRF is generated"]
6962 pub const _1: Self = Self::new(1);
6963 }
6964 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6965 pub struct Tcfpo_SPEC;
6966 pub type Tcfpo = crate::EnumBitfieldStruct<u8, Tcfpo_SPEC>;
6967 impl Tcfpo {
6968 #[doc = "No overflow (crest) occurred"]
6969 pub const _0: Self = Self::new(0);
6970
6971 #[doc = "An overflow (crest) occurred"]
6972 pub const _1: Self = Self::new(1);
6973 }
6974 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6975 pub struct Tcfpu_SPEC;
6976 pub type Tcfpu = crate::EnumBitfieldStruct<u8, Tcfpu_SPEC>;
6977 impl Tcfpu {
6978 #[doc = "No underflow (trough) occurred"]
6979 pub const _0: Self = Self::new(0);
6980
6981 #[doc = "An underflow (trough) occurred"]
6982 pub const _1: Self = Self::new(1);
6983 }
6984 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6985 pub struct Tucf_SPEC;
6986 pub type Tucf = crate::EnumBitfieldStruct<u8, Tucf_SPEC>;
6987 impl Tucf {
6988 #[doc = "GTCNT counter counts downward"]
6989 pub const _0: Self = Self::new(0);
6990
6991 #[doc = "GTCNT counter counts upward"]
6992 pub const _1: Self = Self::new(1);
6993 }
6994 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
6995 pub struct Odf_SPEC;
6996 pub type Odf = crate::EnumBitfieldStruct<u8, Odf_SPEC>;
6997 impl Odf {
6998 #[doc = "No output disable request is generated"]
6999 pub const _0: Self = Self::new(0);
7000
7001 #[doc = "An output disable request is generated"]
7002 pub const _1: Self = Self::new(1);
7003 }
7004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7005 pub struct Oabhf_SPEC;
7006 pub type Oabhf = crate::EnumBitfieldStruct<u8, Oabhf_SPEC>;
7007 impl Oabhf {
7008 #[doc = "No simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred."]
7009 pub const _0: Self = Self::new(0);
7010
7011 #[doc = "A simultaneous generation of 1 both for the GTIOCA and GTIOCB pins has occurred."]
7012 pub const _1: Self = Self::new(1);
7013 }
7014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7015 pub struct Oablf_SPEC;
7016 pub type Oablf = crate::EnumBitfieldStruct<u8, Oablf_SPEC>;
7017 impl Oablf {
7018 #[doc = "No simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred."]
7019 pub const _0: Self = Self::new(0);
7020
7021 #[doc = "A simultaneous generation of 0 both for the GTIOCA and GTIOCB pins has occurred."]
7022 pub const _1: Self = Self::new(1);
7023 }
7024}
7025#[doc(hidden)]
7026#[derive(Copy, Clone, Eq, PartialEq)]
7027pub struct Gtber_SPEC;
7028impl crate::sealed::RegSpec for Gtber_SPEC {
7029 type DataType = u32;
7030}
7031
7032#[doc = "General PWM Timer Buffer Enable Register"]
7033pub type Gtber = crate::RegValueT<Gtber_SPEC>;
7034
7035impl Gtber {
7036 #[doc = "GTCCR Buffer Operation Disable"]
7037 #[inline(always)]
7038 pub fn bd0(
7039 self,
7040 ) -> crate::common::RegisterField<
7041 0,
7042 0x1,
7043 1,
7044 0,
7045 gtber::Bd0,
7046 gtber::Bd0,
7047 Gtber_SPEC,
7048 crate::common::RW,
7049 > {
7050 crate::common::RegisterField::<
7051 0,
7052 0x1,
7053 1,
7054 0,
7055 gtber::Bd0,
7056 gtber::Bd0,
7057 Gtber_SPEC,
7058 crate::common::RW,
7059 >::from_register(self, 0)
7060 }
7061
7062 #[doc = "GTPR Buffer Operation Disable"]
7063 #[inline(always)]
7064 pub fn bd1(
7065 self,
7066 ) -> crate::common::RegisterField<
7067 1,
7068 0x1,
7069 1,
7070 0,
7071 gtber::Bd1,
7072 gtber::Bd1,
7073 Gtber_SPEC,
7074 crate::common::RW,
7075 > {
7076 crate::common::RegisterField::<
7077 1,
7078 0x1,
7079 1,
7080 0,
7081 gtber::Bd1,
7082 gtber::Bd1,
7083 Gtber_SPEC,
7084 crate::common::RW,
7085 >::from_register(self, 0)
7086 }
7087
7088 #[doc = "GTCCRA Buffer Operation"]
7089 #[inline(always)]
7090 pub fn ccra(
7091 self,
7092 ) -> crate::common::RegisterField<
7093 16,
7094 0x3,
7095 1,
7096 0,
7097 gtber::Ccra,
7098 gtber::Ccra,
7099 Gtber_SPEC,
7100 crate::common::RW,
7101 > {
7102 crate::common::RegisterField::<
7103 16,
7104 0x3,
7105 1,
7106 0,
7107 gtber::Ccra,
7108 gtber::Ccra,
7109 Gtber_SPEC,
7110 crate::common::RW,
7111 >::from_register(self, 0)
7112 }
7113
7114 #[doc = "GTCCRB Buffer Operation"]
7115 #[inline(always)]
7116 pub fn ccrb(
7117 self,
7118 ) -> crate::common::RegisterField<
7119 18,
7120 0x3,
7121 1,
7122 0,
7123 gtber::Ccrb,
7124 gtber::Ccrb,
7125 Gtber_SPEC,
7126 crate::common::RW,
7127 > {
7128 crate::common::RegisterField::<
7129 18,
7130 0x3,
7131 1,
7132 0,
7133 gtber::Ccrb,
7134 gtber::Ccrb,
7135 Gtber_SPEC,
7136 crate::common::RW,
7137 >::from_register(self, 0)
7138 }
7139
7140 #[doc = "GTPR Buffer Operation"]
7141 #[inline(always)]
7142 pub fn pr(
7143 self,
7144 ) -> crate::common::RegisterField<
7145 20,
7146 0x3,
7147 1,
7148 0,
7149 gtber::Pr,
7150 gtber::Pr,
7151 Gtber_SPEC,
7152 crate::common::RW,
7153 > {
7154 crate::common::RegisterField::<
7155 20,
7156 0x3,
7157 1,
7158 0,
7159 gtber::Pr,
7160 gtber::Pr,
7161 Gtber_SPEC,
7162 crate::common::RW,
7163 >::from_register(self, 0)
7164 }
7165
7166 #[doc = "GTCCRA and GTCCRB Forcible Buffer Operation"]
7167 #[inline(always)]
7168 pub fn ccrswt(
7169 self,
7170 ) -> crate::common::RegisterFieldBool<22, 1, 0, Gtber_SPEC, crate::common::W> {
7171 crate::common::RegisterFieldBool::<22, 1, 0, Gtber_SPEC, crate::common::W>::from_register(
7172 self, 0,
7173 )
7174 }
7175}
7176impl ::core::default::Default for Gtber {
7177 #[inline(always)]
7178 fn default() -> Gtber {
7179 <crate::RegValueT<Gtber_SPEC> as RegisterValue<_>>::new(0)
7180 }
7181}
7182pub mod gtber {
7183
7184 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7185 pub struct Bd0_SPEC;
7186 pub type Bd0 = crate::EnumBitfieldStruct<u8, Bd0_SPEC>;
7187 impl Bd0 {
7188 #[doc = "Buffer operation is enabled"]
7189 pub const _0: Self = Self::new(0);
7190
7191 #[doc = "Buffer operation is disabled"]
7192 pub const _1: Self = Self::new(1);
7193 }
7194 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7195 pub struct Bd1_SPEC;
7196 pub type Bd1 = crate::EnumBitfieldStruct<u8, Bd1_SPEC>;
7197 impl Bd1 {
7198 #[doc = "Buffer operation is enabled"]
7199 pub const _0: Self = Self::new(0);
7200
7201 #[doc = "Buffer operation is disabled"]
7202 pub const _1: Self = Self::new(1);
7203 }
7204 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7205 pub struct Ccra_SPEC;
7206 pub type Ccra = crate::EnumBitfieldStruct<u8, Ccra_SPEC>;
7207 impl Ccra {
7208 #[doc = "No buffer operation"]
7209 pub const _00: Self = Self::new(0);
7210
7211 #[doc = "Single buffer operation (GTCCRA ↔ GTCCRC)"]
7212 pub const _01: Self = Self::new(1);
7213 }
7214 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7215 pub struct Ccrb_SPEC;
7216 pub type Ccrb = crate::EnumBitfieldStruct<u8, Ccrb_SPEC>;
7217 impl Ccrb {
7218 #[doc = "No buffer operation"]
7219 pub const _00: Self = Self::new(0);
7220
7221 #[doc = "Single buffer operation (GTCCRB ↔ GTCCRE)"]
7222 pub const _01: Self = Self::new(1);
7223 }
7224 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7225 pub struct Pr_SPEC;
7226 pub type Pr = crate::EnumBitfieldStruct<u8, Pr_SPEC>;
7227 impl Pr {
7228 #[doc = "No buffer operation"]
7229 pub const _00: Self = Self::new(0);
7230
7231 #[doc = "Single buffer operation (GTPBR → GTPR)"]
7232 pub const _01: Self = Self::new(1);
7233 }
7234}
7235#[doc(hidden)]
7236#[derive(Copy, Clone, Eq, PartialEq)]
7237pub struct Gtcnt_SPEC;
7238impl crate::sealed::RegSpec for Gtcnt_SPEC {
7239 type DataType = u32;
7240}
7241
7242#[doc = "General PWM Timer Counter"]
7243pub type Gtcnt = crate::RegValueT<Gtcnt_SPEC>;
7244
7245impl NoBitfieldReg<Gtcnt_SPEC> for Gtcnt {}
7246impl ::core::default::Default for Gtcnt {
7247 #[inline(always)]
7248 fn default() -> Gtcnt {
7249 <crate::RegValueT<Gtcnt_SPEC> as RegisterValue<_>>::new(0)
7250 }
7251}
7252
7253#[doc(hidden)]
7254#[derive(Copy, Clone, Eq, PartialEq)]
7255pub struct Gtccra_SPEC;
7256impl crate::sealed::RegSpec for Gtccra_SPEC {
7257 type DataType = u32;
7258}
7259
7260#[doc = "General PWM Timer Compare Capture Register A"]
7261pub type Gtccra = crate::RegValueT<Gtccra_SPEC>;
7262
7263impl NoBitfieldReg<Gtccra_SPEC> for Gtccra {}
7264impl ::core::default::Default for Gtccra {
7265 #[inline(always)]
7266 fn default() -> Gtccra {
7267 <crate::RegValueT<Gtccra_SPEC> as RegisterValue<_>>::new(4294967295)
7268 }
7269}
7270
7271#[doc(hidden)]
7272#[derive(Copy, Clone, Eq, PartialEq)]
7273pub struct Gtccrb_SPEC;
7274impl crate::sealed::RegSpec for Gtccrb_SPEC {
7275 type DataType = u32;
7276}
7277
7278#[doc = "General PWM Timer Compare Capture Register B"]
7279pub type Gtccrb = crate::RegValueT<Gtccrb_SPEC>;
7280
7281impl NoBitfieldReg<Gtccrb_SPEC> for Gtccrb {}
7282impl ::core::default::Default for Gtccrb {
7283 #[inline(always)]
7284 fn default() -> Gtccrb {
7285 <crate::RegValueT<Gtccrb_SPEC> as RegisterValue<_>>::new(4294967295)
7286 }
7287}
7288
7289#[doc(hidden)]
7290#[derive(Copy, Clone, Eq, PartialEq)]
7291pub struct Gtccrc_SPEC;
7292impl crate::sealed::RegSpec for Gtccrc_SPEC {
7293 type DataType = u32;
7294}
7295
7296#[doc = "General PWM Timer Compare Capture Register C"]
7297pub type Gtccrc = crate::RegValueT<Gtccrc_SPEC>;
7298
7299impl NoBitfieldReg<Gtccrc_SPEC> for Gtccrc {}
7300impl ::core::default::Default for Gtccrc {
7301 #[inline(always)]
7302 fn default() -> Gtccrc {
7303 <crate::RegValueT<Gtccrc_SPEC> as RegisterValue<_>>::new(4294967295)
7304 }
7305}
7306
7307#[doc(hidden)]
7308#[derive(Copy, Clone, Eq, PartialEq)]
7309pub struct Gtccre_SPEC;
7310impl crate::sealed::RegSpec for Gtccre_SPEC {
7311 type DataType = u32;
7312}
7313
7314#[doc = "General PWM Timer Compare Capture Register E"]
7315pub type Gtccre = crate::RegValueT<Gtccre_SPEC>;
7316
7317impl NoBitfieldReg<Gtccre_SPEC> for Gtccre {}
7318impl ::core::default::Default for Gtccre {
7319 #[inline(always)]
7320 fn default() -> Gtccre {
7321 <crate::RegValueT<Gtccre_SPEC> as RegisterValue<_>>::new(4294967295)
7322 }
7323}
7324
7325#[doc(hidden)]
7326#[derive(Copy, Clone, Eq, PartialEq)]
7327pub struct Gtccrd_SPEC;
7328impl crate::sealed::RegSpec for Gtccrd_SPEC {
7329 type DataType = u32;
7330}
7331
7332#[doc = "General PWM Timer Compare Capture Register D"]
7333pub type Gtccrd = crate::RegValueT<Gtccrd_SPEC>;
7334
7335impl NoBitfieldReg<Gtccrd_SPEC> for Gtccrd {}
7336impl ::core::default::Default for Gtccrd {
7337 #[inline(always)]
7338 fn default() -> Gtccrd {
7339 <crate::RegValueT<Gtccrd_SPEC> as RegisterValue<_>>::new(4294967295)
7340 }
7341}
7342
7343#[doc(hidden)]
7344#[derive(Copy, Clone, Eq, PartialEq)]
7345pub struct Gtccrf_SPEC;
7346impl crate::sealed::RegSpec for Gtccrf_SPEC {
7347 type DataType = u32;
7348}
7349
7350#[doc = "General PWM Timer Compare Capture Register F"]
7351pub type Gtccrf = crate::RegValueT<Gtccrf_SPEC>;
7352
7353impl NoBitfieldReg<Gtccrf_SPEC> for Gtccrf {}
7354impl ::core::default::Default for Gtccrf {
7355 #[inline(always)]
7356 fn default() -> Gtccrf {
7357 <crate::RegValueT<Gtccrf_SPEC> as RegisterValue<_>>::new(4294967295)
7358 }
7359}
7360
7361#[doc(hidden)]
7362#[derive(Copy, Clone, Eq, PartialEq)]
7363pub struct Gtpr_SPEC;
7364impl crate::sealed::RegSpec for Gtpr_SPEC {
7365 type DataType = u32;
7366}
7367
7368#[doc = "General PWM Timer Cycle Setting Register"]
7369pub type Gtpr = crate::RegValueT<Gtpr_SPEC>;
7370
7371impl NoBitfieldReg<Gtpr_SPEC> for Gtpr {}
7372impl ::core::default::Default for Gtpr {
7373 #[inline(always)]
7374 fn default() -> Gtpr {
7375 <crate::RegValueT<Gtpr_SPEC> as RegisterValue<_>>::new(4294967295)
7376 }
7377}
7378
7379#[doc(hidden)]
7380#[derive(Copy, Clone, Eq, PartialEq)]
7381pub struct Gtpbr_SPEC;
7382impl crate::sealed::RegSpec for Gtpbr_SPEC {
7383 type DataType = u32;
7384}
7385
7386#[doc = "General PWM Timer Cycle Setting Buffer Register"]
7387pub type Gtpbr = crate::RegValueT<Gtpbr_SPEC>;
7388
7389impl NoBitfieldReg<Gtpbr_SPEC> for Gtpbr {}
7390impl ::core::default::Default for Gtpbr {
7391 #[inline(always)]
7392 fn default() -> Gtpbr {
7393 <crate::RegValueT<Gtpbr_SPEC> as RegisterValue<_>>::new(4294967295)
7394 }
7395}
7396
7397#[doc(hidden)]
7398#[derive(Copy, Clone, Eq, PartialEq)]
7399pub struct Gtdtcr_SPEC;
7400impl crate::sealed::RegSpec for Gtdtcr_SPEC {
7401 type DataType = u32;
7402}
7403
7404#[doc = "General PWM Timer Dead Time Control Register"]
7405pub type Gtdtcr = crate::RegValueT<Gtdtcr_SPEC>;
7406
7407impl Gtdtcr {
7408 #[doc = "Negative-Phase Waveform Setting"]
7409 #[inline(always)]
7410 pub fn tde(
7411 self,
7412 ) -> crate::common::RegisterField<
7413 0,
7414 0x1,
7415 1,
7416 0,
7417 gtdtcr::Tde,
7418 gtdtcr::Tde,
7419 Gtdtcr_SPEC,
7420 crate::common::RW,
7421 > {
7422 crate::common::RegisterField::<
7423 0,
7424 0x1,
7425 1,
7426 0,
7427 gtdtcr::Tde,
7428 gtdtcr::Tde,
7429 Gtdtcr_SPEC,
7430 crate::common::RW,
7431 >::from_register(self, 0)
7432 }
7433}
7434impl ::core::default::Default for Gtdtcr {
7435 #[inline(always)]
7436 fn default() -> Gtdtcr {
7437 <crate::RegValueT<Gtdtcr_SPEC> as RegisterValue<_>>::new(0)
7438 }
7439}
7440pub mod gtdtcr {
7441
7442 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
7443 pub struct Tde_SPEC;
7444 pub type Tde = crate::EnumBitfieldStruct<u8, Tde_SPEC>;
7445 impl Tde {
7446 #[doc = "GTCCRB is set without using GTDVU"]
7447 pub const _0: Self = Self::new(0);
7448
7449 #[doc = "GTDVU is used to set the compare match value for negative-phase waveform with dead time automatically in GTCCRB"]
7450 pub const _1: Self = Self::new(1);
7451 }
7452}
7453#[doc(hidden)]
7454#[derive(Copy, Clone, Eq, PartialEq)]
7455pub struct Gtdvu_SPEC;
7456impl crate::sealed::RegSpec for Gtdvu_SPEC {
7457 type DataType = u32;
7458}
7459
7460#[doc = "General PWM Timer Dead Time Value Register U"]
7461pub type Gtdvu = crate::RegValueT<Gtdvu_SPEC>;
7462
7463impl NoBitfieldReg<Gtdvu_SPEC> for Gtdvu {}
7464impl ::core::default::Default for Gtdvu {
7465 #[inline(always)]
7466 fn default() -> Gtdvu {
7467 <crate::RegValueT<Gtdvu_SPEC> as RegisterValue<_>>::new(4294967295)
7468 }
7469}