1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"System Control"]
28unsafe impl ::core::marker::Send for super::Sysc {}
29unsafe impl ::core::marker::Sync for super::Sysc {}
30impl super::Sysc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "Standby Control Register"]
38 #[inline(always)]
39 pub const fn sbycr(&self) -> &'static crate::common::Reg<self::Sbycr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Sbycr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(12usize),
43 )
44 }
45 }
46
47 #[doc = "Module Stop Control Register A"]
48 #[inline(always)]
49 pub const fn mstpcra(
50 &self,
51 ) -> &'static crate::common::Reg<self::Mstpcra_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Mstpcra_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(28usize),
55 )
56 }
57 }
58
59 #[doc = "System Clock Division Control Register"]
60 #[inline(always)]
61 pub const fn sckdivcr(
62 &self,
63 ) -> &'static crate::common::Reg<self::Sckdivcr_SPEC, crate::common::RW> {
64 unsafe {
65 crate::common::Reg::<self::Sckdivcr_SPEC, crate::common::RW>::from_ptr(
66 self._svd2pac_as_ptr().add(32usize),
67 )
68 }
69 }
70
71 #[doc = "System Clock Source Control Register"]
72 #[inline(always)]
73 pub const fn sckscr(
74 &self,
75 ) -> &'static crate::common::Reg<self::Sckscr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Sckscr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(38usize),
79 )
80 }
81 }
82
83 #[doc = "Memory Wait Cycle Control Register for Code Flash"]
84 #[inline(always)]
85 pub const fn memwait(
86 &self,
87 ) -> &'static crate::common::Reg<self::Memwait_SPEC, crate::common::RW> {
88 unsafe {
89 crate::common::Reg::<self::Memwait_SPEC, crate::common::RW>::from_ptr(
90 self._svd2pac_as_ptr().add(49usize),
91 )
92 }
93 }
94
95 #[doc = "Main Clock Oscillator Control Register"]
96 #[inline(always)]
97 pub const fn mosccr(
98 &self,
99 ) -> &'static crate::common::Reg<self::Mosccr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Mosccr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(50usize),
103 )
104 }
105 }
106
107 #[doc = "High-Speed On-Chip Oscillator Control Register"]
108 #[inline(always)]
109 pub const fn hococr(
110 &self,
111 ) -> &'static crate::common::Reg<self::Hococr_SPEC, crate::common::RW> {
112 unsafe {
113 crate::common::Reg::<self::Hococr_SPEC, crate::common::RW>::from_ptr(
114 self._svd2pac_as_ptr().add(54usize),
115 )
116 }
117 }
118
119 #[doc = "Middle-Speed On-Chip Oscillator Control Register"]
120 #[inline(always)]
121 pub const fn mococr(
122 &self,
123 ) -> &'static crate::common::Reg<self::Mococr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Mococr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(56usize),
127 )
128 }
129 }
130
131 #[doc = "Oscillation Stabilization Flag Register"]
132 #[inline(always)]
133 pub const fn oscsf(&self) -> &'static crate::common::Reg<self::Oscsf_SPEC, crate::common::R> {
134 unsafe {
135 crate::common::Reg::<self::Oscsf_SPEC, crate::common::R>::from_ptr(
136 self._svd2pac_as_ptr().add(60usize),
137 )
138 }
139 }
140
141 #[doc = "Clock Out Control Register"]
142 #[inline(always)]
143 pub const fn ckocr(&self) -> &'static crate::common::Reg<self::Ckocr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Ckocr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(62usize),
147 )
148 }
149 }
150
151 #[doc = "Oscillation Stop Detection Control Register"]
152 #[inline(always)]
153 pub const fn ostdcr(
154 &self,
155 ) -> &'static crate::common::Reg<self::Ostdcr_SPEC, crate::common::RW> {
156 unsafe {
157 crate::common::Reg::<self::Ostdcr_SPEC, crate::common::RW>::from_ptr(
158 self._svd2pac_as_ptr().add(64usize),
159 )
160 }
161 }
162
163 #[doc = "Oscillation Stop Detection Status Register"]
164 #[inline(always)]
165 pub const fn ostdsr(
166 &self,
167 ) -> &'static crate::common::Reg<self::Ostdsr_SPEC, crate::common::RW> {
168 unsafe {
169 crate::common::Reg::<self::Ostdsr_SPEC, crate::common::RW>::from_ptr(
170 self._svd2pac_as_ptr().add(65usize),
171 )
172 }
173 }
174
175 #[doc = "Lower Power Operation Control Register"]
176 #[inline(always)]
177 pub const fn lpopt(&self) -> &'static crate::common::Reg<self::Lpopt_SPEC, crate::common::RW> {
178 unsafe {
179 crate::common::Reg::<self::Lpopt_SPEC, crate::common::RW>::from_ptr(
180 self._svd2pac_as_ptr().add(76usize),
181 )
182 }
183 }
184
185 #[doc = "MOCO User Trimming Control Register"]
186 #[inline(always)]
187 pub const fn mocoutcr(
188 &self,
189 ) -> &'static crate::common::Reg<self::Mocoutcr_SPEC, crate::common::RW> {
190 unsafe {
191 crate::common::Reg::<self::Mocoutcr_SPEC, crate::common::RW>::from_ptr(
192 self._svd2pac_as_ptr().add(97usize),
193 )
194 }
195 }
196
197 #[doc = "HOCO User Trimming Control Register"]
198 #[inline(always)]
199 pub const fn hocoutcr(
200 &self,
201 ) -> &'static crate::common::Reg<self::Hocoutcr_SPEC, crate::common::RW> {
202 unsafe {
203 crate::common::Reg::<self::Hocoutcr_SPEC, crate::common::RW>::from_ptr(
204 self._svd2pac_as_ptr().add(98usize),
205 )
206 }
207 }
208
209 #[doc = "Snooze Control Register"]
210 #[inline(always)]
211 pub const fn snzcr(&self) -> &'static crate::common::Reg<self::Snzcr_SPEC, crate::common::RW> {
212 unsafe {
213 crate::common::Reg::<self::Snzcr_SPEC, crate::common::RW>::from_ptr(
214 self._svd2pac_as_ptr().add(146usize),
215 )
216 }
217 }
218
219 #[doc = "Snooze End Control Register 0"]
220 #[inline(always)]
221 pub const fn snzedcr0(
222 &self,
223 ) -> &'static crate::common::Reg<self::Snzedcr0_SPEC, crate::common::RW> {
224 unsafe {
225 crate::common::Reg::<self::Snzedcr0_SPEC, crate::common::RW>::from_ptr(
226 self._svd2pac_as_ptr().add(148usize),
227 )
228 }
229 }
230
231 #[doc = "Snooze Request Control Register 0"]
232 #[inline(always)]
233 pub const fn snzreqcr0(
234 &self,
235 ) -> &'static crate::common::Reg<self::Snzreqcr0_SPEC, crate::common::RW> {
236 unsafe {
237 crate::common::Reg::<self::Snzreqcr0_SPEC, crate::common::RW>::from_ptr(
238 self._svd2pac_as_ptr().add(152usize),
239 )
240 }
241 }
242
243 #[doc = "Power Save Memory Control Register"]
244 #[inline(always)]
245 pub const fn psmcr(&self) -> &'static crate::common::Reg<self::Psmcr_SPEC, crate::common::RW> {
246 unsafe {
247 crate::common::Reg::<self::Psmcr_SPEC, crate::common::RW>::from_ptr(
248 self._svd2pac_as_ptr().add(159usize),
249 )
250 }
251 }
252
253 #[doc = "Operating Power Control Register"]
254 #[inline(always)]
255 pub const fn opccr(&self) -> &'static crate::common::Reg<self::Opccr_SPEC, crate::common::RW> {
256 unsafe {
257 crate::common::Reg::<self::Opccr_SPEC, crate::common::RW>::from_ptr(
258 self._svd2pac_as_ptr().add(160usize),
259 )
260 }
261 }
262
263 #[doc = "Main Clock Oscillator Wait Control Register"]
264 #[inline(always)]
265 pub const fn moscwtcr(
266 &self,
267 ) -> &'static crate::common::Reg<self::Moscwtcr_SPEC, crate::common::RW> {
268 unsafe {
269 crate::common::Reg::<self::Moscwtcr_SPEC, crate::common::RW>::from_ptr(
270 self._svd2pac_as_ptr().add(162usize),
271 )
272 }
273 }
274
275 #[doc = "High-Speed On-Chip Oscillator Wait Control Register"]
276 #[inline(always)]
277 pub const fn hocowtcr(
278 &self,
279 ) -> &'static crate::common::Reg<self::Hocowtcr_SPEC, crate::common::RW> {
280 unsafe {
281 crate::common::Reg::<self::Hocowtcr_SPEC, crate::common::RW>::from_ptr(
282 self._svd2pac_as_ptr().add(165usize),
283 )
284 }
285 }
286
287 #[doc = "Sub Operating Power Control Register"]
288 #[inline(always)]
289 pub const fn sopccr(
290 &self,
291 ) -> &'static crate::common::Reg<self::Sopccr_SPEC, crate::common::RW> {
292 unsafe {
293 crate::common::Reg::<self::Sopccr_SPEC, crate::common::RW>::from_ptr(
294 self._svd2pac_as_ptr().add(170usize),
295 )
296 }
297 }
298
299 #[doc = "Reset Status Register 1"]
300 #[inline(always)]
301 pub const fn rstsr1(
302 &self,
303 ) -> &'static crate::common::Reg<self::Rstsr1_SPEC, crate::common::RW> {
304 unsafe {
305 crate::common::Reg::<self::Rstsr1_SPEC, crate::common::RW>::from_ptr(
306 self._svd2pac_as_ptr().add(192usize),
307 )
308 }
309 }
310
311 #[doc = "Voltage Monitor 1 Circuit Control Register"]
312 #[inline(always)]
313 pub const fn lvd1cr1(
314 &self,
315 ) -> &'static crate::common::Reg<self::Lvd1Cr1_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Lvd1Cr1_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(224usize),
319 )
320 }
321 }
322
323 #[doc = "Voltage Monitor 1 Circuit Status Register"]
324 #[inline(always)]
325 pub const fn lvd1sr(
326 &self,
327 ) -> &'static crate::common::Reg<self::Lvd1Sr_SPEC, crate::common::RW> {
328 unsafe {
329 crate::common::Reg::<self::Lvd1Sr_SPEC, crate::common::RW>::from_ptr(
330 self._svd2pac_as_ptr().add(225usize),
331 )
332 }
333 }
334
335 #[doc = "Voltage Monitor 2 Circuit Control Register 1"]
336 #[inline(always)]
337 pub const fn lvd2cr1(
338 &self,
339 ) -> &'static crate::common::Reg<self::Lvd2Cr1_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::Lvd2Cr1_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(226usize),
343 )
344 }
345 }
346
347 #[doc = "Voltage Monitor 2 Circuit Status Register"]
348 #[inline(always)]
349 pub const fn lvd2sr(
350 &self,
351 ) -> &'static crate::common::Reg<self::Lvd2Sr_SPEC, crate::common::RW> {
352 unsafe {
353 crate::common::Reg::<self::Lvd2Sr_SPEC, crate::common::RW>::from_ptr(
354 self._svd2pac_as_ptr().add(227usize),
355 )
356 }
357 }
358
359 #[doc = "Protect Register"]
360 #[inline(always)]
361 pub const fn prcr(&self) -> &'static crate::common::Reg<self::Prcr_SPEC, crate::common::RW> {
362 unsafe {
363 crate::common::Reg::<self::Prcr_SPEC, crate::common::RW>::from_ptr(
364 self._svd2pac_as_ptr().add(1022usize),
365 )
366 }
367 }
368
369 #[doc = "System Control OCD Control Register"]
370 #[inline(always)]
371 pub const fn syocdcr(
372 &self,
373 ) -> &'static crate::common::Reg<self::Syocdcr_SPEC, crate::common::RW> {
374 unsafe {
375 crate::common::Reg::<self::Syocdcr_SPEC, crate::common::RW>::from_ptr(
376 self._svd2pac_as_ptr().add(1038usize),
377 )
378 }
379 }
380
381 #[doc = "Reset Status Register 0"]
382 #[inline(always)]
383 pub const fn rstsr0(
384 &self,
385 ) -> &'static crate::common::Reg<self::Rstsr0_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Rstsr0_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(1040usize),
389 )
390 }
391 }
392
393 #[doc = "Reset Status Register 2"]
394 #[inline(always)]
395 pub const fn rstsr2(
396 &self,
397 ) -> &'static crate::common::Reg<self::Rstsr2_SPEC, crate::common::RW> {
398 unsafe {
399 crate::common::Reg::<self::Rstsr2_SPEC, crate::common::RW>::from_ptr(
400 self._svd2pac_as_ptr().add(1041usize),
401 )
402 }
403 }
404
405 #[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
406 #[inline(always)]
407 pub const fn momcr(&self) -> &'static crate::common::Reg<self::Momcr_SPEC, crate::common::RW> {
408 unsafe {
409 crate::common::Reg::<self::Momcr_SPEC, crate::common::RW>::from_ptr(
410 self._svd2pac_as_ptr().add(1043usize),
411 )
412 }
413 }
414
415 #[doc = "Voltage Monitor Circuit Control Register"]
416 #[inline(always)]
417 pub const fn lvcmpcr(
418 &self,
419 ) -> &'static crate::common::Reg<self::Lvcmpcr_SPEC, crate::common::RW> {
420 unsafe {
421 crate::common::Reg::<self::Lvcmpcr_SPEC, crate::common::RW>::from_ptr(
422 self._svd2pac_as_ptr().add(1047usize),
423 )
424 }
425 }
426
427 #[doc = "Voltage Detection Level Select Register"]
428 #[inline(always)]
429 pub const fn lvdlvlr(
430 &self,
431 ) -> &'static crate::common::Reg<self::Lvdlvlr_SPEC, crate::common::RW> {
432 unsafe {
433 crate::common::Reg::<self::Lvdlvlr_SPEC, crate::common::RW>::from_ptr(
434 self._svd2pac_as_ptr().add(1048usize),
435 )
436 }
437 }
438
439 #[doc = "Voltage Monitor 1 Circuit Control Register 0"]
440 #[inline(always)]
441 pub const fn lvd1cr0(
442 &self,
443 ) -> &'static crate::common::Reg<self::Lvd1Cr0_SPEC, crate::common::RW> {
444 unsafe {
445 crate::common::Reg::<self::Lvd1Cr0_SPEC, crate::common::RW>::from_ptr(
446 self._svd2pac_as_ptr().add(1050usize),
447 )
448 }
449 }
450
451 #[doc = "Voltage Monitor 2 Circuit Control Register 0"]
452 #[inline(always)]
453 pub const fn lvd2cr0(
454 &self,
455 ) -> &'static crate::common::Reg<self::Lvd2Cr0_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Lvd2Cr0_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(1051usize),
459 )
460 }
461 }
462
463 #[doc = "Sub-Clock Oscillator Control Register"]
464 #[inline(always)]
465 pub const fn sosccr(
466 &self,
467 ) -> &'static crate::common::Reg<self::Sosccr_SPEC, crate::common::RW> {
468 unsafe {
469 crate::common::Reg::<self::Sosccr_SPEC, crate::common::RW>::from_ptr(
470 self._svd2pac_as_ptr().add(1152usize),
471 )
472 }
473 }
474
475 #[doc = "Sub-Clock Oscillator Mode Control Register"]
476 #[inline(always)]
477 pub const fn somcr(&self) -> &'static crate::common::Reg<self::Somcr_SPEC, crate::common::RW> {
478 unsafe {
479 crate::common::Reg::<self::Somcr_SPEC, crate::common::RW>::from_ptr(
480 self._svd2pac_as_ptr().add(1153usize),
481 )
482 }
483 }
484
485 #[doc = "Sub-Clock Oscillator Margin Check Register"]
486 #[inline(always)]
487 pub const fn somrg(&self) -> &'static crate::common::Reg<self::Somrg_SPEC, crate::common::RW> {
488 unsafe {
489 crate::common::Reg::<self::Somrg_SPEC, crate::common::RW>::from_ptr(
490 self._svd2pac_as_ptr().add(1154usize),
491 )
492 }
493 }
494
495 #[doc = "Low-Speed On-Chip Oscillator Control Register"]
496 #[inline(always)]
497 pub const fn lococr(
498 &self,
499 ) -> &'static crate::common::Reg<self::Lococr_SPEC, crate::common::RW> {
500 unsafe {
501 crate::common::Reg::<self::Lococr_SPEC, crate::common::RW>::from_ptr(
502 self._svd2pac_as_ptr().add(1168usize),
503 )
504 }
505 }
506
507 #[doc = "LOCO User Trimming Control Register"]
508 #[inline(always)]
509 pub const fn locoutcr(
510 &self,
511 ) -> &'static crate::common::Reg<self::Locoutcr_SPEC, crate::common::RW> {
512 unsafe {
513 crate::common::Reg::<self::Locoutcr_SPEC, crate::common::RW>::from_ptr(
514 self._svd2pac_as_ptr().add(1170usize),
515 )
516 }
517 }
518}
519#[doc(hidden)]
520#[derive(Copy, Clone, Eq, PartialEq)]
521pub struct Sbycr_SPEC;
522impl crate::sealed::RegSpec for Sbycr_SPEC {
523 type DataType = u16;
524}
525
526#[doc = "Standby Control Register"]
527pub type Sbycr = crate::RegValueT<Sbycr_SPEC>;
528
529impl Sbycr {
530 #[doc = "Software Standby Mode Select"]
531 #[inline(always)]
532 pub fn ssby(
533 self,
534 ) -> crate::common::RegisterField<
535 15,
536 0x1,
537 1,
538 0,
539 sbycr::Ssby,
540 sbycr::Ssby,
541 Sbycr_SPEC,
542 crate::common::RW,
543 > {
544 crate::common::RegisterField::<
545 15,
546 0x1,
547 1,
548 0,
549 sbycr::Ssby,
550 sbycr::Ssby,
551 Sbycr_SPEC,
552 crate::common::RW,
553 >::from_register(self, 0)
554 }
555}
556impl ::core::default::Default for Sbycr {
557 #[inline(always)]
558 fn default() -> Sbycr {
559 <crate::RegValueT<Sbycr_SPEC> as RegisterValue<_>>::new(0)
560 }
561}
562pub mod sbycr {
563
564 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
565 pub struct Ssby_SPEC;
566 pub type Ssby = crate::EnumBitfieldStruct<u8, Ssby_SPEC>;
567 impl Ssby {
568 #[doc = "Sleep mode"]
569 pub const _0: Self = Self::new(0);
570
571 #[doc = "Software Standby mode."]
572 pub const _1: Self = Self::new(1);
573 }
574}
575#[doc(hidden)]
576#[derive(Copy, Clone, Eq, PartialEq)]
577pub struct Mstpcra_SPEC;
578impl crate::sealed::RegSpec for Mstpcra_SPEC {
579 type DataType = u32;
580}
581
582#[doc = "Module Stop Control Register A"]
583pub type Mstpcra = crate::RegValueT<Mstpcra_SPEC>;
584
585impl Mstpcra {
586 #[doc = "DTC Module Stop"]
587 #[inline(always)]
588 pub fn mstpa22(
589 self,
590 ) -> crate::common::RegisterField<
591 22,
592 0x1,
593 1,
594 0,
595 mstpcra::Mstpa22,
596 mstpcra::Mstpa22,
597 Mstpcra_SPEC,
598 crate::common::RW,
599 > {
600 crate::common::RegisterField::<
601 22,
602 0x1,
603 1,
604 0,
605 mstpcra::Mstpa22,
606 mstpcra::Mstpa22,
607 Mstpcra_SPEC,
608 crate::common::RW,
609 >::from_register(self, 0)
610 }
611}
612impl ::core::default::Default for Mstpcra {
613 #[inline(always)]
614 fn default() -> Mstpcra {
615 <crate::RegValueT<Mstpcra_SPEC> as RegisterValue<_>>::new(4290772991)
616 }
617}
618pub mod mstpcra {
619
620 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
621 pub struct Mstpa22_SPEC;
622 pub type Mstpa22 = crate::EnumBitfieldStruct<u8, Mstpa22_SPEC>;
623 impl Mstpa22 {
624 #[doc = "Cancel the module-stop state"]
625 pub const _0: Self = Self::new(0);
626
627 #[doc = "Enter the module-stop state"]
628 pub const _1: Self = Self::new(1);
629 }
630}
631#[doc(hidden)]
632#[derive(Copy, Clone, Eq, PartialEq)]
633pub struct Sckdivcr_SPEC;
634impl crate::sealed::RegSpec for Sckdivcr_SPEC {
635 type DataType = u32;
636}
637
638#[doc = "System Clock Division Control Register"]
639pub type Sckdivcr = crate::RegValueT<Sckdivcr_SPEC>;
640
641impl Sckdivcr {
642 #[doc = "Peripheral Module Clock D (PCLKD) Select"]
643 #[inline(always)]
644 pub fn pckd(
645 self,
646 ) -> crate::common::RegisterField<
647 0,
648 0x7,
649 1,
650 0,
651 sckdivcr::Pckd,
652 sckdivcr::Pckd,
653 Sckdivcr_SPEC,
654 crate::common::RW,
655 > {
656 crate::common::RegisterField::<
657 0,
658 0x7,
659 1,
660 0,
661 sckdivcr::Pckd,
662 sckdivcr::Pckd,
663 Sckdivcr_SPEC,
664 crate::common::RW,
665 >::from_register(self, 0)
666 }
667
668 #[doc = "Peripheral Module Clock B (PCLKB) Select"]
669 #[inline(always)]
670 pub fn pckb(
671 self,
672 ) -> crate::common::RegisterField<
673 8,
674 0x7,
675 1,
676 0,
677 sckdivcr::Pckb,
678 sckdivcr::Pckb,
679 Sckdivcr_SPEC,
680 crate::common::RW,
681 > {
682 crate::common::RegisterField::<
683 8,
684 0x7,
685 1,
686 0,
687 sckdivcr::Pckb,
688 sckdivcr::Pckb,
689 Sckdivcr_SPEC,
690 crate::common::RW,
691 >::from_register(self, 0)
692 }
693
694 #[doc = "System Clock (ICLK) Select"]
695 #[inline(always)]
696 pub fn ick(
697 self,
698 ) -> crate::common::RegisterField<
699 24,
700 0x7,
701 1,
702 0,
703 sckdivcr::Ick,
704 sckdivcr::Ick,
705 Sckdivcr_SPEC,
706 crate::common::RW,
707 > {
708 crate::common::RegisterField::<
709 24,
710 0x7,
711 1,
712 0,
713 sckdivcr::Ick,
714 sckdivcr::Ick,
715 Sckdivcr_SPEC,
716 crate::common::RW,
717 >::from_register(self, 0)
718 }
719}
720impl ::core::default::Default for Sckdivcr {
721 #[inline(always)]
722 fn default() -> Sckdivcr {
723 <crate::RegValueT<Sckdivcr_SPEC> as RegisterValue<_>>::new(67109892)
724 }
725}
726pub mod sckdivcr {
727
728 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
729 pub struct Pckd_SPEC;
730 pub type Pckd = crate::EnumBitfieldStruct<u8, Pckd_SPEC>;
731 impl Pckd {
732 #[doc = "x 1/1"]
733 pub const _000: Self = Self::new(0);
734
735 #[doc = "x 1/2"]
736 pub const _001: Self = Self::new(1);
737
738 #[doc = "x 1/4"]
739 pub const _010: Self = Self::new(2);
740
741 #[doc = "x 1/8"]
742 pub const _011: Self = Self::new(3);
743
744 #[doc = "x 1/16"]
745 pub const _100: Self = Self::new(4);
746
747 #[doc = "x 1/32"]
748 pub const _101: Self = Self::new(5);
749
750 #[doc = "x 1/64"]
751 pub const _110: Self = Self::new(6);
752 }
753 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
754 pub struct Pckb_SPEC;
755 pub type Pckb = crate::EnumBitfieldStruct<u8, Pckb_SPEC>;
756 impl Pckb {
757 #[doc = "x 1/1"]
758 pub const _000: Self = Self::new(0);
759
760 #[doc = "x 1/2"]
761 pub const _001: Self = Self::new(1);
762
763 #[doc = "x 1/4"]
764 pub const _010: Self = Self::new(2);
765
766 #[doc = "x 1/8"]
767 pub const _011: Self = Self::new(3);
768
769 #[doc = "x 1/16"]
770 pub const _100: Self = Self::new(4);
771
772 #[doc = "x 1/32"]
773 pub const _101: Self = Self::new(5);
774
775 #[doc = "x 1/64"]
776 pub const _110: Self = Self::new(6);
777 }
778 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
779 pub struct Ick_SPEC;
780 pub type Ick = crate::EnumBitfieldStruct<u8, Ick_SPEC>;
781 impl Ick {
782 #[doc = "x 1/1"]
783 pub const _000: Self = Self::new(0);
784
785 #[doc = "x 1/2"]
786 pub const _001: Self = Self::new(1);
787
788 #[doc = "x 1/4"]
789 pub const _010: Self = Self::new(2);
790
791 #[doc = "x 1/8"]
792 pub const _011: Self = Self::new(3);
793
794 #[doc = "x 1/16"]
795 pub const _100: Self = Self::new(4);
796
797 #[doc = "x 1/32"]
798 pub const _101: Self = Self::new(5);
799
800 #[doc = "x 1/64"]
801 pub const _110: Self = Self::new(6);
802 }
803}
804#[doc(hidden)]
805#[derive(Copy, Clone, Eq, PartialEq)]
806pub struct Sckscr_SPEC;
807impl crate::sealed::RegSpec for Sckscr_SPEC {
808 type DataType = u8;
809}
810
811#[doc = "System Clock Source Control Register"]
812pub type Sckscr = crate::RegValueT<Sckscr_SPEC>;
813
814impl Sckscr {
815 #[doc = "Clock Source Select"]
816 #[inline(always)]
817 pub fn cksel(
818 self,
819 ) -> crate::common::RegisterField<
820 0,
821 0x7,
822 1,
823 0,
824 sckscr::Cksel,
825 sckscr::Cksel,
826 Sckscr_SPEC,
827 crate::common::RW,
828 > {
829 crate::common::RegisterField::<
830 0,
831 0x7,
832 1,
833 0,
834 sckscr::Cksel,
835 sckscr::Cksel,
836 Sckscr_SPEC,
837 crate::common::RW,
838 >::from_register(self, 0)
839 }
840}
841impl ::core::default::Default for Sckscr {
842 #[inline(always)]
843 fn default() -> Sckscr {
844 <crate::RegValueT<Sckscr_SPEC> as RegisterValue<_>>::new(1)
845 }
846}
847pub mod sckscr {
848
849 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
850 pub struct Cksel_SPEC;
851 pub type Cksel = crate::EnumBitfieldStruct<u8, Cksel_SPEC>;
852 impl Cksel {
853 #[doc = "HOCO"]
854 pub const _000: Self = Self::new(0);
855
856 #[doc = "MOCO"]
857 pub const _001: Self = Self::new(1);
858
859 #[doc = "LOCO"]
860 pub const _010: Self = Self::new(2);
861
862 #[doc = "Main clock oscillator (MOSC)"]
863 pub const _011: Self = Self::new(3);
864
865 #[doc = "Sub-clock oscillator (SOSC)"]
866 pub const _100: Self = Self::new(4);
867
868 #[doc = "Setting prohibited"]
869 pub const _101: Self = Self::new(5);
870
871 #[doc = "Setting prohibited"]
872 pub const _110: Self = Self::new(6);
873
874 #[doc = "Setting prohibited"]
875 pub const _111: Self = Self::new(7);
876 }
877}
878#[doc(hidden)]
879#[derive(Copy, Clone, Eq, PartialEq)]
880pub struct Memwait_SPEC;
881impl crate::sealed::RegSpec for Memwait_SPEC {
882 type DataType = u8;
883}
884
885#[doc = "Memory Wait Cycle Control Register for Code Flash"]
886pub type Memwait = crate::RegValueT<Memwait_SPEC>;
887
888impl Memwait {
889 #[doc = "Memory Wait Cycle Select for Code Flash"]
890 #[inline(always)]
891 pub fn memwait(
892 self,
893 ) -> crate::common::RegisterField<
894 0,
895 0x1,
896 1,
897 0,
898 memwait::Memwait,
899 memwait::Memwait,
900 Memwait_SPEC,
901 crate::common::RW,
902 > {
903 crate::common::RegisterField::<
904 0,
905 0x1,
906 1,
907 0,
908 memwait::Memwait,
909 memwait::Memwait,
910 Memwait_SPEC,
911 crate::common::RW,
912 >::from_register(self, 0)
913 }
914}
915impl ::core::default::Default for Memwait {
916 #[inline(always)]
917 fn default() -> Memwait {
918 <crate::RegValueT<Memwait_SPEC> as RegisterValue<_>>::new(0)
919 }
920}
921pub mod memwait {
922
923 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
924 pub struct Memwait_SPEC;
925 pub type Memwait = crate::EnumBitfieldStruct<u8, Memwait_SPEC>;
926 impl Memwait {
927 #[doc = "No wait"]
928 pub const _0: Self = Self::new(0);
929
930 #[doc = "Wait"]
931 pub const _1: Self = Self::new(1);
932 }
933}
934#[doc(hidden)]
935#[derive(Copy, Clone, Eq, PartialEq)]
936pub struct Mosccr_SPEC;
937impl crate::sealed::RegSpec for Mosccr_SPEC {
938 type DataType = u8;
939}
940
941#[doc = "Main Clock Oscillator Control Register"]
942pub type Mosccr = crate::RegValueT<Mosccr_SPEC>;
943
944impl Mosccr {
945 #[doc = "Main Clock Oscillator Stop"]
946 #[inline(always)]
947 pub fn mostp(
948 self,
949 ) -> crate::common::RegisterField<
950 0,
951 0x1,
952 1,
953 0,
954 mosccr::Mostp,
955 mosccr::Mostp,
956 Mosccr_SPEC,
957 crate::common::RW,
958 > {
959 crate::common::RegisterField::<
960 0,
961 0x1,
962 1,
963 0,
964 mosccr::Mostp,
965 mosccr::Mostp,
966 Mosccr_SPEC,
967 crate::common::RW,
968 >::from_register(self, 0)
969 }
970}
971impl ::core::default::Default for Mosccr {
972 #[inline(always)]
973 fn default() -> Mosccr {
974 <crate::RegValueT<Mosccr_SPEC> as RegisterValue<_>>::new(1)
975 }
976}
977pub mod mosccr {
978
979 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
980 pub struct Mostp_SPEC;
981 pub type Mostp = crate::EnumBitfieldStruct<u8, Mostp_SPEC>;
982 impl Mostp {
983 #[doc = "Operate the main clock oscillator"]
984 pub const _0: Self = Self::new(0);
985
986 #[doc = "Stop the main clock oscillator"]
987 pub const _1: Self = Self::new(1);
988 }
989}
990#[doc(hidden)]
991#[derive(Copy, Clone, Eq, PartialEq)]
992pub struct Hococr_SPEC;
993impl crate::sealed::RegSpec for Hococr_SPEC {
994 type DataType = u8;
995}
996
997#[doc = "High-Speed On-Chip Oscillator Control Register"]
998pub type Hococr = crate::RegValueT<Hococr_SPEC>;
999
1000impl Hococr {
1001 #[doc = "HOCO Stop"]
1002 #[inline(always)]
1003 pub fn hcstp(
1004 self,
1005 ) -> crate::common::RegisterField<
1006 0,
1007 0x1,
1008 1,
1009 0,
1010 hococr::Hcstp,
1011 hococr::Hcstp,
1012 Hococr_SPEC,
1013 crate::common::RW,
1014 > {
1015 crate::common::RegisterField::<
1016 0,
1017 0x1,
1018 1,
1019 0,
1020 hococr::Hcstp,
1021 hococr::Hcstp,
1022 Hococr_SPEC,
1023 crate::common::RW,
1024 >::from_register(self, 0)
1025 }
1026}
1027impl ::core::default::Default for Hococr {
1028 #[inline(always)]
1029 fn default() -> Hococr {
1030 <crate::RegValueT<Hococr_SPEC> as RegisterValue<_>>::new(0)
1031 }
1032}
1033pub mod hococr {
1034
1035 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1036 pub struct Hcstp_SPEC;
1037 pub type Hcstp = crate::EnumBitfieldStruct<u8, Hcstp_SPEC>;
1038 impl Hcstp {
1039 #[doc = "Operate the HOCO clock"]
1040 pub const _0: Self = Self::new(0);
1041
1042 #[doc = "Stop the HOCO clock"]
1043 pub const _1: Self = Self::new(1);
1044 }
1045}
1046#[doc(hidden)]
1047#[derive(Copy, Clone, Eq, PartialEq)]
1048pub struct Mococr_SPEC;
1049impl crate::sealed::RegSpec for Mococr_SPEC {
1050 type DataType = u8;
1051}
1052
1053#[doc = "Middle-Speed On-Chip Oscillator Control Register"]
1054pub type Mococr = crate::RegValueT<Mococr_SPEC>;
1055
1056impl Mococr {
1057 #[doc = "MOCO Stop"]
1058 #[inline(always)]
1059 pub fn mcstp(
1060 self,
1061 ) -> crate::common::RegisterField<
1062 0,
1063 0x1,
1064 1,
1065 0,
1066 mococr::Mcstp,
1067 mococr::Mcstp,
1068 Mococr_SPEC,
1069 crate::common::RW,
1070 > {
1071 crate::common::RegisterField::<
1072 0,
1073 0x1,
1074 1,
1075 0,
1076 mococr::Mcstp,
1077 mococr::Mcstp,
1078 Mococr_SPEC,
1079 crate::common::RW,
1080 >::from_register(self, 0)
1081 }
1082}
1083impl ::core::default::Default for Mococr {
1084 #[inline(always)]
1085 fn default() -> Mococr {
1086 <crate::RegValueT<Mococr_SPEC> as RegisterValue<_>>::new(0)
1087 }
1088}
1089pub mod mococr {
1090
1091 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1092 pub struct Mcstp_SPEC;
1093 pub type Mcstp = crate::EnumBitfieldStruct<u8, Mcstp_SPEC>;
1094 impl Mcstp {
1095 #[doc = "MOCO clock is operating"]
1096 pub const _0: Self = Self::new(0);
1097
1098 #[doc = "MOCO clock is stopped"]
1099 pub const _1: Self = Self::new(1);
1100 }
1101}
1102#[doc(hidden)]
1103#[derive(Copy, Clone, Eq, PartialEq)]
1104pub struct Oscsf_SPEC;
1105impl crate::sealed::RegSpec for Oscsf_SPEC {
1106 type DataType = u8;
1107}
1108
1109#[doc = "Oscillation Stabilization Flag Register"]
1110pub type Oscsf = crate::RegValueT<Oscsf_SPEC>;
1111
1112impl Oscsf {
1113 #[doc = "HOCO Clock Oscillation Stabilization Flag"]
1114 #[inline(always)]
1115 pub fn hocosf(
1116 self,
1117 ) -> crate::common::RegisterField<
1118 0,
1119 0x1,
1120 1,
1121 0,
1122 oscsf::Hocosf,
1123 oscsf::Hocosf,
1124 Oscsf_SPEC,
1125 crate::common::R,
1126 > {
1127 crate::common::RegisterField::<
1128 0,
1129 0x1,
1130 1,
1131 0,
1132 oscsf::Hocosf,
1133 oscsf::Hocosf,
1134 Oscsf_SPEC,
1135 crate::common::R,
1136 >::from_register(self, 0)
1137 }
1138
1139 #[doc = "Main Clock Oscillation Stabilization Flag"]
1140 #[inline(always)]
1141 pub fn moscsf(
1142 self,
1143 ) -> crate::common::RegisterField<
1144 3,
1145 0x1,
1146 1,
1147 0,
1148 oscsf::Moscsf,
1149 oscsf::Moscsf,
1150 Oscsf_SPEC,
1151 crate::common::R,
1152 > {
1153 crate::common::RegisterField::<
1154 3,
1155 0x1,
1156 1,
1157 0,
1158 oscsf::Moscsf,
1159 oscsf::Moscsf,
1160 Oscsf_SPEC,
1161 crate::common::R,
1162 >::from_register(self, 0)
1163 }
1164}
1165impl ::core::default::Default for Oscsf {
1166 #[inline(always)]
1167 fn default() -> Oscsf {
1168 <crate::RegValueT<Oscsf_SPEC> as RegisterValue<_>>::new(0)
1169 }
1170}
1171pub mod oscsf {
1172
1173 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1174 pub struct Hocosf_SPEC;
1175 pub type Hocosf = crate::EnumBitfieldStruct<u8, Hocosf_SPEC>;
1176 impl Hocosf {
1177 #[doc = "The HOCO clock is stopped or is not yet stable"]
1178 pub const _0: Self = Self::new(0);
1179
1180 #[doc = "The HOCO clock is stable, so is available for use as the system clock"]
1181 pub const _1: Self = Self::new(1);
1182 }
1183 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1184 pub struct Moscsf_SPEC;
1185 pub type Moscsf = crate::EnumBitfieldStruct<u8, Moscsf_SPEC>;
1186 impl Moscsf {
1187 #[doc = "The main clock oscillator is stopped (MOSTP = 1) or is not yet stable"]
1188 pub const _0: Self = Self::new(0);
1189
1190 #[doc = "The main clock oscillator is stable, so is available for use as the system clock"]
1191 pub const _1: Self = Self::new(1);
1192 }
1193}
1194#[doc(hidden)]
1195#[derive(Copy, Clone, Eq, PartialEq)]
1196pub struct Ckocr_SPEC;
1197impl crate::sealed::RegSpec for Ckocr_SPEC {
1198 type DataType = u8;
1199}
1200
1201#[doc = "Clock Out Control Register"]
1202pub type Ckocr = crate::RegValueT<Ckocr_SPEC>;
1203
1204impl Ckocr {
1205 #[doc = "Clock Out Source Select"]
1206 #[inline(always)]
1207 pub fn ckosel(
1208 self,
1209 ) -> crate::common::RegisterField<
1210 0,
1211 0x7,
1212 1,
1213 0,
1214 ckocr::Ckosel,
1215 ckocr::Ckosel,
1216 Ckocr_SPEC,
1217 crate::common::RW,
1218 > {
1219 crate::common::RegisterField::<
1220 0,
1221 0x7,
1222 1,
1223 0,
1224 ckocr::Ckosel,
1225 ckocr::Ckosel,
1226 Ckocr_SPEC,
1227 crate::common::RW,
1228 >::from_register(self, 0)
1229 }
1230
1231 #[doc = "Clock Output Frequency Division Ratio"]
1232 #[inline(always)]
1233 pub fn ckodiv(
1234 self,
1235 ) -> crate::common::RegisterField<
1236 4,
1237 0x7,
1238 1,
1239 0,
1240 ckocr::Ckodiv,
1241 ckocr::Ckodiv,
1242 Ckocr_SPEC,
1243 crate::common::RW,
1244 > {
1245 crate::common::RegisterField::<
1246 4,
1247 0x7,
1248 1,
1249 0,
1250 ckocr::Ckodiv,
1251 ckocr::Ckodiv,
1252 Ckocr_SPEC,
1253 crate::common::RW,
1254 >::from_register(self, 0)
1255 }
1256
1257 #[doc = "Clock Out Enable"]
1258 #[inline(always)]
1259 pub fn ckoen(
1260 self,
1261 ) -> crate::common::RegisterField<
1262 7,
1263 0x1,
1264 1,
1265 0,
1266 ckocr::Ckoen,
1267 ckocr::Ckoen,
1268 Ckocr_SPEC,
1269 crate::common::RW,
1270 > {
1271 crate::common::RegisterField::<
1272 7,
1273 0x1,
1274 1,
1275 0,
1276 ckocr::Ckoen,
1277 ckocr::Ckoen,
1278 Ckocr_SPEC,
1279 crate::common::RW,
1280 >::from_register(self, 0)
1281 }
1282}
1283impl ::core::default::Default for Ckocr {
1284 #[inline(always)]
1285 fn default() -> Ckocr {
1286 <crate::RegValueT<Ckocr_SPEC> as RegisterValue<_>>::new(0)
1287 }
1288}
1289pub mod ckocr {
1290
1291 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1292 pub struct Ckosel_SPEC;
1293 pub type Ckosel = crate::EnumBitfieldStruct<u8, Ckosel_SPEC>;
1294 impl Ckosel {
1295 #[doc = "HOCO (value after reset)"]
1296 pub const _000: Self = Self::new(0);
1297
1298 #[doc = "MOCO"]
1299 pub const _001: Self = Self::new(1);
1300
1301 #[doc = "LOCO"]
1302 pub const _010: Self = Self::new(2);
1303
1304 #[doc = "MOSC"]
1305 pub const _011: Self = Self::new(3);
1306
1307 #[doc = "SOSC"]
1308 pub const _100: Self = Self::new(4);
1309
1310 #[doc = "Setting prohibited"]
1311 pub const _101: Self = Self::new(5);
1312 }
1313 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1314 pub struct Ckodiv_SPEC;
1315 pub type Ckodiv = crate::EnumBitfieldStruct<u8, Ckodiv_SPEC>;
1316 impl Ckodiv {
1317 #[doc = "x 1/1"]
1318 pub const _000: Self = Self::new(0);
1319
1320 #[doc = "x 1/2"]
1321 pub const _001: Self = Self::new(1);
1322
1323 #[doc = "x 1/4"]
1324 pub const _010: Self = Self::new(2);
1325
1326 #[doc = "x 1/8"]
1327 pub const _011: Self = Self::new(3);
1328
1329 #[doc = "x 1/16"]
1330 pub const _100: Self = Self::new(4);
1331
1332 #[doc = "x 1/32"]
1333 pub const _101: Self = Self::new(5);
1334
1335 #[doc = "x 1/64"]
1336 pub const _110: Self = Self::new(6);
1337
1338 #[doc = "x 1/128"]
1339 pub const _111: Self = Self::new(7);
1340 }
1341 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1342 pub struct Ckoen_SPEC;
1343 pub type Ckoen = crate::EnumBitfieldStruct<u8, Ckoen_SPEC>;
1344 impl Ckoen {
1345 #[doc = "Disable clock out"]
1346 pub const _0: Self = Self::new(0);
1347
1348 #[doc = "Enable clock out"]
1349 pub const _1: Self = Self::new(1);
1350 }
1351}
1352#[doc(hidden)]
1353#[derive(Copy, Clone, Eq, PartialEq)]
1354pub struct Ostdcr_SPEC;
1355impl crate::sealed::RegSpec for Ostdcr_SPEC {
1356 type DataType = u8;
1357}
1358
1359#[doc = "Oscillation Stop Detection Control Register"]
1360pub type Ostdcr = crate::RegValueT<Ostdcr_SPEC>;
1361
1362impl Ostdcr {
1363 #[doc = "Oscillation Stop Detection Interrupt Enable"]
1364 #[inline(always)]
1365 pub fn ostdie(
1366 self,
1367 ) -> crate::common::RegisterField<
1368 0,
1369 0x1,
1370 1,
1371 0,
1372 ostdcr::Ostdie,
1373 ostdcr::Ostdie,
1374 Ostdcr_SPEC,
1375 crate::common::RW,
1376 > {
1377 crate::common::RegisterField::<
1378 0,
1379 0x1,
1380 1,
1381 0,
1382 ostdcr::Ostdie,
1383 ostdcr::Ostdie,
1384 Ostdcr_SPEC,
1385 crate::common::RW,
1386 >::from_register(self, 0)
1387 }
1388
1389 #[doc = "Oscillation Stop Detection Function Enable"]
1390 #[inline(always)]
1391 pub fn ostde(
1392 self,
1393 ) -> crate::common::RegisterField<
1394 7,
1395 0x1,
1396 1,
1397 0,
1398 ostdcr::Ostde,
1399 ostdcr::Ostde,
1400 Ostdcr_SPEC,
1401 crate::common::RW,
1402 > {
1403 crate::common::RegisterField::<
1404 7,
1405 0x1,
1406 1,
1407 0,
1408 ostdcr::Ostde,
1409 ostdcr::Ostde,
1410 Ostdcr_SPEC,
1411 crate::common::RW,
1412 >::from_register(self, 0)
1413 }
1414}
1415impl ::core::default::Default for Ostdcr {
1416 #[inline(always)]
1417 fn default() -> Ostdcr {
1418 <crate::RegValueT<Ostdcr_SPEC> as RegisterValue<_>>::new(0)
1419 }
1420}
1421pub mod ostdcr {
1422
1423 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1424 pub struct Ostdie_SPEC;
1425 pub type Ostdie = crate::EnumBitfieldStruct<u8, Ostdie_SPEC>;
1426 impl Ostdie {
1427 #[doc = "Disable oscillation stop detection interrupt (do not notify the POEG)"]
1428 pub const _0: Self = Self::new(0);
1429
1430 #[doc = "Enable oscillation stop detection interrupt (notify the POEG)"]
1431 pub const _1: Self = Self::new(1);
1432 }
1433 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1434 pub struct Ostde_SPEC;
1435 pub type Ostde = crate::EnumBitfieldStruct<u8, Ostde_SPEC>;
1436 impl Ostde {
1437 #[doc = "Disable oscillation stop detection function"]
1438 pub const _0: Self = Self::new(0);
1439
1440 #[doc = "Enable oscillation stop detection function"]
1441 pub const _1: Self = Self::new(1);
1442 }
1443}
1444#[doc(hidden)]
1445#[derive(Copy, Clone, Eq, PartialEq)]
1446pub struct Ostdsr_SPEC;
1447impl crate::sealed::RegSpec for Ostdsr_SPEC {
1448 type DataType = u8;
1449}
1450
1451#[doc = "Oscillation Stop Detection Status Register"]
1452pub type Ostdsr = crate::RegValueT<Ostdsr_SPEC>;
1453
1454impl Ostdsr {
1455 #[doc = "Oscillation Stop Detection Flag"]
1456 #[inline(always)]
1457 pub fn ostdf(
1458 self,
1459 ) -> crate::common::RegisterField<
1460 0,
1461 0x1,
1462 1,
1463 0,
1464 ostdsr::Ostdf,
1465 ostdsr::Ostdf,
1466 Ostdsr_SPEC,
1467 crate::common::RW,
1468 > {
1469 crate::common::RegisterField::<
1470 0,
1471 0x1,
1472 1,
1473 0,
1474 ostdsr::Ostdf,
1475 ostdsr::Ostdf,
1476 Ostdsr_SPEC,
1477 crate::common::RW,
1478 >::from_register(self, 0)
1479 }
1480}
1481impl ::core::default::Default for Ostdsr {
1482 #[inline(always)]
1483 fn default() -> Ostdsr {
1484 <crate::RegValueT<Ostdsr_SPEC> as RegisterValue<_>>::new(0)
1485 }
1486}
1487pub mod ostdsr {
1488
1489 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1490 pub struct Ostdf_SPEC;
1491 pub type Ostdf = crate::EnumBitfieldStruct<u8, Ostdf_SPEC>;
1492 impl Ostdf {
1493 #[doc = "Main clock oscillation stop not detected"]
1494 pub const _0: Self = Self::new(0);
1495
1496 #[doc = "Main clock oscillation stop detected"]
1497 pub const _1: Self = Self::new(1);
1498 }
1499}
1500#[doc(hidden)]
1501#[derive(Copy, Clone, Eq, PartialEq)]
1502pub struct Lpopt_SPEC;
1503impl crate::sealed::RegSpec for Lpopt_SPEC {
1504 type DataType = u8;
1505}
1506
1507#[doc = "Lower Power Operation Control Register"]
1508pub type Lpopt = crate::RegValueT<Lpopt_SPEC>;
1509
1510impl Lpopt {
1511 #[doc = "MPU Clock Disable Control"]
1512 #[inline(always)]
1513 pub fn mpudis(
1514 self,
1515 ) -> crate::common::RegisterField<
1516 0,
1517 0x1,
1518 1,
1519 0,
1520 lpopt::Mpudis,
1521 lpopt::Mpudis,
1522 Lpopt_SPEC,
1523 crate::common::RW,
1524 > {
1525 crate::common::RegisterField::<
1526 0,
1527 0x1,
1528 1,
1529 0,
1530 lpopt::Mpudis,
1531 lpopt::Mpudis,
1532 Lpopt_SPEC,
1533 crate::common::RW,
1534 >::from_register(self, 0)
1535 }
1536
1537 #[doc = "Debug Clock Disable Control"]
1538 #[inline(always)]
1539 pub fn dclkdis(
1540 self,
1541 ) -> crate::common::RegisterField<
1542 1,
1543 0x3,
1544 1,
1545 0,
1546 lpopt::Dclkdis,
1547 lpopt::Dclkdis,
1548 Lpopt_SPEC,
1549 crate::common::RW,
1550 > {
1551 crate::common::RegisterField::<
1552 1,
1553 0x3,
1554 1,
1555 0,
1556 lpopt::Dclkdis,
1557 lpopt::Dclkdis,
1558 Lpopt_SPEC,
1559 crate::common::RW,
1560 >::from_register(self, 0)
1561 }
1562
1563 #[doc = "BPF Clock Disable Control"]
1564 #[inline(always)]
1565 pub fn bpfclkdis(
1566 self,
1567 ) -> crate::common::RegisterField<
1568 3,
1569 0x1,
1570 1,
1571 0,
1572 lpopt::Bpfclkdis,
1573 lpopt::Bpfclkdis,
1574 Lpopt_SPEC,
1575 crate::common::RW,
1576 > {
1577 crate::common::RegisterField::<
1578 3,
1579 0x1,
1580 1,
1581 0,
1582 lpopt::Bpfclkdis,
1583 lpopt::Bpfclkdis,
1584 Lpopt_SPEC,
1585 crate::common::RW,
1586 >::from_register(self, 0)
1587 }
1588
1589 #[doc = "Lower Power Operation Enable"]
1590 #[inline(always)]
1591 pub fn lpopten(
1592 self,
1593 ) -> crate::common::RegisterField<
1594 7,
1595 0x1,
1596 1,
1597 0,
1598 lpopt::Lpopten,
1599 lpopt::Lpopten,
1600 Lpopt_SPEC,
1601 crate::common::RW,
1602 > {
1603 crate::common::RegisterField::<
1604 7,
1605 0x1,
1606 1,
1607 0,
1608 lpopt::Lpopten,
1609 lpopt::Lpopten,
1610 Lpopt_SPEC,
1611 crate::common::RW,
1612 >::from_register(self, 0)
1613 }
1614}
1615impl ::core::default::Default for Lpopt {
1616 #[inline(always)]
1617 fn default() -> Lpopt {
1618 <crate::RegValueT<Lpopt_SPEC> as RegisterValue<_>>::new(64)
1619 }
1620}
1621pub mod lpopt {
1622
1623 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1624 pub struct Mpudis_SPEC;
1625 pub type Mpudis = crate::EnumBitfieldStruct<u8, Mpudis_SPEC>;
1626 impl Mpudis {
1627 #[doc = "MPU operates as normal"]
1628 pub const _0: Self = Self::new(0);
1629
1630 #[doc = "MPU operate clock stops (MPU function disable)."]
1631 pub const _1: Self = Self::new(1);
1632 }
1633 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1634 pub struct Dclkdis_SPEC;
1635 pub type Dclkdis = crate::EnumBitfieldStruct<u8, Dclkdis_SPEC>;
1636 impl Dclkdis {
1637 #[doc = "Debug clock does not stop"]
1638 pub const _00: Self = Self::new(0);
1639 }
1640 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1641 pub struct Bpfclkdis_SPEC;
1642 pub type Bpfclkdis = crate::EnumBitfieldStruct<u8, Bpfclkdis_SPEC>;
1643 impl Bpfclkdis {
1644 #[doc = "Flash register R/W clock operates as normal"]
1645 pub const _0: Self = Self::new(0);
1646
1647 #[doc = "Flash register R/W clock stops."]
1648 pub const _1: Self = Self::new(1);
1649 }
1650 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1651 pub struct Lpopten_SPEC;
1652 pub type Lpopten = crate::EnumBitfieldStruct<u8, Lpopten_SPEC>;
1653 impl Lpopten {
1654 #[doc = "All lower power counter measure disable"]
1655 pub const _0: Self = Self::new(0);
1656
1657 #[doc = "All lower power counter measure enable"]
1658 pub const _1: Self = Self::new(1);
1659 }
1660}
1661#[doc(hidden)]
1662#[derive(Copy, Clone, Eq, PartialEq)]
1663pub struct Mocoutcr_SPEC;
1664impl crate::sealed::RegSpec for Mocoutcr_SPEC {
1665 type DataType = u8;
1666}
1667
1668#[doc = "MOCO User Trimming Control Register"]
1669pub type Mocoutcr = crate::RegValueT<Mocoutcr_SPEC>;
1670
1671impl Mocoutcr {
1672 #[doc = "MOCO User Trimming"]
1673 #[inline(always)]
1674 pub fn mocoutrm(
1675 self,
1676 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Mocoutcr_SPEC, crate::common::RW> {
1677 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Mocoutcr_SPEC,crate::common::RW>::from_register(self,0)
1678 }
1679}
1680impl ::core::default::Default for Mocoutcr {
1681 #[inline(always)]
1682 fn default() -> Mocoutcr {
1683 <crate::RegValueT<Mocoutcr_SPEC> as RegisterValue<_>>::new(0)
1684 }
1685}
1686
1687#[doc(hidden)]
1688#[derive(Copy, Clone, Eq, PartialEq)]
1689pub struct Hocoutcr_SPEC;
1690impl crate::sealed::RegSpec for Hocoutcr_SPEC {
1691 type DataType = u8;
1692}
1693
1694#[doc = "HOCO User Trimming Control Register"]
1695pub type Hocoutcr = crate::RegValueT<Hocoutcr_SPEC>;
1696
1697impl Hocoutcr {
1698 #[doc = "HOCO User Trimming"]
1699 #[inline(always)]
1700 pub fn hocoutrm(
1701 self,
1702 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Hocoutcr_SPEC, crate::common::RW> {
1703 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Hocoutcr_SPEC,crate::common::RW>::from_register(self,0)
1704 }
1705}
1706impl ::core::default::Default for Hocoutcr {
1707 #[inline(always)]
1708 fn default() -> Hocoutcr {
1709 <crate::RegValueT<Hocoutcr_SPEC> as RegisterValue<_>>::new(0)
1710 }
1711}
1712
1713#[doc(hidden)]
1714#[derive(Copy, Clone, Eq, PartialEq)]
1715pub struct Snzcr_SPEC;
1716impl crate::sealed::RegSpec for Snzcr_SPEC {
1717 type DataType = u8;
1718}
1719
1720#[doc = "Snooze Control Register"]
1721pub type Snzcr = crate::RegValueT<Snzcr_SPEC>;
1722
1723impl Snzcr {
1724 #[doc = "RXD0 Snooze Request Enable"]
1725 #[inline(always)]
1726 pub fn rxdreqen(
1727 self,
1728 ) -> crate::common::RegisterField<
1729 0,
1730 0x1,
1731 1,
1732 0,
1733 snzcr::Rxdreqen,
1734 snzcr::Rxdreqen,
1735 Snzcr_SPEC,
1736 crate::common::RW,
1737 > {
1738 crate::common::RegisterField::<
1739 0,
1740 0x1,
1741 1,
1742 0,
1743 snzcr::Rxdreqen,
1744 snzcr::Rxdreqen,
1745 Snzcr_SPEC,
1746 crate::common::RW,
1747 >::from_register(self, 0)
1748 }
1749
1750 #[doc = "DTC Enable in Snooze mode"]
1751 #[inline(always)]
1752 pub fn snzdtcen(
1753 self,
1754 ) -> crate::common::RegisterField<
1755 1,
1756 0x1,
1757 1,
1758 0,
1759 snzcr::Snzdtcen,
1760 snzcr::Snzdtcen,
1761 Snzcr_SPEC,
1762 crate::common::RW,
1763 > {
1764 crate::common::RegisterField::<
1765 1,
1766 0x1,
1767 1,
1768 0,
1769 snzcr::Snzdtcen,
1770 snzcr::Snzdtcen,
1771 Snzcr_SPEC,
1772 crate::common::RW,
1773 >::from_register(self, 0)
1774 }
1775
1776 #[doc = "Snooze mode Enable"]
1777 #[inline(always)]
1778 pub fn snze(
1779 self,
1780 ) -> crate::common::RegisterField<
1781 7,
1782 0x1,
1783 1,
1784 0,
1785 snzcr::Snze,
1786 snzcr::Snze,
1787 Snzcr_SPEC,
1788 crate::common::RW,
1789 > {
1790 crate::common::RegisterField::<
1791 7,
1792 0x1,
1793 1,
1794 0,
1795 snzcr::Snze,
1796 snzcr::Snze,
1797 Snzcr_SPEC,
1798 crate::common::RW,
1799 >::from_register(self, 0)
1800 }
1801}
1802impl ::core::default::Default for Snzcr {
1803 #[inline(always)]
1804 fn default() -> Snzcr {
1805 <crate::RegValueT<Snzcr_SPEC> as RegisterValue<_>>::new(0)
1806 }
1807}
1808pub mod snzcr {
1809
1810 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1811 pub struct Rxdreqen_SPEC;
1812 pub type Rxdreqen = crate::EnumBitfieldStruct<u8, Rxdreqen_SPEC>;
1813 impl Rxdreqen {
1814 #[doc = "Ignore RXD0 falling edge in Software Standby mode"]
1815 pub const _0: Self = Self::new(0);
1816
1817 #[doc = "Detect RXD0 falling edge in Software Standby mode"]
1818 pub const _1: Self = Self::new(1);
1819 }
1820 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1821 pub struct Snzdtcen_SPEC;
1822 pub type Snzdtcen = crate::EnumBitfieldStruct<u8, Snzdtcen_SPEC>;
1823 impl Snzdtcen {
1824 #[doc = "Disable DTC operation"]
1825 pub const _0: Self = Self::new(0);
1826
1827 #[doc = "Enable DTC operation"]
1828 pub const _1: Self = Self::new(1);
1829 }
1830 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1831 pub struct Snze_SPEC;
1832 pub type Snze = crate::EnumBitfieldStruct<u8, Snze_SPEC>;
1833 impl Snze {
1834 #[doc = "Disable Snooze mode"]
1835 pub const _0: Self = Self::new(0);
1836
1837 #[doc = "Enable Snooze mode"]
1838 pub const _1: Self = Self::new(1);
1839 }
1840}
1841#[doc(hidden)]
1842#[derive(Copy, Clone, Eq, PartialEq)]
1843pub struct Snzedcr0_SPEC;
1844impl crate::sealed::RegSpec for Snzedcr0_SPEC {
1845 type DataType = u8;
1846}
1847
1848#[doc = "Snooze End Control Register 0"]
1849pub type Snzedcr0 = crate::RegValueT<Snzedcr0_SPEC>;
1850
1851impl Snzedcr0 {
1852 #[doc = "AGT1 Underflow Snooze End Enable"]
1853 #[inline(always)]
1854 pub fn agtunfed(
1855 self,
1856 ) -> crate::common::RegisterField<
1857 0,
1858 0x1,
1859 1,
1860 0,
1861 snzedcr0::Agtunfed,
1862 snzedcr0::Agtunfed,
1863 Snzedcr0_SPEC,
1864 crate::common::RW,
1865 > {
1866 crate::common::RegisterField::<
1867 0,
1868 0x1,
1869 1,
1870 0,
1871 snzedcr0::Agtunfed,
1872 snzedcr0::Agtunfed,
1873 Snzedcr0_SPEC,
1874 crate::common::RW,
1875 >::from_register(self, 0)
1876 }
1877
1878 #[doc = "Last DTC Transmission Completion Snooze End Enable"]
1879 #[inline(always)]
1880 pub fn dtczred(
1881 self,
1882 ) -> crate::common::RegisterField<
1883 1,
1884 0x1,
1885 1,
1886 0,
1887 snzedcr0::Dtczred,
1888 snzedcr0::Dtczred,
1889 Snzedcr0_SPEC,
1890 crate::common::RW,
1891 > {
1892 crate::common::RegisterField::<
1893 1,
1894 0x1,
1895 1,
1896 0,
1897 snzedcr0::Dtczred,
1898 snzedcr0::Dtczred,
1899 Snzedcr0_SPEC,
1900 crate::common::RW,
1901 >::from_register(self, 0)
1902 }
1903
1904 #[doc = "Not Last DTC Transmission Completion Snooze End Enable"]
1905 #[inline(always)]
1906 pub fn dtcnzred(
1907 self,
1908 ) -> crate::common::RegisterField<
1909 2,
1910 0x1,
1911 1,
1912 0,
1913 snzedcr0::Dtcnzred,
1914 snzedcr0::Dtcnzred,
1915 Snzedcr0_SPEC,
1916 crate::common::RW,
1917 > {
1918 crate::common::RegisterField::<
1919 2,
1920 0x1,
1921 1,
1922 0,
1923 snzedcr0::Dtcnzred,
1924 snzedcr0::Dtcnzred,
1925 Snzedcr0_SPEC,
1926 crate::common::RW,
1927 >::from_register(self, 0)
1928 }
1929
1930 #[doc = "ADC12 Compare Match Snooze End Enable"]
1931 #[inline(always)]
1932 pub fn ad0mated(
1933 self,
1934 ) -> crate::common::RegisterField<
1935 3,
1936 0x1,
1937 1,
1938 0,
1939 snzedcr0::Ad0Mated,
1940 snzedcr0::Ad0Mated,
1941 Snzedcr0_SPEC,
1942 crate::common::RW,
1943 > {
1944 crate::common::RegisterField::<
1945 3,
1946 0x1,
1947 1,
1948 0,
1949 snzedcr0::Ad0Mated,
1950 snzedcr0::Ad0Mated,
1951 Snzedcr0_SPEC,
1952 crate::common::RW,
1953 >::from_register(self, 0)
1954 }
1955
1956 #[doc = "ADC12 Compare Mismatch Snooze End Enable"]
1957 #[inline(always)]
1958 pub fn ad0umted(
1959 self,
1960 ) -> crate::common::RegisterField<
1961 4,
1962 0x1,
1963 1,
1964 0,
1965 snzedcr0::Ad0Umted,
1966 snzedcr0::Ad0Umted,
1967 Snzedcr0_SPEC,
1968 crate::common::RW,
1969 > {
1970 crate::common::RegisterField::<
1971 4,
1972 0x1,
1973 1,
1974 0,
1975 snzedcr0::Ad0Umted,
1976 snzedcr0::Ad0Umted,
1977 Snzedcr0_SPEC,
1978 crate::common::RW,
1979 >::from_register(self, 0)
1980 }
1981
1982 #[doc = "SCI0 Address Mismatch Snooze End Enable"]
1983 #[inline(always)]
1984 pub fn sci0umted(
1985 self,
1986 ) -> crate::common::RegisterField<
1987 7,
1988 0x1,
1989 1,
1990 0,
1991 snzedcr0::Sci0Umted,
1992 snzedcr0::Sci0Umted,
1993 Snzedcr0_SPEC,
1994 crate::common::RW,
1995 > {
1996 crate::common::RegisterField::<
1997 7,
1998 0x1,
1999 1,
2000 0,
2001 snzedcr0::Sci0Umted,
2002 snzedcr0::Sci0Umted,
2003 Snzedcr0_SPEC,
2004 crate::common::RW,
2005 >::from_register(self, 0)
2006 }
2007}
2008impl ::core::default::Default for Snzedcr0 {
2009 #[inline(always)]
2010 fn default() -> Snzedcr0 {
2011 <crate::RegValueT<Snzedcr0_SPEC> as RegisterValue<_>>::new(0)
2012 }
2013}
2014pub mod snzedcr0 {
2015
2016 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2017 pub struct Agtunfed_SPEC;
2018 pub type Agtunfed = crate::EnumBitfieldStruct<u8, Agtunfed_SPEC>;
2019 impl Agtunfed {
2020 #[doc = "Disable the snooze end request"]
2021 pub const _0: Self = Self::new(0);
2022
2023 #[doc = "Enable the snooze end request"]
2024 pub const _1: Self = Self::new(1);
2025 }
2026 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2027 pub struct Dtczred_SPEC;
2028 pub type Dtczred = crate::EnumBitfieldStruct<u8, Dtczred_SPEC>;
2029 impl Dtczred {
2030 #[doc = "Disable the snooze end request"]
2031 pub const _0: Self = Self::new(0);
2032
2033 #[doc = "Enable the snooze end request"]
2034 pub const _1: Self = Self::new(1);
2035 }
2036 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2037 pub struct Dtcnzred_SPEC;
2038 pub type Dtcnzred = crate::EnumBitfieldStruct<u8, Dtcnzred_SPEC>;
2039 impl Dtcnzred {
2040 #[doc = "Disable the snooze end request"]
2041 pub const _0: Self = Self::new(0);
2042
2043 #[doc = "Enable the snooze end request"]
2044 pub const _1: Self = Self::new(1);
2045 }
2046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2047 pub struct Ad0Mated_SPEC;
2048 pub type Ad0Mated = crate::EnumBitfieldStruct<u8, Ad0Mated_SPEC>;
2049 impl Ad0Mated {
2050 #[doc = "Disable the snooze end request"]
2051 pub const _0: Self = Self::new(0);
2052
2053 #[doc = "Enable the snooze end request"]
2054 pub const _1: Self = Self::new(1);
2055 }
2056 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2057 pub struct Ad0Umted_SPEC;
2058 pub type Ad0Umted = crate::EnumBitfieldStruct<u8, Ad0Umted_SPEC>;
2059 impl Ad0Umted {
2060 #[doc = "Disable the snooze end request"]
2061 pub const _0: Self = Self::new(0);
2062
2063 #[doc = "Enable the snooze end request"]
2064 pub const _1: Self = Self::new(1);
2065 }
2066 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2067 pub struct Sci0Umted_SPEC;
2068 pub type Sci0Umted = crate::EnumBitfieldStruct<u8, Sci0Umted_SPEC>;
2069 impl Sci0Umted {
2070 #[doc = "Disable the snooze end request"]
2071 pub const _0: Self = Self::new(0);
2072
2073 #[doc = "Enable the snooze end request"]
2074 pub const _1: Self = Self::new(1);
2075 }
2076}
2077#[doc(hidden)]
2078#[derive(Copy, Clone, Eq, PartialEq)]
2079pub struct Snzreqcr0_SPEC;
2080impl crate::sealed::RegSpec for Snzreqcr0_SPEC {
2081 type DataType = u32;
2082}
2083
2084#[doc = "Snooze Request Control Register 0"]
2085pub type Snzreqcr0 = crate::RegValueT<Snzreqcr0_SPEC>;
2086
2087impl Snzreqcr0 {
2088 #[doc = "Enable IRQ0 pin snooze request"]
2089 #[inline(always)]
2090 pub fn snzreqen0(
2091 self,
2092 ) -> crate::common::RegisterField<
2093 0,
2094 0x1,
2095 1,
2096 0,
2097 snzreqcr0::Snzreqen0,
2098 snzreqcr0::Snzreqen0,
2099 Snzreqcr0_SPEC,
2100 crate::common::RW,
2101 > {
2102 crate::common::RegisterField::<
2103 0,
2104 0x1,
2105 1,
2106 0,
2107 snzreqcr0::Snzreqen0,
2108 snzreqcr0::Snzreqen0,
2109 Snzreqcr0_SPEC,
2110 crate::common::RW,
2111 >::from_register(self, 0)
2112 }
2113
2114 #[doc = "Enable IRQ1 pin snooze request"]
2115 #[inline(always)]
2116 pub fn snzreqen1(
2117 self,
2118 ) -> crate::common::RegisterField<
2119 1,
2120 0x1,
2121 1,
2122 0,
2123 snzreqcr0::Snzreqen1,
2124 snzreqcr0::Snzreqen1,
2125 Snzreqcr0_SPEC,
2126 crate::common::RW,
2127 > {
2128 crate::common::RegisterField::<
2129 1,
2130 0x1,
2131 1,
2132 0,
2133 snzreqcr0::Snzreqen1,
2134 snzreqcr0::Snzreqen1,
2135 Snzreqcr0_SPEC,
2136 crate::common::RW,
2137 >::from_register(self, 0)
2138 }
2139
2140 #[doc = "Enable IRQ2 pin snooze request"]
2141 #[inline(always)]
2142 pub fn snzreqen2(
2143 self,
2144 ) -> crate::common::RegisterField<
2145 2,
2146 0x1,
2147 1,
2148 0,
2149 snzreqcr0::Snzreqen2,
2150 snzreqcr0::Snzreqen2,
2151 Snzreqcr0_SPEC,
2152 crate::common::RW,
2153 > {
2154 crate::common::RegisterField::<
2155 2,
2156 0x1,
2157 1,
2158 0,
2159 snzreqcr0::Snzreqen2,
2160 snzreqcr0::Snzreqen2,
2161 Snzreqcr0_SPEC,
2162 crate::common::RW,
2163 >::from_register(self, 0)
2164 }
2165
2166 #[doc = "Enable IRQ3 pin snooze request"]
2167 #[inline(always)]
2168 pub fn snzreqen3(
2169 self,
2170 ) -> crate::common::RegisterField<
2171 3,
2172 0x1,
2173 1,
2174 0,
2175 snzreqcr0::Snzreqen3,
2176 snzreqcr0::Snzreqen3,
2177 Snzreqcr0_SPEC,
2178 crate::common::RW,
2179 > {
2180 crate::common::RegisterField::<
2181 3,
2182 0x1,
2183 1,
2184 0,
2185 snzreqcr0::Snzreqen3,
2186 snzreqcr0::Snzreqen3,
2187 Snzreqcr0_SPEC,
2188 crate::common::RW,
2189 >::from_register(self, 0)
2190 }
2191
2192 #[doc = "Enable IRQ4 pin snooze request"]
2193 #[inline(always)]
2194 pub fn snzreqen4(
2195 self,
2196 ) -> crate::common::RegisterField<
2197 4,
2198 0x1,
2199 1,
2200 0,
2201 snzreqcr0::Snzreqen4,
2202 snzreqcr0::Snzreqen4,
2203 Snzreqcr0_SPEC,
2204 crate::common::RW,
2205 > {
2206 crate::common::RegisterField::<
2207 4,
2208 0x1,
2209 1,
2210 0,
2211 snzreqcr0::Snzreqen4,
2212 snzreqcr0::Snzreqen4,
2213 Snzreqcr0_SPEC,
2214 crate::common::RW,
2215 >::from_register(self, 0)
2216 }
2217
2218 #[doc = "Enable IRQ5 pin snooze request"]
2219 #[inline(always)]
2220 pub fn snzreqen5(
2221 self,
2222 ) -> crate::common::RegisterField<
2223 5,
2224 0x1,
2225 1,
2226 0,
2227 snzreqcr0::Snzreqen5,
2228 snzreqcr0::Snzreqen5,
2229 Snzreqcr0_SPEC,
2230 crate::common::RW,
2231 > {
2232 crate::common::RegisterField::<
2233 5,
2234 0x1,
2235 1,
2236 0,
2237 snzreqcr0::Snzreqen5,
2238 snzreqcr0::Snzreqen5,
2239 Snzreqcr0_SPEC,
2240 crate::common::RW,
2241 >::from_register(self, 0)
2242 }
2243
2244 #[doc = "Enable IRQ6 pin snooze request"]
2245 #[inline(always)]
2246 pub fn snzreqen6(
2247 self,
2248 ) -> crate::common::RegisterField<
2249 6,
2250 0x1,
2251 1,
2252 0,
2253 snzreqcr0::Snzreqen6,
2254 snzreqcr0::Snzreqen6,
2255 Snzreqcr0_SPEC,
2256 crate::common::RW,
2257 > {
2258 crate::common::RegisterField::<
2259 6,
2260 0x1,
2261 1,
2262 0,
2263 snzreqcr0::Snzreqen6,
2264 snzreqcr0::Snzreqen6,
2265 Snzreqcr0_SPEC,
2266 crate::common::RW,
2267 >::from_register(self, 0)
2268 }
2269
2270 #[doc = "Enable IRQ7 pin snooze request"]
2271 #[inline(always)]
2272 pub fn snzreqen7(
2273 self,
2274 ) -> crate::common::RegisterField<
2275 7,
2276 0x1,
2277 1,
2278 0,
2279 snzreqcr0::Snzreqen7,
2280 snzreqcr0::Snzreqen7,
2281 Snzreqcr0_SPEC,
2282 crate::common::RW,
2283 > {
2284 crate::common::RegisterField::<
2285 7,
2286 0x1,
2287 1,
2288 0,
2289 snzreqcr0::Snzreqen7,
2290 snzreqcr0::Snzreqen7,
2291 Snzreqcr0_SPEC,
2292 crate::common::RW,
2293 >::from_register(self, 0)
2294 }
2295
2296 #[doc = "Enable KEY_INTKR snooze request"]
2297 #[inline(always)]
2298 pub fn snzreqen17(
2299 self,
2300 ) -> crate::common::RegisterField<
2301 17,
2302 0x1,
2303 1,
2304 0,
2305 snzreqcr0::Snzreqen17,
2306 snzreqcr0::Snzreqen17,
2307 Snzreqcr0_SPEC,
2308 crate::common::RW,
2309 > {
2310 crate::common::RegisterField::<
2311 17,
2312 0x1,
2313 1,
2314 0,
2315 snzreqcr0::Snzreqen17,
2316 snzreqcr0::Snzreqen17,
2317 Snzreqcr0_SPEC,
2318 crate::common::RW,
2319 >::from_register(self, 0)
2320 }
2321
2322 #[doc = "Enable ACMPLP snooze request"]
2323 #[inline(always)]
2324 pub fn snzreqen23(
2325 self,
2326 ) -> crate::common::RegisterField<
2327 23,
2328 0x1,
2329 1,
2330 0,
2331 snzreqcr0::Snzreqen23,
2332 snzreqcr0::Snzreqen23,
2333 Snzreqcr0_SPEC,
2334 crate::common::RW,
2335 > {
2336 crate::common::RegisterField::<
2337 23,
2338 0x1,
2339 1,
2340 0,
2341 snzreqcr0::Snzreqen23,
2342 snzreqcr0::Snzreqen23,
2343 Snzreqcr0_SPEC,
2344 crate::common::RW,
2345 >::from_register(self, 0)
2346 }
2347
2348 #[doc = "Enable RTC alarm snooze request"]
2349 #[inline(always)]
2350 pub fn snzreqen24(
2351 self,
2352 ) -> crate::common::RegisterField<
2353 24,
2354 0x1,
2355 1,
2356 0,
2357 snzreqcr0::Snzreqen24,
2358 snzreqcr0::Snzreqen24,
2359 Snzreqcr0_SPEC,
2360 crate::common::RW,
2361 > {
2362 crate::common::RegisterField::<
2363 24,
2364 0x1,
2365 1,
2366 0,
2367 snzreqcr0::Snzreqen24,
2368 snzreqcr0::Snzreqen24,
2369 Snzreqcr0_SPEC,
2370 crate::common::RW,
2371 >::from_register(self, 0)
2372 }
2373
2374 #[doc = "Enable RTC period snooze request"]
2375 #[inline(always)]
2376 pub fn snzreqen25(
2377 self,
2378 ) -> crate::common::RegisterField<
2379 25,
2380 0x1,
2381 1,
2382 0,
2383 snzreqcr0::Snzreqen25,
2384 snzreqcr0::Snzreqen25,
2385 Snzreqcr0_SPEC,
2386 crate::common::RW,
2387 > {
2388 crate::common::RegisterField::<
2389 25,
2390 0x1,
2391 1,
2392 0,
2393 snzreqcr0::Snzreqen25,
2394 snzreqcr0::Snzreqen25,
2395 Snzreqcr0_SPEC,
2396 crate::common::RW,
2397 >::from_register(self, 0)
2398 }
2399
2400 #[doc = "Enable AGT1 underflow snooze request"]
2401 #[inline(always)]
2402 pub fn snzreqen28(
2403 self,
2404 ) -> crate::common::RegisterField<
2405 28,
2406 0x1,
2407 1,
2408 0,
2409 snzreqcr0::Snzreqen28,
2410 snzreqcr0::Snzreqen28,
2411 Snzreqcr0_SPEC,
2412 crate::common::RW,
2413 > {
2414 crate::common::RegisterField::<
2415 28,
2416 0x1,
2417 1,
2418 0,
2419 snzreqcr0::Snzreqen28,
2420 snzreqcr0::Snzreqen28,
2421 Snzreqcr0_SPEC,
2422 crate::common::RW,
2423 >::from_register(self, 0)
2424 }
2425
2426 #[doc = "Enable AGT1 compare match A snooze request"]
2427 #[inline(always)]
2428 pub fn snzreqen29(
2429 self,
2430 ) -> crate::common::RegisterField<
2431 29,
2432 0x1,
2433 1,
2434 0,
2435 snzreqcr0::Snzreqen29,
2436 snzreqcr0::Snzreqen29,
2437 Snzreqcr0_SPEC,
2438 crate::common::RW,
2439 > {
2440 crate::common::RegisterField::<
2441 29,
2442 0x1,
2443 1,
2444 0,
2445 snzreqcr0::Snzreqen29,
2446 snzreqcr0::Snzreqen29,
2447 Snzreqcr0_SPEC,
2448 crate::common::RW,
2449 >::from_register(self, 0)
2450 }
2451
2452 #[doc = "Enable AGT1 compare match B snooze request"]
2453 #[inline(always)]
2454 pub fn snzreqen30(
2455 self,
2456 ) -> crate::common::RegisterField<
2457 30,
2458 0x1,
2459 1,
2460 0,
2461 snzreqcr0::Snzreqen30,
2462 snzreqcr0::Snzreqen30,
2463 Snzreqcr0_SPEC,
2464 crate::common::RW,
2465 > {
2466 crate::common::RegisterField::<
2467 30,
2468 0x1,
2469 1,
2470 0,
2471 snzreqcr0::Snzreqen30,
2472 snzreqcr0::Snzreqen30,
2473 Snzreqcr0_SPEC,
2474 crate::common::RW,
2475 >::from_register(self, 0)
2476 }
2477}
2478impl ::core::default::Default for Snzreqcr0 {
2479 #[inline(always)]
2480 fn default() -> Snzreqcr0 {
2481 <crate::RegValueT<Snzreqcr0_SPEC> as RegisterValue<_>>::new(0)
2482 }
2483}
2484pub mod snzreqcr0 {
2485
2486 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2487 pub struct Snzreqen0_SPEC;
2488 pub type Snzreqen0 = crate::EnumBitfieldStruct<u8, Snzreqen0_SPEC>;
2489 impl Snzreqen0 {
2490 #[doc = "Disable the snooze request"]
2491 pub const _0: Self = Self::new(0);
2492
2493 #[doc = "Enable the snooze request"]
2494 pub const _1: Self = Self::new(1);
2495 }
2496 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2497 pub struct Snzreqen1_SPEC;
2498 pub type Snzreqen1 = crate::EnumBitfieldStruct<u8, Snzreqen1_SPEC>;
2499 impl Snzreqen1 {
2500 #[doc = "Disable the snooze request"]
2501 pub const _0: Self = Self::new(0);
2502
2503 #[doc = "Enable the snooze request"]
2504 pub const _1: Self = Self::new(1);
2505 }
2506 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2507 pub struct Snzreqen2_SPEC;
2508 pub type Snzreqen2 = crate::EnumBitfieldStruct<u8, Snzreqen2_SPEC>;
2509 impl Snzreqen2 {
2510 #[doc = "Disable the snooze request"]
2511 pub const _0: Self = Self::new(0);
2512
2513 #[doc = "Enable the snooze request"]
2514 pub const _1: Self = Self::new(1);
2515 }
2516 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2517 pub struct Snzreqen3_SPEC;
2518 pub type Snzreqen3 = crate::EnumBitfieldStruct<u8, Snzreqen3_SPEC>;
2519 impl Snzreqen3 {
2520 #[doc = "Disable the snooze request"]
2521 pub const _0: Self = Self::new(0);
2522
2523 #[doc = "Enable the snooze request"]
2524 pub const _1: Self = Self::new(1);
2525 }
2526 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2527 pub struct Snzreqen4_SPEC;
2528 pub type Snzreqen4 = crate::EnumBitfieldStruct<u8, Snzreqen4_SPEC>;
2529 impl Snzreqen4 {
2530 #[doc = "Disable the snooze request"]
2531 pub const _0: Self = Self::new(0);
2532
2533 #[doc = "Enable the snooze request"]
2534 pub const _1: Self = Self::new(1);
2535 }
2536 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2537 pub struct Snzreqen5_SPEC;
2538 pub type Snzreqen5 = crate::EnumBitfieldStruct<u8, Snzreqen5_SPEC>;
2539 impl Snzreqen5 {
2540 #[doc = "Disable the snooze request"]
2541 pub const _0: Self = Self::new(0);
2542
2543 #[doc = "Enable the snooze request"]
2544 pub const _1: Self = Self::new(1);
2545 }
2546 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2547 pub struct Snzreqen6_SPEC;
2548 pub type Snzreqen6 = crate::EnumBitfieldStruct<u8, Snzreqen6_SPEC>;
2549 impl Snzreqen6 {
2550 #[doc = "Disable the snooze request"]
2551 pub const _0: Self = Self::new(0);
2552
2553 #[doc = "Enable the snooze request"]
2554 pub const _1: Self = Self::new(1);
2555 }
2556 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2557 pub struct Snzreqen7_SPEC;
2558 pub type Snzreqen7 = crate::EnumBitfieldStruct<u8, Snzreqen7_SPEC>;
2559 impl Snzreqen7 {
2560 #[doc = "Disable the snooze request"]
2561 pub const _0: Self = Self::new(0);
2562
2563 #[doc = "Enable the snooze request"]
2564 pub const _1: Self = Self::new(1);
2565 }
2566 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2567 pub struct Snzreqen17_SPEC;
2568 pub type Snzreqen17 = crate::EnumBitfieldStruct<u8, Snzreqen17_SPEC>;
2569 impl Snzreqen17 {
2570 #[doc = "Disable the snooze request"]
2571 pub const _0: Self = Self::new(0);
2572
2573 #[doc = "Enable the snooze request"]
2574 pub const _1: Self = Self::new(1);
2575 }
2576 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2577 pub struct Snzreqen23_SPEC;
2578 pub type Snzreqen23 = crate::EnumBitfieldStruct<u8, Snzreqen23_SPEC>;
2579 impl Snzreqen23 {
2580 #[doc = "Disable the snooze request"]
2581 pub const _0: Self = Self::new(0);
2582
2583 #[doc = "Enable the snooze request"]
2584 pub const _1: Self = Self::new(1);
2585 }
2586 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2587 pub struct Snzreqen24_SPEC;
2588 pub type Snzreqen24 = crate::EnumBitfieldStruct<u8, Snzreqen24_SPEC>;
2589 impl Snzreqen24 {
2590 #[doc = "Disable the snooze request"]
2591 pub const _0: Self = Self::new(0);
2592
2593 #[doc = "Enable the snooze request"]
2594 pub const _1: Self = Self::new(1);
2595 }
2596 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2597 pub struct Snzreqen25_SPEC;
2598 pub type Snzreqen25 = crate::EnumBitfieldStruct<u8, Snzreqen25_SPEC>;
2599 impl Snzreqen25 {
2600 #[doc = "Disable the snooze request"]
2601 pub const _0: Self = Self::new(0);
2602
2603 #[doc = "Enable the snooze request"]
2604 pub const _1: Self = Self::new(1);
2605 }
2606 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2607 pub struct Snzreqen28_SPEC;
2608 pub type Snzreqen28 = crate::EnumBitfieldStruct<u8, Snzreqen28_SPEC>;
2609 impl Snzreqen28 {
2610 #[doc = "Disable the snooze request"]
2611 pub const _0: Self = Self::new(0);
2612
2613 #[doc = "Enable the snooze request"]
2614 pub const _1: Self = Self::new(1);
2615 }
2616 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2617 pub struct Snzreqen29_SPEC;
2618 pub type Snzreqen29 = crate::EnumBitfieldStruct<u8, Snzreqen29_SPEC>;
2619 impl Snzreqen29 {
2620 #[doc = "Disable the snooze request"]
2621 pub const _0: Self = Self::new(0);
2622
2623 #[doc = "Enable the snooze request"]
2624 pub const _1: Self = Self::new(1);
2625 }
2626 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2627 pub struct Snzreqen30_SPEC;
2628 pub type Snzreqen30 = crate::EnumBitfieldStruct<u8, Snzreqen30_SPEC>;
2629 impl Snzreqen30 {
2630 #[doc = "Disable the snooze request"]
2631 pub const _0: Self = Self::new(0);
2632
2633 #[doc = "Enable the snooze request"]
2634 pub const _1: Self = Self::new(1);
2635 }
2636}
2637#[doc(hidden)]
2638#[derive(Copy, Clone, Eq, PartialEq)]
2639pub struct Psmcr_SPEC;
2640impl crate::sealed::RegSpec for Psmcr_SPEC {
2641 type DataType = u8;
2642}
2643
2644#[doc = "Power Save Memory Control Register"]
2645pub type Psmcr = crate::RegValueT<Psmcr_SPEC>;
2646
2647impl Psmcr {
2648 #[doc = "Power Save Memory Control"]
2649 #[inline(always)]
2650 pub fn psmc(
2651 self,
2652 ) -> crate::common::RegisterField<
2653 0,
2654 0x3,
2655 1,
2656 0,
2657 psmcr::Psmc,
2658 psmcr::Psmc,
2659 Psmcr_SPEC,
2660 crate::common::RW,
2661 > {
2662 crate::common::RegisterField::<
2663 0,
2664 0x3,
2665 1,
2666 0,
2667 psmcr::Psmc,
2668 psmcr::Psmc,
2669 Psmcr_SPEC,
2670 crate::common::RW,
2671 >::from_register(self, 0)
2672 }
2673}
2674impl ::core::default::Default for Psmcr {
2675 #[inline(always)]
2676 fn default() -> Psmcr {
2677 <crate::RegValueT<Psmcr_SPEC> as RegisterValue<_>>::new(0)
2678 }
2679}
2680pub mod psmcr {
2681
2682 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2683 pub struct Psmc_SPEC;
2684 pub type Psmc = crate::EnumBitfieldStruct<u8, Psmc_SPEC>;
2685 impl Psmc {
2686 #[doc = "All SRAMs are on in Software Standby mode"]
2687 pub const _00: Self = Self::new(0);
2688
2689 #[doc = "8 KB SRAM (0x2000_4000 to 0x2000_5FFF) is on in Software Standby mode"]
2690 pub const _01: Self = Self::new(1);
2691
2692 #[doc = "Setting prohibited"]
2693 pub const _10: Self = Self::new(2);
2694
2695 #[doc = "Setting prohibited"]
2696 pub const _11: Self = Self::new(3);
2697 }
2698}
2699#[doc(hidden)]
2700#[derive(Copy, Clone, Eq, PartialEq)]
2701pub struct Opccr_SPEC;
2702impl crate::sealed::RegSpec for Opccr_SPEC {
2703 type DataType = u8;
2704}
2705
2706#[doc = "Operating Power Control Register"]
2707pub type Opccr = crate::RegValueT<Opccr_SPEC>;
2708
2709impl Opccr {
2710 #[doc = "Operating Power Control Mode Select"]
2711 #[inline(always)]
2712 pub fn opcm(
2713 self,
2714 ) -> crate::common::RegisterField<
2715 0,
2716 0x3,
2717 1,
2718 0,
2719 opccr::Opcm,
2720 opccr::Opcm,
2721 Opccr_SPEC,
2722 crate::common::RW,
2723 > {
2724 crate::common::RegisterField::<
2725 0,
2726 0x3,
2727 1,
2728 0,
2729 opccr::Opcm,
2730 opccr::Opcm,
2731 Opccr_SPEC,
2732 crate::common::RW,
2733 >::from_register(self, 0)
2734 }
2735
2736 #[doc = "Operating Power Control Mode Transition Status Flag"]
2737 #[inline(always)]
2738 pub fn opcmtsf(
2739 self,
2740 ) -> crate::common::RegisterField<
2741 4,
2742 0x1,
2743 1,
2744 0,
2745 opccr::Opcmtsf,
2746 opccr::Opcmtsf,
2747 Opccr_SPEC,
2748 crate::common::R,
2749 > {
2750 crate::common::RegisterField::<
2751 4,
2752 0x1,
2753 1,
2754 0,
2755 opccr::Opcmtsf,
2756 opccr::Opcmtsf,
2757 Opccr_SPEC,
2758 crate::common::R,
2759 >::from_register(self, 0)
2760 }
2761}
2762impl ::core::default::Default for Opccr {
2763 #[inline(always)]
2764 fn default() -> Opccr {
2765 <crate::RegValueT<Opccr_SPEC> as RegisterValue<_>>::new(1)
2766 }
2767}
2768pub mod opccr {
2769
2770 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2771 pub struct Opcm_SPEC;
2772 pub type Opcm = crate::EnumBitfieldStruct<u8, Opcm_SPEC>;
2773 impl Opcm {
2774 #[doc = "High-speed mode"]
2775 pub const _00: Self = Self::new(0);
2776
2777 #[doc = "Middle-speed mode"]
2778 pub const _01: Self = Self::new(1);
2779
2780 #[doc = "Setting prohibited"]
2781 pub const _10: Self = Self::new(2);
2782
2783 #[doc = "Low-speed mode"]
2784 pub const _11: Self = Self::new(3);
2785 }
2786 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2787 pub struct Opcmtsf_SPEC;
2788 pub type Opcmtsf = crate::EnumBitfieldStruct<u8, Opcmtsf_SPEC>;
2789 impl Opcmtsf {
2790 #[doc = "Transition completed"]
2791 pub const _0: Self = Self::new(0);
2792
2793 #[doc = "During transition"]
2794 pub const _1: Self = Self::new(1);
2795 }
2796}
2797#[doc(hidden)]
2798#[derive(Copy, Clone, Eq, PartialEq)]
2799pub struct Moscwtcr_SPEC;
2800impl crate::sealed::RegSpec for Moscwtcr_SPEC {
2801 type DataType = u8;
2802}
2803
2804#[doc = "Main Clock Oscillator Wait Control Register"]
2805pub type Moscwtcr = crate::RegValueT<Moscwtcr_SPEC>;
2806
2807impl Moscwtcr {
2808 #[doc = "Main Clock Oscillator Wait Time Setting"]
2809 #[inline(always)]
2810 pub fn msts(
2811 self,
2812 ) -> crate::common::RegisterField<
2813 0,
2814 0xf,
2815 1,
2816 0,
2817 moscwtcr::Msts,
2818 moscwtcr::Msts,
2819 Moscwtcr_SPEC,
2820 crate::common::RW,
2821 > {
2822 crate::common::RegisterField::<
2823 0,
2824 0xf,
2825 1,
2826 0,
2827 moscwtcr::Msts,
2828 moscwtcr::Msts,
2829 Moscwtcr_SPEC,
2830 crate::common::RW,
2831 >::from_register(self, 0)
2832 }
2833}
2834impl ::core::default::Default for Moscwtcr {
2835 #[inline(always)]
2836 fn default() -> Moscwtcr {
2837 <crate::RegValueT<Moscwtcr_SPEC> as RegisterValue<_>>::new(5)
2838 }
2839}
2840pub mod moscwtcr {
2841
2842 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2843 pub struct Msts_SPEC;
2844 pub type Msts = crate::EnumBitfieldStruct<u8, Msts_SPEC>;
2845 impl Msts {
2846 #[doc = "Wait time = 2 cycles (0.25 us)"]
2847 pub const _0_X_0: Self = Self::new(0);
2848
2849 #[doc = "Wait time = 1024 cycles (128 us)"]
2850 pub const _0_X_1: Self = Self::new(1);
2851
2852 #[doc = "Wait time = 2048 cycles (256 us)"]
2853 pub const _0_X_2: Self = Self::new(2);
2854
2855 #[doc = "Wait time = 4096 cycles (512 us)"]
2856 pub const _0_X_3: Self = Self::new(3);
2857
2858 #[doc = "Wait time = 8192 cycles (1024 us)"]
2859 pub const _0_X_4: Self = Self::new(4);
2860
2861 #[doc = "Wait time = 16384 cycles (2048 us)"]
2862 pub const _0_X_5: Self = Self::new(5);
2863
2864 #[doc = "Wait time = 32768 cycles (4096 us)"]
2865 pub const _0_X_6: Self = Self::new(6);
2866
2867 #[doc = "Wait time = 65536 cycles (8192 us)"]
2868 pub const _0_X_7: Self = Self::new(7);
2869
2870 #[doc = "Wait time = 131072 cycles (16384 us)"]
2871 pub const _0_X_8: Self = Self::new(8);
2872
2873 #[doc = "Wait time = 262144 cycles (32768 us)"]
2874 pub const _0_X_9: Self = Self::new(9);
2875 }
2876}
2877#[doc(hidden)]
2878#[derive(Copy, Clone, Eq, PartialEq)]
2879pub struct Hocowtcr_SPEC;
2880impl crate::sealed::RegSpec for Hocowtcr_SPEC {
2881 type DataType = u8;
2882}
2883
2884#[doc = "High-Speed On-Chip Oscillator Wait Control Register"]
2885pub type Hocowtcr = crate::RegValueT<Hocowtcr_SPEC>;
2886
2887impl Hocowtcr {
2888 #[doc = "HOCO Wait Time Setting"]
2889 #[inline(always)]
2890 pub fn hsts(
2891 self,
2892 ) -> crate::common::RegisterField<
2893 0,
2894 0x7,
2895 1,
2896 0,
2897 hocowtcr::Hsts,
2898 hocowtcr::Hsts,
2899 Hocowtcr_SPEC,
2900 crate::common::RW,
2901 > {
2902 crate::common::RegisterField::<
2903 0,
2904 0x7,
2905 1,
2906 0,
2907 hocowtcr::Hsts,
2908 hocowtcr::Hsts,
2909 Hocowtcr_SPEC,
2910 crate::common::RW,
2911 >::from_register(self, 0)
2912 }
2913}
2914impl ::core::default::Default for Hocowtcr {
2915 #[inline(always)]
2916 fn default() -> Hocowtcr {
2917 <crate::RegValueT<Hocowtcr_SPEC> as RegisterValue<_>>::new(5)
2918 }
2919}
2920pub mod hocowtcr {
2921
2922 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2923 pub struct Hsts_SPEC;
2924 pub type Hsts = crate::EnumBitfieldStruct<u8, Hsts_SPEC>;
2925 impl Hsts {
2926 #[doc = "Value after reset."]
2927 pub const _101: Self = Self::new(5);
2928
2929 #[doc = "Before starting high-speed on-chip oscillator by setting HOCOCR.HCSTP bit, the HSTS\\[2:0\\] bits must be set to 011b beforehand. Wait time = 46 cycles (5.75 µs) Wait time is calculated at MOCO = 8 MHz (typically 0.125 µs)."]
2930 pub const _011: Self = Self::new(3);
2931 }
2932}
2933#[doc(hidden)]
2934#[derive(Copy, Clone, Eq, PartialEq)]
2935pub struct Sopccr_SPEC;
2936impl crate::sealed::RegSpec for Sopccr_SPEC {
2937 type DataType = u8;
2938}
2939
2940#[doc = "Sub Operating Power Control Register"]
2941pub type Sopccr = crate::RegValueT<Sopccr_SPEC>;
2942
2943impl Sopccr {
2944 #[doc = "Sub Operating Power Control Mode Select"]
2945 #[inline(always)]
2946 pub fn sopcm(
2947 self,
2948 ) -> crate::common::RegisterField<
2949 0,
2950 0x1,
2951 1,
2952 0,
2953 sopccr::Sopcm,
2954 sopccr::Sopcm,
2955 Sopccr_SPEC,
2956 crate::common::RW,
2957 > {
2958 crate::common::RegisterField::<
2959 0,
2960 0x1,
2961 1,
2962 0,
2963 sopccr::Sopcm,
2964 sopccr::Sopcm,
2965 Sopccr_SPEC,
2966 crate::common::RW,
2967 >::from_register(self, 0)
2968 }
2969
2970 #[doc = "Operating Power Control Mode Transition Status Flag"]
2971 #[inline(always)]
2972 pub fn sopcmtsf(
2973 self,
2974 ) -> crate::common::RegisterField<
2975 4,
2976 0x1,
2977 1,
2978 0,
2979 sopccr::Sopcmtsf,
2980 sopccr::Sopcmtsf,
2981 Sopccr_SPEC,
2982 crate::common::R,
2983 > {
2984 crate::common::RegisterField::<
2985 4,
2986 0x1,
2987 1,
2988 0,
2989 sopccr::Sopcmtsf,
2990 sopccr::Sopcmtsf,
2991 Sopccr_SPEC,
2992 crate::common::R,
2993 >::from_register(self, 0)
2994 }
2995}
2996impl ::core::default::Default for Sopccr {
2997 #[inline(always)]
2998 fn default() -> Sopccr {
2999 <crate::RegValueT<Sopccr_SPEC> as RegisterValue<_>>::new(0)
3000 }
3001}
3002pub mod sopccr {
3003
3004 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3005 pub struct Sopcm_SPEC;
3006 pub type Sopcm = crate::EnumBitfieldStruct<u8, Sopcm_SPEC>;
3007 impl Sopcm {
3008 #[doc = "Other than Subosc-speed mode"]
3009 pub const _0: Self = Self::new(0);
3010
3011 #[doc = "Subosc-speed mode"]
3012 pub const _1: Self = Self::new(1);
3013 }
3014 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3015 pub struct Sopcmtsf_SPEC;
3016 pub type Sopcmtsf = crate::EnumBitfieldStruct<u8, Sopcmtsf_SPEC>;
3017 impl Sopcmtsf {
3018 #[doc = "Transition completed"]
3019 pub const _0: Self = Self::new(0);
3020
3021 #[doc = "During transition"]
3022 pub const _1: Self = Self::new(1);
3023 }
3024}
3025#[doc(hidden)]
3026#[derive(Copy, Clone, Eq, PartialEq)]
3027pub struct Rstsr1_SPEC;
3028impl crate::sealed::RegSpec for Rstsr1_SPEC {
3029 type DataType = u16;
3030}
3031
3032#[doc = "Reset Status Register 1"]
3033pub type Rstsr1 = crate::RegValueT<Rstsr1_SPEC>;
3034
3035impl Rstsr1 {
3036 #[doc = "Independent Watchdog Timer Reset Detect Flag"]
3037 #[inline(always)]
3038 pub fn iwdtrf(
3039 self,
3040 ) -> crate::common::RegisterField<
3041 0,
3042 0x1,
3043 1,
3044 0,
3045 rstsr1::Iwdtrf,
3046 rstsr1::Iwdtrf,
3047 Rstsr1_SPEC,
3048 crate::common::RW,
3049 > {
3050 crate::common::RegisterField::<
3051 0,
3052 0x1,
3053 1,
3054 0,
3055 rstsr1::Iwdtrf,
3056 rstsr1::Iwdtrf,
3057 Rstsr1_SPEC,
3058 crate::common::RW,
3059 >::from_register(self, 0)
3060 }
3061
3062 #[doc = "Watchdog Timer Reset Detect Flag"]
3063 #[inline(always)]
3064 pub fn wdtrf(
3065 self,
3066 ) -> crate::common::RegisterField<
3067 1,
3068 0x1,
3069 1,
3070 0,
3071 rstsr1::Wdtrf,
3072 rstsr1::Wdtrf,
3073 Rstsr1_SPEC,
3074 crate::common::RW,
3075 > {
3076 crate::common::RegisterField::<
3077 1,
3078 0x1,
3079 1,
3080 0,
3081 rstsr1::Wdtrf,
3082 rstsr1::Wdtrf,
3083 Rstsr1_SPEC,
3084 crate::common::RW,
3085 >::from_register(self, 0)
3086 }
3087
3088 #[doc = "Software Reset Detect Flag"]
3089 #[inline(always)]
3090 pub fn swrf(
3091 self,
3092 ) -> crate::common::RegisterField<
3093 2,
3094 0x1,
3095 1,
3096 0,
3097 rstsr1::Swrf,
3098 rstsr1::Swrf,
3099 Rstsr1_SPEC,
3100 crate::common::RW,
3101 > {
3102 crate::common::RegisterField::<
3103 2,
3104 0x1,
3105 1,
3106 0,
3107 rstsr1::Swrf,
3108 rstsr1::Swrf,
3109 Rstsr1_SPEC,
3110 crate::common::RW,
3111 >::from_register(self, 0)
3112 }
3113
3114 #[doc = "SRAM Parity Error Reset Detect Flag"]
3115 #[inline(always)]
3116 pub fn rperf(
3117 self,
3118 ) -> crate::common::RegisterField<
3119 8,
3120 0x1,
3121 1,
3122 0,
3123 rstsr1::Rperf,
3124 rstsr1::Rperf,
3125 Rstsr1_SPEC,
3126 crate::common::RW,
3127 > {
3128 crate::common::RegisterField::<
3129 8,
3130 0x1,
3131 1,
3132 0,
3133 rstsr1::Rperf,
3134 rstsr1::Rperf,
3135 Rstsr1_SPEC,
3136 crate::common::RW,
3137 >::from_register(self, 0)
3138 }
3139
3140 #[doc = "Bus Slave MPU Error Reset Detect Flag"]
3141 #[inline(always)]
3142 pub fn bussrf(
3143 self,
3144 ) -> crate::common::RegisterField<
3145 10,
3146 0x1,
3147 1,
3148 0,
3149 rstsr1::Bussrf,
3150 rstsr1::Bussrf,
3151 Rstsr1_SPEC,
3152 crate::common::RW,
3153 > {
3154 crate::common::RegisterField::<
3155 10,
3156 0x1,
3157 1,
3158 0,
3159 rstsr1::Bussrf,
3160 rstsr1::Bussrf,
3161 Rstsr1_SPEC,
3162 crate::common::RW,
3163 >::from_register(self, 0)
3164 }
3165
3166 #[doc = "Bus Master MPU Error Reset Detect Flag"]
3167 #[inline(always)]
3168 pub fn busmrf(
3169 self,
3170 ) -> crate::common::RegisterField<
3171 11,
3172 0x1,
3173 1,
3174 0,
3175 rstsr1::Busmrf,
3176 rstsr1::Busmrf,
3177 Rstsr1_SPEC,
3178 crate::common::RW,
3179 > {
3180 crate::common::RegisterField::<
3181 11,
3182 0x1,
3183 1,
3184 0,
3185 rstsr1::Busmrf,
3186 rstsr1::Busmrf,
3187 Rstsr1_SPEC,
3188 crate::common::RW,
3189 >::from_register(self, 0)
3190 }
3191
3192 #[doc = "CPU Stack Pointer Error Reset Detect Flag"]
3193 #[inline(always)]
3194 pub fn sperf(
3195 self,
3196 ) -> crate::common::RegisterField<
3197 12,
3198 0x1,
3199 1,
3200 0,
3201 rstsr1::Sperf,
3202 rstsr1::Sperf,
3203 Rstsr1_SPEC,
3204 crate::common::RW,
3205 > {
3206 crate::common::RegisterField::<
3207 12,
3208 0x1,
3209 1,
3210 0,
3211 rstsr1::Sperf,
3212 rstsr1::Sperf,
3213 Rstsr1_SPEC,
3214 crate::common::RW,
3215 >::from_register(self, 0)
3216 }
3217}
3218impl ::core::default::Default for Rstsr1 {
3219 #[inline(always)]
3220 fn default() -> Rstsr1 {
3221 <crate::RegValueT<Rstsr1_SPEC> as RegisterValue<_>>::new(0)
3222 }
3223}
3224pub mod rstsr1 {
3225
3226 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3227 pub struct Iwdtrf_SPEC;
3228 pub type Iwdtrf = crate::EnumBitfieldStruct<u8, Iwdtrf_SPEC>;
3229 impl Iwdtrf {
3230 #[doc = "Independent watchdog timer reset not detected"]
3231 pub const _0: Self = Self::new(0);
3232
3233 #[doc = "Independent watchdog timer reset detected"]
3234 pub const _1: Self = Self::new(1);
3235 }
3236 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3237 pub struct Wdtrf_SPEC;
3238 pub type Wdtrf = crate::EnumBitfieldStruct<u8, Wdtrf_SPEC>;
3239 impl Wdtrf {
3240 #[doc = "Watchdog timer reset not detected"]
3241 pub const _0: Self = Self::new(0);
3242
3243 #[doc = "Watchdog timer reset detected"]
3244 pub const _1: Self = Self::new(1);
3245 }
3246 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3247 pub struct Swrf_SPEC;
3248 pub type Swrf = crate::EnumBitfieldStruct<u8, Swrf_SPEC>;
3249 impl Swrf {
3250 #[doc = "Software reset not detected"]
3251 pub const _0: Self = Self::new(0);
3252
3253 #[doc = "Software reset detected"]
3254 pub const _1: Self = Self::new(1);
3255 }
3256 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3257 pub struct Rperf_SPEC;
3258 pub type Rperf = crate::EnumBitfieldStruct<u8, Rperf_SPEC>;
3259 impl Rperf {
3260 #[doc = "SRAM parity error reset not detected"]
3261 pub const _0: Self = Self::new(0);
3262
3263 #[doc = "SRAM parity error reset detected"]
3264 pub const _1: Self = Self::new(1);
3265 }
3266 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3267 pub struct Bussrf_SPEC;
3268 pub type Bussrf = crate::EnumBitfieldStruct<u8, Bussrf_SPEC>;
3269 impl Bussrf {
3270 #[doc = "Bus slave MPU error reset not detected"]
3271 pub const _0: Self = Self::new(0);
3272
3273 #[doc = "Bus slave MPU error reset detected"]
3274 pub const _1: Self = Self::new(1);
3275 }
3276 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3277 pub struct Busmrf_SPEC;
3278 pub type Busmrf = crate::EnumBitfieldStruct<u8, Busmrf_SPEC>;
3279 impl Busmrf {
3280 #[doc = "Bus master MPU error reset not detected"]
3281 pub const _0: Self = Self::new(0);
3282
3283 #[doc = "Bus master MPU error reset detected"]
3284 pub const _1: Self = Self::new(1);
3285 }
3286 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3287 pub struct Sperf_SPEC;
3288 pub type Sperf = crate::EnumBitfieldStruct<u8, Sperf_SPEC>;
3289 impl Sperf {
3290 #[doc = "CPU stack pointer error reset not detected"]
3291 pub const _0: Self = Self::new(0);
3292
3293 #[doc = "CPU stack pointer error reset detected"]
3294 pub const _1: Self = Self::new(1);
3295 }
3296}
3297#[doc(hidden)]
3298#[derive(Copy, Clone, Eq, PartialEq)]
3299pub struct Lvd1Cr1_SPEC;
3300impl crate::sealed::RegSpec for Lvd1Cr1_SPEC {
3301 type DataType = u8;
3302}
3303
3304#[doc = "Voltage Monitor 1 Circuit Control Register"]
3305pub type Lvd1Cr1 = crate::RegValueT<Lvd1Cr1_SPEC>;
3306
3307impl Lvd1Cr1 {
3308 #[doc = "Voltage Monitor 1 Interrupt Generation Condition Select"]
3309 #[inline(always)]
3310 pub fn idtsel(
3311 self,
3312 ) -> crate::common::RegisterField<
3313 0,
3314 0x3,
3315 1,
3316 0,
3317 lvd1cr1::Idtsel,
3318 lvd1cr1::Idtsel,
3319 Lvd1Cr1_SPEC,
3320 crate::common::RW,
3321 > {
3322 crate::common::RegisterField::<
3323 0,
3324 0x3,
3325 1,
3326 0,
3327 lvd1cr1::Idtsel,
3328 lvd1cr1::Idtsel,
3329 Lvd1Cr1_SPEC,
3330 crate::common::RW,
3331 >::from_register(self, 0)
3332 }
3333
3334 #[doc = "Voltage Monitor 1 Interrupt Type Select"]
3335 #[inline(always)]
3336 pub fn irqsel(
3337 self,
3338 ) -> crate::common::RegisterField<
3339 2,
3340 0x1,
3341 1,
3342 0,
3343 lvd1cr1::Irqsel,
3344 lvd1cr1::Irqsel,
3345 Lvd1Cr1_SPEC,
3346 crate::common::RW,
3347 > {
3348 crate::common::RegisterField::<
3349 2,
3350 0x1,
3351 1,
3352 0,
3353 lvd1cr1::Irqsel,
3354 lvd1cr1::Irqsel,
3355 Lvd1Cr1_SPEC,
3356 crate::common::RW,
3357 >::from_register(self, 0)
3358 }
3359}
3360impl ::core::default::Default for Lvd1Cr1 {
3361 #[inline(always)]
3362 fn default() -> Lvd1Cr1 {
3363 <crate::RegValueT<Lvd1Cr1_SPEC> as RegisterValue<_>>::new(1)
3364 }
3365}
3366pub mod lvd1cr1 {
3367
3368 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3369 pub struct Idtsel_SPEC;
3370 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
3371 impl Idtsel {
3372 #[doc = "When VCC >= Vdet1 (rise) is detected"]
3373 pub const _00: Self = Self::new(0);
3374
3375 #[doc = "When VCC < Vdet1 (fall) is detected"]
3376 pub const _01: Self = Self::new(1);
3377
3378 #[doc = "When fall and rise are detected"]
3379 pub const _10: Self = Self::new(2);
3380
3381 #[doc = "Settings prohibited"]
3382 pub const _11: Self = Self::new(3);
3383 }
3384 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3385 pub struct Irqsel_SPEC;
3386 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
3387 impl Irqsel {
3388 #[doc = "Non-maskable interrupt"]
3389 pub const _0: Self = Self::new(0);
3390
3391 #[doc = "Maskable interrupt"]
3392 pub const _1: Self = Self::new(1);
3393 }
3394}
3395#[doc(hidden)]
3396#[derive(Copy, Clone, Eq, PartialEq)]
3397pub struct Lvd1Sr_SPEC;
3398impl crate::sealed::RegSpec for Lvd1Sr_SPEC {
3399 type DataType = u8;
3400}
3401
3402#[doc = "Voltage Monitor 1 Circuit Status Register"]
3403pub type Lvd1Sr = crate::RegValueT<Lvd1Sr_SPEC>;
3404
3405impl Lvd1Sr {
3406 #[doc = "Voltage Monitor 1 Voltage Variation Detection Flag"]
3407 #[inline(always)]
3408 pub fn det(
3409 self,
3410 ) -> crate::common::RegisterField<
3411 0,
3412 0x1,
3413 1,
3414 0,
3415 lvd1sr::Det,
3416 lvd1sr::Det,
3417 Lvd1Sr_SPEC,
3418 crate::common::RW,
3419 > {
3420 crate::common::RegisterField::<
3421 0,
3422 0x1,
3423 1,
3424 0,
3425 lvd1sr::Det,
3426 lvd1sr::Det,
3427 Lvd1Sr_SPEC,
3428 crate::common::RW,
3429 >::from_register(self, 0)
3430 }
3431
3432 #[doc = "Voltage Monitor 1 Signal Monitor Flag"]
3433 #[inline(always)]
3434 pub fn mon(
3435 self,
3436 ) -> crate::common::RegisterField<
3437 1,
3438 0x1,
3439 1,
3440 0,
3441 lvd1sr::Mon,
3442 lvd1sr::Mon,
3443 Lvd1Sr_SPEC,
3444 crate::common::R,
3445 > {
3446 crate::common::RegisterField::<
3447 1,
3448 0x1,
3449 1,
3450 0,
3451 lvd1sr::Mon,
3452 lvd1sr::Mon,
3453 Lvd1Sr_SPEC,
3454 crate::common::R,
3455 >::from_register(self, 0)
3456 }
3457}
3458impl ::core::default::Default for Lvd1Sr {
3459 #[inline(always)]
3460 fn default() -> Lvd1Sr {
3461 <crate::RegValueT<Lvd1Sr_SPEC> as RegisterValue<_>>::new(2)
3462 }
3463}
3464pub mod lvd1sr {
3465
3466 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3467 pub struct Det_SPEC;
3468 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
3469 impl Det {
3470 #[doc = "Not detected"]
3471 pub const _0: Self = Self::new(0);
3472
3473 #[doc = "Vdet1 crossing is detected"]
3474 pub const _1: Self = Self::new(1);
3475 }
3476 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3477 pub struct Mon_SPEC;
3478 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
3479 impl Mon {
3480 #[doc = "VCC < Vdet1"]
3481 pub const _0: Self = Self::new(0);
3482
3483 #[doc = "VCC >= Vdet1 or MON is disabled"]
3484 pub const _1: Self = Self::new(1);
3485 }
3486}
3487#[doc(hidden)]
3488#[derive(Copy, Clone, Eq, PartialEq)]
3489pub struct Lvd2Cr1_SPEC;
3490impl crate::sealed::RegSpec for Lvd2Cr1_SPEC {
3491 type DataType = u8;
3492}
3493
3494#[doc = "Voltage Monitor 2 Circuit Control Register 1"]
3495pub type Lvd2Cr1 = crate::RegValueT<Lvd2Cr1_SPEC>;
3496
3497impl Lvd2Cr1 {
3498 #[doc = "Voltage Monitor 2 Interrupt Generation Condition Select"]
3499 #[inline(always)]
3500 pub fn idtsel(
3501 self,
3502 ) -> crate::common::RegisterField<
3503 0,
3504 0x3,
3505 1,
3506 0,
3507 lvd2cr1::Idtsel,
3508 lvd2cr1::Idtsel,
3509 Lvd2Cr1_SPEC,
3510 crate::common::RW,
3511 > {
3512 crate::common::RegisterField::<
3513 0,
3514 0x3,
3515 1,
3516 0,
3517 lvd2cr1::Idtsel,
3518 lvd2cr1::Idtsel,
3519 Lvd2Cr1_SPEC,
3520 crate::common::RW,
3521 >::from_register(self, 0)
3522 }
3523
3524 #[doc = "Voltage Monitor 2 Interrupt Type Select"]
3525 #[inline(always)]
3526 pub fn irqsel(
3527 self,
3528 ) -> crate::common::RegisterField<
3529 2,
3530 0x1,
3531 1,
3532 0,
3533 lvd2cr1::Irqsel,
3534 lvd2cr1::Irqsel,
3535 Lvd2Cr1_SPEC,
3536 crate::common::RW,
3537 > {
3538 crate::common::RegisterField::<
3539 2,
3540 0x1,
3541 1,
3542 0,
3543 lvd2cr1::Irqsel,
3544 lvd2cr1::Irqsel,
3545 Lvd2Cr1_SPEC,
3546 crate::common::RW,
3547 >::from_register(self, 0)
3548 }
3549}
3550impl ::core::default::Default for Lvd2Cr1 {
3551 #[inline(always)]
3552 fn default() -> Lvd2Cr1 {
3553 <crate::RegValueT<Lvd2Cr1_SPEC> as RegisterValue<_>>::new(1)
3554 }
3555}
3556pub mod lvd2cr1 {
3557
3558 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3559 pub struct Idtsel_SPEC;
3560 pub type Idtsel = crate::EnumBitfieldStruct<u8, Idtsel_SPEC>;
3561 impl Idtsel {
3562 #[doc = "When VCC >= Vdet2 (rise) is detected"]
3563 pub const _00: Self = Self::new(0);
3564
3565 #[doc = "When VCC < Vdet2 (fall) is detected"]
3566 pub const _01: Self = Self::new(1);
3567
3568 #[doc = "When fall and rise are detected"]
3569 pub const _10: Self = Self::new(2);
3570
3571 #[doc = "Settings prohibited"]
3572 pub const _11: Self = Self::new(3);
3573 }
3574 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3575 pub struct Irqsel_SPEC;
3576 pub type Irqsel = crate::EnumBitfieldStruct<u8, Irqsel_SPEC>;
3577 impl Irqsel {
3578 #[doc = "Non-maskable interrupt"]
3579 pub const _0: Self = Self::new(0);
3580
3581 #[doc = "Maskable interrupt"]
3582 pub const _1: Self = Self::new(1);
3583 }
3584}
3585#[doc(hidden)]
3586#[derive(Copy, Clone, Eq, PartialEq)]
3587pub struct Lvd2Sr_SPEC;
3588impl crate::sealed::RegSpec for Lvd2Sr_SPEC {
3589 type DataType = u8;
3590}
3591
3592#[doc = "Voltage Monitor 2 Circuit Status Register"]
3593pub type Lvd2Sr = crate::RegValueT<Lvd2Sr_SPEC>;
3594
3595impl Lvd2Sr {
3596 #[doc = "Voltage Monitor 2 Voltage Variation Detection Flag"]
3597 #[inline(always)]
3598 pub fn det(
3599 self,
3600 ) -> crate::common::RegisterField<
3601 0,
3602 0x1,
3603 1,
3604 0,
3605 lvd2sr::Det,
3606 lvd2sr::Det,
3607 Lvd2Sr_SPEC,
3608 crate::common::RW,
3609 > {
3610 crate::common::RegisterField::<
3611 0,
3612 0x1,
3613 1,
3614 0,
3615 lvd2sr::Det,
3616 lvd2sr::Det,
3617 Lvd2Sr_SPEC,
3618 crate::common::RW,
3619 >::from_register(self, 0)
3620 }
3621
3622 #[doc = "Voltage Monitor 2 Signal Monitor Flag"]
3623 #[inline(always)]
3624 pub fn mon(
3625 self,
3626 ) -> crate::common::RegisterField<
3627 1,
3628 0x1,
3629 1,
3630 0,
3631 lvd2sr::Mon,
3632 lvd2sr::Mon,
3633 Lvd2Sr_SPEC,
3634 crate::common::R,
3635 > {
3636 crate::common::RegisterField::<
3637 1,
3638 0x1,
3639 1,
3640 0,
3641 lvd2sr::Mon,
3642 lvd2sr::Mon,
3643 Lvd2Sr_SPEC,
3644 crate::common::R,
3645 >::from_register(self, 0)
3646 }
3647}
3648impl ::core::default::Default for Lvd2Sr {
3649 #[inline(always)]
3650 fn default() -> Lvd2Sr {
3651 <crate::RegValueT<Lvd2Sr_SPEC> as RegisterValue<_>>::new(2)
3652 }
3653}
3654pub mod lvd2sr {
3655
3656 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3657 pub struct Det_SPEC;
3658 pub type Det = crate::EnumBitfieldStruct<u8, Det_SPEC>;
3659 impl Det {
3660 #[doc = "Not detected"]
3661 pub const _0: Self = Self::new(0);
3662
3663 #[doc = "Vdet2 crossing is detected"]
3664 pub const _1: Self = Self::new(1);
3665 }
3666 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3667 pub struct Mon_SPEC;
3668 pub type Mon = crate::EnumBitfieldStruct<u8, Mon_SPEC>;
3669 impl Mon {
3670 #[doc = "VCC < Vdet2"]
3671 pub const _0: Self = Self::new(0);
3672
3673 #[doc = "VCC >= Vdet2 or MON is disabled"]
3674 pub const _1: Self = Self::new(1);
3675 }
3676}
3677#[doc(hidden)]
3678#[derive(Copy, Clone, Eq, PartialEq)]
3679pub struct Prcr_SPEC;
3680impl crate::sealed::RegSpec for Prcr_SPEC {
3681 type DataType = u16;
3682}
3683
3684#[doc = "Protect Register"]
3685pub type Prcr = crate::RegValueT<Prcr_SPEC>;
3686
3687impl Prcr {
3688 #[doc = "Enable writing to the registers related to the clock generation circuit"]
3689 #[inline(always)]
3690 pub fn prc0(
3691 self,
3692 ) -> crate::common::RegisterField<
3693 0,
3694 0x1,
3695 1,
3696 0,
3697 prcr::Prc0,
3698 prcr::Prc0,
3699 Prcr_SPEC,
3700 crate::common::RW,
3701 > {
3702 crate::common::RegisterField::<
3703 0,
3704 0x1,
3705 1,
3706 0,
3707 prcr::Prc0,
3708 prcr::Prc0,
3709 Prcr_SPEC,
3710 crate::common::RW,
3711 >::from_register(self, 0)
3712 }
3713
3714 #[doc = "Enable writing to the registers related to the low power modes"]
3715 #[inline(always)]
3716 pub fn prc1(
3717 self,
3718 ) -> crate::common::RegisterField<
3719 1,
3720 0x1,
3721 1,
3722 0,
3723 prcr::Prc1,
3724 prcr::Prc1,
3725 Prcr_SPEC,
3726 crate::common::RW,
3727 > {
3728 crate::common::RegisterField::<
3729 1,
3730 0x1,
3731 1,
3732 0,
3733 prcr::Prc1,
3734 prcr::Prc1,
3735 Prcr_SPEC,
3736 crate::common::RW,
3737 >::from_register(self, 0)
3738 }
3739
3740 #[doc = "Enable writing to the registers related to the LVD"]
3741 #[inline(always)]
3742 pub fn prc3(
3743 self,
3744 ) -> crate::common::RegisterField<
3745 3,
3746 0x1,
3747 1,
3748 0,
3749 prcr::Prc3,
3750 prcr::Prc3,
3751 Prcr_SPEC,
3752 crate::common::RW,
3753 > {
3754 crate::common::RegisterField::<
3755 3,
3756 0x1,
3757 1,
3758 0,
3759 prcr::Prc3,
3760 prcr::Prc3,
3761 Prcr_SPEC,
3762 crate::common::RW,
3763 >::from_register(self, 0)
3764 }
3765
3766 #[doc = "PRC Key Code"]
3767 #[inline(always)]
3768 pub fn prkey(
3769 self,
3770 ) -> crate::common::RegisterField<8, 0xff, 1, 0, u8, u8, Prcr_SPEC, crate::common::W> {
3771 crate::common::RegisterField::<8,0xff,1,0,u8,u8,Prcr_SPEC,crate::common::W>::from_register(self,0)
3772 }
3773}
3774impl ::core::default::Default for Prcr {
3775 #[inline(always)]
3776 fn default() -> Prcr {
3777 <crate::RegValueT<Prcr_SPEC> as RegisterValue<_>>::new(0)
3778 }
3779}
3780pub mod prcr {
3781
3782 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3783 pub struct Prc0_SPEC;
3784 pub type Prc0 = crate::EnumBitfieldStruct<u8, Prc0_SPEC>;
3785 impl Prc0 {
3786 #[doc = "Disable writes"]
3787 pub const _0: Self = Self::new(0);
3788
3789 #[doc = "Enable writes"]
3790 pub const _1: Self = Self::new(1);
3791 }
3792 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3793 pub struct Prc1_SPEC;
3794 pub type Prc1 = crate::EnumBitfieldStruct<u8, Prc1_SPEC>;
3795 impl Prc1 {
3796 #[doc = "Disable writes"]
3797 pub const _0: Self = Self::new(0);
3798
3799 #[doc = "Enable writes"]
3800 pub const _1: Self = Self::new(1);
3801 }
3802 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3803 pub struct Prc3_SPEC;
3804 pub type Prc3 = crate::EnumBitfieldStruct<u8, Prc3_SPEC>;
3805 impl Prc3 {
3806 #[doc = "Disable writes"]
3807 pub const _0: Self = Self::new(0);
3808
3809 #[doc = "Enable writes"]
3810 pub const _1: Self = Self::new(1);
3811 }
3812}
3813#[doc(hidden)]
3814#[derive(Copy, Clone, Eq, PartialEq)]
3815pub struct Syocdcr_SPEC;
3816impl crate::sealed::RegSpec for Syocdcr_SPEC {
3817 type DataType = u8;
3818}
3819
3820#[doc = "System Control OCD Control Register"]
3821pub type Syocdcr = crate::RegValueT<Syocdcr_SPEC>;
3822
3823impl Syocdcr {
3824 #[doc = "Debugger Enable bit"]
3825 #[inline(always)]
3826 pub fn dbgen(
3827 self,
3828 ) -> crate::common::RegisterField<
3829 7,
3830 0x1,
3831 1,
3832 0,
3833 syocdcr::Dbgen,
3834 syocdcr::Dbgen,
3835 Syocdcr_SPEC,
3836 crate::common::RW,
3837 > {
3838 crate::common::RegisterField::<
3839 7,
3840 0x1,
3841 1,
3842 0,
3843 syocdcr::Dbgen,
3844 syocdcr::Dbgen,
3845 Syocdcr_SPEC,
3846 crate::common::RW,
3847 >::from_register(self, 0)
3848 }
3849}
3850impl ::core::default::Default for Syocdcr {
3851 #[inline(always)]
3852 fn default() -> Syocdcr {
3853 <crate::RegValueT<Syocdcr_SPEC> as RegisterValue<_>>::new(0)
3854 }
3855}
3856pub mod syocdcr {
3857
3858 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3859 pub struct Dbgen_SPEC;
3860 pub type Dbgen = crate::EnumBitfieldStruct<u8, Dbgen_SPEC>;
3861 impl Dbgen {
3862 #[doc = "On-chip debugger is disabled"]
3863 pub const _0: Self = Self::new(0);
3864
3865 #[doc = "On-chip debugger is enabled"]
3866 pub const _1: Self = Self::new(1);
3867 }
3868}
3869#[doc(hidden)]
3870#[derive(Copy, Clone, Eq, PartialEq)]
3871pub struct Rstsr0_SPEC;
3872impl crate::sealed::RegSpec for Rstsr0_SPEC {
3873 type DataType = u8;
3874}
3875
3876#[doc = "Reset Status Register 0"]
3877pub type Rstsr0 = crate::RegValueT<Rstsr0_SPEC>;
3878
3879impl Rstsr0 {
3880 #[doc = "Power-On Reset Detect Flag"]
3881 #[inline(always)]
3882 pub fn porf(
3883 self,
3884 ) -> crate::common::RegisterField<
3885 0,
3886 0x1,
3887 1,
3888 0,
3889 rstsr0::Porf,
3890 rstsr0::Porf,
3891 Rstsr0_SPEC,
3892 crate::common::RW,
3893 > {
3894 crate::common::RegisterField::<
3895 0,
3896 0x1,
3897 1,
3898 0,
3899 rstsr0::Porf,
3900 rstsr0::Porf,
3901 Rstsr0_SPEC,
3902 crate::common::RW,
3903 >::from_register(self, 0)
3904 }
3905
3906 #[doc = "Voltage Monitor 0 Reset Detect Flag"]
3907 #[inline(always)]
3908 pub fn lvd0rf(
3909 self,
3910 ) -> crate::common::RegisterField<
3911 1,
3912 0x1,
3913 1,
3914 0,
3915 rstsr0::Lvd0Rf,
3916 rstsr0::Lvd0Rf,
3917 Rstsr0_SPEC,
3918 crate::common::RW,
3919 > {
3920 crate::common::RegisterField::<
3921 1,
3922 0x1,
3923 1,
3924 0,
3925 rstsr0::Lvd0Rf,
3926 rstsr0::Lvd0Rf,
3927 Rstsr0_SPEC,
3928 crate::common::RW,
3929 >::from_register(self, 0)
3930 }
3931
3932 #[doc = "Voltage Monitor 1 Reset Detect Flag"]
3933 #[inline(always)]
3934 pub fn lvd1rf(
3935 self,
3936 ) -> crate::common::RegisterField<
3937 2,
3938 0x1,
3939 1,
3940 0,
3941 rstsr0::Lvd1Rf,
3942 rstsr0::Lvd1Rf,
3943 Rstsr0_SPEC,
3944 crate::common::RW,
3945 > {
3946 crate::common::RegisterField::<
3947 2,
3948 0x1,
3949 1,
3950 0,
3951 rstsr0::Lvd1Rf,
3952 rstsr0::Lvd1Rf,
3953 Rstsr0_SPEC,
3954 crate::common::RW,
3955 >::from_register(self, 0)
3956 }
3957
3958 #[doc = "Voltage Monitor 2 Reset Detect Flag"]
3959 #[inline(always)]
3960 pub fn lvd2rf(
3961 self,
3962 ) -> crate::common::RegisterField<
3963 3,
3964 0x1,
3965 1,
3966 0,
3967 rstsr0::Lvd2Rf,
3968 rstsr0::Lvd2Rf,
3969 Rstsr0_SPEC,
3970 crate::common::RW,
3971 > {
3972 crate::common::RegisterField::<
3973 3,
3974 0x1,
3975 1,
3976 0,
3977 rstsr0::Lvd2Rf,
3978 rstsr0::Lvd2Rf,
3979 Rstsr0_SPEC,
3980 crate::common::RW,
3981 >::from_register(self, 0)
3982 }
3983}
3984impl ::core::default::Default for Rstsr0 {
3985 #[inline(always)]
3986 fn default() -> Rstsr0 {
3987 <crate::RegValueT<Rstsr0_SPEC> as RegisterValue<_>>::new(0)
3988 }
3989}
3990pub mod rstsr0 {
3991
3992 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3993 pub struct Porf_SPEC;
3994 pub type Porf = crate::EnumBitfieldStruct<u8, Porf_SPEC>;
3995 impl Porf {
3996 #[doc = "Power-on reset not detected"]
3997 pub const _0: Self = Self::new(0);
3998
3999 #[doc = "Power-on reset detected"]
4000 pub const _1: Self = Self::new(1);
4001 }
4002 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4003 pub struct Lvd0Rf_SPEC;
4004 pub type Lvd0Rf = crate::EnumBitfieldStruct<u8, Lvd0Rf_SPEC>;
4005 impl Lvd0Rf {
4006 #[doc = "Voltage monitor 0 reset not detected"]
4007 pub const _0: Self = Self::new(0);
4008
4009 #[doc = "Voltage monitor 0 reset detected"]
4010 pub const _1: Self = Self::new(1);
4011 }
4012 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4013 pub struct Lvd1Rf_SPEC;
4014 pub type Lvd1Rf = crate::EnumBitfieldStruct<u8, Lvd1Rf_SPEC>;
4015 impl Lvd1Rf {
4016 #[doc = "Voltage monitor 1 reset not detected"]
4017 pub const _0: Self = Self::new(0);
4018
4019 #[doc = "Voltage monitor 1 reset detected"]
4020 pub const _1: Self = Self::new(1);
4021 }
4022 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4023 pub struct Lvd2Rf_SPEC;
4024 pub type Lvd2Rf = crate::EnumBitfieldStruct<u8, Lvd2Rf_SPEC>;
4025 impl Lvd2Rf {
4026 #[doc = "Voltage monitor 2 reset not detected"]
4027 pub const _0: Self = Self::new(0);
4028
4029 #[doc = "Voltage monitor 2 reset detected"]
4030 pub const _1: Self = Self::new(1);
4031 }
4032}
4033#[doc(hidden)]
4034#[derive(Copy, Clone, Eq, PartialEq)]
4035pub struct Rstsr2_SPEC;
4036impl crate::sealed::RegSpec for Rstsr2_SPEC {
4037 type DataType = u8;
4038}
4039
4040#[doc = "Reset Status Register 2"]
4041pub type Rstsr2 = crate::RegValueT<Rstsr2_SPEC>;
4042
4043impl Rstsr2 {
4044 #[doc = "Cold/Warm Start Determination Flag"]
4045 #[inline(always)]
4046 pub fn cwsf(
4047 self,
4048 ) -> crate::common::RegisterField<
4049 0,
4050 0x1,
4051 1,
4052 0,
4053 rstsr2::Cwsf,
4054 rstsr2::Cwsf,
4055 Rstsr2_SPEC,
4056 crate::common::RW,
4057 > {
4058 crate::common::RegisterField::<
4059 0,
4060 0x1,
4061 1,
4062 0,
4063 rstsr2::Cwsf,
4064 rstsr2::Cwsf,
4065 Rstsr2_SPEC,
4066 crate::common::RW,
4067 >::from_register(self, 0)
4068 }
4069}
4070impl ::core::default::Default for Rstsr2 {
4071 #[inline(always)]
4072 fn default() -> Rstsr2 {
4073 <crate::RegValueT<Rstsr2_SPEC> as RegisterValue<_>>::new(0)
4074 }
4075}
4076pub mod rstsr2 {
4077
4078 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4079 pub struct Cwsf_SPEC;
4080 pub type Cwsf = crate::EnumBitfieldStruct<u8, Cwsf_SPEC>;
4081 impl Cwsf {
4082 #[doc = "Cold start"]
4083 pub const _0: Self = Self::new(0);
4084
4085 #[doc = "Warm start"]
4086 pub const _1: Self = Self::new(1);
4087 }
4088}
4089#[doc(hidden)]
4090#[derive(Copy, Clone, Eq, PartialEq)]
4091pub struct Momcr_SPEC;
4092impl crate::sealed::RegSpec for Momcr_SPEC {
4093 type DataType = u8;
4094}
4095
4096#[doc = "Main Clock Oscillator Mode Oscillation Control Register"]
4097pub type Momcr = crate::RegValueT<Momcr_SPEC>;
4098
4099impl Momcr {
4100 #[doc = "Main Clock Oscillator Drive Capability 1 Switching"]
4101 #[inline(always)]
4102 pub fn modrv1(
4103 self,
4104 ) -> crate::common::RegisterField<
4105 3,
4106 0x1,
4107 1,
4108 0,
4109 momcr::Modrv1,
4110 momcr::Modrv1,
4111 Momcr_SPEC,
4112 crate::common::RW,
4113 > {
4114 crate::common::RegisterField::<
4115 3,
4116 0x1,
4117 1,
4118 0,
4119 momcr::Modrv1,
4120 momcr::Modrv1,
4121 Momcr_SPEC,
4122 crate::common::RW,
4123 >::from_register(self, 0)
4124 }
4125
4126 #[doc = "Main Clock Oscillator Switching"]
4127 #[inline(always)]
4128 pub fn mosel(
4129 self,
4130 ) -> crate::common::RegisterField<
4131 6,
4132 0x1,
4133 1,
4134 0,
4135 momcr::Mosel,
4136 momcr::Mosel,
4137 Momcr_SPEC,
4138 crate::common::RW,
4139 > {
4140 crate::common::RegisterField::<
4141 6,
4142 0x1,
4143 1,
4144 0,
4145 momcr::Mosel,
4146 momcr::Mosel,
4147 Momcr_SPEC,
4148 crate::common::RW,
4149 >::from_register(self, 0)
4150 }
4151}
4152impl ::core::default::Default for Momcr {
4153 #[inline(always)]
4154 fn default() -> Momcr {
4155 <crate::RegValueT<Momcr_SPEC> as RegisterValue<_>>::new(0)
4156 }
4157}
4158pub mod momcr {
4159
4160 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4161 pub struct Modrv1_SPEC;
4162 pub type Modrv1 = crate::EnumBitfieldStruct<u8, Modrv1_SPEC>;
4163 impl Modrv1 {
4164 #[doc = "10 MHz to 20 MHz"]
4165 pub const _0: Self = Self::new(0);
4166
4167 #[doc = "1 MHz to 10 MHz"]
4168 pub const _1: Self = Self::new(1);
4169 }
4170 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4171 pub struct Mosel_SPEC;
4172 pub type Mosel = crate::EnumBitfieldStruct<u8, Mosel_SPEC>;
4173 impl Mosel {
4174 #[doc = "Resonator"]
4175 pub const _0: Self = Self::new(0);
4176
4177 #[doc = "External clock input"]
4178 pub const _1: Self = Self::new(1);
4179 }
4180}
4181#[doc(hidden)]
4182#[derive(Copy, Clone, Eq, PartialEq)]
4183pub struct Lvcmpcr_SPEC;
4184impl crate::sealed::RegSpec for Lvcmpcr_SPEC {
4185 type DataType = u8;
4186}
4187
4188#[doc = "Voltage Monitor Circuit Control Register"]
4189pub type Lvcmpcr = crate::RegValueT<Lvcmpcr_SPEC>;
4190
4191impl Lvcmpcr {
4192 #[doc = "Voltage Detection 1 Enable"]
4193 #[inline(always)]
4194 pub fn lvd1e(
4195 self,
4196 ) -> crate::common::RegisterField<
4197 5,
4198 0x1,
4199 1,
4200 0,
4201 lvcmpcr::Lvd1E,
4202 lvcmpcr::Lvd1E,
4203 Lvcmpcr_SPEC,
4204 crate::common::RW,
4205 > {
4206 crate::common::RegisterField::<
4207 5,
4208 0x1,
4209 1,
4210 0,
4211 lvcmpcr::Lvd1E,
4212 lvcmpcr::Lvd1E,
4213 Lvcmpcr_SPEC,
4214 crate::common::RW,
4215 >::from_register(self, 0)
4216 }
4217
4218 #[doc = "Voltage Detection 2 Enable"]
4219 #[inline(always)]
4220 pub fn lvd2e(
4221 self,
4222 ) -> crate::common::RegisterField<
4223 6,
4224 0x1,
4225 1,
4226 0,
4227 lvcmpcr::Lvd2E,
4228 lvcmpcr::Lvd2E,
4229 Lvcmpcr_SPEC,
4230 crate::common::RW,
4231 > {
4232 crate::common::RegisterField::<
4233 6,
4234 0x1,
4235 1,
4236 0,
4237 lvcmpcr::Lvd2E,
4238 lvcmpcr::Lvd2E,
4239 Lvcmpcr_SPEC,
4240 crate::common::RW,
4241 >::from_register(self, 0)
4242 }
4243}
4244impl ::core::default::Default for Lvcmpcr {
4245 #[inline(always)]
4246 fn default() -> Lvcmpcr {
4247 <crate::RegValueT<Lvcmpcr_SPEC> as RegisterValue<_>>::new(0)
4248 }
4249}
4250pub mod lvcmpcr {
4251
4252 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4253 pub struct Lvd1E_SPEC;
4254 pub type Lvd1E = crate::EnumBitfieldStruct<u8, Lvd1E_SPEC>;
4255 impl Lvd1E {
4256 #[doc = "Voltage detection 1 circuit disabled"]
4257 pub const _0: Self = Self::new(0);
4258
4259 #[doc = "Voltage detection 1 circuit enabled"]
4260 pub const _1: Self = Self::new(1);
4261 }
4262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4263 pub struct Lvd2E_SPEC;
4264 pub type Lvd2E = crate::EnumBitfieldStruct<u8, Lvd2E_SPEC>;
4265 impl Lvd2E {
4266 #[doc = "Voltage detection 2 circuit disabled"]
4267 pub const _0: Self = Self::new(0);
4268
4269 #[doc = "Voltage detection 2 circuit enabled"]
4270 pub const _1: Self = Self::new(1);
4271 }
4272}
4273#[doc(hidden)]
4274#[derive(Copy, Clone, Eq, PartialEq)]
4275pub struct Lvdlvlr_SPEC;
4276impl crate::sealed::RegSpec for Lvdlvlr_SPEC {
4277 type DataType = u8;
4278}
4279
4280#[doc = "Voltage Detection Level Select Register"]
4281pub type Lvdlvlr = crate::RegValueT<Lvdlvlr_SPEC>;
4282
4283impl Lvdlvlr {
4284 #[doc = "Voltage Detection 1 Level Select (Standard voltage during fall in voltage)"]
4285 #[inline(always)]
4286 pub fn lvd1lvl(
4287 self,
4288 ) -> crate::common::RegisterField<
4289 0,
4290 0x1f,
4291 1,
4292 0,
4293 lvdlvlr::Lvd1Lvl,
4294 lvdlvlr::Lvd1Lvl,
4295 Lvdlvlr_SPEC,
4296 crate::common::RW,
4297 > {
4298 crate::common::RegisterField::<
4299 0,
4300 0x1f,
4301 1,
4302 0,
4303 lvdlvlr::Lvd1Lvl,
4304 lvdlvlr::Lvd1Lvl,
4305 Lvdlvlr_SPEC,
4306 crate::common::RW,
4307 >::from_register(self, 0)
4308 }
4309
4310 #[doc = "Voltage Detection 2 Level Select (Standard voltage during fall in voltage)"]
4311 #[inline(always)]
4312 pub fn lvd2lvl(
4313 self,
4314 ) -> crate::common::RegisterField<
4315 5,
4316 0x7,
4317 1,
4318 0,
4319 lvdlvlr::Lvd2Lvl,
4320 lvdlvlr::Lvd2Lvl,
4321 Lvdlvlr_SPEC,
4322 crate::common::RW,
4323 > {
4324 crate::common::RegisterField::<
4325 5,
4326 0x7,
4327 1,
4328 0,
4329 lvdlvlr::Lvd2Lvl,
4330 lvdlvlr::Lvd2Lvl,
4331 Lvdlvlr_SPEC,
4332 crate::common::RW,
4333 >::from_register(self, 0)
4334 }
4335}
4336impl ::core::default::Default for Lvdlvlr {
4337 #[inline(always)]
4338 fn default() -> Lvdlvlr {
4339 <crate::RegValueT<Lvdlvlr_SPEC> as RegisterValue<_>>::new(7)
4340 }
4341}
4342pub mod lvdlvlr {
4343
4344 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4345 pub struct Lvd1Lvl_SPEC;
4346 pub type Lvd1Lvl = crate::EnumBitfieldStruct<u8, Lvd1Lvl_SPEC>;
4347 impl Lvd1Lvl {
4348 #[doc = "Vdet1_0"]
4349 pub const _0_X_00: Self = Self::new(0);
4350
4351 #[doc = "Vdet1_1"]
4352 pub const _0_X_01: Self = Self::new(1);
4353
4354 #[doc = "Vdet1_2"]
4355 pub const _0_X_02: Self = Self::new(2);
4356
4357 #[doc = "Vdet1_3"]
4358 pub const _0_X_03: Self = Self::new(3);
4359
4360 #[doc = "Vdet1_4"]
4361 pub const _0_X_04: Self = Self::new(4);
4362
4363 #[doc = "Vdet1_5"]
4364 pub const _0_X_05: Self = Self::new(5);
4365
4366 #[doc = "Vdet1_6"]
4367 pub const _0_X_06: Self = Self::new(6);
4368
4369 #[doc = "Vdet1_7"]
4370 pub const _0_X_07: Self = Self::new(7);
4371
4372 #[doc = "Vdet1_8"]
4373 pub const _0_X_08: Self = Self::new(8);
4374
4375 #[doc = "Vdet1_9"]
4376 pub const _0_X_09: Self = Self::new(9);
4377
4378 #[doc = "Vdet1_A"]
4379 pub const _0_X_0_A: Self = Self::new(10);
4380
4381 #[doc = "Vdet1_B"]
4382 pub const _0_X_0_B: Self = Self::new(11);
4383
4384 #[doc = "Vdet1_C"]
4385 pub const _0_X_0_C: Self = Self::new(12);
4386
4387 #[doc = "Vdet1_D"]
4388 pub const _0_X_0_D: Self = Self::new(13);
4389
4390 #[doc = "Vdet1_E"]
4391 pub const _0_X_0_E: Self = Self::new(14);
4392
4393 #[doc = "Vdet1_F"]
4394 pub const _0_X_0_F: Self = Self::new(15);
4395 }
4396 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4397 pub struct Lvd2Lvl_SPEC;
4398 pub type Lvd2Lvl = crate::EnumBitfieldStruct<u8, Lvd2Lvl_SPEC>;
4399 impl Lvd2Lvl {
4400 #[doc = "Vdet2_0"]
4401 pub const _000: Self = Self::new(0);
4402
4403 #[doc = "Vdet2_1"]
4404 pub const _001: Self = Self::new(1);
4405
4406 #[doc = "Vdet2_2"]
4407 pub const _010: Self = Self::new(2);
4408
4409 #[doc = "Vdet2_3"]
4410 pub const _011: Self = Self::new(3);
4411 }
4412}
4413#[doc(hidden)]
4414#[derive(Copy, Clone, Eq, PartialEq)]
4415pub struct Lvd1Cr0_SPEC;
4416impl crate::sealed::RegSpec for Lvd1Cr0_SPEC {
4417 type DataType = u8;
4418}
4419
4420#[doc = "Voltage Monitor 1 Circuit Control Register 0"]
4421pub type Lvd1Cr0 = crate::RegValueT<Lvd1Cr0_SPEC>;
4422
4423impl Lvd1Cr0 {
4424 #[doc = "Voltage Monitor 1 Interrupt/Reset Enable"]
4425 #[inline(always)]
4426 pub fn rie(
4427 self,
4428 ) -> crate::common::RegisterField<
4429 0,
4430 0x1,
4431 1,
4432 0,
4433 lvd1cr0::Rie,
4434 lvd1cr0::Rie,
4435 Lvd1Cr0_SPEC,
4436 crate::common::RW,
4437 > {
4438 crate::common::RegisterField::<
4439 0,
4440 0x1,
4441 1,
4442 0,
4443 lvd1cr0::Rie,
4444 lvd1cr0::Rie,
4445 Lvd1Cr0_SPEC,
4446 crate::common::RW,
4447 >::from_register(self, 0)
4448 }
4449
4450 #[doc = "Voltage Monitor 1 Circuit Comparison Result Output Enable"]
4451 #[inline(always)]
4452 pub fn cmpe(
4453 self,
4454 ) -> crate::common::RegisterField<
4455 2,
4456 0x1,
4457 1,
4458 0,
4459 lvd1cr0::Cmpe,
4460 lvd1cr0::Cmpe,
4461 Lvd1Cr0_SPEC,
4462 crate::common::RW,
4463 > {
4464 crate::common::RegisterField::<
4465 2,
4466 0x1,
4467 1,
4468 0,
4469 lvd1cr0::Cmpe,
4470 lvd1cr0::Cmpe,
4471 Lvd1Cr0_SPEC,
4472 crate::common::RW,
4473 >::from_register(self, 0)
4474 }
4475
4476 #[doc = "Voltage Monitor 1 Circuit Mode Select"]
4477 #[inline(always)]
4478 pub fn ri(
4479 self,
4480 ) -> crate::common::RegisterField<
4481 6,
4482 0x1,
4483 1,
4484 0,
4485 lvd1cr0::Ri,
4486 lvd1cr0::Ri,
4487 Lvd1Cr0_SPEC,
4488 crate::common::RW,
4489 > {
4490 crate::common::RegisterField::<
4491 6,
4492 0x1,
4493 1,
4494 0,
4495 lvd1cr0::Ri,
4496 lvd1cr0::Ri,
4497 Lvd1Cr0_SPEC,
4498 crate::common::RW,
4499 >::from_register(self, 0)
4500 }
4501
4502 #[doc = "Voltage Monitor 1 Reset Negate Select"]
4503 #[inline(always)]
4504 pub fn rn(
4505 self,
4506 ) -> crate::common::RegisterField<
4507 7,
4508 0x1,
4509 1,
4510 0,
4511 lvd1cr0::Rn,
4512 lvd1cr0::Rn,
4513 Lvd1Cr0_SPEC,
4514 crate::common::RW,
4515 > {
4516 crate::common::RegisterField::<
4517 7,
4518 0x1,
4519 1,
4520 0,
4521 lvd1cr0::Rn,
4522 lvd1cr0::Rn,
4523 Lvd1Cr0_SPEC,
4524 crate::common::RW,
4525 >::from_register(self, 0)
4526 }
4527}
4528impl ::core::default::Default for Lvd1Cr0 {
4529 #[inline(always)]
4530 fn default() -> Lvd1Cr0 {
4531 <crate::RegValueT<Lvd1Cr0_SPEC> as RegisterValue<_>>::new(128)
4532 }
4533}
4534pub mod lvd1cr0 {
4535
4536 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4537 pub struct Rie_SPEC;
4538 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
4539 impl Rie {
4540 #[doc = "Disable"]
4541 pub const _0: Self = Self::new(0);
4542
4543 #[doc = "Enable"]
4544 pub const _1: Self = Self::new(1);
4545 }
4546 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4547 pub struct Cmpe_SPEC;
4548 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
4549 impl Cmpe {
4550 #[doc = "Disable voltage monitor 1 circuit comparison result output"]
4551 pub const _0: Self = Self::new(0);
4552
4553 #[doc = "Enable voltage monitor 1 circuit comparison result output"]
4554 pub const _1: Self = Self::new(1);
4555 }
4556 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4557 pub struct Ri_SPEC;
4558 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
4559 impl Ri {
4560 #[doc = "Generate voltage monitor 1 interrupt on Vdet1 crossing"]
4561 pub const _0: Self = Self::new(0);
4562
4563 #[doc = "Enable voltage monitor 1 reset when the voltage falls to and below Vdet1"]
4564 pub const _1: Self = Self::new(1);
4565 }
4566 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4567 pub struct Rn_SPEC;
4568 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
4569 impl Rn {
4570 #[doc = "Negate after a stabilization time (tLVD1) when VCC > Vdet1 is detected"]
4571 pub const _0: Self = Self::new(0);
4572
4573 #[doc = "Negate after a stabilization time (tLVD1) on assertion of the LVD1 reset"]
4574 pub const _1: Self = Self::new(1);
4575 }
4576}
4577#[doc(hidden)]
4578#[derive(Copy, Clone, Eq, PartialEq)]
4579pub struct Lvd2Cr0_SPEC;
4580impl crate::sealed::RegSpec for Lvd2Cr0_SPEC {
4581 type DataType = u8;
4582}
4583
4584#[doc = "Voltage Monitor 2 Circuit Control Register 0"]
4585pub type Lvd2Cr0 = crate::RegValueT<Lvd2Cr0_SPEC>;
4586
4587impl Lvd2Cr0 {
4588 #[doc = "Voltage Monitor 2 Interrupt/Reset Enable"]
4589 #[inline(always)]
4590 pub fn rie(
4591 self,
4592 ) -> crate::common::RegisterField<
4593 0,
4594 0x1,
4595 1,
4596 0,
4597 lvd2cr0::Rie,
4598 lvd2cr0::Rie,
4599 Lvd2Cr0_SPEC,
4600 crate::common::RW,
4601 > {
4602 crate::common::RegisterField::<
4603 0,
4604 0x1,
4605 1,
4606 0,
4607 lvd2cr0::Rie,
4608 lvd2cr0::Rie,
4609 Lvd2Cr0_SPEC,
4610 crate::common::RW,
4611 >::from_register(self, 0)
4612 }
4613
4614 #[doc = "Voltage Monitor 2 Circuit Comparison Result Output Enable"]
4615 #[inline(always)]
4616 pub fn cmpe(
4617 self,
4618 ) -> crate::common::RegisterField<
4619 2,
4620 0x1,
4621 1,
4622 0,
4623 lvd2cr0::Cmpe,
4624 lvd2cr0::Cmpe,
4625 Lvd2Cr0_SPEC,
4626 crate::common::RW,
4627 > {
4628 crate::common::RegisterField::<
4629 2,
4630 0x1,
4631 1,
4632 0,
4633 lvd2cr0::Cmpe,
4634 lvd2cr0::Cmpe,
4635 Lvd2Cr0_SPEC,
4636 crate::common::RW,
4637 >::from_register(self, 0)
4638 }
4639
4640 #[doc = "Voltage Monitor 2 Circuit Mode Select"]
4641 #[inline(always)]
4642 pub fn ri(
4643 self,
4644 ) -> crate::common::RegisterField<
4645 6,
4646 0x1,
4647 1,
4648 0,
4649 lvd2cr0::Ri,
4650 lvd2cr0::Ri,
4651 Lvd2Cr0_SPEC,
4652 crate::common::RW,
4653 > {
4654 crate::common::RegisterField::<
4655 6,
4656 0x1,
4657 1,
4658 0,
4659 lvd2cr0::Ri,
4660 lvd2cr0::Ri,
4661 Lvd2Cr0_SPEC,
4662 crate::common::RW,
4663 >::from_register(self, 0)
4664 }
4665
4666 #[doc = "Voltage Monitor 2 Reset Negate Select"]
4667 #[inline(always)]
4668 pub fn rn(
4669 self,
4670 ) -> crate::common::RegisterField<
4671 7,
4672 0x1,
4673 1,
4674 0,
4675 lvd2cr0::Rn,
4676 lvd2cr0::Rn,
4677 Lvd2Cr0_SPEC,
4678 crate::common::RW,
4679 > {
4680 crate::common::RegisterField::<
4681 7,
4682 0x1,
4683 1,
4684 0,
4685 lvd2cr0::Rn,
4686 lvd2cr0::Rn,
4687 Lvd2Cr0_SPEC,
4688 crate::common::RW,
4689 >::from_register(self, 0)
4690 }
4691}
4692impl ::core::default::Default for Lvd2Cr0 {
4693 #[inline(always)]
4694 fn default() -> Lvd2Cr0 {
4695 <crate::RegValueT<Lvd2Cr0_SPEC> as RegisterValue<_>>::new(128)
4696 }
4697}
4698pub mod lvd2cr0 {
4699
4700 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4701 pub struct Rie_SPEC;
4702 pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
4703 impl Rie {
4704 #[doc = "Disable"]
4705 pub const _0: Self = Self::new(0);
4706
4707 #[doc = "Enable"]
4708 pub const _1: Self = Self::new(1);
4709 }
4710 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4711 pub struct Cmpe_SPEC;
4712 pub type Cmpe = crate::EnumBitfieldStruct<u8, Cmpe_SPEC>;
4713 impl Cmpe {
4714 #[doc = "Disable voltage monitor 2 circuit comparison result output"]
4715 pub const _0: Self = Self::new(0);
4716
4717 #[doc = "Enable voltage monitor 2 circuit comparison result output"]
4718 pub const _1: Self = Self::new(1);
4719 }
4720 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4721 pub struct Ri_SPEC;
4722 pub type Ri = crate::EnumBitfieldStruct<u8, Ri_SPEC>;
4723 impl Ri {
4724 #[doc = "Generate voltage monitor 2 interrupt on Vdet2 crossing"]
4725 pub const _0: Self = Self::new(0);
4726
4727 #[doc = "Enable voltage monitor 2 reset when the voltage falls to and below Vdet2"]
4728 pub const _1: Self = Self::new(1);
4729 }
4730 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4731 pub struct Rn_SPEC;
4732 pub type Rn = crate::EnumBitfieldStruct<u8, Rn_SPEC>;
4733 impl Rn {
4734 #[doc = "Negate after a stabilization time (tLVD2) when VCC > Vdet2 is detected"]
4735 pub const _0: Self = Self::new(0);
4736
4737 #[doc = "Negate after a stabilization time (tLVD2) on assertion of the LVD2 reset"]
4738 pub const _1: Self = Self::new(1);
4739 }
4740}
4741#[doc(hidden)]
4742#[derive(Copy, Clone, Eq, PartialEq)]
4743pub struct Sosccr_SPEC;
4744impl crate::sealed::RegSpec for Sosccr_SPEC {
4745 type DataType = u8;
4746}
4747
4748#[doc = "Sub-Clock Oscillator Control Register"]
4749pub type Sosccr = crate::RegValueT<Sosccr_SPEC>;
4750
4751impl Sosccr {
4752 #[doc = "Sub Clock Oscillator Stop"]
4753 #[inline(always)]
4754 pub fn sostp(
4755 self,
4756 ) -> crate::common::RegisterField<
4757 0,
4758 0x1,
4759 1,
4760 0,
4761 sosccr::Sostp,
4762 sosccr::Sostp,
4763 Sosccr_SPEC,
4764 crate::common::RW,
4765 > {
4766 crate::common::RegisterField::<
4767 0,
4768 0x1,
4769 1,
4770 0,
4771 sosccr::Sostp,
4772 sosccr::Sostp,
4773 Sosccr_SPEC,
4774 crate::common::RW,
4775 >::from_register(self, 0)
4776 }
4777}
4778impl ::core::default::Default for Sosccr {
4779 #[inline(always)]
4780 fn default() -> Sosccr {
4781 <crate::RegValueT<Sosccr_SPEC> as RegisterValue<_>>::new(1)
4782 }
4783}
4784pub mod sosccr {
4785
4786 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4787 pub struct Sostp_SPEC;
4788 pub type Sostp = crate::EnumBitfieldStruct<u8, Sostp_SPEC>;
4789 impl Sostp {
4790 #[doc = "Operate the sub-clock oscillator"]
4791 pub const _0: Self = Self::new(0);
4792
4793 #[doc = "Stop the sub-clock oscillator"]
4794 pub const _1: Self = Self::new(1);
4795 }
4796}
4797#[doc(hidden)]
4798#[derive(Copy, Clone, Eq, PartialEq)]
4799pub struct Somcr_SPEC;
4800impl crate::sealed::RegSpec for Somcr_SPEC {
4801 type DataType = u8;
4802}
4803
4804#[doc = "Sub-Clock Oscillator Mode Control Register"]
4805pub type Somcr = crate::RegValueT<Somcr_SPEC>;
4806
4807impl Somcr {
4808 #[doc = "Sub-Clock Oscillator Drive Capability Switching"]
4809 #[inline(always)]
4810 pub fn sodrv(
4811 self,
4812 ) -> crate::common::RegisterField<
4813 0,
4814 0x3,
4815 1,
4816 0,
4817 somcr::Sodrv,
4818 somcr::Sodrv,
4819 Somcr_SPEC,
4820 crate::common::RW,
4821 > {
4822 crate::common::RegisterField::<
4823 0,
4824 0x3,
4825 1,
4826 0,
4827 somcr::Sodrv,
4828 somcr::Sodrv,
4829 Somcr_SPEC,
4830 crate::common::RW,
4831 >::from_register(self, 0)
4832 }
4833}
4834impl ::core::default::Default for Somcr {
4835 #[inline(always)]
4836 fn default() -> Somcr {
4837 <crate::RegValueT<Somcr_SPEC> as RegisterValue<_>>::new(0)
4838 }
4839}
4840pub mod somcr {
4841
4842 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4843 pub struct Sodrv_SPEC;
4844 pub type Sodrv = crate::EnumBitfieldStruct<u8, Sodrv_SPEC>;
4845 impl Sodrv {
4846 #[doc = "Normal Mode"]
4847 pub const _00: Self = Self::new(0);
4848
4849 #[doc = "Low Power Mode 1"]
4850 pub const _01: Self = Self::new(1);
4851
4852 #[doc = "Low Power Mode 2"]
4853 pub const _10: Self = Self::new(2);
4854
4855 #[doc = "Low Power Mode 3"]
4856 pub const _11: Self = Self::new(3);
4857 }
4858}
4859#[doc(hidden)]
4860#[derive(Copy, Clone, Eq, PartialEq)]
4861pub struct Somrg_SPEC;
4862impl crate::sealed::RegSpec for Somrg_SPEC {
4863 type DataType = u8;
4864}
4865
4866#[doc = "Sub-Clock Oscillator Margin Check Register"]
4867pub type Somrg = crate::RegValueT<Somrg_SPEC>;
4868
4869impl Somrg {
4870 #[doc = "Sub Clock Oscillator Margin check Switching"]
4871 #[inline(always)]
4872 pub fn soscmrg(
4873 self,
4874 ) -> crate::common::RegisterField<
4875 0,
4876 0x3,
4877 1,
4878 0,
4879 somrg::Soscmrg,
4880 somrg::Soscmrg,
4881 Somrg_SPEC,
4882 crate::common::RW,
4883 > {
4884 crate::common::RegisterField::<
4885 0,
4886 0x3,
4887 1,
4888 0,
4889 somrg::Soscmrg,
4890 somrg::Soscmrg,
4891 Somrg_SPEC,
4892 crate::common::RW,
4893 >::from_register(self, 0)
4894 }
4895}
4896impl ::core::default::Default for Somrg {
4897 #[inline(always)]
4898 fn default() -> Somrg {
4899 <crate::RegValueT<Somrg_SPEC> as RegisterValue<_>>::new(0)
4900 }
4901}
4902pub mod somrg {
4903
4904 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4905 pub struct Soscmrg_SPEC;
4906 pub type Soscmrg = crate::EnumBitfieldStruct<u8, Soscmrg_SPEC>;
4907 impl Soscmrg {
4908 #[doc = "Normal Current"]
4909 pub const _00: Self = Self::new(0);
4910
4911 #[doc = "Lower Margin check"]
4912 pub const _01: Self = Self::new(1);
4913
4914 #[doc = "Upper Margin check"]
4915 pub const _10: Self = Self::new(2);
4916
4917 #[doc = "Setting prohibited"]
4918 pub const _11: Self = Self::new(3);
4919 }
4920}
4921#[doc(hidden)]
4922#[derive(Copy, Clone, Eq, PartialEq)]
4923pub struct Lococr_SPEC;
4924impl crate::sealed::RegSpec for Lococr_SPEC {
4925 type DataType = u8;
4926}
4927
4928#[doc = "Low-Speed On-Chip Oscillator Control Register"]
4929pub type Lococr = crate::RegValueT<Lococr_SPEC>;
4930
4931impl Lococr {
4932 #[doc = "LOCO Stop"]
4933 #[inline(always)]
4934 pub fn lcstp(
4935 self,
4936 ) -> crate::common::RegisterField<
4937 0,
4938 0x1,
4939 1,
4940 0,
4941 lococr::Lcstp,
4942 lococr::Lcstp,
4943 Lococr_SPEC,
4944 crate::common::RW,
4945 > {
4946 crate::common::RegisterField::<
4947 0,
4948 0x1,
4949 1,
4950 0,
4951 lococr::Lcstp,
4952 lococr::Lcstp,
4953 Lococr_SPEC,
4954 crate::common::RW,
4955 >::from_register(self, 0)
4956 }
4957}
4958impl ::core::default::Default for Lococr {
4959 #[inline(always)]
4960 fn default() -> Lococr {
4961 <crate::RegValueT<Lococr_SPEC> as RegisterValue<_>>::new(0)
4962 }
4963}
4964pub mod lococr {
4965
4966 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4967 pub struct Lcstp_SPEC;
4968 pub type Lcstp = crate::EnumBitfieldStruct<u8, Lcstp_SPEC>;
4969 impl Lcstp {
4970 #[doc = "Operate the LOCO clock"]
4971 pub const _0: Self = Self::new(0);
4972
4973 #[doc = "Stop the LOCO clock"]
4974 pub const _1: Self = Self::new(1);
4975 }
4976}
4977#[doc(hidden)]
4978#[derive(Copy, Clone, Eq, PartialEq)]
4979pub struct Locoutcr_SPEC;
4980impl crate::sealed::RegSpec for Locoutcr_SPEC {
4981 type DataType = u8;
4982}
4983
4984#[doc = "LOCO User Trimming Control Register"]
4985pub type Locoutcr = crate::RegValueT<Locoutcr_SPEC>;
4986
4987impl Locoutcr {
4988 #[doc = "LOCO User Trimming"]
4989 #[inline(always)]
4990 pub fn locoutrm(
4991 self,
4992 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Locoutcr_SPEC, crate::common::RW> {
4993 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Locoutcr_SPEC,crate::common::RW>::from_register(self,0)
4994 }
4995}
4996impl ::core::default::Default for Locoutcr {
4997 #[inline(always)]
4998 fn default() -> Locoutcr {
4999 <crate::RegValueT<Locoutcr_SPEC> as RegisterValue<_>>::new(0)
5000 }
5001}