ra2e1_pac/
lib.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.51.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:43 +0000
19#![cfg_attr(not(feature = "tracing"), no_std)]
20#![allow(non_camel_case_types)]
21#![doc = "Arm Cortex-M23 based Microcontroller RA2E1 device"]
22pub mod common;
23pub use common::*;
24
25#[cfg(feature = "tracing")]
26pub mod reg_name;
27#[cfg(feature = "tracing")]
28pub mod tracing;
29
30#[cfg(feature = "acmplp")]
31pub mod acmplp;
32#[cfg(feature = "adc120")]
33pub mod adc120;
34#[cfg(feature = "agt0")]
35pub mod agt0;
36#[cfg(feature = "bus")]
37pub mod bus;
38#[cfg(feature = "cac")]
39pub mod cac;
40#[cfg(feature = "crc")]
41pub mod crc;
42#[cfg(feature = "ctsu")]
43pub mod ctsu;
44#[cfg(feature = "dbg")]
45pub mod dbg;
46#[cfg(feature = "doc")]
47pub mod doc;
48#[cfg(feature = "dtc")]
49pub mod dtc;
50#[cfg(feature = "elc")]
51pub mod elc;
52#[cfg(feature = "flcn")]
53pub mod flcn;
54#[cfg(feature = "gpt164")]
55pub mod gpt164;
56#[cfg(feature = "gpt320")]
57pub mod gpt320;
58#[cfg(feature = "gpt_ops")]
59pub mod gpt_ops;
60#[cfg(feature = "icu")]
61pub mod icu;
62#[cfg(feature = "iic0")]
63pub mod iic0;
64#[cfg(feature = "iic0wu")]
65pub mod iic0wu;
66#[cfg(feature = "iwdt")]
67pub mod iwdt;
68#[cfg(feature = "kint")]
69pub mod kint;
70#[cfg(feature = "mstp")]
71pub mod mstp;
72#[cfg(feature = "pfs")]
73pub mod pfs;
74#[cfg(feature = "poeg")]
75pub mod poeg;
76#[cfg(feature = "port0")]
77pub mod port0;
78#[cfg(feature = "port1")]
79pub mod port1;
80#[cfg(feature = "rmpu")]
81pub mod rmpu;
82#[cfg(feature = "rtc")]
83pub mod rtc;
84#[cfg(feature = "sci0")]
85pub mod sci0;
86#[cfg(feature = "sci1")]
87pub mod sci1;
88#[cfg(feature = "spi0")]
89pub mod spi0;
90#[cfg(feature = "sram")]
91pub mod sram;
92#[cfg(feature = "sysc")]
93pub mod sysc;
94#[cfg(feature = "wdt")]
95pub mod wdt;
96
97#[cfg(feature = "rmpu")]
98#[derive(Copy, Clone, Eq, PartialEq)]
99pub struct Rmpu {
100    ptr: *mut u8,
101}
102#[cfg(feature = "rmpu")]
103pub const RMPU: self::Rmpu = self::Rmpu {
104    ptr: 0x40000000u32 as _,
105};
106#[cfg(feature = "sram")]
107#[derive(Copy, Clone, Eq, PartialEq)]
108pub struct Sram {
109    ptr: *mut u8,
110}
111#[cfg(feature = "sram")]
112pub const SRAM: self::Sram = self::Sram {
113    ptr: 0x40002000u32 as _,
114};
115#[cfg(feature = "bus")]
116#[derive(Copy, Clone, Eq, PartialEq)]
117pub struct Bus {
118    ptr: *mut u8,
119}
120#[cfg(feature = "bus")]
121pub const BUS: self::Bus = self::Bus {
122    ptr: 0x40003000u32 as _,
123};
124#[cfg(feature = "dtc")]
125#[derive(Copy, Clone, Eq, PartialEq)]
126pub struct Dtc {
127    ptr: *mut u8,
128}
129#[cfg(feature = "dtc")]
130pub const DTC: self::Dtc = self::Dtc {
131    ptr: 0x40005400u32 as _,
132};
133#[cfg(feature = "icu")]
134#[derive(Copy, Clone, Eq, PartialEq)]
135pub struct Icu {
136    ptr: *mut u8,
137}
138#[cfg(feature = "icu")]
139pub const ICU: self::Icu = self::Icu {
140    ptr: 0x40006000u32 as _,
141};
142#[cfg(feature = "dbg")]
143#[derive(Copy, Clone, Eq, PartialEq)]
144pub struct Dbg {
145    ptr: *mut u8,
146}
147#[cfg(feature = "dbg")]
148pub const DBG: self::Dbg = self::Dbg {
149    ptr: 0x4001b000u32 as _,
150};
151#[cfg(feature = "sysc")]
152#[derive(Copy, Clone, Eq, PartialEq)]
153pub struct Sysc {
154    ptr: *mut u8,
155}
156#[cfg(feature = "sysc")]
157pub const SYSC: self::Sysc = self::Sysc {
158    ptr: 0x4001e000u32 as _,
159};
160#[cfg(feature = "port0")]
161#[derive(Copy, Clone, Eq, PartialEq)]
162pub struct Port0 {
163    ptr: *mut u8,
164}
165#[cfg(feature = "port0")]
166pub const PORT0: self::Port0 = self::Port0 {
167    ptr: 0x40040000u32 as _,
168};
169#[cfg(feature = "port1")]
170#[derive(Copy, Clone, Eq, PartialEq)]
171pub struct Port1 {
172    ptr: *mut u8,
173}
174#[cfg(feature = "port1")]
175pub const PORT1: self::Port1 = self::Port1 {
176    ptr: 0x40040020u32 as _,
177};
178#[cfg(feature = "port2")]
179pub const PORT2: self::Port1 = self::Port1 {
180    ptr: 0x40040040u32 as _,
181};
182#[cfg(feature = "port3")]
183pub const PORT3: self::Port0 = self::Port0 {
184    ptr: 0x40040060u32 as _,
185};
186#[cfg(feature = "port4")]
187pub const PORT4: self::Port0 = self::Port0 {
188    ptr: 0x40040080u32 as _,
189};
190#[cfg(feature = "port5")]
191pub const PORT5: self::Port0 = self::Port0 {
192    ptr: 0x400400a0u32 as _,
193};
194#[cfg(feature = "port9")]
195pub const PORT9: self::Port0 = self::Port0 {
196    ptr: 0x40040120u32 as _,
197};
198#[cfg(feature = "pfs")]
199#[derive(Copy, Clone, Eq, PartialEq)]
200pub struct Pfs {
201    ptr: *mut u8,
202}
203#[cfg(feature = "pfs")]
204pub const PFS: self::Pfs = self::Pfs {
205    ptr: 0x40040800u32 as _,
206};
207#[cfg(feature = "elc")]
208#[derive(Copy, Clone, Eq, PartialEq)]
209pub struct Elc {
210    ptr: *mut u8,
211}
212#[cfg(feature = "elc")]
213pub const ELC: self::Elc = self::Elc {
214    ptr: 0x40041000u32 as _,
215};
216#[cfg(feature = "poeg")]
217#[derive(Copy, Clone, Eq, PartialEq)]
218pub struct Poeg {
219    ptr: *mut u8,
220}
221#[cfg(feature = "poeg")]
222pub const POEG: self::Poeg = self::Poeg {
223    ptr: 0x40042000u32 as _,
224};
225#[cfg(feature = "rtc")]
226#[derive(Copy, Clone, Eq, PartialEq)]
227pub struct Rtc {
228    ptr: *mut u8,
229}
230#[cfg(feature = "rtc")]
231pub const RTC: self::Rtc = self::Rtc {
232    ptr: 0x40044000u32 as _,
233};
234#[cfg(feature = "wdt")]
235#[derive(Copy, Clone, Eq, PartialEq)]
236pub struct Wdt {
237    ptr: *mut u8,
238}
239#[cfg(feature = "wdt")]
240pub const WDT: self::Wdt = self::Wdt {
241    ptr: 0x40044200u32 as _,
242};
243#[cfg(feature = "iwdt")]
244#[derive(Copy, Clone, Eq, PartialEq)]
245pub struct Iwdt {
246    ptr: *mut u8,
247}
248#[cfg(feature = "iwdt")]
249pub const IWDT: self::Iwdt = self::Iwdt {
250    ptr: 0x40044400u32 as _,
251};
252#[cfg(feature = "cac")]
253#[derive(Copy, Clone, Eq, PartialEq)]
254pub struct Cac {
255    ptr: *mut u8,
256}
257#[cfg(feature = "cac")]
258pub const CAC: self::Cac = self::Cac {
259    ptr: 0x40044600u32 as _,
260};
261#[cfg(feature = "mstp")]
262#[derive(Copy, Clone, Eq, PartialEq)]
263pub struct Mstp {
264    ptr: *mut u8,
265}
266#[cfg(feature = "mstp")]
267pub const MSTP: self::Mstp = self::Mstp {
268    ptr: 0x40047000u32 as _,
269};
270#[cfg(feature = "iic0")]
271#[derive(Copy, Clone, Eq, PartialEq)]
272pub struct Iic0 {
273    ptr: *mut u8,
274}
275#[cfg(feature = "iic0")]
276pub const IIC0: self::Iic0 = self::Iic0 {
277    ptr: 0x40053000u32 as _,
278};
279#[cfg(feature = "iic0wu")]
280#[derive(Copy, Clone, Eq, PartialEq)]
281pub struct Iic0Wu {
282    ptr: *mut u8,
283}
284#[cfg(feature = "iic0wu")]
285pub const IIC0WU: self::Iic0Wu = self::Iic0Wu {
286    ptr: 0x40053014u32 as _,
287};
288#[cfg(feature = "doc")]
289#[derive(Copy, Clone, Eq, PartialEq)]
290pub struct Doc {
291    ptr: *mut u8,
292}
293#[cfg(feature = "doc")]
294pub const DOC: self::Doc = self::Doc {
295    ptr: 0x40054100u32 as _,
296};
297#[cfg(feature = "adc120")]
298#[derive(Copy, Clone, Eq, PartialEq)]
299pub struct Adc120 {
300    ptr: *mut u8,
301}
302#[cfg(feature = "adc120")]
303pub const ADC120: self::Adc120 = self::Adc120 {
304    ptr: 0x4005c000u32 as _,
305};
306#[cfg(feature = "sci0")]
307#[derive(Copy, Clone, Eq, PartialEq)]
308pub struct Sci0 {
309    ptr: *mut u8,
310}
311#[cfg(feature = "sci0")]
312pub const SCI0: self::Sci0 = self::Sci0 {
313    ptr: 0x40070000u32 as _,
314};
315#[cfg(feature = "sci1")]
316#[derive(Copy, Clone, Eq, PartialEq)]
317pub struct Sci1 {
318    ptr: *mut u8,
319}
320#[cfg(feature = "sci1")]
321pub const SCI1: self::Sci1 = self::Sci1 {
322    ptr: 0x40070020u32 as _,
323};
324#[cfg(feature = "sci2")]
325pub const SCI2: self::Sci1 = self::Sci1 {
326    ptr: 0x40070040u32 as _,
327};
328#[cfg(feature = "sci9")]
329pub const SCI9: self::Sci1 = self::Sci1 {
330    ptr: 0x40070120u32 as _,
331};
332#[cfg(feature = "spi0")]
333#[derive(Copy, Clone, Eq, PartialEq)]
334pub struct Spi0 {
335    ptr: *mut u8,
336}
337#[cfg(feature = "spi0")]
338pub const SPI0: self::Spi0 = self::Spi0 {
339    ptr: 0x40072000u32 as _,
340};
341#[cfg(feature = "crc")]
342#[derive(Copy, Clone, Eq, PartialEq)]
343pub struct Crc {
344    ptr: *mut u8,
345}
346#[cfg(feature = "crc")]
347pub const CRC: self::Crc = self::Crc {
348    ptr: 0x40074000u32 as _,
349};
350#[cfg(feature = "gpt320")]
351#[derive(Copy, Clone, Eq, PartialEq)]
352pub struct Gpt320 {
353    ptr: *mut u8,
354}
355#[cfg(feature = "gpt320")]
356pub const GPT320: self::Gpt320 = self::Gpt320 {
357    ptr: 0x40078000u32 as _,
358};
359#[cfg(feature = "gpt164")]
360#[derive(Copy, Clone, Eq, PartialEq)]
361pub struct Gpt164 {
362    ptr: *mut u8,
363}
364#[cfg(feature = "gpt164")]
365pub const GPT164: self::Gpt164 = self::Gpt164 {
366    ptr: 0x40078400u32 as _,
367};
368#[cfg(feature = "gpt165")]
369pub const GPT165: self::Gpt164 = self::Gpt164 {
370    ptr: 0x40078500u32 as _,
371};
372#[cfg(feature = "gpt166")]
373pub const GPT166: self::Gpt164 = self::Gpt164 {
374    ptr: 0x40078600u32 as _,
375};
376#[cfg(feature = "gpt167")]
377pub const GPT167: self::Gpt164 = self::Gpt164 {
378    ptr: 0x40078700u32 as _,
379};
380#[cfg(feature = "gpt168")]
381pub const GPT168: self::Gpt164 = self::Gpt164 {
382    ptr: 0x40078800u32 as _,
383};
384#[cfg(feature = "gpt169")]
385pub const GPT169: self::Gpt164 = self::Gpt164 {
386    ptr: 0x40078900u32 as _,
387};
388#[cfg(feature = "gpt_ops")]
389#[derive(Copy, Clone, Eq, PartialEq)]
390pub struct GptOps {
391    ptr: *mut u8,
392}
393#[cfg(feature = "gpt_ops")]
394pub const GPT_OPS: self::GptOps = self::GptOps {
395    ptr: 0x40078ff0u32 as _,
396};
397#[cfg(feature = "kint")]
398#[derive(Copy, Clone, Eq, PartialEq)]
399pub struct Kint {
400    ptr: *mut u8,
401}
402#[cfg(feature = "kint")]
403pub const KINT: self::Kint = self::Kint {
404    ptr: 0x40080000u32 as _,
405};
406#[cfg(feature = "ctsu")]
407#[derive(Copy, Clone, Eq, PartialEq)]
408pub struct Ctsu {
409    ptr: *mut u8,
410}
411#[cfg(feature = "ctsu")]
412pub const CTSU: self::Ctsu = self::Ctsu {
413    ptr: 0x40082000u32 as _,
414};
415#[cfg(feature = "agt0")]
416#[derive(Copy, Clone, Eq, PartialEq)]
417pub struct Agt0 {
418    ptr: *mut u8,
419}
420#[cfg(feature = "agt0")]
421pub const AGT0: self::Agt0 = self::Agt0 {
422    ptr: 0x40084000u32 as _,
423};
424#[cfg(feature = "agt1")]
425pub const AGT1: self::Agt0 = self::Agt0 {
426    ptr: 0x40084100u32 as _,
427};
428#[cfg(feature = "acmplp")]
429#[derive(Copy, Clone, Eq, PartialEq)]
430pub struct Acmplp {
431    ptr: *mut u8,
432}
433#[cfg(feature = "acmplp")]
434pub const ACMPLP: self::Acmplp = self::Acmplp {
435    ptr: 0x40085e00u32 as _,
436};
437#[cfg(feature = "flcn")]
438#[derive(Copy, Clone, Eq, PartialEq)]
439pub struct Flcn {
440    ptr: *mut u8,
441}
442#[cfg(feature = "flcn")]
443pub const FLCN: self::Flcn = self::Flcn {
444    ptr: 0x407ec000u32 as _,
445};
446
447pub use cortex_m::peripheral::Peripherals as CorePeripherals;
448pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
449#[doc = "Number available in the NVIC for configuring priority"]
450pub const NVIC_PRIO_BITS: u8 = 2;
451#[doc(hidden)]
452pub union Vector {
453    _handler: unsafe extern "C" fn(),
454    _reserved: u32,
455}
456#[cfg(feature = "rt")]
457pub use self::Interrupt as interrupt;
458#[cfg(feature = "rt")]
459pub use cortex_m_rt::interrupt;
460#[cfg(feature = "rt")]
461pub mod interrupt_handlers {
462    unsafe extern "C" {
463        pub fn IEL0();
464        pub fn IEL1();
465        pub fn IEL2();
466        pub fn IEL3();
467        pub fn IEL4();
468        pub fn IEL5();
469        pub fn IEL6();
470        pub fn IEL7();
471        pub fn IEL8();
472        pub fn IEL9();
473        pub fn IEL10();
474        pub fn IEL11();
475        pub fn IEL12();
476        pub fn IEL13();
477        pub fn IEL14();
478        pub fn IEL15();
479        pub fn IEL16();
480        pub fn IEL17();
481        pub fn IEL18();
482        pub fn IEL19();
483        pub fn IEL20();
484        pub fn IEL21();
485        pub fn IEL22();
486        pub fn IEL23();
487        pub fn IEL24();
488        pub fn IEL25();
489        pub fn IEL26();
490        pub fn IEL27();
491        pub fn IEL28();
492        pub fn IEL29();
493        pub fn IEL30();
494        pub fn IEL31();
495    }
496}
497#[cfg(feature = "rt")]
498#[doc(hidden)]
499#[unsafe(link_section = ".vector_table.interrupts")]
500#[unsafe(no_mangle)]
501pub static __INTERRUPTS: [Vector; 32] = [
502    Vector {
503        _handler: interrupt_handlers::IEL0,
504    },
505    Vector {
506        _handler: interrupt_handlers::IEL1,
507    },
508    Vector {
509        _handler: interrupt_handlers::IEL2,
510    },
511    Vector {
512        _handler: interrupt_handlers::IEL3,
513    },
514    Vector {
515        _handler: interrupt_handlers::IEL4,
516    },
517    Vector {
518        _handler: interrupt_handlers::IEL5,
519    },
520    Vector {
521        _handler: interrupt_handlers::IEL6,
522    },
523    Vector {
524        _handler: interrupt_handlers::IEL7,
525    },
526    Vector {
527        _handler: interrupt_handlers::IEL8,
528    },
529    Vector {
530        _handler: interrupt_handlers::IEL9,
531    },
532    Vector {
533        _handler: interrupt_handlers::IEL10,
534    },
535    Vector {
536        _handler: interrupt_handlers::IEL11,
537    },
538    Vector {
539        _handler: interrupt_handlers::IEL12,
540    },
541    Vector {
542        _handler: interrupt_handlers::IEL13,
543    },
544    Vector {
545        _handler: interrupt_handlers::IEL14,
546    },
547    Vector {
548        _handler: interrupt_handlers::IEL15,
549    },
550    Vector {
551        _handler: interrupt_handlers::IEL16,
552    },
553    Vector {
554        _handler: interrupt_handlers::IEL17,
555    },
556    Vector {
557        _handler: interrupt_handlers::IEL18,
558    },
559    Vector {
560        _handler: interrupt_handlers::IEL19,
561    },
562    Vector {
563        _handler: interrupt_handlers::IEL20,
564    },
565    Vector {
566        _handler: interrupt_handlers::IEL21,
567    },
568    Vector {
569        _handler: interrupt_handlers::IEL22,
570    },
571    Vector {
572        _handler: interrupt_handlers::IEL23,
573    },
574    Vector {
575        _handler: interrupt_handlers::IEL24,
576    },
577    Vector {
578        _handler: interrupt_handlers::IEL25,
579    },
580    Vector {
581        _handler: interrupt_handlers::IEL26,
582    },
583    Vector {
584        _handler: interrupt_handlers::IEL27,
585    },
586    Vector {
587        _handler: interrupt_handlers::IEL28,
588    },
589    Vector {
590        _handler: interrupt_handlers::IEL29,
591    },
592    Vector {
593        _handler: interrupt_handlers::IEL30,
594    },
595    Vector {
596        _handler: interrupt_handlers::IEL31,
597    },
598];
599#[doc = "Enumeration of all the interrupts."]
600#[derive(Copy, Clone, Debug, PartialEq, Eq)]
601#[repr(u16)]
602pub enum Interrupt {
603    #[doc = "ICU Interrupt 0"]
604    IEL0 = 0,
605
606    #[doc = "ICU Interrupt 1"]
607    IEL1 = 1,
608
609    #[doc = "ICU Interrupt 2"]
610    IEL2 = 2,
611
612    #[doc = "ICU Interrupt 3"]
613    IEL3 = 3,
614
615    #[doc = "ICU Interrupt 4"]
616    IEL4 = 4,
617
618    #[doc = "ICU Interrupt 5"]
619    IEL5 = 5,
620
621    #[doc = "ICU Interrupt 6"]
622    IEL6 = 6,
623
624    #[doc = "ICU Interrupt 7"]
625    IEL7 = 7,
626
627    #[doc = "ICU Interrupt 8"]
628    IEL8 = 8,
629
630    #[doc = "ICU Interrupt 9"]
631    IEL9 = 9,
632
633    #[doc = "ICU Interrupt 10"]
634    IEL10 = 10,
635
636    #[doc = "ICU Interrupt 11"]
637    IEL11 = 11,
638
639    #[doc = "ICU Interrupt 12"]
640    IEL12 = 12,
641
642    #[doc = "ICU Interrupt 13"]
643    IEL13 = 13,
644
645    #[doc = "ICU Interrupt 14"]
646    IEL14 = 14,
647
648    #[doc = "ICU Interrupt 15"]
649    IEL15 = 15,
650
651    #[doc = "ICU Interrupt 16"]
652    IEL16 = 16,
653
654    #[doc = "ICU Interrupt 17"]
655    IEL17 = 17,
656
657    #[doc = "ICU Interrupt 18"]
658    IEL18 = 18,
659
660    #[doc = "ICU Interrupt 19"]
661    IEL19 = 19,
662
663    #[doc = "ICU Interrupt 20"]
664    IEL20 = 20,
665
666    #[doc = "ICU Interrupt 21"]
667    IEL21 = 21,
668
669    #[doc = "ICU Interrupt 22"]
670    IEL22 = 22,
671
672    #[doc = "ICU Interrupt 23"]
673    IEL23 = 23,
674
675    #[doc = "ICU Interrupt 24"]
676    IEL24 = 24,
677
678    #[doc = "ICU Interrupt 25"]
679    IEL25 = 25,
680
681    #[doc = "ICU Interrupt 26"]
682    IEL26 = 26,
683
684    #[doc = "ICU Interrupt 27"]
685    IEL27 = 27,
686
687    #[doc = "ICU Interrupt 28"]
688    IEL28 = 28,
689
690    #[doc = "ICU Interrupt 29"]
691    IEL29 = 29,
692
693    #[doc = "ICU Interrupt 30"]
694    IEL30 = 30,
695
696    #[doc = "ICU Interrupt 31"]
697    IEL31 = 31,
698}
699unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
700    #[inline(always)]
701    fn number(self) -> u16 {
702        self as u16
703    }
704}
705#[allow(non_snake_case)]
706/// Required for compatibility with RTIC and other frameworks
707pub struct Peripherals {
708    #[cfg(feature = "rmpu")]
709    pub RMPU: self::Rmpu,
710    #[cfg(feature = "sram")]
711    pub SRAM: self::Sram,
712    #[cfg(feature = "bus")]
713    pub BUS: self::Bus,
714    #[cfg(feature = "dtc")]
715    pub DTC: self::Dtc,
716    #[cfg(feature = "icu")]
717    pub ICU: self::Icu,
718    #[cfg(feature = "dbg")]
719    pub DBG: self::Dbg,
720    #[cfg(feature = "sysc")]
721    pub SYSC: self::Sysc,
722    #[cfg(feature = "port0")]
723    pub PORT0: self::Port0,
724    #[cfg(feature = "port1")]
725    pub PORT1: self::Port1,
726    #[cfg(feature = "port2")]
727    pub PORT2: self::Port1,
728    #[cfg(feature = "port3")]
729    pub PORT3: self::Port0,
730    #[cfg(feature = "port4")]
731    pub PORT4: self::Port0,
732    #[cfg(feature = "port5")]
733    pub PORT5: self::Port0,
734    #[cfg(feature = "port9")]
735    pub PORT9: self::Port0,
736    #[cfg(feature = "pfs")]
737    pub PFS: self::Pfs,
738    #[cfg(feature = "elc")]
739    pub ELC: self::Elc,
740    #[cfg(feature = "poeg")]
741    pub POEG: self::Poeg,
742    #[cfg(feature = "rtc")]
743    pub RTC: self::Rtc,
744    #[cfg(feature = "wdt")]
745    pub WDT: self::Wdt,
746    #[cfg(feature = "iwdt")]
747    pub IWDT: self::Iwdt,
748    #[cfg(feature = "cac")]
749    pub CAC: self::Cac,
750    #[cfg(feature = "mstp")]
751    pub MSTP: self::Mstp,
752    #[cfg(feature = "iic0")]
753    pub IIC0: self::Iic0,
754    #[cfg(feature = "iic0wu")]
755    pub IIC0WU: self::Iic0Wu,
756    #[cfg(feature = "doc")]
757    pub DOC: self::Doc,
758    #[cfg(feature = "adc120")]
759    pub ADC120: self::Adc120,
760    #[cfg(feature = "sci0")]
761    pub SCI0: self::Sci0,
762    #[cfg(feature = "sci1")]
763    pub SCI1: self::Sci1,
764    #[cfg(feature = "sci2")]
765    pub SCI2: self::Sci1,
766    #[cfg(feature = "sci9")]
767    pub SCI9: self::Sci1,
768    #[cfg(feature = "spi0")]
769    pub SPI0: self::Spi0,
770    #[cfg(feature = "crc")]
771    pub CRC: self::Crc,
772    #[cfg(feature = "gpt320")]
773    pub GPT320: self::Gpt320,
774    #[cfg(feature = "gpt164")]
775    pub GPT164: self::Gpt164,
776    #[cfg(feature = "gpt165")]
777    pub GPT165: self::Gpt164,
778    #[cfg(feature = "gpt166")]
779    pub GPT166: self::Gpt164,
780    #[cfg(feature = "gpt167")]
781    pub GPT167: self::Gpt164,
782    #[cfg(feature = "gpt168")]
783    pub GPT168: self::Gpt164,
784    #[cfg(feature = "gpt169")]
785    pub GPT169: self::Gpt164,
786    #[cfg(feature = "gpt_ops")]
787    pub GPT_OPS: self::GptOps,
788    #[cfg(feature = "kint")]
789    pub KINT: self::Kint,
790    #[cfg(feature = "ctsu")]
791    pub CTSU: self::Ctsu,
792    #[cfg(feature = "agt0")]
793    pub AGT0: self::Agt0,
794    #[cfg(feature = "agt1")]
795    pub AGT1: self::Agt0,
796    #[cfg(feature = "acmplp")]
797    pub ACMPLP: self::Acmplp,
798    #[cfg(feature = "flcn")]
799    pub FLCN: self::Flcn,
800}
801
802impl Peripherals {
803    /// Returns Peripheral struct multiple times
804    /// Required for compatibility with RTIC and other frameworks
805    #[inline]
806    pub fn take() -> Option<Self> {
807        Some(Self::steal())
808    }
809
810    /// Returns Peripheral struct multiple times
811    /// Required for compatibility with RTIC and other frameworks
812    #[inline]
813    pub fn steal() -> Self {
814        Peripherals {
815            #[cfg(feature = "rmpu")]
816            RMPU: crate::RMPU,
817            #[cfg(feature = "sram")]
818            SRAM: crate::SRAM,
819            #[cfg(feature = "bus")]
820            BUS: crate::BUS,
821            #[cfg(feature = "dtc")]
822            DTC: crate::DTC,
823            #[cfg(feature = "icu")]
824            ICU: crate::ICU,
825            #[cfg(feature = "dbg")]
826            DBG: crate::DBG,
827            #[cfg(feature = "sysc")]
828            SYSC: crate::SYSC,
829            #[cfg(feature = "port0")]
830            PORT0: crate::PORT0,
831            #[cfg(feature = "port1")]
832            PORT1: crate::PORT1,
833            #[cfg(feature = "port2")]
834            PORT2: crate::PORT2,
835            #[cfg(feature = "port3")]
836            PORT3: crate::PORT3,
837            #[cfg(feature = "port4")]
838            PORT4: crate::PORT4,
839            #[cfg(feature = "port5")]
840            PORT5: crate::PORT5,
841            #[cfg(feature = "port9")]
842            PORT9: crate::PORT9,
843            #[cfg(feature = "pfs")]
844            PFS: crate::PFS,
845            #[cfg(feature = "elc")]
846            ELC: crate::ELC,
847            #[cfg(feature = "poeg")]
848            POEG: crate::POEG,
849            #[cfg(feature = "rtc")]
850            RTC: crate::RTC,
851            #[cfg(feature = "wdt")]
852            WDT: crate::WDT,
853            #[cfg(feature = "iwdt")]
854            IWDT: crate::IWDT,
855            #[cfg(feature = "cac")]
856            CAC: crate::CAC,
857            #[cfg(feature = "mstp")]
858            MSTP: crate::MSTP,
859            #[cfg(feature = "iic0")]
860            IIC0: crate::IIC0,
861            #[cfg(feature = "iic0wu")]
862            IIC0WU: crate::IIC0WU,
863            #[cfg(feature = "doc")]
864            DOC: crate::DOC,
865            #[cfg(feature = "adc120")]
866            ADC120: crate::ADC120,
867            #[cfg(feature = "sci0")]
868            SCI0: crate::SCI0,
869            #[cfg(feature = "sci1")]
870            SCI1: crate::SCI1,
871            #[cfg(feature = "sci2")]
872            SCI2: crate::SCI2,
873            #[cfg(feature = "sci9")]
874            SCI9: crate::SCI9,
875            #[cfg(feature = "spi0")]
876            SPI0: crate::SPI0,
877            #[cfg(feature = "crc")]
878            CRC: crate::CRC,
879            #[cfg(feature = "gpt320")]
880            GPT320: crate::GPT320,
881            #[cfg(feature = "gpt164")]
882            GPT164: crate::GPT164,
883            #[cfg(feature = "gpt165")]
884            GPT165: crate::GPT165,
885            #[cfg(feature = "gpt166")]
886            GPT166: crate::GPT166,
887            #[cfg(feature = "gpt167")]
888            GPT167: crate::GPT167,
889            #[cfg(feature = "gpt168")]
890            GPT168: crate::GPT168,
891            #[cfg(feature = "gpt169")]
892            GPT169: crate::GPT169,
893            #[cfg(feature = "gpt_ops")]
894            GPT_OPS: crate::GPT_OPS,
895            #[cfg(feature = "kint")]
896            KINT: crate::KINT,
897            #[cfg(feature = "ctsu")]
898            CTSU: crate::CTSU,
899            #[cfg(feature = "agt0")]
900            AGT0: crate::AGT0,
901            #[cfg(feature = "agt1")]
902            AGT1: crate::AGT1,
903            #[cfg(feature = "acmplp")]
904            ACMPLP: crate::ACMPLP,
905            #[cfg(feature = "flcn")]
906            FLCN: crate::FLCN,
907        }
908    }
909}
ra2e1_pac/lib.rs

ra2e1_pac/
lib.rs
