ra2e1_pac/
acmplp.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.51.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:43 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Low-Power Analog Comparator"]
28unsafe impl ::core::marker::Send for super::Acmplp {}
29unsafe impl ::core::marker::Sync for super::Acmplp {}
30impl super::Acmplp {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "ACMPLP Mode Setting Register"]
38    #[inline(always)]
39    pub const fn compmdr(
40        &self,
41    ) -> &'static crate::common::Reg<self::Compmdr_SPEC, crate::common::RW> {
42        unsafe {
43            crate::common::Reg::<self::Compmdr_SPEC, crate::common::RW>::from_ptr(
44                self._svd2pac_as_ptr().add(0usize),
45            )
46        }
47    }
48
49    #[doc = "ACMPLP Filter Control Register"]
50    #[inline(always)]
51    pub const fn compfir(
52        &self,
53    ) -> &'static crate::common::Reg<self::Compfir_SPEC, crate::common::RW> {
54        unsafe {
55            crate::common::Reg::<self::Compfir_SPEC, crate::common::RW>::from_ptr(
56                self._svd2pac_as_ptr().add(1usize),
57            )
58        }
59    }
60
61    #[doc = "ACMPLP Output Control Register"]
62    #[inline(always)]
63    pub const fn compocr(
64        &self,
65    ) -> &'static crate::common::Reg<self::Compocr_SPEC, crate::common::RW> {
66        unsafe {
67            crate::common::Reg::<self::Compocr_SPEC, crate::common::RW>::from_ptr(
68                self._svd2pac_as_ptr().add(2usize),
69            )
70        }
71    }
72}
73#[doc(hidden)]
74#[derive(Copy, Clone, Eq, PartialEq)]
75pub struct Compmdr_SPEC;
76impl crate::sealed::RegSpec for Compmdr_SPEC {
77    type DataType = u8;
78}
79
80#[doc = "ACMPLP Mode Setting Register"]
81pub type Compmdr = crate::RegValueT<Compmdr_SPEC>;
82
83impl Compmdr {
84    #[doc = "ACMPLP0 Operation Enable"]
85    #[inline(always)]
86    pub fn c0enb(
87        self,
88    ) -> crate::common::RegisterField<
89        0,
90        0x1,
91        1,
92        0,
93        compmdr::C0Enb,
94        compmdr::C0Enb,
95        Compmdr_SPEC,
96        crate::common::RW,
97    > {
98        crate::common::RegisterField::<
99            0,
100            0x1,
101            1,
102            0,
103            compmdr::C0Enb,
104            compmdr::C0Enb,
105            Compmdr_SPEC,
106            crate::common::RW,
107        >::from_register(self, 0)
108    }
109
110    #[doc = "ACMPLP0 Window Function Mode Enable"]
111    #[inline(always)]
112    pub fn c0wde(
113        self,
114    ) -> crate::common::RegisterField<
115        1,
116        0x1,
117        1,
118        0,
119        compmdr::C0Wde,
120        compmdr::C0Wde,
121        Compmdr_SPEC,
122        crate::common::RW,
123    > {
124        crate::common::RegisterField::<
125            1,
126            0x1,
127            1,
128            0,
129            compmdr::C0Wde,
130            compmdr::C0Wde,
131            Compmdr_SPEC,
132            crate::common::RW,
133        >::from_register(self, 0)
134    }
135
136    #[doc = "ACMPLP0 Reference Voltage Selection"]
137    #[inline(always)]
138    pub fn c0vrf(
139        self,
140    ) -> crate::common::RegisterField<
141        2,
142        0x1,
143        1,
144        0,
145        compmdr::C0Vrf,
146        compmdr::C0Vrf,
147        Compmdr_SPEC,
148        crate::common::RW,
149    > {
150        crate::common::RegisterField::<
151            2,
152            0x1,
153            1,
154            0,
155            compmdr::C0Vrf,
156            compmdr::C0Vrf,
157            Compmdr_SPEC,
158            crate::common::RW,
159        >::from_register(self, 0)
160    }
161
162    #[doc = "ACMPLP0 Monitor Flag"]
163    #[inline(always)]
164    pub fn c0mon(
165        self,
166    ) -> crate::common::RegisterFieldBool<3, 1, 0, Compmdr_SPEC, crate::common::R> {
167        crate::common::RegisterFieldBool::<3, 1, 0, Compmdr_SPEC, crate::common::R>::from_register(
168            self, 0,
169        )
170    }
171
172    #[doc = "ACMPLP1 Operation Enable"]
173    #[inline(always)]
174    pub fn c1enb(
175        self,
176    ) -> crate::common::RegisterField<
177        4,
178        0x1,
179        1,
180        0,
181        compmdr::C1Enb,
182        compmdr::C1Enb,
183        Compmdr_SPEC,
184        crate::common::RW,
185    > {
186        crate::common::RegisterField::<
187            4,
188            0x1,
189            1,
190            0,
191            compmdr::C1Enb,
192            compmdr::C1Enb,
193            Compmdr_SPEC,
194            crate::common::RW,
195        >::from_register(self, 0)
196    }
197
198    #[doc = "ACMPLP1 Window Function Mode Enable"]
199    #[inline(always)]
200    pub fn c1wde(
201        self,
202    ) -> crate::common::RegisterField<
203        5,
204        0x1,
205        1,
206        0,
207        compmdr::C1Wde,
208        compmdr::C1Wde,
209        Compmdr_SPEC,
210        crate::common::RW,
211    > {
212        crate::common::RegisterField::<
213            5,
214            0x1,
215            1,
216            0,
217            compmdr::C1Wde,
218            compmdr::C1Wde,
219            Compmdr_SPEC,
220            crate::common::RW,
221        >::from_register(self, 0)
222    }
223
224    #[doc = "ACMPLP1 Reference Voltage Selection"]
225    #[inline(always)]
226    pub fn c1vrf(
227        self,
228    ) -> crate::common::RegisterField<
229        6,
230        0x1,
231        1,
232        0,
233        compmdr::C1Vrf,
234        compmdr::C1Vrf,
235        Compmdr_SPEC,
236        crate::common::RW,
237    > {
238        crate::common::RegisterField::<
239            6,
240            0x1,
241            1,
242            0,
243            compmdr::C1Vrf,
244            compmdr::C1Vrf,
245            Compmdr_SPEC,
246            crate::common::RW,
247        >::from_register(self, 0)
248    }
249
250    #[doc = "ACMPLP1 Monitor Flag"]
251    #[inline(always)]
252    pub fn c1mon(
253        self,
254    ) -> crate::common::RegisterFieldBool<7, 1, 0, Compmdr_SPEC, crate::common::R> {
255        crate::common::RegisterFieldBool::<7, 1, 0, Compmdr_SPEC, crate::common::R>::from_register(
256            self, 0,
257        )
258    }
259}
260impl ::core::default::Default for Compmdr {
261    #[inline(always)]
262    fn default() -> Compmdr {
263        <crate::RegValueT<Compmdr_SPEC> as RegisterValue<_>>::new(0)
264    }
265}
266pub mod compmdr {
267
268    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
269    pub struct C0Enb_SPEC;
270    pub type C0Enb = crate::EnumBitfieldStruct<u8, C0Enb_SPEC>;
271    impl C0Enb {
272        #[doc = "Disable comparator channel ACMPLP0"]
273        pub const _0: Self = Self::new(0);
274
275        #[doc = "Enable comparator channel ACMPLP0"]
276        pub const _1: Self = Self::new(1);
277    }
278    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
279    pub struct C0Wde_SPEC;
280    pub type C0Wde = crate::EnumBitfieldStruct<u8, C0Wde_SPEC>;
281    impl C0Wde {
282        #[doc = "Disable window function for ACMPLP0"]
283        pub const _0: Self = Self::new(0);
284
285        #[doc = "Enable window function for ACMPLP0"]
286        pub const _1: Self = Self::new(1);
287    }
288    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
289    pub struct C0Vrf_SPEC;
290    pub type C0Vrf = crate::EnumBitfieldStruct<u8, C0Vrf_SPEC>;
291    impl C0Vrf {
292        #[doc = "Select CMPREF0 input as ACMPLP0 reference voltage."]
293        pub const _0: Self = Self::new(0);
294
295        #[doc = "Select internal reference voltage (Vref) as ACMPLP0 reference voltage."]
296        pub const _1: Self = Self::new(1);
297    }
298    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
299    pub struct C1Enb_SPEC;
300    pub type C1Enb = crate::EnumBitfieldStruct<u8, C1Enb_SPEC>;
301    impl C1Enb {
302        #[doc = "Disable ACMPLP1 operation"]
303        pub const _0: Self = Self::new(0);
304
305        #[doc = "Enable ACMPLP1 operation"]
306        pub const _1: Self = Self::new(1);
307    }
308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
309    pub struct C1Wde_SPEC;
310    pub type C1Wde = crate::EnumBitfieldStruct<u8, C1Wde_SPEC>;
311    impl C1Wde {
312        #[doc = "Disable ACMPLP1 window function mode"]
313        pub const _0: Self = Self::new(0);
314
315        #[doc = "Enable ACMPLP1 window function mode"]
316        pub const _1: Self = Self::new(1);
317    }
318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
319    pub struct C1Vrf_SPEC;
320    pub type C1Vrf = crate::EnumBitfieldStruct<u8, C1Vrf_SPEC>;
321    impl C1Vrf {
322        #[doc = "Select CMPREF1 input as ACMPLP1 reference voltage."]
323        pub const _0: Self = Self::new(0);
324
325        #[doc = "Select internal reference voltage (Vref) as ACMPLP1 reference voltage."]
326        pub const _1: Self = Self::new(1);
327    }
328}
329#[doc(hidden)]
330#[derive(Copy, Clone, Eq, PartialEq)]
331pub struct Compfir_SPEC;
332impl crate::sealed::RegSpec for Compfir_SPEC {
333    type DataType = u8;
334}
335
336#[doc = "ACMPLP Filter Control Register"]
337pub type Compfir = crate::RegValueT<Compfir_SPEC>;
338
339impl Compfir {
340    #[doc = "ACMPLP0 Filter Select"]
341    #[inline(always)]
342    pub fn c0fck(
343        self,
344    ) -> crate::common::RegisterField<
345        0,
346        0x3,
347        1,
348        0,
349        compfir::C0Fck,
350        compfir::C0Fck,
351        Compfir_SPEC,
352        crate::common::RW,
353    > {
354        crate::common::RegisterField::<
355            0,
356            0x3,
357            1,
358            0,
359            compfir::C0Fck,
360            compfir::C0Fck,
361            Compfir_SPEC,
362            crate::common::RW,
363        >::from_register(self, 0)
364    }
365
366    #[doc = "ACMPLP0 Edge Polarity Switching"]
367    #[inline(always)]
368    pub fn c0epo(
369        self,
370    ) -> crate::common::RegisterField<
371        2,
372        0x1,
373        1,
374        0,
375        compfir::C0Epo,
376        compfir::C0Epo,
377        Compfir_SPEC,
378        crate::common::RW,
379    > {
380        crate::common::RegisterField::<
381            2,
382            0x1,
383            1,
384            0,
385            compfir::C0Epo,
386            compfir::C0Epo,
387            Compfir_SPEC,
388            crate::common::RW,
389        >::from_register(self, 0)
390    }
391
392    #[doc = "ACMPLP0 Edge Detection Selection"]
393    #[inline(always)]
394    pub fn c0edg(
395        self,
396    ) -> crate::common::RegisterField<
397        3,
398        0x1,
399        1,
400        0,
401        compfir::C0Edg,
402        compfir::C0Edg,
403        Compfir_SPEC,
404        crate::common::RW,
405    > {
406        crate::common::RegisterField::<
407            3,
408            0x1,
409            1,
410            0,
411            compfir::C0Edg,
412            compfir::C0Edg,
413            Compfir_SPEC,
414            crate::common::RW,
415        >::from_register(self, 0)
416    }
417
418    #[doc = "ACMPLP1 Filter Select"]
419    #[inline(always)]
420    pub fn c1fck(
421        self,
422    ) -> crate::common::RegisterField<
423        4,
424        0x3,
425        1,
426        0,
427        compfir::C1Fck,
428        compfir::C1Fck,
429        Compfir_SPEC,
430        crate::common::RW,
431    > {
432        crate::common::RegisterField::<
433            4,
434            0x3,
435            1,
436            0,
437            compfir::C1Fck,
438            compfir::C1Fck,
439            Compfir_SPEC,
440            crate::common::RW,
441        >::from_register(self, 0)
442    }
443
444    #[doc = "ACMPLP1 Edge Polarity Switching"]
445    #[inline(always)]
446    pub fn c1epo(
447        self,
448    ) -> crate::common::RegisterField<
449        6,
450        0x1,
451        1,
452        0,
453        compfir::C1Epo,
454        compfir::C1Epo,
455        Compfir_SPEC,
456        crate::common::RW,
457    > {
458        crate::common::RegisterField::<
459            6,
460            0x1,
461            1,
462            0,
463            compfir::C1Epo,
464            compfir::C1Epo,
465            Compfir_SPEC,
466            crate::common::RW,
467        >::from_register(self, 0)
468    }
469
470    #[doc = "ACMPLP1 Edge Detection Selection"]
471    #[inline(always)]
472    pub fn c1edg(
473        self,
474    ) -> crate::common::RegisterField<
475        7,
476        0x1,
477        1,
478        0,
479        compfir::C1Edg,
480        compfir::C1Edg,
481        Compfir_SPEC,
482        crate::common::RW,
483    > {
484        crate::common::RegisterField::<
485            7,
486            0x1,
487            1,
488            0,
489            compfir::C1Edg,
490            compfir::C1Edg,
491            Compfir_SPEC,
492            crate::common::RW,
493        >::from_register(self, 0)
494    }
495}
496impl ::core::default::Default for Compfir {
497    #[inline(always)]
498    fn default() -> Compfir {
499        <crate::RegValueT<Compfir_SPEC> as RegisterValue<_>>::new(0)
500    }
501}
502pub mod compfir {
503
504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
505    pub struct C0Fck_SPEC;
506    pub type C0Fck = crate::EnumBitfieldStruct<u8, C0Fck_SPEC>;
507    impl C0Fck {
508        #[doc = "No Sampling (bypass)"]
509        pub const _00: Self = Self::new(0);
510
511        #[doc = "Sampling at PCLKB"]
512        pub const _01: Self = Self::new(1);
513
514        #[doc = "Sampling at PCLKB/8"]
515        pub const _10: Self = Self::new(2);
516
517        #[doc = "Sampling at PCLKB/32"]
518        pub const _11: Self = Self::new(3);
519    }
520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
521    pub struct C0Epo_SPEC;
522    pub type C0Epo = crate::EnumBitfieldStruct<u8, C0Epo_SPEC>;
523    impl C0Epo {
524        #[doc = "Interrupt and ELC event request on rising edge"]
525        pub const _0: Self = Self::new(0);
526
527        #[doc = "Interrupt and ELC event request on falling edge"]
528        pub const _1: Self = Self::new(1);
529    }
530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
531    pub struct C0Edg_SPEC;
532    pub type C0Edg = crate::EnumBitfieldStruct<u8, C0Edg_SPEC>;
533    impl C0Edg {
534        #[doc = "Interrupt and ELC event request by one-edge detection"]
535        pub const _0: Self = Self::new(0);
536
537        #[doc = "Interrupt and ELC event request by both-edge detection"]
538        pub const _1: Self = Self::new(1);
539    }
540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
541    pub struct C1Fck_SPEC;
542    pub type C1Fck = crate::EnumBitfieldStruct<u8, C1Fck_SPEC>;
543    impl C1Fck {
544        #[doc = "No Sampling (bypass)"]
545        pub const _00: Self = Self::new(0);
546
547        #[doc = "Sampling at PCLKB"]
548        pub const _01: Self = Self::new(1);
549
550        #[doc = "Sampling at PCLKB/8"]
551        pub const _10: Self = Self::new(2);
552
553        #[doc = "Sampling at PCLKB/32"]
554        pub const _11: Self = Self::new(3);
555    }
556    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
557    pub struct C1Epo_SPEC;
558    pub type C1Epo = crate::EnumBitfieldStruct<u8, C1Epo_SPEC>;
559    impl C1Epo {
560        #[doc = "Interrupt and ELC event request on rising edge"]
561        pub const _0: Self = Self::new(0);
562
563        #[doc = "Interrupt and ELC event request on falling edge"]
564        pub const _1: Self = Self::new(1);
565    }
566    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
567    pub struct C1Edg_SPEC;
568    pub type C1Edg = crate::EnumBitfieldStruct<u8, C1Edg_SPEC>;
569    impl C1Edg {
570        #[doc = "Interrupt and ELC event request by one-edge detection"]
571        pub const _0: Self = Self::new(0);
572
573        #[doc = "Interrupt and ELC event request by both-edge detection"]
574        pub const _1: Self = Self::new(1);
575    }
576}
577#[doc(hidden)]
578#[derive(Copy, Clone, Eq, PartialEq)]
579pub struct Compocr_SPEC;
580impl crate::sealed::RegSpec for Compocr_SPEC {
581    type DataType = u8;
582}
583
584#[doc = "ACMPLP Output Control Register"]
585pub type Compocr = crate::RegValueT<Compocr_SPEC>;
586
587impl Compocr {
588    #[doc = "ACMPLP0 VCOUT Pin Output Enable"]
589    #[inline(always)]
590    pub fn c0oe(
591        self,
592    ) -> crate::common::RegisterField<
593        1,
594        0x1,
595        1,
596        0,
597        compocr::C0Oe,
598        compocr::C0Oe,
599        Compocr_SPEC,
600        crate::common::RW,
601    > {
602        crate::common::RegisterField::<
603            1,
604            0x1,
605            1,
606            0,
607            compocr::C0Oe,
608            compocr::C0Oe,
609            Compocr_SPEC,
610            crate::common::RW,
611        >::from_register(self, 0)
612    }
613
614    #[doc = "ACMPLP0 VCOUT Output Polarity Selection"]
615    #[inline(always)]
616    pub fn c0op(
617        self,
618    ) -> crate::common::RegisterField<
619        2,
620        0x1,
621        1,
622        0,
623        compocr::C0Op,
624        compocr::C0Op,
625        Compocr_SPEC,
626        crate::common::RW,
627    > {
628        crate::common::RegisterField::<
629            2,
630            0x1,
631            1,
632            0,
633            compocr::C0Op,
634            compocr::C0Op,
635            Compocr_SPEC,
636            crate::common::RW,
637        >::from_register(self, 0)
638    }
639
640    #[doc = "ACMPLP1 VCOUT Pin Output Enable"]
641    #[inline(always)]
642    pub fn c1oe(
643        self,
644    ) -> crate::common::RegisterField<
645        5,
646        0x1,
647        1,
648        0,
649        compocr::C1Oe,
650        compocr::C1Oe,
651        Compocr_SPEC,
652        crate::common::RW,
653    > {
654        crate::common::RegisterField::<
655            5,
656            0x1,
657            1,
658            0,
659            compocr::C1Oe,
660            compocr::C1Oe,
661            Compocr_SPEC,
662            crate::common::RW,
663        >::from_register(self, 0)
664    }
665
666    #[doc = "ACMPLP1 VCOUT Output Polarity Selection"]
667    #[inline(always)]
668    pub fn c1op(
669        self,
670    ) -> crate::common::RegisterField<
671        6,
672        0x1,
673        1,
674        0,
675        compocr::C1Op,
676        compocr::C1Op,
677        Compocr_SPEC,
678        crate::common::RW,
679    > {
680        crate::common::RegisterField::<
681            6,
682            0x1,
683            1,
684            0,
685            compocr::C1Op,
686            compocr::C1Op,
687            Compocr_SPEC,
688            crate::common::RW,
689        >::from_register(self, 0)
690    }
691
692    #[doc = "ACMPLP0/ACMPLP1 Speed Selection"]
693    #[inline(always)]
694    pub fn spdmd(
695        self,
696    ) -> crate::common::RegisterField<
697        7,
698        0x1,
699        1,
700        0,
701        compocr::Spdmd,
702        compocr::Spdmd,
703        Compocr_SPEC,
704        crate::common::RW,
705    > {
706        crate::common::RegisterField::<
707            7,
708            0x1,
709            1,
710            0,
711            compocr::Spdmd,
712            compocr::Spdmd,
713            Compocr_SPEC,
714            crate::common::RW,
715        >::from_register(self, 0)
716    }
717}
718impl ::core::default::Default for Compocr {
719    #[inline(always)]
720    fn default() -> Compocr {
721        <crate::RegValueT<Compocr_SPEC> as RegisterValue<_>>::new(0)
722    }
723}
724pub mod compocr {
725
726    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
727    pub struct C0Oe_SPEC;
728    pub type C0Oe = crate::EnumBitfieldStruct<u8, C0Oe_SPEC>;
729    impl C0Oe {
730        #[doc = "Disabled"]
731        pub const _0: Self = Self::new(0);
732
733        #[doc = "Enabled"]
734        pub const _1: Self = Self::new(1);
735    }
736    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
737    pub struct C0Op_SPEC;
738    pub type C0Op = crate::EnumBitfieldStruct<u8, C0Op_SPEC>;
739    impl C0Op {
740        #[doc = "Non-inverted"]
741        pub const _0: Self = Self::new(0);
742
743        #[doc = "Inverted"]
744        pub const _1: Self = Self::new(1);
745    }
746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
747    pub struct C1Oe_SPEC;
748    pub type C1Oe = crate::EnumBitfieldStruct<u8, C1Oe_SPEC>;
749    impl C1Oe {
750        #[doc = "Disabled"]
751        pub const _0: Self = Self::new(0);
752
753        #[doc = "Enabled"]
754        pub const _1: Self = Self::new(1);
755    }
756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
757    pub struct C1Op_SPEC;
758    pub type C1Op = crate::EnumBitfieldStruct<u8, C1Op_SPEC>;
759    impl C1Op {
760        #[doc = "Non-inverted"]
761        pub const _0: Self = Self::new(0);
762
763        #[doc = "Inverted"]
764        pub const _1: Self = Self::new(1);
765    }
766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767    pub struct Spdmd_SPEC;
768    pub type Spdmd = crate::EnumBitfieldStruct<u8, Spdmd_SPEC>;
769    impl Spdmd {
770        #[doc = "Low-speed mode"]
771        pub const _0: Self = Self::new(0);
772
773        #[doc = "High-speed mode"]
774        pub const _1: Self = Self::new(1);
775    }
776}
ra2e1_pac/acmplp.rs

ra2e1_pac/
acmplp.rs
