ra2a2_pac/
sci1.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.02, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:00 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Communication Interface 1"]
28unsafe impl ::core::marker::Send for super::Sci1 {}
29unsafe impl ::core::marker::Sync for super::Sci1 {}
30impl super::Sci1 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
38    #[inline(always)]
39    pub const fn smr(&self) -> &'static crate::common::Reg<self::Smr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Smr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
48    #[inline(always)]
49    pub const fn smr_smci(
50        &self,
51    ) -> &'static crate::common::Reg<self::SmrSmci_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::SmrSmci_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0usize),
55            )
56        }
57    }
58
59    #[doc = "Bit Rate Register"]
60    #[inline(always)]
61    pub const fn brr(&self) -> &'static crate::common::Reg<self::Brr_SPEC, crate::common::RW> {
62        unsafe {
63            crate::common::Reg::<self::Brr_SPEC, crate::common::RW>::from_ptr(
64                self._svd2pac_as_ptr().add(1usize),
65            )
66        }
67    }
68
69    #[doc = "Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
70    #[inline(always)]
71    pub const fn scr(&self) -> &'static crate::common::Reg<self::Scr_SPEC, crate::common::RW> {
72        unsafe {
73            crate::common::Reg::<self::Scr_SPEC, crate::common::RW>::from_ptr(
74                self._svd2pac_as_ptr().add(2usize),
75            )
76        }
77    }
78
79    #[doc = "Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
80    #[inline(always)]
81    pub const fn scr_smci(
82        &self,
83    ) -> &'static crate::common::Reg<self::ScrSmci_SPEC, crate::common::RW> {
84        unsafe {
85            crate::common::Reg::<self::ScrSmci_SPEC, crate::common::RW>::from_ptr(
86                self._svd2pac_as_ptr().add(2usize),
87            )
88        }
89    }
90
91    #[doc = "Transmit Data Register"]
92    #[inline(always)]
93    pub const fn tdr(&self) -> &'static crate::common::Reg<self::Tdr_SPEC, crate::common::RW> {
94        unsafe {
95            crate::common::Reg::<self::Tdr_SPEC, crate::common::RW>::from_ptr(
96                self._svd2pac_as_ptr().add(3usize),
97            )
98        }
99    }
100
101    #[doc = "Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0)"]
102    #[inline(always)]
103    pub const fn ssr(&self) -> &'static crate::common::Reg<self::Ssr_SPEC, crate::common::RW> {
104        unsafe {
105            crate::common::Reg::<self::Ssr_SPEC, crate::common::RW>::from_ptr(
106                self._svd2pac_as_ptr().add(4usize),
107            )
108        }
109    }
110
111    #[doc = "Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
112    #[inline(always)]
113    pub const fn ssr_smci(
114        &self,
115    ) -> &'static crate::common::Reg<self::SsrSmci_SPEC, crate::common::RW> {
116        unsafe {
117            crate::common::Reg::<self::SsrSmci_SPEC, crate::common::RW>::from_ptr(
118                self._svd2pac_as_ptr().add(4usize),
119            )
120        }
121    }
122
123    #[doc = "Receive Data Register"]
124    #[inline(always)]
125    pub const fn rdr(&self) -> &'static crate::common::Reg<self::Rdr_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::Rdr_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(5usize),
129            )
130        }
131    }
132
133    #[doc = "Smart Card Mode Register"]
134    #[inline(always)]
135    pub const fn scmr(&self) -> &'static crate::common::Reg<self::Scmr_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::Scmr_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(6usize),
139            )
140        }
141    }
142
143    #[doc = "Serial Extended Mode Register"]
144    #[inline(always)]
145    pub const fn semr(&self) -> &'static crate::common::Reg<self::Semr_SPEC, crate::common::RW> {
146        unsafe {
147            crate::common::Reg::<self::Semr_SPEC, crate::common::RW>::from_ptr(
148                self._svd2pac_as_ptr().add(7usize),
149            )
150        }
151    }
152
153    #[doc = "Noise Filter Setting Register"]
154    #[inline(always)]
155    pub const fn snfr(&self) -> &'static crate::common::Reg<self::Snfr_SPEC, crate::common::RW> {
156        unsafe {
157            crate::common::Reg::<self::Snfr_SPEC, crate::common::RW>::from_ptr(
158                self._svd2pac_as_ptr().add(8usize),
159            )
160        }
161    }
162
163    #[doc = "IIC Mode Register 1"]
164    #[inline(always)]
165    pub const fn simr1(&self) -> &'static crate::common::Reg<self::Simr1_SPEC, crate::common::RW> {
166        unsafe {
167            crate::common::Reg::<self::Simr1_SPEC, crate::common::RW>::from_ptr(
168                self._svd2pac_as_ptr().add(9usize),
169            )
170        }
171    }
172
173    #[doc = "IIC Mode Register 2"]
174    #[inline(always)]
175    pub const fn simr2(&self) -> &'static crate::common::Reg<self::Simr2_SPEC, crate::common::RW> {
176        unsafe {
177            crate::common::Reg::<self::Simr2_SPEC, crate::common::RW>::from_ptr(
178                self._svd2pac_as_ptr().add(10usize),
179            )
180        }
181    }
182
183    #[doc = "IIC Mode Register 3"]
184    #[inline(always)]
185    pub const fn simr3(&self) -> &'static crate::common::Reg<self::Simr3_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::Simr3_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(11usize),
189            )
190        }
191    }
192
193    #[doc = "IIC Status Register"]
194    #[inline(always)]
195    pub const fn sisr(&self) -> &'static crate::common::Reg<self::Sisr_SPEC, crate::common::R> {
196        unsafe {
197            crate::common::Reg::<self::Sisr_SPEC, crate::common::R>::from_ptr(
198                self._svd2pac_as_ptr().add(12usize),
199            )
200        }
201    }
202
203    #[doc = "SPI Mode Register"]
204    #[inline(always)]
205    pub const fn spmr(&self) -> &'static crate::common::Reg<self::Spmr_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Spmr_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(13usize),
209            )
210        }
211    }
212
213    #[doc = "Transmit Data Register"]
214    #[inline(always)]
215    pub const fn tdrhl(&self) -> &'static crate::common::Reg<self::Tdrhl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Tdrhl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(14usize),
219            )
220        }
221    }
222
223    #[doc = "Receive Data Register"]
224    #[inline(always)]
225    pub const fn rdrhl(&self) -> &'static crate::common::Reg<self::Rdrhl_SPEC, crate::common::R> {
226        unsafe {
227            crate::common::Reg::<self::Rdrhl_SPEC, crate::common::R>::from_ptr(
228                self._svd2pac_as_ptr().add(16usize),
229            )
230        }
231    }
232
233    #[doc = "Modulation Duty Register"]
234    #[inline(always)]
235    pub const fn mddr(&self) -> &'static crate::common::Reg<self::Mddr_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Mddr_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "Data Compare Match Control Register"]
244    #[inline(always)]
245    pub const fn dccr(&self) -> &'static crate::common::Reg<self::Dccr_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::Dccr_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252
253    #[doc = "Compare Match Data Register"]
254    #[inline(always)]
255    pub const fn cdr(&self) -> &'static crate::common::Reg<self::Cdr_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Cdr_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(26usize),
259            )
260        }
261    }
262
263    #[doc = "Serial Port Register"]
264    #[inline(always)]
265    pub const fn sptr(&self) -> &'static crate::common::Reg<self::Sptr_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::Sptr_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(28usize),
269            )
270        }
271    }
272}
273#[doc(hidden)]
274#[derive(Copy, Clone, Eq, PartialEq)]
275pub struct Smr_SPEC;
276impl crate::sealed::RegSpec for Smr_SPEC {
277    type DataType = u8;
278}
279
280#[doc = "Serial Mode Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
281pub type Smr = crate::RegValueT<Smr_SPEC>;
282
283impl Smr {
284    #[doc = "Clock Select"]
285    #[inline(always)]
286    pub fn cks(
287        self,
288    ) -> crate::common::RegisterField<0, 0x3, 1, 0, smr::Cks, smr::Cks, Smr_SPEC, crate::common::RW>
289    {
290        crate::common::RegisterField::<0,0x3,1,0,smr::Cks,smr::Cks,Smr_SPEC,crate::common::RW>::from_register(self,0)
291    }
292
293    #[doc = "Multi-Processor Mode"]
294    #[inline(always)]
295    pub fn mp(
296        self,
297    ) -> crate::common::RegisterField<2, 0x1, 1, 0, smr::Mp, smr::Mp, Smr_SPEC, crate::common::RW>
298    {
299        crate::common::RegisterField::<2,0x1,1,0,smr::Mp,smr::Mp,Smr_SPEC,crate::common::RW>::from_register(self,0)
300    }
301
302    #[doc = "Stop Bit Length"]
303    #[inline(always)]
304    pub fn stop(
305        self,
306    ) -> crate::common::RegisterField<3, 0x1, 1, 0, smr::Stop, smr::Stop, Smr_SPEC, crate::common::RW>
307    {
308        crate::common::RegisterField::<
309            3,
310            0x1,
311            1,
312            0,
313            smr::Stop,
314            smr::Stop,
315            Smr_SPEC,
316            crate::common::RW,
317        >::from_register(self, 0)
318    }
319
320    #[doc = "Parity Mode"]
321    #[inline(always)]
322    pub fn pm(
323        self,
324    ) -> crate::common::RegisterField<4, 0x1, 1, 0, smr::Pm, smr::Pm, Smr_SPEC, crate::common::RW>
325    {
326        crate::common::RegisterField::<4,0x1,1,0,smr::Pm,smr::Pm,Smr_SPEC,crate::common::RW>::from_register(self,0)
327    }
328
329    #[doc = "Parity Enable"]
330    #[inline(always)]
331    pub fn pe(
332        self,
333    ) -> crate::common::RegisterField<5, 0x1, 1, 0, smr::Pe, smr::Pe, Smr_SPEC, crate::common::RW>
334    {
335        crate::common::RegisterField::<5,0x1,1,0,smr::Pe,smr::Pe,Smr_SPEC,crate::common::RW>::from_register(self,0)
336    }
337
338    #[doc = "Character Length"]
339    #[inline(always)]
340    pub fn chr(
341        self,
342    ) -> crate::common::RegisterField<6, 0x1, 1, 0, smr::Chr, smr::Chr, Smr_SPEC, crate::common::RW>
343    {
344        crate::common::RegisterField::<6,0x1,1,0,smr::Chr,smr::Chr,Smr_SPEC,crate::common::RW>::from_register(self,0)
345    }
346
347    #[doc = "Communication Mode"]
348    #[inline(always)]
349    pub fn cm(
350        self,
351    ) -> crate::common::RegisterField<7, 0x1, 1, 0, smr::Cm, smr::Cm, Smr_SPEC, crate::common::RW>
352    {
353        crate::common::RegisterField::<7,0x1,1,0,smr::Cm,smr::Cm,Smr_SPEC,crate::common::RW>::from_register(self,0)
354    }
355}
356impl ::core::default::Default for Smr {
357    #[inline(always)]
358    fn default() -> Smr {
359        <crate::RegValueT<Smr_SPEC> as RegisterValue<_>>::new(0)
360    }
361}
362pub mod smr {
363
364    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
365    pub struct Cks_SPEC;
366    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
367    impl Cks {
368        #[doc = "PCLK clock (n = 0)"]
369        pub const _00: Self = Self::new(0);
370
371        #[doc = "PCLK/4 clock (n = 1)"]
372        pub const _01: Self = Self::new(1);
373
374        #[doc = "PCLK/16 clock (n = 2)"]
375        pub const _10: Self = Self::new(2);
376
377        #[doc = "PCLK/64 clock (n = 3)"]
378        pub const _11: Self = Self::new(3);
379    }
380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
381    pub struct Mp_SPEC;
382    pub type Mp = crate::EnumBitfieldStruct<u8, Mp_SPEC>;
383    impl Mp {
384        #[doc = "Disable multi-processor communications function"]
385        pub const _0: Self = Self::new(0);
386
387        #[doc = "Enable multi-processor communications function"]
388        pub const _1: Self = Self::new(1);
389    }
390    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
391    pub struct Stop_SPEC;
392    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
393    impl Stop {
394        #[doc = "1 stop bit"]
395        pub const _0: Self = Self::new(0);
396
397        #[doc = "2 stop bits"]
398        pub const _1: Self = Self::new(1);
399    }
400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
401    pub struct Pm_SPEC;
402    pub type Pm = crate::EnumBitfieldStruct<u8, Pm_SPEC>;
403    impl Pm {
404        #[doc = "Even parity"]
405        pub const _0: Self = Self::new(0);
406
407        #[doc = "Odd parity"]
408        pub const _1: Self = Self::new(1);
409    }
410    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
411    pub struct Pe_SPEC;
412    pub type Pe = crate::EnumBitfieldStruct<u8, Pe_SPEC>;
413    impl Pe {
414        #[doc = "When transmitting: Do not add parity bit When receiving: Do not check parity bit"]
415        pub const _0: Self = Self::new(0);
416
417        #[doc = "When transmitting: Add parity bit When receiving: Check parity bit"]
418        pub const _1: Self = Self::new(1);
419    }
420    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
421    pub struct Chr_SPEC;
422    pub type Chr = crate::EnumBitfieldStruct<u8, Chr_SPEC>;
423    impl Chr {
424        #[doc = "SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 8-bit data length (initial value)"]
425        pub const _0: Self = Self::new(0);
426
427        #[doc = "SCMR.CHR1 = 0: Transmit/receive in 9-bit data length SCMR.CHR1 = 1: Transmit/receive in 7-bit data length"]
428        pub const _1: Self = Self::new(1);
429    }
430    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
431    pub struct Cm_SPEC;
432    pub type Cm = crate::EnumBitfieldStruct<u8, Cm_SPEC>;
433    impl Cm {
434        #[doc = "Asynchronous mode or simple IIC mode"]
435        pub const _0: Self = Self::new(0);
436
437        #[doc = "Clock synchronous mode or simple SPI mode"]
438        pub const _1: Self = Self::new(1);
439    }
440}
441#[doc(hidden)]
442#[derive(Copy, Clone, Eq, PartialEq)]
443pub struct SmrSmci_SPEC;
444impl crate::sealed::RegSpec for SmrSmci_SPEC {
445    type DataType = u8;
446}
447
448#[doc = "Serial Mode Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
449pub type SmrSmci = crate::RegValueT<SmrSmci_SPEC>;
450
451impl SmrSmci {
452    #[doc = "Clock Select"]
453    #[inline(always)]
454    pub fn cks(
455        self,
456    ) -> crate::common::RegisterField<
457        0,
458        0x3,
459        1,
460        0,
461        smr_smci::Cks,
462        smr_smci::Cks,
463        SmrSmci_SPEC,
464        crate::common::RW,
465    > {
466        crate::common::RegisterField::<
467            0,
468            0x3,
469            1,
470            0,
471            smr_smci::Cks,
472            smr_smci::Cks,
473            SmrSmci_SPEC,
474            crate::common::RW,
475        >::from_register(self, 0)
476    }
477
478    #[doc = "Base Clock Pulse"]
479    #[inline(always)]
480    pub fn bcp(
481        self,
482    ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, SmrSmci_SPEC, crate::common::RW> {
483        crate::common::RegisterField::<2,0x3,1,0,u8,u8,SmrSmci_SPEC,crate::common::RW>::from_register(self,0)
484    }
485
486    #[doc = "Parity Mode"]
487    #[inline(always)]
488    pub fn pm(
489        self,
490    ) -> crate::common::RegisterField<
491        4,
492        0x1,
493        1,
494        0,
495        smr_smci::Pm,
496        smr_smci::Pm,
497        SmrSmci_SPEC,
498        crate::common::RW,
499    > {
500        crate::common::RegisterField::<
501            4,
502            0x1,
503            1,
504            0,
505            smr_smci::Pm,
506            smr_smci::Pm,
507            SmrSmci_SPEC,
508            crate::common::RW,
509        >::from_register(self, 0)
510    }
511
512    #[doc = "Parity Enable"]
513    #[inline(always)]
514    pub fn pe(self) -> crate::common::RegisterFieldBool<5, 1, 0, SmrSmci_SPEC, crate::common::RW> {
515        crate::common::RegisterFieldBool::<5, 1, 0, SmrSmci_SPEC, crate::common::RW>::from_register(
516            self, 0,
517        )
518    }
519
520    #[doc = "Block Transfer Mode"]
521    #[inline(always)]
522    pub fn blk(
523        self,
524    ) -> crate::common::RegisterField<
525        6,
526        0x1,
527        1,
528        0,
529        smr_smci::Blk,
530        smr_smci::Blk,
531        SmrSmci_SPEC,
532        crate::common::RW,
533    > {
534        crate::common::RegisterField::<
535            6,
536            0x1,
537            1,
538            0,
539            smr_smci::Blk,
540            smr_smci::Blk,
541            SmrSmci_SPEC,
542            crate::common::RW,
543        >::from_register(self, 0)
544    }
545
546    #[doc = "GSM Mode"]
547    #[inline(always)]
548    pub fn gm(
549        self,
550    ) -> crate::common::RegisterField<
551        7,
552        0x1,
553        1,
554        0,
555        smr_smci::Gm,
556        smr_smci::Gm,
557        SmrSmci_SPEC,
558        crate::common::RW,
559    > {
560        crate::common::RegisterField::<
561            7,
562            0x1,
563            1,
564            0,
565            smr_smci::Gm,
566            smr_smci::Gm,
567            SmrSmci_SPEC,
568            crate::common::RW,
569        >::from_register(self, 0)
570    }
571}
572impl ::core::default::Default for SmrSmci {
573    #[inline(always)]
574    fn default() -> SmrSmci {
575        <crate::RegValueT<SmrSmci_SPEC> as RegisterValue<_>>::new(0)
576    }
577}
578pub mod smr_smci {
579
580    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
581    pub struct Cks_SPEC;
582    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
583    impl Cks {
584        #[doc = "PCLK clock (n = 0)"]
585        pub const _00: Self = Self::new(0);
586
587        #[doc = "PCLK/4 clock (n = 1)"]
588        pub const _01: Self = Self::new(1);
589
590        #[doc = "PCLK/16 clock (n = 2)"]
591        pub const _10: Self = Self::new(2);
592
593        #[doc = "PCLK/64 clock (n = 3)"]
594        pub const _11: Self = Self::new(3);
595    }
596    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
597    pub struct Pm_SPEC;
598    pub type Pm = crate::EnumBitfieldStruct<u8, Pm_SPEC>;
599    impl Pm {
600        #[doc = "Even parity"]
601        pub const _0: Self = Self::new(0);
602
603        #[doc = "Odd parity"]
604        pub const _1: Self = Self::new(1);
605    }
606    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
607    pub struct Blk_SPEC;
608    pub type Blk = crate::EnumBitfieldStruct<u8, Blk_SPEC>;
609    impl Blk {
610        #[doc = "Normal mode operation"]
611        pub const _0: Self = Self::new(0);
612
613        #[doc = "Block transfer mode operation"]
614        pub const _1: Self = Self::new(1);
615    }
616    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
617    pub struct Gm_SPEC;
618    pub type Gm = crate::EnumBitfieldStruct<u8, Gm_SPEC>;
619    impl Gm {
620        #[doc = "Normal mode operation"]
621        pub const _0: Self = Self::new(0);
622
623        #[doc = "GSM mode operation"]
624        pub const _1: Self = Self::new(1);
625    }
626}
627#[doc(hidden)]
628#[derive(Copy, Clone, Eq, PartialEq)]
629pub struct Brr_SPEC;
630impl crate::sealed::RegSpec for Brr_SPEC {
631    type DataType = u8;
632}
633
634#[doc = "Bit Rate Register"]
635pub type Brr = crate::RegValueT<Brr_SPEC>;
636
637impl NoBitfieldReg<Brr_SPEC> for Brr {}
638impl ::core::default::Default for Brr {
639    #[inline(always)]
640    fn default() -> Brr {
641        <crate::RegValueT<Brr_SPEC> as RegisterValue<_>>::new(255)
642    }
643}
644
645#[doc(hidden)]
646#[derive(Copy, Clone, Eq, PartialEq)]
647pub struct Scr_SPEC;
648impl crate::sealed::RegSpec for Scr_SPEC {
649    type DataType = u8;
650}
651
652#[doc = "Serial Control Register for Non-Smart Card Interface Mode (SCMR.SMIF = 0)"]
653pub type Scr = crate::RegValueT<Scr_SPEC>;
654
655impl Scr {
656    #[doc = "Clock Enable"]
657    #[inline(always)]
658    pub fn cke(
659        self,
660    ) -> crate::common::RegisterField<0, 0x3, 1, 0, scr::Cke, scr::Cke, Scr_SPEC, crate::common::RW>
661    {
662        crate::common::RegisterField::<0,0x3,1,0,scr::Cke,scr::Cke,Scr_SPEC,crate::common::RW>::from_register(self,0)
663    }
664
665    #[doc = "Transmit End Interrupt Enable"]
666    #[inline(always)]
667    pub fn teie(
668        self,
669    ) -> crate::common::RegisterField<2, 0x1, 1, 0, scr::Teie, scr::Teie, Scr_SPEC, crate::common::RW>
670    {
671        crate::common::RegisterField::<
672            2,
673            0x1,
674            1,
675            0,
676            scr::Teie,
677            scr::Teie,
678            Scr_SPEC,
679            crate::common::RW,
680        >::from_register(self, 0)
681    }
682
683    #[doc = "Multi-Processor Interrupt Enable"]
684    #[inline(always)]
685    pub fn mpie(
686        self,
687    ) -> crate::common::RegisterField<3, 0x1, 1, 0, scr::Mpie, scr::Mpie, Scr_SPEC, crate::common::RW>
688    {
689        crate::common::RegisterField::<
690            3,
691            0x1,
692            1,
693            0,
694            scr::Mpie,
695            scr::Mpie,
696            Scr_SPEC,
697            crate::common::RW,
698        >::from_register(self, 0)
699    }
700
701    #[doc = "Receive Enable"]
702    #[inline(always)]
703    pub fn re(
704        self,
705    ) -> crate::common::RegisterField<4, 0x1, 1, 0, scr::Re, scr::Re, Scr_SPEC, crate::common::RW>
706    {
707        crate::common::RegisterField::<4,0x1,1,0,scr::Re,scr::Re,Scr_SPEC,crate::common::RW>::from_register(self,0)
708    }
709
710    #[doc = "Transmit Enable"]
711    #[inline(always)]
712    pub fn te(
713        self,
714    ) -> crate::common::RegisterField<5, 0x1, 1, 0, scr::Te, scr::Te, Scr_SPEC, crate::common::RW>
715    {
716        crate::common::RegisterField::<5,0x1,1,0,scr::Te,scr::Te,Scr_SPEC,crate::common::RW>::from_register(self,0)
717    }
718
719    #[doc = "Receive Interrupt Enable"]
720    #[inline(always)]
721    pub fn rie(
722        self,
723    ) -> crate::common::RegisterField<6, 0x1, 1, 0, scr::Rie, scr::Rie, Scr_SPEC, crate::common::RW>
724    {
725        crate::common::RegisterField::<6,0x1,1,0,scr::Rie,scr::Rie,Scr_SPEC,crate::common::RW>::from_register(self,0)
726    }
727
728    #[doc = "Transmit Interrupt Enable"]
729    #[inline(always)]
730    pub fn tie(
731        self,
732    ) -> crate::common::RegisterField<7, 0x1, 1, 0, scr::Tie, scr::Tie, Scr_SPEC, crate::common::RW>
733    {
734        crate::common::RegisterField::<7,0x1,1,0,scr::Tie,scr::Tie,Scr_SPEC,crate::common::RW>::from_register(self,0)
735    }
736}
737impl ::core::default::Default for Scr {
738    #[inline(always)]
739    fn default() -> Scr {
740        <crate::RegValueT<Scr_SPEC> as RegisterValue<_>>::new(0)
741    }
742}
743pub mod scr {
744
745    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
746    pub struct Cke_SPEC;
747    pub type Cke = crate::EnumBitfieldStruct<u8, Cke_SPEC>;
748    impl Cke {
749        #[doc = "In asynchronous mode, the SCKn pin is available for use as an I/O port based on the I/O port settings. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
750        pub const _00: Self = Self::new(0);
751
752        #[doc = "In asynchronous mode, a clock with the same frequency as the bit rate is output from the SCKn pin. In clock synchronous mode, the SCKn pin functions as the clock output pin."]
753        pub const _01: Self = Self::new(1);
754    }
755    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
756    pub struct Teie_SPEC;
757    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
758    impl Teie {
759        #[doc = "Disable SCIn_TEI interrupt requests"]
760        pub const _0: Self = Self::new(0);
761
762        #[doc = "Enable SCIn_TEI interrupt requests"]
763        pub const _1: Self = Self::new(1);
764    }
765    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
766    pub struct Mpie_SPEC;
767    pub type Mpie = crate::EnumBitfieldStruct<u8, Mpie_SPEC>;
768    impl Mpie {
769        #[doc = "Normal reception"]
770        pub const _0: Self = Self::new(0);
771
772        #[doc = "When data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF, ORER, and FER in SSR to 1 is disabled. When data with the multi-processor bit set to 1 is received, the MPIE bit is automatically set to 0, and normal reception is resumed."]
773        pub const _1: Self = Self::new(1);
774    }
775    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
776    pub struct Re_SPEC;
777    pub type Re = crate::EnumBitfieldStruct<u8, Re_SPEC>;
778    impl Re {
779        #[doc = "Disable serial reception"]
780        pub const _0: Self = Self::new(0);
781
782        #[doc = "Enable serial reception"]
783        pub const _1: Self = Self::new(1);
784    }
785    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
786    pub struct Te_SPEC;
787    pub type Te = crate::EnumBitfieldStruct<u8, Te_SPEC>;
788    impl Te {
789        #[doc = "Disable serial transmission"]
790        pub const _0: Self = Self::new(0);
791
792        #[doc = "Enable serial transmission"]
793        pub const _1: Self = Self::new(1);
794    }
795    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
796    pub struct Rie_SPEC;
797    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
798    impl Rie {
799        #[doc = "Disable SCIn_RXI and SCIn_ERI interrupt requests"]
800        pub const _0: Self = Self::new(0);
801
802        #[doc = "Enable SCIn_RXI and SCIn_ERI interrupt requests"]
803        pub const _1: Self = Self::new(1);
804    }
805    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
806    pub struct Tie_SPEC;
807    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
808    impl Tie {
809        #[doc = "Disable SCIn_TXI interrupt requests"]
810        pub const _0: Self = Self::new(0);
811
812        #[doc = "Enable SCIn_TXI interrupt requests"]
813        pub const _1: Self = Self::new(1);
814    }
815}
816#[doc(hidden)]
817#[derive(Copy, Clone, Eq, PartialEq)]
818pub struct ScrSmci_SPEC;
819impl crate::sealed::RegSpec for ScrSmci_SPEC {
820    type DataType = u8;
821}
822
823#[doc = "Serial Control Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
824pub type ScrSmci = crate::RegValueT<ScrSmci_SPEC>;
825
826impl ScrSmci {
827    #[doc = "Clock Enable"]
828    #[inline(always)]
829    pub fn cke(
830        self,
831    ) -> crate::common::RegisterField<
832        0,
833        0x3,
834        1,
835        0,
836        scr_smci::Cke,
837        scr_smci::Cke,
838        ScrSmci_SPEC,
839        crate::common::RW,
840    > {
841        crate::common::RegisterField::<
842            0,
843            0x3,
844            1,
845            0,
846            scr_smci::Cke,
847            scr_smci::Cke,
848            ScrSmci_SPEC,
849            crate::common::RW,
850        >::from_register(self, 0)
851    }
852
853    #[doc = "Transmit End Interrupt Enable"]
854    #[inline(always)]
855    pub fn teie(
856        self,
857    ) -> crate::common::RegisterFieldBool<2, 1, 0, ScrSmci_SPEC, crate::common::RW> {
858        crate::common::RegisterFieldBool::<2, 1, 0, ScrSmci_SPEC, crate::common::RW>::from_register(
859            self, 0,
860        )
861    }
862
863    #[doc = "Multi-Processor Interrupt Enable"]
864    #[inline(always)]
865    pub fn mpie(
866        self,
867    ) -> crate::common::RegisterFieldBool<3, 1, 0, ScrSmci_SPEC, crate::common::RW> {
868        crate::common::RegisterFieldBool::<3, 1, 0, ScrSmci_SPEC, crate::common::RW>::from_register(
869            self, 0,
870        )
871    }
872
873    #[doc = "Receive Enable"]
874    #[inline(always)]
875    pub fn re(
876        self,
877    ) -> crate::common::RegisterField<
878        4,
879        0x1,
880        1,
881        0,
882        scr_smci::Re,
883        scr_smci::Re,
884        ScrSmci_SPEC,
885        crate::common::RW,
886    > {
887        crate::common::RegisterField::<
888            4,
889            0x1,
890            1,
891            0,
892            scr_smci::Re,
893            scr_smci::Re,
894            ScrSmci_SPEC,
895            crate::common::RW,
896        >::from_register(self, 0)
897    }
898
899    #[doc = "Transmit Enable"]
900    #[inline(always)]
901    pub fn te(
902        self,
903    ) -> crate::common::RegisterField<
904        5,
905        0x1,
906        1,
907        0,
908        scr_smci::Te,
909        scr_smci::Te,
910        ScrSmci_SPEC,
911        crate::common::RW,
912    > {
913        crate::common::RegisterField::<
914            5,
915            0x1,
916            1,
917            0,
918            scr_smci::Te,
919            scr_smci::Te,
920            ScrSmci_SPEC,
921            crate::common::RW,
922        >::from_register(self, 0)
923    }
924
925    #[doc = "Receive Interrupt Enable"]
926    #[inline(always)]
927    pub fn rie(
928        self,
929    ) -> crate::common::RegisterField<
930        6,
931        0x1,
932        1,
933        0,
934        scr_smci::Rie,
935        scr_smci::Rie,
936        ScrSmci_SPEC,
937        crate::common::RW,
938    > {
939        crate::common::RegisterField::<
940            6,
941            0x1,
942            1,
943            0,
944            scr_smci::Rie,
945            scr_smci::Rie,
946            ScrSmci_SPEC,
947            crate::common::RW,
948        >::from_register(self, 0)
949    }
950
951    #[doc = "Transmit Interrupt Enable"]
952    #[inline(always)]
953    pub fn tie(
954        self,
955    ) -> crate::common::RegisterField<
956        7,
957        0x1,
958        1,
959        0,
960        scr_smci::Tie,
961        scr_smci::Tie,
962        ScrSmci_SPEC,
963        crate::common::RW,
964    > {
965        crate::common::RegisterField::<
966            7,
967            0x1,
968            1,
969            0,
970            scr_smci::Tie,
971            scr_smci::Tie,
972            ScrSmci_SPEC,
973            crate::common::RW,
974        >::from_register(self, 0)
975    }
976}
977impl ::core::default::Default for ScrSmci {
978    #[inline(always)]
979    fn default() -> ScrSmci {
980        <crate::RegValueT<ScrSmci_SPEC> as RegisterValue<_>>::new(0)
981    }
982}
983pub mod scr_smci {
984
985    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
986    pub struct Cke_SPEC;
987    pub type Cke = crate::EnumBitfieldStruct<u8, Cke_SPEC>;
988    impl Cke {
989        #[doc = "When SMR_SMCI.GM = 0: Disable output The SCKn pin is available for use as an I/O port if set up in the I/O port settings When SMR_SMCI.GM = 1: Fix output low"]
990        pub const _00: Self = Self::new(0);
991
992        #[doc = "When SMR_SMCI.GM = 0: Output clock When SMR_SMCI.GM = 1: Output clock"]
993        pub const _01: Self = Self::new(1);
994
995        #[doc = "When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Fix output high"]
996        pub const _10: Self = Self::new(2);
997
998        #[doc = "When SMR_SMCI.GM = 0: Setting prohibited When SMR_SMCI.GM = 1: Output clock"]
999        pub const _11: Self = Self::new(3);
1000    }
1001    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1002    pub struct Re_SPEC;
1003    pub type Re = crate::EnumBitfieldStruct<u8, Re_SPEC>;
1004    impl Re {
1005        #[doc = "Disable serial reception"]
1006        pub const _0: Self = Self::new(0);
1007
1008        #[doc = "Enable serial reception"]
1009        pub const _1: Self = Self::new(1);
1010    }
1011    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1012    pub struct Te_SPEC;
1013    pub type Te = crate::EnumBitfieldStruct<u8, Te_SPEC>;
1014    impl Te {
1015        #[doc = "Disable serial transmission"]
1016        pub const _0: Self = Self::new(0);
1017
1018        #[doc = "Enable serial transmission"]
1019        pub const _1: Self = Self::new(1);
1020    }
1021    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1022    pub struct Rie_SPEC;
1023    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
1024    impl Rie {
1025        #[doc = "Disable SCIn_RXI and SCIn_ERI interrupt requests"]
1026        pub const _0: Self = Self::new(0);
1027
1028        #[doc = "Enable SCIn_RXI and SCIn_ERI interrupt requests"]
1029        pub const _1: Self = Self::new(1);
1030    }
1031    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1032    pub struct Tie_SPEC;
1033    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
1034    impl Tie {
1035        #[doc = "Disable SCIn_TXI interrupt requests"]
1036        pub const _0: Self = Self::new(0);
1037
1038        #[doc = "Enable SCIn_TXI interrupt requests"]
1039        pub const _1: Self = Self::new(1);
1040    }
1041}
1042#[doc(hidden)]
1043#[derive(Copy, Clone, Eq, PartialEq)]
1044pub struct Tdr_SPEC;
1045impl crate::sealed::RegSpec for Tdr_SPEC {
1046    type DataType = u8;
1047}
1048
1049#[doc = "Transmit Data Register"]
1050pub type Tdr = crate::RegValueT<Tdr_SPEC>;
1051
1052impl NoBitfieldReg<Tdr_SPEC> for Tdr {}
1053impl ::core::default::Default for Tdr {
1054    #[inline(always)]
1055    fn default() -> Tdr {
1056        <crate::RegValueT<Tdr_SPEC> as RegisterValue<_>>::new(255)
1057    }
1058}
1059
1060#[doc(hidden)]
1061#[derive(Copy, Clone, Eq, PartialEq)]
1062pub struct Ssr_SPEC;
1063impl crate::sealed::RegSpec for Ssr_SPEC {
1064    type DataType = u8;
1065}
1066
1067#[doc = "Serial Status Register for Non-Smart Card Interface and Non-FIFO Mode (SCMR.SMIF = 0, FCR.FM = 0)"]
1068pub type Ssr = crate::RegValueT<Ssr_SPEC>;
1069
1070impl Ssr {
1071    #[doc = "Multi-Processor Bit Transfer"]
1072    #[inline(always)]
1073    pub fn mpbt(
1074        self,
1075    ) -> crate::common::RegisterField<0, 0x1, 1, 0, ssr::Mpbt, ssr::Mpbt, Ssr_SPEC, crate::common::RW>
1076    {
1077        crate::common::RegisterField::<
1078            0,
1079            0x1,
1080            1,
1081            0,
1082            ssr::Mpbt,
1083            ssr::Mpbt,
1084            Ssr_SPEC,
1085            crate::common::RW,
1086        >::from_register(self, 0)
1087    }
1088
1089    #[doc = "Multi-Processor"]
1090    #[inline(always)]
1091    pub fn mpb(
1092        self,
1093    ) -> crate::common::RegisterField<1, 0x1, 1, 0, ssr::Mpb, ssr::Mpb, Ssr_SPEC, crate::common::R>
1094    {
1095        crate::common::RegisterField::<1,0x1,1,0,ssr::Mpb,ssr::Mpb,Ssr_SPEC,crate::common::R>::from_register(self,0)
1096    }
1097
1098    #[doc = "Transmit End Flag"]
1099    #[inline(always)]
1100    pub fn tend(
1101        self,
1102    ) -> crate::common::RegisterField<2, 0x1, 1, 0, ssr::Tend, ssr::Tend, Ssr_SPEC, crate::common::R>
1103    {
1104        crate::common::RegisterField::<2,0x1,1,0,ssr::Tend,ssr::Tend,Ssr_SPEC,crate::common::R>::from_register(self,0)
1105    }
1106
1107    #[doc = "Parity Error Flag"]
1108    #[inline(always)]
1109    pub fn per(
1110        self,
1111    ) -> crate::common::RegisterField<3, 0x1, 1, 0, ssr::Per, ssr::Per, Ssr_SPEC, crate::common::RW>
1112    {
1113        crate::common::RegisterField::<3,0x1,1,0,ssr::Per,ssr::Per,Ssr_SPEC,crate::common::RW>::from_register(self,0)
1114    }
1115
1116    #[doc = "Framing Error Flag"]
1117    #[inline(always)]
1118    pub fn fer(
1119        self,
1120    ) -> crate::common::RegisterField<4, 0x1, 1, 0, ssr::Fer, ssr::Fer, Ssr_SPEC, crate::common::RW>
1121    {
1122        crate::common::RegisterField::<4,0x1,1,0,ssr::Fer,ssr::Fer,Ssr_SPEC,crate::common::RW>::from_register(self,0)
1123    }
1124
1125    #[doc = "Overrun Error Flag"]
1126    #[inline(always)]
1127    pub fn orer(
1128        self,
1129    ) -> crate::common::RegisterField<5, 0x1, 1, 0, ssr::Orer, ssr::Orer, Ssr_SPEC, crate::common::RW>
1130    {
1131        crate::common::RegisterField::<
1132            5,
1133            0x1,
1134            1,
1135            0,
1136            ssr::Orer,
1137            ssr::Orer,
1138            Ssr_SPEC,
1139            crate::common::RW,
1140        >::from_register(self, 0)
1141    }
1142
1143    #[doc = "Receive Data Full Flag"]
1144    #[inline(always)]
1145    pub fn rdrf(
1146        self,
1147    ) -> crate::common::RegisterField<6, 0x1, 1, 0, ssr::Rdrf, ssr::Rdrf, Ssr_SPEC, crate::common::RW>
1148    {
1149        crate::common::RegisterField::<
1150            6,
1151            0x1,
1152            1,
1153            0,
1154            ssr::Rdrf,
1155            ssr::Rdrf,
1156            Ssr_SPEC,
1157            crate::common::RW,
1158        >::from_register(self, 0)
1159    }
1160
1161    #[doc = "Transmit Data Empty Flag"]
1162    #[inline(always)]
1163    pub fn tdre(
1164        self,
1165    ) -> crate::common::RegisterField<7, 0x1, 1, 0, ssr::Tdre, ssr::Tdre, Ssr_SPEC, crate::common::RW>
1166    {
1167        crate::common::RegisterField::<
1168            7,
1169            0x1,
1170            1,
1171            0,
1172            ssr::Tdre,
1173            ssr::Tdre,
1174            Ssr_SPEC,
1175            crate::common::RW,
1176        >::from_register(self, 0)
1177    }
1178}
1179impl ::core::default::Default for Ssr {
1180    #[inline(always)]
1181    fn default() -> Ssr {
1182        <crate::RegValueT<Ssr_SPEC> as RegisterValue<_>>::new(132)
1183    }
1184}
1185pub mod ssr {
1186
1187    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1188    pub struct Mpbt_SPEC;
1189    pub type Mpbt = crate::EnumBitfieldStruct<u8, Mpbt_SPEC>;
1190    impl Mpbt {
1191        #[doc = "Data transmission cycle"]
1192        pub const _0: Self = Self::new(0);
1193
1194        #[doc = "ID transmission cycle"]
1195        pub const _1: Self = Self::new(1);
1196    }
1197    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1198    pub struct Mpb_SPEC;
1199    pub type Mpb = crate::EnumBitfieldStruct<u8, Mpb_SPEC>;
1200    impl Mpb {
1201        #[doc = "Data transmission cycle"]
1202        pub const _0: Self = Self::new(0);
1203
1204        #[doc = "ID transmission cycle"]
1205        pub const _1: Self = Self::new(1);
1206    }
1207    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1208    pub struct Tend_SPEC;
1209    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
1210    impl Tend {
1211        #[doc = "A character is being transmitted"]
1212        pub const _0: Self = Self::new(0);
1213
1214        #[doc = "Character transfer is complete"]
1215        pub const _1: Self = Self::new(1);
1216    }
1217    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1218    pub struct Per_SPEC;
1219    pub type Per = crate::EnumBitfieldStruct<u8, Per_SPEC>;
1220    impl Per {
1221        #[doc = "No parity error occurred"]
1222        pub const _0: Self = Self::new(0);
1223
1224        #[doc = "Parity error occurred"]
1225        pub const _1: Self = Self::new(1);
1226    }
1227    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1228    pub struct Fer_SPEC;
1229    pub type Fer = crate::EnumBitfieldStruct<u8, Fer_SPEC>;
1230    impl Fer {
1231        #[doc = "No framing error occurred"]
1232        pub const _0: Self = Self::new(0);
1233
1234        #[doc = "Framing error occurred"]
1235        pub const _1: Self = Self::new(1);
1236    }
1237    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1238    pub struct Orer_SPEC;
1239    pub type Orer = crate::EnumBitfieldStruct<u8, Orer_SPEC>;
1240    impl Orer {
1241        #[doc = "No overrun error occurred"]
1242        pub const _0: Self = Self::new(0);
1243
1244        #[doc = "Overrun error occurred"]
1245        pub const _1: Self = Self::new(1);
1246    }
1247    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1248    pub struct Rdrf_SPEC;
1249    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
1250    impl Rdrf {
1251        #[doc = "No received data in RDR register"]
1252        pub const _0: Self = Self::new(0);
1253
1254        #[doc = "Received data in RDR register"]
1255        pub const _1: Self = Self::new(1);
1256    }
1257    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1258    pub struct Tdre_SPEC;
1259    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
1260    impl Tdre {
1261        #[doc = "Transmit data in TDR register"]
1262        pub const _0: Self = Self::new(0);
1263
1264        #[doc = "No transmit data in TDR register"]
1265        pub const _1: Self = Self::new(1);
1266    }
1267}
1268#[doc(hidden)]
1269#[derive(Copy, Clone, Eq, PartialEq)]
1270pub struct SsrSmci_SPEC;
1271impl crate::sealed::RegSpec for SsrSmci_SPEC {
1272    type DataType = u8;
1273}
1274
1275#[doc = "Serial Status Register for Smart Card Interface Mode (SCMR.SMIF = 1)"]
1276pub type SsrSmci = crate::RegValueT<SsrSmci_SPEC>;
1277
1278impl SsrSmci {
1279    #[doc = "Multi-Processor Bit Transfer"]
1280    #[inline(always)]
1281    pub fn mpbt(
1282        self,
1283    ) -> crate::common::RegisterFieldBool<0, 1, 0, SsrSmci_SPEC, crate::common::RW> {
1284        crate::common::RegisterFieldBool::<0, 1, 0, SsrSmci_SPEC, crate::common::RW>::from_register(
1285            self, 0,
1286        )
1287    }
1288
1289    #[doc = "Multi-Processor"]
1290    #[inline(always)]
1291    pub fn mpb(self) -> crate::common::RegisterFieldBool<1, 1, 0, SsrSmci_SPEC, crate::common::R> {
1292        crate::common::RegisterFieldBool::<1, 1, 0, SsrSmci_SPEC, crate::common::R>::from_register(
1293            self, 0,
1294        )
1295    }
1296
1297    #[doc = "Transmit End Flag"]
1298    #[inline(always)]
1299    pub fn tend(
1300        self,
1301    ) -> crate::common::RegisterField<
1302        2,
1303        0x1,
1304        1,
1305        0,
1306        ssr_smci::Tend,
1307        ssr_smci::Tend,
1308        SsrSmci_SPEC,
1309        crate::common::R,
1310    > {
1311        crate::common::RegisterField::<
1312            2,
1313            0x1,
1314            1,
1315            0,
1316            ssr_smci::Tend,
1317            ssr_smci::Tend,
1318            SsrSmci_SPEC,
1319            crate::common::R,
1320        >::from_register(self, 0)
1321    }
1322
1323    #[doc = "Parity Error Flag"]
1324    #[inline(always)]
1325    pub fn per(
1326        self,
1327    ) -> crate::common::RegisterField<
1328        3,
1329        0x1,
1330        1,
1331        0,
1332        ssr_smci::Per,
1333        ssr_smci::Per,
1334        SsrSmci_SPEC,
1335        crate::common::RW,
1336    > {
1337        crate::common::RegisterField::<
1338            3,
1339            0x1,
1340            1,
1341            0,
1342            ssr_smci::Per,
1343            ssr_smci::Per,
1344            SsrSmci_SPEC,
1345            crate::common::RW,
1346        >::from_register(self, 0)
1347    }
1348
1349    #[doc = "Error Signal Status Flag"]
1350    #[inline(always)]
1351    pub fn ers(
1352        self,
1353    ) -> crate::common::RegisterField<
1354        4,
1355        0x1,
1356        1,
1357        0,
1358        ssr_smci::Ers,
1359        ssr_smci::Ers,
1360        SsrSmci_SPEC,
1361        crate::common::RW,
1362    > {
1363        crate::common::RegisterField::<
1364            4,
1365            0x1,
1366            1,
1367            0,
1368            ssr_smci::Ers,
1369            ssr_smci::Ers,
1370            SsrSmci_SPEC,
1371            crate::common::RW,
1372        >::from_register(self, 0)
1373    }
1374
1375    #[doc = "Overrun Error Flag"]
1376    #[inline(always)]
1377    pub fn orer(
1378        self,
1379    ) -> crate::common::RegisterField<
1380        5,
1381        0x1,
1382        1,
1383        0,
1384        ssr_smci::Orer,
1385        ssr_smci::Orer,
1386        SsrSmci_SPEC,
1387        crate::common::RW,
1388    > {
1389        crate::common::RegisterField::<
1390            5,
1391            0x1,
1392            1,
1393            0,
1394            ssr_smci::Orer,
1395            ssr_smci::Orer,
1396            SsrSmci_SPEC,
1397            crate::common::RW,
1398        >::from_register(self, 0)
1399    }
1400
1401    #[doc = "Receive Data Full Flag"]
1402    #[inline(always)]
1403    pub fn rdrf(
1404        self,
1405    ) -> crate::common::RegisterField<
1406        6,
1407        0x1,
1408        1,
1409        0,
1410        ssr_smci::Rdrf,
1411        ssr_smci::Rdrf,
1412        SsrSmci_SPEC,
1413        crate::common::RW,
1414    > {
1415        crate::common::RegisterField::<
1416            6,
1417            0x1,
1418            1,
1419            0,
1420            ssr_smci::Rdrf,
1421            ssr_smci::Rdrf,
1422            SsrSmci_SPEC,
1423            crate::common::RW,
1424        >::from_register(self, 0)
1425    }
1426
1427    #[doc = "Transmit Data Empty Flag"]
1428    #[inline(always)]
1429    pub fn tdre(
1430        self,
1431    ) -> crate::common::RegisterField<
1432        7,
1433        0x1,
1434        1,
1435        0,
1436        ssr_smci::Tdre,
1437        ssr_smci::Tdre,
1438        SsrSmci_SPEC,
1439        crate::common::RW,
1440    > {
1441        crate::common::RegisterField::<
1442            7,
1443            0x1,
1444            1,
1445            0,
1446            ssr_smci::Tdre,
1447            ssr_smci::Tdre,
1448            SsrSmci_SPEC,
1449            crate::common::RW,
1450        >::from_register(self, 0)
1451    }
1452}
1453impl ::core::default::Default for SsrSmci {
1454    #[inline(always)]
1455    fn default() -> SsrSmci {
1456        <crate::RegValueT<SsrSmci_SPEC> as RegisterValue<_>>::new(132)
1457    }
1458}
1459pub mod ssr_smci {
1460
1461    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1462    pub struct Tend_SPEC;
1463    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
1464    impl Tend {
1465        #[doc = "A character is being transmitted"]
1466        pub const _0: Self = Self::new(0);
1467
1468        #[doc = "Character transfer is complete"]
1469        pub const _1: Self = Self::new(1);
1470    }
1471    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1472    pub struct Per_SPEC;
1473    pub type Per = crate::EnumBitfieldStruct<u8, Per_SPEC>;
1474    impl Per {
1475        #[doc = "No parity error occurred"]
1476        pub const _0: Self = Self::new(0);
1477
1478        #[doc = "Parity error occurred"]
1479        pub const _1: Self = Self::new(1);
1480    }
1481    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1482    pub struct Ers_SPEC;
1483    pub type Ers = crate::EnumBitfieldStruct<u8, Ers_SPEC>;
1484    impl Ers {
1485        #[doc = "No low error signal response"]
1486        pub const _0: Self = Self::new(0);
1487
1488        #[doc = "Low error signal response occurred"]
1489        pub const _1: Self = Self::new(1);
1490    }
1491    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1492    pub struct Orer_SPEC;
1493    pub type Orer = crate::EnumBitfieldStruct<u8, Orer_SPEC>;
1494    impl Orer {
1495        #[doc = "No overrun error occurred"]
1496        pub const _0: Self = Self::new(0);
1497
1498        #[doc = "Overrun error occurred"]
1499        pub const _1: Self = Self::new(1);
1500    }
1501    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1502    pub struct Rdrf_SPEC;
1503    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
1504    impl Rdrf {
1505        #[doc = "No received data in RDR register"]
1506        pub const _0: Self = Self::new(0);
1507
1508        #[doc = "Received data in RDR register"]
1509        pub const _1: Self = Self::new(1);
1510    }
1511    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1512    pub struct Tdre_SPEC;
1513    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
1514    impl Tdre {
1515        #[doc = "Transmit data in TDR register"]
1516        pub const _0: Self = Self::new(0);
1517
1518        #[doc = "No transmit data in TDR register"]
1519        pub const _1: Self = Self::new(1);
1520    }
1521}
1522#[doc(hidden)]
1523#[derive(Copy, Clone, Eq, PartialEq)]
1524pub struct Rdr_SPEC;
1525impl crate::sealed::RegSpec for Rdr_SPEC {
1526    type DataType = u8;
1527}
1528
1529#[doc = "Receive Data Register"]
1530pub type Rdr = crate::RegValueT<Rdr_SPEC>;
1531
1532impl NoBitfieldReg<Rdr_SPEC> for Rdr {}
1533impl ::core::default::Default for Rdr {
1534    #[inline(always)]
1535    fn default() -> Rdr {
1536        <crate::RegValueT<Rdr_SPEC> as RegisterValue<_>>::new(0)
1537    }
1538}
1539
1540#[doc(hidden)]
1541#[derive(Copy, Clone, Eq, PartialEq)]
1542pub struct Scmr_SPEC;
1543impl crate::sealed::RegSpec for Scmr_SPEC {
1544    type DataType = u8;
1545}
1546
1547#[doc = "Smart Card Mode Register"]
1548pub type Scmr = crate::RegValueT<Scmr_SPEC>;
1549
1550impl Scmr {
1551    #[doc = "Smart Card Interface Mode Select"]
1552    #[inline(always)]
1553    pub fn smif(
1554        self,
1555    ) -> crate::common::RegisterField<
1556        0,
1557        0x1,
1558        1,
1559        0,
1560        scmr::Smif,
1561        scmr::Smif,
1562        Scmr_SPEC,
1563        crate::common::RW,
1564    > {
1565        crate::common::RegisterField::<
1566            0,
1567            0x1,
1568            1,
1569            0,
1570            scmr::Smif,
1571            scmr::Smif,
1572            Scmr_SPEC,
1573            crate::common::RW,
1574        >::from_register(self, 0)
1575    }
1576
1577    #[doc = "Transmitted/Received Data Invert"]
1578    #[inline(always)]
1579    pub fn sinv(
1580        self,
1581    ) -> crate::common::RegisterField<
1582        2,
1583        0x1,
1584        1,
1585        0,
1586        scmr::Sinv,
1587        scmr::Sinv,
1588        Scmr_SPEC,
1589        crate::common::RW,
1590    > {
1591        crate::common::RegisterField::<
1592            2,
1593            0x1,
1594            1,
1595            0,
1596            scmr::Sinv,
1597            scmr::Sinv,
1598            Scmr_SPEC,
1599            crate::common::RW,
1600        >::from_register(self, 0)
1601    }
1602
1603    #[doc = "Transmitted/Received Data Transfer Direction"]
1604    #[inline(always)]
1605    pub fn sdir(
1606        self,
1607    ) -> crate::common::RegisterField<
1608        3,
1609        0x1,
1610        1,
1611        0,
1612        scmr::Sdir,
1613        scmr::Sdir,
1614        Scmr_SPEC,
1615        crate::common::RW,
1616    > {
1617        crate::common::RegisterField::<
1618            3,
1619            0x1,
1620            1,
1621            0,
1622            scmr::Sdir,
1623            scmr::Sdir,
1624            Scmr_SPEC,
1625            crate::common::RW,
1626        >::from_register(self, 0)
1627    }
1628
1629    #[doc = "Character Length 1"]
1630    #[inline(always)]
1631    pub fn chr1(
1632        self,
1633    ) -> crate::common::RegisterField<
1634        4,
1635        0x1,
1636        1,
1637        0,
1638        scmr::Chr1,
1639        scmr::Chr1,
1640        Scmr_SPEC,
1641        crate::common::RW,
1642    > {
1643        crate::common::RegisterField::<
1644            4,
1645            0x1,
1646            1,
1647            0,
1648            scmr::Chr1,
1649            scmr::Chr1,
1650            Scmr_SPEC,
1651            crate::common::RW,
1652        >::from_register(self, 0)
1653    }
1654
1655    #[doc = "Base Clock Pulse 2"]
1656    #[inline(always)]
1657    pub fn bcp2(self) -> crate::common::RegisterFieldBool<7, 1, 0, Scmr_SPEC, crate::common::RW> {
1658        crate::common::RegisterFieldBool::<7, 1, 0, Scmr_SPEC, crate::common::RW>::from_register(
1659            self, 0,
1660        )
1661    }
1662}
1663impl ::core::default::Default for Scmr {
1664    #[inline(always)]
1665    fn default() -> Scmr {
1666        <crate::RegValueT<Scmr_SPEC> as RegisterValue<_>>::new(242)
1667    }
1668}
1669pub mod scmr {
1670
1671    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1672    pub struct Smif_SPEC;
1673    pub type Smif = crate::EnumBitfieldStruct<u8, Smif_SPEC>;
1674    impl Smif {
1675        #[doc = "Non-smart card interface mode (asynchronous mode, clock synchronous mode, simple SPI mode, or simple IIC mode)"]
1676        pub const _0: Self = Self::new(0);
1677
1678        #[doc = "Smart card interface mode"]
1679        pub const _1: Self = Self::new(1);
1680    }
1681    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1682    pub struct Sinv_SPEC;
1683    pub type Sinv = crate::EnumBitfieldStruct<u8, Sinv_SPEC>;
1684    impl Sinv {
1685        #[doc = "TDR contents are transmitted as they are. Received data is stored as received in the RDR register."]
1686        pub const _0: Self = Self::new(0);
1687
1688        #[doc = "TDR register contents are inverted before transmission. Receive data is stored in inverted form in the RDR register."]
1689        pub const _1: Self = Self::new(1);
1690    }
1691    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1692    pub struct Sdir_SPEC;
1693    pub type Sdir = crate::EnumBitfieldStruct<u8, Sdir_SPEC>;
1694    impl Sdir {
1695        #[doc = "Transfer LSB-first"]
1696        pub const _0: Self = Self::new(0);
1697
1698        #[doc = "Transfer MSB-first"]
1699        pub const _1: Self = Self::new(1);
1700    }
1701    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1702    pub struct Chr1_SPEC;
1703    pub type Chr1 = crate::EnumBitfieldStruct<u8, Chr1_SPEC>;
1704    impl Chr1 {
1705        #[doc = "SMR.CHR = 0: Transmit/receive in 9-bit data length SMR.CHR = 1: Transmit/receive in 9-bit data length"]
1706        pub const _0: Self = Self::new(0);
1707
1708        #[doc = "SMR.CHR = 0: Transmit/receive in 8-bit data length (initial value) SMR.CHR = 1: Transmit/receive in 7-bit data length"]
1709        pub const _1: Self = Self::new(1);
1710    }
1711}
1712#[doc(hidden)]
1713#[derive(Copy, Clone, Eq, PartialEq)]
1714pub struct Semr_SPEC;
1715impl crate::sealed::RegSpec for Semr_SPEC {
1716    type DataType = u8;
1717}
1718
1719#[doc = "Serial Extended Mode Register"]
1720pub type Semr = crate::RegValueT<Semr_SPEC>;
1721
1722impl Semr {
1723    #[doc = "Bit Rate Modulation Enable"]
1724    #[inline(always)]
1725    pub fn brme(
1726        self,
1727    ) -> crate::common::RegisterField<
1728        2,
1729        0x1,
1730        1,
1731        0,
1732        semr::Brme,
1733        semr::Brme,
1734        Semr_SPEC,
1735        crate::common::RW,
1736    > {
1737        crate::common::RegisterField::<
1738            2,
1739            0x1,
1740            1,
1741            0,
1742            semr::Brme,
1743            semr::Brme,
1744            Semr_SPEC,
1745            crate::common::RW,
1746        >::from_register(self, 0)
1747    }
1748
1749    #[doc = "Asynchronous Mode Extended Base Clock Select 1"]
1750    #[inline(always)]
1751    pub fn abcse(
1752        self,
1753    ) -> crate::common::RegisterField<
1754        3,
1755        0x1,
1756        1,
1757        0,
1758        semr::Abcse,
1759        semr::Abcse,
1760        Semr_SPEC,
1761        crate::common::RW,
1762    > {
1763        crate::common::RegisterField::<
1764            3,
1765            0x1,
1766            1,
1767            0,
1768            semr::Abcse,
1769            semr::Abcse,
1770            Semr_SPEC,
1771            crate::common::RW,
1772        >::from_register(self, 0)
1773    }
1774
1775    #[doc = "Asynchronous Mode Base Clock Select"]
1776    #[inline(always)]
1777    pub fn abcs(
1778        self,
1779    ) -> crate::common::RegisterField<
1780        4,
1781        0x1,
1782        1,
1783        0,
1784        semr::Abcs,
1785        semr::Abcs,
1786        Semr_SPEC,
1787        crate::common::RW,
1788    > {
1789        crate::common::RegisterField::<
1790            4,
1791            0x1,
1792            1,
1793            0,
1794            semr::Abcs,
1795            semr::Abcs,
1796            Semr_SPEC,
1797            crate::common::RW,
1798        >::from_register(self, 0)
1799    }
1800
1801    #[doc = "Digital Noise Filter Function Enable"]
1802    #[inline(always)]
1803    pub fn nfen(
1804        self,
1805    ) -> crate::common::RegisterField<
1806        5,
1807        0x1,
1808        1,
1809        0,
1810        semr::Nfen,
1811        semr::Nfen,
1812        Semr_SPEC,
1813        crate::common::RW,
1814    > {
1815        crate::common::RegisterField::<
1816            5,
1817            0x1,
1818            1,
1819            0,
1820            semr::Nfen,
1821            semr::Nfen,
1822            Semr_SPEC,
1823            crate::common::RW,
1824        >::from_register(self, 0)
1825    }
1826
1827    #[doc = "Baud Rate Generator Double-Speed Mode Select"]
1828    #[inline(always)]
1829    pub fn bgdm(
1830        self,
1831    ) -> crate::common::RegisterField<
1832        6,
1833        0x1,
1834        1,
1835        0,
1836        semr::Bgdm,
1837        semr::Bgdm,
1838        Semr_SPEC,
1839        crate::common::RW,
1840    > {
1841        crate::common::RegisterField::<
1842            6,
1843            0x1,
1844            1,
1845            0,
1846            semr::Bgdm,
1847            semr::Bgdm,
1848            Semr_SPEC,
1849            crate::common::RW,
1850        >::from_register(self, 0)
1851    }
1852
1853    #[doc = "Asynchronous Start Bit Edge Detection Select"]
1854    #[inline(always)]
1855    pub fn rxdesel(
1856        self,
1857    ) -> crate::common::RegisterField<
1858        7,
1859        0x1,
1860        1,
1861        0,
1862        semr::Rxdesel,
1863        semr::Rxdesel,
1864        Semr_SPEC,
1865        crate::common::RW,
1866    > {
1867        crate::common::RegisterField::<
1868            7,
1869            0x1,
1870            1,
1871            0,
1872            semr::Rxdesel,
1873            semr::Rxdesel,
1874            Semr_SPEC,
1875            crate::common::RW,
1876        >::from_register(self, 0)
1877    }
1878}
1879impl ::core::default::Default for Semr {
1880    #[inline(always)]
1881    fn default() -> Semr {
1882        <crate::RegValueT<Semr_SPEC> as RegisterValue<_>>::new(0)
1883    }
1884}
1885pub mod semr {
1886
1887    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1888    pub struct Brme_SPEC;
1889    pub type Brme = crate::EnumBitfieldStruct<u8, Brme_SPEC>;
1890    impl Brme {
1891        #[doc = "Disable bit rate modulation function"]
1892        pub const _0: Self = Self::new(0);
1893
1894        #[doc = "Enable bit rate modulation function"]
1895        pub const _1: Self = Self::new(1);
1896    }
1897    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1898    pub struct Abcse_SPEC;
1899    pub type Abcse = crate::EnumBitfieldStruct<u8, Abcse_SPEC>;
1900    impl Abcse {
1901        #[doc = "Clock cycles for 1-bit period determined by combination of the BGDM and ABCS bits in the SEMR register"]
1902        pub const _0: Self = Self::new(0);
1903
1904        #[doc = "Baud rate is 6 base clock cycles for 1-bit period"]
1905        pub const _1: Self = Self::new(1);
1906    }
1907    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1908    pub struct Abcs_SPEC;
1909    pub type Abcs = crate::EnumBitfieldStruct<u8, Abcs_SPEC>;
1910    impl Abcs {
1911        #[doc = "Select 16 base clock cycles for 1-bit period"]
1912        pub const _0: Self = Self::new(0);
1913
1914        #[doc = "Select 8 base clock cycles for 1-bit period"]
1915        pub const _1: Self = Self::new(1);
1916    }
1917    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1918    pub struct Nfen_SPEC;
1919    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
1920    impl Nfen {
1921        #[doc = "In asynchronous mode: Disable noise cancellation function for RXDn input signal In simple I2C mode: Disable noise cancellation function for SCLn and SDAn input signals"]
1922        pub const _0: Self = Self::new(0);
1923
1924        #[doc = "In asynchronous mode: Enable noise cancellation function for RXDn input signal In simple I2C mode: Enable noise cancellation function for SCLn and SDAn input signals"]
1925        pub const _1: Self = Self::new(1);
1926    }
1927    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1928    pub struct Bgdm_SPEC;
1929    pub type Bgdm = crate::EnumBitfieldStruct<u8, Bgdm_SPEC>;
1930    impl Bgdm {
1931        #[doc = "Output clock from baud rate generator with normal frequency"]
1932        pub const _0: Self = Self::new(0);
1933
1934        #[doc = "Output clock from baud rate generator with doubled frequency"]
1935        pub const _1: Self = Self::new(1);
1936    }
1937    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1938    pub struct Rxdesel_SPEC;
1939    pub type Rxdesel = crate::EnumBitfieldStruct<u8, Rxdesel_SPEC>;
1940    impl Rxdesel {
1941        #[doc = "Detect low level on RXDn pin as start bit"]
1942        pub const _0: Self = Self::new(0);
1943
1944        #[doc = "Detect falling edge of RXDn pin as start bit"]
1945        pub const _1: Self = Self::new(1);
1946    }
1947}
1948#[doc(hidden)]
1949#[derive(Copy, Clone, Eq, PartialEq)]
1950pub struct Snfr_SPEC;
1951impl crate::sealed::RegSpec for Snfr_SPEC {
1952    type DataType = u8;
1953}
1954
1955#[doc = "Noise Filter Setting Register"]
1956pub type Snfr = crate::RegValueT<Snfr_SPEC>;
1957
1958impl Snfr {
1959    #[doc = "Noise Filter Clock Select"]
1960    #[inline(always)]
1961    pub fn nfcs(
1962        self,
1963    ) -> crate::common::RegisterField<
1964        0,
1965        0x7,
1966        1,
1967        0,
1968        snfr::Nfcs,
1969        snfr::Nfcs,
1970        Snfr_SPEC,
1971        crate::common::RW,
1972    > {
1973        crate::common::RegisterField::<
1974            0,
1975            0x7,
1976            1,
1977            0,
1978            snfr::Nfcs,
1979            snfr::Nfcs,
1980            Snfr_SPEC,
1981            crate::common::RW,
1982        >::from_register(self, 0)
1983    }
1984}
1985impl ::core::default::Default for Snfr {
1986    #[inline(always)]
1987    fn default() -> Snfr {
1988        <crate::RegValueT<Snfr_SPEC> as RegisterValue<_>>::new(0)
1989    }
1990}
1991pub mod snfr {
1992
1993    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1994    pub struct Nfcs_SPEC;
1995    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
1996    impl Nfcs {
1997        #[doc = "In asynchronous mode: Use clock signal divided by 1 with noise filter In simple I2C mode: Setting prohibited"]
1998        pub const _000: Self = Self::new(0);
1999
2000        #[doc = "In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 1 with noise filter"]
2001        pub const _001: Self = Self::new(1);
2002
2003        #[doc = "In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 2 with noise filter"]
2004        pub const _010: Self = Self::new(2);
2005
2006        #[doc = "In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 4 with noise filter"]
2007        pub const _011: Self = Self::new(3);
2008
2009        #[doc = "In asynchronous mode: Setting prohibited In simple I2C mode: Use clock signal divided by 8 with noise filter"]
2010        pub const _100: Self = Self::new(4);
2011    }
2012}
2013#[doc(hidden)]
2014#[derive(Copy, Clone, Eq, PartialEq)]
2015pub struct Simr1_SPEC;
2016impl crate::sealed::RegSpec for Simr1_SPEC {
2017    type DataType = u8;
2018}
2019
2020#[doc = "IIC Mode Register 1"]
2021pub type Simr1 = crate::RegValueT<Simr1_SPEC>;
2022
2023impl Simr1 {
2024    #[doc = "Simple IIC Mode Select"]
2025    #[inline(always)]
2026    pub fn iicm(
2027        self,
2028    ) -> crate::common::RegisterField<
2029        0,
2030        0x1,
2031        1,
2032        0,
2033        simr1::Iicm,
2034        simr1::Iicm,
2035        Simr1_SPEC,
2036        crate::common::RW,
2037    > {
2038        crate::common::RegisterField::<
2039            0,
2040            0x1,
2041            1,
2042            0,
2043            simr1::Iicm,
2044            simr1::Iicm,
2045            Simr1_SPEC,
2046            crate::common::RW,
2047        >::from_register(self, 0)
2048    }
2049
2050    #[doc = "SDAn Delay Output Select"]
2051    #[inline(always)]
2052    pub fn iicdl(
2053        self,
2054    ) -> crate::common::RegisterField<
2055        3,
2056        0x1f,
2057        1,
2058        0,
2059        simr1::Iicdl,
2060        simr1::Iicdl,
2061        Simr1_SPEC,
2062        crate::common::RW,
2063    > {
2064        crate::common::RegisterField::<
2065            3,
2066            0x1f,
2067            1,
2068            0,
2069            simr1::Iicdl,
2070            simr1::Iicdl,
2071            Simr1_SPEC,
2072            crate::common::RW,
2073        >::from_register(self, 0)
2074    }
2075}
2076impl ::core::default::Default for Simr1 {
2077    #[inline(always)]
2078    fn default() -> Simr1 {
2079        <crate::RegValueT<Simr1_SPEC> as RegisterValue<_>>::new(0)
2080    }
2081}
2082pub mod simr1 {
2083
2084    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2085    pub struct Iicm_SPEC;
2086    pub type Iicm = crate::EnumBitfieldStruct<u8, Iicm_SPEC>;
2087    impl Iicm {
2088        #[doc = "SCMR.SMIF = 0: Asynchronous mode (including multi-processor mode), clock synchronous mode, or simple SPI mode SCMR.SMIF = 1: Smart card interface mode"]
2089        pub const _0: Self = Self::new(0);
2090
2091        #[doc = "SCMR.SMIF = 0: Simple IIC mode SCMR.SMIF = 1: Setting prohibited"]
2092        pub const _1: Self = Self::new(1);
2093    }
2094    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2095    pub struct Iicdl_SPEC;
2096    pub type Iicdl = crate::EnumBitfieldStruct<u8, Iicdl_SPEC>;
2097    impl Iicdl {
2098        #[doc = "No output delay"]
2099        pub const _0_X_00: Self = Self::new(0);
2100    }
2101}
2102#[doc(hidden)]
2103#[derive(Copy, Clone, Eq, PartialEq)]
2104pub struct Simr2_SPEC;
2105impl crate::sealed::RegSpec for Simr2_SPEC {
2106    type DataType = u8;
2107}
2108
2109#[doc = "IIC Mode Register 2"]
2110pub type Simr2 = crate::RegValueT<Simr2_SPEC>;
2111
2112impl Simr2 {
2113    #[doc = "IIC Interrupt Mode Select"]
2114    #[inline(always)]
2115    pub fn iicintm(
2116        self,
2117    ) -> crate::common::RegisterField<
2118        0,
2119        0x1,
2120        1,
2121        0,
2122        simr2::Iicintm,
2123        simr2::Iicintm,
2124        Simr2_SPEC,
2125        crate::common::RW,
2126    > {
2127        crate::common::RegisterField::<
2128            0,
2129            0x1,
2130            1,
2131            0,
2132            simr2::Iicintm,
2133            simr2::Iicintm,
2134            Simr2_SPEC,
2135            crate::common::RW,
2136        >::from_register(self, 0)
2137    }
2138
2139    #[doc = "Clock Synchronization"]
2140    #[inline(always)]
2141    pub fn iiccsc(
2142        self,
2143    ) -> crate::common::RegisterField<
2144        1,
2145        0x1,
2146        1,
2147        0,
2148        simr2::Iiccsc,
2149        simr2::Iiccsc,
2150        Simr2_SPEC,
2151        crate::common::RW,
2152    > {
2153        crate::common::RegisterField::<
2154            1,
2155            0x1,
2156            1,
2157            0,
2158            simr2::Iiccsc,
2159            simr2::Iiccsc,
2160            Simr2_SPEC,
2161            crate::common::RW,
2162        >::from_register(self, 0)
2163    }
2164
2165    #[doc = "ACK Transmission Data"]
2166    #[inline(always)]
2167    pub fn iicackt(
2168        self,
2169    ) -> crate::common::RegisterField<
2170        5,
2171        0x1,
2172        1,
2173        0,
2174        simr2::Iicackt,
2175        simr2::Iicackt,
2176        Simr2_SPEC,
2177        crate::common::RW,
2178    > {
2179        crate::common::RegisterField::<
2180            5,
2181            0x1,
2182            1,
2183            0,
2184            simr2::Iicackt,
2185            simr2::Iicackt,
2186            Simr2_SPEC,
2187            crate::common::RW,
2188        >::from_register(self, 0)
2189    }
2190}
2191impl ::core::default::Default for Simr2 {
2192    #[inline(always)]
2193    fn default() -> Simr2 {
2194        <crate::RegValueT<Simr2_SPEC> as RegisterValue<_>>::new(0)
2195    }
2196}
2197pub mod simr2 {
2198
2199    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2200    pub struct Iicintm_SPEC;
2201    pub type Iicintm = crate::EnumBitfieldStruct<u8, Iicintm_SPEC>;
2202    impl Iicintm {
2203        #[doc = "Use ACK/NACK interrupts"]
2204        pub const _0: Self = Self::new(0);
2205
2206        #[doc = "Use reception and transmission interrupts"]
2207        pub const _1: Self = Self::new(1);
2208    }
2209    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2210    pub struct Iiccsc_SPEC;
2211    pub type Iiccsc = crate::EnumBitfieldStruct<u8, Iiccsc_SPEC>;
2212    impl Iiccsc {
2213        #[doc = "Do not synchronize with clock signal"]
2214        pub const _0: Self = Self::new(0);
2215
2216        #[doc = "Synchronize with clock signal"]
2217        pub const _1: Self = Self::new(1);
2218    }
2219    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2220    pub struct Iicackt_SPEC;
2221    pub type Iicackt = crate::EnumBitfieldStruct<u8, Iicackt_SPEC>;
2222    impl Iicackt {
2223        #[doc = "ACK transmission"]
2224        pub const _0: Self = Self::new(0);
2225
2226        #[doc = "NACK transmission and ACK/NACK reception"]
2227        pub const _1: Self = Self::new(1);
2228    }
2229}
2230#[doc(hidden)]
2231#[derive(Copy, Clone, Eq, PartialEq)]
2232pub struct Simr3_SPEC;
2233impl crate::sealed::RegSpec for Simr3_SPEC {
2234    type DataType = u8;
2235}
2236
2237#[doc = "IIC Mode Register 3"]
2238pub type Simr3 = crate::RegValueT<Simr3_SPEC>;
2239
2240impl Simr3 {
2241    #[doc = "Start Condition Generation"]
2242    #[inline(always)]
2243    pub fn iicstareq(
2244        self,
2245    ) -> crate::common::RegisterField<
2246        0,
2247        0x1,
2248        1,
2249        0,
2250        simr3::Iicstareq,
2251        simr3::Iicstareq,
2252        Simr3_SPEC,
2253        crate::common::RW,
2254    > {
2255        crate::common::RegisterField::<
2256            0,
2257            0x1,
2258            1,
2259            0,
2260            simr3::Iicstareq,
2261            simr3::Iicstareq,
2262            Simr3_SPEC,
2263            crate::common::RW,
2264        >::from_register(self, 0)
2265    }
2266
2267    #[doc = "Restart Condition Generation"]
2268    #[inline(always)]
2269    pub fn iicrstareq(
2270        self,
2271    ) -> crate::common::RegisterField<
2272        1,
2273        0x1,
2274        1,
2275        0,
2276        simr3::Iicrstareq,
2277        simr3::Iicrstareq,
2278        Simr3_SPEC,
2279        crate::common::RW,
2280    > {
2281        crate::common::RegisterField::<
2282            1,
2283            0x1,
2284            1,
2285            0,
2286            simr3::Iicrstareq,
2287            simr3::Iicrstareq,
2288            Simr3_SPEC,
2289            crate::common::RW,
2290        >::from_register(self, 0)
2291    }
2292
2293    #[doc = "Stop Condition Generation"]
2294    #[inline(always)]
2295    pub fn iicstpreq(
2296        self,
2297    ) -> crate::common::RegisterField<
2298        2,
2299        0x1,
2300        1,
2301        0,
2302        simr3::Iicstpreq,
2303        simr3::Iicstpreq,
2304        Simr3_SPEC,
2305        crate::common::RW,
2306    > {
2307        crate::common::RegisterField::<
2308            2,
2309            0x1,
2310            1,
2311            0,
2312            simr3::Iicstpreq,
2313            simr3::Iicstpreq,
2314            Simr3_SPEC,
2315            crate::common::RW,
2316        >::from_register(self, 0)
2317    }
2318
2319    #[doc = "Issuing of Start, Restart, or Stop Condition Completed Flag"]
2320    #[inline(always)]
2321    pub fn iicstif(
2322        self,
2323    ) -> crate::common::RegisterField<
2324        3,
2325        0x1,
2326        1,
2327        0,
2328        simr3::Iicstif,
2329        simr3::Iicstif,
2330        Simr3_SPEC,
2331        crate::common::RW,
2332    > {
2333        crate::common::RegisterField::<
2334            3,
2335            0x1,
2336            1,
2337            0,
2338            simr3::Iicstif,
2339            simr3::Iicstif,
2340            Simr3_SPEC,
2341            crate::common::RW,
2342        >::from_register(self, 0)
2343    }
2344
2345    #[doc = "SDAn Output Select"]
2346    #[inline(always)]
2347    pub fn iicsdas(
2348        self,
2349    ) -> crate::common::RegisterField<
2350        4,
2351        0x3,
2352        1,
2353        0,
2354        simr3::Iicsdas,
2355        simr3::Iicsdas,
2356        Simr3_SPEC,
2357        crate::common::RW,
2358    > {
2359        crate::common::RegisterField::<
2360            4,
2361            0x3,
2362            1,
2363            0,
2364            simr3::Iicsdas,
2365            simr3::Iicsdas,
2366            Simr3_SPEC,
2367            crate::common::RW,
2368        >::from_register(self, 0)
2369    }
2370
2371    #[doc = "SCLn Output Select"]
2372    #[inline(always)]
2373    pub fn iicscls(
2374        self,
2375    ) -> crate::common::RegisterField<
2376        6,
2377        0x3,
2378        1,
2379        0,
2380        simr3::Iicscls,
2381        simr3::Iicscls,
2382        Simr3_SPEC,
2383        crate::common::RW,
2384    > {
2385        crate::common::RegisterField::<
2386            6,
2387            0x3,
2388            1,
2389            0,
2390            simr3::Iicscls,
2391            simr3::Iicscls,
2392            Simr3_SPEC,
2393            crate::common::RW,
2394        >::from_register(self, 0)
2395    }
2396}
2397impl ::core::default::Default for Simr3 {
2398    #[inline(always)]
2399    fn default() -> Simr3 {
2400        <crate::RegValueT<Simr3_SPEC> as RegisterValue<_>>::new(0)
2401    }
2402}
2403pub mod simr3 {
2404
2405    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2406    pub struct Iicstareq_SPEC;
2407    pub type Iicstareq = crate::EnumBitfieldStruct<u8, Iicstareq_SPEC>;
2408    impl Iicstareq {
2409        #[doc = "Do not generate start condition"]
2410        pub const _0: Self = Self::new(0);
2411
2412        #[doc = "Generate start condition"]
2413        pub const _1: Self = Self::new(1);
2414    }
2415    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2416    pub struct Iicrstareq_SPEC;
2417    pub type Iicrstareq = crate::EnumBitfieldStruct<u8, Iicrstareq_SPEC>;
2418    impl Iicrstareq {
2419        #[doc = "Do not generate restart condition"]
2420        pub const _0: Self = Self::new(0);
2421
2422        #[doc = "Generate restart condition"]
2423        pub const _1: Self = Self::new(1);
2424    }
2425    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2426    pub struct Iicstpreq_SPEC;
2427    pub type Iicstpreq = crate::EnumBitfieldStruct<u8, Iicstpreq_SPEC>;
2428    impl Iicstpreq {
2429        #[doc = "Do not generate stop condition"]
2430        pub const _0: Self = Self::new(0);
2431
2432        #[doc = "Generate stop condition"]
2433        pub const _1: Self = Self::new(1);
2434    }
2435    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2436    pub struct Iicstif_SPEC;
2437    pub type Iicstif = crate::EnumBitfieldStruct<u8, Iicstif_SPEC>;
2438    impl Iicstif {
2439        #[doc = "No requests are being made for generating conditions, or a condition is being generated"]
2440        pub const _0: Self = Self::new(0);
2441
2442        #[doc = "Generation of start, restart, or stop condition is complete. When 0 is written to IICSTIF, it is set to 0"]
2443        pub const _1: Self = Self::new(1);
2444    }
2445    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2446    pub struct Iicsdas_SPEC;
2447    pub type Iicsdas = crate::EnumBitfieldStruct<u8, Iicsdas_SPEC>;
2448    impl Iicsdas {
2449        #[doc = "Output serial data"]
2450        pub const _00: Self = Self::new(0);
2451
2452        #[doc = "Generate start, restart, or stop condition"]
2453        pub const _01: Self = Self::new(1);
2454
2455        #[doc = "Output low on SDAn pin"]
2456        pub const _10: Self = Self::new(2);
2457
2458        #[doc = "Drive SDAn pin to high-impedance state"]
2459        pub const _11: Self = Self::new(3);
2460    }
2461    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2462    pub struct Iicscls_SPEC;
2463    pub type Iicscls = crate::EnumBitfieldStruct<u8, Iicscls_SPEC>;
2464    impl Iicscls {
2465        #[doc = "Output serial clock"]
2466        pub const _00: Self = Self::new(0);
2467
2468        #[doc = "Generate start, restart, or stop condition"]
2469        pub const _01: Self = Self::new(1);
2470
2471        #[doc = "Output low on SCLn pin"]
2472        pub const _10: Self = Self::new(2);
2473
2474        #[doc = "Drive SCLn pin to high-impedance state"]
2475        pub const _11: Self = Self::new(3);
2476    }
2477}
2478#[doc(hidden)]
2479#[derive(Copy, Clone, Eq, PartialEq)]
2480pub struct Sisr_SPEC;
2481impl crate::sealed::RegSpec for Sisr_SPEC {
2482    type DataType = u8;
2483}
2484
2485#[doc = "IIC Status Register"]
2486pub type Sisr = crate::RegValueT<Sisr_SPEC>;
2487
2488impl Sisr {
2489    #[doc = "ACK Reception Data Flag"]
2490    #[inline(always)]
2491    pub fn iicackr(
2492        self,
2493    ) -> crate::common::RegisterField<
2494        0,
2495        0x1,
2496        1,
2497        0,
2498        sisr::Iicackr,
2499        sisr::Iicackr,
2500        Sisr_SPEC,
2501        crate::common::R,
2502    > {
2503        crate::common::RegisterField::<
2504            0,
2505            0x1,
2506            1,
2507            0,
2508            sisr::Iicackr,
2509            sisr::Iicackr,
2510            Sisr_SPEC,
2511            crate::common::R,
2512        >::from_register(self, 0)
2513    }
2514}
2515impl ::core::default::Default for Sisr {
2516    #[inline(always)]
2517    fn default() -> Sisr {
2518        <crate::RegValueT<Sisr_SPEC> as RegisterValue<_>>::new(0)
2519    }
2520}
2521pub mod sisr {
2522
2523    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2524    pub struct Iicackr_SPEC;
2525    pub type Iicackr = crate::EnumBitfieldStruct<u8, Iicackr_SPEC>;
2526    impl Iicackr {
2527        #[doc = "ACK received"]
2528        pub const _0: Self = Self::new(0);
2529
2530        #[doc = "NACK received"]
2531        pub const _1: Self = Self::new(1);
2532    }
2533}
2534#[doc(hidden)]
2535#[derive(Copy, Clone, Eq, PartialEq)]
2536pub struct Spmr_SPEC;
2537impl crate::sealed::RegSpec for Spmr_SPEC {
2538    type DataType = u8;
2539}
2540
2541#[doc = "SPI Mode Register"]
2542pub type Spmr = crate::RegValueT<Spmr_SPEC>;
2543
2544impl Spmr {
2545    #[doc = "SSn Pin Function Enable"]
2546    #[inline(always)]
2547    pub fn sse(
2548        self,
2549    ) -> crate::common::RegisterField<
2550        0,
2551        0x1,
2552        1,
2553        0,
2554        spmr::Sse,
2555        spmr::Sse,
2556        Spmr_SPEC,
2557        crate::common::RW,
2558    > {
2559        crate::common::RegisterField::<
2560            0,
2561            0x1,
2562            1,
2563            0,
2564            spmr::Sse,
2565            spmr::Sse,
2566            Spmr_SPEC,
2567            crate::common::RW,
2568        >::from_register(self, 0)
2569    }
2570
2571    #[doc = "CTS Enable"]
2572    #[inline(always)]
2573    pub fn ctse(
2574        self,
2575    ) -> crate::common::RegisterField<
2576        1,
2577        0x1,
2578        1,
2579        0,
2580        spmr::Ctse,
2581        spmr::Ctse,
2582        Spmr_SPEC,
2583        crate::common::RW,
2584    > {
2585        crate::common::RegisterField::<
2586            1,
2587            0x1,
2588            1,
2589            0,
2590            spmr::Ctse,
2591            spmr::Ctse,
2592            Spmr_SPEC,
2593            crate::common::RW,
2594        >::from_register(self, 0)
2595    }
2596
2597    #[doc = "Master Slave Select"]
2598    #[inline(always)]
2599    pub fn mss(
2600        self,
2601    ) -> crate::common::RegisterField<
2602        2,
2603        0x1,
2604        1,
2605        0,
2606        spmr::Mss,
2607        spmr::Mss,
2608        Spmr_SPEC,
2609        crate::common::RW,
2610    > {
2611        crate::common::RegisterField::<
2612            2,
2613            0x1,
2614            1,
2615            0,
2616            spmr::Mss,
2617            spmr::Mss,
2618            Spmr_SPEC,
2619            crate::common::RW,
2620        >::from_register(self, 0)
2621    }
2622
2623    #[doc = "Mode Fault Flag"]
2624    #[inline(always)]
2625    pub fn mff(
2626        self,
2627    ) -> crate::common::RegisterField<
2628        4,
2629        0x1,
2630        1,
2631        0,
2632        spmr::Mff,
2633        spmr::Mff,
2634        Spmr_SPEC,
2635        crate::common::RW,
2636    > {
2637        crate::common::RegisterField::<
2638            4,
2639            0x1,
2640            1,
2641            0,
2642            spmr::Mff,
2643            spmr::Mff,
2644            Spmr_SPEC,
2645            crate::common::RW,
2646        >::from_register(self, 0)
2647    }
2648
2649    #[doc = "Clock Polarity Select"]
2650    #[inline(always)]
2651    pub fn ckpol(
2652        self,
2653    ) -> crate::common::RegisterField<
2654        6,
2655        0x1,
2656        1,
2657        0,
2658        spmr::Ckpol,
2659        spmr::Ckpol,
2660        Spmr_SPEC,
2661        crate::common::RW,
2662    > {
2663        crate::common::RegisterField::<
2664            6,
2665            0x1,
2666            1,
2667            0,
2668            spmr::Ckpol,
2669            spmr::Ckpol,
2670            Spmr_SPEC,
2671            crate::common::RW,
2672        >::from_register(self, 0)
2673    }
2674
2675    #[doc = "Clock Phase Select"]
2676    #[inline(always)]
2677    pub fn ckph(
2678        self,
2679    ) -> crate::common::RegisterField<
2680        7,
2681        0x1,
2682        1,
2683        0,
2684        spmr::Ckph,
2685        spmr::Ckph,
2686        Spmr_SPEC,
2687        crate::common::RW,
2688    > {
2689        crate::common::RegisterField::<
2690            7,
2691            0x1,
2692            1,
2693            0,
2694            spmr::Ckph,
2695            spmr::Ckph,
2696            Spmr_SPEC,
2697            crate::common::RW,
2698        >::from_register(self, 0)
2699    }
2700}
2701impl ::core::default::Default for Spmr {
2702    #[inline(always)]
2703    fn default() -> Spmr {
2704        <crate::RegValueT<Spmr_SPEC> as RegisterValue<_>>::new(0)
2705    }
2706}
2707pub mod spmr {
2708
2709    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2710    pub struct Sse_SPEC;
2711    pub type Sse = crate::EnumBitfieldStruct<u8, Sse_SPEC>;
2712    impl Sse {
2713        #[doc = "Disable SSn pin function"]
2714        pub const _0: Self = Self::new(0);
2715
2716        #[doc = "Enable SSn pin function"]
2717        pub const _1: Self = Self::new(1);
2718    }
2719    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2720    pub struct Ctse_SPEC;
2721    pub type Ctse = crate::EnumBitfieldStruct<u8, Ctse_SPEC>;
2722    impl Ctse {
2723        #[doc = "Disable CTS function (enable RTS output function)"]
2724        pub const _0: Self = Self::new(0);
2725
2726        #[doc = "Enable CTS function"]
2727        pub const _1: Self = Self::new(1);
2728    }
2729    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2730    pub struct Mss_SPEC;
2731    pub type Mss = crate::EnumBitfieldStruct<u8, Mss_SPEC>;
2732    impl Mss {
2733        #[doc = "Transmit through TXDn pin and receive through RXDn pin (master mode)"]
2734        pub const _0: Self = Self::new(0);
2735
2736        #[doc = "Receive through TXDn pin and transmit through RXDn pin (slave mode)"]
2737        pub const _1: Self = Self::new(1);
2738    }
2739    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2740    pub struct Mff_SPEC;
2741    pub type Mff = crate::EnumBitfieldStruct<u8, Mff_SPEC>;
2742    impl Mff {
2743        #[doc = "No mode fault error"]
2744        pub const _0: Self = Self::new(0);
2745
2746        #[doc = "Mode fault error"]
2747        pub const _1: Self = Self::new(1);
2748    }
2749    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2750    pub struct Ckpol_SPEC;
2751    pub type Ckpol = crate::EnumBitfieldStruct<u8, Ckpol_SPEC>;
2752    impl Ckpol {
2753        #[doc = "Do not invert clock polarity"]
2754        pub const _0: Self = Self::new(0);
2755
2756        #[doc = "Invert clock polarity"]
2757        pub const _1: Self = Self::new(1);
2758    }
2759    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2760    pub struct Ckph_SPEC;
2761    pub type Ckph = crate::EnumBitfieldStruct<u8, Ckph_SPEC>;
2762    impl Ckph {
2763        #[doc = "Do not delay clock"]
2764        pub const _0: Self = Self::new(0);
2765
2766        #[doc = "Delay clock"]
2767        pub const _1: Self = Self::new(1);
2768    }
2769}
2770#[doc(hidden)]
2771#[derive(Copy, Clone, Eq, PartialEq)]
2772pub struct Tdrhl_SPEC;
2773impl crate::sealed::RegSpec for Tdrhl_SPEC {
2774    type DataType = u16;
2775}
2776
2777#[doc = "Transmit Data Register"]
2778pub type Tdrhl = crate::RegValueT<Tdrhl_SPEC>;
2779
2780impl Tdrhl {
2781    #[doc = "Serial Transmit Data"]
2782    #[inline(always)]
2783    pub fn tdat(
2784        self,
2785    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Tdrhl_SPEC, crate::common::RW> {
2786        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Tdrhl_SPEC,crate::common::RW>::from_register(self,0)
2787    }
2788}
2789impl ::core::default::Default for Tdrhl {
2790    #[inline(always)]
2791    fn default() -> Tdrhl {
2792        <crate::RegValueT<Tdrhl_SPEC> as RegisterValue<_>>::new(65535)
2793    }
2794}
2795
2796#[doc(hidden)]
2797#[derive(Copy, Clone, Eq, PartialEq)]
2798pub struct Rdrhl_SPEC;
2799impl crate::sealed::RegSpec for Rdrhl_SPEC {
2800    type DataType = u16;
2801}
2802
2803#[doc = "Receive Data Register"]
2804pub type Rdrhl = crate::RegValueT<Rdrhl_SPEC>;
2805
2806impl Rdrhl {
2807    #[doc = "Serial Receive Data"]
2808    #[inline(always)]
2809    pub fn rdat(
2810        self,
2811    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Rdrhl_SPEC, crate::common::R> {
2812        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Rdrhl_SPEC,crate::common::R>::from_register(self,0)
2813    }
2814}
2815impl ::core::default::Default for Rdrhl {
2816    #[inline(always)]
2817    fn default() -> Rdrhl {
2818        <crate::RegValueT<Rdrhl_SPEC> as RegisterValue<_>>::new(0)
2819    }
2820}
2821
2822#[doc(hidden)]
2823#[derive(Copy, Clone, Eq, PartialEq)]
2824pub struct Mddr_SPEC;
2825impl crate::sealed::RegSpec for Mddr_SPEC {
2826    type DataType = u8;
2827}
2828
2829#[doc = "Modulation Duty Register"]
2830pub type Mddr = crate::RegValueT<Mddr_SPEC>;
2831
2832impl NoBitfieldReg<Mddr_SPEC> for Mddr {}
2833impl ::core::default::Default for Mddr {
2834    #[inline(always)]
2835    fn default() -> Mddr {
2836        <crate::RegValueT<Mddr_SPEC> as RegisterValue<_>>::new(255)
2837    }
2838}
2839
2840#[doc(hidden)]
2841#[derive(Copy, Clone, Eq, PartialEq)]
2842pub struct Dccr_SPEC;
2843impl crate::sealed::RegSpec for Dccr_SPEC {
2844    type DataType = u8;
2845}
2846
2847#[doc = "Data Compare Match Control Register"]
2848pub type Dccr = crate::RegValueT<Dccr_SPEC>;
2849
2850impl Dccr {
2851    #[doc = "Data Compare Match Flag"]
2852    #[inline(always)]
2853    pub fn dcmf(
2854        self,
2855    ) -> crate::common::RegisterField<
2856        0,
2857        0x1,
2858        1,
2859        0,
2860        dccr::Dcmf,
2861        dccr::Dcmf,
2862        Dccr_SPEC,
2863        crate::common::RW,
2864    > {
2865        crate::common::RegisterField::<
2866            0,
2867            0x1,
2868            1,
2869            0,
2870            dccr::Dcmf,
2871            dccr::Dcmf,
2872            Dccr_SPEC,
2873            crate::common::RW,
2874        >::from_register(self, 0)
2875    }
2876
2877    #[doc = "Data Compare Match Parity Error Flag"]
2878    #[inline(always)]
2879    pub fn dper(
2880        self,
2881    ) -> crate::common::RegisterField<
2882        3,
2883        0x1,
2884        1,
2885        0,
2886        dccr::Dper,
2887        dccr::Dper,
2888        Dccr_SPEC,
2889        crate::common::RW,
2890    > {
2891        crate::common::RegisterField::<
2892            3,
2893            0x1,
2894            1,
2895            0,
2896            dccr::Dper,
2897            dccr::Dper,
2898            Dccr_SPEC,
2899            crate::common::RW,
2900        >::from_register(self, 0)
2901    }
2902
2903    #[doc = "Data Compare Match Framing Error Flag"]
2904    #[inline(always)]
2905    pub fn dfer(
2906        self,
2907    ) -> crate::common::RegisterField<
2908        4,
2909        0x1,
2910        1,
2911        0,
2912        dccr::Dfer,
2913        dccr::Dfer,
2914        Dccr_SPEC,
2915        crate::common::RW,
2916    > {
2917        crate::common::RegisterField::<
2918            4,
2919            0x1,
2920            1,
2921            0,
2922            dccr::Dfer,
2923            dccr::Dfer,
2924            Dccr_SPEC,
2925            crate::common::RW,
2926        >::from_register(self, 0)
2927    }
2928
2929    #[doc = "ID Frame Select"]
2930    #[inline(always)]
2931    pub fn idsel(
2932        self,
2933    ) -> crate::common::RegisterField<
2934        6,
2935        0x1,
2936        1,
2937        0,
2938        dccr::Idsel,
2939        dccr::Idsel,
2940        Dccr_SPEC,
2941        crate::common::RW,
2942    > {
2943        crate::common::RegisterField::<
2944            6,
2945            0x1,
2946            1,
2947            0,
2948            dccr::Idsel,
2949            dccr::Idsel,
2950            Dccr_SPEC,
2951            crate::common::RW,
2952        >::from_register(self, 0)
2953    }
2954
2955    #[doc = "Data Compare Match Enable"]
2956    #[inline(always)]
2957    pub fn dcme(
2958        self,
2959    ) -> crate::common::RegisterField<
2960        7,
2961        0x1,
2962        1,
2963        0,
2964        dccr::Dcme,
2965        dccr::Dcme,
2966        Dccr_SPEC,
2967        crate::common::RW,
2968    > {
2969        crate::common::RegisterField::<
2970            7,
2971            0x1,
2972            1,
2973            0,
2974            dccr::Dcme,
2975            dccr::Dcme,
2976            Dccr_SPEC,
2977            crate::common::RW,
2978        >::from_register(self, 0)
2979    }
2980}
2981impl ::core::default::Default for Dccr {
2982    #[inline(always)]
2983    fn default() -> Dccr {
2984        <crate::RegValueT<Dccr_SPEC> as RegisterValue<_>>::new(64)
2985    }
2986}
2987pub mod dccr {
2988
2989    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2990    pub struct Dcmf_SPEC;
2991    pub type Dcmf = crate::EnumBitfieldStruct<u8, Dcmf_SPEC>;
2992    impl Dcmf {
2993        #[doc = "Not matched"]
2994        pub const _0: Self = Self::new(0);
2995
2996        #[doc = "Matched"]
2997        pub const _1: Self = Self::new(1);
2998    }
2999    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3000    pub struct Dper_SPEC;
3001    pub type Dper = crate::EnumBitfieldStruct<u8, Dper_SPEC>;
3002    impl Dper {
3003        #[doc = "No parity error occurred"]
3004        pub const _0: Self = Self::new(0);
3005
3006        #[doc = "Parity error occurred"]
3007        pub const _1: Self = Self::new(1);
3008    }
3009    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3010    pub struct Dfer_SPEC;
3011    pub type Dfer = crate::EnumBitfieldStruct<u8, Dfer_SPEC>;
3012    impl Dfer {
3013        #[doc = "No framing error occurred"]
3014        pub const _0: Self = Self::new(0);
3015
3016        #[doc = "Framing error occurred"]
3017        pub const _1: Self = Self::new(1);
3018    }
3019    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3020    pub struct Idsel_SPEC;
3021    pub type Idsel = crate::EnumBitfieldStruct<u8, Idsel_SPEC>;
3022    impl Idsel {
3023        #[doc = "Always compare data regardless of the MPB bit value"]
3024        pub const _0: Self = Self::new(0);
3025
3026        #[doc = "Only compare data when MPB bit = 1 (ID frame)"]
3027        pub const _1: Self = Self::new(1);
3028    }
3029    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3030    pub struct Dcme_SPEC;
3031    pub type Dcme = crate::EnumBitfieldStruct<u8, Dcme_SPEC>;
3032    impl Dcme {
3033        #[doc = "Disable address match function"]
3034        pub const _0: Self = Self::new(0);
3035
3036        #[doc = "Enable address match function"]
3037        pub const _1: Self = Self::new(1);
3038    }
3039}
3040#[doc(hidden)]
3041#[derive(Copy, Clone, Eq, PartialEq)]
3042pub struct Cdr_SPEC;
3043impl crate::sealed::RegSpec for Cdr_SPEC {
3044    type DataType = u16;
3045}
3046
3047#[doc = "Compare Match Data Register"]
3048pub type Cdr = crate::RegValueT<Cdr_SPEC>;
3049
3050impl Cdr {
3051    #[doc = "Compare Match Data"]
3052    #[inline(always)]
3053    pub fn cmpd(
3054        self,
3055    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cdr_SPEC, crate::common::RW> {
3056        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cdr_SPEC,crate::common::RW>::from_register(self,0)
3057    }
3058}
3059impl ::core::default::Default for Cdr {
3060    #[inline(always)]
3061    fn default() -> Cdr {
3062        <crate::RegValueT<Cdr_SPEC> as RegisterValue<_>>::new(0)
3063    }
3064}
3065
3066#[doc(hidden)]
3067#[derive(Copy, Clone, Eq, PartialEq)]
3068pub struct Sptr_SPEC;
3069impl crate::sealed::RegSpec for Sptr_SPEC {
3070    type DataType = u8;
3071}
3072
3073#[doc = "Serial Port Register"]
3074pub type Sptr = crate::RegValueT<Sptr_SPEC>;
3075
3076impl Sptr {
3077    #[doc = "Serial Input Data Monitor"]
3078    #[inline(always)]
3079    pub fn rxdmon(
3080        self,
3081    ) -> crate::common::RegisterField<
3082        0,
3083        0x1,
3084        1,
3085        0,
3086        sptr::Rxdmon,
3087        sptr::Rxdmon,
3088        Sptr_SPEC,
3089        crate::common::R,
3090    > {
3091        crate::common::RegisterField::<
3092            0,
3093            0x1,
3094            1,
3095            0,
3096            sptr::Rxdmon,
3097            sptr::Rxdmon,
3098            Sptr_SPEC,
3099            crate::common::R,
3100        >::from_register(self, 0)
3101    }
3102
3103    #[doc = "Serial Port Break Data Select"]
3104    #[inline(always)]
3105    pub fn spb2dt(
3106        self,
3107    ) -> crate::common::RegisterField<
3108        1,
3109        0x1,
3110        1,
3111        0,
3112        sptr::Spb2Dt,
3113        sptr::Spb2Dt,
3114        Sptr_SPEC,
3115        crate::common::RW,
3116    > {
3117        crate::common::RegisterField::<
3118            1,
3119            0x1,
3120            1,
3121            0,
3122            sptr::Spb2Dt,
3123            sptr::Spb2Dt,
3124            Sptr_SPEC,
3125            crate::common::RW,
3126        >::from_register(self, 0)
3127    }
3128
3129    #[doc = "Serial Port Break I/O"]
3130    #[inline(always)]
3131    pub fn spb2io(
3132        self,
3133    ) -> crate::common::RegisterField<
3134        2,
3135        0x1,
3136        1,
3137        0,
3138        sptr::Spb2Io,
3139        sptr::Spb2Io,
3140        Sptr_SPEC,
3141        crate::common::RW,
3142    > {
3143        crate::common::RegisterField::<
3144            2,
3145            0x1,
3146            1,
3147            0,
3148            sptr::Spb2Io,
3149            sptr::Spb2Io,
3150            Sptr_SPEC,
3151            crate::common::RW,
3152        >::from_register(self, 0)
3153    }
3154}
3155impl ::core::default::Default for Sptr {
3156    #[inline(always)]
3157    fn default() -> Sptr {
3158        <crate::RegValueT<Sptr_SPEC> as RegisterValue<_>>::new(3)
3159    }
3160}
3161pub mod sptr {
3162
3163    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3164    pub struct Rxdmon_SPEC;
3165    pub type Rxdmon = crate::EnumBitfieldStruct<u8, Rxdmon_SPEC>;
3166    impl Rxdmon {
3167        #[doc = "RXDn terminal is the low level"]
3168        pub const _0: Self = Self::new(0);
3169
3170        #[doc = "RXDn terminal is the high level"]
3171        pub const _1: Self = Self::new(1);
3172    }
3173    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3174    pub struct Spb2Dt_SPEC;
3175    pub type Spb2Dt = crate::EnumBitfieldStruct<u8, Spb2Dt_SPEC>;
3176    impl Spb2Dt {
3177        #[doc = "Low level is output in TXDn terminal"]
3178        pub const _0: Self = Self::new(0);
3179
3180        #[doc = "High level is output in TXDn terminal"]
3181        pub const _1: Self = Self::new(1);
3182    }
3183    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3184    pub struct Spb2Io_SPEC;
3185    pub type Spb2Io = crate::EnumBitfieldStruct<u8, Spb2Io_SPEC>;
3186    impl Spb2Io {
3187        #[doc = "Do not output value of SPB2DT bit on TXDn pin"]
3188        pub const _0: Self = Self::new(0);
3189
3190        #[doc = "Output value of SPB2DT bit on TXDn pin"]
3191        pub const _1: Self = Self::new(1);
3192    }
3193}
ra2a2_pac/sci1.rs

ra2a2_pac/
sci1.rs
