1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"ICU for CPU"]
28unsafe impl ::core::marker::Send for super::Icu {}
29unsafe impl ::core::marker::Sync for super::Icu {}
30impl super::Icu {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "IRQ Control Register %s"]
38 #[inline(always)]
39 pub const fn irqcr(
40 &self,
41 ) -> &'static crate::common::ClusterRegisterArray<
42 crate::common::Reg<self::Irqcr_SPEC, crate::common::RW>,
43 12,
44 0x1,
45 > {
46 unsafe {
47 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48 }
49 }
50 #[inline(always)]
51 pub const fn irqcr0(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
52 unsafe {
53 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
54 self._svd2pac_as_ptr().add(0x0usize),
55 )
56 }
57 }
58 #[inline(always)]
59 pub const fn irqcr1(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(0x1usize),
63 )
64 }
65 }
66 #[inline(always)]
67 pub const fn irqcr2(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
68 unsafe {
69 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
70 self._svd2pac_as_ptr().add(0x2usize),
71 )
72 }
73 }
74 #[inline(always)]
75 pub const fn irqcr3(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
76 unsafe {
77 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
78 self._svd2pac_as_ptr().add(0x3usize),
79 )
80 }
81 }
82 #[inline(always)]
83 pub const fn irqcr4(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(0x4usize),
87 )
88 }
89 }
90 #[inline(always)]
91 pub const fn irqcr5(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
92 unsafe {
93 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
94 self._svd2pac_as_ptr().add(0x5usize),
95 )
96 }
97 }
98 #[inline(always)]
99 pub const fn irqcr6(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x6usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn irqcr7(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
108 unsafe {
109 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
110 self._svd2pac_as_ptr().add(0x7usize),
111 )
112 }
113 }
114 #[inline(always)]
115 pub const fn irqcr8(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
116 unsafe {
117 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
118 self._svd2pac_as_ptr().add(0x8usize),
119 )
120 }
121 }
122 #[inline(always)]
123 pub const fn irqcr9(&self) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
124 unsafe {
125 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
126 self._svd2pac_as_ptr().add(0x9usize),
127 )
128 }
129 }
130 #[inline(always)]
131 pub const fn irqcr10(
132 &self,
133 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(0xausize),
137 )
138 }
139 }
140 #[inline(always)]
141 pub const fn irqcr11(
142 &self,
143 ) -> &'static crate::common::Reg<self::Irqcr_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::Irqcr_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(0xbusize),
147 )
148 }
149 }
150
151 #[doc = "NMI Pin Interrupt Control Register"]
152 #[inline(always)]
153 pub const fn nmicr(&self) -> &'static crate::common::Reg<self::Nmicr_SPEC, crate::common::RW> {
154 unsafe {
155 crate::common::Reg::<self::Nmicr_SPEC, crate::common::RW>::from_ptr(
156 self._svd2pac_as_ptr().add(256usize),
157 )
158 }
159 }
160
161 #[doc = "Non-Maskable Interrupt Enable Register"]
162 #[inline(always)]
163 pub const fn nmier(&self) -> &'static crate::common::Reg<self::Nmier_SPEC, crate::common::RW> {
164 unsafe {
165 crate::common::Reg::<self::Nmier_SPEC, crate::common::RW>::from_ptr(
166 self._svd2pac_as_ptr().add(288usize),
167 )
168 }
169 }
170
171 #[doc = "Non-Maskable Interrupt Status Clear Register"]
172 #[inline(always)]
173 pub const fn nmiclr(
174 &self,
175 ) -> &'static crate::common::Reg<self::Nmiclr_SPEC, crate::common::RW> {
176 unsafe {
177 crate::common::Reg::<self::Nmiclr_SPEC, crate::common::RW>::from_ptr(
178 self._svd2pac_as_ptr().add(304usize),
179 )
180 }
181 }
182
183 #[doc = "Non-Maskable Interrupt Status Register"]
184 #[inline(always)]
185 pub const fn nmisr(&self) -> &'static crate::common::Reg<self::Nmisr_SPEC, crate::common::R> {
186 unsafe {
187 crate::common::Reg::<self::Nmisr_SPEC, crate::common::R>::from_ptr(
188 self._svd2pac_as_ptr().add(320usize),
189 )
190 }
191 }
192
193 #[doc = "Wake Up Interrupt Enable Register 0"]
194 #[inline(always)]
195 pub const fn wupen0(
196 &self,
197 ) -> &'static crate::common::Reg<self::Wupen0_SPEC, crate::common::RW> {
198 unsafe {
199 crate::common::Reg::<self::Wupen0_SPEC, crate::common::RW>::from_ptr(
200 self._svd2pac_as_ptr().add(416usize),
201 )
202 }
203 }
204
205 #[doc = "Wake Up Interrupt Enable Register 1"]
206 #[inline(always)]
207 pub const fn wupen1(
208 &self,
209 ) -> &'static crate::common::Reg<self::Wupen1_SPEC, crate::common::RW> {
210 unsafe {
211 crate::common::Reg::<self::Wupen1_SPEC, crate::common::RW>::from_ptr(
212 self._svd2pac_as_ptr().add(420usize),
213 )
214 }
215 }
216
217 #[doc = "ICU Event Enable Register"]
218 #[inline(always)]
219 pub const fn ielen(&self) -> &'static crate::common::Reg<self::Ielen_SPEC, crate::common::RW> {
220 unsafe {
221 crate::common::Reg::<self::Ielen_SPEC, crate::common::RW>::from_ptr(
222 self._svd2pac_as_ptr().add(448usize),
223 )
224 }
225 }
226
227 #[doc = "SYS Event Link Setting Register"]
228 #[inline(always)]
229 pub const fn selsr0(
230 &self,
231 ) -> &'static crate::common::Reg<self::Selsr0_SPEC, crate::common::RW> {
232 unsafe {
233 crate::common::Reg::<self::Selsr0_SPEC, crate::common::RW>::from_ptr(
234 self._svd2pac_as_ptr().add(512usize),
235 )
236 }
237 }
238
239 #[doc = "ICU Event Link Setting Register %s"]
240 #[inline(always)]
241 pub const fn ielsr(
242 &self,
243 ) -> &'static crate::common::ClusterRegisterArray<
244 crate::common::Reg<self::Ielsr_SPEC, crate::common::RW>,
245 36,
246 0x4,
247 > {
248 unsafe {
249 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x380usize))
250 }
251 }
252 #[inline(always)]
253 pub const fn ielsr32(
254 &self,
255 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
256 unsafe {
257 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
258 self._svd2pac_as_ptr().add(0x380usize),
259 )
260 }
261 }
262 #[inline(always)]
263 pub const fn ielsr33(
264 &self,
265 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
266 unsafe {
267 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
268 self._svd2pac_as_ptr().add(0x384usize),
269 )
270 }
271 }
272 #[inline(always)]
273 pub const fn ielsr34(
274 &self,
275 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
276 unsafe {
277 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
278 self._svd2pac_as_ptr().add(0x388usize),
279 )
280 }
281 }
282 #[inline(always)]
283 pub const fn ielsr35(
284 &self,
285 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(0x38cusize),
289 )
290 }
291 }
292 #[inline(always)]
293 pub const fn ielsr36(
294 &self,
295 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
296 unsafe {
297 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
298 self._svd2pac_as_ptr().add(0x390usize),
299 )
300 }
301 }
302 #[inline(always)]
303 pub const fn ielsr37(
304 &self,
305 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
306 unsafe {
307 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
308 self._svd2pac_as_ptr().add(0x394usize),
309 )
310 }
311 }
312 #[inline(always)]
313 pub const fn ielsr38(
314 &self,
315 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
316 unsafe {
317 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
318 self._svd2pac_as_ptr().add(0x398usize),
319 )
320 }
321 }
322 #[inline(always)]
323 pub const fn ielsr39(
324 &self,
325 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
326 unsafe {
327 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
328 self._svd2pac_as_ptr().add(0x39cusize),
329 )
330 }
331 }
332 #[inline(always)]
333 pub const fn ielsr40(
334 &self,
335 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
336 unsafe {
337 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
338 self._svd2pac_as_ptr().add(0x3a0usize),
339 )
340 }
341 }
342 #[inline(always)]
343 pub const fn ielsr41(
344 &self,
345 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
346 unsafe {
347 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
348 self._svd2pac_as_ptr().add(0x3a4usize),
349 )
350 }
351 }
352 #[inline(always)]
353 pub const fn ielsr42(
354 &self,
355 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
356 unsafe {
357 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
358 self._svd2pac_as_ptr().add(0x3a8usize),
359 )
360 }
361 }
362 #[inline(always)]
363 pub const fn ielsr43(
364 &self,
365 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
366 unsafe {
367 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
368 self._svd2pac_as_ptr().add(0x3acusize),
369 )
370 }
371 }
372 #[inline(always)]
373 pub const fn ielsr44(
374 &self,
375 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
376 unsafe {
377 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
378 self._svd2pac_as_ptr().add(0x3b0usize),
379 )
380 }
381 }
382 #[inline(always)]
383 pub const fn ielsr45(
384 &self,
385 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
386 unsafe {
387 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
388 self._svd2pac_as_ptr().add(0x3b4usize),
389 )
390 }
391 }
392 #[inline(always)]
393 pub const fn ielsr46(
394 &self,
395 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(0x3b8usize),
399 )
400 }
401 }
402 #[inline(always)]
403 pub const fn ielsr47(
404 &self,
405 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
406 unsafe {
407 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
408 self._svd2pac_as_ptr().add(0x3bcusize),
409 )
410 }
411 }
412 #[inline(always)]
413 pub const fn ielsr48(
414 &self,
415 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
416 unsafe {
417 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
418 self._svd2pac_as_ptr().add(0x3c0usize),
419 )
420 }
421 }
422 #[inline(always)]
423 pub const fn ielsr49(
424 &self,
425 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
426 unsafe {
427 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
428 self._svd2pac_as_ptr().add(0x3c4usize),
429 )
430 }
431 }
432 #[inline(always)]
433 pub const fn ielsr50(
434 &self,
435 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
436 unsafe {
437 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
438 self._svd2pac_as_ptr().add(0x3c8usize),
439 )
440 }
441 }
442 #[inline(always)]
443 pub const fn ielsr51(
444 &self,
445 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
446 unsafe {
447 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
448 self._svd2pac_as_ptr().add(0x3ccusize),
449 )
450 }
451 }
452 #[inline(always)]
453 pub const fn ielsr52(
454 &self,
455 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
456 unsafe {
457 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
458 self._svd2pac_as_ptr().add(0x3d0usize),
459 )
460 }
461 }
462 #[inline(always)]
463 pub const fn ielsr53(
464 &self,
465 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
466 unsafe {
467 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
468 self._svd2pac_as_ptr().add(0x3d4usize),
469 )
470 }
471 }
472 #[inline(always)]
473 pub const fn ielsr54(
474 &self,
475 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
476 unsafe {
477 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
478 self._svd2pac_as_ptr().add(0x3d8usize),
479 )
480 }
481 }
482 #[inline(always)]
483 pub const fn ielsr55(
484 &self,
485 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
486 unsafe {
487 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
488 self._svd2pac_as_ptr().add(0x3dcusize),
489 )
490 }
491 }
492 #[inline(always)]
493 pub const fn ielsr56(
494 &self,
495 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
496 unsafe {
497 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
498 self._svd2pac_as_ptr().add(0x3e0usize),
499 )
500 }
501 }
502 #[inline(always)]
503 pub const fn ielsr57(
504 &self,
505 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
506 unsafe {
507 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
508 self._svd2pac_as_ptr().add(0x3e4usize),
509 )
510 }
511 }
512 #[inline(always)]
513 pub const fn ielsr58(
514 &self,
515 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
516 unsafe {
517 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
518 self._svd2pac_as_ptr().add(0x3e8usize),
519 )
520 }
521 }
522 #[inline(always)]
523 pub const fn ielsr59(
524 &self,
525 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
526 unsafe {
527 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
528 self._svd2pac_as_ptr().add(0x3ecusize),
529 )
530 }
531 }
532 #[inline(always)]
533 pub const fn ielsr60(
534 &self,
535 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
536 unsafe {
537 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
538 self._svd2pac_as_ptr().add(0x3f0usize),
539 )
540 }
541 }
542 #[inline(always)]
543 pub const fn ielsr61(
544 &self,
545 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
546 unsafe {
547 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
548 self._svd2pac_as_ptr().add(0x3f4usize),
549 )
550 }
551 }
552 #[inline(always)]
553 pub const fn ielsr62(
554 &self,
555 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
556 unsafe {
557 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
558 self._svd2pac_as_ptr().add(0x3f8usize),
559 )
560 }
561 }
562 #[inline(always)]
563 pub const fn ielsr63(
564 &self,
565 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
566 unsafe {
567 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
568 self._svd2pac_as_ptr().add(0x3fcusize),
569 )
570 }
571 }
572 #[inline(always)]
573 pub const fn ielsr64(
574 &self,
575 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
576 unsafe {
577 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
578 self._svd2pac_as_ptr().add(0x400usize),
579 )
580 }
581 }
582 #[inline(always)]
583 pub const fn ielsr65(
584 &self,
585 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
586 unsafe {
587 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
588 self._svd2pac_as_ptr().add(0x404usize),
589 )
590 }
591 }
592 #[inline(always)]
593 pub const fn ielsr66(
594 &self,
595 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
596 unsafe {
597 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
598 self._svd2pac_as_ptr().add(0x408usize),
599 )
600 }
601 }
602 #[inline(always)]
603 pub const fn ielsr67(
604 &self,
605 ) -> &'static crate::common::Reg<self::Ielsr_SPEC, crate::common::RW> {
606 unsafe {
607 crate::common::Reg::<self::Ielsr_SPEC, crate::common::RW>::from_ptr(
608 self._svd2pac_as_ptr().add(0x40cusize),
609 )
610 }
611 }
612}
613#[doc(hidden)]
614#[derive(Copy, Clone, Eq, PartialEq)]
615pub struct Irqcr_SPEC;
616impl crate::sealed::RegSpec for Irqcr_SPEC {
617 type DataType = u8;
618}
619
620#[doc = "IRQ Control Register %s"]
621pub type Irqcr = crate::RegValueT<Irqcr_SPEC>;
622
623impl Irqcr {
624 #[doc = "IRQi Detection Sense Select"]
625 #[inline(always)]
626 pub fn irqmd(
627 self,
628 ) -> crate::common::RegisterField<
629 0,
630 0x3,
631 1,
632 0,
633 irqcr::Irqmd,
634 irqcr::Irqmd,
635 Irqcr_SPEC,
636 crate::common::RW,
637 > {
638 crate::common::RegisterField::<
639 0,
640 0x3,
641 1,
642 0,
643 irqcr::Irqmd,
644 irqcr::Irqmd,
645 Irqcr_SPEC,
646 crate::common::RW,
647 >::from_register(self, 0)
648 }
649
650 #[doc = "IRQi Digital Filter Sampling Clock Select"]
651 #[inline(always)]
652 pub fn fclksel(
653 self,
654 ) -> crate::common::RegisterField<
655 4,
656 0x3,
657 1,
658 0,
659 irqcr::Fclksel,
660 irqcr::Fclksel,
661 Irqcr_SPEC,
662 crate::common::RW,
663 > {
664 crate::common::RegisterField::<
665 4,
666 0x3,
667 1,
668 0,
669 irqcr::Fclksel,
670 irqcr::Fclksel,
671 Irqcr_SPEC,
672 crate::common::RW,
673 >::from_register(self, 0)
674 }
675
676 #[doc = "IRQi Digital Filter Enable"]
677 #[inline(always)]
678 pub fn flten(
679 self,
680 ) -> crate::common::RegisterField<
681 7,
682 0x1,
683 1,
684 0,
685 irqcr::Flten,
686 irqcr::Flten,
687 Irqcr_SPEC,
688 crate::common::RW,
689 > {
690 crate::common::RegisterField::<
691 7,
692 0x1,
693 1,
694 0,
695 irqcr::Flten,
696 irqcr::Flten,
697 Irqcr_SPEC,
698 crate::common::RW,
699 >::from_register(self, 0)
700 }
701}
702impl ::core::default::Default for Irqcr {
703 #[inline(always)]
704 fn default() -> Irqcr {
705 <crate::RegValueT<Irqcr_SPEC> as RegisterValue<_>>::new(0)
706 }
707}
708pub mod irqcr {
709
710 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
711 pub struct Irqmd_SPEC;
712 pub type Irqmd = crate::EnumBitfieldStruct<u8, Irqmd_SPEC>;
713 impl Irqmd {
714 #[doc = "Falling edge"]
715 pub const _00: Self = Self::new(0);
716
717 #[doc = "Rising edge"]
718 pub const _01: Self = Self::new(1);
719
720 #[doc = "Rising and falling edges"]
721 pub const _10: Self = Self::new(2);
722
723 #[doc = "Low level"]
724 pub const _11: Self = Self::new(3);
725 }
726 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
727 pub struct Fclksel_SPEC;
728 pub type Fclksel = crate::EnumBitfieldStruct<u8, Fclksel_SPEC>;
729 impl Fclksel {
730 #[doc = "PCLKB"]
731 pub const _00: Self = Self::new(0);
732
733 #[doc = "PCLKB/8"]
734 pub const _01: Self = Self::new(1);
735
736 #[doc = "PCLKB/32"]
737 pub const _10: Self = Self::new(2);
738
739 #[doc = "PCLKB/64"]
740 pub const _11: Self = Self::new(3);
741 }
742 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
743 pub struct Flten_SPEC;
744 pub type Flten = crate::EnumBitfieldStruct<u8, Flten_SPEC>;
745 impl Flten {
746 #[doc = "Digital filter is disabled"]
747 pub const _0: Self = Self::new(0);
748
749 #[doc = "Digital filter is enabled"]
750 pub const _1: Self = Self::new(1);
751 }
752}
753#[doc(hidden)]
754#[derive(Copy, Clone, Eq, PartialEq)]
755pub struct Nmicr_SPEC;
756impl crate::sealed::RegSpec for Nmicr_SPEC {
757 type DataType = u8;
758}
759
760#[doc = "NMI Pin Interrupt Control Register"]
761pub type Nmicr = crate::RegValueT<Nmicr_SPEC>;
762
763impl Nmicr {
764 #[doc = "NMI Detection Set"]
765 #[inline(always)]
766 pub fn nmimd(
767 self,
768 ) -> crate::common::RegisterField<
769 0,
770 0x1,
771 1,
772 0,
773 nmicr::Nmimd,
774 nmicr::Nmimd,
775 Nmicr_SPEC,
776 crate::common::RW,
777 > {
778 crate::common::RegisterField::<
779 0,
780 0x1,
781 1,
782 0,
783 nmicr::Nmimd,
784 nmicr::Nmimd,
785 Nmicr_SPEC,
786 crate::common::RW,
787 >::from_register(self, 0)
788 }
789
790 #[doc = "NMI Digital Filter Sampling Clock Select"]
791 #[inline(always)]
792 pub fn nfclksel(
793 self,
794 ) -> crate::common::RegisterField<
795 4,
796 0x3,
797 1,
798 0,
799 nmicr::Nfclksel,
800 nmicr::Nfclksel,
801 Nmicr_SPEC,
802 crate::common::RW,
803 > {
804 crate::common::RegisterField::<
805 4,
806 0x3,
807 1,
808 0,
809 nmicr::Nfclksel,
810 nmicr::Nfclksel,
811 Nmicr_SPEC,
812 crate::common::RW,
813 >::from_register(self, 0)
814 }
815
816 #[doc = "NMI Digital Filter Enable"]
817 #[inline(always)]
818 pub fn nflten(
819 self,
820 ) -> crate::common::RegisterField<
821 7,
822 0x1,
823 1,
824 0,
825 nmicr::Nflten,
826 nmicr::Nflten,
827 Nmicr_SPEC,
828 crate::common::RW,
829 > {
830 crate::common::RegisterField::<
831 7,
832 0x1,
833 1,
834 0,
835 nmicr::Nflten,
836 nmicr::Nflten,
837 Nmicr_SPEC,
838 crate::common::RW,
839 >::from_register(self, 0)
840 }
841}
842impl ::core::default::Default for Nmicr {
843 #[inline(always)]
844 fn default() -> Nmicr {
845 <crate::RegValueT<Nmicr_SPEC> as RegisterValue<_>>::new(0)
846 }
847}
848pub mod nmicr {
849
850 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
851 pub struct Nmimd_SPEC;
852 pub type Nmimd = crate::EnumBitfieldStruct<u8, Nmimd_SPEC>;
853 impl Nmimd {
854 #[doc = "Falling edge"]
855 pub const _0: Self = Self::new(0);
856
857 #[doc = "Rising edge"]
858 pub const _1: Self = Self::new(1);
859 }
860 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
861 pub struct Nfclksel_SPEC;
862 pub type Nfclksel = crate::EnumBitfieldStruct<u8, Nfclksel_SPEC>;
863 impl Nfclksel {
864 #[doc = "PCLKB"]
865 pub const _00: Self = Self::new(0);
866
867 #[doc = "PCLKB/8"]
868 pub const _01: Self = Self::new(1);
869
870 #[doc = "PCLKB/32"]
871 pub const _10: Self = Self::new(2);
872
873 #[doc = "PCLKB/64"]
874 pub const _11: Self = Self::new(3);
875 }
876 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
877 pub struct Nflten_SPEC;
878 pub type Nflten = crate::EnumBitfieldStruct<u8, Nflten_SPEC>;
879 impl Nflten {
880 #[doc = "Disabled"]
881 pub const _0: Self = Self::new(0);
882
883 #[doc = "Enabled"]
884 pub const _1: Self = Self::new(1);
885 }
886}
887#[doc(hidden)]
888#[derive(Copy, Clone, Eq, PartialEq)]
889pub struct Nmier_SPEC;
890impl crate::sealed::RegSpec for Nmier_SPEC {
891 type DataType = u16;
892}
893
894#[doc = "Non-Maskable Interrupt Enable Register"]
895pub type Nmier = crate::RegValueT<Nmier_SPEC>;
896
897impl Nmier {
898 #[doc = "IWDT Underflow/Refresh Error Interrupt Enable"]
899 #[inline(always)]
900 pub fn iwdten(
901 self,
902 ) -> crate::common::RegisterField<
903 0,
904 0x1,
905 1,
906 0,
907 nmier::Iwdten,
908 nmier::Iwdten,
909 Nmier_SPEC,
910 crate::common::RW,
911 > {
912 crate::common::RegisterField::<
913 0,
914 0x1,
915 1,
916 0,
917 nmier::Iwdten,
918 nmier::Iwdten,
919 Nmier_SPEC,
920 crate::common::RW,
921 >::from_register(self, 0)
922 }
923
924 #[doc = "WDT Underflow/Refresh Error Interrupt Enable"]
925 #[inline(always)]
926 pub fn wdten(
927 self,
928 ) -> crate::common::RegisterField<
929 1,
930 0x1,
931 1,
932 0,
933 nmier::Wdten,
934 nmier::Wdten,
935 Nmier_SPEC,
936 crate::common::RW,
937 > {
938 crate::common::RegisterField::<
939 1,
940 0x1,
941 1,
942 0,
943 nmier::Wdten,
944 nmier::Wdten,
945 Nmier_SPEC,
946 crate::common::RW,
947 >::from_register(self, 0)
948 }
949
950 #[doc = "Voltage monitor 1 Interrupt Enable"]
951 #[inline(always)]
952 pub fn lvd1en(
953 self,
954 ) -> crate::common::RegisterField<
955 2,
956 0x1,
957 1,
958 0,
959 nmier::Lvd1En,
960 nmier::Lvd1En,
961 Nmier_SPEC,
962 crate::common::RW,
963 > {
964 crate::common::RegisterField::<
965 2,
966 0x1,
967 1,
968 0,
969 nmier::Lvd1En,
970 nmier::Lvd1En,
971 Nmier_SPEC,
972 crate::common::RW,
973 >::from_register(self, 0)
974 }
975
976 #[doc = "Voltage monitor 2 Interrupt Enable"]
977 #[inline(always)]
978 pub fn lvd2en(
979 self,
980 ) -> crate::common::RegisterField<
981 3,
982 0x1,
983 1,
984 0,
985 nmier::Lvd2En,
986 nmier::Lvd2En,
987 Nmier_SPEC,
988 crate::common::RW,
989 > {
990 crate::common::RegisterField::<
991 3,
992 0x1,
993 1,
994 0,
995 nmier::Lvd2En,
996 nmier::Lvd2En,
997 Nmier_SPEC,
998 crate::common::RW,
999 >::from_register(self, 0)
1000 }
1001
1002 #[doc = "Main Clock Oscillation Stop Detection Interrupt Enable"]
1003 #[inline(always)]
1004 pub fn osten(
1005 self,
1006 ) -> crate::common::RegisterField<
1007 6,
1008 0x1,
1009 1,
1010 0,
1011 nmier::Osten,
1012 nmier::Osten,
1013 Nmier_SPEC,
1014 crate::common::RW,
1015 > {
1016 crate::common::RegisterField::<
1017 6,
1018 0x1,
1019 1,
1020 0,
1021 nmier::Osten,
1022 nmier::Osten,
1023 Nmier_SPEC,
1024 crate::common::RW,
1025 >::from_register(self, 0)
1026 }
1027
1028 #[doc = "NMI Pin Interrupt Enable"]
1029 #[inline(always)]
1030 pub fn nmien(
1031 self,
1032 ) -> crate::common::RegisterField<
1033 7,
1034 0x1,
1035 1,
1036 0,
1037 nmier::Nmien,
1038 nmier::Nmien,
1039 Nmier_SPEC,
1040 crate::common::RW,
1041 > {
1042 crate::common::RegisterField::<
1043 7,
1044 0x1,
1045 1,
1046 0,
1047 nmier::Nmien,
1048 nmier::Nmien,
1049 Nmier_SPEC,
1050 crate::common::RW,
1051 >::from_register(self, 0)
1052 }
1053
1054 #[doc = "SRAM Parity Error Interrupt Enable"]
1055 #[inline(always)]
1056 pub fn rpeen(
1057 self,
1058 ) -> crate::common::RegisterField<
1059 8,
1060 0x1,
1061 1,
1062 0,
1063 nmier::Rpeen,
1064 nmier::Rpeen,
1065 Nmier_SPEC,
1066 crate::common::RW,
1067 > {
1068 crate::common::RegisterField::<
1069 8,
1070 0x1,
1071 1,
1072 0,
1073 nmier::Rpeen,
1074 nmier::Rpeen,
1075 Nmier_SPEC,
1076 crate::common::RW,
1077 >::from_register(self, 0)
1078 }
1079
1080 #[doc = "SRAM ECC Error Interrupt Enable"]
1081 #[inline(always)]
1082 pub fn reccen(
1083 self,
1084 ) -> crate::common::RegisterField<
1085 9,
1086 0x1,
1087 1,
1088 0,
1089 nmier::Reccen,
1090 nmier::Reccen,
1091 Nmier_SPEC,
1092 crate::common::RW,
1093 > {
1094 crate::common::RegisterField::<
1095 9,
1096 0x1,
1097 1,
1098 0,
1099 nmier::Reccen,
1100 nmier::Reccen,
1101 Nmier_SPEC,
1102 crate::common::RW,
1103 >::from_register(self, 0)
1104 }
1105
1106 #[doc = "Bus Slave MPU Error Interrupt Enable"]
1107 #[inline(always)]
1108 pub fn bussen(
1109 self,
1110 ) -> crate::common::RegisterField<
1111 10,
1112 0x1,
1113 1,
1114 0,
1115 nmier::Bussen,
1116 nmier::Bussen,
1117 Nmier_SPEC,
1118 crate::common::RW,
1119 > {
1120 crate::common::RegisterField::<
1121 10,
1122 0x1,
1123 1,
1124 0,
1125 nmier::Bussen,
1126 nmier::Bussen,
1127 Nmier_SPEC,
1128 crate::common::RW,
1129 >::from_register(self, 0)
1130 }
1131
1132 #[doc = "Bus Master MPU Error Interrupt Enable"]
1133 #[inline(always)]
1134 pub fn busmen(
1135 self,
1136 ) -> crate::common::RegisterField<
1137 11,
1138 0x1,
1139 1,
1140 0,
1141 nmier::Busmen,
1142 nmier::Busmen,
1143 Nmier_SPEC,
1144 crate::common::RW,
1145 > {
1146 crate::common::RegisterField::<
1147 11,
1148 0x1,
1149 1,
1150 0,
1151 nmier::Busmen,
1152 nmier::Busmen,
1153 Nmier_SPEC,
1154 crate::common::RW,
1155 >::from_register(self, 0)
1156 }
1157
1158 #[doc = "CPU Stack Pointer Monitor Interrupt Enable"]
1159 #[inline(always)]
1160 pub fn speen(
1161 self,
1162 ) -> crate::common::RegisterField<
1163 12,
1164 0x1,
1165 1,
1166 0,
1167 nmier::Speen,
1168 nmier::Speen,
1169 Nmier_SPEC,
1170 crate::common::RW,
1171 > {
1172 crate::common::RegisterField::<
1173 12,
1174 0x1,
1175 1,
1176 0,
1177 nmier::Speen,
1178 nmier::Speen,
1179 Nmier_SPEC,
1180 crate::common::RW,
1181 >::from_register(self, 0)
1182 }
1183}
1184impl ::core::default::Default for Nmier {
1185 #[inline(always)]
1186 fn default() -> Nmier {
1187 <crate::RegValueT<Nmier_SPEC> as RegisterValue<_>>::new(0)
1188 }
1189}
1190pub mod nmier {
1191
1192 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1193 pub struct Iwdten_SPEC;
1194 pub type Iwdten = crate::EnumBitfieldStruct<u8, Iwdten_SPEC>;
1195 impl Iwdten {
1196 #[doc = "Disabled"]
1197 pub const _0: Self = Self::new(0);
1198
1199 #[doc = "Enabled"]
1200 pub const _1: Self = Self::new(1);
1201 }
1202 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1203 pub struct Wdten_SPEC;
1204 pub type Wdten = crate::EnumBitfieldStruct<u8, Wdten_SPEC>;
1205 impl Wdten {
1206 #[doc = "Disabled"]
1207 pub const _0: Self = Self::new(0);
1208
1209 #[doc = "Enabled"]
1210 pub const _1: Self = Self::new(1);
1211 }
1212 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1213 pub struct Lvd1En_SPEC;
1214 pub type Lvd1En = crate::EnumBitfieldStruct<u8, Lvd1En_SPEC>;
1215 impl Lvd1En {
1216 #[doc = "Disabled"]
1217 pub const _0: Self = Self::new(0);
1218
1219 #[doc = "Enabled"]
1220 pub const _1: Self = Self::new(1);
1221 }
1222 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1223 pub struct Lvd2En_SPEC;
1224 pub type Lvd2En = crate::EnumBitfieldStruct<u8, Lvd2En_SPEC>;
1225 impl Lvd2En {
1226 #[doc = "Disabled"]
1227 pub const _0: Self = Self::new(0);
1228
1229 #[doc = "Enabled"]
1230 pub const _1: Self = Self::new(1);
1231 }
1232 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1233 pub struct Osten_SPEC;
1234 pub type Osten = crate::EnumBitfieldStruct<u8, Osten_SPEC>;
1235 impl Osten {
1236 #[doc = "Disabled"]
1237 pub const _0: Self = Self::new(0);
1238
1239 #[doc = "Enabled"]
1240 pub const _1: Self = Self::new(1);
1241 }
1242 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1243 pub struct Nmien_SPEC;
1244 pub type Nmien = crate::EnumBitfieldStruct<u8, Nmien_SPEC>;
1245 impl Nmien {
1246 #[doc = "Disabled"]
1247 pub const _0: Self = Self::new(0);
1248
1249 #[doc = "Enabled"]
1250 pub const _1: Self = Self::new(1);
1251 }
1252 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1253 pub struct Rpeen_SPEC;
1254 pub type Rpeen = crate::EnumBitfieldStruct<u8, Rpeen_SPEC>;
1255 impl Rpeen {
1256 #[doc = "Disabled"]
1257 pub const _0: Self = Self::new(0);
1258
1259 #[doc = "Enabled"]
1260 pub const _1: Self = Self::new(1);
1261 }
1262 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1263 pub struct Reccen_SPEC;
1264 pub type Reccen = crate::EnumBitfieldStruct<u8, Reccen_SPEC>;
1265 impl Reccen {
1266 #[doc = "Disabled"]
1267 pub const _0: Self = Self::new(0);
1268
1269 #[doc = "Enabled"]
1270 pub const _1: Self = Self::new(1);
1271 }
1272 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1273 pub struct Bussen_SPEC;
1274 pub type Bussen = crate::EnumBitfieldStruct<u8, Bussen_SPEC>;
1275 impl Bussen {
1276 #[doc = "Disabled"]
1277 pub const _0: Self = Self::new(0);
1278
1279 #[doc = "Enabled"]
1280 pub const _1: Self = Self::new(1);
1281 }
1282 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1283 pub struct Busmen_SPEC;
1284 pub type Busmen = crate::EnumBitfieldStruct<u8, Busmen_SPEC>;
1285 impl Busmen {
1286 #[doc = "Disabled"]
1287 pub const _0: Self = Self::new(0);
1288
1289 #[doc = "Enabled"]
1290 pub const _1: Self = Self::new(1);
1291 }
1292 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1293 pub struct Speen_SPEC;
1294 pub type Speen = crate::EnumBitfieldStruct<u8, Speen_SPEC>;
1295 impl Speen {
1296 #[doc = "Disabled"]
1297 pub const _0: Self = Self::new(0);
1298
1299 #[doc = "Enabled"]
1300 pub const _1: Self = Self::new(1);
1301 }
1302}
1303#[doc(hidden)]
1304#[derive(Copy, Clone, Eq, PartialEq)]
1305pub struct Nmiclr_SPEC;
1306impl crate::sealed::RegSpec for Nmiclr_SPEC {
1307 type DataType = u16;
1308}
1309
1310#[doc = "Non-Maskable Interrupt Status Clear Register"]
1311pub type Nmiclr = crate::RegValueT<Nmiclr_SPEC>;
1312
1313impl Nmiclr {
1314 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1315 #[inline(always)]
1316 pub fn iwdtclr(
1317 self,
1318 ) -> crate::common::RegisterField<
1319 0,
1320 0x1,
1321 1,
1322 0,
1323 nmiclr::Iwdtclr,
1324 nmiclr::Iwdtclr,
1325 Nmiclr_SPEC,
1326 crate::common::RW,
1327 > {
1328 crate::common::RegisterField::<
1329 0,
1330 0x1,
1331 1,
1332 0,
1333 nmiclr::Iwdtclr,
1334 nmiclr::Iwdtclr,
1335 Nmiclr_SPEC,
1336 crate::common::RW,
1337 >::from_register(self, 0)
1338 }
1339
1340 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag Clear"]
1341 #[inline(always)]
1342 pub fn wdtclr(
1343 self,
1344 ) -> crate::common::RegisterField<
1345 1,
1346 0x1,
1347 1,
1348 0,
1349 nmiclr::Wdtclr,
1350 nmiclr::Wdtclr,
1351 Nmiclr_SPEC,
1352 crate::common::RW,
1353 > {
1354 crate::common::RegisterField::<
1355 1,
1356 0x1,
1357 1,
1358 0,
1359 nmiclr::Wdtclr,
1360 nmiclr::Wdtclr,
1361 Nmiclr_SPEC,
1362 crate::common::RW,
1363 >::from_register(self, 0)
1364 }
1365
1366 #[doc = "Voltage Monitor 1 Interrupt Status Flag Clear"]
1367 #[inline(always)]
1368 pub fn lvd1clr(
1369 self,
1370 ) -> crate::common::RegisterField<
1371 2,
1372 0x1,
1373 1,
1374 0,
1375 nmiclr::Lvd1Clr,
1376 nmiclr::Lvd1Clr,
1377 Nmiclr_SPEC,
1378 crate::common::RW,
1379 > {
1380 crate::common::RegisterField::<
1381 2,
1382 0x1,
1383 1,
1384 0,
1385 nmiclr::Lvd1Clr,
1386 nmiclr::Lvd1Clr,
1387 Nmiclr_SPEC,
1388 crate::common::RW,
1389 >::from_register(self, 0)
1390 }
1391
1392 #[doc = "Voltage Monitor 2 Interrupt Status Flag Clear"]
1393 #[inline(always)]
1394 pub fn lvd2clr(
1395 self,
1396 ) -> crate::common::RegisterField<
1397 3,
1398 0x1,
1399 1,
1400 0,
1401 nmiclr::Lvd2Clr,
1402 nmiclr::Lvd2Clr,
1403 Nmiclr_SPEC,
1404 crate::common::RW,
1405 > {
1406 crate::common::RegisterField::<
1407 3,
1408 0x1,
1409 1,
1410 0,
1411 nmiclr::Lvd2Clr,
1412 nmiclr::Lvd2Clr,
1413 Nmiclr_SPEC,
1414 crate::common::RW,
1415 >::from_register(self, 0)
1416 }
1417
1418 #[doc = "Oscillation Stop Detection Interrupt Status Flag Clear"]
1419 #[inline(always)]
1420 pub fn ostclr(
1421 self,
1422 ) -> crate::common::RegisterField<
1423 6,
1424 0x1,
1425 1,
1426 0,
1427 nmiclr::Ostclr,
1428 nmiclr::Ostclr,
1429 Nmiclr_SPEC,
1430 crate::common::RW,
1431 > {
1432 crate::common::RegisterField::<
1433 6,
1434 0x1,
1435 1,
1436 0,
1437 nmiclr::Ostclr,
1438 nmiclr::Ostclr,
1439 Nmiclr_SPEC,
1440 crate::common::RW,
1441 >::from_register(self, 0)
1442 }
1443
1444 #[doc = "NMI Pin Interrupt Status Flag Clear"]
1445 #[inline(always)]
1446 pub fn nmiclr(
1447 self,
1448 ) -> crate::common::RegisterField<
1449 7,
1450 0x1,
1451 1,
1452 0,
1453 nmiclr::Nmiclr,
1454 nmiclr::Nmiclr,
1455 Nmiclr_SPEC,
1456 crate::common::RW,
1457 > {
1458 crate::common::RegisterField::<
1459 7,
1460 0x1,
1461 1,
1462 0,
1463 nmiclr::Nmiclr,
1464 nmiclr::Nmiclr,
1465 Nmiclr_SPEC,
1466 crate::common::RW,
1467 >::from_register(self, 0)
1468 }
1469
1470 #[doc = "SRAM Parity Error Interrupt Status Flag Clear"]
1471 #[inline(always)]
1472 pub fn rpeclr(
1473 self,
1474 ) -> crate::common::RegisterField<
1475 8,
1476 0x1,
1477 1,
1478 0,
1479 nmiclr::Rpeclr,
1480 nmiclr::Rpeclr,
1481 Nmiclr_SPEC,
1482 crate::common::RW,
1483 > {
1484 crate::common::RegisterField::<
1485 8,
1486 0x1,
1487 1,
1488 0,
1489 nmiclr::Rpeclr,
1490 nmiclr::Rpeclr,
1491 Nmiclr_SPEC,
1492 crate::common::RW,
1493 >::from_register(self, 0)
1494 }
1495
1496 #[doc = "SRAM ECC Error Interrupt Status Flag Clear"]
1497 #[inline(always)]
1498 pub fn reccclr(
1499 self,
1500 ) -> crate::common::RegisterField<
1501 9,
1502 0x1,
1503 1,
1504 0,
1505 nmiclr::Reccclr,
1506 nmiclr::Reccclr,
1507 Nmiclr_SPEC,
1508 crate::common::RW,
1509 > {
1510 crate::common::RegisterField::<
1511 9,
1512 0x1,
1513 1,
1514 0,
1515 nmiclr::Reccclr,
1516 nmiclr::Reccclr,
1517 Nmiclr_SPEC,
1518 crate::common::RW,
1519 >::from_register(self, 0)
1520 }
1521
1522 #[doc = "Bus Slave MPU Error Interrupt Status Flag Clear"]
1523 #[inline(always)]
1524 pub fn bussclr(
1525 self,
1526 ) -> crate::common::RegisterField<
1527 10,
1528 0x1,
1529 1,
1530 0,
1531 nmiclr::Bussclr,
1532 nmiclr::Bussclr,
1533 Nmiclr_SPEC,
1534 crate::common::RW,
1535 > {
1536 crate::common::RegisterField::<
1537 10,
1538 0x1,
1539 1,
1540 0,
1541 nmiclr::Bussclr,
1542 nmiclr::Bussclr,
1543 Nmiclr_SPEC,
1544 crate::common::RW,
1545 >::from_register(self, 0)
1546 }
1547
1548 #[doc = "Bus Master MPU Error Interrupt Status Flag Clear"]
1549 #[inline(always)]
1550 pub fn busmclr(
1551 self,
1552 ) -> crate::common::RegisterField<
1553 11,
1554 0x1,
1555 1,
1556 0,
1557 nmiclr::Busmclr,
1558 nmiclr::Busmclr,
1559 Nmiclr_SPEC,
1560 crate::common::RW,
1561 > {
1562 crate::common::RegisterField::<
1563 11,
1564 0x1,
1565 1,
1566 0,
1567 nmiclr::Busmclr,
1568 nmiclr::Busmclr,
1569 Nmiclr_SPEC,
1570 crate::common::RW,
1571 >::from_register(self, 0)
1572 }
1573
1574 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag Clear"]
1575 #[inline(always)]
1576 pub fn speclr(
1577 self,
1578 ) -> crate::common::RegisterField<
1579 12,
1580 0x1,
1581 1,
1582 0,
1583 nmiclr::Speclr,
1584 nmiclr::Speclr,
1585 Nmiclr_SPEC,
1586 crate::common::RW,
1587 > {
1588 crate::common::RegisterField::<
1589 12,
1590 0x1,
1591 1,
1592 0,
1593 nmiclr::Speclr,
1594 nmiclr::Speclr,
1595 Nmiclr_SPEC,
1596 crate::common::RW,
1597 >::from_register(self, 0)
1598 }
1599}
1600impl ::core::default::Default for Nmiclr {
1601 #[inline(always)]
1602 fn default() -> Nmiclr {
1603 <crate::RegValueT<Nmiclr_SPEC> as RegisterValue<_>>::new(0)
1604 }
1605}
1606pub mod nmiclr {
1607
1608 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1609 pub struct Iwdtclr_SPEC;
1610 pub type Iwdtclr = crate::EnumBitfieldStruct<u8, Iwdtclr_SPEC>;
1611 impl Iwdtclr {
1612 #[doc = "No effect"]
1613 pub const _0: Self = Self::new(0);
1614
1615 #[doc = "Clear the NMISR.IWDTST flag"]
1616 pub const _1: Self = Self::new(1);
1617 }
1618 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1619 pub struct Wdtclr_SPEC;
1620 pub type Wdtclr = crate::EnumBitfieldStruct<u8, Wdtclr_SPEC>;
1621 impl Wdtclr {
1622 #[doc = "No effect"]
1623 pub const _0: Self = Self::new(0);
1624
1625 #[doc = "Clear the NMISR.WDTST flag"]
1626 pub const _1: Self = Self::new(1);
1627 }
1628 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1629 pub struct Lvd1Clr_SPEC;
1630 pub type Lvd1Clr = crate::EnumBitfieldStruct<u8, Lvd1Clr_SPEC>;
1631 impl Lvd1Clr {
1632 #[doc = "No effect"]
1633 pub const _0: Self = Self::new(0);
1634
1635 #[doc = "Clear the NMISR.LVD1ST flag"]
1636 pub const _1: Self = Self::new(1);
1637 }
1638 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1639 pub struct Lvd2Clr_SPEC;
1640 pub type Lvd2Clr = crate::EnumBitfieldStruct<u8, Lvd2Clr_SPEC>;
1641 impl Lvd2Clr {
1642 #[doc = "No effect"]
1643 pub const _0: Self = Self::new(0);
1644
1645 #[doc = "Clear the NMISR.LVD2ST flag"]
1646 pub const _1: Self = Self::new(1);
1647 }
1648 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1649 pub struct Ostclr_SPEC;
1650 pub type Ostclr = crate::EnumBitfieldStruct<u8, Ostclr_SPEC>;
1651 impl Ostclr {
1652 #[doc = "No effect"]
1653 pub const _0: Self = Self::new(0);
1654
1655 #[doc = "Clear the NMISR.OSTST flag"]
1656 pub const _1: Self = Self::new(1);
1657 }
1658 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1659 pub struct Nmiclr_SPEC;
1660 pub type Nmiclr = crate::EnumBitfieldStruct<u8, Nmiclr_SPEC>;
1661 impl Nmiclr {
1662 #[doc = "No effect"]
1663 pub const _0: Self = Self::new(0);
1664
1665 #[doc = "Clear the NMISR.NMIST flag"]
1666 pub const _1: Self = Self::new(1);
1667 }
1668 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1669 pub struct Rpeclr_SPEC;
1670 pub type Rpeclr = crate::EnumBitfieldStruct<u8, Rpeclr_SPEC>;
1671 impl Rpeclr {
1672 #[doc = "No effect"]
1673 pub const _0: Self = Self::new(0);
1674
1675 #[doc = "Clear the NMISR.RPEST flag"]
1676 pub const _1: Self = Self::new(1);
1677 }
1678 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1679 pub struct Reccclr_SPEC;
1680 pub type Reccclr = crate::EnumBitfieldStruct<u8, Reccclr_SPEC>;
1681 impl Reccclr {
1682 #[doc = "No effect"]
1683 pub const _0: Self = Self::new(0);
1684
1685 #[doc = "Clear the NMISR.RECCST flag"]
1686 pub const _1: Self = Self::new(1);
1687 }
1688 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1689 pub struct Bussclr_SPEC;
1690 pub type Bussclr = crate::EnumBitfieldStruct<u8, Bussclr_SPEC>;
1691 impl Bussclr {
1692 #[doc = "No effect"]
1693 pub const _0: Self = Self::new(0);
1694
1695 #[doc = "Clear the NMISR.BUSSST flag"]
1696 pub const _1: Self = Self::new(1);
1697 }
1698 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1699 pub struct Busmclr_SPEC;
1700 pub type Busmclr = crate::EnumBitfieldStruct<u8, Busmclr_SPEC>;
1701 impl Busmclr {
1702 #[doc = "No effect"]
1703 pub const _0: Self = Self::new(0);
1704
1705 #[doc = "Clear the NMISR.BUSMST flag"]
1706 pub const _1: Self = Self::new(1);
1707 }
1708 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1709 pub struct Speclr_SPEC;
1710 pub type Speclr = crate::EnumBitfieldStruct<u8, Speclr_SPEC>;
1711 impl Speclr {
1712 #[doc = "No effect"]
1713 pub const _0: Self = Self::new(0);
1714
1715 #[doc = "Clear the NMISR.SPEST flag"]
1716 pub const _1: Self = Self::new(1);
1717 }
1718}
1719#[doc(hidden)]
1720#[derive(Copy, Clone, Eq, PartialEq)]
1721pub struct Nmisr_SPEC;
1722impl crate::sealed::RegSpec for Nmisr_SPEC {
1723 type DataType = u16;
1724}
1725
1726#[doc = "Non-Maskable Interrupt Status Register"]
1727pub type Nmisr = crate::RegValueT<Nmisr_SPEC>;
1728
1729impl Nmisr {
1730 #[doc = "IWDT Underflow/Refresh Error Interrupt Status Flag"]
1731 #[inline(always)]
1732 pub fn iwdtst(
1733 self,
1734 ) -> crate::common::RegisterField<
1735 0,
1736 0x1,
1737 1,
1738 0,
1739 nmisr::Iwdtst,
1740 nmisr::Iwdtst,
1741 Nmisr_SPEC,
1742 crate::common::R,
1743 > {
1744 crate::common::RegisterField::<
1745 0,
1746 0x1,
1747 1,
1748 0,
1749 nmisr::Iwdtst,
1750 nmisr::Iwdtst,
1751 Nmisr_SPEC,
1752 crate::common::R,
1753 >::from_register(self, 0)
1754 }
1755
1756 #[doc = "WDT Underflow/Refresh Error Interrupt Status Flag"]
1757 #[inline(always)]
1758 pub fn wdtst(
1759 self,
1760 ) -> crate::common::RegisterField<
1761 1,
1762 0x1,
1763 1,
1764 0,
1765 nmisr::Wdtst,
1766 nmisr::Wdtst,
1767 Nmisr_SPEC,
1768 crate::common::R,
1769 > {
1770 crate::common::RegisterField::<
1771 1,
1772 0x1,
1773 1,
1774 0,
1775 nmisr::Wdtst,
1776 nmisr::Wdtst,
1777 Nmisr_SPEC,
1778 crate::common::R,
1779 >::from_register(self, 0)
1780 }
1781
1782 #[doc = "Voltage Monitor 1 Interrupt Status Flag"]
1783 #[inline(always)]
1784 pub fn lvd1st(
1785 self,
1786 ) -> crate::common::RegisterField<
1787 2,
1788 0x1,
1789 1,
1790 0,
1791 nmisr::Lvd1St,
1792 nmisr::Lvd1St,
1793 Nmisr_SPEC,
1794 crate::common::R,
1795 > {
1796 crate::common::RegisterField::<
1797 2,
1798 0x1,
1799 1,
1800 0,
1801 nmisr::Lvd1St,
1802 nmisr::Lvd1St,
1803 Nmisr_SPEC,
1804 crate::common::R,
1805 >::from_register(self, 0)
1806 }
1807
1808 #[doc = "Voltage Monitor 2 Interrupt Status Flag"]
1809 #[inline(always)]
1810 pub fn lvd2st(
1811 self,
1812 ) -> crate::common::RegisterField<
1813 3,
1814 0x1,
1815 1,
1816 0,
1817 nmisr::Lvd2St,
1818 nmisr::Lvd2St,
1819 Nmisr_SPEC,
1820 crate::common::R,
1821 > {
1822 crate::common::RegisterField::<
1823 3,
1824 0x1,
1825 1,
1826 0,
1827 nmisr::Lvd2St,
1828 nmisr::Lvd2St,
1829 Nmisr_SPEC,
1830 crate::common::R,
1831 >::from_register(self, 0)
1832 }
1833
1834 #[doc = "Main Clock Oscillation Stop Detection Interrupt Status Flag"]
1835 #[inline(always)]
1836 pub fn ostst(
1837 self,
1838 ) -> crate::common::RegisterField<
1839 6,
1840 0x1,
1841 1,
1842 0,
1843 nmisr::Ostst,
1844 nmisr::Ostst,
1845 Nmisr_SPEC,
1846 crate::common::R,
1847 > {
1848 crate::common::RegisterField::<
1849 6,
1850 0x1,
1851 1,
1852 0,
1853 nmisr::Ostst,
1854 nmisr::Ostst,
1855 Nmisr_SPEC,
1856 crate::common::R,
1857 >::from_register(self, 0)
1858 }
1859
1860 #[doc = "NMI Pin Interrupt Status Flag"]
1861 #[inline(always)]
1862 pub fn nmist(
1863 self,
1864 ) -> crate::common::RegisterField<
1865 7,
1866 0x1,
1867 1,
1868 0,
1869 nmisr::Nmist,
1870 nmisr::Nmist,
1871 Nmisr_SPEC,
1872 crate::common::R,
1873 > {
1874 crate::common::RegisterField::<
1875 7,
1876 0x1,
1877 1,
1878 0,
1879 nmisr::Nmist,
1880 nmisr::Nmist,
1881 Nmisr_SPEC,
1882 crate::common::R,
1883 >::from_register(self, 0)
1884 }
1885
1886 #[doc = "SRAM Parity Error Interrupt Status Flag"]
1887 #[inline(always)]
1888 pub fn rpest(
1889 self,
1890 ) -> crate::common::RegisterField<
1891 8,
1892 0x1,
1893 1,
1894 0,
1895 nmisr::Rpest,
1896 nmisr::Rpest,
1897 Nmisr_SPEC,
1898 crate::common::R,
1899 > {
1900 crate::common::RegisterField::<
1901 8,
1902 0x1,
1903 1,
1904 0,
1905 nmisr::Rpest,
1906 nmisr::Rpest,
1907 Nmisr_SPEC,
1908 crate::common::R,
1909 >::from_register(self, 0)
1910 }
1911
1912 #[doc = "SRAM ECC Error Interrupt Status Flag"]
1913 #[inline(always)]
1914 pub fn reccst(
1915 self,
1916 ) -> crate::common::RegisterField<
1917 9,
1918 0x1,
1919 1,
1920 0,
1921 nmisr::Reccst,
1922 nmisr::Reccst,
1923 Nmisr_SPEC,
1924 crate::common::R,
1925 > {
1926 crate::common::RegisterField::<
1927 9,
1928 0x1,
1929 1,
1930 0,
1931 nmisr::Reccst,
1932 nmisr::Reccst,
1933 Nmisr_SPEC,
1934 crate::common::R,
1935 >::from_register(self, 0)
1936 }
1937
1938 #[doc = "Bus Slave MPU Error Interrupt Status Flag"]
1939 #[inline(always)]
1940 pub fn bussst(
1941 self,
1942 ) -> crate::common::RegisterField<
1943 10,
1944 0x1,
1945 1,
1946 0,
1947 nmisr::Bussst,
1948 nmisr::Bussst,
1949 Nmisr_SPEC,
1950 crate::common::R,
1951 > {
1952 crate::common::RegisterField::<
1953 10,
1954 0x1,
1955 1,
1956 0,
1957 nmisr::Bussst,
1958 nmisr::Bussst,
1959 Nmisr_SPEC,
1960 crate::common::R,
1961 >::from_register(self, 0)
1962 }
1963
1964 #[doc = "Bus Master MPU Error Interrupt Status Flag"]
1965 #[inline(always)]
1966 pub fn busmst(
1967 self,
1968 ) -> crate::common::RegisterField<
1969 11,
1970 0x1,
1971 1,
1972 0,
1973 nmisr::Busmst,
1974 nmisr::Busmst,
1975 Nmisr_SPEC,
1976 crate::common::R,
1977 > {
1978 crate::common::RegisterField::<
1979 11,
1980 0x1,
1981 1,
1982 0,
1983 nmisr::Busmst,
1984 nmisr::Busmst,
1985 Nmisr_SPEC,
1986 crate::common::R,
1987 >::from_register(self, 0)
1988 }
1989
1990 #[doc = "CPU Stack Pointer Monitor Interrupt Status Flag"]
1991 #[inline(always)]
1992 pub fn spest(
1993 self,
1994 ) -> crate::common::RegisterField<
1995 12,
1996 0x1,
1997 1,
1998 0,
1999 nmisr::Spest,
2000 nmisr::Spest,
2001 Nmisr_SPEC,
2002 crate::common::R,
2003 > {
2004 crate::common::RegisterField::<
2005 12,
2006 0x1,
2007 1,
2008 0,
2009 nmisr::Spest,
2010 nmisr::Spest,
2011 Nmisr_SPEC,
2012 crate::common::R,
2013 >::from_register(self, 0)
2014 }
2015}
2016impl ::core::default::Default for Nmisr {
2017 #[inline(always)]
2018 fn default() -> Nmisr {
2019 <crate::RegValueT<Nmisr_SPEC> as RegisterValue<_>>::new(0)
2020 }
2021}
2022pub mod nmisr {
2023
2024 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2025 pub struct Iwdtst_SPEC;
2026 pub type Iwdtst = crate::EnumBitfieldStruct<u8, Iwdtst_SPEC>;
2027 impl Iwdtst {
2028 #[doc = "Interrupt not requested"]
2029 pub const _0: Self = Self::new(0);
2030
2031 #[doc = "Interrupt requested"]
2032 pub const _1: Self = Self::new(1);
2033 }
2034 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2035 pub struct Wdtst_SPEC;
2036 pub type Wdtst = crate::EnumBitfieldStruct<u8, Wdtst_SPEC>;
2037 impl Wdtst {
2038 #[doc = "Interrupt not requested"]
2039 pub const _0: Self = Self::new(0);
2040
2041 #[doc = "Interrupt requested"]
2042 pub const _1: Self = Self::new(1);
2043 }
2044 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2045 pub struct Lvd1St_SPEC;
2046 pub type Lvd1St = crate::EnumBitfieldStruct<u8, Lvd1St_SPEC>;
2047 impl Lvd1St {
2048 #[doc = "Interrupt not requested"]
2049 pub const _0: Self = Self::new(0);
2050
2051 #[doc = "Interrupt requested"]
2052 pub const _1: Self = Self::new(1);
2053 }
2054 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2055 pub struct Lvd2St_SPEC;
2056 pub type Lvd2St = crate::EnumBitfieldStruct<u8, Lvd2St_SPEC>;
2057 impl Lvd2St {
2058 #[doc = "Interrupt not requested"]
2059 pub const _0: Self = Self::new(0);
2060
2061 #[doc = "Interrupt requested"]
2062 pub const _1: Self = Self::new(1);
2063 }
2064 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2065 pub struct Ostst_SPEC;
2066 pub type Ostst = crate::EnumBitfieldStruct<u8, Ostst_SPEC>;
2067 impl Ostst {
2068 #[doc = "Interrupt not requested for main clock oscillation stop"]
2069 pub const _0: Self = Self::new(0);
2070
2071 #[doc = "Interrupt requested for main clock oscillation stop"]
2072 pub const _1: Self = Self::new(1);
2073 }
2074 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2075 pub struct Nmist_SPEC;
2076 pub type Nmist = crate::EnumBitfieldStruct<u8, Nmist_SPEC>;
2077 impl Nmist {
2078 #[doc = "Interrupt not requested"]
2079 pub const _0: Self = Self::new(0);
2080
2081 #[doc = "Interrupt requested"]
2082 pub const _1: Self = Self::new(1);
2083 }
2084 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2085 pub struct Rpest_SPEC;
2086 pub type Rpest = crate::EnumBitfieldStruct<u8, Rpest_SPEC>;
2087 impl Rpest {
2088 #[doc = "Interrupt not requested"]
2089 pub const _0: Self = Self::new(0);
2090
2091 #[doc = "Interrupt requested"]
2092 pub const _1: Self = Self::new(1);
2093 }
2094 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2095 pub struct Reccst_SPEC;
2096 pub type Reccst = crate::EnumBitfieldStruct<u8, Reccst_SPEC>;
2097 impl Reccst {
2098 #[doc = "Interrupt not requested"]
2099 pub const _0: Self = Self::new(0);
2100
2101 #[doc = "Interrupt requested"]
2102 pub const _1: Self = Self::new(1);
2103 }
2104 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2105 pub struct Bussst_SPEC;
2106 pub type Bussst = crate::EnumBitfieldStruct<u8, Bussst_SPEC>;
2107 impl Bussst {
2108 #[doc = "Interrupt not requested"]
2109 pub const _0: Self = Self::new(0);
2110
2111 #[doc = "Interrupt requested"]
2112 pub const _1: Self = Self::new(1);
2113 }
2114 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2115 pub struct Busmst_SPEC;
2116 pub type Busmst = crate::EnumBitfieldStruct<u8, Busmst_SPEC>;
2117 impl Busmst {
2118 #[doc = "Interrupt not requested"]
2119 pub const _0: Self = Self::new(0);
2120
2121 #[doc = "Interrupt requested"]
2122 pub const _1: Self = Self::new(1);
2123 }
2124 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2125 pub struct Spest_SPEC;
2126 pub type Spest = crate::EnumBitfieldStruct<u8, Spest_SPEC>;
2127 impl Spest {
2128 #[doc = "Interrupt not requested"]
2129 pub const _0: Self = Self::new(0);
2130
2131 #[doc = "Interrupt requested"]
2132 pub const _1: Self = Self::new(1);
2133 }
2134}
2135#[doc(hidden)]
2136#[derive(Copy, Clone, Eq, PartialEq)]
2137pub struct Wupen0_SPEC;
2138impl crate::sealed::RegSpec for Wupen0_SPEC {
2139 type DataType = u32;
2140}
2141
2142#[doc = "Wake Up Interrupt Enable Register 0"]
2143pub type Wupen0 = crate::RegValueT<Wupen0_SPEC>;
2144
2145impl Wupen0 {
2146 #[doc = "IRQ Interrupt Software Standby/Snooze Mode Returns Enable"]
2147 #[inline(always)]
2148 pub fn irqwupen(
2149 self,
2150 ) -> crate::common::RegisterField<
2151 0,
2152 0xfff,
2153 1,
2154 0,
2155 wupen0::Irqwupen,
2156 wupen0::Irqwupen,
2157 Wupen0_SPEC,
2158 crate::common::RW,
2159 > {
2160 crate::common::RegisterField::<
2161 0,
2162 0xfff,
2163 1,
2164 0,
2165 wupen0::Irqwupen,
2166 wupen0::Irqwupen,
2167 Wupen0_SPEC,
2168 crate::common::RW,
2169 >::from_register(self, 0)
2170 }
2171
2172 #[doc = "IWDT Interrupt Software Standby/Snooze Mode Returns Enable"]
2173 #[inline(always)]
2174 pub fn iwdtwupen(
2175 self,
2176 ) -> crate::common::RegisterField<
2177 16,
2178 0x1,
2179 1,
2180 0,
2181 wupen0::Iwdtwupen,
2182 wupen0::Iwdtwupen,
2183 Wupen0_SPEC,
2184 crate::common::RW,
2185 > {
2186 crate::common::RegisterField::<
2187 16,
2188 0x1,
2189 1,
2190 0,
2191 wupen0::Iwdtwupen,
2192 wupen0::Iwdtwupen,
2193 Wupen0_SPEC,
2194 crate::common::RW,
2195 >::from_register(self, 0)
2196 }
2197
2198 #[doc = "LVD1 Interrupt Software Standby/Snooze Mode Returns Enable"]
2199 #[inline(always)]
2200 pub fn lvd1wupen(
2201 self,
2202 ) -> crate::common::RegisterField<
2203 18,
2204 0x1,
2205 1,
2206 0,
2207 wupen0::Lvd1Wupen,
2208 wupen0::Lvd1Wupen,
2209 Wupen0_SPEC,
2210 crate::common::RW,
2211 > {
2212 crate::common::RegisterField::<
2213 18,
2214 0x1,
2215 1,
2216 0,
2217 wupen0::Lvd1Wupen,
2218 wupen0::Lvd1Wupen,
2219 Wupen0_SPEC,
2220 crate::common::RW,
2221 >::from_register(self, 0)
2222 }
2223
2224 #[doc = "LVD2 Interrupt Software Standby/Snooze Mode Returns Enable"]
2225 #[inline(always)]
2226 pub fn lvd2wupen(
2227 self,
2228 ) -> crate::common::RegisterField<
2229 19,
2230 0x1,
2231 1,
2232 0,
2233 wupen0::Lvd2Wupen,
2234 wupen0::Lvd2Wupen,
2235 Wupen0_SPEC,
2236 crate::common::RW,
2237 > {
2238 crate::common::RegisterField::<
2239 19,
2240 0x1,
2241 1,
2242 0,
2243 wupen0::Lvd2Wupen,
2244 wupen0::Lvd2Wupen,
2245 Wupen0_SPEC,
2246 crate::common::RW,
2247 >::from_register(self, 0)
2248 }
2249
2250 #[doc = "LVDVBAT Interrupt Software Standby/Snooze Mode Returns Enable"]
2251 #[inline(always)]
2252 pub fn lvdvbatwupen(
2253 self,
2254 ) -> crate::common::RegisterField<
2255 20,
2256 0x1,
2257 1,
2258 0,
2259 wupen0::Lvdvbatwupen,
2260 wupen0::Lvdvbatwupen,
2261 Wupen0_SPEC,
2262 crate::common::RW,
2263 > {
2264 crate::common::RegisterField::<
2265 20,
2266 0x1,
2267 1,
2268 0,
2269 wupen0::Lvdvbatwupen,
2270 wupen0::Lvdvbatwupen,
2271 Wupen0_SPEC,
2272 crate::common::RW,
2273 >::from_register(self, 0)
2274 }
2275
2276 #[doc = "LVDVRTC Interrupt Software Standby/Snooze Mode Returns Enable"]
2277 #[inline(always)]
2278 pub fn lvdvrtcwupen(
2279 self,
2280 ) -> crate::common::RegisterField<
2281 21,
2282 0x1,
2283 1,
2284 0,
2285 wupen0::Lvdvrtcwupen,
2286 wupen0::Lvdvrtcwupen,
2287 Wupen0_SPEC,
2288 crate::common::RW,
2289 > {
2290 crate::common::RegisterField::<
2291 21,
2292 0x1,
2293 1,
2294 0,
2295 wupen0::Lvdvrtcwupen,
2296 wupen0::Lvdvrtcwupen,
2297 Wupen0_SPEC,
2298 crate::common::RW,
2299 >::from_register(self, 0)
2300 }
2301
2302 #[doc = "LVDEXLVD Interrupt Software Standby/Snooze Mode Returns Enable"]
2303 #[inline(always)]
2304 pub fn lvdexlvdwupen(
2305 self,
2306 ) -> crate::common::RegisterField<
2307 22,
2308 0x1,
2309 1,
2310 0,
2311 wupen0::Lvdexlvdwupen,
2312 wupen0::Lvdexlvdwupen,
2313 Wupen0_SPEC,
2314 crate::common::RW,
2315 > {
2316 crate::common::RegisterField::<
2317 22,
2318 0x1,
2319 1,
2320 0,
2321 wupen0::Lvdexlvdwupen,
2322 wupen0::Lvdexlvdwupen,
2323 Wupen0_SPEC,
2324 crate::common::RW,
2325 >::from_register(self, 0)
2326 }
2327
2328 #[doc = "RTC Alarm Interrupt 1 Software Standby/Snooze Mode Returns Enable"]
2329 #[inline(always)]
2330 pub fn rtcalm1wupen(
2331 self,
2332 ) -> crate::common::RegisterField<
2333 23,
2334 0x1,
2335 1,
2336 0,
2337 wupen0::Rtcalm1Wupen,
2338 wupen0::Rtcalm1Wupen,
2339 Wupen0_SPEC,
2340 crate::common::RW,
2341 > {
2342 crate::common::RegisterField::<
2343 23,
2344 0x1,
2345 1,
2346 0,
2347 wupen0::Rtcalm1Wupen,
2348 wupen0::Rtcalm1Wupen,
2349 Wupen0_SPEC,
2350 crate::common::RW,
2351 >::from_register(self, 0)
2352 }
2353
2354 #[doc = "RTC Alarm Interrupt 0 Software Standby/Snooze Mode Returns Enable"]
2355 #[inline(always)]
2356 pub fn rtcalm0wupen(
2357 self,
2358 ) -> crate::common::RegisterField<
2359 24,
2360 0x1,
2361 1,
2362 0,
2363 wupen0::Rtcalm0Wupen,
2364 wupen0::Rtcalm0Wupen,
2365 Wupen0_SPEC,
2366 crate::common::RW,
2367 > {
2368 crate::common::RegisterField::<
2369 24,
2370 0x1,
2371 1,
2372 0,
2373 wupen0::Rtcalm0Wupen,
2374 wupen0::Rtcalm0Wupen,
2375 Wupen0_SPEC,
2376 crate::common::RW,
2377 >::from_register(self, 0)
2378 }
2379
2380 #[doc = "RTC Period Interrupt Software Standby/Snooze Mode Returns Enable"]
2381 #[inline(always)]
2382 pub fn rtcprdwupen(
2383 self,
2384 ) -> crate::common::RegisterField<
2385 25,
2386 0x1,
2387 1,
2388 0,
2389 wupen0::Rtcprdwupen,
2390 wupen0::Rtcprdwupen,
2391 Wupen0_SPEC,
2392 crate::common::RW,
2393 > {
2394 crate::common::RegisterField::<
2395 25,
2396 0x1,
2397 1,
2398 0,
2399 wupen0::Rtcprdwupen,
2400 wupen0::Rtcprdwupen,
2401 Wupen0_SPEC,
2402 crate::common::RW,
2403 >::from_register(self, 0)
2404 }
2405
2406 #[doc = "AGTW0 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2407 #[inline(always)]
2408 pub fn agtw0udwupen(
2409 self,
2410 ) -> crate::common::RegisterField<
2411 27,
2412 0x1,
2413 1,
2414 0,
2415 wupen0::Agtw0Udwupen,
2416 wupen0::Agtw0Udwupen,
2417 Wupen0_SPEC,
2418 crate::common::RW,
2419 > {
2420 crate::common::RegisterField::<
2421 27,
2422 0x1,
2423 1,
2424 0,
2425 wupen0::Agtw0Udwupen,
2426 wupen0::Agtw0Udwupen,
2427 Wupen0_SPEC,
2428 crate::common::RW,
2429 >::from_register(self, 0)
2430 }
2431
2432 #[doc = "AGTW1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2433 #[inline(always)]
2434 pub fn agtw1udwupen(
2435 self,
2436 ) -> crate::common::RegisterField<
2437 28,
2438 0x1,
2439 1,
2440 0,
2441 wupen0::Agtw1Udwupen,
2442 wupen0::Agtw1Udwupen,
2443 Wupen0_SPEC,
2444 crate::common::RW,
2445 > {
2446 crate::common::RegisterField::<
2447 28,
2448 0x1,
2449 1,
2450 0,
2451 wupen0::Agtw1Udwupen,
2452 wupen0::Agtw1Udwupen,
2453 Wupen0_SPEC,
2454 crate::common::RW,
2455 >::from_register(self, 0)
2456 }
2457
2458 #[doc = "AGTW1 Compare Match A Interrupt Software Standby/Snooze Mode Returns Enable"]
2459 #[inline(always)]
2460 pub fn agtw1cawupen(
2461 self,
2462 ) -> crate::common::RegisterField<
2463 29,
2464 0x1,
2465 1,
2466 0,
2467 wupen0::Agtw1Cawupen,
2468 wupen0::Agtw1Cawupen,
2469 Wupen0_SPEC,
2470 crate::common::RW,
2471 > {
2472 crate::common::RegisterField::<
2473 29,
2474 0x1,
2475 1,
2476 0,
2477 wupen0::Agtw1Cawupen,
2478 wupen0::Agtw1Cawupen,
2479 Wupen0_SPEC,
2480 crate::common::RW,
2481 >::from_register(self, 0)
2482 }
2483
2484 #[doc = "AGTW1 Compare Match B Interrupt Software Standby/Snooze Mode Returns Enable"]
2485 #[inline(always)]
2486 pub fn agtw1cbwupen(
2487 self,
2488 ) -> crate::common::RegisterField<
2489 30,
2490 0x1,
2491 1,
2492 0,
2493 wupen0::Agtw1Cbwupen,
2494 wupen0::Agtw1Cbwupen,
2495 Wupen0_SPEC,
2496 crate::common::RW,
2497 > {
2498 crate::common::RegisterField::<
2499 30,
2500 0x1,
2501 1,
2502 0,
2503 wupen0::Agtw1Cbwupen,
2504 wupen0::Agtw1Cbwupen,
2505 Wupen0_SPEC,
2506 crate::common::RW,
2507 >::from_register(self, 0)
2508 }
2509
2510 #[doc = "IIC0 Address Match Interrupt Software Standby/Snooze Mode Returns Enable"]
2511 #[inline(always)]
2512 pub fn iic0wupen(
2513 self,
2514 ) -> crate::common::RegisterField<
2515 31,
2516 0x1,
2517 1,
2518 0,
2519 wupen0::Iic0Wupen,
2520 wupen0::Iic0Wupen,
2521 Wupen0_SPEC,
2522 crate::common::RW,
2523 > {
2524 crate::common::RegisterField::<
2525 31,
2526 0x1,
2527 1,
2528 0,
2529 wupen0::Iic0Wupen,
2530 wupen0::Iic0Wupen,
2531 Wupen0_SPEC,
2532 crate::common::RW,
2533 >::from_register(self, 0)
2534 }
2535}
2536impl ::core::default::Default for Wupen0 {
2537 #[inline(always)]
2538 fn default() -> Wupen0 {
2539 <crate::RegValueT<Wupen0_SPEC> as RegisterValue<_>>::new(0)
2540 }
2541}
2542pub mod wupen0 {
2543
2544 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2545 pub struct Irqwupen_SPEC;
2546 pub type Irqwupen = crate::EnumBitfieldStruct<u8, Irqwupen_SPEC>;
2547 impl Irqwupen {
2548 #[doc = "Software Standby/Snooze mode returns by IRQn interrupt disabled"]
2549 pub const _0: Self = Self::new(0);
2550
2551 #[doc = "Software Standby/Snooze mode returns by IRQn interrupt enabled"]
2552 pub const _1: Self = Self::new(1);
2553 }
2554 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2555 pub struct Iwdtwupen_SPEC;
2556 pub type Iwdtwupen = crate::EnumBitfieldStruct<u8, Iwdtwupen_SPEC>;
2557 impl Iwdtwupen {
2558 #[doc = "Software Standby/Snooze mode returns by IWDT interrupt disabled"]
2559 pub const _0: Self = Self::new(0);
2560
2561 #[doc = "Software Standby/Snooze mode returns by IWDT interrupt enabled"]
2562 pub const _1: Self = Self::new(1);
2563 }
2564 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2565 pub struct Lvd1Wupen_SPEC;
2566 pub type Lvd1Wupen = crate::EnumBitfieldStruct<u8, Lvd1Wupen_SPEC>;
2567 impl Lvd1Wupen {
2568 #[doc = "Software Standby/Snooze mode returns by LVD1 interrupt disabled"]
2569 pub const _0: Self = Self::new(0);
2570
2571 #[doc = "Software Standby/Snooze mode returns by LVD1 interrupt enabled"]
2572 pub const _1: Self = Self::new(1);
2573 }
2574 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2575 pub struct Lvd2Wupen_SPEC;
2576 pub type Lvd2Wupen = crate::EnumBitfieldStruct<u8, Lvd2Wupen_SPEC>;
2577 impl Lvd2Wupen {
2578 #[doc = "Software Standby/Snooze mode returns by LVD2 interrupt disabled"]
2579 pub const _0: Self = Self::new(0);
2580
2581 #[doc = "Software Standby/Snooze mode returns by LVD2 interrupt enabled"]
2582 pub const _1: Self = Self::new(1);
2583 }
2584 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2585 pub struct Lvdvbatwupen_SPEC;
2586 pub type Lvdvbatwupen = crate::EnumBitfieldStruct<u8, Lvdvbatwupen_SPEC>;
2587 impl Lvdvbatwupen {
2588 #[doc = "Software Standby/Snooze mode returns by LVDVBAT interrupt disabled"]
2589 pub const _0: Self = Self::new(0);
2590
2591 #[doc = "Software Standby/Snooze mode returns by LVDVBAT interrupt enabled"]
2592 pub const _1: Self = Self::new(1);
2593 }
2594 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2595 pub struct Lvdvrtcwupen_SPEC;
2596 pub type Lvdvrtcwupen = crate::EnumBitfieldStruct<u8, Lvdvrtcwupen_SPEC>;
2597 impl Lvdvrtcwupen {
2598 #[doc = "Software Standby/Snooze mode returns by LVDVRTC interrupt disabled"]
2599 pub const _0: Self = Self::new(0);
2600
2601 #[doc = "Software Standby/Snooze mode returns by LVDVRTC interrupt enabled"]
2602 pub const _1: Self = Self::new(1);
2603 }
2604 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2605 pub struct Lvdexlvdwupen_SPEC;
2606 pub type Lvdexlvdwupen = crate::EnumBitfieldStruct<u8, Lvdexlvdwupen_SPEC>;
2607 impl Lvdexlvdwupen {
2608 #[doc = "Software Standby/Snooze mode returns by LVDEXLVD interrupt disabled"]
2609 pub const _0: Self = Self::new(0);
2610
2611 #[doc = "Software Standby/Snooze mode returns by LVDEXLVD interrupt enabled"]
2612 pub const _1: Self = Self::new(1);
2613 }
2614 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2615 pub struct Rtcalm1Wupen_SPEC;
2616 pub type Rtcalm1Wupen = crate::EnumBitfieldStruct<u8, Rtcalm1Wupen_SPEC>;
2617 impl Rtcalm1Wupen {
2618 #[doc = "Software Standby/Snooze mode returns by RTCALM1 interrupt disabled"]
2619 pub const _0: Self = Self::new(0);
2620
2621 #[doc = "Software Standby/Snooze mode returns by RTCALM1 interrupt enabled"]
2622 pub const _1: Self = Self::new(1);
2623 }
2624 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2625 pub struct Rtcalm0Wupen_SPEC;
2626 pub type Rtcalm0Wupen = crate::EnumBitfieldStruct<u8, Rtcalm0Wupen_SPEC>;
2627 impl Rtcalm0Wupen {
2628 #[doc = "Software Standby/Snooze mode returns by RTC alarm interrupt disabled"]
2629 pub const _0: Self = Self::new(0);
2630
2631 #[doc = "Software Standby/Snooze mode returns by RTC alarm interrupt enabled"]
2632 pub const _1: Self = Self::new(1);
2633 }
2634 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2635 pub struct Rtcprdwupen_SPEC;
2636 pub type Rtcprdwupen = crate::EnumBitfieldStruct<u8, Rtcprdwupen_SPEC>;
2637 impl Rtcprdwupen {
2638 #[doc = "Software Standby/Snooze mode returns by RTC period interrupt disabled"]
2639 pub const _0: Self = Self::new(0);
2640
2641 #[doc = "Software Standby/Snooze mode returns by RTC period interrupt enabled"]
2642 pub const _1: Self = Self::new(1);
2643 }
2644 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2645 pub struct Agtw0Udwupen_SPEC;
2646 pub type Agtw0Udwupen = crate::EnumBitfieldStruct<u8, Agtw0Udwupen_SPEC>;
2647 impl Agtw0Udwupen {
2648 #[doc = "Software Standby/Snooze mode returns by AGTW0 underflow interrupt disabled"]
2649 pub const _0: Self = Self::new(0);
2650
2651 #[doc = "Software Standby/Snooze mode returns by AGTW0 underflow interrupt enabled"]
2652 pub const _1: Self = Self::new(1);
2653 }
2654 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2655 pub struct Agtw1Udwupen_SPEC;
2656 pub type Agtw1Udwupen = crate::EnumBitfieldStruct<u8, Agtw1Udwupen_SPEC>;
2657 impl Agtw1Udwupen {
2658 #[doc = "Software Standby/Snooze mode returns by AGTW1 underflow interrupt disabled"]
2659 pub const _0: Self = Self::new(0);
2660
2661 #[doc = "Software Standby/Snooze mode returns by AGTW1 underflow interrupt enabled"]
2662 pub const _1: Self = Self::new(1);
2663 }
2664 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2665 pub struct Agtw1Cawupen_SPEC;
2666 pub type Agtw1Cawupen = crate::EnumBitfieldStruct<u8, Agtw1Cawupen_SPEC>;
2667 impl Agtw1Cawupen {
2668 #[doc = "Software Standby/Snooze mode returns by AGTW1 compare match A interrupt disabled"]
2669 pub const _0: Self = Self::new(0);
2670
2671 #[doc = "Software Standby/Snooze mode returns by AGTW1 compare match A interrupt enabled"]
2672 pub const _1: Self = Self::new(1);
2673 }
2674 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2675 pub struct Agtw1Cbwupen_SPEC;
2676 pub type Agtw1Cbwupen = crate::EnumBitfieldStruct<u8, Agtw1Cbwupen_SPEC>;
2677 impl Agtw1Cbwupen {
2678 #[doc = "Software Standby/Snooze mode returns by AGTW1 compare match B interrupt disabled"]
2679 pub const _0: Self = Self::new(0);
2680
2681 #[doc = "Software Standby/Snooze mode returns by AGTW1 compare match B interrupt enabled"]
2682 pub const _1: Self = Self::new(1);
2683 }
2684 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2685 pub struct Iic0Wupen_SPEC;
2686 pub type Iic0Wupen = crate::EnumBitfieldStruct<u8, Iic0Wupen_SPEC>;
2687 impl Iic0Wupen {
2688 #[doc = "Software Standby/Snooze mode returns by IIC0 address match interrupt disabled"]
2689 pub const _0: Self = Self::new(0);
2690
2691 #[doc = "Software Standby/Snooze mode returns by IIC0 address match interrupt enabled"]
2692 pub const _1: Self = Self::new(1);
2693 }
2694}
2695#[doc(hidden)]
2696#[derive(Copy, Clone, Eq, PartialEq)]
2697pub struct Wupen1_SPEC;
2698impl crate::sealed::RegSpec for Wupen1_SPEC {
2699 type DataType = u32;
2700}
2701
2702#[doc = "Wake Up Interrupt Enable Register 1"]
2703pub type Wupen1 = crate::RegValueT<Wupen1_SPEC>;
2704
2705impl Wupen1 {
2706 #[doc = "AGT0 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2707 #[inline(always)]
2708 pub fn agt0udwupen(
2709 self,
2710 ) -> crate::common::RegisterField<
2711 0,
2712 0x1,
2713 1,
2714 0,
2715 wupen1::Agt0Udwupen,
2716 wupen1::Agt0Udwupen,
2717 Wupen1_SPEC,
2718 crate::common::RW,
2719 > {
2720 crate::common::RegisterField::<
2721 0,
2722 0x1,
2723 1,
2724 0,
2725 wupen1::Agt0Udwupen,
2726 wupen1::Agt0Udwupen,
2727 Wupen1_SPEC,
2728 crate::common::RW,
2729 >::from_register(self, 0)
2730 }
2731
2732 #[doc = "AGT1 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2733 #[inline(always)]
2734 pub fn agt1udwupen(
2735 self,
2736 ) -> crate::common::RegisterField<
2737 1,
2738 0x1,
2739 1,
2740 0,
2741 wupen1::Agt1Udwupen,
2742 wupen1::Agt1Udwupen,
2743 Wupen1_SPEC,
2744 crate::common::RW,
2745 > {
2746 crate::common::RegisterField::<
2747 1,
2748 0x1,
2749 1,
2750 0,
2751 wupen1::Agt1Udwupen,
2752 wupen1::Agt1Udwupen,
2753 Wupen1_SPEC,
2754 crate::common::RW,
2755 >::from_register(self, 0)
2756 }
2757
2758 #[doc = "AGT2 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2759 #[inline(always)]
2760 pub fn agt2udwupen(
2761 self,
2762 ) -> crate::common::RegisterField<
2763 2,
2764 0x1,
2765 1,
2766 0,
2767 wupen1::Agt2Udwupen,
2768 wupen1::Agt2Udwupen,
2769 Wupen1_SPEC,
2770 crate::common::RW,
2771 > {
2772 crate::common::RegisterField::<
2773 2,
2774 0x1,
2775 1,
2776 0,
2777 wupen1::Agt2Udwupen,
2778 wupen1::Agt2Udwupen,
2779 Wupen1_SPEC,
2780 crate::common::RW,
2781 >::from_register(self, 0)
2782 }
2783
2784 #[doc = "AGT3 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2785 #[inline(always)]
2786 pub fn agt3udwupen(
2787 self,
2788 ) -> crate::common::RegisterField<
2789 3,
2790 0x1,
2791 1,
2792 0,
2793 wupen1::Agt3Udwupen,
2794 wupen1::Agt3Udwupen,
2795 Wupen1_SPEC,
2796 crate::common::RW,
2797 > {
2798 crate::common::RegisterField::<
2799 3,
2800 0x1,
2801 1,
2802 0,
2803 wupen1::Agt3Udwupen,
2804 wupen1::Agt3Udwupen,
2805 Wupen1_SPEC,
2806 crate::common::RW,
2807 >::from_register(self, 0)
2808 }
2809
2810 #[doc = "AGT4 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2811 #[inline(always)]
2812 pub fn agt4udwupen(
2813 self,
2814 ) -> crate::common::RegisterField<
2815 4,
2816 0x1,
2817 1,
2818 0,
2819 wupen1::Agt4Udwupen,
2820 wupen1::Agt4Udwupen,
2821 Wupen1_SPEC,
2822 crate::common::RW,
2823 > {
2824 crate::common::RegisterField::<
2825 4,
2826 0x1,
2827 1,
2828 0,
2829 wupen1::Agt4Udwupen,
2830 wupen1::Agt4Udwupen,
2831 Wupen1_SPEC,
2832 crate::common::RW,
2833 >::from_register(self, 0)
2834 }
2835
2836 #[doc = "AGT5 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2837 #[inline(always)]
2838 pub fn agt5udwupen(
2839 self,
2840 ) -> crate::common::RegisterField<
2841 5,
2842 0x1,
2843 1,
2844 0,
2845 wupen1::Agt5Udwupen,
2846 wupen1::Agt5Udwupen,
2847 Wupen1_SPEC,
2848 crate::common::RW,
2849 > {
2850 crate::common::RegisterField::<
2851 5,
2852 0x1,
2853 1,
2854 0,
2855 wupen1::Agt5Udwupen,
2856 wupen1::Agt5Udwupen,
2857 Wupen1_SPEC,
2858 crate::common::RW,
2859 >::from_register(self, 0)
2860 }
2861
2862 #[doc = "AGT6 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2863 #[inline(always)]
2864 pub fn agt6udwupen(
2865 self,
2866 ) -> crate::common::RegisterField<
2867 6,
2868 0x1,
2869 1,
2870 0,
2871 wupen1::Agt6Udwupen,
2872 wupen1::Agt6Udwupen,
2873 Wupen1_SPEC,
2874 crate::common::RW,
2875 > {
2876 crate::common::RegisterField::<
2877 6,
2878 0x1,
2879 1,
2880 0,
2881 wupen1::Agt6Udwupen,
2882 wupen1::Agt6Udwupen,
2883 Wupen1_SPEC,
2884 crate::common::RW,
2885 >::from_register(self, 0)
2886 }
2887
2888 #[doc = "AGT7 Underflow Interrupt Software Standby/Snooze Mode Returns Enable"]
2889 #[inline(always)]
2890 pub fn agt7udwupen(
2891 self,
2892 ) -> crate::common::RegisterField<
2893 7,
2894 0x1,
2895 1,
2896 0,
2897 wupen1::Agt7Udwupen,
2898 wupen1::Agt7Udwupen,
2899 Wupen1_SPEC,
2900 crate::common::RW,
2901 > {
2902 crate::common::RegisterField::<
2903 7,
2904 0x1,
2905 1,
2906 0,
2907 wupen1::Agt7Udwupen,
2908 wupen1::Agt7Udwupen,
2909 Wupen1_SPEC,
2910 crate::common::RW,
2911 >::from_register(self, 0)
2912 }
2913
2914 #[doc = "SOSTD Interrupt Software Standby/Snooze Mode Returns Enable"]
2915 #[inline(always)]
2916 pub fn sostdwupen(
2917 self,
2918 ) -> crate::common::RegisterField<
2919 8,
2920 0x1,
2921 1,
2922 0,
2923 wupen1::Sostdwupen,
2924 wupen1::Sostdwupen,
2925 Wupen1_SPEC,
2926 crate::common::RW,
2927 > {
2928 crate::common::RegisterField::<
2929 8,
2930 0x1,
2931 1,
2932 0,
2933 wupen1::Sostdwupen,
2934 wupen1::Sostdwupen,
2935 Wupen1_SPEC,
2936 crate::common::RW,
2937 >::from_register(self, 0)
2938 }
2939}
2940impl ::core::default::Default for Wupen1 {
2941 #[inline(always)]
2942 fn default() -> Wupen1 {
2943 <crate::RegValueT<Wupen1_SPEC> as RegisterValue<_>>::new(0)
2944 }
2945}
2946pub mod wupen1 {
2947
2948 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2949 pub struct Agt0Udwupen_SPEC;
2950 pub type Agt0Udwupen = crate::EnumBitfieldStruct<u8, Agt0Udwupen_SPEC>;
2951 impl Agt0Udwupen {
2952 #[doc = "Software Standby/Snooze Mode returns by AGT0 underflow interrupt disabled"]
2953 pub const _0: Self = Self::new(0);
2954
2955 #[doc = "Software Standby/Snooze Mode returns by AGT0 underflow interrupt enabled"]
2956 pub const _1: Self = Self::new(1);
2957 }
2958 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2959 pub struct Agt1Udwupen_SPEC;
2960 pub type Agt1Udwupen = crate::EnumBitfieldStruct<u8, Agt1Udwupen_SPEC>;
2961 impl Agt1Udwupen {
2962 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt disabled"]
2963 pub const _0: Self = Self::new(0);
2964
2965 #[doc = "Software Standby/Snooze Mode returns by AGT1 underflow interrupt enabled"]
2966 pub const _1: Self = Self::new(1);
2967 }
2968 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2969 pub struct Agt2Udwupen_SPEC;
2970 pub type Agt2Udwupen = crate::EnumBitfieldStruct<u8, Agt2Udwupen_SPEC>;
2971 impl Agt2Udwupen {
2972 #[doc = "Software Standby/Snooze Mode returns by AGT2 underflow interrupt disabled"]
2973 pub const _0: Self = Self::new(0);
2974
2975 #[doc = "Software Standby/Snooze Mode returns by AGT2 underflow interrupt enabled"]
2976 pub const _1: Self = Self::new(1);
2977 }
2978 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2979 pub struct Agt3Udwupen_SPEC;
2980 pub type Agt3Udwupen = crate::EnumBitfieldStruct<u8, Agt3Udwupen_SPEC>;
2981 impl Agt3Udwupen {
2982 #[doc = "Software Standby/Snooze Mode returns by AGT3 underflow interrupt disabled"]
2983 pub const _0: Self = Self::new(0);
2984
2985 #[doc = "Software Standby/Snooze Mode returns by AGT3 underflow interrupt enabled"]
2986 pub const _1: Self = Self::new(1);
2987 }
2988 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2989 pub struct Agt4Udwupen_SPEC;
2990 pub type Agt4Udwupen = crate::EnumBitfieldStruct<u8, Agt4Udwupen_SPEC>;
2991 impl Agt4Udwupen {
2992 #[doc = "Software Standby/Snooze Mode returns by AGT4 underflow interrupt disabled"]
2993 pub const _0: Self = Self::new(0);
2994
2995 #[doc = "Software Standby/Snooze Mode returns by AGT4 underflow interrupt enabled"]
2996 pub const _1: Self = Self::new(1);
2997 }
2998 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2999 pub struct Agt5Udwupen_SPEC;
3000 pub type Agt5Udwupen = crate::EnumBitfieldStruct<u8, Agt5Udwupen_SPEC>;
3001 impl Agt5Udwupen {
3002 #[doc = "Software Standby/Snooze Mode returns by AGT5 underflow interrupt disabled"]
3003 pub const _0: Self = Self::new(0);
3004
3005 #[doc = "Software Standby/Snooze Mode returns by AGT5 underflow interrupt enabled"]
3006 pub const _1: Self = Self::new(1);
3007 }
3008 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3009 pub struct Agt6Udwupen_SPEC;
3010 pub type Agt6Udwupen = crate::EnumBitfieldStruct<u8, Agt6Udwupen_SPEC>;
3011 impl Agt6Udwupen {
3012 #[doc = "Software Standby/Snooze Mode returns by AGT6 underflow interrupt disabled"]
3013 pub const _0: Self = Self::new(0);
3014
3015 #[doc = "Software Standby/Snooze Mode returns by AGT6 underflow interrupt enabled"]
3016 pub const _1: Self = Self::new(1);
3017 }
3018 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3019 pub struct Agt7Udwupen_SPEC;
3020 pub type Agt7Udwupen = crate::EnumBitfieldStruct<u8, Agt7Udwupen_SPEC>;
3021 impl Agt7Udwupen {
3022 #[doc = "Software Standby/Snooze Mode returns by AGT7 underflow interrupt disabled"]
3023 pub const _0: Self = Self::new(0);
3024
3025 #[doc = "Software Standby/Snooze Mode returns by AGT7 underflow interrupt enabled"]
3026 pub const _1: Self = Self::new(1);
3027 }
3028 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3029 pub struct Sostdwupen_SPEC;
3030 pub type Sostdwupen = crate::EnumBitfieldStruct<u8, Sostdwupen_SPEC>;
3031 impl Sostdwupen {
3032 #[doc = "Software Standby/Snooze Mode returns by SOSTD interrupt disabled"]
3033 pub const _0: Self = Self::new(0);
3034
3035 #[doc = "Software Standby/Snooze Mode returns by SOSTD interrupt enabled"]
3036 pub const _1: Self = Self::new(1);
3037 }
3038}
3039#[doc(hidden)]
3040#[derive(Copy, Clone, Eq, PartialEq)]
3041pub struct Ielen_SPEC;
3042impl crate::sealed::RegSpec for Ielen_SPEC {
3043 type DataType = u8;
3044}
3045
3046#[doc = "ICU Event Enable Register"]
3047pub type Ielen = crate::RegValueT<Ielen_SPEC>;
3048
3049impl Ielen {
3050 #[doc = "RTCALM0, RTCALM1, and RTCPRD Interrupts Enable (when LPOPTEN bit = 1)"]
3051 #[inline(always)]
3052 pub fn rtcinten(
3053 self,
3054 ) -> crate::common::RegisterField<
3055 0,
3056 0x1,
3057 1,
3058 0,
3059 ielen::Rtcinten,
3060 ielen::Rtcinten,
3061 Ielen_SPEC,
3062 crate::common::RW,
3063 > {
3064 crate::common::RegisterField::<
3065 0,
3066 0x1,
3067 1,
3068 0,
3069 ielen::Rtcinten,
3070 ielen::Rtcinten,
3071 Ielen_SPEC,
3072 crate::common::RW,
3073 >::from_register(self, 0)
3074 }
3075
3076 #[doc = "Parts Asynchronous Interrupts Enable except RTC (when LPOPTEN bit = 1)"]
3077 #[inline(always)]
3078 pub fn ielen(
3079 self,
3080 ) -> crate::common::RegisterField<
3081 1,
3082 0x1,
3083 1,
3084 0,
3085 ielen::Ielen,
3086 ielen::Ielen,
3087 Ielen_SPEC,
3088 crate::common::RW,
3089 > {
3090 crate::common::RegisterField::<
3091 1,
3092 0x1,
3093 1,
3094 0,
3095 ielen::Ielen,
3096 ielen::Ielen,
3097 Ielen_SPEC,
3098 crate::common::RW,
3099 >::from_register(self, 0)
3100 }
3101}
3102impl ::core::default::Default for Ielen {
3103 #[inline(always)]
3104 fn default() -> Ielen {
3105 <crate::RegValueT<Ielen_SPEC> as RegisterValue<_>>::new(0)
3106 }
3107}
3108pub mod ielen {
3109
3110 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3111 pub struct Rtcinten_SPEC;
3112 pub type Rtcinten = crate::EnumBitfieldStruct<u8, Rtcinten_SPEC>;
3113 impl Rtcinten {
3114 #[doc = "Disabled"]
3115 pub const _0: Self = Self::new(0);
3116
3117 #[doc = "Enabled"]
3118 pub const _1: Self = Self::new(1);
3119 }
3120 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3121 pub struct Ielen_SPEC;
3122 pub type Ielen = crate::EnumBitfieldStruct<u8, Ielen_SPEC>;
3123 impl Ielen {
3124 #[doc = "Disabled"]
3125 pub const _0: Self = Self::new(0);
3126
3127 #[doc = "Enabled"]
3128 pub const _1: Self = Self::new(1);
3129 }
3130}
3131#[doc(hidden)]
3132#[derive(Copy, Clone, Eq, PartialEq)]
3133pub struct Selsr0_SPEC;
3134impl crate::sealed::RegSpec for Selsr0_SPEC {
3135 type DataType = u16;
3136}
3137
3138#[doc = "SYS Event Link Setting Register"]
3139pub type Selsr0 = crate::RegValueT<Selsr0_SPEC>;
3140
3141impl NoBitfieldReg<Selsr0_SPEC> for Selsr0 {}
3142impl ::core::default::Default for Selsr0 {
3143 #[inline(always)]
3144 fn default() -> Selsr0 {
3145 <crate::RegValueT<Selsr0_SPEC> as RegisterValue<_>>::new(0)
3146 }
3147}
3148
3149#[doc(hidden)]
3150#[derive(Copy, Clone, Eq, PartialEq)]
3151pub struct Ielsr_SPEC;
3152impl crate::sealed::RegSpec for Ielsr_SPEC {
3153 type DataType = u32;
3154}
3155
3156#[doc = "ICU Event Link Setting Register %s"]
3157pub type Ielsr = crate::RegValueT<Ielsr_SPEC>;
3158
3159impl NoBitfieldReg<Ielsr_SPEC> for Ielsr {}
3160impl ::core::default::Default for Ielsr {
3161 #[inline(always)]
3162 fn default() -> Ielsr {
3163 <crate::RegValueT<Ielsr_SPEC> as RegisterValue<_>>::new(0)
3164 }
3165}