ra2a2_pac/
gpt_ops.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.02, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:00 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Output Phase Switching Controller"]
28unsafe impl ::core::marker::Send for super::GptOps {}
29unsafe impl ::core::marker::Sync for super::GptOps {}
30impl super::GptOps {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Output Phase Switching Control Register"]
38    #[inline(always)]
39    pub const fn opscr(&self) -> &'static crate::common::Reg<self::Opscr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Opscr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46}
47#[doc(hidden)]
48#[derive(Copy, Clone, Eq, PartialEq)]
49pub struct Opscr_SPEC;
50impl crate::sealed::RegSpec for Opscr_SPEC {
51    type DataType = u32;
52}
53
54#[doc = "Output Phase Switching Control Register"]
55pub type Opscr = crate::RegValueT<Opscr_SPEC>;
56
57impl Opscr {
58    #[inline(always)]
59    pub fn uf(self) -> crate::common::RegisterFieldBool<0, 1, 0, Opscr_SPEC, crate::common::RW> {
60        crate::common::RegisterFieldBool::<0, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
61            self, 0,
62        )
63    }
64
65    #[inline(always)]
66    pub fn vf(self) -> crate::common::RegisterFieldBool<1, 1, 0, Opscr_SPEC, crate::common::RW> {
67        crate::common::RegisterFieldBool::<1, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
68            self, 0,
69        )
70    }
71
72    #[inline(always)]
73    pub fn wf(self) -> crate::common::RegisterFieldBool<2, 1, 0, Opscr_SPEC, crate::common::RW> {
74        crate::common::RegisterFieldBool::<2, 1, 0, Opscr_SPEC, crate::common::RW>::from_register(
75            self, 0,
76        )
77    }
78
79    #[doc = "Output Phase Enable"]
80    #[inline(always)]
81    pub fn en(
82        self,
83    ) -> crate::common::RegisterField<
84        8,
85        0x1,
86        1,
87        0,
88        opscr::En,
89        opscr::En,
90        Opscr_SPEC,
91        crate::common::RW,
92    > {
93        crate::common::RegisterField::<
94            8,
95            0x1,
96            1,
97            0,
98            opscr::En,
99            opscr::En,
100            Opscr_SPEC,
101            crate::common::RW,
102        >::from_register(self, 0)
103    }
104
105    #[doc = "External Feedback Signal Enable"]
106    #[inline(always)]
107    pub fn fb(
108        self,
109    ) -> crate::common::RegisterField<
110        16,
111        0x1,
112        1,
113        0,
114        opscr::Fb,
115        opscr::Fb,
116        Opscr_SPEC,
117        crate::common::RW,
118    > {
119        crate::common::RegisterField::<
120            16,
121            0x1,
122            1,
123            0,
124            opscr::Fb,
125            opscr::Fb,
126            Opscr_SPEC,
127            crate::common::RW,
128        >::from_register(self, 0)
129    }
130
131    #[doc = "Positive-Phase Output (P) Control"]
132    #[inline(always)]
133    pub fn p(
134        self,
135    ) -> crate::common::RegisterField<
136        17,
137        0x1,
138        1,
139        0,
140        opscr::P,
141        opscr::P,
142        Opscr_SPEC,
143        crate::common::RW,
144    > {
145        crate::common::RegisterField::<
146            17,
147            0x1,
148            1,
149            0,
150            opscr::P,
151            opscr::P,
152            Opscr_SPEC,
153            crate::common::RW,
154        >::from_register(self, 0)
155    }
156
157    #[doc = "Negative-Phase Output (N) Control"]
158    #[inline(always)]
159    pub fn n(
160        self,
161    ) -> crate::common::RegisterField<
162        18,
163        0x1,
164        1,
165        0,
166        opscr::N,
167        opscr::N,
168        Opscr_SPEC,
169        crate::common::RW,
170    > {
171        crate::common::RegisterField::<
172            18,
173            0x1,
174            1,
175            0,
176            opscr::N,
177            opscr::N,
178            Opscr_SPEC,
179            crate::common::RW,
180        >::from_register(self, 0)
181    }
182
183    #[doc = "Output Phase Invert Control"]
184    #[inline(always)]
185    pub fn inv(
186        self,
187    ) -> crate::common::RegisterField<
188        19,
189        0x1,
190        1,
191        0,
192        opscr::Inv,
193        opscr::Inv,
194        Opscr_SPEC,
195        crate::common::RW,
196    > {
197        crate::common::RegisterField::<
198            19,
199            0x1,
200            1,
201            0,
202            opscr::Inv,
203            opscr::Inv,
204            Opscr_SPEC,
205            crate::common::RW,
206        >::from_register(self, 0)
207    }
208
209    #[doc = "Output Phase Rotation Direction Reversal Control"]
210    #[inline(always)]
211    pub fn rv(
212        self,
213    ) -> crate::common::RegisterField<
214        20,
215        0x1,
216        1,
217        0,
218        opscr::Rv,
219        opscr::Rv,
220        Opscr_SPEC,
221        crate::common::RW,
222    > {
223        crate::common::RegisterField::<
224            20,
225            0x1,
226            1,
227            0,
228            opscr::Rv,
229            opscr::Rv,
230            Opscr_SPEC,
231            crate::common::RW,
232        >::from_register(self, 0)
233    }
234
235    #[doc = "Input Phase Alignment"]
236    #[inline(always)]
237    pub fn align(
238        self,
239    ) -> crate::common::RegisterField<
240        21,
241        0x1,
242        1,
243        0,
244        opscr::Align,
245        opscr::Align,
246        Opscr_SPEC,
247        crate::common::RW,
248    > {
249        crate::common::RegisterField::<
250            21,
251            0x1,
252            1,
253            0,
254            opscr::Align,
255            opscr::Align,
256            Opscr_SPEC,
257            crate::common::RW,
258        >::from_register(self, 0)
259    }
260
261    #[doc = "Output Disabled Source Selection"]
262    #[inline(always)]
263    pub fn grp(
264        self,
265    ) -> crate::common::RegisterField<24, 0x3, 1, 0, u8, u8, Opscr_SPEC, crate::common::RW> {
266        crate::common::RegisterField::<24,0x3,1,0,u8,u8,Opscr_SPEC,crate::common::RW>::from_register(self,0)
267    }
268
269    #[doc = "Group Output Disable Function"]
270    #[inline(always)]
271    pub fn godf(
272        self,
273    ) -> crate::common::RegisterField<
274        26,
275        0x1,
276        1,
277        0,
278        opscr::Godf,
279        opscr::Godf,
280        Opscr_SPEC,
281        crate::common::RW,
282    > {
283        crate::common::RegisterField::<
284            26,
285            0x1,
286            1,
287            0,
288            opscr::Godf,
289            opscr::Godf,
290            Opscr_SPEC,
291            crate::common::RW,
292        >::from_register(self, 0)
293    }
294
295    #[doc = "External Input Noise Filter Enable"]
296    #[inline(always)]
297    pub fn nfen(
298        self,
299    ) -> crate::common::RegisterField<
300        29,
301        0x1,
302        1,
303        0,
304        opscr::Nfen,
305        opscr::Nfen,
306        Opscr_SPEC,
307        crate::common::RW,
308    > {
309        crate::common::RegisterField::<
310            29,
311            0x1,
312            1,
313            0,
314            opscr::Nfen,
315            opscr::Nfen,
316            Opscr_SPEC,
317            crate::common::RW,
318        >::from_register(self, 0)
319    }
320
321    #[doc = "External Input Noise Filter Clock Selection"]
322    #[inline(always)]
323    pub fn nfcs(
324        self,
325    ) -> crate::common::RegisterField<
326        30,
327        0x3,
328        1,
329        0,
330        opscr::Nfcs,
331        opscr::Nfcs,
332        Opscr_SPEC,
333        crate::common::RW,
334    > {
335        crate::common::RegisterField::<
336            30,
337            0x3,
338            1,
339            0,
340            opscr::Nfcs,
341            opscr::Nfcs,
342            Opscr_SPEC,
343            crate::common::RW,
344        >::from_register(self, 0)
345    }
346}
347impl ::core::default::Default for Opscr {
348    #[inline(always)]
349    fn default() -> Opscr {
350        <crate::RegValueT<Opscr_SPEC> as RegisterValue<_>>::new(0)
351    }
352}
353pub mod opscr {
354
355    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
356    pub struct En_SPEC;
357    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
358    impl En {
359        #[doc = "Do not output (Hi-Z external pin)"]
360        pub const _0: Self = Self::new(0);
361
362        #[doc = "Output"]
363        pub const _1: Self = Self::new(1);
364    }
365    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
366    pub struct Fb_SPEC;
367    pub type Fb = crate::EnumBitfieldStruct<u8, Fb_SPEC>;
368    impl Fb {
369        #[doc = "Do not use"]
370        pub const _0: Self = Self::new(0);
371
372        #[doc = "Select the soft setting (OPSCR.UF, VF, WF)"]
373        pub const _1: Self = Self::new(1);
374    }
375    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
376    pub struct P_SPEC;
377    pub type P = crate::EnumBitfieldStruct<u8, P_SPEC>;
378    impl P {
379        #[doc = "Level signal output"]
380        pub const _0: Self = Self::new(0);
381
382        #[doc = "PWM signal output"]
383        pub const _1: Self = Self::new(1);
384    }
385    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
386    pub struct N_SPEC;
387    pub type N = crate::EnumBitfieldStruct<u8, N_SPEC>;
388    impl N {
389        #[doc = "Level signal output"]
390        pub const _0: Self = Self::new(0);
391
392        #[doc = "PWM signal output"]
393        pub const _1: Self = Self::new(1);
394    }
395    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
396    pub struct Inv_SPEC;
397    pub type Inv = crate::EnumBitfieldStruct<u8, Inv_SPEC>;
398    impl Inv {
399        #[doc = "Positive logic (active-high) output"]
400        pub const _0: Self = Self::new(0);
401
402        #[doc = "Negative logic (active-low) output"]
403        pub const _1: Self = Self::new(1);
404    }
405    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
406    pub struct Rv_SPEC;
407    pub type Rv = crate::EnumBitfieldStruct<u8, Rv_SPEC>;
408    impl Rv {
409        #[doc = "Positive rotation"]
410        pub const _0: Self = Self::new(0);
411
412        #[doc = "Reverse rotation"]
413        pub const _1: Self = Self::new(1);
414    }
415    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
416    pub struct Align_SPEC;
417    pub type Align = crate::EnumBitfieldStruct<u8, Align_SPEC>;
418    impl Align {
419        #[doc = "Input phase aligned to PCLKD"]
420        pub const _0: Self = Self::new(0);
421
422        #[doc = "Input phase aligned to the falling edge of PWM"]
423        pub const _1: Self = Self::new(1);
424    }
425    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
426    pub struct Godf_SPEC;
427    pub type Godf = crate::EnumBitfieldStruct<u8, Godf_SPEC>;
428    impl Godf {
429        #[doc = "This bit function is ignored"]
430        pub const _0: Self = Self::new(0);
431
432        #[doc = "Group disable clears the OPSCR.EN bit"]
433        pub const _1: Self = Self::new(1);
434    }
435    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
436    pub struct Nfen_SPEC;
437    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
438    impl Nfen {
439        #[doc = "Do not use a noise filter on the external input"]
440        pub const _0: Self = Self::new(0);
441
442        #[doc = "Use a noise filter on the external input"]
443        pub const _1: Self = Self::new(1);
444    }
445    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
446    pub struct Nfcs_SPEC;
447    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
448    impl Nfcs {
449        #[doc = "PCLKD/1"]
450        pub const _00: Self = Self::new(0);
451
452        #[doc = "PCLKD/4"]
453        pub const _01: Self = Self::new(1);
454
455        #[doc = "PCLKD/16"]
456        pub const _10: Self = Self::new(2);
457
458        #[doc = "PCLKD/64"]
459        pub const _11: Self = Self::new(3);
460    }
461}
ra2a2_pac/gpt_ops.rs

ra2a2_pac/
gpt_ops.rs
