ra2a2_pac/
lib.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.20.02, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:01:00 +0000
19#![cfg_attr(not(feature = "tracing"), no_std)]
20#![allow(non_camel_case_types)]
21#![doc = "Arm Cortex-M23 based Microcontroller RA2A2 group"]
22pub mod common;
23pub use common::*;
24
25#[cfg(feature = "tracing")]
26pub mod reg_name;
27#[cfg(feature = "tracing")]
28pub mod tracing;
29
30#[cfg(feature = "adc120")]
31pub mod adc120;
32#[cfg(feature = "agt0")]
33pub mod agt0;
34#[cfg(feature = "agtw0")]
35pub mod agtw0;
36#[cfg(feature = "bus")]
37pub mod bus;
38#[cfg(feature = "cac")]
39pub mod cac;
40#[cfg(feature = "crc")]
41pub mod crc;
42#[cfg(feature = "dbg")]
43pub mod dbg;
44#[cfg(feature = "doc")]
45pub mod doc;
46#[cfg(feature = "dtc")]
47pub mod dtc;
48#[cfg(feature = "elc")]
49pub mod elc;
50#[cfg(feature = "flcn")]
51pub mod flcn;
52#[cfg(feature = "gpt164")]
53pub mod gpt164;
54#[cfg(feature = "gpt_ops")]
55pub mod gpt_ops;
56#[cfg(feature = "icu")]
57pub mod icu;
58#[cfg(feature = "iic0")]
59pub mod iic0;
60#[cfg(feature = "iic0wu")]
61pub mod iic0wu;
62#[cfg(feature = "iwdt")]
63pub mod iwdt;
64#[cfg(feature = "macl")]
65pub mod macl;
66#[cfg(feature = "mmf")]
67pub mod mmf;
68#[cfg(feature = "mstp")]
69pub mod mstp;
70#[cfg(feature = "pfs")]
71pub mod pfs;
72#[cfg(feature = "poeg")]
73pub mod poeg;
74#[cfg(feature = "port0")]
75pub mod port0;
76#[cfg(feature = "port1")]
77pub mod port1;
78#[cfg(feature = "rmpu")]
79pub mod rmpu;
80#[cfg(feature = "rtc")]
81pub mod rtc;
82#[cfg(feature = "sci0")]
83pub mod sci0;
84#[cfg(feature = "sci1")]
85pub mod sci1;
86#[cfg(feature = "sdadc24_b")]
87pub mod sdadc24_b;
88#[cfg(feature = "slcdc")]
89pub mod slcdc;
90#[cfg(feature = "spi0")]
91pub mod spi0;
92#[cfg(feature = "sram")]
93pub mod sram;
94#[cfg(feature = "sysc")]
95pub mod sysc;
96#[cfg(feature = "wdt")]
97pub mod wdt;
98
99#[cfg(feature = "rmpu")]
100#[derive(Copy, Clone, Eq, PartialEq)]
101pub struct Rmpu {
102    ptr: *mut u8,
103}
104#[cfg(feature = "rmpu")]
105pub const RMPU: self::Rmpu = self::Rmpu {
106    ptr: 0x40000000u32 as _,
107};
108#[cfg(feature = "mmf")]
109#[derive(Copy, Clone, Eq, PartialEq)]
110pub struct Mmf {
111    ptr: *mut u8,
112}
113#[cfg(feature = "mmf")]
114pub const MMF: self::Mmf = self::Mmf {
115    ptr: 0x40001000u32 as _,
116};
117#[cfg(feature = "sram")]
118#[derive(Copy, Clone, Eq, PartialEq)]
119pub struct Sram {
120    ptr: *mut u8,
121}
122#[cfg(feature = "sram")]
123pub const SRAM: self::Sram = self::Sram {
124    ptr: 0x40002000u32 as _,
125};
126#[cfg(feature = "bus")]
127#[derive(Copy, Clone, Eq, PartialEq)]
128pub struct Bus {
129    ptr: *mut u8,
130}
131#[cfg(feature = "bus")]
132pub const BUS: self::Bus = self::Bus {
133    ptr: 0x40003000u32 as _,
134};
135#[cfg(feature = "dtc")]
136#[derive(Copy, Clone, Eq, PartialEq)]
137pub struct Dtc {
138    ptr: *mut u8,
139}
140#[cfg(feature = "dtc")]
141pub const DTC: self::Dtc = self::Dtc {
142    ptr: 0x40005400u32 as _,
143};
144#[cfg(feature = "icu")]
145#[derive(Copy, Clone, Eq, PartialEq)]
146pub struct Icu {
147    ptr: *mut u8,
148}
149#[cfg(feature = "icu")]
150pub const ICU: self::Icu = self::Icu {
151    ptr: 0x40006000u32 as _,
152};
153#[cfg(feature = "dbg")]
154#[derive(Copy, Clone, Eq, PartialEq)]
155pub struct Dbg {
156    ptr: *mut u8,
157}
158#[cfg(feature = "dbg")]
159pub const DBG: self::Dbg = self::Dbg {
160    ptr: 0x4001b000u32 as _,
161};
162#[cfg(feature = "sysc")]
163#[derive(Copy, Clone, Eq, PartialEq)]
164pub struct Sysc {
165    ptr: *mut u8,
166}
167#[cfg(feature = "sysc")]
168pub const SYSC: self::Sysc = self::Sysc {
169    ptr: 0x4001e000u32 as _,
170};
171#[cfg(feature = "port0")]
172#[derive(Copy, Clone, Eq, PartialEq)]
173pub struct Port0 {
174    ptr: *mut u8,
175}
176#[cfg(feature = "port0")]
177pub const PORT0: self::Port0 = self::Port0 {
178    ptr: 0x40040000u32 as _,
179};
180#[cfg(feature = "port1")]
181#[derive(Copy, Clone, Eq, PartialEq)]
182pub struct Port1 {
183    ptr: *mut u8,
184}
185#[cfg(feature = "port1")]
186pub const PORT1: self::Port1 = self::Port1 {
187    ptr: 0x40040020u32 as _,
188};
189#[cfg(feature = "port2")]
190pub const PORT2: self::Port1 = self::Port1 {
191    ptr: 0x40040040u32 as _,
192};
193#[cfg(feature = "port3")]
194pub const PORT3: self::Port0 = self::Port0 {
195    ptr: 0x40040060u32 as _,
196};
197#[cfg(feature = "port4")]
198pub const PORT4: self::Port0 = self::Port0 {
199    ptr: 0x40040080u32 as _,
200};
201#[cfg(feature = "port5")]
202pub const PORT5: self::Port0 = self::Port0 {
203    ptr: 0x400400a0u32 as _,
204};
205#[cfg(feature = "port6")]
206pub const PORT6: self::Port0 = self::Port0 {
207    ptr: 0x400400c0u32 as _,
208};
209#[cfg(feature = "pfs")]
210#[derive(Copy, Clone, Eq, PartialEq)]
211pub struct Pfs {
212    ptr: *mut u8,
213}
214#[cfg(feature = "pfs")]
215pub const PFS: self::Pfs = self::Pfs {
216    ptr: 0x40040800u32 as _,
217};
218#[cfg(feature = "elc")]
219#[derive(Copy, Clone, Eq, PartialEq)]
220pub struct Elc {
221    ptr: *mut u8,
222}
223#[cfg(feature = "elc")]
224pub const ELC: self::Elc = self::Elc {
225    ptr: 0x40041000u32 as _,
226};
227#[cfg(feature = "poeg")]
228#[derive(Copy, Clone, Eq, PartialEq)]
229pub struct Poeg {
230    ptr: *mut u8,
231}
232#[cfg(feature = "poeg")]
233pub const POEG: self::Poeg = self::Poeg {
234    ptr: 0x40042000u32 as _,
235};
236#[cfg(feature = "rtc")]
237#[derive(Copy, Clone, Eq, PartialEq)]
238pub struct Rtc {
239    ptr: *mut u8,
240}
241#[cfg(feature = "rtc")]
242pub const RTC: self::Rtc = self::Rtc {
243    ptr: 0x40044000u32 as _,
244};
245#[cfg(feature = "wdt")]
246#[derive(Copy, Clone, Eq, PartialEq)]
247pub struct Wdt {
248    ptr: *mut u8,
249}
250#[cfg(feature = "wdt")]
251pub const WDT: self::Wdt = self::Wdt {
252    ptr: 0x40044200u32 as _,
253};
254#[cfg(feature = "iwdt")]
255#[derive(Copy, Clone, Eq, PartialEq)]
256pub struct Iwdt {
257    ptr: *mut u8,
258}
259#[cfg(feature = "iwdt")]
260pub const IWDT: self::Iwdt = self::Iwdt {
261    ptr: 0x40044400u32 as _,
262};
263#[cfg(feature = "cac")]
264#[derive(Copy, Clone, Eq, PartialEq)]
265pub struct Cac {
266    ptr: *mut u8,
267}
268#[cfg(feature = "cac")]
269pub const CAC: self::Cac = self::Cac {
270    ptr: 0x40044600u32 as _,
271};
272#[cfg(feature = "mstp")]
273#[derive(Copy, Clone, Eq, PartialEq)]
274pub struct Mstp {
275    ptr: *mut u8,
276}
277#[cfg(feature = "mstp")]
278pub const MSTP: self::Mstp = self::Mstp {
279    ptr: 0x40047000u32 as _,
280};
281#[cfg(feature = "iic0")]
282#[derive(Copy, Clone, Eq, PartialEq)]
283pub struct Iic0 {
284    ptr: *mut u8,
285}
286#[cfg(feature = "iic0")]
287pub const IIC0: self::Iic0 = self::Iic0 {
288    ptr: 0x40053000u32 as _,
289};
290#[cfg(feature = "iic0wu")]
291#[derive(Copy, Clone, Eq, PartialEq)]
292pub struct Iic0Wu {
293    ptr: *mut u8,
294}
295#[cfg(feature = "iic0wu")]
296pub const IIC0WU: self::Iic0Wu = self::Iic0Wu {
297    ptr: 0x40053014u32 as _,
298};
299#[cfg(feature = "iic1")]
300pub const IIC1: self::Iic0 = self::Iic0 {
301    ptr: 0x40053100u32 as _,
302};
303#[cfg(feature = "doc")]
304#[derive(Copy, Clone, Eq, PartialEq)]
305pub struct Doc {
306    ptr: *mut u8,
307}
308#[cfg(feature = "doc")]
309pub const DOC: self::Doc = self::Doc {
310    ptr: 0x40054100u32 as _,
311};
312#[cfg(feature = "adc120")]
313#[derive(Copy, Clone, Eq, PartialEq)]
314pub struct Adc120 {
315    ptr: *mut u8,
316}
317#[cfg(feature = "adc120")]
318pub const ADC120: self::Adc120 = self::Adc120 {
319    ptr: 0x4005c000u32 as _,
320};
321#[cfg(feature = "sci0")]
322#[derive(Copy, Clone, Eq, PartialEq)]
323pub struct Sci0 {
324    ptr: *mut u8,
325}
326#[cfg(feature = "sci0")]
327pub const SCI0: self::Sci0 = self::Sci0 {
328    ptr: 0x40070000u32 as _,
329};
330#[cfg(feature = "sci1")]
331#[derive(Copy, Clone, Eq, PartialEq)]
332pub struct Sci1 {
333    ptr: *mut u8,
334}
335#[cfg(feature = "sci1")]
336pub const SCI1: self::Sci1 = self::Sci1 {
337    ptr: 0x40070020u32 as _,
338};
339#[cfg(feature = "sci2")]
340pub const SCI2: self::Sci1 = self::Sci1 {
341    ptr: 0x40070040u32 as _,
342};
343#[cfg(feature = "sci3")]
344pub const SCI3: self::Sci1 = self::Sci1 {
345    ptr: 0x40070060u32 as _,
346};
347#[cfg(feature = "sci9")]
348pub const SCI9: self::Sci1 = self::Sci1 {
349    ptr: 0x40070120u32 as _,
350};
351#[cfg(feature = "spi0")]
352#[derive(Copy, Clone, Eq, PartialEq)]
353pub struct Spi0 {
354    ptr: *mut u8,
355}
356#[cfg(feature = "spi0")]
357pub const SPI0: self::Spi0 = self::Spi0 {
358    ptr: 0x40072000u32 as _,
359};
360#[cfg(feature = "crc")]
361#[derive(Copy, Clone, Eq, PartialEq)]
362pub struct Crc {
363    ptr: *mut u8,
364}
365#[cfg(feature = "crc")]
366pub const CRC: self::Crc = self::Crc {
367    ptr: 0x40074000u32 as _,
368};
369#[cfg(feature = "gpt164")]
370#[derive(Copy, Clone, Eq, PartialEq)]
371pub struct Gpt164 {
372    ptr: *mut u8,
373}
374#[cfg(feature = "gpt164")]
375pub const GPT164: self::Gpt164 = self::Gpt164 {
376    ptr: 0x40078400u32 as _,
377};
378#[cfg(feature = "gpt165")]
379pub const GPT165: self::Gpt164 = self::Gpt164 {
380    ptr: 0x40078500u32 as _,
381};
382#[cfg(feature = "gpt166")]
383pub const GPT166: self::Gpt164 = self::Gpt164 {
384    ptr: 0x40078600u32 as _,
385};
386#[cfg(feature = "gpt167")]
387pub const GPT167: self::Gpt164 = self::Gpt164 {
388    ptr: 0x40078700u32 as _,
389};
390#[cfg(feature = "gpt168")]
391pub const GPT168: self::Gpt164 = self::Gpt164 {
392    ptr: 0x40078800u32 as _,
393};
394#[cfg(feature = "gpt169")]
395pub const GPT169: self::Gpt164 = self::Gpt164 {
396    ptr: 0x40078900u32 as _,
397};
398#[cfg(feature = "gpt_ops")]
399#[derive(Copy, Clone, Eq, PartialEq)]
400pub struct GptOps {
401    ptr: *mut u8,
402}
403#[cfg(feature = "gpt_ops")]
404pub const GPT_OPS: self::GptOps = self::GptOps {
405    ptr: 0x40078ff0u32 as _,
406};
407#[cfg(feature = "slcdc")]
408#[derive(Copy, Clone, Eq, PartialEq)]
409pub struct Slcdc {
410    ptr: *mut u8,
411}
412#[cfg(feature = "slcdc")]
413pub const SLCDC: self::Slcdc = self::Slcdc {
414    ptr: 0x40082000u32 as _,
415};
416#[cfg(feature = "agtw0")]
417#[derive(Copy, Clone, Eq, PartialEq)]
418pub struct Agtw0 {
419    ptr: *mut u8,
420}
421#[cfg(feature = "agtw0")]
422pub const AGTW0: self::Agtw0 = self::Agtw0 {
423    ptr: 0x40084000u32 as _,
424};
425#[cfg(feature = "agtw1")]
426pub const AGTW1: self::Agtw0 = self::Agtw0 {
427    ptr: 0x40084100u32 as _,
428};
429#[cfg(feature = "agt0")]
430#[derive(Copy, Clone, Eq, PartialEq)]
431pub struct Agt0 {
432    ptr: *mut u8,
433}
434#[cfg(feature = "agt0")]
435pub const AGT0: self::Agt0 = self::Agt0 {
436    ptr: 0x40084200u32 as _,
437};
438#[cfg(feature = "agt1")]
439pub const AGT1: self::Agt0 = self::Agt0 {
440    ptr: 0x40084300u32 as _,
441};
442#[cfg(feature = "agt2")]
443pub const AGT2: self::Agt0 = self::Agt0 {
444    ptr: 0x40084400u32 as _,
445};
446#[cfg(feature = "agt3")]
447pub const AGT3: self::Agt0 = self::Agt0 {
448    ptr: 0x40084500u32 as _,
449};
450#[cfg(feature = "agt4")]
451pub const AGT4: self::Agt0 = self::Agt0 {
452    ptr: 0x40084600u32 as _,
453};
454#[cfg(feature = "agt5")]
455pub const AGT5: self::Agt0 = self::Agt0 {
456    ptr: 0x40084700u32 as _,
457};
458#[cfg(feature = "agt6")]
459pub const AGT6: self::Agt0 = self::Agt0 {
460    ptr: 0x40084800u32 as _,
461};
462#[cfg(feature = "agt7")]
463pub const AGT7: self::Agt0 = self::Agt0 {
464    ptr: 0x40084900u32 as _,
465};
466#[cfg(feature = "sdadc24_b")]
467#[derive(Copy, Clone, Eq, PartialEq)]
468pub struct Sdadc24B {
469    ptr: *mut u8,
470}
471#[cfg(feature = "sdadc24_b")]
472pub const SDADC24_B: self::Sdadc24B = self::Sdadc24B {
473    ptr: 0x4009c000u32 as _,
474};
475#[cfg(feature = "macl")]
476#[derive(Copy, Clone, Eq, PartialEq)]
477pub struct Macl {
478    ptr: *mut u8,
479}
480#[cfg(feature = "macl")]
481pub const MACL: self::Macl = self::Macl {
482    ptr: 0x400a0000u32 as _,
483};
484#[cfg(feature = "flcn")]
485#[derive(Copy, Clone, Eq, PartialEq)]
486pub struct Flcn {
487    ptr: *mut u8,
488}
489#[cfg(feature = "flcn")]
490pub const FLCN: self::Flcn = self::Flcn {
491    ptr: 0x407ec000u32 as _,
492};
493
494pub use cortex_m::peripheral::Peripherals as CorePeripherals;
495pub use cortex_m::peripheral::{CBP, CPUID, DCB, DWT, FPB, ITM, MPU, NVIC, SCB, SYST, TPIU};
496#[doc = "Number available in the NVIC for configuring priority"]
497pub const NVIC_PRIO_BITS: u8 = 2;
498#[doc(hidden)]
499pub union Vector {
500    _handler: unsafe extern "C" fn(),
501    _reserved: u32,
502}
503#[cfg(feature = "rt")]
504pub use self::Interrupt as interrupt;
505#[cfg(feature = "rt")]
506pub use cortex_m_rt::interrupt;
507#[cfg(feature = "rt")]
508pub mod interrupt_handlers {
509    unsafe extern "C" {
510        pub fn IEL0();
511        pub fn IEL1();
512        pub fn IEL2();
513        pub fn IEL3();
514        pub fn IEL4();
515        pub fn IEL5();
516        pub fn IEL6();
517        pub fn IEL7();
518        pub fn IEL8();
519        pub fn IEL9();
520        pub fn IEL10();
521        pub fn IEL11();
522        pub fn IEL12();
523        pub fn IEL13();
524        pub fn IEL14();
525        pub fn IEL15();
526        pub fn IEL16();
527        pub fn IEL17();
528        pub fn IEL18();
529        pub fn IEL19();
530        pub fn IEL20();
531        pub fn IEL21();
532        pub fn IEL22();
533        pub fn IEL23();
534        pub fn IEL24();
535        pub fn IEL25();
536        pub fn IEL26();
537        pub fn IEL27();
538        pub fn IEL28();
539        pub fn IEL29();
540        pub fn IEL30();
541        pub fn IEL31();
542    }
543}
544#[cfg(feature = "rt")]
545#[doc(hidden)]
546#[unsafe(link_section = ".vector_table.interrupts")]
547#[unsafe(no_mangle)]
548pub static __INTERRUPTS: [Vector; 32] = [
549    Vector {
550        _handler: interrupt_handlers::IEL0,
551    },
552    Vector {
553        _handler: interrupt_handlers::IEL1,
554    },
555    Vector {
556        _handler: interrupt_handlers::IEL2,
557    },
558    Vector {
559        _handler: interrupt_handlers::IEL3,
560    },
561    Vector {
562        _handler: interrupt_handlers::IEL4,
563    },
564    Vector {
565        _handler: interrupt_handlers::IEL5,
566    },
567    Vector {
568        _handler: interrupt_handlers::IEL6,
569    },
570    Vector {
571        _handler: interrupt_handlers::IEL7,
572    },
573    Vector {
574        _handler: interrupt_handlers::IEL8,
575    },
576    Vector {
577        _handler: interrupt_handlers::IEL9,
578    },
579    Vector {
580        _handler: interrupt_handlers::IEL10,
581    },
582    Vector {
583        _handler: interrupt_handlers::IEL11,
584    },
585    Vector {
586        _handler: interrupt_handlers::IEL12,
587    },
588    Vector {
589        _handler: interrupt_handlers::IEL13,
590    },
591    Vector {
592        _handler: interrupt_handlers::IEL14,
593    },
594    Vector {
595        _handler: interrupt_handlers::IEL15,
596    },
597    Vector {
598        _handler: interrupt_handlers::IEL16,
599    },
600    Vector {
601        _handler: interrupt_handlers::IEL17,
602    },
603    Vector {
604        _handler: interrupt_handlers::IEL18,
605    },
606    Vector {
607        _handler: interrupt_handlers::IEL19,
608    },
609    Vector {
610        _handler: interrupt_handlers::IEL20,
611    },
612    Vector {
613        _handler: interrupt_handlers::IEL21,
614    },
615    Vector {
616        _handler: interrupt_handlers::IEL22,
617    },
618    Vector {
619        _handler: interrupt_handlers::IEL23,
620    },
621    Vector {
622        _handler: interrupt_handlers::IEL24,
623    },
624    Vector {
625        _handler: interrupt_handlers::IEL25,
626    },
627    Vector {
628        _handler: interrupt_handlers::IEL26,
629    },
630    Vector {
631        _handler: interrupt_handlers::IEL27,
632    },
633    Vector {
634        _handler: interrupt_handlers::IEL28,
635    },
636    Vector {
637        _handler: interrupt_handlers::IEL29,
638    },
639    Vector {
640        _handler: interrupt_handlers::IEL30,
641    },
642    Vector {
643        _handler: interrupt_handlers::IEL31,
644    },
645];
646#[doc = "Enumeration of all the interrupts."]
647#[derive(Copy, Clone, Debug, PartialEq, Eq)]
648#[repr(u16)]
649pub enum Interrupt {
650    #[doc = "ICU Interrupt 0"]
651    IEL0 = 0,
652
653    #[doc = "ICU Interrupt 1"]
654    IEL1 = 1,
655
656    #[doc = "ICU Interrupt 2"]
657    IEL2 = 2,
658
659    #[doc = "ICU Interrupt 3"]
660    IEL3 = 3,
661
662    #[doc = "ICU Interrupt 4"]
663    IEL4 = 4,
664
665    #[doc = "ICU Interrupt 5"]
666    IEL5 = 5,
667
668    #[doc = "ICU Interrupt 6"]
669    IEL6 = 6,
670
671    #[doc = "ICU Interrupt 7"]
672    IEL7 = 7,
673
674    #[doc = "ICU Interrupt 8"]
675    IEL8 = 8,
676
677    #[doc = "ICU Interrupt 9"]
678    IEL9 = 9,
679
680    #[doc = "ICU Interrupt 10"]
681    IEL10 = 10,
682
683    #[doc = "ICU Interrupt 11"]
684    IEL11 = 11,
685
686    #[doc = "ICU Interrupt 12"]
687    IEL12 = 12,
688
689    #[doc = "ICU Interrupt 13"]
690    IEL13 = 13,
691
692    #[doc = "ICU Interrupt 14"]
693    IEL14 = 14,
694
695    #[doc = "ICU Interrupt 15"]
696    IEL15 = 15,
697
698    #[doc = "ICU Interrupt 16"]
699    IEL16 = 16,
700
701    #[doc = "ICU Interrupt 17"]
702    IEL17 = 17,
703
704    #[doc = "ICU Interrupt 18"]
705    IEL18 = 18,
706
707    #[doc = "ICU Interrupt 19"]
708    IEL19 = 19,
709
710    #[doc = "ICU Interrupt 20"]
711    IEL20 = 20,
712
713    #[doc = "ICU Interrupt 21"]
714    IEL21 = 21,
715
716    #[doc = "ICU Interrupt 22"]
717    IEL22 = 22,
718
719    #[doc = "ICU Interrupt 23"]
720    IEL23 = 23,
721
722    #[doc = "ICU Interrupt 24"]
723    IEL24 = 24,
724
725    #[doc = "ICU Interrupt 25"]
726    IEL25 = 25,
727
728    #[doc = "ICU Interrupt 26"]
729    IEL26 = 26,
730
731    #[doc = "ICU Interrupt 27"]
732    IEL27 = 27,
733
734    #[doc = "ICU Interrupt 28"]
735    IEL28 = 28,
736
737    #[doc = "ICU Interrupt 29"]
738    IEL29 = 29,
739
740    #[doc = "ICU Interrupt 30"]
741    IEL30 = 30,
742
743    #[doc = "ICU Interrupt 31"]
744    IEL31 = 31,
745}
746unsafe impl cortex_m::interrupt::InterruptNumber for Interrupt {
747    #[inline(always)]
748    fn number(self) -> u16 {
749        self as u16
750    }
751}
752#[allow(non_snake_case)]
753/// Required for compatibility with RTIC and other frameworks
754pub struct Peripherals {
755    #[cfg(feature = "rmpu")]
756    pub RMPU: self::Rmpu,
757    #[cfg(feature = "mmf")]
758    pub MMF: self::Mmf,
759    #[cfg(feature = "sram")]
760    pub SRAM: self::Sram,
761    #[cfg(feature = "bus")]
762    pub BUS: self::Bus,
763    #[cfg(feature = "dtc")]
764    pub DTC: self::Dtc,
765    #[cfg(feature = "icu")]
766    pub ICU: self::Icu,
767    #[cfg(feature = "dbg")]
768    pub DBG: self::Dbg,
769    #[cfg(feature = "sysc")]
770    pub SYSC: self::Sysc,
771    #[cfg(feature = "port0")]
772    pub PORT0: self::Port0,
773    #[cfg(feature = "port1")]
774    pub PORT1: self::Port1,
775    #[cfg(feature = "port2")]
776    pub PORT2: self::Port1,
777    #[cfg(feature = "port3")]
778    pub PORT3: self::Port0,
779    #[cfg(feature = "port4")]
780    pub PORT4: self::Port0,
781    #[cfg(feature = "port5")]
782    pub PORT5: self::Port0,
783    #[cfg(feature = "port6")]
784    pub PORT6: self::Port0,
785    #[cfg(feature = "pfs")]
786    pub PFS: self::Pfs,
787    #[cfg(feature = "elc")]
788    pub ELC: self::Elc,
789    #[cfg(feature = "poeg")]
790    pub POEG: self::Poeg,
791    #[cfg(feature = "rtc")]
792    pub RTC: self::Rtc,
793    #[cfg(feature = "wdt")]
794    pub WDT: self::Wdt,
795    #[cfg(feature = "iwdt")]
796    pub IWDT: self::Iwdt,
797    #[cfg(feature = "cac")]
798    pub CAC: self::Cac,
799    #[cfg(feature = "mstp")]
800    pub MSTP: self::Mstp,
801    #[cfg(feature = "iic0")]
802    pub IIC0: self::Iic0,
803    #[cfg(feature = "iic0wu")]
804    pub IIC0WU: self::Iic0Wu,
805    #[cfg(feature = "iic1")]
806    pub IIC1: self::Iic0,
807    #[cfg(feature = "doc")]
808    pub DOC: self::Doc,
809    #[cfg(feature = "adc120")]
810    pub ADC120: self::Adc120,
811    #[cfg(feature = "sci0")]
812    pub SCI0: self::Sci0,
813    #[cfg(feature = "sci1")]
814    pub SCI1: self::Sci1,
815    #[cfg(feature = "sci2")]
816    pub SCI2: self::Sci1,
817    #[cfg(feature = "sci3")]
818    pub SCI3: self::Sci1,
819    #[cfg(feature = "sci9")]
820    pub SCI9: self::Sci1,
821    #[cfg(feature = "spi0")]
822    pub SPI0: self::Spi0,
823    #[cfg(feature = "crc")]
824    pub CRC: self::Crc,
825    #[cfg(feature = "gpt164")]
826    pub GPT164: self::Gpt164,
827    #[cfg(feature = "gpt165")]
828    pub GPT165: self::Gpt164,
829    #[cfg(feature = "gpt166")]
830    pub GPT166: self::Gpt164,
831    #[cfg(feature = "gpt167")]
832    pub GPT167: self::Gpt164,
833    #[cfg(feature = "gpt168")]
834    pub GPT168: self::Gpt164,
835    #[cfg(feature = "gpt169")]
836    pub GPT169: self::Gpt164,
837    #[cfg(feature = "gpt_ops")]
838    pub GPT_OPS: self::GptOps,
839    #[cfg(feature = "slcdc")]
840    pub SLCDC: self::Slcdc,
841    #[cfg(feature = "agtw0")]
842    pub AGTW0: self::Agtw0,
843    #[cfg(feature = "agtw1")]
844    pub AGTW1: self::Agtw0,
845    #[cfg(feature = "agt0")]
846    pub AGT0: self::Agt0,
847    #[cfg(feature = "agt1")]
848    pub AGT1: self::Agt0,
849    #[cfg(feature = "agt2")]
850    pub AGT2: self::Agt0,
851    #[cfg(feature = "agt3")]
852    pub AGT3: self::Agt0,
853    #[cfg(feature = "agt4")]
854    pub AGT4: self::Agt0,
855    #[cfg(feature = "agt5")]
856    pub AGT5: self::Agt0,
857    #[cfg(feature = "agt6")]
858    pub AGT6: self::Agt0,
859    #[cfg(feature = "agt7")]
860    pub AGT7: self::Agt0,
861    #[cfg(feature = "sdadc24_b")]
862    pub SDADC24_B: self::Sdadc24B,
863    #[cfg(feature = "macl")]
864    pub MACL: self::Macl,
865    #[cfg(feature = "flcn")]
866    pub FLCN: self::Flcn,
867}
868
869impl Peripherals {
870    /// Returns Peripheral struct multiple times
871    /// Required for compatibility with RTIC and other frameworks
872    #[inline]
873    pub fn take() -> Option<Self> {
874        Some(Self::steal())
875    }
876
877    /// Returns Peripheral struct multiple times
878    /// Required for compatibility with RTIC and other frameworks
879    #[inline]
880    pub fn steal() -> Self {
881        Peripherals {
882            #[cfg(feature = "rmpu")]
883            RMPU: crate::RMPU,
884            #[cfg(feature = "mmf")]
885            MMF: crate::MMF,
886            #[cfg(feature = "sram")]
887            SRAM: crate::SRAM,
888            #[cfg(feature = "bus")]
889            BUS: crate::BUS,
890            #[cfg(feature = "dtc")]
891            DTC: crate::DTC,
892            #[cfg(feature = "icu")]
893            ICU: crate::ICU,
894            #[cfg(feature = "dbg")]
895            DBG: crate::DBG,
896            #[cfg(feature = "sysc")]
897            SYSC: crate::SYSC,
898            #[cfg(feature = "port0")]
899            PORT0: crate::PORT0,
900            #[cfg(feature = "port1")]
901            PORT1: crate::PORT1,
902            #[cfg(feature = "port2")]
903            PORT2: crate::PORT2,
904            #[cfg(feature = "port3")]
905            PORT3: crate::PORT3,
906            #[cfg(feature = "port4")]
907            PORT4: crate::PORT4,
908            #[cfg(feature = "port5")]
909            PORT5: crate::PORT5,
910            #[cfg(feature = "port6")]
911            PORT6: crate::PORT6,
912            #[cfg(feature = "pfs")]
913            PFS: crate::PFS,
914            #[cfg(feature = "elc")]
915            ELC: crate::ELC,
916            #[cfg(feature = "poeg")]
917            POEG: crate::POEG,
918            #[cfg(feature = "rtc")]
919            RTC: crate::RTC,
920            #[cfg(feature = "wdt")]
921            WDT: crate::WDT,
922            #[cfg(feature = "iwdt")]
923            IWDT: crate::IWDT,
924            #[cfg(feature = "cac")]
925            CAC: crate::CAC,
926            #[cfg(feature = "mstp")]
927            MSTP: crate::MSTP,
928            #[cfg(feature = "iic0")]
929            IIC0: crate::IIC0,
930            #[cfg(feature = "iic0wu")]
931            IIC0WU: crate::IIC0WU,
932            #[cfg(feature = "iic1")]
933            IIC1: crate::IIC1,
934            #[cfg(feature = "doc")]
935            DOC: crate::DOC,
936            #[cfg(feature = "adc120")]
937            ADC120: crate::ADC120,
938            #[cfg(feature = "sci0")]
939            SCI0: crate::SCI0,
940            #[cfg(feature = "sci1")]
941            SCI1: crate::SCI1,
942            #[cfg(feature = "sci2")]
943            SCI2: crate::SCI2,
944            #[cfg(feature = "sci3")]
945            SCI3: crate::SCI3,
946            #[cfg(feature = "sci9")]
947            SCI9: crate::SCI9,
948            #[cfg(feature = "spi0")]
949            SPI0: crate::SPI0,
950            #[cfg(feature = "crc")]
951            CRC: crate::CRC,
952            #[cfg(feature = "gpt164")]
953            GPT164: crate::GPT164,
954            #[cfg(feature = "gpt165")]
955            GPT165: crate::GPT165,
956            #[cfg(feature = "gpt166")]
957            GPT166: crate::GPT166,
958            #[cfg(feature = "gpt167")]
959            GPT167: crate::GPT167,
960            #[cfg(feature = "gpt168")]
961            GPT168: crate::GPT168,
962            #[cfg(feature = "gpt169")]
963            GPT169: crate::GPT169,
964            #[cfg(feature = "gpt_ops")]
965            GPT_OPS: crate::GPT_OPS,
966            #[cfg(feature = "slcdc")]
967            SLCDC: crate::SLCDC,
968            #[cfg(feature = "agtw0")]
969            AGTW0: crate::AGTW0,
970            #[cfg(feature = "agtw1")]
971            AGTW1: crate::AGTW1,
972            #[cfg(feature = "agt0")]
973            AGT0: crate::AGT0,
974            #[cfg(feature = "agt1")]
975            AGT1: crate::AGT1,
976            #[cfg(feature = "agt2")]
977            AGT2: crate::AGT2,
978            #[cfg(feature = "agt3")]
979            AGT3: crate::AGT3,
980            #[cfg(feature = "agt4")]
981            AGT4: crate::AGT4,
982            #[cfg(feature = "agt5")]
983            AGT5: crate::AGT5,
984            #[cfg(feature = "agt6")]
985            AGT6: crate::AGT6,
986            #[cfg(feature = "agt7")]
987            AGT7: crate::AGT7,
988            #[cfg(feature = "sdadc24_b")]
989            SDADC24_B: crate::SDADC24_B,
990            #[cfg(feature = "macl")]
991            MACL: crate::MACL,
992            #[cfg(feature = "flcn")]
993            FLCN: crate::FLCN,
994        }
995    }
996}
ra2a2_pac/lib.rs

ra2a2_pac/
lib.rs
