ra2a1/sdadc24/
stc1.rs

1#[doc = "Register `STC1` reader"]
2pub struct R(crate::R<STC1_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<STC1_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<STC1_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<STC1_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `STC1` writer"]
17pub struct W(crate::W<STC1_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<STC1_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<STC1_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<STC1_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CLKDIV` reader - SDADC24 reference clock division select"]
38pub type CLKDIV_R = crate::FieldReader<u8, CLKDIV_A>;
39#[doc = "SDADC24 reference clock division select\n\nValue on reset: 8"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum CLKDIV_A {
43    #[doc = "0: SDADCCLK (no division)"]
44    _0000 = 0,
45    #[doc = "1: SDADCCLK/2 (1/2)"]
46    _0001 = 1,
47    #[doc = "2: SDADCCLK/3 (1/3)"]
48    _0010 = 2,
49    #[doc = "3: SDADCCLK/4 (1/4)"]
50    _0011 = 3,
51    #[doc = "4: SDADCCLK/5 (1/5)"]
52    _0100 = 4,
53    #[doc = "5: SDADCCLK/6 (1/6)"]
54    _0101 = 5,
55    #[doc = "6: SDADCCLK/8 (1/8)"]
56    _0110 = 6,
57    #[doc = "7: SDADCCLK/12 (1/12)"]
58    _0111 = 7,
59    #[doc = "8: SDADCCLK/16 (1/16)."]
60    _1000 = 8,
61}
62impl From<CLKDIV_A> for u8 {
63    #[inline(always)]
64    fn from(variant: CLKDIV_A) -> Self {
65        variant as _
66    }
67}
68impl CLKDIV_R {
69    #[doc = "Get enumerated values variant"]
70    #[inline(always)]
71    pub fn variant(&self) -> Option<CLKDIV_A> {
72        match self.bits {
73            0 => Some(CLKDIV_A::_0000),
74            1 => Some(CLKDIV_A::_0001),
75            2 => Some(CLKDIV_A::_0010),
76            3 => Some(CLKDIV_A::_0011),
77            4 => Some(CLKDIV_A::_0100),
78            5 => Some(CLKDIV_A::_0101),
79            6 => Some(CLKDIV_A::_0110),
80            7 => Some(CLKDIV_A::_0111),
81            8 => Some(CLKDIV_A::_1000),
82            _ => None,
83        }
84    }
85    #[doc = "Checks if the value of the field is `_0000`"]
86    #[inline(always)]
87    pub fn is_0000(&self) -> bool {
88        *self == CLKDIV_A::_0000
89    }
90    #[doc = "Checks if the value of the field is `_0001`"]
91    #[inline(always)]
92    pub fn is_0001(&self) -> bool {
93        *self == CLKDIV_A::_0001
94    }
95    #[doc = "Checks if the value of the field is `_0010`"]
96    #[inline(always)]
97    pub fn is_0010(&self) -> bool {
98        *self == CLKDIV_A::_0010
99    }
100    #[doc = "Checks if the value of the field is `_0011`"]
101    #[inline(always)]
102    pub fn is_0011(&self) -> bool {
103        *self == CLKDIV_A::_0011
104    }
105    #[doc = "Checks if the value of the field is `_0100`"]
106    #[inline(always)]
107    pub fn is_0100(&self) -> bool {
108        *self == CLKDIV_A::_0100
109    }
110    #[doc = "Checks if the value of the field is `_0101`"]
111    #[inline(always)]
112    pub fn is_0101(&self) -> bool {
113        *self == CLKDIV_A::_0101
114    }
115    #[doc = "Checks if the value of the field is `_0110`"]
116    #[inline(always)]
117    pub fn is_0110(&self) -> bool {
118        *self == CLKDIV_A::_0110
119    }
120    #[doc = "Checks if the value of the field is `_0111`"]
121    #[inline(always)]
122    pub fn is_0111(&self) -> bool {
123        *self == CLKDIV_A::_0111
124    }
125    #[doc = "Checks if the value of the field is `_1000`"]
126    #[inline(always)]
127    pub fn is_1000(&self) -> bool {
128        *self == CLKDIV_A::_1000
129    }
130}
131#[doc = "Field `CLKDIV` writer - SDADC24 reference clock division select"]
132pub type CLKDIV_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STC1_SPEC, u8, CLKDIV_A, 4, O>;
133impl<'a, const O: u8> CLKDIV_W<'a, O> {
134    #[doc = "SDADCCLK (no division)"]
135    #[inline(always)]
136    pub fn _0000(self) -> &'a mut W {
137        self.variant(CLKDIV_A::_0000)
138    }
139    #[doc = "SDADCCLK/2 (1/2)"]
140    #[inline(always)]
141    pub fn _0001(self) -> &'a mut W {
142        self.variant(CLKDIV_A::_0001)
143    }
144    #[doc = "SDADCCLK/3 (1/3)"]
145    #[inline(always)]
146    pub fn _0010(self) -> &'a mut W {
147        self.variant(CLKDIV_A::_0010)
148    }
149    #[doc = "SDADCCLK/4 (1/4)"]
150    #[inline(always)]
151    pub fn _0011(self) -> &'a mut W {
152        self.variant(CLKDIV_A::_0011)
153    }
154    #[doc = "SDADCCLK/5 (1/5)"]
155    #[inline(always)]
156    pub fn _0100(self) -> &'a mut W {
157        self.variant(CLKDIV_A::_0100)
158    }
159    #[doc = "SDADCCLK/6 (1/6)"]
160    #[inline(always)]
161    pub fn _0101(self) -> &'a mut W {
162        self.variant(CLKDIV_A::_0101)
163    }
164    #[doc = "SDADCCLK/8 (1/8)"]
165    #[inline(always)]
166    pub fn _0110(self) -> &'a mut W {
167        self.variant(CLKDIV_A::_0110)
168    }
169    #[doc = "SDADCCLK/12 (1/12)"]
170    #[inline(always)]
171    pub fn _0111(self) -> &'a mut W {
172        self.variant(CLKDIV_A::_0111)
173    }
174    #[doc = "SDADCCLK/16 (1/16)."]
175    #[inline(always)]
176    pub fn _1000(self) -> &'a mut W {
177        self.variant(CLKDIV_A::_1000)
178    }
179}
180#[doc = "Field `SDADLPM` reader - A/D conversion operation mode select"]
181pub type SDADLPM_R = crate::BitReader<SDADLPM_A>;
182#[doc = "A/D conversion operation mode select\n\nValue on reset: 0"]
183#[derive(Clone, Copy, Debug, PartialEq, Eq)]
184pub enum SDADLPM_A {
185    #[doc = "0: Normal A/D conversion mode: SDADC24 reference clock:4 MHz, Oversampling clock:1 MHz"]
186    _0 = 0,
187    #[doc = "1: Low-power A/D conversion mode(1/8 of the clock in normal A/D conversion mode): SDADC24 reference clock:500 kHz,Oversampling clock: 125 kHz"]
188    _1 = 1,
189}
190impl From<SDADLPM_A> for bool {
191    #[inline(always)]
192    fn from(variant: SDADLPM_A) -> Self {
193        variant as u8 != 0
194    }
195}
196impl SDADLPM_R {
197    #[doc = "Get enumerated values variant"]
198    #[inline(always)]
199    pub fn variant(&self) -> SDADLPM_A {
200        match self.bits {
201            false => SDADLPM_A::_0,
202            true => SDADLPM_A::_1,
203        }
204    }
205    #[doc = "Checks if the value of the field is `_0`"]
206    #[inline(always)]
207    pub fn is_0(&self) -> bool {
208        *self == SDADLPM_A::_0
209    }
210    #[doc = "Checks if the value of the field is `_1`"]
211    #[inline(always)]
212    pub fn is_1(&self) -> bool {
213        *self == SDADLPM_A::_1
214    }
215}
216#[doc = "Field `SDADLPM` writer - A/D conversion operation mode select"]
217pub type SDADLPM_W<'a, const O: u8> = crate::BitWriter<'a, u16, STC1_SPEC, SDADLPM_A, O>;
218impl<'a, const O: u8> SDADLPM_W<'a, O> {
219    #[doc = "Normal A/D conversion mode: SDADC24 reference clock:4 MHz, Oversampling clock:1 MHz"]
220    #[inline(always)]
221    pub fn _0(self) -> &'a mut W {
222        self.variant(SDADLPM_A::_0)
223    }
224    #[doc = "Low-power A/D conversion mode(1/8 of the clock in normal A/D conversion mode): SDADC24 reference clock:500 kHz,Oversampling clock: 125 kHz"]
225    #[inline(always)]
226    pub fn _1(self) -> &'a mut W {
227        self.variant(SDADLPM_A::_1)
228    }
229}
230#[doc = "Field `VSBIAS` reader - Reference voltage select"]
231pub type VSBIAS_R = crate::FieldReader<u8, VSBIAS_A>;
232#[doc = "Reference voltage select\n\nValue on reset: 0"]
233#[derive(Clone, Copy, Debug, PartialEq, Eq)]
234#[repr(u8)]
235pub enum VSBIAS_A {
236    #[doc = "0: 0.8 V"]
237    _0000 = 0,
238    #[doc = "1: 1.0 V"]
239    _0001 = 1,
240    #[doc = "2: 1.2 V"]
241    _0010 = 2,
242    #[doc = "3: 1.4 V"]
243    _0011 = 3,
244    #[doc = "4: 1.6 V"]
245    _0100 = 4,
246    #[doc = "5: 1.8 V"]
247    _0101 = 5,
248    #[doc = "6: 2.0 V"]
249    _0110 = 6,
250    #[doc = "7: 2.2 V"]
251    _0111 = 7,
252    #[doc = "15: 2.4 V (This voltage can be set only if VREFSEL = 1. When VREFSEL = 0, 2.2 V is set (rather than 2.4 V))"]
253    _1111 = 15,
254}
255impl From<VSBIAS_A> for u8 {
256    #[inline(always)]
257    fn from(variant: VSBIAS_A) -> Self {
258        variant as _
259    }
260}
261impl VSBIAS_R {
262    #[doc = "Get enumerated values variant"]
263    #[inline(always)]
264    pub fn variant(&self) -> Option<VSBIAS_A> {
265        match self.bits {
266            0 => Some(VSBIAS_A::_0000),
267            1 => Some(VSBIAS_A::_0001),
268            2 => Some(VSBIAS_A::_0010),
269            3 => Some(VSBIAS_A::_0011),
270            4 => Some(VSBIAS_A::_0100),
271            5 => Some(VSBIAS_A::_0101),
272            6 => Some(VSBIAS_A::_0110),
273            7 => Some(VSBIAS_A::_0111),
274            15 => Some(VSBIAS_A::_1111),
275            _ => None,
276        }
277    }
278    #[doc = "Checks if the value of the field is `_0000`"]
279    #[inline(always)]
280    pub fn is_0000(&self) -> bool {
281        *self == VSBIAS_A::_0000
282    }
283    #[doc = "Checks if the value of the field is `_0001`"]
284    #[inline(always)]
285    pub fn is_0001(&self) -> bool {
286        *self == VSBIAS_A::_0001
287    }
288    #[doc = "Checks if the value of the field is `_0010`"]
289    #[inline(always)]
290    pub fn is_0010(&self) -> bool {
291        *self == VSBIAS_A::_0010
292    }
293    #[doc = "Checks if the value of the field is `_0011`"]
294    #[inline(always)]
295    pub fn is_0011(&self) -> bool {
296        *self == VSBIAS_A::_0011
297    }
298    #[doc = "Checks if the value of the field is `_0100`"]
299    #[inline(always)]
300    pub fn is_0100(&self) -> bool {
301        *self == VSBIAS_A::_0100
302    }
303    #[doc = "Checks if the value of the field is `_0101`"]
304    #[inline(always)]
305    pub fn is_0101(&self) -> bool {
306        *self == VSBIAS_A::_0101
307    }
308    #[doc = "Checks if the value of the field is `_0110`"]
309    #[inline(always)]
310    pub fn is_0110(&self) -> bool {
311        *self == VSBIAS_A::_0110
312    }
313    #[doc = "Checks if the value of the field is `_0111`"]
314    #[inline(always)]
315    pub fn is_0111(&self) -> bool {
316        *self == VSBIAS_A::_0111
317    }
318    #[doc = "Checks if the value of the field is `_1111`"]
319    #[inline(always)]
320    pub fn is_1111(&self) -> bool {
321        *self == VSBIAS_A::_1111
322    }
323}
324#[doc = "Field `VSBIAS` writer - Reference voltage select"]
325pub type VSBIAS_W<'a, const O: u8> = crate::FieldWriter<'a, u16, STC1_SPEC, u8, VSBIAS_A, 4, O>;
326impl<'a, const O: u8> VSBIAS_W<'a, O> {
327    #[doc = "0.8 V"]
328    #[inline(always)]
329    pub fn _0000(self) -> &'a mut W {
330        self.variant(VSBIAS_A::_0000)
331    }
332    #[doc = "1.0 V"]
333    #[inline(always)]
334    pub fn _0001(self) -> &'a mut W {
335        self.variant(VSBIAS_A::_0001)
336    }
337    #[doc = "1.2 V"]
338    #[inline(always)]
339    pub fn _0010(self) -> &'a mut W {
340        self.variant(VSBIAS_A::_0010)
341    }
342    #[doc = "1.4 V"]
343    #[inline(always)]
344    pub fn _0011(self) -> &'a mut W {
345        self.variant(VSBIAS_A::_0011)
346    }
347    #[doc = "1.6 V"]
348    #[inline(always)]
349    pub fn _0100(self) -> &'a mut W {
350        self.variant(VSBIAS_A::_0100)
351    }
352    #[doc = "1.8 V"]
353    #[inline(always)]
354    pub fn _0101(self) -> &'a mut W {
355        self.variant(VSBIAS_A::_0101)
356    }
357    #[doc = "2.0 V"]
358    #[inline(always)]
359    pub fn _0110(self) -> &'a mut W {
360        self.variant(VSBIAS_A::_0110)
361    }
362    #[doc = "2.2 V"]
363    #[inline(always)]
364    pub fn _0111(self) -> &'a mut W {
365        self.variant(VSBIAS_A::_0111)
366    }
367    #[doc = "2.4 V (This voltage can be set only if VREFSEL = 1. When VREFSEL = 0, 2.2 V is set (rather than 2.4 V))"]
368    #[inline(always)]
369    pub fn _1111(self) -> &'a mut W {
370        self.variant(VSBIAS_A::_1111)
371    }
372}
373#[doc = "Field `VREFSEL` reader - VREF mode select"]
374pub type VREFSEL_R = crate::BitReader<VREFSEL_A>;
375#[doc = "VREF mode select\n\nValue on reset: 1"]
376#[derive(Clone, Copy, Debug, PartialEq, Eq)]
377pub enum VREFSEL_A {
378    #[doc = "0: Internal VREF mode"]
379    _0 = 0,
380    #[doc = "1: External VREF mode"]
381    _1 = 1,
382}
383impl From<VREFSEL_A> for bool {
384    #[inline(always)]
385    fn from(variant: VREFSEL_A) -> Self {
386        variant as u8 != 0
387    }
388}
389impl VREFSEL_R {
390    #[doc = "Get enumerated values variant"]
391    #[inline(always)]
392    pub fn variant(&self) -> VREFSEL_A {
393        match self.bits {
394            false => VREFSEL_A::_0,
395            true => VREFSEL_A::_1,
396        }
397    }
398    #[doc = "Checks if the value of the field is `_0`"]
399    #[inline(always)]
400    pub fn is_0(&self) -> bool {
401        *self == VREFSEL_A::_0
402    }
403    #[doc = "Checks if the value of the field is `_1`"]
404    #[inline(always)]
405    pub fn is_1(&self) -> bool {
406        *self == VREFSEL_A::_1
407    }
408}
409#[doc = "Field `VREFSEL` writer - VREF mode select"]
410pub type VREFSEL_W<'a, const O: u8> = crate::BitWriter<'a, u16, STC1_SPEC, VREFSEL_A, O>;
411impl<'a, const O: u8> VREFSEL_W<'a, O> {
412    #[doc = "Internal VREF mode"]
413    #[inline(always)]
414    pub fn _0(self) -> &'a mut W {
415        self.variant(VREFSEL_A::_0)
416    }
417    #[doc = "External VREF mode"]
418    #[inline(always)]
419    pub fn _1(self) -> &'a mut W {
420        self.variant(VREFSEL_A::_1)
421    }
422}
423impl R {
424    #[doc = "Bits 0:3 - SDADC24 reference clock division select"]
425    #[inline(always)]
426    pub fn clkdiv(&self) -> CLKDIV_R {
427        CLKDIV_R::new((self.bits & 0x0f) as u8)
428    }
429    #[doc = "Bit 7 - A/D conversion operation mode select"]
430    #[inline(always)]
431    pub fn sdadlpm(&self) -> SDADLPM_R {
432        SDADLPM_R::new(((self.bits >> 7) & 1) != 0)
433    }
434    #[doc = "Bits 8:11 - Reference voltage select"]
435    #[inline(always)]
436    pub fn vsbias(&self) -> VSBIAS_R {
437        VSBIAS_R::new(((self.bits >> 8) & 0x0f) as u8)
438    }
439    #[doc = "Bit 15 - VREF mode select"]
440    #[inline(always)]
441    pub fn vrefsel(&self) -> VREFSEL_R {
442        VREFSEL_R::new(((self.bits >> 15) & 1) != 0)
443    }
444}
445impl W {
446    #[doc = "Bits 0:3 - SDADC24 reference clock division select"]
447    #[inline(always)]
448    #[must_use]
449    pub fn clkdiv(&mut self) -> CLKDIV_W<0> {
450        CLKDIV_W::new(self)
451    }
452    #[doc = "Bit 7 - A/D conversion operation mode select"]
453    #[inline(always)]
454    #[must_use]
455    pub fn sdadlpm(&mut self) -> SDADLPM_W<7> {
456        SDADLPM_W::new(self)
457    }
458    #[doc = "Bits 8:11 - Reference voltage select"]
459    #[inline(always)]
460    #[must_use]
461    pub fn vsbias(&mut self) -> VSBIAS_W<8> {
462        VSBIAS_W::new(self)
463    }
464    #[doc = "Bit 15 - VREF mode select"]
465    #[inline(always)]
466    #[must_use]
467    pub fn vrefsel(&mut self) -> VREFSEL_W<15> {
468        VREFSEL_W::new(self)
469    }
470    #[doc = "Writes raw bits to the register."]
471    #[inline(always)]
472    pub unsafe fn bits(&mut self, bits: u16) -> &mut Self {
473        self.0.bits(bits);
474        self
475    }
476}
477#[doc = "Startup Control Register 1\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [stc1](index.html) module"]
478pub struct STC1_SPEC;
479impl crate::RegisterSpec for STC1_SPEC {
480    type Ux = u16;
481}
482#[doc = "`read()` method returns [stc1::R](R) reader structure"]
483impl crate::Readable for STC1_SPEC {
484    type Reader = R;
485}
486#[doc = "`write(|w| ..)` method takes [stc1::W](W) writer structure"]
487impl crate::Writable for STC1_SPEC {
488    type Writer = W;
489    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
490    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
491}
492#[doc = "`reset()` method sets STC1 to value 0x8008"]
493impl crate::Resettable for STC1_SPEC {
494    const RESET_VALUE: Self::Ux = 0x8008;
495}
ra2a1/sdadc24/stc1.rs

ra2a1/sdadc24/
stc1.rs
