1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Watchdog Timer"]
28unsafe impl ::core::marker::Send for super::Wdt {}
29unsafe impl ::core::marker::Sync for super::Wdt {}
30impl super::Wdt {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "WDT Refresh Register"]
38 #[inline(always)]
39 pub const fn wdtrr(&self) -> &'static crate::common::Reg<self::Wdtrr_SPEC, crate::common::RW> {
40 unsafe {
41 crate::common::Reg::<self::Wdtrr_SPEC, crate::common::RW>::from_ptr(
42 self._svd2pac_as_ptr().add(0usize),
43 )
44 }
45 }
46
47 #[doc = "WDT Control Register"]
48 #[inline(always)]
49 pub const fn wdtcr(&self) -> &'static crate::common::Reg<self::Wdtcr_SPEC, crate::common::RW> {
50 unsafe {
51 crate::common::Reg::<self::Wdtcr_SPEC, crate::common::RW>::from_ptr(
52 self._svd2pac_as_ptr().add(2usize),
53 )
54 }
55 }
56
57 #[doc = "WDT Status Register"]
58 #[inline(always)]
59 pub const fn wdtsr(&self) -> &'static crate::common::Reg<self::Wdtsr_SPEC, crate::common::RW> {
60 unsafe {
61 crate::common::Reg::<self::Wdtsr_SPEC, crate::common::RW>::from_ptr(
62 self._svd2pac_as_ptr().add(4usize),
63 )
64 }
65 }
66
67 #[doc = "WDT Reset Control Register"]
68 #[inline(always)]
69 pub const fn wdtrcr(
70 &self,
71 ) -> &'static crate::common::Reg<self::Wdtrcr_SPEC, crate::common::RW> {
72 unsafe {
73 crate::common::Reg::<self::Wdtrcr_SPEC, crate::common::RW>::from_ptr(
74 self._svd2pac_as_ptr().add(6usize),
75 )
76 }
77 }
78
79 #[doc = "WDT Count Stop Control Register"]
80 #[inline(always)]
81 pub const fn wdtcstpr(
82 &self,
83 ) -> &'static crate::common::Reg<self::Wdtcstpr_SPEC, crate::common::RW> {
84 unsafe {
85 crate::common::Reg::<self::Wdtcstpr_SPEC, crate::common::RW>::from_ptr(
86 self._svd2pac_as_ptr().add(8usize),
87 )
88 }
89 }
90}
91#[doc(hidden)]
92#[derive(Copy, Clone, Eq, PartialEq)]
93pub struct Wdtrr_SPEC;
94impl crate::sealed::RegSpec for Wdtrr_SPEC {
95 type DataType = u8;
96}
97
98#[doc = "WDT Refresh Register"]
99pub type Wdtrr = crate::RegValueT<Wdtrr_SPEC>;
100
101impl Wdtrr {
102 #[doc = "WDTRR is an 8-bit register that refreshes the down-counter of the WDT."]
103 #[inline(always)]
104 pub fn wdtrr(
105 self,
106 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Wdtrr_SPEC, crate::common::RW> {
107 crate::common::RegisterField::<0,0xff,1,0,u8,u8,Wdtrr_SPEC,crate::common::RW>::from_register(self,0)
108 }
109}
110impl ::core::default::Default for Wdtrr {
111 #[inline(always)]
112 fn default() -> Wdtrr {
113 <crate::RegValueT<Wdtrr_SPEC> as RegisterValue<_>>::new(255)
114 }
115}
116
117#[doc(hidden)]
118#[derive(Copy, Clone, Eq, PartialEq)]
119pub struct Wdtcr_SPEC;
120impl crate::sealed::RegSpec for Wdtcr_SPEC {
121 type DataType = u16;
122}
123
124#[doc = "WDT Control Register"]
125pub type Wdtcr = crate::RegValueT<Wdtcr_SPEC>;
126
127impl Wdtcr {
128 #[doc = "Window Start Position Selection"]
129 #[inline(always)]
130 pub fn rpss(
131 self,
132 ) -> crate::common::RegisterField<
133 12,
134 0x3,
135 1,
136 0,
137 wdtcr::Rpss,
138 wdtcr::Rpss,
139 Wdtcr_SPEC,
140 crate::common::RW,
141 > {
142 crate::common::RegisterField::<
143 12,
144 0x3,
145 1,
146 0,
147 wdtcr::Rpss,
148 wdtcr::Rpss,
149 Wdtcr_SPEC,
150 crate::common::RW,
151 >::from_register(self, 0)
152 }
153
154 #[doc = "Window End Position Selection"]
155 #[inline(always)]
156 pub fn rpes(
157 self,
158 ) -> crate::common::RegisterField<
159 8,
160 0x3,
161 1,
162 0,
163 wdtcr::Rpes,
164 wdtcr::Rpes,
165 Wdtcr_SPEC,
166 crate::common::RW,
167 > {
168 crate::common::RegisterField::<
169 8,
170 0x3,
171 1,
172 0,
173 wdtcr::Rpes,
174 wdtcr::Rpes,
175 Wdtcr_SPEC,
176 crate::common::RW,
177 >::from_register(self, 0)
178 }
179
180 #[doc = "Clock Division Ratio Selection"]
181 #[inline(always)]
182 pub fn cks(
183 self,
184 ) -> crate::common::RegisterField<
185 4,
186 0xf,
187 1,
188 0,
189 wdtcr::Cks,
190 wdtcr::Cks,
191 Wdtcr_SPEC,
192 crate::common::RW,
193 > {
194 crate::common::RegisterField::<
195 4,
196 0xf,
197 1,
198 0,
199 wdtcr::Cks,
200 wdtcr::Cks,
201 Wdtcr_SPEC,
202 crate::common::RW,
203 >::from_register(self, 0)
204 }
205
206 #[doc = "These bits are read as 00. The write value should be 00."]
207 #[inline(always)]
208 pub fn reserved(
209 self,
210 ) -> crate::common::RegisterField<2, 0x3, 1, 0, u8, u8, Wdtcr_SPEC, crate::common::RW> {
211 crate::common::RegisterField::<2,0x3,1,0,u8,u8,Wdtcr_SPEC,crate::common::RW>::from_register(self,0)
212 }
213
214 #[doc = "Timeout Period Selection"]
215 #[inline(always)]
216 pub fn tops(
217 self,
218 ) -> crate::common::RegisterField<
219 0,
220 0x3,
221 1,
222 0,
223 wdtcr::Tops,
224 wdtcr::Tops,
225 Wdtcr_SPEC,
226 crate::common::RW,
227 > {
228 crate::common::RegisterField::<
229 0,
230 0x3,
231 1,
232 0,
233 wdtcr::Tops,
234 wdtcr::Tops,
235 Wdtcr_SPEC,
236 crate::common::RW,
237 >::from_register(self, 0)
238 }
239}
240impl ::core::default::Default for Wdtcr {
241 #[inline(always)]
242 fn default() -> Wdtcr {
243 <crate::RegValueT<Wdtcr_SPEC> as RegisterValue<_>>::new(13299)
244 }
245}
246pub mod wdtcr {
247
248 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
249 pub struct Rpss_SPEC;
250 pub type Rpss = crate::EnumBitfieldStruct<u8, Rpss_SPEC>;
251 impl Rpss {
252 #[doc = "25 percent"]
253 pub const _00: Self = Self::new(0);
254
255 #[doc = "50 percent"]
256 pub const _01: Self = Self::new(1);
257
258 #[doc = "75 percent"]
259 pub const _10: Self = Self::new(2);
260
261 #[doc = "100 percent (window start position is not specified)"]
262 pub const _11: Self = Self::new(3);
263 }
264 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
265 pub struct Rpes_SPEC;
266 pub type Rpes = crate::EnumBitfieldStruct<u8, Rpes_SPEC>;
267 impl Rpes {
268 #[doc = "75 percent"]
269 pub const _00: Self = Self::new(0);
270
271 #[doc = "50 percent"]
272 pub const _01: Self = Self::new(1);
273
274 #[doc = "25 percent"]
275 pub const _10: Self = Self::new(2);
276
277 #[doc = "0 percent (window end position is not specified)"]
278 pub const _11: Self = Self::new(3);
279 }
280 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
281 pub struct Cks_SPEC;
282 pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
283 impl Cks {
284 #[doc = "PCLK/4"]
285 pub const _0001: Self = Self::new(1);
286
287 #[doc = "PCLK/64"]
288 pub const _0100: Self = Self::new(4);
289
290 #[doc = "PCLK/128"]
291 pub const _1111: Self = Self::new(15);
292
293 #[doc = "PCLK/512"]
294 pub const _0110: Self = Self::new(6);
295
296 #[doc = "PCLK/2048"]
297 pub const _0111: Self = Self::new(7);
298
299 #[doc = "PCLK/8192"]
300 pub const _1000: Self = Self::new(8);
301 }
302 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
303 pub struct Tops_SPEC;
304 pub type Tops = crate::EnumBitfieldStruct<u8, Tops_SPEC>;
305 impl Tops {
306 #[doc = "1,024 cycles (03FFh)"]
307 pub const _00: Self = Self::new(0);
308
309 #[doc = "4,096 cycles (0FFFh)"]
310 pub const _01: Self = Self::new(1);
311
312 #[doc = "8,192 cycles (1FFFh)"]
313 pub const _10: Self = Self::new(2);
314
315 #[doc = "16,384 cycles (3FFFh)"]
316 pub const _11: Self = Self::new(3);
317 }
318}
319#[doc(hidden)]
320#[derive(Copy, Clone, Eq, PartialEq)]
321pub struct Wdtsr_SPEC;
322impl crate::sealed::RegSpec for Wdtsr_SPEC {
323 type DataType = u16;
324}
325
326#[doc = "WDT Status Register"]
327pub type Wdtsr = crate::RegValueT<Wdtsr_SPEC>;
328
329impl Wdtsr {
330 #[doc = "Refresh Error Flag"]
331 #[inline(always)]
332 pub fn refef(
333 self,
334 ) -> crate::common::RegisterField<
335 15,
336 0x1,
337 1,
338 0,
339 wdtsr::Refef,
340 wdtsr::Refef,
341 Wdtsr_SPEC,
342 crate::common::RW,
343 > {
344 crate::common::RegisterField::<
345 15,
346 0x1,
347 1,
348 0,
349 wdtsr::Refef,
350 wdtsr::Refef,
351 Wdtsr_SPEC,
352 crate::common::RW,
353 >::from_register(self, 0)
354 }
355
356 #[doc = "Underflow Flag"]
357 #[inline(always)]
358 pub fn undff(
359 self,
360 ) -> crate::common::RegisterField<
361 14,
362 0x1,
363 1,
364 0,
365 wdtsr::Undff,
366 wdtsr::Undff,
367 Wdtsr_SPEC,
368 crate::common::RW,
369 > {
370 crate::common::RegisterField::<
371 14,
372 0x1,
373 1,
374 0,
375 wdtsr::Undff,
376 wdtsr::Undff,
377 Wdtsr_SPEC,
378 crate::common::RW,
379 >::from_register(self, 0)
380 }
381
382 #[doc = "Down-Counter ValueValue counted by the down-counter"]
383 #[inline(always)]
384 pub fn cntval(
385 self,
386 ) -> crate::common::RegisterField<0, 0x3fff, 1, 0, u16, u16, Wdtsr_SPEC, crate::common::R> {
387 crate::common::RegisterField::<0,0x3fff,1,0,u16,u16,Wdtsr_SPEC,crate::common::R>::from_register(self,0)
388 }
389}
390impl ::core::default::Default for Wdtsr {
391 #[inline(always)]
392 fn default() -> Wdtsr {
393 <crate::RegValueT<Wdtsr_SPEC> as RegisterValue<_>>::new(0)
394 }
395}
396pub mod wdtsr {
397
398 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
399 pub struct Refef_SPEC;
400 pub type Refef = crate::EnumBitfieldStruct<u8, Refef_SPEC>;
401 impl Refef {
402 #[doc = "No refresh error occurred"]
403 pub const _0: Self = Self::new(0);
404
405 #[doc = "Refresh error occurred"]
406 pub const _1: Self = Self::new(1);
407 }
408 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
409 pub struct Undff_SPEC;
410 pub type Undff = crate::EnumBitfieldStruct<u8, Undff_SPEC>;
411 impl Undff {
412 #[doc = "No underflow occurred"]
413 pub const _0: Self = Self::new(0);
414
415 #[doc = "Underflow occurred"]
416 pub const _1: Self = Self::new(1);
417 }
418}
419#[doc(hidden)]
420#[derive(Copy, Clone, Eq, PartialEq)]
421pub struct Wdtrcr_SPEC;
422impl crate::sealed::RegSpec for Wdtrcr_SPEC {
423 type DataType = u8;
424}
425
426#[doc = "WDT Reset Control Register"]
427pub type Wdtrcr = crate::RegValueT<Wdtrcr_SPEC>;
428
429impl Wdtrcr {
430 #[doc = "Reset Interrupt Request Selection"]
431 #[inline(always)]
432 pub fn rstirqs(
433 self,
434 ) -> crate::common::RegisterField<
435 7,
436 0x1,
437 1,
438 0,
439 wdtrcr::Rstirqs,
440 wdtrcr::Rstirqs,
441 Wdtrcr_SPEC,
442 crate::common::RW,
443 > {
444 crate::common::RegisterField::<
445 7,
446 0x1,
447 1,
448 0,
449 wdtrcr::Rstirqs,
450 wdtrcr::Rstirqs,
451 Wdtrcr_SPEC,
452 crate::common::RW,
453 >::from_register(self, 0)
454 }
455}
456impl ::core::default::Default for Wdtrcr {
457 #[inline(always)]
458 fn default() -> Wdtrcr {
459 <crate::RegValueT<Wdtrcr_SPEC> as RegisterValue<_>>::new(128)
460 }
461}
462pub mod wdtrcr {
463
464 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
465 pub struct Rstirqs_SPEC;
466 pub type Rstirqs = crate::EnumBitfieldStruct<u8, Rstirqs_SPEC>;
467 impl Rstirqs {
468 #[doc = "Non-maskable interrupt request or interrupt request output is enabled"]
469 pub const _0: Self = Self::new(0);
470
471 #[doc = "Reset output is enabled."]
472 pub const _1: Self = Self::new(1);
473 }
474}
475#[doc(hidden)]
476#[derive(Copy, Clone, Eq, PartialEq)]
477pub struct Wdtcstpr_SPEC;
478impl crate::sealed::RegSpec for Wdtcstpr_SPEC {
479 type DataType = u8;
480}
481
482#[doc = "WDT Count Stop Control Register"]
483pub type Wdtcstpr = crate::RegValueT<Wdtcstpr_SPEC>;
484
485impl Wdtcstpr {
486 #[doc = "Sleep-Mode Count Stop Control"]
487 #[inline(always)]
488 pub fn slcstp(
489 self,
490 ) -> crate::common::RegisterField<
491 7,
492 0x1,
493 1,
494 0,
495 wdtcstpr::Slcstp,
496 wdtcstpr::Slcstp,
497 Wdtcstpr_SPEC,
498 crate::common::RW,
499 > {
500 crate::common::RegisterField::<
501 7,
502 0x1,
503 1,
504 0,
505 wdtcstpr::Slcstp,
506 wdtcstpr::Slcstp,
507 Wdtcstpr_SPEC,
508 crate::common::RW,
509 >::from_register(self, 0)
510 }
511
512 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
513 #[inline(always)]
514 pub fn reserved(
515 self,
516 ) -> crate::common::RegisterField<0, 0x7f, 1, 0, u8, u8, Wdtcstpr_SPEC, crate::common::RW> {
517 crate::common::RegisterField::<0,0x7f,1,0,u8,u8,Wdtcstpr_SPEC,crate::common::RW>::from_register(self,0)
518 }
519}
520impl ::core::default::Default for Wdtcstpr {
521 #[inline(always)]
522 fn default() -> Wdtcstpr {
523 <crate::RegValueT<Wdtcstpr_SPEC> as RegisterValue<_>>::new(128)
524 }
525}
526pub mod wdtcstpr {
527
528 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
529 pub struct Slcstp_SPEC;
530 pub type Slcstp = crate::EnumBitfieldStruct<u8, Slcstp_SPEC>;
531 impl Slcstp {
532 #[doc = "Count stop is disabled."]
533 pub const _0: Self = Self::new(0);
534
535 #[doc = "Count is stopped at a transition to sleep mode."]
536 pub const _1: Self = Self::new(1);
537 }
538}