1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"SRAM Control"]
28unsafe impl ::core::marker::Send for super::Sram {}
29unsafe impl ::core::marker::Sync for super::Sram {}
30impl super::Sram {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "SRAM Parity Error Operation After Detection Register"]
38 #[inline(always)]
39 pub const fn parioad(
40 &self,
41 ) -> &'static crate::common::Reg<self::Parioad_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Parioad_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "SRAM Protection Register"]
50 #[inline(always)]
51 pub const fn sramprcr(
52 &self,
53 ) -> &'static crate::common::Reg<self::Sramprcr_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Sramprcr_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(4usize),
57 )
58 }
59 }
60
61 #[doc = "ECC Operating Mode Control Register"]
62 #[inline(always)]
63 pub const fn eccmode(
64 &self,
65 ) -> &'static crate::common::Reg<self::Eccmode_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Eccmode_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(192usize),
69 )
70 }
71 }
72
73 #[doc = "ECC 2-Bit Error Status Register"]
74 #[inline(always)]
75 pub const fn ecc2sts(
76 &self,
77 ) -> &'static crate::common::Reg<self::Ecc2Sts_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::Ecc2Sts_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(193usize),
81 )
82 }
83 }
84
85 #[doc = "ECC 1-Bit Error Information Update Enable Register"]
86 #[inline(always)]
87 pub const fn ecc1stsen(
88 &self,
89 ) -> &'static crate::common::Reg<self::Ecc1Stsen_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Ecc1Stsen_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(194usize),
93 )
94 }
95 }
96
97 #[doc = "ECC 1-Bit Error Status Register"]
98 #[inline(always)]
99 pub const fn ecc1sts(
100 &self,
101 ) -> &'static crate::common::Reg<self::Ecc1Sts_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::Ecc1Sts_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(195usize),
105 )
106 }
107 }
108
109 #[doc = "ECC Protection Register"]
110 #[inline(always)]
111 pub const fn eccprcr(
112 &self,
113 ) -> &'static crate::common::Reg<self::Eccprcr_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::Eccprcr_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(196usize),
117 )
118 }
119 }
120
121 #[doc = "ECC Protection Register 2"]
122 #[inline(always)]
123 pub const fn eccprcr2(
124 &self,
125 ) -> &'static crate::common::Reg<self::Eccprcr2_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::Eccprcr2_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(208usize),
129 )
130 }
131 }
132
133 #[doc = "ECC Test Control Register"]
134 #[inline(always)]
135 pub const fn eccetst(
136 &self,
137 ) -> &'static crate::common::Reg<self::Eccetst_SPEC, crate::common::RW> {
138 unsafe {
139 crate::common::Reg::<self::Eccetst_SPEC, crate::common::RW>::from_ptr(
140 self._svd2pac_as_ptr().add(212usize),
141 )
142 }
143 }
144
145 #[doc = "SRAM ECC Error Operation After Detection Register"]
146 #[inline(always)]
147 pub const fn eccoad(
148 &self,
149 ) -> &'static crate::common::Reg<self::Eccoad_SPEC, crate::common::RW> {
150 unsafe {
151 crate::common::Reg::<self::Eccoad_SPEC, crate::common::RW>::from_ptr(
152 self._svd2pac_as_ptr().add(216usize),
153 )
154 }
155 }
156}
157#[doc(hidden)]
158#[derive(Copy, Clone, Eq, PartialEq)]
159pub struct Parioad_SPEC;
160impl crate::sealed::RegSpec for Parioad_SPEC {
161 type DataType = u8;
162}
163
164#[doc = "SRAM Parity Error Operation After Detection Register"]
165pub type Parioad = crate::RegValueT<Parioad_SPEC>;
166
167impl Parioad {
168 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
169 #[inline(always)]
170 pub fn reserved(
171 self,
172 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Parioad_SPEC, crate::common::RW> {
173 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Parioad_SPEC,crate::common::RW>::from_register(self,0)
174 }
175
176 #[doc = "Operation after Detection"]
177 #[inline(always)]
178 pub fn oad(
179 self,
180 ) -> crate::common::RegisterField<
181 0,
182 0x1,
183 1,
184 0,
185 parioad::Oad,
186 parioad::Oad,
187 Parioad_SPEC,
188 crate::common::RW,
189 > {
190 crate::common::RegisterField::<
191 0,
192 0x1,
193 1,
194 0,
195 parioad::Oad,
196 parioad::Oad,
197 Parioad_SPEC,
198 crate::common::RW,
199 >::from_register(self, 0)
200 }
201}
202impl ::core::default::Default for Parioad {
203 #[inline(always)]
204 fn default() -> Parioad {
205 <crate::RegValueT<Parioad_SPEC> as RegisterValue<_>>::new(0)
206 }
207}
208pub mod parioad {
209
210 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
211 pub struct Oad_SPEC;
212 pub type Oad = crate::EnumBitfieldStruct<u8, Oad_SPEC>;
213 impl Oad {
214 #[doc = "Reset."]
215 pub const _1: Self = Self::new(1);
216
217 #[doc = "Non maskable interrupt."]
218 pub const _0: Self = Self::new(0);
219 }
220}
221#[doc(hidden)]
222#[derive(Copy, Clone, Eq, PartialEq)]
223pub struct Sramprcr_SPEC;
224impl crate::sealed::RegSpec for Sramprcr_SPEC {
225 type DataType = u8;
226}
227
228#[doc = "SRAM Protection Register"]
229pub type Sramprcr = crate::RegValueT<Sramprcr_SPEC>;
230
231impl Sramprcr {
232 #[doc = "Write Key Code"]
233 #[inline(always)]
234 pub fn kw(
235 self,
236 ) -> crate::common::RegisterField<
237 1,
238 0x7f,
239 1,
240 0,
241 sramprcr::Kw,
242 sramprcr::Kw,
243 Sramprcr_SPEC,
244 crate::common::W,
245 > {
246 crate::common::RegisterField::<
247 1,
248 0x7f,
249 1,
250 0,
251 sramprcr::Kw,
252 sramprcr::Kw,
253 Sramprcr_SPEC,
254 crate::common::W,
255 >::from_register(self, 0)
256 }
257
258 #[doc = "Register Write Control"]
259 #[inline(always)]
260 pub fn sramprcr(
261 self,
262 ) -> crate::common::RegisterField<
263 0,
264 0x1,
265 1,
266 0,
267 sramprcr::Sramprcr,
268 sramprcr::Sramprcr,
269 Sramprcr_SPEC,
270 crate::common::RW,
271 > {
272 crate::common::RegisterField::<
273 0,
274 0x1,
275 1,
276 0,
277 sramprcr::Sramprcr,
278 sramprcr::Sramprcr,
279 Sramprcr_SPEC,
280 crate::common::RW,
281 >::from_register(self, 0)
282 }
283}
284impl ::core::default::Default for Sramprcr {
285 #[inline(always)]
286 fn default() -> Sramprcr {
287 <crate::RegValueT<Sramprcr_SPEC> as RegisterValue<_>>::new(0)
288 }
289}
290pub mod sramprcr {
291
292 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
293 pub struct Kw_SPEC;
294 pub type Kw = crate::EnumBitfieldStruct<u8, Kw_SPEC>;
295 impl Kw {
296 #[doc = "Writing to the RAMPRCR bit is valid, when the KEY bits are written 1111000b."]
297 pub const _1111000: Self = Self::new(120);
298 }
299 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
300 pub struct Sramprcr_SPEC;
301 pub type Sramprcr = crate::EnumBitfieldStruct<u8, Sramprcr_SPEC>;
302 impl Sramprcr {
303 #[doc = "Writing to the protected register is disabled."]
304 pub const _0: Self = Self::new(0);
305
306 #[doc = "Writing to the protected register is enabled."]
307 pub const _1: Self = Self::new(1);
308 }
309}
310#[doc(hidden)]
311#[derive(Copy, Clone, Eq, PartialEq)]
312pub struct Eccmode_SPEC;
313impl crate::sealed::RegSpec for Eccmode_SPEC {
314 type DataType = u8;
315}
316
317#[doc = "ECC Operating Mode Control Register"]
318pub type Eccmode = crate::RegValueT<Eccmode_SPEC>;
319
320impl Eccmode {
321 #[doc = "These bits are read as 000000. The write value should be 000000."]
322 #[inline(always)]
323 pub fn reserved(
324 self,
325 ) -> crate::common::RegisterField<2, 0x3f, 1, 0, u8, u8, Eccmode_SPEC, crate::common::RW> {
326 crate::common::RegisterField::<2,0x3f,1,0,u8,u8,Eccmode_SPEC,crate::common::RW>::from_register(self,0)
327 }
328
329 #[doc = "ECC Operating Mode Select"]
330 #[inline(always)]
331 pub fn eccmod(
332 self,
333 ) -> crate::common::RegisterField<
334 0,
335 0x3,
336 1,
337 0,
338 eccmode::Eccmod,
339 eccmode::Eccmod,
340 Eccmode_SPEC,
341 crate::common::RW,
342 > {
343 crate::common::RegisterField::<
344 0,
345 0x3,
346 1,
347 0,
348 eccmode::Eccmod,
349 eccmode::Eccmod,
350 Eccmode_SPEC,
351 crate::common::RW,
352 >::from_register(self, 0)
353 }
354}
355impl ::core::default::Default for Eccmode {
356 #[inline(always)]
357 fn default() -> Eccmode {
358 <crate::RegValueT<Eccmode_SPEC> as RegisterValue<_>>::new(0)
359 }
360}
361pub mod eccmode {
362
363 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
364 pub struct Eccmod_SPEC;
365 pub type Eccmod = crate::EnumBitfieldStruct<u8, Eccmod_SPEC>;
366 impl Eccmod {
367 #[doc = "ECC is disabled"]
368 pub const _00: Self = Self::new(0);
369
370 #[doc = "Setting prohibited"]
371 pub const _01: Self = Self::new(1);
372
373 #[doc = "ECC is enabled without error checking."]
374 pub const _10: Self = Self::new(2);
375
376 #[doc = "ECC is enabled with error checking."]
377 pub const _11: Self = Self::new(3);
378 }
379}
380#[doc(hidden)]
381#[derive(Copy, Clone, Eq, PartialEq)]
382pub struct Ecc2Sts_SPEC;
383impl crate::sealed::RegSpec for Ecc2Sts_SPEC {
384 type DataType = u8;
385}
386
387#[doc = "ECC 2-Bit Error Status Register"]
388pub type Ecc2Sts = crate::RegValueT<Ecc2Sts_SPEC>;
389
390impl Ecc2Sts {
391 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
392 #[inline(always)]
393 pub fn reserved(
394 self,
395 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Ecc2Sts_SPEC, crate::common::RW> {
396 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Ecc2Sts_SPEC,crate::common::RW>::from_register(self,0)
397 }
398
399 #[doc = "ECC 2-Bit Error Status"]
400 #[inline(always)]
401 pub fn ecc2err(
402 self,
403 ) -> crate::common::RegisterField<
404 0,
405 0x1,
406 1,
407 0,
408 ecc2sts::Ecc2Err,
409 ecc2sts::Ecc2Err,
410 Ecc2Sts_SPEC,
411 crate::common::RW,
412 > {
413 crate::common::RegisterField::<
414 0,
415 0x1,
416 1,
417 0,
418 ecc2sts::Ecc2Err,
419 ecc2sts::Ecc2Err,
420 Ecc2Sts_SPEC,
421 crate::common::RW,
422 >::from_register(self, 0)
423 }
424}
425impl ::core::default::Default for Ecc2Sts {
426 #[inline(always)]
427 fn default() -> Ecc2Sts {
428 <crate::RegValueT<Ecc2Sts_SPEC> as RegisterValue<_>>::new(0)
429 }
430}
431pub mod ecc2sts {
432
433 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
434 pub struct Ecc2Err_SPEC;
435 pub type Ecc2Err = crate::EnumBitfieldStruct<u8, Ecc2Err_SPEC>;
436 impl Ecc2Err {
437 #[doc = "A 2-bit ECC error has not occurred."]
438 pub const _0: Self = Self::new(0);
439
440 #[doc = "A 2-bit ECC error has occurred."]
441 pub const _1: Self = Self::new(1);
442 }
443}
444#[doc(hidden)]
445#[derive(Copy, Clone, Eq, PartialEq)]
446pub struct Ecc1Stsen_SPEC;
447impl crate::sealed::RegSpec for Ecc1Stsen_SPEC {
448 type DataType = u8;
449}
450
451#[doc = "ECC 1-Bit Error Information Update Enable Register"]
452pub type Ecc1Stsen = crate::RegValueT<Ecc1Stsen_SPEC>;
453
454impl Ecc1Stsen {
455 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
456 #[inline(always)]
457 pub fn reserved(
458 self,
459 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Ecc1Stsen_SPEC, crate::common::RW>
460 {
461 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Ecc1Stsen_SPEC,crate::common::RW>::from_register(self,0)
462 }
463
464 #[doc = "ECC 1-Bit Error Information Update Enable"]
465 #[inline(always)]
466 pub fn e1stsen(
467 self,
468 ) -> crate::common::RegisterField<
469 0,
470 0x1,
471 1,
472 0,
473 ecc1stsen::E1Stsen,
474 ecc1stsen::E1Stsen,
475 Ecc1Stsen_SPEC,
476 crate::common::RW,
477 > {
478 crate::common::RegisterField::<
479 0,
480 0x1,
481 1,
482 0,
483 ecc1stsen::E1Stsen,
484 ecc1stsen::E1Stsen,
485 Ecc1Stsen_SPEC,
486 crate::common::RW,
487 >::from_register(self, 0)
488 }
489}
490impl ::core::default::Default for Ecc1Stsen {
491 #[inline(always)]
492 fn default() -> Ecc1Stsen {
493 <crate::RegValueT<Ecc1Stsen_SPEC> as RegisterValue<_>>::new(0)
494 }
495}
496pub mod ecc1stsen {
497
498 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
499 pub struct E1Stsen_SPEC;
500 pub type E1Stsen = crate::EnumBitfieldStruct<u8, E1Stsen_SPEC>;
501 impl E1Stsen {
502 #[doc = "Disables updating of the 1-bit ECC error information."]
503 pub const _0: Self = Self::new(0);
504
505 #[doc = "Enables updating of the 1-bit ECC error information."]
506 pub const _1: Self = Self::new(1);
507 }
508}
509#[doc(hidden)]
510#[derive(Copy, Clone, Eq, PartialEq)]
511pub struct Ecc1Sts_SPEC;
512impl crate::sealed::RegSpec for Ecc1Sts_SPEC {
513 type DataType = u8;
514}
515
516#[doc = "ECC 1-Bit Error Status Register"]
517pub type Ecc1Sts = crate::RegValueT<Ecc1Sts_SPEC>;
518
519impl Ecc1Sts {
520 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
521 #[inline(always)]
522 pub fn reserved(
523 self,
524 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Ecc1Sts_SPEC, crate::common::RW> {
525 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Ecc1Sts_SPEC,crate::common::RW>::from_register(self,0)
526 }
527
528 #[doc = "ECC 1-Bit Error Status"]
529 #[inline(always)]
530 pub fn ecc1err(
531 self,
532 ) -> crate::common::RegisterField<
533 0,
534 0x1,
535 1,
536 0,
537 ecc1sts::Ecc1Err,
538 ecc1sts::Ecc1Err,
539 Ecc1Sts_SPEC,
540 crate::common::RW,
541 > {
542 crate::common::RegisterField::<
543 0,
544 0x1,
545 1,
546 0,
547 ecc1sts::Ecc1Err,
548 ecc1sts::Ecc1Err,
549 Ecc1Sts_SPEC,
550 crate::common::RW,
551 >::from_register(self, 0)
552 }
553}
554impl ::core::default::Default for Ecc1Sts {
555 #[inline(always)]
556 fn default() -> Ecc1Sts {
557 <crate::RegValueT<Ecc1Sts_SPEC> as RegisterValue<_>>::new(0)
558 }
559}
560pub mod ecc1sts {
561
562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
563 pub struct Ecc1Err_SPEC;
564 pub type Ecc1Err = crate::EnumBitfieldStruct<u8, Ecc1Err_SPEC>;
565 impl Ecc1Err {
566 #[doc = "A 1-bit ECC error has not occurred."]
567 pub const _0: Self = Self::new(0);
568
569 #[doc = "A 1-bit ECC error has occurred."]
570 pub const _1: Self = Self::new(1);
571 }
572}
573#[doc(hidden)]
574#[derive(Copy, Clone, Eq, PartialEq)]
575pub struct Eccprcr_SPEC;
576impl crate::sealed::RegSpec for Eccprcr_SPEC {
577 type DataType = u8;
578}
579
580#[doc = "ECC Protection Register"]
581pub type Eccprcr = crate::RegValueT<Eccprcr_SPEC>;
582
583impl Eccprcr {
584 #[doc = "Write Key Code"]
585 #[inline(always)]
586 pub fn kw(
587 self,
588 ) -> crate::common::RegisterField<
589 1,
590 0x7f,
591 1,
592 0,
593 eccprcr::Kw,
594 eccprcr::Kw,
595 Eccprcr_SPEC,
596 crate::common::W,
597 > {
598 crate::common::RegisterField::<
599 1,
600 0x7f,
601 1,
602 0,
603 eccprcr::Kw,
604 eccprcr::Kw,
605 Eccprcr_SPEC,
606 crate::common::W,
607 >::from_register(self, 0)
608 }
609
610 #[doc = "Register Write Control"]
611 #[inline(always)]
612 pub fn eccprcr(
613 self,
614 ) -> crate::common::RegisterField<
615 0,
616 0x1,
617 1,
618 0,
619 eccprcr::Eccprcr,
620 eccprcr::Eccprcr,
621 Eccprcr_SPEC,
622 crate::common::RW,
623 > {
624 crate::common::RegisterField::<
625 0,
626 0x1,
627 1,
628 0,
629 eccprcr::Eccprcr,
630 eccprcr::Eccprcr,
631 Eccprcr_SPEC,
632 crate::common::RW,
633 >::from_register(self, 0)
634 }
635}
636impl ::core::default::Default for Eccprcr {
637 #[inline(always)]
638 fn default() -> Eccprcr {
639 <crate::RegValueT<Eccprcr_SPEC> as RegisterValue<_>>::new(0)
640 }
641}
642pub mod eccprcr {
643
644 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
645 pub struct Kw_SPEC;
646 pub type Kw = crate::EnumBitfieldStruct<u8, Kw_SPEC>;
647 impl Kw {
648 #[doc = "Writing to the ECCPRCR bit is valid, when the KW bits are written 1111000b."]
649 pub const _1111000: Self = Self::new(120);
650 }
651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
652 pub struct Eccprcr_SPEC;
653 pub type Eccprcr = crate::EnumBitfieldStruct<u8, Eccprcr_SPEC>;
654 impl Eccprcr {
655 #[doc = "Writing to the protect register is disabled."]
656 pub const _0: Self = Self::new(0);
657
658 #[doc = "Writing to the protect register is enabled."]
659 pub const _1: Self = Self::new(1);
660 }
661}
662#[doc(hidden)]
663#[derive(Copy, Clone, Eq, PartialEq)]
664pub struct Eccprcr2_SPEC;
665impl crate::sealed::RegSpec for Eccprcr2_SPEC {
666 type DataType = u8;
667}
668
669#[doc = "ECC Protection Register 2"]
670pub type Eccprcr2 = crate::RegValueT<Eccprcr2_SPEC>;
671
672impl Eccprcr2 {
673 #[doc = "Write Key Code"]
674 #[inline(always)]
675 pub fn kw(
676 self,
677 ) -> crate::common::RegisterField<
678 1,
679 0x7f,
680 1,
681 0,
682 eccprcr2::Kw,
683 eccprcr2::Kw,
684 Eccprcr2_SPEC,
685 crate::common::W,
686 > {
687 crate::common::RegisterField::<
688 1,
689 0x7f,
690 1,
691 0,
692 eccprcr2::Kw,
693 eccprcr2::Kw,
694 Eccprcr2_SPEC,
695 crate::common::W,
696 >::from_register(self, 0)
697 }
698
699 #[doc = "Register Write Control"]
700 #[inline(always)]
701 pub fn eccprcr2(
702 self,
703 ) -> crate::common::RegisterField<
704 0,
705 0x1,
706 1,
707 0,
708 eccprcr2::Eccprcr2,
709 eccprcr2::Eccprcr2,
710 Eccprcr2_SPEC,
711 crate::common::RW,
712 > {
713 crate::common::RegisterField::<
714 0,
715 0x1,
716 1,
717 0,
718 eccprcr2::Eccprcr2,
719 eccprcr2::Eccprcr2,
720 Eccprcr2_SPEC,
721 crate::common::RW,
722 >::from_register(self, 0)
723 }
724}
725impl ::core::default::Default for Eccprcr2 {
726 #[inline(always)]
727 fn default() -> Eccprcr2 {
728 <crate::RegValueT<Eccprcr2_SPEC> as RegisterValue<_>>::new(0)
729 }
730}
731pub mod eccprcr2 {
732
733 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
734 pub struct Kw_SPEC;
735 pub type Kw = crate::EnumBitfieldStruct<u8, Kw_SPEC>;
736 impl Kw {
737 #[doc = "Writing to the ECCPRCR2 bit is valid, when the KEY bits are written 1111000b."]
738 pub const _1111000: Self = Self::new(120);
739 }
740 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
741 pub struct Eccprcr2_SPEC;
742 pub type Eccprcr2 = crate::EnumBitfieldStruct<u8, Eccprcr2_SPEC>;
743 impl Eccprcr2 {
744 #[doc = "Writing to the protect register is disabled."]
745 pub const _0: Self = Self::new(0);
746
747 #[doc = "Writing to the protect register is enabled."]
748 pub const _1: Self = Self::new(1);
749 }
750}
751#[doc(hidden)]
752#[derive(Copy, Clone, Eq, PartialEq)]
753pub struct Eccetst_SPEC;
754impl crate::sealed::RegSpec for Eccetst_SPEC {
755 type DataType = u8;
756}
757
758#[doc = "ECC Test Control Register"]
759pub type Eccetst = crate::RegValueT<Eccetst_SPEC>;
760
761impl Eccetst {
762 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
763 #[inline(always)]
764 pub fn reserved(
765 self,
766 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Eccetst_SPEC, crate::common::RW> {
767 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Eccetst_SPEC,crate::common::RW>::from_register(self,0)
768 }
769
770 #[doc = "ECC Bypass Select"]
771 #[inline(always)]
772 pub fn tstbyp(
773 self,
774 ) -> crate::common::RegisterField<
775 0,
776 0x1,
777 1,
778 0,
779 eccetst::Tstbyp,
780 eccetst::Tstbyp,
781 Eccetst_SPEC,
782 crate::common::RW,
783 > {
784 crate::common::RegisterField::<
785 0,
786 0x1,
787 1,
788 0,
789 eccetst::Tstbyp,
790 eccetst::Tstbyp,
791 Eccetst_SPEC,
792 crate::common::RW,
793 >::from_register(self, 0)
794 }
795}
796impl ::core::default::Default for Eccetst {
797 #[inline(always)]
798 fn default() -> Eccetst {
799 <crate::RegValueT<Eccetst_SPEC> as RegisterValue<_>>::new(0)
800 }
801}
802pub mod eccetst {
803
804 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
805 pub struct Tstbyp_SPEC;
806 pub type Tstbyp = crate::EnumBitfieldStruct<u8, Tstbyp_SPEC>;
807 impl Tstbyp {
808 #[doc = "ECC bypass is disabled."]
809 pub const _0: Self = Self::new(0);
810
811 #[doc = "ECC bypass is enabled."]
812 pub const _1: Self = Self::new(1);
813 }
814}
815#[doc(hidden)]
816#[derive(Copy, Clone, Eq, PartialEq)]
817pub struct Eccoad_SPEC;
818impl crate::sealed::RegSpec for Eccoad_SPEC {
819 type DataType = u8;
820}
821
822#[doc = "SRAM ECC Error Operation After Detection Register"]
823pub type Eccoad = crate::RegValueT<Eccoad_SPEC>;
824
825impl Eccoad {
826 #[doc = "These bits are read as 0000000. The write value should be 0000000."]
827 #[inline(always)]
828 pub fn reserved(
829 self,
830 ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Eccoad_SPEC, crate::common::RW> {
831 crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Eccoad_SPEC,crate::common::RW>::from_register(self,0)
832 }
833
834 #[doc = "Operation after Detection"]
835 #[inline(always)]
836 pub fn oad(
837 self,
838 ) -> crate::common::RegisterField<
839 0,
840 0x1,
841 1,
842 0,
843 eccoad::Oad,
844 eccoad::Oad,
845 Eccoad_SPEC,
846 crate::common::RW,
847 > {
848 crate::common::RegisterField::<
849 0,
850 0x1,
851 1,
852 0,
853 eccoad::Oad,
854 eccoad::Oad,
855 Eccoad_SPEC,
856 crate::common::RW,
857 >::from_register(self, 0)
858 }
859}
860impl ::core::default::Default for Eccoad {
861 #[inline(always)]
862 fn default() -> Eccoad {
863 <crate::RegValueT<Eccoad_SPEC> as RegisterValue<_>>::new(0)
864 }
865}
866pub mod eccoad {
867
868 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
869 pub struct Oad_SPEC;
870 pub type Oad = crate::EnumBitfieldStruct<u8, Oad_SPEC>;
871 impl Oad {
872 #[doc = "Non maskable interrupt."]
873 pub const _0: Self = Self::new(0);
874
875 #[doc = "Internal reset."]
876 pub const _1: Self = Self::new(1);
877 }
878}