ra2a1_pac/
sdadc24.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"24-Bit Sigma-Delta A/D Converter"]
28unsafe impl ::core::marker::Send for super::Sdadc24 {}
29unsafe impl ::core::marker::Sync for super::Sdadc24 {}
30impl super::Sdadc24 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Startup Control Register 1"]
38    #[inline(always)]
39    pub const fn stc1(&self) -> &'static crate::common::Reg<self::Stc1_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Stc1_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Startup Control Register 2"]
48    #[inline(always)]
49    pub const fn stc2(&self) -> &'static crate::common::Reg<self::Stc2_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Stc2_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(4usize),
53            )
54        }
55    }
56
57    #[doc = "Input Multiplexer %s Setting Register"]
58    #[inline(always)]
59    pub const fn pgac(
60        &self,
61    ) -> &'static crate::common::ClusterRegisterArray<
62        crate::common::Reg<self::Pgac_SPEC, crate::common::RW>,
63        5,
64        0x4,
65    > {
66        unsafe {
67            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x8usize))
68        }
69    }
70    #[inline(always)]
71    pub const fn pgac0(&self) -> &'static crate::common::Reg<self::Pgac_SPEC, crate::common::RW> {
72        unsafe {
73            crate::common::Reg::<self::Pgac_SPEC, crate::common::RW>::from_ptr(
74                self._svd2pac_as_ptr().add(0x8usize),
75            )
76        }
77    }
78    #[inline(always)]
79    pub const fn pgac1(&self) -> &'static crate::common::Reg<self::Pgac_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Pgac_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(0xcusize),
83            )
84        }
85    }
86    #[inline(always)]
87    pub const fn pgac2(&self) -> &'static crate::common::Reg<self::Pgac_SPEC, crate::common::RW> {
88        unsafe {
89            crate::common::Reg::<self::Pgac_SPEC, crate::common::RW>::from_ptr(
90                self._svd2pac_as_ptr().add(0x10usize),
91            )
92        }
93    }
94    #[inline(always)]
95    pub const fn pgac3(&self) -> &'static crate::common::Reg<self::Pgac_SPEC, crate::common::RW> {
96        unsafe {
97            crate::common::Reg::<self::Pgac_SPEC, crate::common::RW>::from_ptr(
98                self._svd2pac_as_ptr().add(0x14usize),
99            )
100        }
101    }
102    #[inline(always)]
103    pub const fn pgac4(&self) -> &'static crate::common::Reg<self::Pgac_SPEC, crate::common::RW> {
104        unsafe {
105            crate::common::Reg::<self::Pgac_SPEC, crate::common::RW>::from_ptr(
106                self._svd2pac_as_ptr().add(0x18usize),
107            )
108        }
109    }
110
111    #[doc = "Sigma-delta A/D Converter Control Register 1"]
112    #[inline(always)]
113    pub const fn adc1(&self) -> &'static crate::common::Reg<self::Adc1_SPEC, crate::common::RW> {
114        unsafe {
115            crate::common::Reg::<self::Adc1_SPEC, crate::common::RW>::from_ptr(
116                self._svd2pac_as_ptr().add(28usize),
117            )
118        }
119    }
120
121    #[doc = "Sigma-delta A/D Converter Control Register 2"]
122    #[inline(always)]
123    pub const fn adc2(&self) -> &'static crate::common::Reg<self::Adc2_SPEC, crate::common::RW> {
124        unsafe {
125            crate::common::Reg::<self::Adc2_SPEC, crate::common::RW>::from_ptr(
126                self._svd2pac_as_ptr().add(32usize),
127            )
128        }
129    }
130
131    #[doc = "Sigma-delta A/D Converter Conversion Result Register"]
132    #[inline(always)]
133    pub const fn adcr(&self) -> &'static crate::common::Reg<self::Adcr_SPEC, crate::common::RW> {
134        unsafe {
135            crate::common::Reg::<self::Adcr_SPEC, crate::common::RW>::from_ptr(
136                self._svd2pac_as_ptr().add(36usize),
137            )
138        }
139    }
140
141    #[doc = "Sigma-delta A/D Converter Average Value Register"]
142    #[inline(always)]
143    pub const fn adar(&self) -> &'static crate::common::Reg<self::Adar_SPEC, crate::common::R> {
144        unsafe {
145            crate::common::Reg::<self::Adar_SPEC, crate::common::R>::from_ptr(
146                self._svd2pac_as_ptr().add(40usize),
147            )
148        }
149    }
150
151    #[doc = "Calibration Control Register"]
152    #[inline(always)]
153    pub const fn clbc(&self) -> &'static crate::common::Reg<self::Clbc_SPEC, crate::common::RW> {
154        unsafe {
155            crate::common::Reg::<self::Clbc_SPEC, crate::common::RW>::from_ptr(
156                self._svd2pac_as_ptr().add(48usize),
157            )
158        }
159    }
160
161    #[doc = "Calibration Start Control Register"]
162    #[inline(always)]
163    pub const fn clbstr(
164        &self,
165    ) -> &'static crate::common::Reg<self::Clbstr_SPEC, crate::common::RW> {
166        unsafe {
167            crate::common::Reg::<self::Clbstr_SPEC, crate::common::RW>::from_ptr(
168                self._svd2pac_as_ptr().add(52usize),
169            )
170        }
171    }
172
173    #[doc = "Calibration Status Register"]
174    #[inline(always)]
175    pub const fn clbssr(&self) -> &'static crate::common::Reg<self::Clbssr_SPEC, crate::common::R> {
176        unsafe {
177            crate::common::Reg::<self::Clbssr_SPEC, crate::common::R>::from_ptr(
178                self._svd2pac_as_ptr().add(60usize),
179            )
180        }
181    }
182}
183#[doc(hidden)]
184#[derive(Copy, Clone, Eq, PartialEq)]
185pub struct Stc1_SPEC;
186impl crate::sealed::RegSpec for Stc1_SPEC {
187    type DataType = u16;
188}
189
190#[doc = "Startup Control Register 1"]
191pub type Stc1 = crate::RegValueT<Stc1_SPEC>;
192
193impl Stc1 {
194    #[doc = "VREF mode select"]
195    #[inline(always)]
196    pub fn vrefsel(
197        self,
198    ) -> crate::common::RegisterField<
199        15,
200        0x1,
201        1,
202        0,
203        stc1::Vrefsel,
204        stc1::Vrefsel,
205        Stc1_SPEC,
206        crate::common::RW,
207    > {
208        crate::common::RegisterField::<
209            15,
210            0x1,
211            1,
212            0,
213            stc1::Vrefsel,
214            stc1::Vrefsel,
215            Stc1_SPEC,
216            crate::common::RW,
217        >::from_register(self, 0)
218    }
219
220    #[doc = "Reference voltage select"]
221    #[inline(always)]
222    pub fn vsbias(
223        self,
224    ) -> crate::common::RegisterField<
225        8,
226        0xf,
227        1,
228        0,
229        stc1::Vsbias,
230        stc1::Vsbias,
231        Stc1_SPEC,
232        crate::common::RW,
233    > {
234        crate::common::RegisterField::<
235            8,
236            0xf,
237            1,
238            0,
239            stc1::Vsbias,
240            stc1::Vsbias,
241            Stc1_SPEC,
242            crate::common::RW,
243        >::from_register(self, 0)
244    }
245
246    #[doc = "A/D conversion operation mode select"]
247    #[inline(always)]
248    pub fn sdadlpm(
249        self,
250    ) -> crate::common::RegisterField<
251        7,
252        0x1,
253        1,
254        0,
255        stc1::Sdadlpm,
256        stc1::Sdadlpm,
257        Stc1_SPEC,
258        crate::common::RW,
259    > {
260        crate::common::RegisterField::<
261            7,
262            0x1,
263            1,
264            0,
265            stc1::Sdadlpm,
266            stc1::Sdadlpm,
267            Stc1_SPEC,
268            crate::common::RW,
269        >::from_register(self, 0)
270    }
271
272    #[doc = "These bits are read as 000. The write value should be 000."]
273    #[inline(always)]
274    pub fn reserved(
275        self,
276    ) -> crate::common::RegisterField<4, 0x7, 1, 0, u8, u8, Stc1_SPEC, crate::common::RW> {
277        crate::common::RegisterField::<4,0x7,1,0,u8,u8,Stc1_SPEC,crate::common::RW>::from_register(self,0)
278    }
279
280    #[doc = "SDADC24 reference clock division select"]
281    #[inline(always)]
282    pub fn clkdiv(
283        self,
284    ) -> crate::common::RegisterField<
285        0,
286        0xf,
287        1,
288        0,
289        stc1::Clkdiv,
290        stc1::Clkdiv,
291        Stc1_SPEC,
292        crate::common::RW,
293    > {
294        crate::common::RegisterField::<
295            0,
296            0xf,
297            1,
298            0,
299            stc1::Clkdiv,
300            stc1::Clkdiv,
301            Stc1_SPEC,
302            crate::common::RW,
303        >::from_register(self, 0)
304    }
305}
306impl ::core::default::Default for Stc1 {
307    #[inline(always)]
308    fn default() -> Stc1 {
309        <crate::RegValueT<Stc1_SPEC> as RegisterValue<_>>::new(32776)
310    }
311}
312pub mod stc1 {
313
314    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
315    pub struct Vrefsel_SPEC;
316    pub type Vrefsel = crate::EnumBitfieldStruct<u8, Vrefsel_SPEC>;
317    impl Vrefsel {
318        #[doc = "Internal VREF mode"]
319        pub const _0: Self = Self::new(0);
320
321        #[doc = "External VREF mode"]
322        pub const _1: Self = Self::new(1);
323    }
324    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
325    pub struct Vsbias_SPEC;
326    pub type Vsbias = crate::EnumBitfieldStruct<u8, Vsbias_SPEC>;
327    impl Vsbias {
328        #[doc = "0.8 V"]
329        pub const _0000: Self = Self::new(0);
330
331        #[doc = "1.0 V"]
332        pub const _0001: Self = Self::new(1);
333
334        #[doc = "1.2 V"]
335        pub const _0010: Self = Self::new(2);
336
337        #[doc = "1.4 V"]
338        pub const _0011: Self = Self::new(3);
339
340        #[doc = "1.6 V"]
341        pub const _0100: Self = Self::new(4);
342
343        #[doc = "1.8 V"]
344        pub const _0101: Self = Self::new(5);
345
346        #[doc = "2.0 V"]
347        pub const _0110: Self = Self::new(6);
348
349        #[doc = "2.2 V"]
350        pub const _0111: Self = Self::new(7);
351
352        #[doc = "2.4 V (This voltage can be set only if VREFSEL = 1.  When VREFSEL = 0, 2.2 V is set (rather than 2.4 V))"]
353        pub const _1111: Self = Self::new(15);
354    }
355    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
356    pub struct Sdadlpm_SPEC;
357    pub type Sdadlpm = crate::EnumBitfieldStruct<u8, Sdadlpm_SPEC>;
358    impl Sdadlpm {
359        #[doc = "Normal A/D conversion mode: SDADC24 reference clock:4 MHz, Oversampling clock:1 MHz"]
360        pub const _0: Self = Self::new(0);
361
362        #[doc = "Low-power A/D conversion mode(1/8 of the clock in normal A/D conversion mode): SDADC24 reference clock:500 kHz,Oversampling clock: 125 kHz"]
363        pub const _1: Self = Self::new(1);
364    }
365    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
366    pub struct Clkdiv_SPEC;
367    pub type Clkdiv = crate::EnumBitfieldStruct<u8, Clkdiv_SPEC>;
368    impl Clkdiv {
369        #[doc = "SDADCCLK (no division)"]
370        pub const _0000: Self = Self::new(0);
371
372        #[doc = "SDADCCLK/2 (1/2)"]
373        pub const _0001: Self = Self::new(1);
374
375        #[doc = "SDADCCLK/3 (1/3)"]
376        pub const _0010: Self = Self::new(2);
377
378        #[doc = "SDADCCLK/4 (1/4)"]
379        pub const _0011: Self = Self::new(3);
380
381        #[doc = "SDADCCLK/5 (1/5)"]
382        pub const _0100: Self = Self::new(4);
383
384        #[doc = "SDADCCLK/6 (1/6)"]
385        pub const _0101: Self = Self::new(5);
386
387        #[doc = "SDADCCLK/8 (1/8)"]
388        pub const _0110: Self = Self::new(6);
389
390        #[doc = "SDADCCLK/12 (1/12)"]
391        pub const _0111: Self = Self::new(7);
392
393        #[doc = "SDADCCLK/16 (1/16)."]
394        pub const _1000: Self = Self::new(8);
395    }
396}
397#[doc(hidden)]
398#[derive(Copy, Clone, Eq, PartialEq)]
399pub struct Stc2_SPEC;
400impl crate::sealed::RegSpec for Stc2_SPEC {
401    type DataType = u8;
402}
403
404#[doc = "Startup Control Register 2"]
405pub type Stc2 = crate::RegValueT<Stc2_SPEC>;
406
407impl Stc2 {
408    #[doc = "These bits are read as 00000. The write value should be 00000."]
409    #[inline(always)]
410    pub fn reserved(
411        self,
412    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Stc2_SPEC, crate::common::RW> {
413        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Stc2_SPEC,crate::common::RW>::from_register(self,0)
414    }
415
416    #[doc = "ADREG forced power-down mode"]
417    #[inline(always)]
418    pub fn adfpwds(
419        self,
420    ) -> crate::common::RegisterField<
421        2,
422        0x1,
423        1,
424        0,
425        stc2::Adfpwds,
426        stc2::Adfpwds,
427        Stc2_SPEC,
428        crate::common::RW,
429    > {
430        crate::common::RegisterField::<
431            2,
432            0x1,
433            1,
434            0,
435            stc2::Adfpwds,
436            stc2::Adfpwds,
437            Stc2_SPEC,
438            crate::common::RW,
439        >::from_register(self, 0)
440    }
441
442    #[doc = "ADC reference supply part power control"]
443    #[inline(always)]
444    pub fn adcpon(
445        self,
446    ) -> crate::common::RegisterField<
447        1,
448        0x1,
449        1,
450        0,
451        stc2::Adcpon,
452        stc2::Adcpon,
453        Stc2_SPEC,
454        crate::common::RW,
455    > {
456        crate::common::RegisterField::<
457            1,
458            0x1,
459            1,
460            0,
461            stc2::Adcpon,
462            stc2::Adcpon,
463            Stc2_SPEC,
464            crate::common::RW,
465        >::from_register(self, 0)
466    }
467
468    #[doc = "BGR part power control"]
469    #[inline(always)]
470    pub fn bgrpon(
471        self,
472    ) -> crate::common::RegisterField<
473        0,
474        0x1,
475        1,
476        0,
477        stc2::Bgrpon,
478        stc2::Bgrpon,
479        Stc2_SPEC,
480        crate::common::RW,
481    > {
482        crate::common::RegisterField::<
483            0,
484            0x1,
485            1,
486            0,
487            stc2::Bgrpon,
488            stc2::Bgrpon,
489            Stc2_SPEC,
490            crate::common::RW,
491        >::from_register(self, 0)
492    }
493}
494impl ::core::default::Default for Stc2 {
495    #[inline(always)]
496    fn default() -> Stc2 {
497        <crate::RegValueT<Stc2_SPEC> as RegisterValue<_>>::new(0)
498    }
499}
500pub mod stc2 {
501
502    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
503    pub struct Adfpwds_SPEC;
504    pub type Adfpwds = crate::EnumBitfieldStruct<u8, Adfpwds_SPEC>;
505    impl Adfpwds {
506        #[doc = "Power of ADREG is controlled by the BGRPON setting"]
507        pub const _0: Self = Self::new(0);
508
509        #[doc = "Power of only ADREG is turned off regardless of the BGRPON setting"]
510        pub const _1: Self = Self::new(1);
511    }
512    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
513    pub struct Adcpon_SPEC;
514    pub type Adcpon = crate::EnumBitfieldStruct<u8, Adcpon_SPEC>;
515    impl Adcpon {
516        #[doc = "Turn off the power of VBIAS, PGA and sigma-delta A/D converter"]
517        pub const _0: Self = Self::new(0);
518
519        #[doc = "Turn on the power of VBIAS, PGA and sigma-delta A/D converter"]
520        pub const _1: Self = Self::new(1);
521    }
522    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
523    pub struct Bgrpon_SPEC;
524    pub type Bgrpon = crate::EnumBitfieldStruct<u8, Bgrpon_SPEC>;
525    impl Bgrpon {
526        #[doc = "Turn off the power of ADBGR, SBIAS/VREFI, and ADREG"]
527        pub const _0: Self = Self::new(0);
528
529        #[doc = "Turn on the power of ADBGR, SBIAS/VREFI, and ADREG"]
530        pub const _1: Self = Self::new(1);
531    }
532}
533#[doc(hidden)]
534#[derive(Copy, Clone, Eq, PartialEq)]
535pub struct Pgac_SPEC;
536impl crate::sealed::RegSpec for Pgac_SPEC {
537    type DataType = u32;
538}
539
540#[doc = "Input Multiplexer %s Setting Register"]
541pub type Pgac = crate::RegValueT<Pgac_SPEC>;
542
543impl Pgac {
544    #[doc = "Selection of the mode for specifying the number of A/D conversions in ADSCAN"]
545    #[inline(always)]
546    pub fn pgaasn(
547        self,
548    ) -> crate::common::RegisterField<
549        31,
550        0x1,
551        1,
552        0,
553        pgac::Pgaasn,
554        pgac::Pgaasn,
555        Pgac_SPEC,
556        crate::common::RW,
557    > {
558        crate::common::RegisterField::<
559            31,
560            0x1,
561            1,
562            0,
563            pgac::Pgaasn,
564            pgac::Pgaasn,
565            Pgac_SPEC,
566            crate::common::RW,
567        >::from_register(self, 0)
568    }
569
570    #[doc = "Calibration enable"]
571    #[inline(always)]
572    pub fn pgacve(
573        self,
574    ) -> crate::common::RegisterField<
575        30,
576        0x1,
577        1,
578        0,
579        pgac::Pgacve,
580        pgac::Pgacve,
581        Pgac_SPEC,
582        crate::common::RW,
583    > {
584        crate::common::RegisterField::<
585            30,
586            0x1,
587            1,
588            0,
589            pgac::Pgacve,
590            pgac::Pgacve,
591            Pgac_SPEC,
592            crate::common::RW,
593        >::from_register(self, 0)
594    }
595
596    #[doc = "Single-End Input A/D Converted Data Inversion Select"]
597    #[inline(always)]
598    pub fn pgarev(
599        self,
600    ) -> crate::common::RegisterField<
601        28,
602        0x1,
603        1,
604        0,
605        pgac::Pgarev,
606        pgac::Pgarev,
607        Pgac_SPEC,
608        crate::common::RW,
609    > {
610        crate::common::RegisterField::<
611            28,
612            0x1,
613            1,
614            0,
615            pgac::Pgarev,
616            pgac::Pgarev,
617            Pgac_SPEC,
618            crate::common::RW,
619        >::from_register(self, 0)
620    }
621
622    #[doc = "Selection of averaging processing"]
623    #[inline(always)]
624    pub fn pgaave(
625        self,
626    ) -> crate::common::RegisterField<
627        26,
628        0x3,
629        1,
630        0,
631        pgac::Pgaave,
632        pgac::Pgaave,
633        Pgac_SPEC,
634        crate::common::RW,
635    > {
636        crate::common::RegisterField::<
637            26,
638            0x3,
639            1,
640            0,
641            pgac::Pgaave,
642            pgac::Pgaave,
643            Pgac_SPEC,
644            crate::common::RW,
645        >::from_register(self, 0)
646    }
647
648    #[doc = "Selection of the number of data to be averaged"]
649    #[inline(always)]
650    pub fn pgaavn(
651        self,
652    ) -> crate::common::RegisterField<
653        24,
654        0x3,
655        1,
656        0,
657        pgac::Pgaavn,
658        pgac::Pgaavn,
659        Pgac_SPEC,
660        crate::common::RW,
661    > {
662        crate::common::RegisterField::<
663            24,
664            0x3,
665            1,
666            0,
667            pgac::Pgaavn,
668            pgac::Pgaavn,
669            Pgac_SPEC,
670            crate::common::RW,
671        >::from_register(self, 0)
672    }
673
674    #[doc = "Coefficient (n) selection of the A/D conversion count (N) in AUTOSCAN"]
675    #[inline(always)]
676    pub fn pgactn(
677        self,
678    ) -> crate::common::RegisterField<
679        21,
680        0x7,
681        1,
682        0,
683        pgac::Pgactn,
684        pgac::Pgactn,
685        Pgac_SPEC,
686        crate::common::RW,
687    > {
688        crate::common::RegisterField::<
689            21,
690            0x7,
691            1,
692            0,
693            pgac::Pgactn,
694            pgac::Pgactn,
695            Pgac_SPEC,
696            crate::common::RW,
697        >::from_register(self, 0)
698    }
699
700    #[doc = "Coefficient (m) selection of the A/D conversion count (N) in AUTOSCAN"]
701    #[inline(always)]
702    pub fn pgactm(
703        self,
704    ) -> crate::common::RegisterField<16, 0x1f, 1, 0, u8, u8, Pgac_SPEC, crate::common::RW> {
705        crate::common::RegisterField::<16,0x1f,1,0,u8,u8,Pgac_SPEC,crate::common::RW>::from_register(self,0)
706    }
707
708    #[doc = "Analog Channel Input Mode Select"]
709    #[inline(always)]
710    pub fn pgasel(
711        self,
712    ) -> crate::common::RegisterField<
713        15,
714        0x1,
715        1,
716        0,
717        pgac::Pgasel,
718        pgac::Pgasel,
719        Pgac_SPEC,
720        crate::common::RW,
721    > {
722        crate::common::RegisterField::<
723            15,
724            0x1,
725            1,
726            0,
727            pgac::Pgasel,
728            pgac::Pgasel,
729            Pgac_SPEC,
730            crate::common::RW,
731        >::from_register(self, 0)
732    }
733
734    #[doc = "Polarity select"]
735    #[inline(always)]
736    pub fn pgapol(
737        self,
738    ) -> crate::common::RegisterField<
739        14,
740        0x1,
741        1,
742        0,
743        pgac::Pgapol,
744        pgac::Pgapol,
745        Pgac_SPEC,
746        crate::common::RW,
747    > {
748        crate::common::RegisterField::<
749            14,
750            0x1,
751            1,
752            0,
753            pgac::Pgapol,
754            pgac::Pgapol,
755            Pgac_SPEC,
756            crate::common::RW,
757        >::from_register(self, 0)
758    }
759
760    #[doc = "This bit is read as 0. The write value should be 0."]
761    #[inline(always)]
762    pub fn reserved(
763        self,
764    ) -> crate::common::RegisterFieldBool<13, 1, 0, Pgac_SPEC, crate::common::RW> {
765        crate::common::RegisterFieldBool::<13, 1, 0, Pgac_SPEC, crate::common::RW>::from_register(
766            self, 0,
767        )
768    }
769
770    #[doc = "Offset voltage select"]
771    #[inline(always)]
772    pub fn pgaofs(
773        self,
774    ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, Pgac_SPEC, crate::common::RW> {
775        crate::common::RegisterField::<8,0x1f,1,0,u8,u8,Pgac_SPEC,crate::common::RW>::from_register(self,0)
776    }
777
778    #[doc = "Oversampling ratio select"]
779    #[inline(always)]
780    pub fn pgaosr(
781        self,
782    ) -> crate::common::RegisterField<
783        5,
784        0x7,
785        1,
786        0,
787        pgac::Pgaosr,
788        pgac::Pgaosr,
789        Pgac_SPEC,
790        crate::common::RW,
791    > {
792        crate::common::RegisterField::<
793            5,
794            0x7,
795            1,
796            0,
797            pgac::Pgaosr,
798            pgac::Pgaosr,
799            Pgac_SPEC,
800            crate::common::RW,
801        >::from_register(self, 0)
802    }
803
804    #[doc = "Gain selection of a programmable gain instrumentation amplifier ( Gset1, Gset2, Gtotal )"]
805    #[inline(always)]
806    pub fn pgagc(
807        self,
808    ) -> crate::common::RegisterField<
809        0,
810        0x1f,
811        1,
812        0,
813        pgac::Pgagc,
814        pgac::Pgagc,
815        Pgac_SPEC,
816        crate::common::RW,
817    > {
818        crate::common::RegisterField::<
819            0,
820            0x1f,
821            1,
822            0,
823            pgac::Pgagc,
824            pgac::Pgagc,
825            Pgac_SPEC,
826            crate::common::RW,
827        >::from_register(self, 0)
828    }
829}
830impl ::core::default::Default for Pgac {
831    #[inline(always)]
832    fn default() -> Pgac {
833        <crate::RegValueT<Pgac_SPEC> as RegisterValue<_>>::new(65600)
834    }
835}
836pub mod pgac {
837
838    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
839    pub struct Pgaasn_SPEC;
840    pub type Pgaasn = crate::EnumBitfieldStruct<u8, Pgaasn_SPEC>;
841    impl Pgaasn {
842        #[doc = "Specify 1 to 8,032 times by using the value set in the PGACTN\\[2:0\\] and PGACTM\\[4:0\\] bits"]
843        pub const _0: Self = Self::new(0);
844
845        #[doc = "Specify 1 to 255 times linearly by using the value set in the PGACTN\\[2:0\\] and PGACTM\\[4:0\\] bits"]
846        pub const _1: Self = Self::new(1);
847    }
848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
849    pub struct Pgacve_SPEC;
850    pub type Pgacve = crate::EnumBitfieldStruct<u8, Pgacve_SPEC>;
851    impl Pgacve {
852        #[doc = "Do not calculate the calibration correction factor"]
853        pub const _0: Self = Self::new(0);
854
855        #[doc = "Calculate the calibration correction factor"]
856        pub const _1: Self = Self::new(1);
857    }
858    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
859    pub struct Pgarev_SPEC;
860    pub type Pgarev = crate::EnumBitfieldStruct<u8, Pgarev_SPEC>;
861    impl Pgarev {
862        #[doc = "Do not invert the conversion result data"]
863        pub const _0: Self = Self::new(0);
864
865        #[doc = "Invert the conversion result data"]
866        pub const _1: Self = Self::new(1);
867    }
868    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
869    pub struct Pgaave_SPEC;
870    pub type Pgaave = crate::EnumBitfieldStruct<u8, Pgaave_SPEC>;
871    impl Pgaave {
872        #[doc = "Do not average the A/D conversion results"]
873        pub const _00: Self = Self::new(0);
874
875        #[doc = "Do not average the A/D conversion results"]
876        pub const _01: Self = Self::new(1);
877
878        #[doc = "Average the A/D conversion results and generates SDADC_ADI each time an A/D conversion occurs"]
879        pub const _10: Self = Self::new(2);
880
881        #[doc = "Perform averaging, and generate SDADC_ADI at each time of average value output (A/D conversion is performed N times)."]
882        pub const _11: Self = Self::new(3);
883    }
884    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
885    pub struct Pgaavn_SPEC;
886    pub type Pgaavn = crate::EnumBitfieldStruct<u8, Pgaavn_SPEC>;
887    impl Pgaavn {
888        #[doc = "8"]
889        pub const _00: Self = Self::new(0);
890
891        #[doc = "16"]
892        pub const _01: Self = Self::new(1);
893
894        #[doc = "32"]
895        pub const _10: Self = Self::new(2);
896
897        #[doc = "64"]
898        pub const _11: Self = Self::new(3);
899    }
900    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
901    pub struct Pgactn_SPEC;
902    pub type Pgactn = crate::EnumBitfieldStruct<u8, Pgactn_SPEC>;
903    impl Pgactn {
904        #[doc = "0"]
905        pub const _000: Self = Self::new(0);
906
907        #[doc = "1"]
908        pub const _001: Self = Self::new(1);
909
910        #[doc = "2"]
911        pub const _010: Self = Self::new(2);
912
913        #[doc = "3"]
914        pub const _011: Self = Self::new(3);
915
916        #[doc = "4"]
917        pub const _100: Self = Self::new(4);
918
919        #[doc = "5"]
920        pub const _101: Self = Self::new(5);
921
922        #[doc = "6"]
923        pub const _110: Self = Self::new(6);
924
925        #[doc = "7"]
926        pub const _111: Self = Self::new(7);
927    }
928    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
929    pub struct Pgasel_SPEC;
930    pub type Pgasel = crate::EnumBitfieldStruct<u8, Pgasel_SPEC>;
931    impl Pgasel {
932        #[doc = "Differential input mode"]
933        pub const _0: Self = Self::new(0);
934
935        #[doc = "Single-end input mode"]
936        pub const _1: Self = Self::new(1);
937    }
938    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
939    pub struct Pgapol_SPEC;
940    pub type Pgapol = crate::EnumBitfieldStruct<u8, Pgapol_SPEC>;
941    impl Pgapol {
942        #[doc = "Positive-side single-end input"]
943        pub const _0: Self = Self::new(0);
944
945        #[doc = "Negative-side single-end input"]
946        pub const _1: Self = Self::new(1);
947    }
948    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
949    pub struct Pgaosr_SPEC;
950    pub type Pgaosr = crate::EnumBitfieldStruct<u8, Pgaosr_SPEC>;
951    impl Pgaosr {
952        #[doc = "64"]
953        pub const _000: Self = Self::new(0);
954
955        #[doc = "128"]
956        pub const _001: Self = Self::new(1);
957
958        #[doc = "256"]
959        pub const _010: Self = Self::new(2);
960
961        #[doc = "512"]
962        pub const _011: Self = Self::new(3);
963
964        #[doc = "1024"]
965        pub const _100: Self = Self::new(4);
966
967        #[doc = "2048"]
968        pub const _101: Self = Self::new(5);
969    }
970    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
971    pub struct Pgagc_SPEC;
972    pub type Pgagc = crate::EnumBitfieldStruct<u8, Pgagc_SPEC>;
973    impl Pgagc {
974        #[doc = "(1, 1, 1)"]
975        pub const _00000: Self = Self::new(0);
976
977        #[doc = "(2, 1, 2)"]
978        pub const _00100: Self = Self::new(4);
979
980        #[doc = "(3, 1, 3)"]
981        pub const _01000: Self = Self::new(8);
982
983        #[doc = "(4, 1, 4)"]
984        pub const _01100: Self = Self::new(12);
985
986        #[doc = "(8, 1, 8)"]
987        pub const _10000: Self = Self::new(16);
988
989        #[doc = "(1, 2, 2)"]
990        pub const _00001: Self = Self::new(1);
991
992        #[doc = "(2, 2, 4)"]
993        pub const _00101: Self = Self::new(5);
994
995        #[doc = "(3, 2, 6)"]
996        pub const _01001: Self = Self::new(9);
997
998        #[doc = "(4, 2, 8)"]
999        pub const _01101: Self = Self::new(13);
1000
1001        #[doc = "(8, 2, 16)"]
1002        pub const _10001: Self = Self::new(17);
1003
1004        #[doc = "(1, 4, 4)"]
1005        pub const _00010: Self = Self::new(2);
1006
1007        #[doc = "(2, 4, 8)"]
1008        pub const _00110: Self = Self::new(6);
1009
1010        #[doc = "(3, 4, 12)"]
1011        pub const _01010: Self = Self::new(10);
1012
1013        #[doc = "(4, 4, 16)"]
1014        pub const _01110: Self = Self::new(14);
1015
1016        #[doc = "(8, 4, 32)"]
1017        pub const _10010: Self = Self::new(18);
1018
1019        #[doc = "(1, 8, 8)"]
1020        pub const _00011: Self = Self::new(3);
1021
1022        #[doc = "(2, 8, 16)"]
1023        pub const _00111: Self = Self::new(7);
1024
1025        #[doc = "(3, 8, 24)"]
1026        pub const _01011: Self = Self::new(11);
1027
1028        #[doc = "(4, 8, 32)."]
1029        pub const _01111: Self = Self::new(15);
1030    }
1031}
1032#[doc(hidden)]
1033#[derive(Copy, Clone, Eq, PartialEq)]
1034pub struct Adc1_SPEC;
1035impl crate::sealed::RegSpec for Adc1_SPEC {
1036    type DataType = u32;
1037}
1038
1039#[doc = "Sigma-delta A/D Converter Control Register 1"]
1040pub type Adc1 = crate::RegValueT<Adc1_SPEC>;
1041
1042impl Adc1 {
1043    #[doc = "PGA offset self-diagnosis enable"]
1044    #[inline(always)]
1045    pub fn pgaslft(
1046        self,
1047    ) -> crate::common::RegisterField<
1048        20,
1049        0x1,
1050        1,
1051        0,
1052        adc1::Pgaslft,
1053        adc1::Pgaslft,
1054        Adc1_SPEC,
1055        crate::common::RW,
1056    > {
1057        crate::common::RegisterField::<
1058            20,
1059            0x1,
1060            1,
1061            0,
1062            adc1::Pgaslft,
1063            adc1::Pgaslft,
1064            Adc1_SPEC,
1065            crate::common::RW,
1066        >::from_register(self, 0)
1067    }
1068
1069    #[doc = "Disconnection Detection Assist Setting"]
1070    #[inline(always)]
1071    pub fn pgadisc(
1072        self,
1073    ) -> crate::common::RegisterField<
1074        17,
1075        0x1,
1076        1,
1077        0,
1078        adc1::Pgadisc,
1079        adc1::Pgadisc,
1080        Adc1_SPEC,
1081        crate::common::RW,
1082    > {
1083        crate::common::RegisterField::<
1084            17,
1085            0x1,
1086            1,
1087            0,
1088            adc1::Pgadisc,
1089            adc1::Pgadisc,
1090            Adc1_SPEC,
1091            crate::common::RW,
1092        >::from_register(self, 0)
1093    }
1094
1095    #[doc = "Control of disconnection detection"]
1096    #[inline(always)]
1097    pub fn pgadisa(
1098        self,
1099    ) -> crate::common::RegisterField<
1100        16,
1101        0x1,
1102        1,
1103        0,
1104        adc1::Pgadisa,
1105        adc1::Pgadisa,
1106        Adc1_SPEC,
1107        crate::common::RW,
1108    > {
1109        crate::common::RegisterField::<
1110            16,
1111            0x1,
1112            1,
1113            0,
1114            adc1::Pgadisa,
1115            adc1::Pgadisa,
1116            Adc1_SPEC,
1117            crate::common::RW,
1118        >::from_register(self, 0)
1119    }
1120
1121    #[doc = "A/D conversion control of the signal from input multiplexer"]
1122    #[inline(always)]
1123    pub fn sdadbmp(
1124        self,
1125    ) -> crate::common::RegisterField<8, 0x1f, 1, 0, u8, u8, Adc1_SPEC, crate::common::RW> {
1126        crate::common::RegisterField::<8,0x1f,1,0,u8,u8,Adc1_SPEC,crate::common::RW>::from_register(self,0)
1127    }
1128
1129    #[doc = "Selection of A/D conversion trigger signal"]
1130    #[inline(always)]
1131    pub fn sdadtmd(
1132        self,
1133    ) -> crate::common::RegisterField<
1134        4,
1135        0x1,
1136        1,
1137        0,
1138        adc1::Sdadtmd,
1139        adc1::Sdadtmd,
1140        Adc1_SPEC,
1141        crate::common::RW,
1142    > {
1143        crate::common::RegisterField::<
1144            4,
1145            0x1,
1146            1,
1147            0,
1148            adc1::Sdadtmd,
1149            adc1::Sdadtmd,
1150            Adc1_SPEC,
1151            crate::common::RW,
1152        >::from_register(self, 0)
1153    }
1154
1155    #[doc = "These bits are read as 000. The write value should be 000."]
1156    #[inline(always)]
1157    pub fn reserved(
1158        self,
1159    ) -> crate::common::RegisterField<1, 0x7, 1, 0, u8, u8, Adc1_SPEC, crate::common::RW> {
1160        crate::common::RegisterField::<1,0x7,1,0,u8,u8,Adc1_SPEC,crate::common::RW>::from_register(self,0)
1161    }
1162
1163    #[doc = "Selection of autoscan mode"]
1164    #[inline(always)]
1165    pub fn sdadscm(
1166        self,
1167    ) -> crate::common::RegisterField<
1168        0,
1169        0x1,
1170        1,
1171        0,
1172        adc1::Sdadscm,
1173        adc1::Sdadscm,
1174        Adc1_SPEC,
1175        crate::common::RW,
1176    > {
1177        crate::common::RegisterField::<
1178            0,
1179            0x1,
1180            1,
1181            0,
1182            adc1::Sdadscm,
1183            adc1::Sdadscm,
1184            Adc1_SPEC,
1185            crate::common::RW,
1186        >::from_register(self, 0)
1187    }
1188}
1189impl ::core::default::Default for Adc1 {
1190    #[inline(always)]
1191    fn default() -> Adc1 {
1192        <crate::RegValueT<Adc1_SPEC> as RegisterValue<_>>::new(0)
1193    }
1194}
1195pub mod adc1 {
1196
1197    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1198    pub struct Pgaslft_SPEC;
1199    pub type Pgaslft = crate::EnumBitfieldStruct<u8, Pgaslft_SPEC>;
1200    impl Pgaslft {
1201        #[doc = "Disable PGA offset self-diagnosis"]
1202        pub const _0: Self = Self::new(0);
1203
1204        #[doc = "Enable PGA offset self-diagnosis"]
1205        pub const _1: Self = Self::new(1);
1206    }
1207    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1208    pub struct Pgadisc_SPEC;
1209    pub type Pgadisc = crate::EnumBitfieldStruct<u8, Pgadisc_SPEC>;
1210    impl Pgadisc {
1211        #[doc = "Discharge"]
1212        pub const _0: Self = Self::new(0);
1213
1214        #[doc = "Pre-charge"]
1215        pub const _1: Self = Self::new(1);
1216    }
1217    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1218    pub struct Pgadisa_SPEC;
1219    pub type Pgadisa = crate::EnumBitfieldStruct<u8, Pgadisa_SPEC>;
1220    impl Pgadisa {
1221        #[doc = "Normal operation"]
1222        pub const _0: Self = Self::new(0);
1223
1224        #[doc = "State of disconnection detection"]
1225        pub const _1: Self = Self::new(1);
1226    }
1227    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1228    pub struct Sdadtmd_SPEC;
1229    pub type Sdadtmd = crate::EnumBitfieldStruct<u8, Sdadtmd_SPEC>;
1230    impl Sdadtmd {
1231        #[doc = "Software trigger (conversion is started by a write to SFR)"]
1232        pub const _0: Self = Self::new(0);
1233
1234        #[doc = "Hardware trigger (conversion is started in synchronization with the event signal selected by ELC_SDADC24)."]
1235        pub const _1: Self = Self::new(1);
1236    }
1237    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1238    pub struct Sdadscm_SPEC;
1239    pub type Sdadscm = crate::EnumBitfieldStruct<u8, Sdadscm_SPEC>;
1240    impl Sdadscm {
1241        #[doc = "Continuous scan mode"]
1242        pub const _0: Self = Self::new(0);
1243
1244        #[doc = "Single scan mode"]
1245        pub const _1: Self = Self::new(1);
1246    }
1247}
1248#[doc(hidden)]
1249#[derive(Copy, Clone, Eq, PartialEq)]
1250pub struct Adc2_SPEC;
1251impl crate::sealed::RegSpec for Adc2_SPEC {
1252    type DataType = u8;
1253}
1254
1255#[doc = "Sigma-delta A/D Converter Control Register 2"]
1256pub type Adc2 = crate::RegValueT<Adc2_SPEC>;
1257
1258impl Adc2 {
1259    #[doc = "These bits are read as 0000000. The write value should be 0000000."]
1260    #[inline(always)]
1261    pub fn reserved(
1262        self,
1263    ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Adc2_SPEC, crate::common::RW> {
1264        crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Adc2_SPEC,crate::common::RW>::from_register(self,0)
1265    }
1266
1267    #[doc = "Control of A/D conversion"]
1268    #[inline(always)]
1269    pub fn sdadst(
1270        self,
1271    ) -> crate::common::RegisterField<
1272        0,
1273        0x1,
1274        1,
1275        0,
1276        adc2::Sdadst,
1277        adc2::Sdadst,
1278        Adc2_SPEC,
1279        crate::common::RW,
1280    > {
1281        crate::common::RegisterField::<
1282            0,
1283            0x1,
1284            1,
1285            0,
1286            adc2::Sdadst,
1287            adc2::Sdadst,
1288            Adc2_SPEC,
1289            crate::common::RW,
1290        >::from_register(self, 0)
1291    }
1292}
1293impl ::core::default::Default for Adc2 {
1294    #[inline(always)]
1295    fn default() -> Adc2 {
1296        <crate::RegValueT<Adc2_SPEC> as RegisterValue<_>>::new(0)
1297    }
1298}
1299pub mod adc2 {
1300
1301    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1302    pub struct Sdadst_SPEC;
1303    pub type Sdadst = crate::EnumBitfieldStruct<u8, Sdadst_SPEC>;
1304    impl Sdadst {
1305        #[doc = "Stop A/D conversion"]
1306        pub const _0: Self = Self::new(0);
1307
1308        #[doc = "Start A/D conversion"]
1309        pub const _1: Self = Self::new(1);
1310    }
1311}
1312#[doc(hidden)]
1313#[derive(Copy, Clone, Eq, PartialEq)]
1314pub struct Adcr_SPEC;
1315impl crate::sealed::RegSpec for Adcr_SPEC {
1316    type DataType = u32;
1317}
1318
1319#[doc = "Sigma-delta A/D Converter Conversion Result Register"]
1320pub type Adcr = crate::RegValueT<Adcr_SPEC>;
1321
1322impl Adcr {
1323    #[doc = "Channel number for an A/D conversion result"]
1324    #[inline(always)]
1325    pub fn sdadcrc(
1326        self,
1327    ) -> crate::common::RegisterField<
1328        25,
1329        0x7,
1330        1,
1331        0,
1332        adcr::Sdadcrc,
1333        adcr::Sdadcrc,
1334        Adcr_SPEC,
1335        crate::common::R,
1336    > {
1337        crate::common::RegisterField::<
1338            25,
1339            0x7,
1340            1,
1341            0,
1342            adcr::Sdadcrc,
1343            adcr::Sdadcrc,
1344            Adcr_SPEC,
1345            crate::common::R,
1346        >::from_register(self, 0)
1347    }
1348
1349    #[doc = "Status of an A/D conversion result"]
1350    #[inline(always)]
1351    pub fn sdadcrs(
1352        self,
1353    ) -> crate::common::RegisterField<
1354        24,
1355        0x1,
1356        1,
1357        0,
1358        adcr::Sdadcrs,
1359        adcr::Sdadcrs,
1360        Adcr_SPEC,
1361        crate::common::R,
1362    > {
1363        crate::common::RegisterField::<
1364            24,
1365            0x1,
1366            1,
1367            0,
1368            adcr::Sdadcrs,
1369            adcr::Sdadcrs,
1370            Adcr_SPEC,
1371            crate::common::R,
1372        >::from_register(self, 0)
1373    }
1374
1375    #[doc = "The 24-bit A/D conversion result"]
1376    #[inline(always)]
1377    pub fn sdadcrd(
1378        self,
1379    ) -> crate::common::RegisterField<0, 0xffffff, 1, 0, u32, u32, Adcr_SPEC, crate::common::R>
1380    {
1381        crate::common::RegisterField::<0,0xffffff,1,0,u32,u32,Adcr_SPEC,crate::common::R>::from_register(self,0)
1382    }
1383
1384    #[doc = "These bits are read as 0000000000000000. The write value should be 0000000000000000."]
1385    #[inline(always)]
1386    pub fn reserved(
1387        self,
1388    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Adcr_SPEC, crate::common::RW> {
1389        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Adcr_SPEC,crate::common::RW>::from_register(self,0)
1390    }
1391}
1392impl ::core::default::Default for Adcr {
1393    #[inline(always)]
1394    fn default() -> Adcr {
1395        <crate::RegValueT<Adcr_SPEC> as RegisterValue<_>>::new(0)
1396    }
1397}
1398pub mod adcr {
1399
1400    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1401    pub struct Sdadcrc_SPEC;
1402    pub type Sdadcrc = crate::EnumBitfieldStruct<u8, Sdadcrc_SPEC>;
1403    impl Sdadcrc {
1404        #[doc = "Reset value (Conversion result is invalid)"]
1405        pub const _000: Self = Self::new(0);
1406
1407        #[doc = "Input multiplexer 0 (ANSD0P / ANSD0N)"]
1408        pub const _001: Self = Self::new(1);
1409
1410        #[doc = "Input multiplexer 1 (ANSD1P / ANSD1N)"]
1411        pub const _010: Self = Self::new(2);
1412
1413        #[doc = "Input multiplexer 2 (ANSD2P / ANSD2N)"]
1414        pub const _011: Self = Self::new(3);
1415
1416        #[doc = "Input multiplexer 3 (ANSD3P / ANSD3N)"]
1417        pub const _100: Self = Self::new(4);
1418
1419        #[doc = "Input multiplexer 4 (AMP0O / AMP1O)"]
1420        pub const _101: Self = Self::new(5);
1421    }
1422    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1423    pub struct Sdadcrs_SPEC;
1424    pub type Sdadcrs = crate::EnumBitfieldStruct<u8, Sdadcrs_SPEC>;
1425    impl Sdadcrs {
1426        #[doc = "Normal status (within the range)"]
1427        pub const _0: Self = Self::new(0);
1428
1429        #[doc = "Overflow occurred"]
1430        pub const _1: Self = Self::new(1);
1431    }
1432}
1433#[doc(hidden)]
1434#[derive(Copy, Clone, Eq, PartialEq)]
1435pub struct Adar_SPEC;
1436impl crate::sealed::RegSpec for Adar_SPEC {
1437    type DataType = u32;
1438}
1439
1440#[doc = "Sigma-delta A/D Converter Average Value Register"]
1441pub type Adar = crate::RegValueT<Adar_SPEC>;
1442
1443impl Adar {
1444    #[doc = "Channel number for an A/D conversion result"]
1445    #[inline(always)]
1446    pub fn sdadmvc(
1447        self,
1448    ) -> crate::common::RegisterField<
1449        25,
1450        0x7,
1451        1,
1452        0,
1453        adar::Sdadmvc,
1454        adar::Sdadmvc,
1455        Adar_SPEC,
1456        crate::common::R,
1457    > {
1458        crate::common::RegisterField::<
1459            25,
1460            0x7,
1461            1,
1462            0,
1463            adar::Sdadmvc,
1464            adar::Sdadmvc,
1465            Adar_SPEC,
1466            crate::common::R,
1467        >::from_register(self, 0)
1468    }
1469
1470    #[doc = "Status of an A/D conversion result"]
1471    #[inline(always)]
1472    pub fn sdadmvs(
1473        self,
1474    ) -> crate::common::RegisterField<
1475        24,
1476        0x1,
1477        1,
1478        0,
1479        adar::Sdadmvs,
1480        adar::Sdadmvs,
1481        Adar_SPEC,
1482        crate::common::R,
1483    > {
1484        crate::common::RegisterField::<
1485            24,
1486            0x1,
1487            1,
1488            0,
1489            adar::Sdadmvs,
1490            adar::Sdadmvs,
1491            Adar_SPEC,
1492            crate::common::R,
1493        >::from_register(self, 0)
1494    }
1495
1496    #[doc = "The 24-bit A/D average value"]
1497    #[inline(always)]
1498    pub fn sdadmvd(
1499        self,
1500    ) -> crate::common::RegisterField<0, 0xffffff, 1, 0, u32, u32, Adar_SPEC, crate::common::R>
1501    {
1502        crate::common::RegisterField::<0,0xffffff,1,0,u32,u32,Adar_SPEC,crate::common::R>::from_register(self,0)
1503    }
1504
1505    #[doc = "These bits are read as 0000000000000000."]
1506    #[inline(always)]
1507    pub fn reserved(
1508        self,
1509    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Adar_SPEC, crate::common::R> {
1510        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Adar_SPEC,crate::common::R>::from_register(self,0)
1511    }
1512}
1513impl ::core::default::Default for Adar {
1514    #[inline(always)]
1515    fn default() -> Adar {
1516        <crate::RegValueT<Adar_SPEC> as RegisterValue<_>>::new(0)
1517    }
1518}
1519pub mod adar {
1520
1521    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1522    pub struct Sdadmvc_SPEC;
1523    pub type Sdadmvc = crate::EnumBitfieldStruct<u8, Sdadmvc_SPEC>;
1524    impl Sdadmvc {
1525        #[doc = "Reset value (Conversion result is invalid)"]
1526        pub const _000: Self = Self::new(0);
1527
1528        #[doc = "Input multiplexer 0 (ANSD0P / ANSD0N)"]
1529        pub const _001: Self = Self::new(1);
1530
1531        #[doc = "Input multiplexer 1 (ANSD1P / ANSD1N)"]
1532        pub const _010: Self = Self::new(2);
1533
1534        #[doc = "Input multiplexer 2 (ANSD2P / ANSD2N)"]
1535        pub const _011: Self = Self::new(3);
1536
1537        #[doc = "Input multiplexer 3 (ANSD3P / ANSD3N)"]
1538        pub const _100: Self = Self::new(4);
1539
1540        #[doc = "Input multiplexer 4 (AMP0O / AMP1O)."]
1541        pub const _101: Self = Self::new(5);
1542    }
1543    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1544    pub struct Sdadmvs_SPEC;
1545    pub type Sdadmvs = crate::EnumBitfieldStruct<u8, Sdadmvs_SPEC>;
1546    impl Sdadmvs {
1547        #[doc = "Normal status (within the range)"]
1548        pub const _0: Self = Self::new(0);
1549
1550        #[doc = "Overflow occurred"]
1551        pub const _1: Self = Self::new(1);
1552    }
1553}
1554#[doc(hidden)]
1555#[derive(Copy, Clone, Eq, PartialEq)]
1556pub struct Clbc_SPEC;
1557impl crate::sealed::RegSpec for Clbc_SPEC {
1558    type DataType = u8;
1559}
1560
1561#[doc = "Calibration Control Register"]
1562pub type Clbc = crate::RegValueT<Clbc_SPEC>;
1563
1564impl Clbc {
1565    #[doc = "These bits are read as 000000. The write value should be 000000."]
1566    #[inline(always)]
1567    pub fn reserved(
1568        self,
1569    ) -> crate::common::RegisterField<2, 0x3f, 1, 0, u8, u8, Clbc_SPEC, crate::common::RW> {
1570        crate::common::RegisterField::<2,0x3f,1,0,u8,u8,Clbc_SPEC,crate::common::RW>::from_register(self,0)
1571    }
1572
1573    #[doc = "These bits are read as 0. The write value should be 0."]
1574    #[inline(always)]
1575    pub fn clbmd(
1576        self,
1577    ) -> crate::common::RegisterField<
1578        0,
1579        0x3,
1580        1,
1581        0,
1582        clbc::Clbmd,
1583        clbc::Clbmd,
1584        Clbc_SPEC,
1585        crate::common::RW,
1586    > {
1587        crate::common::RegisterField::<
1588            0,
1589            0x3,
1590            1,
1591            0,
1592            clbc::Clbmd,
1593            clbc::Clbmd,
1594            Clbc_SPEC,
1595            crate::common::RW,
1596        >::from_register(self, 0)
1597    }
1598}
1599impl ::core::default::Default for Clbc {
1600    #[inline(always)]
1601    fn default() -> Clbc {
1602        <crate::RegValueT<Clbc_SPEC> as RegisterValue<_>>::new(0)
1603    }
1604}
1605pub mod clbc {
1606
1607    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1608    pub struct Clbmd_SPEC;
1609    pub type Clbmd = crate::EnumBitfieldStruct<u8, Clbmd_SPEC>;
1610    impl Clbmd {
1611        #[doc = "Internal calibration mode"]
1612        pub const _00: Self = Self::new(0);
1613
1614        #[doc = "External offset calibration mode"]
1615        pub const _01: Self = Self::new(1);
1616
1617        #[doc = "External gain calibration mode"]
1618        pub const _10: Self = Self::new(2);
1619
1620        #[doc = "Settings are prohibited"]
1621        pub const _11: Self = Self::new(3);
1622    }
1623}
1624#[doc(hidden)]
1625#[derive(Copy, Clone, Eq, PartialEq)]
1626pub struct Clbstr_SPEC;
1627impl crate::sealed::RegSpec for Clbstr_SPEC {
1628    type DataType = u8;
1629}
1630
1631#[doc = "Calibration Start Control Register"]
1632pub type Clbstr = crate::RegValueT<Clbstr_SPEC>;
1633
1634impl Clbstr {
1635    #[doc = "These bits are read as 0000000. The write value should be 0000000."]
1636    #[inline(always)]
1637    pub fn reserved(
1638        self,
1639    ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Clbstr_SPEC, crate::common::RW> {
1640        crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Clbstr_SPEC,crate::common::RW>::from_register(self,0)
1641    }
1642
1643    #[doc = "Calibration start control"]
1644    #[inline(always)]
1645    pub fn clbst(
1646        self,
1647    ) -> crate::common::RegisterField<
1648        0,
1649        0x1,
1650        1,
1651        0,
1652        clbstr::Clbst,
1653        clbstr::Clbst,
1654        Clbstr_SPEC,
1655        crate::common::RW,
1656    > {
1657        crate::common::RegisterField::<
1658            0,
1659            0x1,
1660            1,
1661            0,
1662            clbstr::Clbst,
1663            clbstr::Clbst,
1664            Clbstr_SPEC,
1665            crate::common::RW,
1666        >::from_register(self, 0)
1667    }
1668}
1669impl ::core::default::Default for Clbstr {
1670    #[inline(always)]
1671    fn default() -> Clbstr {
1672        <crate::RegValueT<Clbstr_SPEC> as RegisterValue<_>>::new(0)
1673    }
1674}
1675pub mod clbstr {
1676
1677    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1678    pub struct Clbst_SPEC;
1679    pub type Clbst = crate::EnumBitfieldStruct<u8, Clbst_SPEC>;
1680    impl Clbst {
1681        #[doc = "Disable writing"]
1682        pub const _0: Self = Self::new(0);
1683
1684        #[doc = "Start calibration"]
1685        pub const _1: Self = Self::new(1);
1686    }
1687}
1688#[doc(hidden)]
1689#[derive(Copy, Clone, Eq, PartialEq)]
1690pub struct Clbssr_SPEC;
1691impl crate::sealed::RegSpec for Clbssr_SPEC {
1692    type DataType = u8;
1693}
1694
1695#[doc = "Calibration Status Register"]
1696pub type Clbssr = crate::RegValueT<Clbssr_SPEC>;
1697
1698impl Clbssr {
1699    #[doc = "These bits are read as 0000000."]
1700    #[inline(always)]
1701    pub fn reserved(
1702        self,
1703    ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Clbssr_SPEC, crate::common::R> {
1704        crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Clbssr_SPEC,crate::common::R>::from_register(self,0)
1705    }
1706
1707    #[doc = "Calibration status"]
1708    #[inline(always)]
1709    pub fn clbss(
1710        self,
1711    ) -> crate::common::RegisterField<
1712        0,
1713        0x1,
1714        1,
1715        0,
1716        clbssr::Clbss,
1717        clbssr::Clbss,
1718        Clbssr_SPEC,
1719        crate::common::R,
1720    > {
1721        crate::common::RegisterField::<
1722            0,
1723            0x1,
1724            1,
1725            0,
1726            clbssr::Clbss,
1727            clbssr::Clbss,
1728            Clbssr_SPEC,
1729            crate::common::R,
1730        >::from_register(self, 0)
1731    }
1732}
1733impl ::core::default::Default for Clbssr {
1734    #[inline(always)]
1735    fn default() -> Clbssr {
1736        <crate::RegValueT<Clbssr_SPEC> as RegisterValue<_>>::new(0)
1737    }
1738}
1739pub mod clbssr {
1740
1741    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1742    pub struct Clbss_SPEC;
1743    pub type Clbss = crate::EnumBitfieldStruct<u8, Clbss_SPEC>;
1744    impl Clbss {
1745        #[doc = "Calibration is not running"]
1746        pub const _0: Self = Self::new(0);
1747
1748        #[doc = "Calibration is running"]
1749        pub const _1: Self = Self::new(1);
1750    }
1751}
ra2a1_pac/sdadc24.rs

ra2a1_pac/
sdadc24.rs
