1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Pmn Pin Function Control Register"]
28unsafe impl ::core::marker::Send for super::Pfs {}
29unsafe impl ::core::marker::Sync for super::Pfs {}
30impl super::Pfs {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "P000 Pin Function Control Register"]
38 #[inline(always)]
39 pub const fn p000pfs(
40 &self,
41 ) -> &'static crate::common::Reg<self::P000Pfs_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::P000Pfs_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "P000 Pin Function Control Register"]
50 #[inline(always)]
51 pub const fn p000pfs_ha(
52 &self,
53 ) -> &'static crate::common::Reg<self::P000PfsHa_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::P000PfsHa_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(2usize),
57 )
58 }
59 }
60
61 #[doc = "P000 Pin Function Control Register"]
62 #[inline(always)]
63 pub const fn p000pfs_by(
64 &self,
65 ) -> &'static crate::common::Reg<self::P000PfsBy_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::P000PfsBy_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(3usize),
69 )
70 }
71 }
72
73 #[doc = "P00%s Pin Function Control Register"]
74 #[inline(always)]
75 pub const fn p00pfs(
76 &self,
77 ) -> &'static crate::common::ClusterRegisterArray<
78 crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW>,
79 3,
80 0x4,
81 > {
82 unsafe {
83 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x4usize))
84 }
85 }
86 #[inline(always)]
87 pub const fn p001pfs(
88 &self,
89 ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(0x4usize),
93 )
94 }
95 }
96 #[inline(always)]
97 pub const fn p002pfs(
98 &self,
99 ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
100 unsafe {
101 crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
102 self._svd2pac_as_ptr().add(0x8usize),
103 )
104 }
105 }
106 #[inline(always)]
107 pub const fn p003pfs(
108 &self,
109 ) -> &'static crate::common::Reg<self::P00Pfs_SPEC, crate::common::RW> {
110 unsafe {
111 crate::common::Reg::<self::P00Pfs_SPEC, crate::common::RW>::from_ptr(
112 self._svd2pac_as_ptr().add(0xcusize),
113 )
114 }
115 }
116
117 #[doc = "P00%s Pin Function Control Register"]
118 #[inline(always)]
119 pub const fn p00pfs_ha(
120 &self,
121 ) -> &'static crate::common::ClusterRegisterArray<
122 crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW>,
123 3,
124 0x4,
125 > {
126 unsafe {
127 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6usize))
128 }
129 }
130 #[inline(always)]
131 pub const fn p001pfs_ha(
132 &self,
133 ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
134 unsafe {
135 crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
136 self._svd2pac_as_ptr().add(0x6usize),
137 )
138 }
139 }
140 #[inline(always)]
141 pub const fn p002pfs_ha(
142 &self,
143 ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
144 unsafe {
145 crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
146 self._svd2pac_as_ptr().add(0xausize),
147 )
148 }
149 }
150 #[inline(always)]
151 pub const fn p003pfs_ha(
152 &self,
153 ) -> &'static crate::common::Reg<self::P00PfsHa_SPEC, crate::common::RW> {
154 unsafe {
155 crate::common::Reg::<self::P00PfsHa_SPEC, crate::common::RW>::from_ptr(
156 self._svd2pac_as_ptr().add(0xeusize),
157 )
158 }
159 }
160
161 #[doc = "P00%s Pin Function Control Register"]
162 #[inline(always)]
163 pub const fn p00pfs_by(
164 &self,
165 ) -> &'static crate::common::ClusterRegisterArray<
166 crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW>,
167 3,
168 0x4,
169 > {
170 unsafe {
171 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x7usize))
172 }
173 }
174 #[inline(always)]
175 pub const fn p001pfs_by(
176 &self,
177 ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
178 unsafe {
179 crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
180 self._svd2pac_as_ptr().add(0x7usize),
181 )
182 }
183 }
184 #[inline(always)]
185 pub const fn p002pfs_by(
186 &self,
187 ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
188 unsafe {
189 crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
190 self._svd2pac_as_ptr().add(0xbusize),
191 )
192 }
193 }
194 #[inline(always)]
195 pub const fn p003pfs_by(
196 &self,
197 ) -> &'static crate::common::Reg<self::P00PfsBy_SPEC, crate::common::RW> {
198 unsafe {
199 crate::common::Reg::<self::P00PfsBy_SPEC, crate::common::RW>::from_ptr(
200 self._svd2pac_as_ptr().add(0xfusize),
201 )
202 }
203 }
204
205 #[doc = "P0%s Pin Function Control Register"]
206 #[inline(always)]
207 pub const fn p0pfs(
208 &self,
209 ) -> &'static crate::common::ClusterRegisterArray<
210 crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW>,
211 4,
212 0x4,
213 > {
214 unsafe {
215 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x30usize))
216 }
217 }
218 #[inline(always)]
219 pub const fn p012pfs(
220 &self,
221 ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
222 unsafe {
223 crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
224 self._svd2pac_as_ptr().add(0x30usize),
225 )
226 }
227 }
228 #[inline(always)]
229 pub const fn p013pfs(
230 &self,
231 ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
232 unsafe {
233 crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
234 self._svd2pac_as_ptr().add(0x34usize),
235 )
236 }
237 }
238 #[inline(always)]
239 pub const fn p014pfs(
240 &self,
241 ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
242 unsafe {
243 crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
244 self._svd2pac_as_ptr().add(0x38usize),
245 )
246 }
247 }
248 #[inline(always)]
249 pub const fn p015pfs(
250 &self,
251 ) -> &'static crate::common::Reg<self::P0Pfs_SPEC, crate::common::RW> {
252 unsafe {
253 crate::common::Reg::<self::P0Pfs_SPEC, crate::common::RW>::from_ptr(
254 self._svd2pac_as_ptr().add(0x3cusize),
255 )
256 }
257 }
258
259 #[doc = "P0%s Pin Function Control Register"]
260 #[inline(always)]
261 pub const fn p0pfs_ha(
262 &self,
263 ) -> &'static crate::common::ClusterRegisterArray<
264 crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW>,
265 4,
266 0x4,
267 > {
268 unsafe {
269 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x32usize))
270 }
271 }
272 #[inline(always)]
273 pub const fn p012pfs_ha(
274 &self,
275 ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
276 unsafe {
277 crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
278 self._svd2pac_as_ptr().add(0x32usize),
279 )
280 }
281 }
282 #[inline(always)]
283 pub const fn p013pfs_ha(
284 &self,
285 ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
286 unsafe {
287 crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
288 self._svd2pac_as_ptr().add(0x36usize),
289 )
290 }
291 }
292 #[inline(always)]
293 pub const fn p014pfs_ha(
294 &self,
295 ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
296 unsafe {
297 crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
298 self._svd2pac_as_ptr().add(0x3ausize),
299 )
300 }
301 }
302 #[inline(always)]
303 pub const fn p015pfs_ha(
304 &self,
305 ) -> &'static crate::common::Reg<self::P0PfsHa_SPEC, crate::common::RW> {
306 unsafe {
307 crate::common::Reg::<self::P0PfsHa_SPEC, crate::common::RW>::from_ptr(
308 self._svd2pac_as_ptr().add(0x3eusize),
309 )
310 }
311 }
312
313 #[doc = "P0%s Pin Function Control Register"]
314 #[inline(always)]
315 pub const fn p0pfs_by(
316 &self,
317 ) -> &'static crate::common::ClusterRegisterArray<
318 crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW>,
319 4,
320 0x4,
321 > {
322 unsafe {
323 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x33usize))
324 }
325 }
326 #[inline(always)]
327 pub const fn p012pfs_by(
328 &self,
329 ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
330 unsafe {
331 crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
332 self._svd2pac_as_ptr().add(0x33usize),
333 )
334 }
335 }
336 #[inline(always)]
337 pub const fn p013pfs_by(
338 &self,
339 ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
340 unsafe {
341 crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
342 self._svd2pac_as_ptr().add(0x37usize),
343 )
344 }
345 }
346 #[inline(always)]
347 pub const fn p014pfs_by(
348 &self,
349 ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
350 unsafe {
351 crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
352 self._svd2pac_as_ptr().add(0x3busize),
353 )
354 }
355 }
356 #[inline(always)]
357 pub const fn p015pfs_by(
358 &self,
359 ) -> &'static crate::common::Reg<self::P0PfsBy_SPEC, crate::common::RW> {
360 unsafe {
361 crate::common::Reg::<self::P0PfsBy_SPEC, crate::common::RW>::from_ptr(
362 self._svd2pac_as_ptr().add(0x3fusize),
363 )
364 }
365 }
366
367 #[doc = "P100 Pin Function Control Register"]
368 #[inline(always)]
369 pub const fn p100pfs(
370 &self,
371 ) -> &'static crate::common::Reg<self::P100Pfs_SPEC, crate::common::RW> {
372 unsafe {
373 crate::common::Reg::<self::P100Pfs_SPEC, crate::common::RW>::from_ptr(
374 self._svd2pac_as_ptr().add(64usize),
375 )
376 }
377 }
378
379 #[doc = "P100 Pin Function Control Register"]
380 #[inline(always)]
381 pub const fn p100pfs_ha(
382 &self,
383 ) -> &'static crate::common::Reg<self::P100PfsHa_SPEC, crate::common::RW> {
384 unsafe {
385 crate::common::Reg::<self::P100PfsHa_SPEC, crate::common::RW>::from_ptr(
386 self._svd2pac_as_ptr().add(66usize),
387 )
388 }
389 }
390
391 #[doc = "P100 Pin Function Control Register"]
392 #[inline(always)]
393 pub const fn p100pfs_by(
394 &self,
395 ) -> &'static crate::common::Reg<self::P100PfsBy_SPEC, crate::common::RW> {
396 unsafe {
397 crate::common::Reg::<self::P100PfsBy_SPEC, crate::common::RW>::from_ptr(
398 self._svd2pac_as_ptr().add(67usize),
399 )
400 }
401 }
402
403 #[doc = "P10%s Pin Function Control Register"]
404 #[inline(always)]
405 pub const fn p10pfs(
406 &self,
407 ) -> &'static crate::common::ClusterRegisterArray<
408 crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW>,
409 7,
410 0x4,
411 > {
412 unsafe {
413 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x44usize))
414 }
415 }
416 #[inline(always)]
417 pub const fn p101pfs(
418 &self,
419 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
420 unsafe {
421 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
422 self._svd2pac_as_ptr().add(0x44usize),
423 )
424 }
425 }
426 #[inline(always)]
427 pub const fn p102pfs(
428 &self,
429 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
430 unsafe {
431 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
432 self._svd2pac_as_ptr().add(0x48usize),
433 )
434 }
435 }
436 #[inline(always)]
437 pub const fn p103pfs(
438 &self,
439 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
440 unsafe {
441 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
442 self._svd2pac_as_ptr().add(0x4cusize),
443 )
444 }
445 }
446 #[inline(always)]
447 pub const fn p104pfs(
448 &self,
449 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
450 unsafe {
451 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
452 self._svd2pac_as_ptr().add(0x50usize),
453 )
454 }
455 }
456 #[inline(always)]
457 pub const fn p105pfs(
458 &self,
459 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
460 unsafe {
461 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
462 self._svd2pac_as_ptr().add(0x54usize),
463 )
464 }
465 }
466 #[inline(always)]
467 pub const fn p106pfs(
468 &self,
469 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
470 unsafe {
471 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
472 self._svd2pac_as_ptr().add(0x58usize),
473 )
474 }
475 }
476 #[inline(always)]
477 pub const fn p107pfs(
478 &self,
479 ) -> &'static crate::common::Reg<self::P10Pfs_SPEC, crate::common::RW> {
480 unsafe {
481 crate::common::Reg::<self::P10Pfs_SPEC, crate::common::RW>::from_ptr(
482 self._svd2pac_as_ptr().add(0x5cusize),
483 )
484 }
485 }
486
487 #[doc = "P10%s Pin Function Control Register"]
488 #[inline(always)]
489 pub const fn p10pfs_ha(
490 &self,
491 ) -> &'static crate::common::ClusterRegisterArray<
492 crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW>,
493 7,
494 0x4,
495 > {
496 unsafe {
497 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x46usize))
498 }
499 }
500 #[inline(always)]
501 pub const fn p101pfs_ha(
502 &self,
503 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
504 unsafe {
505 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
506 self._svd2pac_as_ptr().add(0x46usize),
507 )
508 }
509 }
510 #[inline(always)]
511 pub const fn p102pfs_ha(
512 &self,
513 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
514 unsafe {
515 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
516 self._svd2pac_as_ptr().add(0x4ausize),
517 )
518 }
519 }
520 #[inline(always)]
521 pub const fn p103pfs_ha(
522 &self,
523 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
524 unsafe {
525 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
526 self._svd2pac_as_ptr().add(0x4eusize),
527 )
528 }
529 }
530 #[inline(always)]
531 pub const fn p104pfs_ha(
532 &self,
533 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
534 unsafe {
535 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
536 self._svd2pac_as_ptr().add(0x52usize),
537 )
538 }
539 }
540 #[inline(always)]
541 pub const fn p105pfs_ha(
542 &self,
543 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
544 unsafe {
545 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
546 self._svd2pac_as_ptr().add(0x56usize),
547 )
548 }
549 }
550 #[inline(always)]
551 pub const fn p106pfs_ha(
552 &self,
553 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
554 unsafe {
555 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
556 self._svd2pac_as_ptr().add(0x5ausize),
557 )
558 }
559 }
560 #[inline(always)]
561 pub const fn p107pfs_ha(
562 &self,
563 ) -> &'static crate::common::Reg<self::P10PfsHa_SPEC, crate::common::RW> {
564 unsafe {
565 crate::common::Reg::<self::P10PfsHa_SPEC, crate::common::RW>::from_ptr(
566 self._svd2pac_as_ptr().add(0x5eusize),
567 )
568 }
569 }
570
571 #[doc = "P10%s Pin Function Control Register"]
572 #[inline(always)]
573 pub const fn p10pfs_by(
574 &self,
575 ) -> &'static crate::common::ClusterRegisterArray<
576 crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW>,
577 7,
578 0x4,
579 > {
580 unsafe {
581 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x47usize))
582 }
583 }
584 #[inline(always)]
585 pub const fn p101pfs_by(
586 &self,
587 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
588 unsafe {
589 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
590 self._svd2pac_as_ptr().add(0x47usize),
591 )
592 }
593 }
594 #[inline(always)]
595 pub const fn p102pfs_by(
596 &self,
597 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
598 unsafe {
599 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
600 self._svd2pac_as_ptr().add(0x4busize),
601 )
602 }
603 }
604 #[inline(always)]
605 pub const fn p103pfs_by(
606 &self,
607 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
608 unsafe {
609 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
610 self._svd2pac_as_ptr().add(0x4fusize),
611 )
612 }
613 }
614 #[inline(always)]
615 pub const fn p104pfs_by(
616 &self,
617 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
618 unsafe {
619 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
620 self._svd2pac_as_ptr().add(0x53usize),
621 )
622 }
623 }
624 #[inline(always)]
625 pub const fn p105pfs_by(
626 &self,
627 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
628 unsafe {
629 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
630 self._svd2pac_as_ptr().add(0x57usize),
631 )
632 }
633 }
634 #[inline(always)]
635 pub const fn p106pfs_by(
636 &self,
637 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
638 unsafe {
639 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
640 self._svd2pac_as_ptr().add(0x5busize),
641 )
642 }
643 }
644 #[inline(always)]
645 pub const fn p107pfs_by(
646 &self,
647 ) -> &'static crate::common::Reg<self::P10PfsBy_SPEC, crate::common::RW> {
648 unsafe {
649 crate::common::Reg::<self::P10PfsBy_SPEC, crate::common::RW>::from_ptr(
650 self._svd2pac_as_ptr().add(0x5fusize),
651 )
652 }
653 }
654
655 #[doc = "P108 Pin Function Control Register"]
656 #[inline(always)]
657 pub const fn p108pfs(
658 &self,
659 ) -> &'static crate::common::Reg<self::P108Pfs_SPEC, crate::common::RW> {
660 unsafe {
661 crate::common::Reg::<self::P108Pfs_SPEC, crate::common::RW>::from_ptr(
662 self._svd2pac_as_ptr().add(96usize),
663 )
664 }
665 }
666
667 #[doc = "P108 Pin Function Control Register"]
668 #[inline(always)]
669 pub const fn p108pfs_ha(
670 &self,
671 ) -> &'static crate::common::Reg<self::P108PfsHa_SPEC, crate::common::RW> {
672 unsafe {
673 crate::common::Reg::<self::P108PfsHa_SPEC, crate::common::RW>::from_ptr(
674 self._svd2pac_as_ptr().add(98usize),
675 )
676 }
677 }
678
679 #[doc = "P108 Pin Function Control Register"]
680 #[inline(always)]
681 pub const fn p108pfs_by(
682 &self,
683 ) -> &'static crate::common::Reg<self::P108PfsBy_SPEC, crate::common::RW> {
684 unsafe {
685 crate::common::Reg::<self::P108PfsBy_SPEC, crate::common::RW>::from_ptr(
686 self._svd2pac_as_ptr().add(99usize),
687 )
688 }
689 }
690
691 #[doc = "P109 Pin Function Control Register"]
692 #[inline(always)]
693 pub const fn p109pfs(
694 &self,
695 ) -> &'static crate::common::Reg<self::P109Pfs_SPEC, crate::common::RW> {
696 unsafe {
697 crate::common::Reg::<self::P109Pfs_SPEC, crate::common::RW>::from_ptr(
698 self._svd2pac_as_ptr().add(100usize),
699 )
700 }
701 }
702
703 #[doc = "P109 Pin Function Control Register"]
704 #[inline(always)]
705 pub const fn p109pfs_ha(
706 &self,
707 ) -> &'static crate::common::Reg<self::P109PfsHa_SPEC, crate::common::RW> {
708 unsafe {
709 crate::common::Reg::<self::P109PfsHa_SPEC, crate::common::RW>::from_ptr(
710 self._svd2pac_as_ptr().add(102usize),
711 )
712 }
713 }
714
715 #[doc = "P109 Pin Function Control Register"]
716 #[inline(always)]
717 pub const fn p109pfs_by(
718 &self,
719 ) -> &'static crate::common::Reg<self::P109PfsBy_SPEC, crate::common::RW> {
720 unsafe {
721 crate::common::Reg::<self::P109PfsBy_SPEC, crate::common::RW>::from_ptr(
722 self._svd2pac_as_ptr().add(103usize),
723 )
724 }
725 }
726
727 #[doc = "P1%s Pin Function Control Register"]
728 #[inline(always)]
729 pub const fn p1pfs(
730 &self,
731 ) -> &'static crate::common::ClusterRegisterArray<
732 crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW>,
733 3,
734 0x4,
735 > {
736 unsafe {
737 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x68usize))
738 }
739 }
740 #[inline(always)]
741 pub const fn p110pfs(
742 &self,
743 ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
744 unsafe {
745 crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
746 self._svd2pac_as_ptr().add(0x68usize),
747 )
748 }
749 }
750 #[inline(always)]
751 pub const fn p111pfs(
752 &self,
753 ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
754 unsafe {
755 crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
756 self._svd2pac_as_ptr().add(0x6cusize),
757 )
758 }
759 }
760 #[inline(always)]
761 pub const fn p112pfs(
762 &self,
763 ) -> &'static crate::common::Reg<self::P1Pfs_SPEC, crate::common::RW> {
764 unsafe {
765 crate::common::Reg::<self::P1Pfs_SPEC, crate::common::RW>::from_ptr(
766 self._svd2pac_as_ptr().add(0x70usize),
767 )
768 }
769 }
770
771 #[doc = "P1%s Pin Function Control Register"]
772 #[inline(always)]
773 pub const fn p1pfs_ha(
774 &self,
775 ) -> &'static crate::common::ClusterRegisterArray<
776 crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW>,
777 3,
778 0x4,
779 > {
780 unsafe {
781 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6ausize))
782 }
783 }
784 #[inline(always)]
785 pub const fn p110pfs_ha(
786 &self,
787 ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
788 unsafe {
789 crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
790 self._svd2pac_as_ptr().add(0x6ausize),
791 )
792 }
793 }
794 #[inline(always)]
795 pub const fn p111pfs_ha(
796 &self,
797 ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
798 unsafe {
799 crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
800 self._svd2pac_as_ptr().add(0x6eusize),
801 )
802 }
803 }
804 #[inline(always)]
805 pub const fn p112pfs_ha(
806 &self,
807 ) -> &'static crate::common::Reg<self::P1PfsHa_SPEC, crate::common::RW> {
808 unsafe {
809 crate::common::Reg::<self::P1PfsHa_SPEC, crate::common::RW>::from_ptr(
810 self._svd2pac_as_ptr().add(0x72usize),
811 )
812 }
813 }
814
815 #[doc = "P1%s Pin Function Control Register"]
816 #[inline(always)]
817 pub const fn p1pfs_by(
818 &self,
819 ) -> &'static crate::common::ClusterRegisterArray<
820 crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW>,
821 3,
822 0x4,
823 > {
824 unsafe {
825 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x6busize))
826 }
827 }
828 #[inline(always)]
829 pub const fn p110pfs_by(
830 &self,
831 ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
832 unsafe {
833 crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
834 self._svd2pac_as_ptr().add(0x6busize),
835 )
836 }
837 }
838 #[inline(always)]
839 pub const fn p111pfs_by(
840 &self,
841 ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
842 unsafe {
843 crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
844 self._svd2pac_as_ptr().add(0x6fusize),
845 )
846 }
847 }
848 #[inline(always)]
849 pub const fn p112pfs_by(
850 &self,
851 ) -> &'static crate::common::Reg<self::P1PfsBy_SPEC, crate::common::RW> {
852 unsafe {
853 crate::common::Reg::<self::P1PfsBy_SPEC, crate::common::RW>::from_ptr(
854 self._svd2pac_as_ptr().add(0x73usize),
855 )
856 }
857 }
858
859 #[doc = "P200 Pin Function Control Register"]
860 #[inline(always)]
861 pub const fn p200pfs(
862 &self,
863 ) -> &'static crate::common::Reg<self::P200Pfs_SPEC, crate::common::RW> {
864 unsafe {
865 crate::common::Reg::<self::P200Pfs_SPEC, crate::common::RW>::from_ptr(
866 self._svd2pac_as_ptr().add(128usize),
867 )
868 }
869 }
870
871 #[doc = "P200 Pin Function Control Register"]
872 #[inline(always)]
873 pub const fn p200pfs_ha(
874 &self,
875 ) -> &'static crate::common::Reg<self::P200PfsHa_SPEC, crate::common::RW> {
876 unsafe {
877 crate::common::Reg::<self::P200PfsHa_SPEC, crate::common::RW>::from_ptr(
878 self._svd2pac_as_ptr().add(130usize),
879 )
880 }
881 }
882
883 #[doc = "P200 Pin Function Control Register"]
884 #[inline(always)]
885 pub const fn p200pfs_by(
886 &self,
887 ) -> &'static crate::common::Reg<self::P200PfsBy_SPEC, crate::common::RW> {
888 unsafe {
889 crate::common::Reg::<self::P200PfsBy_SPEC, crate::common::RW>::from_ptr(
890 self._svd2pac_as_ptr().add(131usize),
891 )
892 }
893 }
894
895 #[doc = "P201 Pin Function Control Register"]
896 #[inline(always)]
897 pub const fn p201pfs(
898 &self,
899 ) -> &'static crate::common::Reg<self::P201Pfs_SPEC, crate::common::RW> {
900 unsafe {
901 crate::common::Reg::<self::P201Pfs_SPEC, crate::common::RW>::from_ptr(
902 self._svd2pac_as_ptr().add(132usize),
903 )
904 }
905 }
906
907 #[doc = "P201 Pin Function Control Register"]
908 #[inline(always)]
909 pub const fn p201pfs_ha(
910 &self,
911 ) -> &'static crate::common::Reg<self::P201PfsHa_SPEC, crate::common::RW> {
912 unsafe {
913 crate::common::Reg::<self::P201PfsHa_SPEC, crate::common::RW>::from_ptr(
914 self._svd2pac_as_ptr().add(134usize),
915 )
916 }
917 }
918
919 #[doc = "P201 Pin Function Control Register"]
920 #[inline(always)]
921 pub const fn p201pfs_by(
922 &self,
923 ) -> &'static crate::common::Reg<self::P201PfsBy_SPEC, crate::common::RW> {
924 unsafe {
925 crate::common::Reg::<self::P201PfsBy_SPEC, crate::common::RW>::from_ptr(
926 self._svd2pac_as_ptr().add(135usize),
927 )
928 }
929 }
930
931 #[doc = "P20%s Pin Function Control Register"]
932 #[inline(always)]
933 pub const fn p20pfs(
934 &self,
935 ) -> &'static crate::common::ClusterRegisterArray<
936 crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW>,
937 3,
938 0x4,
939 > {
940 unsafe {
941 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x90usize))
942 }
943 }
944 #[inline(always)]
945 pub const fn p204pfs(
946 &self,
947 ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
948 unsafe {
949 crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
950 self._svd2pac_as_ptr().add(0x90usize),
951 )
952 }
953 }
954 #[inline(always)]
955 pub const fn p205pfs(
956 &self,
957 ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
958 unsafe {
959 crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
960 self._svd2pac_as_ptr().add(0x94usize),
961 )
962 }
963 }
964 #[inline(always)]
965 pub const fn p206pfs(
966 &self,
967 ) -> &'static crate::common::Reg<self::P20Pfs_SPEC, crate::common::RW> {
968 unsafe {
969 crate::common::Reg::<self::P20Pfs_SPEC, crate::common::RW>::from_ptr(
970 self._svd2pac_as_ptr().add(0x98usize),
971 )
972 }
973 }
974
975 #[doc = "P20%s Pin Function Control Register"]
976 #[inline(always)]
977 pub const fn p20pfs_ha(
978 &self,
979 ) -> &'static crate::common::ClusterRegisterArray<
980 crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW>,
981 3,
982 0x4,
983 > {
984 unsafe {
985 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x92usize))
986 }
987 }
988 #[inline(always)]
989 pub const fn p204pfs_ha(
990 &self,
991 ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
992 unsafe {
993 crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
994 self._svd2pac_as_ptr().add(0x92usize),
995 )
996 }
997 }
998 #[inline(always)]
999 pub const fn p205pfs_ha(
1000 &self,
1001 ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
1002 unsafe {
1003 crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
1004 self._svd2pac_as_ptr().add(0x96usize),
1005 )
1006 }
1007 }
1008 #[inline(always)]
1009 pub const fn p206pfs_ha(
1010 &self,
1011 ) -> &'static crate::common::Reg<self::P20PfsHa_SPEC, crate::common::RW> {
1012 unsafe {
1013 crate::common::Reg::<self::P20PfsHa_SPEC, crate::common::RW>::from_ptr(
1014 self._svd2pac_as_ptr().add(0x9ausize),
1015 )
1016 }
1017 }
1018
1019 #[doc = "P20%s Pin Function Control Register"]
1020 #[inline(always)]
1021 pub const fn p20pfs_by(
1022 &self,
1023 ) -> &'static crate::common::ClusterRegisterArray<
1024 crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW>,
1025 3,
1026 0x4,
1027 > {
1028 unsafe {
1029 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x93usize))
1030 }
1031 }
1032 #[inline(always)]
1033 pub const fn p204pfs_by(
1034 &self,
1035 ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
1036 unsafe {
1037 crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
1038 self._svd2pac_as_ptr().add(0x93usize),
1039 )
1040 }
1041 }
1042 #[inline(always)]
1043 pub const fn p205pfs_by(
1044 &self,
1045 ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
1046 unsafe {
1047 crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
1048 self._svd2pac_as_ptr().add(0x97usize),
1049 )
1050 }
1051 }
1052 #[inline(always)]
1053 pub const fn p206pfs_by(
1054 &self,
1055 ) -> &'static crate::common::Reg<self::P20PfsBy_SPEC, crate::common::RW> {
1056 unsafe {
1057 crate::common::Reg::<self::P20PfsBy_SPEC, crate::common::RW>::from_ptr(
1058 self._svd2pac_as_ptr().add(0x9busize),
1059 )
1060 }
1061 }
1062
1063 #[doc = "P2%s Pin Function Control Register"]
1064 #[inline(always)]
1065 pub const fn p2pfs(
1066 &self,
1067 ) -> &'static crate::common::ClusterRegisterArray<
1068 crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW>,
1069 4,
1070 0x4,
1071 > {
1072 unsafe {
1073 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb0usize))
1074 }
1075 }
1076 #[inline(always)]
1077 pub const fn p212pfs(
1078 &self,
1079 ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1080 unsafe {
1081 crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1082 self._svd2pac_as_ptr().add(0xb0usize),
1083 )
1084 }
1085 }
1086 #[inline(always)]
1087 pub const fn p213pfs(
1088 &self,
1089 ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1090 unsafe {
1091 crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1092 self._svd2pac_as_ptr().add(0xb4usize),
1093 )
1094 }
1095 }
1096 #[inline(always)]
1097 pub const fn p214pfs(
1098 &self,
1099 ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1100 unsafe {
1101 crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1102 self._svd2pac_as_ptr().add(0xb8usize),
1103 )
1104 }
1105 }
1106 #[inline(always)]
1107 pub const fn p215pfs(
1108 &self,
1109 ) -> &'static crate::common::Reg<self::P2Pfs_SPEC, crate::common::RW> {
1110 unsafe {
1111 crate::common::Reg::<self::P2Pfs_SPEC, crate::common::RW>::from_ptr(
1112 self._svd2pac_as_ptr().add(0xbcusize),
1113 )
1114 }
1115 }
1116
1117 #[doc = "P2%s Pin Function Control Register"]
1118 #[inline(always)]
1119 pub const fn p2pfs_ha(
1120 &self,
1121 ) -> &'static crate::common::ClusterRegisterArray<
1122 crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW>,
1123 4,
1124 0x4,
1125 > {
1126 unsafe {
1127 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb2usize))
1128 }
1129 }
1130 #[inline(always)]
1131 pub const fn p212pfs_ha(
1132 &self,
1133 ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1134 unsafe {
1135 crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1136 self._svd2pac_as_ptr().add(0xb2usize),
1137 )
1138 }
1139 }
1140 #[inline(always)]
1141 pub const fn p213pfs_ha(
1142 &self,
1143 ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1144 unsafe {
1145 crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1146 self._svd2pac_as_ptr().add(0xb6usize),
1147 )
1148 }
1149 }
1150 #[inline(always)]
1151 pub const fn p214pfs_ha(
1152 &self,
1153 ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1154 unsafe {
1155 crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1156 self._svd2pac_as_ptr().add(0xbausize),
1157 )
1158 }
1159 }
1160 #[inline(always)]
1161 pub const fn p215pfs_ha(
1162 &self,
1163 ) -> &'static crate::common::Reg<self::P2PfsHa_SPEC, crate::common::RW> {
1164 unsafe {
1165 crate::common::Reg::<self::P2PfsHa_SPEC, crate::common::RW>::from_ptr(
1166 self._svd2pac_as_ptr().add(0xbeusize),
1167 )
1168 }
1169 }
1170
1171 #[doc = "P2%s Pin Function Control Register"]
1172 #[inline(always)]
1173 pub const fn p2pfs_by(
1174 &self,
1175 ) -> &'static crate::common::ClusterRegisterArray<
1176 crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW>,
1177 4,
1178 0x4,
1179 > {
1180 unsafe {
1181 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xb3usize))
1182 }
1183 }
1184 #[inline(always)]
1185 pub const fn p212pfs_by(
1186 &self,
1187 ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1188 unsafe {
1189 crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1190 self._svd2pac_as_ptr().add(0xb3usize),
1191 )
1192 }
1193 }
1194 #[inline(always)]
1195 pub const fn p213pfs_by(
1196 &self,
1197 ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1198 unsafe {
1199 crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1200 self._svd2pac_as_ptr().add(0xb7usize),
1201 )
1202 }
1203 }
1204 #[inline(always)]
1205 pub const fn p214pfs_by(
1206 &self,
1207 ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1208 unsafe {
1209 crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1210 self._svd2pac_as_ptr().add(0xbbusize),
1211 )
1212 }
1213 }
1214 #[inline(always)]
1215 pub const fn p215pfs_by(
1216 &self,
1217 ) -> &'static crate::common::Reg<self::P2PfsBy_SPEC, crate::common::RW> {
1218 unsafe {
1219 crate::common::Reg::<self::P2PfsBy_SPEC, crate::common::RW>::from_ptr(
1220 self._svd2pac_as_ptr().add(0xbfusize),
1221 )
1222 }
1223 }
1224
1225 #[doc = "P300 Pin Function Control Register"]
1226 #[inline(always)]
1227 pub const fn p300pfs(
1228 &self,
1229 ) -> &'static crate::common::Reg<self::P300Pfs_SPEC, crate::common::RW> {
1230 unsafe {
1231 crate::common::Reg::<self::P300Pfs_SPEC, crate::common::RW>::from_ptr(
1232 self._svd2pac_as_ptr().add(192usize),
1233 )
1234 }
1235 }
1236
1237 #[doc = "P300 Pin Function Control Register"]
1238 #[inline(always)]
1239 pub const fn p300pfs_ha(
1240 &self,
1241 ) -> &'static crate::common::Reg<self::P300PfsHa_SPEC, crate::common::RW> {
1242 unsafe {
1243 crate::common::Reg::<self::P300PfsHa_SPEC, crate::common::RW>::from_ptr(
1244 self._svd2pac_as_ptr().add(194usize),
1245 )
1246 }
1247 }
1248
1249 #[doc = "P300 Pin Function Control Register"]
1250 #[inline(always)]
1251 pub const fn p300pfs_by(
1252 &self,
1253 ) -> &'static crate::common::Reg<self::P300PfsBy_SPEC, crate::common::RW> {
1254 unsafe {
1255 crate::common::Reg::<self::P300PfsBy_SPEC, crate::common::RW>::from_ptr(
1256 self._svd2pac_as_ptr().add(195usize),
1257 )
1258 }
1259 }
1260
1261 #[doc = "P30%s Pin Function Control Register"]
1262 #[inline(always)]
1263 pub const fn p30pfs(
1264 &self,
1265 ) -> &'static crate::common::ClusterRegisterArray<
1266 crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW>,
1267 4,
1268 0x4,
1269 > {
1270 unsafe {
1271 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc4usize))
1272 }
1273 }
1274 #[inline(always)]
1275 pub const fn p301pfs(
1276 &self,
1277 ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1278 unsafe {
1279 crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1280 self._svd2pac_as_ptr().add(0xc4usize),
1281 )
1282 }
1283 }
1284 #[inline(always)]
1285 pub const fn p302pfs(
1286 &self,
1287 ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1288 unsafe {
1289 crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1290 self._svd2pac_as_ptr().add(0xc8usize),
1291 )
1292 }
1293 }
1294 #[inline(always)]
1295 pub const fn p303pfs(
1296 &self,
1297 ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1298 unsafe {
1299 crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1300 self._svd2pac_as_ptr().add(0xccusize),
1301 )
1302 }
1303 }
1304 #[inline(always)]
1305 pub const fn p304pfs(
1306 &self,
1307 ) -> &'static crate::common::Reg<self::P30Pfs_SPEC, crate::common::RW> {
1308 unsafe {
1309 crate::common::Reg::<self::P30Pfs_SPEC, crate::common::RW>::from_ptr(
1310 self._svd2pac_as_ptr().add(0xd0usize),
1311 )
1312 }
1313 }
1314
1315 #[doc = "P30%s Pin Function Control Register"]
1316 #[inline(always)]
1317 pub const fn p30pfs_ha(
1318 &self,
1319 ) -> &'static crate::common::ClusterRegisterArray<
1320 crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW>,
1321 4,
1322 0x4,
1323 > {
1324 unsafe {
1325 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc6usize))
1326 }
1327 }
1328 #[inline(always)]
1329 pub const fn p301pfs_ha(
1330 &self,
1331 ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1332 unsafe {
1333 crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1334 self._svd2pac_as_ptr().add(0xc6usize),
1335 )
1336 }
1337 }
1338 #[inline(always)]
1339 pub const fn p302pfs_ha(
1340 &self,
1341 ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1342 unsafe {
1343 crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1344 self._svd2pac_as_ptr().add(0xcausize),
1345 )
1346 }
1347 }
1348 #[inline(always)]
1349 pub const fn p303pfs_ha(
1350 &self,
1351 ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1352 unsafe {
1353 crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1354 self._svd2pac_as_ptr().add(0xceusize),
1355 )
1356 }
1357 }
1358 #[inline(always)]
1359 pub const fn p304pfs_ha(
1360 &self,
1361 ) -> &'static crate::common::Reg<self::P30PfsHa_SPEC, crate::common::RW> {
1362 unsafe {
1363 crate::common::Reg::<self::P30PfsHa_SPEC, crate::common::RW>::from_ptr(
1364 self._svd2pac_as_ptr().add(0xd2usize),
1365 )
1366 }
1367 }
1368
1369 #[doc = "P30%s Pin Function Control Register"]
1370 #[inline(always)]
1371 pub const fn p30pfs_by(
1372 &self,
1373 ) -> &'static crate::common::ClusterRegisterArray<
1374 crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW>,
1375 4,
1376 0x4,
1377 > {
1378 unsafe {
1379 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xc7usize))
1380 }
1381 }
1382 #[inline(always)]
1383 pub const fn p301pfs_by(
1384 &self,
1385 ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1386 unsafe {
1387 crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1388 self._svd2pac_as_ptr().add(0xc7usize),
1389 )
1390 }
1391 }
1392 #[inline(always)]
1393 pub const fn p302pfs_by(
1394 &self,
1395 ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1396 unsafe {
1397 crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1398 self._svd2pac_as_ptr().add(0xcbusize),
1399 )
1400 }
1401 }
1402 #[inline(always)]
1403 pub const fn p303pfs_by(
1404 &self,
1405 ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1406 unsafe {
1407 crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1408 self._svd2pac_as_ptr().add(0xcfusize),
1409 )
1410 }
1411 }
1412 #[inline(always)]
1413 pub const fn p304pfs_by(
1414 &self,
1415 ) -> &'static crate::common::Reg<self::P30PfsBy_SPEC, crate::common::RW> {
1416 unsafe {
1417 crate::common::Reg::<self::P30PfsBy_SPEC, crate::common::RW>::from_ptr(
1418 self._svd2pac_as_ptr().add(0xd3usize),
1419 )
1420 }
1421 }
1422
1423 #[doc = "P407 Pin Function Control Register"]
1424 #[inline(always)]
1425 pub const fn p407pfs(
1426 &self,
1427 ) -> &'static crate::common::Reg<self::P407Pfs_SPEC, crate::common::RW> {
1428 unsafe {
1429 crate::common::Reg::<self::P407Pfs_SPEC, crate::common::RW>::from_ptr(
1430 self._svd2pac_as_ptr().add(284usize),
1431 )
1432 }
1433 }
1434
1435 #[doc = "P407 Pin Function Control Register"]
1436 #[inline(always)]
1437 pub const fn p407pfs_ha(
1438 &self,
1439 ) -> &'static crate::common::Reg<self::P407PfsHa_SPEC, crate::common::RW> {
1440 unsafe {
1441 crate::common::Reg::<self::P407PfsHa_SPEC, crate::common::RW>::from_ptr(
1442 self._svd2pac_as_ptr().add(286usize),
1443 )
1444 }
1445 }
1446
1447 #[doc = "P407 Pin Function Control Register"]
1448 #[inline(always)]
1449 pub const fn p407pfs_by(
1450 &self,
1451 ) -> &'static crate::common::Reg<self::P407PfsBy_SPEC, crate::common::RW> {
1452 unsafe {
1453 crate::common::Reg::<self::P407PfsBy_SPEC, crate::common::RW>::from_ptr(
1454 self._svd2pac_as_ptr().add(287usize),
1455 )
1456 }
1457 }
1458
1459 #[doc = "P40%s Pin Function Control Register"]
1460 #[inline(always)]
1461 pub const fn p40pfs(
1462 &self,
1463 ) -> &'static crate::common::ClusterRegisterArray<
1464 crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW>,
1465 2,
1466 0x4,
1467 > {
1468 unsafe {
1469 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x120usize))
1470 }
1471 }
1472 #[inline(always)]
1473 pub const fn p408pfs(
1474 &self,
1475 ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1476 unsafe {
1477 crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1478 self._svd2pac_as_ptr().add(0x120usize),
1479 )
1480 }
1481 }
1482 #[inline(always)]
1483 pub const fn p409pfs(
1484 &self,
1485 ) -> &'static crate::common::Reg<self::P40Pfs_SPEC, crate::common::RW> {
1486 unsafe {
1487 crate::common::Reg::<self::P40Pfs_SPEC, crate::common::RW>::from_ptr(
1488 self._svd2pac_as_ptr().add(0x124usize),
1489 )
1490 }
1491 }
1492
1493 #[doc = "P40%s Pin Function Control Register"]
1494 #[inline(always)]
1495 pub const fn p40pfs_ha(
1496 &self,
1497 ) -> &'static crate::common::ClusterRegisterArray<
1498 crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW>,
1499 2,
1500 0x4,
1501 > {
1502 unsafe {
1503 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x122usize))
1504 }
1505 }
1506 #[inline(always)]
1507 pub const fn p408pfs_ha(
1508 &self,
1509 ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1510 unsafe {
1511 crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1512 self._svd2pac_as_ptr().add(0x122usize),
1513 )
1514 }
1515 }
1516 #[inline(always)]
1517 pub const fn p409pfs_ha(
1518 &self,
1519 ) -> &'static crate::common::Reg<self::P40PfsHa_SPEC, crate::common::RW> {
1520 unsafe {
1521 crate::common::Reg::<self::P40PfsHa_SPEC, crate::common::RW>::from_ptr(
1522 self._svd2pac_as_ptr().add(0x126usize),
1523 )
1524 }
1525 }
1526
1527 #[doc = "P40%s Pin Function Control Register"]
1528 #[inline(always)]
1529 pub const fn p40pfs_by(
1530 &self,
1531 ) -> &'static crate::common::ClusterRegisterArray<
1532 crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW>,
1533 2,
1534 0x4,
1535 > {
1536 unsafe {
1537 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x123usize))
1538 }
1539 }
1540 #[inline(always)]
1541 pub const fn p408pfs_by(
1542 &self,
1543 ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1544 unsafe {
1545 crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1546 self._svd2pac_as_ptr().add(0x123usize),
1547 )
1548 }
1549 }
1550 #[inline(always)]
1551 pub const fn p409pfs_by(
1552 &self,
1553 ) -> &'static crate::common::Reg<self::P40PfsBy_SPEC, crate::common::RW> {
1554 unsafe {
1555 crate::common::Reg::<self::P40PfsBy_SPEC, crate::common::RW>::from_ptr(
1556 self._svd2pac_as_ptr().add(0x127usize),
1557 )
1558 }
1559 }
1560
1561 #[doc = "P4%s Pin Function Control Register"]
1562 #[inline(always)]
1563 pub const fn p4pfs(
1564 &self,
1565 ) -> &'static crate::common::ClusterRegisterArray<
1566 crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW>,
1567 2,
1568 0x4,
1569 > {
1570 unsafe {
1571 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x128usize))
1572 }
1573 }
1574 #[inline(always)]
1575 pub const fn p410pfs(
1576 &self,
1577 ) -> &'static crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW> {
1578 unsafe {
1579 crate::common::Reg::<self::P4Pfs_SPEC, crate::common::RW>::from_ptr(
1580 self._svd2pac_as_ptr().add(0x128usize),
1581 )
1582 }
1583 }
1584 #[inline(always)]
1585 pub const fn p411pfs(
1586 &self,
1587 ) -> &'static crate::common::Reg<self::P4Pfs_SPEC, crate::common::RW> {
1588 unsafe {
1589 crate::common::Reg::<self::P4Pfs_SPEC, crate::common::RW>::from_ptr(
1590 self._svd2pac_as_ptr().add(0x12cusize),
1591 )
1592 }
1593 }
1594
1595 #[doc = "P4%s Pin Function Control Register"]
1596 #[inline(always)]
1597 pub const fn p4pfs_ha(
1598 &self,
1599 ) -> &'static crate::common::ClusterRegisterArray<
1600 crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW>,
1601 2,
1602 0x4,
1603 > {
1604 unsafe {
1605 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12ausize))
1606 }
1607 }
1608 #[inline(always)]
1609 pub const fn p410pfs_ha(
1610 &self,
1611 ) -> &'static crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW> {
1612 unsafe {
1613 crate::common::Reg::<self::P4PfsHa_SPEC, crate::common::RW>::from_ptr(
1614 self._svd2pac_as_ptr().add(0x12ausize),
1615 )
1616 }
1617 }
1618 #[inline(always)]
1619 pub const fn p411pfs_ha(
1620 &self,
1621 ) -> &'static crate::common::Reg<self::P4PfsHa_SPEC, crate::common::RW> {
1622 unsafe {
1623 crate::common::Reg::<self::P4PfsHa_SPEC, crate::common::RW>::from_ptr(
1624 self._svd2pac_as_ptr().add(0x12eusize),
1625 )
1626 }
1627 }
1628
1629 #[doc = "P4%s Pin Function Control Register"]
1630 #[inline(always)]
1631 pub const fn p4pfs_by(
1632 &self,
1633 ) -> &'static crate::common::ClusterRegisterArray<
1634 crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW>,
1635 2,
1636 0x4,
1637 > {
1638 unsafe {
1639 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x12busize))
1640 }
1641 }
1642 #[inline(always)]
1643 pub const fn p410pfs_by(
1644 &self,
1645 ) -> &'static crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW> {
1646 unsafe {
1647 crate::common::Reg::<self::P4PfsBy_SPEC, crate::common::RW>::from_ptr(
1648 self._svd2pac_as_ptr().add(0x12busize),
1649 )
1650 }
1651 }
1652 #[inline(always)]
1653 pub const fn p411pfs_by(
1654 &self,
1655 ) -> &'static crate::common::Reg<self::P4PfsBy_SPEC, crate::common::RW> {
1656 unsafe {
1657 crate::common::Reg::<self::P4PfsBy_SPEC, crate::common::RW>::from_ptr(
1658 self._svd2pac_as_ptr().add(0x12fusize),
1659 )
1660 }
1661 }
1662
1663 #[doc = "P50%s Pin Function Control Register"]
1664 #[inline(always)]
1665 pub const fn p50pfs(
1666 &self,
1667 ) -> &'static crate::common::ClusterRegisterArray<
1668 crate::common::Reg<self::P50Pfs_SPEC, crate::common::RW>,
1669 3,
1670 0x4,
1671 > {
1672 unsafe {
1673 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x140usize))
1674 }
1675 }
1676 #[inline(always)]
1677 pub const fn p500pfs(
1678 &self,
1679 ) -> &'static crate::common::Reg<self::P50Pfs_SPEC, crate::common::RW> {
1680 unsafe {
1681 crate::common::Reg::<self::P50Pfs_SPEC, crate::common::RW>::from_ptr(
1682 self._svd2pac_as_ptr().add(0x140usize),
1683 )
1684 }
1685 }
1686 #[inline(always)]
1687 pub const fn p501pfs(
1688 &self,
1689 ) -> &'static crate::common::Reg<self::P50Pfs_SPEC, crate::common::RW> {
1690 unsafe {
1691 crate::common::Reg::<self::P50Pfs_SPEC, crate::common::RW>::from_ptr(
1692 self._svd2pac_as_ptr().add(0x144usize),
1693 )
1694 }
1695 }
1696 #[inline(always)]
1697 pub const fn p502pfs(
1698 &self,
1699 ) -> &'static crate::common::Reg<self::P50Pfs_SPEC, crate::common::RW> {
1700 unsafe {
1701 crate::common::Reg::<self::P50Pfs_SPEC, crate::common::RW>::from_ptr(
1702 self._svd2pac_as_ptr().add(0x148usize),
1703 )
1704 }
1705 }
1706
1707 #[doc = "P50%s Pin Function Control Register"]
1708 #[inline(always)]
1709 pub const fn p50pfs_ha(
1710 &self,
1711 ) -> &'static crate::common::ClusterRegisterArray<
1712 crate::common::Reg<self::P50PfsHa_SPEC, crate::common::RW>,
1713 3,
1714 0x4,
1715 > {
1716 unsafe {
1717 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x142usize))
1718 }
1719 }
1720 #[inline(always)]
1721 pub const fn p500pfs_ha(
1722 &self,
1723 ) -> &'static crate::common::Reg<self::P50PfsHa_SPEC, crate::common::RW> {
1724 unsafe {
1725 crate::common::Reg::<self::P50PfsHa_SPEC, crate::common::RW>::from_ptr(
1726 self._svd2pac_as_ptr().add(0x142usize),
1727 )
1728 }
1729 }
1730 #[inline(always)]
1731 pub const fn p501pfs_ha(
1732 &self,
1733 ) -> &'static crate::common::Reg<self::P50PfsHa_SPEC, crate::common::RW> {
1734 unsafe {
1735 crate::common::Reg::<self::P50PfsHa_SPEC, crate::common::RW>::from_ptr(
1736 self._svd2pac_as_ptr().add(0x146usize),
1737 )
1738 }
1739 }
1740 #[inline(always)]
1741 pub const fn p502pfs_ha(
1742 &self,
1743 ) -> &'static crate::common::Reg<self::P50PfsHa_SPEC, crate::common::RW> {
1744 unsafe {
1745 crate::common::Reg::<self::P50PfsHa_SPEC, crate::common::RW>::from_ptr(
1746 self._svd2pac_as_ptr().add(0x14ausize),
1747 )
1748 }
1749 }
1750
1751 #[doc = "P50%s Pin Function Control Register"]
1752 #[inline(always)]
1753 pub const fn p50pfs_by(
1754 &self,
1755 ) -> &'static crate::common::ClusterRegisterArray<
1756 crate::common::Reg<self::P50PfsBy_SPEC, crate::common::RW>,
1757 3,
1758 0x4,
1759 > {
1760 unsafe {
1761 crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x143usize))
1762 }
1763 }
1764 #[inline(always)]
1765 pub const fn p500pfs_by(
1766 &self,
1767 ) -> &'static crate::common::Reg<self::P50PfsBy_SPEC, crate::common::RW> {
1768 unsafe {
1769 crate::common::Reg::<self::P50PfsBy_SPEC, crate::common::RW>::from_ptr(
1770 self._svd2pac_as_ptr().add(0x143usize),
1771 )
1772 }
1773 }
1774 #[inline(always)]
1775 pub const fn p501pfs_by(
1776 &self,
1777 ) -> &'static crate::common::Reg<self::P50PfsBy_SPEC, crate::common::RW> {
1778 unsafe {
1779 crate::common::Reg::<self::P50PfsBy_SPEC, crate::common::RW>::from_ptr(
1780 self._svd2pac_as_ptr().add(0x147usize),
1781 )
1782 }
1783 }
1784 #[inline(always)]
1785 pub const fn p502pfs_by(
1786 &self,
1787 ) -> &'static crate::common::Reg<self::P50PfsBy_SPEC, crate::common::RW> {
1788 unsafe {
1789 crate::common::Reg::<self::P50PfsBy_SPEC, crate::common::RW>::from_ptr(
1790 self._svd2pac_as_ptr().add(0x14busize),
1791 )
1792 }
1793 }
1794
1795 #[doc = "P914 Pin Function Control Register"]
1796 #[inline(always)]
1797 pub const fn p914pfs(
1798 &self,
1799 ) -> &'static crate::common::Reg<self::P914Pfs_SPEC, crate::common::RW> {
1800 unsafe {
1801 crate::common::Reg::<self::P914Pfs_SPEC, crate::common::RW>::from_ptr(
1802 self._svd2pac_as_ptr().add(632usize),
1803 )
1804 }
1805 }
1806
1807 #[doc = "P914 Pin Function Control Register"]
1808 #[inline(always)]
1809 pub const fn p914pfs_ha(
1810 &self,
1811 ) -> &'static crate::common::Reg<self::P914PfsHa_SPEC, crate::common::RW> {
1812 unsafe {
1813 crate::common::Reg::<self::P914PfsHa_SPEC, crate::common::RW>::from_ptr(
1814 self._svd2pac_as_ptr().add(634usize),
1815 )
1816 }
1817 }
1818
1819 #[doc = "P914 Pin Function Control Register"]
1820 #[inline(always)]
1821 pub const fn p914pfs_by(
1822 &self,
1823 ) -> &'static crate::common::Reg<self::P914PfsBy_SPEC, crate::common::RW> {
1824 unsafe {
1825 crate::common::Reg::<self::P914PfsBy_SPEC, crate::common::RW>::from_ptr(
1826 self._svd2pac_as_ptr().add(635usize),
1827 )
1828 }
1829 }
1830
1831 #[doc = "P915 Pin Function Control Register"]
1832 #[inline(always)]
1833 pub const fn p915pfs(
1834 &self,
1835 ) -> &'static crate::common::Reg<self::P915Pfs_SPEC, crate::common::RW> {
1836 unsafe {
1837 crate::common::Reg::<self::P915Pfs_SPEC, crate::common::RW>::from_ptr(
1838 self._svd2pac_as_ptr().add(636usize),
1839 )
1840 }
1841 }
1842
1843 #[doc = "P915 Pin Function Control Register"]
1844 #[inline(always)]
1845 pub const fn p915pfs_ha(
1846 &self,
1847 ) -> &'static crate::common::Reg<self::P915PfsHa_SPEC, crate::common::RW> {
1848 unsafe {
1849 crate::common::Reg::<self::P915PfsHa_SPEC, crate::common::RW>::from_ptr(
1850 self._svd2pac_as_ptr().add(638usize),
1851 )
1852 }
1853 }
1854
1855 #[doc = "P915 Pin Function Control Register"]
1856 #[inline(always)]
1857 pub const fn p915pfs_by(
1858 &self,
1859 ) -> &'static crate::common::Reg<self::P915PfsBy_SPEC, crate::common::RW> {
1860 unsafe {
1861 crate::common::Reg::<self::P915PfsBy_SPEC, crate::common::RW>::from_ptr(
1862 self._svd2pac_as_ptr().add(639usize),
1863 )
1864 }
1865 }
1866}
1867#[doc(hidden)]
1868#[derive(Copy, Clone, Eq, PartialEq)]
1869pub struct P000Pfs_SPEC;
1870impl crate::sealed::RegSpec for P000Pfs_SPEC {
1871 type DataType = u32;
1872}
1873
1874#[doc = "P000 Pin Function Control Register"]
1875pub type P000Pfs = crate::RegValueT<P000Pfs_SPEC>;
1876
1877impl P000Pfs {
1878 #[doc = "Port Function Select\nThese bits select the peripheral function. For individual pin functions, see the MPC table"]
1879 #[inline(always)]
1880 pub fn psel(
1881 self,
1882 ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P000Pfs_SPEC, crate::common::RW> {
1883 crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P000Pfs_SPEC,crate::common::RW>::from_register(self,0)
1884 }
1885
1886 #[doc = "Port Mode Control"]
1887 #[inline(always)]
1888 pub fn pmr(
1889 self,
1890 ) -> crate::common::RegisterField<
1891 16,
1892 0x1,
1893 1,
1894 0,
1895 p000pfs::Pmr,
1896 p000pfs::Pmr,
1897 P000Pfs_SPEC,
1898 crate::common::RW,
1899 > {
1900 crate::common::RegisterField::<
1901 16,
1902 0x1,
1903 1,
1904 0,
1905 p000pfs::Pmr,
1906 p000pfs::Pmr,
1907 P000Pfs_SPEC,
1908 crate::common::RW,
1909 >::from_register(self, 0)
1910 }
1911
1912 #[doc = "Analog Input enable"]
1913 #[inline(always)]
1914 pub fn asel(
1915 self,
1916 ) -> crate::common::RegisterField<
1917 15,
1918 0x1,
1919 1,
1920 0,
1921 p000pfs::Asel,
1922 p000pfs::Asel,
1923 P000Pfs_SPEC,
1924 crate::common::RW,
1925 > {
1926 crate::common::RegisterField::<
1927 15,
1928 0x1,
1929 1,
1930 0,
1931 p000pfs::Asel,
1932 p000pfs::Asel,
1933 P000Pfs_SPEC,
1934 crate::common::RW,
1935 >::from_register(self, 0)
1936 }
1937
1938 #[doc = "IRQ input enable"]
1939 #[inline(always)]
1940 pub fn isel(
1941 self,
1942 ) -> crate::common::RegisterField<
1943 14,
1944 0x1,
1945 1,
1946 0,
1947 p000pfs::Isel,
1948 p000pfs::Isel,
1949 P000Pfs_SPEC,
1950 crate::common::RW,
1951 > {
1952 crate::common::RegisterField::<
1953 14,
1954 0x1,
1955 1,
1956 0,
1957 p000pfs::Isel,
1958 p000pfs::Isel,
1959 P000Pfs_SPEC,
1960 crate::common::RW,
1961 >::from_register(self, 0)
1962 }
1963
1964 #[doc = "Drive Strength Control Register"]
1965 #[inline(always)]
1966 pub fn dscr(
1967 self,
1968 ) -> crate::common::RegisterField<
1969 10,
1970 0x1,
1971 1,
1972 0,
1973 p000pfs::Dscr,
1974 p000pfs::Dscr,
1975 P000Pfs_SPEC,
1976 crate::common::RW,
1977 > {
1978 crate::common::RegisterField::<
1979 10,
1980 0x1,
1981 1,
1982 0,
1983 p000pfs::Dscr,
1984 p000pfs::Dscr,
1985 P000Pfs_SPEC,
1986 crate::common::RW,
1987 >::from_register(self, 0)
1988 }
1989
1990 #[doc = "N-Channel Open Drain Control"]
1991 #[inline(always)]
1992 pub fn ncodr(
1993 self,
1994 ) -> crate::common::RegisterField<
1995 6,
1996 0x1,
1997 1,
1998 0,
1999 p000pfs::Ncodr,
2000 p000pfs::Ncodr,
2001 P000Pfs_SPEC,
2002 crate::common::RW,
2003 > {
2004 crate::common::RegisterField::<
2005 6,
2006 0x1,
2007 1,
2008 0,
2009 p000pfs::Ncodr,
2010 p000pfs::Ncodr,
2011 P000Pfs_SPEC,
2012 crate::common::RW,
2013 >::from_register(self, 0)
2014 }
2015
2016 #[doc = "Pull-up Control"]
2017 #[inline(always)]
2018 pub fn pcr(
2019 self,
2020 ) -> crate::common::RegisterField<
2021 4,
2022 0x1,
2023 1,
2024 0,
2025 p000pfs::Pcr,
2026 p000pfs::Pcr,
2027 P000Pfs_SPEC,
2028 crate::common::RW,
2029 > {
2030 crate::common::RegisterField::<
2031 4,
2032 0x1,
2033 1,
2034 0,
2035 p000pfs::Pcr,
2036 p000pfs::Pcr,
2037 P000Pfs_SPEC,
2038 crate::common::RW,
2039 >::from_register(self, 0)
2040 }
2041
2042 #[doc = "This bit is read as 0. The write value should be 0."]
2043 #[inline(always)]
2044 pub fn reserved(
2045 self,
2046 ) -> crate::common::RegisterFieldBool<3, 1, 0, P000Pfs_SPEC, crate::common::RW> {
2047 crate::common::RegisterFieldBool::<3, 1, 0, P000Pfs_SPEC, crate::common::RW>::from_register(
2048 self, 0,
2049 )
2050 }
2051
2052 #[doc = "Port Direction"]
2053 #[inline(always)]
2054 pub fn pdr(
2055 self,
2056 ) -> crate::common::RegisterField<
2057 2,
2058 0x1,
2059 1,
2060 0,
2061 p000pfs::Pdr,
2062 p000pfs::Pdr,
2063 P000Pfs_SPEC,
2064 crate::common::RW,
2065 > {
2066 crate::common::RegisterField::<
2067 2,
2068 0x1,
2069 1,
2070 0,
2071 p000pfs::Pdr,
2072 p000pfs::Pdr,
2073 P000Pfs_SPEC,
2074 crate::common::RW,
2075 >::from_register(self, 0)
2076 }
2077
2078 #[doc = "Port Input Data"]
2079 #[inline(always)]
2080 pub fn pidr(
2081 self,
2082 ) -> crate::common::RegisterField<
2083 1,
2084 0x1,
2085 1,
2086 0,
2087 p000pfs::Pidr,
2088 p000pfs::Pidr,
2089 P000Pfs_SPEC,
2090 crate::common::R,
2091 > {
2092 crate::common::RegisterField::<
2093 1,
2094 0x1,
2095 1,
2096 0,
2097 p000pfs::Pidr,
2098 p000pfs::Pidr,
2099 P000Pfs_SPEC,
2100 crate::common::R,
2101 >::from_register(self, 0)
2102 }
2103
2104 #[doc = "Port Output Data"]
2105 #[inline(always)]
2106 pub fn podr(
2107 self,
2108 ) -> crate::common::RegisterField<
2109 0,
2110 0x1,
2111 1,
2112 0,
2113 p000pfs::Podr,
2114 p000pfs::Podr,
2115 P000Pfs_SPEC,
2116 crate::common::RW,
2117 > {
2118 crate::common::RegisterField::<
2119 0,
2120 0x1,
2121 1,
2122 0,
2123 p000pfs::Podr,
2124 p000pfs::Podr,
2125 P000Pfs_SPEC,
2126 crate::common::RW,
2127 >::from_register(self, 0)
2128 }
2129}
2130impl ::core::default::Default for P000Pfs {
2131 #[inline(always)]
2132 fn default() -> P000Pfs {
2133 <crate::RegValueT<P000Pfs_SPEC> as RegisterValue<_>>::new(0)
2134 }
2135}
2136pub mod p000pfs {
2137
2138 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2139 pub struct Pmr_SPEC;
2140 pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
2141 impl Pmr {
2142 #[doc = "Uses the pin as a general I/O pin."]
2143 pub const _0: Self = Self::new(0);
2144
2145 #[doc = "Uses the pin as an I/O port for peripheral functions."]
2146 pub const _1: Self = Self::new(1);
2147 }
2148 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2149 pub struct Asel_SPEC;
2150 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2151 impl Asel {
2152 #[doc = "Used other than as analog pin"]
2153 pub const _0: Self = Self::new(0);
2154
2155 #[doc = "Used as analog pin"]
2156 pub const _1: Self = Self::new(1);
2157 }
2158 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2159 pub struct Isel_SPEC;
2160 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2161 impl Isel {
2162 #[doc = "Not used as IRQn input pin"]
2163 pub const _0: Self = Self::new(0);
2164
2165 #[doc = "Used as IRQn input pin"]
2166 pub const _1: Self = Self::new(1);
2167 }
2168 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2169 pub struct Dscr_SPEC;
2170 pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
2171 impl Dscr {
2172 #[doc = "Low drive"]
2173 pub const _0: Self = Self::new(0);
2174
2175 #[doc = "High drive"]
2176 pub const _1: Self = Self::new(1);
2177 }
2178 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2179 pub struct Ncodr_SPEC;
2180 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2181 impl Ncodr {
2182 #[doc = "CMOS output"]
2183 pub const _0: Self = Self::new(0);
2184
2185 #[doc = "NMOS open-drain output"]
2186 pub const _1: Self = Self::new(1);
2187 }
2188 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2189 pub struct Pcr_SPEC;
2190 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2191 impl Pcr {
2192 #[doc = "Disables an input pull-up."]
2193 pub const _0: Self = Self::new(0);
2194
2195 #[doc = "Enables an input pull-up."]
2196 pub const _1: Self = Self::new(1);
2197 }
2198 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2199 pub struct Pdr_SPEC;
2200 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2201 impl Pdr {
2202 #[doc = "Input (Functions as an input pin.)"]
2203 pub const _0: Self = Self::new(0);
2204
2205 #[doc = "Output (Functions as an output pin.)"]
2206 pub const _1: Self = Self::new(1);
2207 }
2208 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2209 pub struct Pidr_SPEC;
2210 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2211 impl Pidr {
2212 #[doc = "Low input"]
2213 pub const _0: Self = Self::new(0);
2214
2215 #[doc = "High input"]
2216 pub const _1: Self = Self::new(1);
2217 }
2218 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2219 pub struct Podr_SPEC;
2220 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2221 impl Podr {
2222 #[doc = "Low output"]
2223 pub const _0: Self = Self::new(0);
2224
2225 #[doc = "High output"]
2226 pub const _1: Self = Self::new(1);
2227 }
2228}
2229#[doc(hidden)]
2230#[derive(Copy, Clone, Eq, PartialEq)]
2231pub struct P000PfsHa_SPEC;
2232impl crate::sealed::RegSpec for P000PfsHa_SPEC {
2233 type DataType = u16;
2234}
2235
2236#[doc = "P000 Pin Function Control Register"]
2237pub type P000PfsHa = crate::RegValueT<P000PfsHa_SPEC>;
2238
2239impl P000PfsHa {
2240 #[doc = "Analog Input enable"]
2241 #[inline(always)]
2242 pub fn asel(
2243 self,
2244 ) -> crate::common::RegisterField<
2245 15,
2246 0x1,
2247 1,
2248 0,
2249 p000pfs_ha::Asel,
2250 p000pfs_ha::Asel,
2251 P000PfsHa_SPEC,
2252 crate::common::RW,
2253 > {
2254 crate::common::RegisterField::<
2255 15,
2256 0x1,
2257 1,
2258 0,
2259 p000pfs_ha::Asel,
2260 p000pfs_ha::Asel,
2261 P000PfsHa_SPEC,
2262 crate::common::RW,
2263 >::from_register(self, 0)
2264 }
2265
2266 #[doc = "IRQ input enable"]
2267 #[inline(always)]
2268 pub fn isel(
2269 self,
2270 ) -> crate::common::RegisterField<
2271 14,
2272 0x1,
2273 1,
2274 0,
2275 p000pfs_ha::Isel,
2276 p000pfs_ha::Isel,
2277 P000PfsHa_SPEC,
2278 crate::common::RW,
2279 > {
2280 crate::common::RegisterField::<
2281 14,
2282 0x1,
2283 1,
2284 0,
2285 p000pfs_ha::Isel,
2286 p000pfs_ha::Isel,
2287 P000PfsHa_SPEC,
2288 crate::common::RW,
2289 >::from_register(self, 0)
2290 }
2291
2292 #[doc = "Drive Strength Control Register"]
2293 #[inline(always)]
2294 pub fn dscr(
2295 self,
2296 ) -> crate::common::RegisterField<
2297 10,
2298 0x1,
2299 1,
2300 0,
2301 p000pfs_ha::Dscr,
2302 p000pfs_ha::Dscr,
2303 P000PfsHa_SPEC,
2304 crate::common::RW,
2305 > {
2306 crate::common::RegisterField::<
2307 10,
2308 0x1,
2309 1,
2310 0,
2311 p000pfs_ha::Dscr,
2312 p000pfs_ha::Dscr,
2313 P000PfsHa_SPEC,
2314 crate::common::RW,
2315 >::from_register(self, 0)
2316 }
2317
2318 #[doc = "N-Channel Open Drain Control"]
2319 #[inline(always)]
2320 pub fn ncodr(
2321 self,
2322 ) -> crate::common::RegisterField<
2323 6,
2324 0x1,
2325 1,
2326 0,
2327 p000pfs_ha::Ncodr,
2328 p000pfs_ha::Ncodr,
2329 P000PfsHa_SPEC,
2330 crate::common::RW,
2331 > {
2332 crate::common::RegisterField::<
2333 6,
2334 0x1,
2335 1,
2336 0,
2337 p000pfs_ha::Ncodr,
2338 p000pfs_ha::Ncodr,
2339 P000PfsHa_SPEC,
2340 crate::common::RW,
2341 >::from_register(self, 0)
2342 }
2343
2344 #[doc = "Pull-up Control"]
2345 #[inline(always)]
2346 pub fn pcr(
2347 self,
2348 ) -> crate::common::RegisterField<
2349 4,
2350 0x1,
2351 1,
2352 0,
2353 p000pfs_ha::Pcr,
2354 p000pfs_ha::Pcr,
2355 P000PfsHa_SPEC,
2356 crate::common::RW,
2357 > {
2358 crate::common::RegisterField::<
2359 4,
2360 0x1,
2361 1,
2362 0,
2363 p000pfs_ha::Pcr,
2364 p000pfs_ha::Pcr,
2365 P000PfsHa_SPEC,
2366 crate::common::RW,
2367 >::from_register(self, 0)
2368 }
2369
2370 #[doc = "This bit is read as 0. The write value should be 0."]
2371 #[inline(always)]
2372 pub fn reserved(
2373 self,
2374 ) -> crate::common::RegisterFieldBool<3, 1, 0, P000PfsHa_SPEC, crate::common::RW> {
2375 crate::common::RegisterFieldBool::<3,1,0,P000PfsHa_SPEC,crate::common::RW>::from_register(self,0)
2376 }
2377
2378 #[doc = "Port Direction"]
2379 #[inline(always)]
2380 pub fn pdr(
2381 self,
2382 ) -> crate::common::RegisterField<
2383 2,
2384 0x1,
2385 1,
2386 0,
2387 p000pfs_ha::Pdr,
2388 p000pfs_ha::Pdr,
2389 P000PfsHa_SPEC,
2390 crate::common::RW,
2391 > {
2392 crate::common::RegisterField::<
2393 2,
2394 0x1,
2395 1,
2396 0,
2397 p000pfs_ha::Pdr,
2398 p000pfs_ha::Pdr,
2399 P000PfsHa_SPEC,
2400 crate::common::RW,
2401 >::from_register(self, 0)
2402 }
2403
2404 #[doc = "Port Input Data"]
2405 #[inline(always)]
2406 pub fn pidr(
2407 self,
2408 ) -> crate::common::RegisterField<
2409 1,
2410 0x1,
2411 1,
2412 0,
2413 p000pfs_ha::Pidr,
2414 p000pfs_ha::Pidr,
2415 P000PfsHa_SPEC,
2416 crate::common::R,
2417 > {
2418 crate::common::RegisterField::<
2419 1,
2420 0x1,
2421 1,
2422 0,
2423 p000pfs_ha::Pidr,
2424 p000pfs_ha::Pidr,
2425 P000PfsHa_SPEC,
2426 crate::common::R,
2427 >::from_register(self, 0)
2428 }
2429
2430 #[doc = "Port Output Data"]
2431 #[inline(always)]
2432 pub fn podr(
2433 self,
2434 ) -> crate::common::RegisterField<
2435 0,
2436 0x1,
2437 1,
2438 0,
2439 p000pfs_ha::Podr,
2440 p000pfs_ha::Podr,
2441 P000PfsHa_SPEC,
2442 crate::common::RW,
2443 > {
2444 crate::common::RegisterField::<
2445 0,
2446 0x1,
2447 1,
2448 0,
2449 p000pfs_ha::Podr,
2450 p000pfs_ha::Podr,
2451 P000PfsHa_SPEC,
2452 crate::common::RW,
2453 >::from_register(self, 0)
2454 }
2455}
2456impl ::core::default::Default for P000PfsHa {
2457 #[inline(always)]
2458 fn default() -> P000PfsHa {
2459 <crate::RegValueT<P000PfsHa_SPEC> as RegisterValue<_>>::new(0)
2460 }
2461}
2462pub mod p000pfs_ha {
2463
2464 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2465 pub struct Asel_SPEC;
2466 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
2467 impl Asel {
2468 #[doc = "Used other than as analog pin"]
2469 pub const _0: Self = Self::new(0);
2470
2471 #[doc = "Used as analog pin"]
2472 pub const _1: Self = Self::new(1);
2473 }
2474 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2475 pub struct Isel_SPEC;
2476 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
2477 impl Isel {
2478 #[doc = "Not used as IRQn input pin"]
2479 pub const _0: Self = Self::new(0);
2480
2481 #[doc = "Used as IRQn input pin"]
2482 pub const _1: Self = Self::new(1);
2483 }
2484 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2485 pub struct Dscr_SPEC;
2486 pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
2487 impl Dscr {
2488 #[doc = "Low drive"]
2489 pub const _0: Self = Self::new(0);
2490
2491 #[doc = "High drive"]
2492 pub const _1: Self = Self::new(1);
2493 }
2494 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2495 pub struct Ncodr_SPEC;
2496 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2497 impl Ncodr {
2498 #[doc = "CMOS output"]
2499 pub const _0: Self = Self::new(0);
2500
2501 #[doc = "NMOS open-drain output"]
2502 pub const _1: Self = Self::new(1);
2503 }
2504 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2505 pub struct Pcr_SPEC;
2506 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2507 impl Pcr {
2508 #[doc = "Disables an input pull-up."]
2509 pub const _0: Self = Self::new(0);
2510
2511 #[doc = "Enables an input pull-up."]
2512 pub const _1: Self = Self::new(1);
2513 }
2514 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2515 pub struct Pdr_SPEC;
2516 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2517 impl Pdr {
2518 #[doc = "Input (Functions as an input pin.)"]
2519 pub const _0: Self = Self::new(0);
2520
2521 #[doc = "Output (Functions as an output pin.)"]
2522 pub const _1: Self = Self::new(1);
2523 }
2524 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2525 pub struct Pidr_SPEC;
2526 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2527 impl Pidr {
2528 #[doc = "Low input"]
2529 pub const _0: Self = Self::new(0);
2530
2531 #[doc = "High input"]
2532 pub const _1: Self = Self::new(1);
2533 }
2534 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2535 pub struct Podr_SPEC;
2536 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2537 impl Podr {
2538 #[doc = "Low output"]
2539 pub const _0: Self = Self::new(0);
2540
2541 #[doc = "High output"]
2542 pub const _1: Self = Self::new(1);
2543 }
2544}
2545#[doc(hidden)]
2546#[derive(Copy, Clone, Eq, PartialEq)]
2547pub struct P000PfsBy_SPEC;
2548impl crate::sealed::RegSpec for P000PfsBy_SPEC {
2549 type DataType = u8;
2550}
2551
2552#[doc = "P000 Pin Function Control Register"]
2553pub type P000PfsBy = crate::RegValueT<P000PfsBy_SPEC>;
2554
2555impl P000PfsBy {
2556 #[doc = "N-Channel Open Drain Control"]
2557 #[inline(always)]
2558 pub fn ncodr(
2559 self,
2560 ) -> crate::common::RegisterField<
2561 6,
2562 0x1,
2563 1,
2564 0,
2565 p000pfs_by::Ncodr,
2566 p000pfs_by::Ncodr,
2567 P000PfsBy_SPEC,
2568 crate::common::RW,
2569 > {
2570 crate::common::RegisterField::<
2571 6,
2572 0x1,
2573 1,
2574 0,
2575 p000pfs_by::Ncodr,
2576 p000pfs_by::Ncodr,
2577 P000PfsBy_SPEC,
2578 crate::common::RW,
2579 >::from_register(self, 0)
2580 }
2581
2582 #[doc = "Pull-up Control"]
2583 #[inline(always)]
2584 pub fn pcr(
2585 self,
2586 ) -> crate::common::RegisterField<
2587 4,
2588 0x1,
2589 1,
2590 0,
2591 p000pfs_by::Pcr,
2592 p000pfs_by::Pcr,
2593 P000PfsBy_SPEC,
2594 crate::common::RW,
2595 > {
2596 crate::common::RegisterField::<
2597 4,
2598 0x1,
2599 1,
2600 0,
2601 p000pfs_by::Pcr,
2602 p000pfs_by::Pcr,
2603 P000PfsBy_SPEC,
2604 crate::common::RW,
2605 >::from_register(self, 0)
2606 }
2607
2608 #[doc = "This bit is read as 0. The write value should be 0."]
2609 #[inline(always)]
2610 pub fn reserved(
2611 self,
2612 ) -> crate::common::RegisterFieldBool<3, 1, 0, P000PfsBy_SPEC, crate::common::RW> {
2613 crate::common::RegisterFieldBool::<3,1,0,P000PfsBy_SPEC,crate::common::RW>::from_register(self,0)
2614 }
2615
2616 #[doc = "Port Direction"]
2617 #[inline(always)]
2618 pub fn pdr(
2619 self,
2620 ) -> crate::common::RegisterField<
2621 2,
2622 0x1,
2623 1,
2624 0,
2625 p000pfs_by::Pdr,
2626 p000pfs_by::Pdr,
2627 P000PfsBy_SPEC,
2628 crate::common::RW,
2629 > {
2630 crate::common::RegisterField::<
2631 2,
2632 0x1,
2633 1,
2634 0,
2635 p000pfs_by::Pdr,
2636 p000pfs_by::Pdr,
2637 P000PfsBy_SPEC,
2638 crate::common::RW,
2639 >::from_register(self, 0)
2640 }
2641
2642 #[doc = "Port Input Data"]
2643 #[inline(always)]
2644 pub fn pidr(
2645 self,
2646 ) -> crate::common::RegisterField<
2647 1,
2648 0x1,
2649 1,
2650 0,
2651 p000pfs_by::Pidr,
2652 p000pfs_by::Pidr,
2653 P000PfsBy_SPEC,
2654 crate::common::R,
2655 > {
2656 crate::common::RegisterField::<
2657 1,
2658 0x1,
2659 1,
2660 0,
2661 p000pfs_by::Pidr,
2662 p000pfs_by::Pidr,
2663 P000PfsBy_SPEC,
2664 crate::common::R,
2665 >::from_register(self, 0)
2666 }
2667
2668 #[doc = "Port Output Data"]
2669 #[inline(always)]
2670 pub fn podr(
2671 self,
2672 ) -> crate::common::RegisterField<
2673 0,
2674 0x1,
2675 1,
2676 0,
2677 p000pfs_by::Podr,
2678 p000pfs_by::Podr,
2679 P000PfsBy_SPEC,
2680 crate::common::RW,
2681 > {
2682 crate::common::RegisterField::<
2683 0,
2684 0x1,
2685 1,
2686 0,
2687 p000pfs_by::Podr,
2688 p000pfs_by::Podr,
2689 P000PfsBy_SPEC,
2690 crate::common::RW,
2691 >::from_register(self, 0)
2692 }
2693}
2694impl ::core::default::Default for P000PfsBy {
2695 #[inline(always)]
2696 fn default() -> P000PfsBy {
2697 <crate::RegValueT<P000PfsBy_SPEC> as RegisterValue<_>>::new(0)
2698 }
2699}
2700pub mod p000pfs_by {
2701
2702 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2703 pub struct Ncodr_SPEC;
2704 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
2705 impl Ncodr {
2706 #[doc = "CMOS output"]
2707 pub const _0: Self = Self::new(0);
2708
2709 #[doc = "NMOS open-drain output"]
2710 pub const _1: Self = Self::new(1);
2711 }
2712 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2713 pub struct Pcr_SPEC;
2714 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
2715 impl Pcr {
2716 #[doc = "Disables an input pull-up."]
2717 pub const _0: Self = Self::new(0);
2718
2719 #[doc = "Enables an input pull-up."]
2720 pub const _1: Self = Self::new(1);
2721 }
2722 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2723 pub struct Pdr_SPEC;
2724 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
2725 impl Pdr {
2726 #[doc = "Input (Functions as an input pin.)"]
2727 pub const _0: Self = Self::new(0);
2728
2729 #[doc = "Output (Functions as an output pin.)"]
2730 pub const _1: Self = Self::new(1);
2731 }
2732 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2733 pub struct Pidr_SPEC;
2734 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
2735 impl Pidr {
2736 #[doc = "Low input"]
2737 pub const _0: Self = Self::new(0);
2738
2739 #[doc = "High input"]
2740 pub const _1: Self = Self::new(1);
2741 }
2742 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2743 pub struct Podr_SPEC;
2744 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
2745 impl Podr {
2746 #[doc = "Low output"]
2747 pub const _0: Self = Self::new(0);
2748
2749 #[doc = "High output"]
2750 pub const _1: Self = Self::new(1);
2751 }
2752}
2753#[doc(hidden)]
2754#[derive(Copy, Clone, Eq, PartialEq)]
2755pub struct P00Pfs_SPEC;
2756impl crate::sealed::RegSpec for P00Pfs_SPEC {
2757 type DataType = u32;
2758}
2759
2760#[doc = "P00%s Pin Function Control Register"]
2761pub type P00Pfs = crate::RegValueT<P00Pfs_SPEC>;
2762
2763impl NoBitfieldReg<P00Pfs_SPEC> for P00Pfs {}
2764impl ::core::default::Default for P00Pfs {
2765 #[inline(always)]
2766 fn default() -> P00Pfs {
2767 <crate::RegValueT<P00Pfs_SPEC> as RegisterValue<_>>::new(0)
2768 }
2769}
2770
2771#[doc(hidden)]
2772#[derive(Copy, Clone, Eq, PartialEq)]
2773pub struct P00PfsHa_SPEC;
2774impl crate::sealed::RegSpec for P00PfsHa_SPEC {
2775 type DataType = u16;
2776}
2777
2778#[doc = "P00%s Pin Function Control Register"]
2779pub type P00PfsHa = crate::RegValueT<P00PfsHa_SPEC>;
2780
2781impl NoBitfieldReg<P00PfsHa_SPEC> for P00PfsHa {}
2782impl ::core::default::Default for P00PfsHa {
2783 #[inline(always)]
2784 fn default() -> P00PfsHa {
2785 <crate::RegValueT<P00PfsHa_SPEC> as RegisterValue<_>>::new(0)
2786 }
2787}
2788
2789#[doc(hidden)]
2790#[derive(Copy, Clone, Eq, PartialEq)]
2791pub struct P00PfsBy_SPEC;
2792impl crate::sealed::RegSpec for P00PfsBy_SPEC {
2793 type DataType = u8;
2794}
2795
2796#[doc = "P00%s Pin Function Control Register"]
2797pub type P00PfsBy = crate::RegValueT<P00PfsBy_SPEC>;
2798
2799impl NoBitfieldReg<P00PfsBy_SPEC> for P00PfsBy {}
2800impl ::core::default::Default for P00PfsBy {
2801 #[inline(always)]
2802 fn default() -> P00PfsBy {
2803 <crate::RegValueT<P00PfsBy_SPEC> as RegisterValue<_>>::new(0)
2804 }
2805}
2806
2807#[doc(hidden)]
2808#[derive(Copy, Clone, Eq, PartialEq)]
2809pub struct P0Pfs_SPEC;
2810impl crate::sealed::RegSpec for P0Pfs_SPEC {
2811 type DataType = u32;
2812}
2813
2814#[doc = "P0%s Pin Function Control Register"]
2815pub type P0Pfs = crate::RegValueT<P0Pfs_SPEC>;
2816
2817impl NoBitfieldReg<P0Pfs_SPEC> for P0Pfs {}
2818impl ::core::default::Default for P0Pfs {
2819 #[inline(always)]
2820 fn default() -> P0Pfs {
2821 <crate::RegValueT<P0Pfs_SPEC> as RegisterValue<_>>::new(0)
2822 }
2823}
2824
2825#[doc(hidden)]
2826#[derive(Copy, Clone, Eq, PartialEq)]
2827pub struct P0PfsHa_SPEC;
2828impl crate::sealed::RegSpec for P0PfsHa_SPEC {
2829 type DataType = u16;
2830}
2831
2832#[doc = "P0%s Pin Function Control Register"]
2833pub type P0PfsHa = crate::RegValueT<P0PfsHa_SPEC>;
2834
2835impl NoBitfieldReg<P0PfsHa_SPEC> for P0PfsHa {}
2836impl ::core::default::Default for P0PfsHa {
2837 #[inline(always)]
2838 fn default() -> P0PfsHa {
2839 <crate::RegValueT<P0PfsHa_SPEC> as RegisterValue<_>>::new(0)
2840 }
2841}
2842
2843#[doc(hidden)]
2844#[derive(Copy, Clone, Eq, PartialEq)]
2845pub struct P0PfsBy_SPEC;
2846impl crate::sealed::RegSpec for P0PfsBy_SPEC {
2847 type DataType = u8;
2848}
2849
2850#[doc = "P0%s Pin Function Control Register"]
2851pub type P0PfsBy = crate::RegValueT<P0PfsBy_SPEC>;
2852
2853impl NoBitfieldReg<P0PfsBy_SPEC> for P0PfsBy {}
2854impl ::core::default::Default for P0PfsBy {
2855 #[inline(always)]
2856 fn default() -> P0PfsBy {
2857 <crate::RegValueT<P0PfsBy_SPEC> as RegisterValue<_>>::new(0)
2858 }
2859}
2860
2861#[doc(hidden)]
2862#[derive(Copy, Clone, Eq, PartialEq)]
2863pub struct P100Pfs_SPEC;
2864impl crate::sealed::RegSpec for P100Pfs_SPEC {
2865 type DataType = u32;
2866}
2867
2868#[doc = "P100 Pin Function Control Register"]
2869pub type P100Pfs = crate::RegValueT<P100Pfs_SPEC>;
2870
2871impl P100Pfs {
2872 #[doc = "Port Function Select\nThese bits select the peripheral function. For individual pin functions, see the MPC table"]
2873 #[inline(always)]
2874 pub fn psel(
2875 self,
2876 ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P100Pfs_SPEC, crate::common::RW> {
2877 crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P100Pfs_SPEC,crate::common::RW>::from_register(self,0)
2878 }
2879
2880 #[doc = "Port Mode Control"]
2881 #[inline(always)]
2882 pub fn pmr(
2883 self,
2884 ) -> crate::common::RegisterField<
2885 16,
2886 0x1,
2887 1,
2888 0,
2889 p100pfs::Pmr,
2890 p100pfs::Pmr,
2891 P100Pfs_SPEC,
2892 crate::common::RW,
2893 > {
2894 crate::common::RegisterField::<
2895 16,
2896 0x1,
2897 1,
2898 0,
2899 p100pfs::Pmr,
2900 p100pfs::Pmr,
2901 P100Pfs_SPEC,
2902 crate::common::RW,
2903 >::from_register(self, 0)
2904 }
2905
2906 #[doc = "Analog Input enable"]
2907 #[inline(always)]
2908 pub fn asel(
2909 self,
2910 ) -> crate::common::RegisterField<
2911 15,
2912 0x1,
2913 1,
2914 0,
2915 p100pfs::Asel,
2916 p100pfs::Asel,
2917 P100Pfs_SPEC,
2918 crate::common::RW,
2919 > {
2920 crate::common::RegisterField::<
2921 15,
2922 0x1,
2923 1,
2924 0,
2925 p100pfs::Asel,
2926 p100pfs::Asel,
2927 P100Pfs_SPEC,
2928 crate::common::RW,
2929 >::from_register(self, 0)
2930 }
2931
2932 #[doc = "IRQ input enable"]
2933 #[inline(always)]
2934 pub fn isel(
2935 self,
2936 ) -> crate::common::RegisterField<
2937 14,
2938 0x1,
2939 1,
2940 0,
2941 p100pfs::Isel,
2942 p100pfs::Isel,
2943 P100Pfs_SPEC,
2944 crate::common::RW,
2945 > {
2946 crate::common::RegisterField::<
2947 14,
2948 0x1,
2949 1,
2950 0,
2951 p100pfs::Isel,
2952 p100pfs::Isel,
2953 P100Pfs_SPEC,
2954 crate::common::RW,
2955 >::from_register(self, 0)
2956 }
2957
2958 #[doc = "Event on Falling/Event on Rising"]
2959 #[inline(always)]
2960 pub fn eofr(
2961 self,
2962 ) -> crate::common::RegisterField<
2963 12,
2964 0x3,
2965 1,
2966 0,
2967 p100pfs::Eofr,
2968 p100pfs::Eofr,
2969 P100Pfs_SPEC,
2970 crate::common::RW,
2971 > {
2972 crate::common::RegisterField::<
2973 12,
2974 0x3,
2975 1,
2976 0,
2977 p100pfs::Eofr,
2978 p100pfs::Eofr,
2979 P100Pfs_SPEC,
2980 crate::common::RW,
2981 >::from_register(self, 0)
2982 }
2983
2984 #[doc = "Drive Strength Control Register"]
2985 #[inline(always)]
2986 pub fn dscr(
2987 self,
2988 ) -> crate::common::RegisterField<
2989 10,
2990 0x1,
2991 1,
2992 0,
2993 p100pfs::Dscr,
2994 p100pfs::Dscr,
2995 P100Pfs_SPEC,
2996 crate::common::RW,
2997 > {
2998 crate::common::RegisterField::<
2999 10,
3000 0x1,
3001 1,
3002 0,
3003 p100pfs::Dscr,
3004 p100pfs::Dscr,
3005 P100Pfs_SPEC,
3006 crate::common::RW,
3007 >::from_register(self, 0)
3008 }
3009
3010 #[doc = "N-Channel Open Drain Control"]
3011 #[inline(always)]
3012 pub fn ncodr(
3013 self,
3014 ) -> crate::common::RegisterField<
3015 6,
3016 0x1,
3017 1,
3018 0,
3019 p100pfs::Ncodr,
3020 p100pfs::Ncodr,
3021 P100Pfs_SPEC,
3022 crate::common::RW,
3023 > {
3024 crate::common::RegisterField::<
3025 6,
3026 0x1,
3027 1,
3028 0,
3029 p100pfs::Ncodr,
3030 p100pfs::Ncodr,
3031 P100Pfs_SPEC,
3032 crate::common::RW,
3033 >::from_register(self, 0)
3034 }
3035
3036 #[doc = "Pull-up Control"]
3037 #[inline(always)]
3038 pub fn pcr(
3039 self,
3040 ) -> crate::common::RegisterField<
3041 4,
3042 0x1,
3043 1,
3044 0,
3045 p100pfs::Pcr,
3046 p100pfs::Pcr,
3047 P100Pfs_SPEC,
3048 crate::common::RW,
3049 > {
3050 crate::common::RegisterField::<
3051 4,
3052 0x1,
3053 1,
3054 0,
3055 p100pfs::Pcr,
3056 p100pfs::Pcr,
3057 P100Pfs_SPEC,
3058 crate::common::RW,
3059 >::from_register(self, 0)
3060 }
3061
3062 #[doc = "This bit is read as 0. The write value should be 0."]
3063 #[inline(always)]
3064 pub fn reserved(
3065 self,
3066 ) -> crate::common::RegisterFieldBool<3, 1, 0, P100Pfs_SPEC, crate::common::RW> {
3067 crate::common::RegisterFieldBool::<3, 1, 0, P100Pfs_SPEC, crate::common::RW>::from_register(
3068 self, 0,
3069 )
3070 }
3071
3072 #[doc = "Port Direction"]
3073 #[inline(always)]
3074 pub fn pdr(
3075 self,
3076 ) -> crate::common::RegisterField<
3077 2,
3078 0x1,
3079 1,
3080 0,
3081 p100pfs::Pdr,
3082 p100pfs::Pdr,
3083 P100Pfs_SPEC,
3084 crate::common::RW,
3085 > {
3086 crate::common::RegisterField::<
3087 2,
3088 0x1,
3089 1,
3090 0,
3091 p100pfs::Pdr,
3092 p100pfs::Pdr,
3093 P100Pfs_SPEC,
3094 crate::common::RW,
3095 >::from_register(self, 0)
3096 }
3097
3098 #[doc = "Port Input Data"]
3099 #[inline(always)]
3100 pub fn pidr(
3101 self,
3102 ) -> crate::common::RegisterField<
3103 1,
3104 0x1,
3105 1,
3106 0,
3107 p100pfs::Pidr,
3108 p100pfs::Pidr,
3109 P100Pfs_SPEC,
3110 crate::common::R,
3111 > {
3112 crate::common::RegisterField::<
3113 1,
3114 0x1,
3115 1,
3116 0,
3117 p100pfs::Pidr,
3118 p100pfs::Pidr,
3119 P100Pfs_SPEC,
3120 crate::common::R,
3121 >::from_register(self, 0)
3122 }
3123
3124 #[doc = "Port Output Data"]
3125 #[inline(always)]
3126 pub fn podr(
3127 self,
3128 ) -> crate::common::RegisterField<
3129 0,
3130 0x1,
3131 1,
3132 0,
3133 p100pfs::Podr,
3134 p100pfs::Podr,
3135 P100Pfs_SPEC,
3136 crate::common::RW,
3137 > {
3138 crate::common::RegisterField::<
3139 0,
3140 0x1,
3141 1,
3142 0,
3143 p100pfs::Podr,
3144 p100pfs::Podr,
3145 P100Pfs_SPEC,
3146 crate::common::RW,
3147 >::from_register(self, 0)
3148 }
3149}
3150impl ::core::default::Default for P100Pfs {
3151 #[inline(always)]
3152 fn default() -> P100Pfs {
3153 <crate::RegValueT<P100Pfs_SPEC> as RegisterValue<_>>::new(0)
3154 }
3155}
3156pub mod p100pfs {
3157
3158 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3159 pub struct Pmr_SPEC;
3160 pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
3161 impl Pmr {
3162 #[doc = "Uses the pin as a general I/O pin."]
3163 pub const _0: Self = Self::new(0);
3164
3165 #[doc = "Uses the pin as an I/O port for peripheral functions."]
3166 pub const _1: Self = Self::new(1);
3167 }
3168 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3169 pub struct Asel_SPEC;
3170 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3171 impl Asel {
3172 #[doc = "Used other than as analog pin"]
3173 pub const _0: Self = Self::new(0);
3174
3175 #[doc = "Used as analog pin"]
3176 pub const _1: Self = Self::new(1);
3177 }
3178 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3179 pub struct Isel_SPEC;
3180 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3181 impl Isel {
3182 #[doc = "Not used as IRQn input pin"]
3183 pub const _0: Self = Self::new(0);
3184
3185 #[doc = "Used as IRQn input pin"]
3186 pub const _1: Self = Self::new(1);
3187 }
3188 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3189 pub struct Eofr_SPEC;
3190 pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3191 impl Eofr {
3192 #[doc = "Don\'t care"]
3193 pub const _00: Self = Self::new(0);
3194
3195 #[doc = "Detect rising edge"]
3196 pub const _01: Self = Self::new(1);
3197
3198 #[doc = "Detect falling edge"]
3199 pub const _10: Self = Self::new(2);
3200
3201 #[doc = "Detect both edge."]
3202 pub const _11: Self = Self::new(3);
3203 }
3204 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3205 pub struct Dscr_SPEC;
3206 pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
3207 impl Dscr {
3208 #[doc = "Low drive"]
3209 pub const _0: Self = Self::new(0);
3210
3211 #[doc = "High drive"]
3212 pub const _1: Self = Self::new(1);
3213 }
3214 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3215 pub struct Ncodr_SPEC;
3216 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3217 impl Ncodr {
3218 #[doc = "CMOS output"]
3219 pub const _0: Self = Self::new(0);
3220
3221 #[doc = "NMOS open-drain output"]
3222 pub const _1: Self = Self::new(1);
3223 }
3224 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3225 pub struct Pcr_SPEC;
3226 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3227 impl Pcr {
3228 #[doc = "Disables an input pull-up."]
3229 pub const _0: Self = Self::new(0);
3230
3231 #[doc = "Enables an input pull-up."]
3232 pub const _1: Self = Self::new(1);
3233 }
3234 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3235 pub struct Pdr_SPEC;
3236 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3237 impl Pdr {
3238 #[doc = "Input (Functions as an input pin.)"]
3239 pub const _0: Self = Self::new(0);
3240
3241 #[doc = "Output (Functions as an output pin.)"]
3242 pub const _1: Self = Self::new(1);
3243 }
3244 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3245 pub struct Pidr_SPEC;
3246 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3247 impl Pidr {
3248 #[doc = "Low input"]
3249 pub const _0: Self = Self::new(0);
3250
3251 #[doc = "High input"]
3252 pub const _1: Self = Self::new(1);
3253 }
3254 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3255 pub struct Podr_SPEC;
3256 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3257 impl Podr {
3258 #[doc = "Low output"]
3259 pub const _0: Self = Self::new(0);
3260
3261 #[doc = "High output"]
3262 pub const _1: Self = Self::new(1);
3263 }
3264}
3265#[doc(hidden)]
3266#[derive(Copy, Clone, Eq, PartialEq)]
3267pub struct P100PfsHa_SPEC;
3268impl crate::sealed::RegSpec for P100PfsHa_SPEC {
3269 type DataType = u16;
3270}
3271
3272#[doc = "P100 Pin Function Control Register"]
3273pub type P100PfsHa = crate::RegValueT<P100PfsHa_SPEC>;
3274
3275impl P100PfsHa {
3276 #[doc = "Analog Input enable"]
3277 #[inline(always)]
3278 pub fn asel(
3279 self,
3280 ) -> crate::common::RegisterField<
3281 15,
3282 0x1,
3283 1,
3284 0,
3285 p100pfs_ha::Asel,
3286 p100pfs_ha::Asel,
3287 P100PfsHa_SPEC,
3288 crate::common::RW,
3289 > {
3290 crate::common::RegisterField::<
3291 15,
3292 0x1,
3293 1,
3294 0,
3295 p100pfs_ha::Asel,
3296 p100pfs_ha::Asel,
3297 P100PfsHa_SPEC,
3298 crate::common::RW,
3299 >::from_register(self, 0)
3300 }
3301
3302 #[doc = "IRQ input enable"]
3303 #[inline(always)]
3304 pub fn isel(
3305 self,
3306 ) -> crate::common::RegisterField<
3307 14,
3308 0x1,
3309 1,
3310 0,
3311 p100pfs_ha::Isel,
3312 p100pfs_ha::Isel,
3313 P100PfsHa_SPEC,
3314 crate::common::RW,
3315 > {
3316 crate::common::RegisterField::<
3317 14,
3318 0x1,
3319 1,
3320 0,
3321 p100pfs_ha::Isel,
3322 p100pfs_ha::Isel,
3323 P100PfsHa_SPEC,
3324 crate::common::RW,
3325 >::from_register(self, 0)
3326 }
3327
3328 #[doc = "Event on Falling/Event on Rising"]
3329 #[inline(always)]
3330 pub fn eofr(
3331 self,
3332 ) -> crate::common::RegisterField<
3333 12,
3334 0x3,
3335 1,
3336 0,
3337 p100pfs_ha::Eofr,
3338 p100pfs_ha::Eofr,
3339 P100PfsHa_SPEC,
3340 crate::common::RW,
3341 > {
3342 crate::common::RegisterField::<
3343 12,
3344 0x3,
3345 1,
3346 0,
3347 p100pfs_ha::Eofr,
3348 p100pfs_ha::Eofr,
3349 P100PfsHa_SPEC,
3350 crate::common::RW,
3351 >::from_register(self, 0)
3352 }
3353
3354 #[doc = "Drive Strength Control Register"]
3355 #[inline(always)]
3356 pub fn dscr(
3357 self,
3358 ) -> crate::common::RegisterField<
3359 10,
3360 0x1,
3361 1,
3362 0,
3363 p100pfs_ha::Dscr,
3364 p100pfs_ha::Dscr,
3365 P100PfsHa_SPEC,
3366 crate::common::RW,
3367 > {
3368 crate::common::RegisterField::<
3369 10,
3370 0x1,
3371 1,
3372 0,
3373 p100pfs_ha::Dscr,
3374 p100pfs_ha::Dscr,
3375 P100PfsHa_SPEC,
3376 crate::common::RW,
3377 >::from_register(self, 0)
3378 }
3379
3380 #[doc = "N-Channel Open Drain Control"]
3381 #[inline(always)]
3382 pub fn ncodr(
3383 self,
3384 ) -> crate::common::RegisterField<
3385 6,
3386 0x1,
3387 1,
3388 0,
3389 p100pfs_ha::Ncodr,
3390 p100pfs_ha::Ncodr,
3391 P100PfsHa_SPEC,
3392 crate::common::RW,
3393 > {
3394 crate::common::RegisterField::<
3395 6,
3396 0x1,
3397 1,
3398 0,
3399 p100pfs_ha::Ncodr,
3400 p100pfs_ha::Ncodr,
3401 P100PfsHa_SPEC,
3402 crate::common::RW,
3403 >::from_register(self, 0)
3404 }
3405
3406 #[doc = "Pull-up Control"]
3407 #[inline(always)]
3408 pub fn pcr(
3409 self,
3410 ) -> crate::common::RegisterField<
3411 4,
3412 0x1,
3413 1,
3414 0,
3415 p100pfs_ha::Pcr,
3416 p100pfs_ha::Pcr,
3417 P100PfsHa_SPEC,
3418 crate::common::RW,
3419 > {
3420 crate::common::RegisterField::<
3421 4,
3422 0x1,
3423 1,
3424 0,
3425 p100pfs_ha::Pcr,
3426 p100pfs_ha::Pcr,
3427 P100PfsHa_SPEC,
3428 crate::common::RW,
3429 >::from_register(self, 0)
3430 }
3431
3432 #[doc = "This bit is read as 0. The write value should be 0."]
3433 #[inline(always)]
3434 pub fn reserved(
3435 self,
3436 ) -> crate::common::RegisterFieldBool<3, 1, 0, P100PfsHa_SPEC, crate::common::RW> {
3437 crate::common::RegisterFieldBool::<3,1,0,P100PfsHa_SPEC,crate::common::RW>::from_register(self,0)
3438 }
3439
3440 #[doc = "Port Direction"]
3441 #[inline(always)]
3442 pub fn pdr(
3443 self,
3444 ) -> crate::common::RegisterField<
3445 2,
3446 0x1,
3447 1,
3448 0,
3449 p100pfs_ha::Pdr,
3450 p100pfs_ha::Pdr,
3451 P100PfsHa_SPEC,
3452 crate::common::RW,
3453 > {
3454 crate::common::RegisterField::<
3455 2,
3456 0x1,
3457 1,
3458 0,
3459 p100pfs_ha::Pdr,
3460 p100pfs_ha::Pdr,
3461 P100PfsHa_SPEC,
3462 crate::common::RW,
3463 >::from_register(self, 0)
3464 }
3465
3466 #[doc = "Port Input Data"]
3467 #[inline(always)]
3468 pub fn pidr(
3469 self,
3470 ) -> crate::common::RegisterField<
3471 1,
3472 0x1,
3473 1,
3474 0,
3475 p100pfs_ha::Pidr,
3476 p100pfs_ha::Pidr,
3477 P100PfsHa_SPEC,
3478 crate::common::R,
3479 > {
3480 crate::common::RegisterField::<
3481 1,
3482 0x1,
3483 1,
3484 0,
3485 p100pfs_ha::Pidr,
3486 p100pfs_ha::Pidr,
3487 P100PfsHa_SPEC,
3488 crate::common::R,
3489 >::from_register(self, 0)
3490 }
3491
3492 #[doc = "Port Output Data"]
3493 #[inline(always)]
3494 pub fn podr(
3495 self,
3496 ) -> crate::common::RegisterField<
3497 0,
3498 0x1,
3499 1,
3500 0,
3501 p100pfs_ha::Podr,
3502 p100pfs_ha::Podr,
3503 P100PfsHa_SPEC,
3504 crate::common::RW,
3505 > {
3506 crate::common::RegisterField::<
3507 0,
3508 0x1,
3509 1,
3510 0,
3511 p100pfs_ha::Podr,
3512 p100pfs_ha::Podr,
3513 P100PfsHa_SPEC,
3514 crate::common::RW,
3515 >::from_register(self, 0)
3516 }
3517}
3518impl ::core::default::Default for P100PfsHa {
3519 #[inline(always)]
3520 fn default() -> P100PfsHa {
3521 <crate::RegValueT<P100PfsHa_SPEC> as RegisterValue<_>>::new(0)
3522 }
3523}
3524pub mod p100pfs_ha {
3525
3526 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3527 pub struct Asel_SPEC;
3528 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
3529 impl Asel {
3530 #[doc = "Used other than as analog pin"]
3531 pub const _0: Self = Self::new(0);
3532
3533 #[doc = "Used as analog pin"]
3534 pub const _1: Self = Self::new(1);
3535 }
3536 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3537 pub struct Isel_SPEC;
3538 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
3539 impl Isel {
3540 #[doc = "Not used as IRQn input pin"]
3541 pub const _0: Self = Self::new(0);
3542
3543 #[doc = "Used as IRQn input pin"]
3544 pub const _1: Self = Self::new(1);
3545 }
3546 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3547 pub struct Eofr_SPEC;
3548 pub type Eofr = crate::EnumBitfieldStruct<u8, Eofr_SPEC>;
3549 impl Eofr {
3550 #[doc = "Don\'t care"]
3551 pub const _00: Self = Self::new(0);
3552
3553 #[doc = "Detect rising edge"]
3554 pub const _01: Self = Self::new(1);
3555
3556 #[doc = "Detect falling edge"]
3557 pub const _10: Self = Self::new(2);
3558
3559 #[doc = "Detect both edge."]
3560 pub const _11: Self = Self::new(3);
3561 }
3562 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3563 pub struct Dscr_SPEC;
3564 pub type Dscr = crate::EnumBitfieldStruct<u8, Dscr_SPEC>;
3565 impl Dscr {
3566 #[doc = "Low drive"]
3567 pub const _0: Self = Self::new(0);
3568
3569 #[doc = "High drive"]
3570 pub const _1: Self = Self::new(1);
3571 }
3572 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3573 pub struct Ncodr_SPEC;
3574 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3575 impl Ncodr {
3576 #[doc = "CMOS output"]
3577 pub const _0: Self = Self::new(0);
3578
3579 #[doc = "NMOS open-drain output"]
3580 pub const _1: Self = Self::new(1);
3581 }
3582 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3583 pub struct Pcr_SPEC;
3584 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3585 impl Pcr {
3586 #[doc = "Disables an input pull-up."]
3587 pub const _0: Self = Self::new(0);
3588
3589 #[doc = "Enables an input pull-up."]
3590 pub const _1: Self = Self::new(1);
3591 }
3592 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3593 pub struct Pdr_SPEC;
3594 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3595 impl Pdr {
3596 #[doc = "Input (Functions as an input pin.)"]
3597 pub const _0: Self = Self::new(0);
3598
3599 #[doc = "Output (Functions as an output pin.)"]
3600 pub const _1: Self = Self::new(1);
3601 }
3602 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3603 pub struct Pidr_SPEC;
3604 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3605 impl Pidr {
3606 #[doc = "Low input"]
3607 pub const _0: Self = Self::new(0);
3608
3609 #[doc = "High input"]
3610 pub const _1: Self = Self::new(1);
3611 }
3612 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3613 pub struct Podr_SPEC;
3614 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3615 impl Podr {
3616 #[doc = "Low output"]
3617 pub const _0: Self = Self::new(0);
3618
3619 #[doc = "High output"]
3620 pub const _1: Self = Self::new(1);
3621 }
3622}
3623#[doc(hidden)]
3624#[derive(Copy, Clone, Eq, PartialEq)]
3625pub struct P100PfsBy_SPEC;
3626impl crate::sealed::RegSpec for P100PfsBy_SPEC {
3627 type DataType = u8;
3628}
3629
3630#[doc = "P100 Pin Function Control Register"]
3631pub type P100PfsBy = crate::RegValueT<P100PfsBy_SPEC>;
3632
3633impl P100PfsBy {
3634 #[doc = "N-Channel Open Drain Control"]
3635 #[inline(always)]
3636 pub fn ncodr(
3637 self,
3638 ) -> crate::common::RegisterField<
3639 6,
3640 0x1,
3641 1,
3642 0,
3643 p100pfs_by::Ncodr,
3644 p100pfs_by::Ncodr,
3645 P100PfsBy_SPEC,
3646 crate::common::RW,
3647 > {
3648 crate::common::RegisterField::<
3649 6,
3650 0x1,
3651 1,
3652 0,
3653 p100pfs_by::Ncodr,
3654 p100pfs_by::Ncodr,
3655 P100PfsBy_SPEC,
3656 crate::common::RW,
3657 >::from_register(self, 0)
3658 }
3659
3660 #[doc = "Pull-up Control"]
3661 #[inline(always)]
3662 pub fn pcr(
3663 self,
3664 ) -> crate::common::RegisterField<
3665 4,
3666 0x1,
3667 1,
3668 0,
3669 p100pfs_by::Pcr,
3670 p100pfs_by::Pcr,
3671 P100PfsBy_SPEC,
3672 crate::common::RW,
3673 > {
3674 crate::common::RegisterField::<
3675 4,
3676 0x1,
3677 1,
3678 0,
3679 p100pfs_by::Pcr,
3680 p100pfs_by::Pcr,
3681 P100PfsBy_SPEC,
3682 crate::common::RW,
3683 >::from_register(self, 0)
3684 }
3685
3686 #[doc = "This bit is read as 0. The write value should be 0."]
3687 #[inline(always)]
3688 pub fn reserved(
3689 self,
3690 ) -> crate::common::RegisterFieldBool<3, 1, 0, P100PfsBy_SPEC, crate::common::RW> {
3691 crate::common::RegisterFieldBool::<3,1,0,P100PfsBy_SPEC,crate::common::RW>::from_register(self,0)
3692 }
3693
3694 #[doc = "Port Direction"]
3695 #[inline(always)]
3696 pub fn pdr(
3697 self,
3698 ) -> crate::common::RegisterField<
3699 2,
3700 0x1,
3701 1,
3702 0,
3703 p100pfs_by::Pdr,
3704 p100pfs_by::Pdr,
3705 P100PfsBy_SPEC,
3706 crate::common::RW,
3707 > {
3708 crate::common::RegisterField::<
3709 2,
3710 0x1,
3711 1,
3712 0,
3713 p100pfs_by::Pdr,
3714 p100pfs_by::Pdr,
3715 P100PfsBy_SPEC,
3716 crate::common::RW,
3717 >::from_register(self, 0)
3718 }
3719
3720 #[doc = "Port Input Data"]
3721 #[inline(always)]
3722 pub fn pidr(
3723 self,
3724 ) -> crate::common::RegisterField<
3725 1,
3726 0x1,
3727 1,
3728 0,
3729 p100pfs_by::Pidr,
3730 p100pfs_by::Pidr,
3731 P100PfsBy_SPEC,
3732 crate::common::R,
3733 > {
3734 crate::common::RegisterField::<
3735 1,
3736 0x1,
3737 1,
3738 0,
3739 p100pfs_by::Pidr,
3740 p100pfs_by::Pidr,
3741 P100PfsBy_SPEC,
3742 crate::common::R,
3743 >::from_register(self, 0)
3744 }
3745
3746 #[doc = "Port Output Data"]
3747 #[inline(always)]
3748 pub fn podr(
3749 self,
3750 ) -> crate::common::RegisterField<
3751 0,
3752 0x1,
3753 1,
3754 0,
3755 p100pfs_by::Podr,
3756 p100pfs_by::Podr,
3757 P100PfsBy_SPEC,
3758 crate::common::RW,
3759 > {
3760 crate::common::RegisterField::<
3761 0,
3762 0x1,
3763 1,
3764 0,
3765 p100pfs_by::Podr,
3766 p100pfs_by::Podr,
3767 P100PfsBy_SPEC,
3768 crate::common::RW,
3769 >::from_register(self, 0)
3770 }
3771}
3772impl ::core::default::Default for P100PfsBy {
3773 #[inline(always)]
3774 fn default() -> P100PfsBy {
3775 <crate::RegValueT<P100PfsBy_SPEC> as RegisterValue<_>>::new(0)
3776 }
3777}
3778pub mod p100pfs_by {
3779
3780 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3781 pub struct Ncodr_SPEC;
3782 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
3783 impl Ncodr {
3784 #[doc = "CMOS output"]
3785 pub const _0: Self = Self::new(0);
3786
3787 #[doc = "NMOS open-drain output"]
3788 pub const _1: Self = Self::new(1);
3789 }
3790 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3791 pub struct Pcr_SPEC;
3792 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
3793 impl Pcr {
3794 #[doc = "Disables an input pull-up."]
3795 pub const _0: Self = Self::new(0);
3796
3797 #[doc = "Enables an input pull-up."]
3798 pub const _1: Self = Self::new(1);
3799 }
3800 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3801 pub struct Pdr_SPEC;
3802 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
3803 impl Pdr {
3804 #[doc = "Input (Functions as an input pin.)"]
3805 pub const _0: Self = Self::new(0);
3806
3807 #[doc = "Output (Functions as an output pin.)"]
3808 pub const _1: Self = Self::new(1);
3809 }
3810 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3811 pub struct Pidr_SPEC;
3812 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
3813 impl Pidr {
3814 #[doc = "Low input"]
3815 pub const _0: Self = Self::new(0);
3816
3817 #[doc = "High input"]
3818 pub const _1: Self = Self::new(1);
3819 }
3820 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3821 pub struct Podr_SPEC;
3822 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
3823 impl Podr {
3824 #[doc = "Low output"]
3825 pub const _0: Self = Self::new(0);
3826
3827 #[doc = "High output"]
3828 pub const _1: Self = Self::new(1);
3829 }
3830}
3831#[doc(hidden)]
3832#[derive(Copy, Clone, Eq, PartialEq)]
3833pub struct P10Pfs_SPEC;
3834impl crate::sealed::RegSpec for P10Pfs_SPEC {
3835 type DataType = u32;
3836}
3837
3838#[doc = "P10%s Pin Function Control Register"]
3839pub type P10Pfs = crate::RegValueT<P10Pfs_SPEC>;
3840
3841impl NoBitfieldReg<P10Pfs_SPEC> for P10Pfs {}
3842impl ::core::default::Default for P10Pfs {
3843 #[inline(always)]
3844 fn default() -> P10Pfs {
3845 <crate::RegValueT<P10Pfs_SPEC> as RegisterValue<_>>::new(0)
3846 }
3847}
3848
3849#[doc(hidden)]
3850#[derive(Copy, Clone, Eq, PartialEq)]
3851pub struct P10PfsHa_SPEC;
3852impl crate::sealed::RegSpec for P10PfsHa_SPEC {
3853 type DataType = u16;
3854}
3855
3856#[doc = "P10%s Pin Function Control Register"]
3857pub type P10PfsHa = crate::RegValueT<P10PfsHa_SPEC>;
3858
3859impl NoBitfieldReg<P10PfsHa_SPEC> for P10PfsHa {}
3860impl ::core::default::Default for P10PfsHa {
3861 #[inline(always)]
3862 fn default() -> P10PfsHa {
3863 <crate::RegValueT<P10PfsHa_SPEC> as RegisterValue<_>>::new(0)
3864 }
3865}
3866
3867#[doc(hidden)]
3868#[derive(Copy, Clone, Eq, PartialEq)]
3869pub struct P10PfsBy_SPEC;
3870impl crate::sealed::RegSpec for P10PfsBy_SPEC {
3871 type DataType = u8;
3872}
3873
3874#[doc = "P10%s Pin Function Control Register"]
3875pub type P10PfsBy = crate::RegValueT<P10PfsBy_SPEC>;
3876
3877impl NoBitfieldReg<P10PfsBy_SPEC> for P10PfsBy {}
3878impl ::core::default::Default for P10PfsBy {
3879 #[inline(always)]
3880 fn default() -> P10PfsBy {
3881 <crate::RegValueT<P10PfsBy_SPEC> as RegisterValue<_>>::new(0)
3882 }
3883}
3884
3885#[doc(hidden)]
3886#[derive(Copy, Clone, Eq, PartialEq)]
3887pub struct P108Pfs_SPEC;
3888impl crate::sealed::RegSpec for P108Pfs_SPEC {
3889 type DataType = u32;
3890}
3891
3892#[doc = "P108 Pin Function Control Register"]
3893pub type P108Pfs = crate::RegValueT<P108Pfs_SPEC>;
3894
3895impl NoBitfieldReg<P108Pfs_SPEC> for P108Pfs {}
3896impl ::core::default::Default for P108Pfs {
3897 #[inline(always)]
3898 fn default() -> P108Pfs {
3899 <crate::RegValueT<P108Pfs_SPEC> as RegisterValue<_>>::new(65552)
3900 }
3901}
3902
3903#[doc(hidden)]
3904#[derive(Copy, Clone, Eq, PartialEq)]
3905pub struct P108PfsHa_SPEC;
3906impl crate::sealed::RegSpec for P108PfsHa_SPEC {
3907 type DataType = u16;
3908}
3909
3910#[doc = "P108 Pin Function Control Register"]
3911pub type P108PfsHa = crate::RegValueT<P108PfsHa_SPEC>;
3912
3913impl NoBitfieldReg<P108PfsHa_SPEC> for P108PfsHa {}
3914impl ::core::default::Default for P108PfsHa {
3915 #[inline(always)]
3916 fn default() -> P108PfsHa {
3917 <crate::RegValueT<P108PfsHa_SPEC> as RegisterValue<_>>::new(16)
3918 }
3919}
3920
3921#[doc(hidden)]
3922#[derive(Copy, Clone, Eq, PartialEq)]
3923pub struct P108PfsBy_SPEC;
3924impl crate::sealed::RegSpec for P108PfsBy_SPEC {
3925 type DataType = u8;
3926}
3927
3928#[doc = "P108 Pin Function Control Register"]
3929pub type P108PfsBy = crate::RegValueT<P108PfsBy_SPEC>;
3930
3931impl NoBitfieldReg<P108PfsBy_SPEC> for P108PfsBy {}
3932impl ::core::default::Default for P108PfsBy {
3933 #[inline(always)]
3934 fn default() -> P108PfsBy {
3935 <crate::RegValueT<P108PfsBy_SPEC> as RegisterValue<_>>::new(16)
3936 }
3937}
3938
3939#[doc(hidden)]
3940#[derive(Copy, Clone, Eq, PartialEq)]
3941pub struct P109Pfs_SPEC;
3942impl crate::sealed::RegSpec for P109Pfs_SPEC {
3943 type DataType = u32;
3944}
3945
3946#[doc = "P109 Pin Function Control Register"]
3947pub type P109Pfs = crate::RegValueT<P109Pfs_SPEC>;
3948
3949impl NoBitfieldReg<P109Pfs_SPEC> for P109Pfs {}
3950impl ::core::default::Default for P109Pfs {
3951 #[inline(always)]
3952 fn default() -> P109Pfs {
3953 <crate::RegValueT<P109Pfs_SPEC> as RegisterValue<_>>::new(0)
3954 }
3955}
3956
3957#[doc(hidden)]
3958#[derive(Copy, Clone, Eq, PartialEq)]
3959pub struct P109PfsHa_SPEC;
3960impl crate::sealed::RegSpec for P109PfsHa_SPEC {
3961 type DataType = u16;
3962}
3963
3964#[doc = "P109 Pin Function Control Register"]
3965pub type P109PfsHa = crate::RegValueT<P109PfsHa_SPEC>;
3966
3967impl NoBitfieldReg<P109PfsHa_SPEC> for P109PfsHa {}
3968impl ::core::default::Default for P109PfsHa {
3969 #[inline(always)]
3970 fn default() -> P109PfsHa {
3971 <crate::RegValueT<P109PfsHa_SPEC> as RegisterValue<_>>::new(0)
3972 }
3973}
3974
3975#[doc(hidden)]
3976#[derive(Copy, Clone, Eq, PartialEq)]
3977pub struct P109PfsBy_SPEC;
3978impl crate::sealed::RegSpec for P109PfsBy_SPEC {
3979 type DataType = u8;
3980}
3981
3982#[doc = "P109 Pin Function Control Register"]
3983pub type P109PfsBy = crate::RegValueT<P109PfsBy_SPEC>;
3984
3985impl NoBitfieldReg<P109PfsBy_SPEC> for P109PfsBy {}
3986impl ::core::default::Default for P109PfsBy {
3987 #[inline(always)]
3988 fn default() -> P109PfsBy {
3989 <crate::RegValueT<P109PfsBy_SPEC> as RegisterValue<_>>::new(0)
3990 }
3991}
3992
3993#[doc(hidden)]
3994#[derive(Copy, Clone, Eq, PartialEq)]
3995pub struct P1Pfs_SPEC;
3996impl crate::sealed::RegSpec for P1Pfs_SPEC {
3997 type DataType = u32;
3998}
3999
4000#[doc = "P1%s Pin Function Control Register"]
4001pub type P1Pfs = crate::RegValueT<P1Pfs_SPEC>;
4002
4003impl NoBitfieldReg<P1Pfs_SPEC> for P1Pfs {}
4004impl ::core::default::Default for P1Pfs {
4005 #[inline(always)]
4006 fn default() -> P1Pfs {
4007 <crate::RegValueT<P1Pfs_SPEC> as RegisterValue<_>>::new(0)
4008 }
4009}
4010
4011#[doc(hidden)]
4012#[derive(Copy, Clone, Eq, PartialEq)]
4013pub struct P1PfsHa_SPEC;
4014impl crate::sealed::RegSpec for P1PfsHa_SPEC {
4015 type DataType = u16;
4016}
4017
4018#[doc = "P1%s Pin Function Control Register"]
4019pub type P1PfsHa = crate::RegValueT<P1PfsHa_SPEC>;
4020
4021impl NoBitfieldReg<P1PfsHa_SPEC> for P1PfsHa {}
4022impl ::core::default::Default for P1PfsHa {
4023 #[inline(always)]
4024 fn default() -> P1PfsHa {
4025 <crate::RegValueT<P1PfsHa_SPEC> as RegisterValue<_>>::new(0)
4026 }
4027}
4028
4029#[doc(hidden)]
4030#[derive(Copy, Clone, Eq, PartialEq)]
4031pub struct P1PfsBy_SPEC;
4032impl crate::sealed::RegSpec for P1PfsBy_SPEC {
4033 type DataType = u8;
4034}
4035
4036#[doc = "P1%s Pin Function Control Register"]
4037pub type P1PfsBy = crate::RegValueT<P1PfsBy_SPEC>;
4038
4039impl NoBitfieldReg<P1PfsBy_SPEC> for P1PfsBy {}
4040impl ::core::default::Default for P1PfsBy {
4041 #[inline(always)]
4042 fn default() -> P1PfsBy {
4043 <crate::RegValueT<P1PfsBy_SPEC> as RegisterValue<_>>::new(0)
4044 }
4045}
4046
4047#[doc(hidden)]
4048#[derive(Copy, Clone, Eq, PartialEq)]
4049pub struct P200Pfs_SPEC;
4050impl crate::sealed::RegSpec for P200Pfs_SPEC {
4051 type DataType = u32;
4052}
4053
4054#[doc = "P200 Pin Function Control Register"]
4055pub type P200Pfs = crate::RegValueT<P200Pfs_SPEC>;
4056
4057impl NoBitfieldReg<P200Pfs_SPEC> for P200Pfs {}
4058impl ::core::default::Default for P200Pfs {
4059 #[inline(always)]
4060 fn default() -> P200Pfs {
4061 <crate::RegValueT<P200Pfs_SPEC> as RegisterValue<_>>::new(0)
4062 }
4063}
4064
4065#[doc(hidden)]
4066#[derive(Copy, Clone, Eq, PartialEq)]
4067pub struct P200PfsHa_SPEC;
4068impl crate::sealed::RegSpec for P200PfsHa_SPEC {
4069 type DataType = u16;
4070}
4071
4072#[doc = "P200 Pin Function Control Register"]
4073pub type P200PfsHa = crate::RegValueT<P200PfsHa_SPEC>;
4074
4075impl NoBitfieldReg<P200PfsHa_SPEC> for P200PfsHa {}
4076impl ::core::default::Default for P200PfsHa {
4077 #[inline(always)]
4078 fn default() -> P200PfsHa {
4079 <crate::RegValueT<P200PfsHa_SPEC> as RegisterValue<_>>::new(0)
4080 }
4081}
4082
4083#[doc(hidden)]
4084#[derive(Copy, Clone, Eq, PartialEq)]
4085pub struct P200PfsBy_SPEC;
4086impl crate::sealed::RegSpec for P200PfsBy_SPEC {
4087 type DataType = u8;
4088}
4089
4090#[doc = "P200 Pin Function Control Register"]
4091pub type P200PfsBy = crate::RegValueT<P200PfsBy_SPEC>;
4092
4093impl NoBitfieldReg<P200PfsBy_SPEC> for P200PfsBy {}
4094impl ::core::default::Default for P200PfsBy {
4095 #[inline(always)]
4096 fn default() -> P200PfsBy {
4097 <crate::RegValueT<P200PfsBy_SPEC> as RegisterValue<_>>::new(0)
4098 }
4099}
4100
4101#[doc(hidden)]
4102#[derive(Copy, Clone, Eq, PartialEq)]
4103pub struct P201Pfs_SPEC;
4104impl crate::sealed::RegSpec for P201Pfs_SPEC {
4105 type DataType = u32;
4106}
4107
4108#[doc = "P201 Pin Function Control Register"]
4109pub type P201Pfs = crate::RegValueT<P201Pfs_SPEC>;
4110
4111impl NoBitfieldReg<P201Pfs_SPEC> for P201Pfs {}
4112impl ::core::default::Default for P201Pfs {
4113 #[inline(always)]
4114 fn default() -> P201Pfs {
4115 <crate::RegValueT<P201Pfs_SPEC> as RegisterValue<_>>::new(16)
4116 }
4117}
4118
4119#[doc(hidden)]
4120#[derive(Copy, Clone, Eq, PartialEq)]
4121pub struct P201PfsHa_SPEC;
4122impl crate::sealed::RegSpec for P201PfsHa_SPEC {
4123 type DataType = u16;
4124}
4125
4126#[doc = "P201 Pin Function Control Register"]
4127pub type P201PfsHa = crate::RegValueT<P201PfsHa_SPEC>;
4128
4129impl NoBitfieldReg<P201PfsHa_SPEC> for P201PfsHa {}
4130impl ::core::default::Default for P201PfsHa {
4131 #[inline(always)]
4132 fn default() -> P201PfsHa {
4133 <crate::RegValueT<P201PfsHa_SPEC> as RegisterValue<_>>::new(16)
4134 }
4135}
4136
4137#[doc(hidden)]
4138#[derive(Copy, Clone, Eq, PartialEq)]
4139pub struct P201PfsBy_SPEC;
4140impl crate::sealed::RegSpec for P201PfsBy_SPEC {
4141 type DataType = u8;
4142}
4143
4144#[doc = "P201 Pin Function Control Register"]
4145pub type P201PfsBy = crate::RegValueT<P201PfsBy_SPEC>;
4146
4147impl NoBitfieldReg<P201PfsBy_SPEC> for P201PfsBy {}
4148impl ::core::default::Default for P201PfsBy {
4149 #[inline(always)]
4150 fn default() -> P201PfsBy {
4151 <crate::RegValueT<P201PfsBy_SPEC> as RegisterValue<_>>::new(16)
4152 }
4153}
4154
4155#[doc(hidden)]
4156#[derive(Copy, Clone, Eq, PartialEq)]
4157pub struct P20Pfs_SPEC;
4158impl crate::sealed::RegSpec for P20Pfs_SPEC {
4159 type DataType = u32;
4160}
4161
4162#[doc = "P20%s Pin Function Control Register"]
4163pub type P20Pfs = crate::RegValueT<P20Pfs_SPEC>;
4164
4165impl NoBitfieldReg<P20Pfs_SPEC> for P20Pfs {}
4166impl ::core::default::Default for P20Pfs {
4167 #[inline(always)]
4168 fn default() -> P20Pfs {
4169 <crate::RegValueT<P20Pfs_SPEC> as RegisterValue<_>>::new(0)
4170 }
4171}
4172
4173#[doc(hidden)]
4174#[derive(Copy, Clone, Eq, PartialEq)]
4175pub struct P20PfsHa_SPEC;
4176impl crate::sealed::RegSpec for P20PfsHa_SPEC {
4177 type DataType = u16;
4178}
4179
4180#[doc = "P20%s Pin Function Control Register"]
4181pub type P20PfsHa = crate::RegValueT<P20PfsHa_SPEC>;
4182
4183impl NoBitfieldReg<P20PfsHa_SPEC> for P20PfsHa {}
4184impl ::core::default::Default for P20PfsHa {
4185 #[inline(always)]
4186 fn default() -> P20PfsHa {
4187 <crate::RegValueT<P20PfsHa_SPEC> as RegisterValue<_>>::new(0)
4188 }
4189}
4190
4191#[doc(hidden)]
4192#[derive(Copy, Clone, Eq, PartialEq)]
4193pub struct P20PfsBy_SPEC;
4194impl crate::sealed::RegSpec for P20PfsBy_SPEC {
4195 type DataType = u8;
4196}
4197
4198#[doc = "P20%s Pin Function Control Register"]
4199pub type P20PfsBy = crate::RegValueT<P20PfsBy_SPEC>;
4200
4201impl NoBitfieldReg<P20PfsBy_SPEC> for P20PfsBy {}
4202impl ::core::default::Default for P20PfsBy {
4203 #[inline(always)]
4204 fn default() -> P20PfsBy {
4205 <crate::RegValueT<P20PfsBy_SPEC> as RegisterValue<_>>::new(0)
4206 }
4207}
4208
4209#[doc(hidden)]
4210#[derive(Copy, Clone, Eq, PartialEq)]
4211pub struct P2Pfs_SPEC;
4212impl crate::sealed::RegSpec for P2Pfs_SPEC {
4213 type DataType = u32;
4214}
4215
4216#[doc = "P2%s Pin Function Control Register"]
4217pub type P2Pfs = crate::RegValueT<P2Pfs_SPEC>;
4218
4219impl NoBitfieldReg<P2Pfs_SPEC> for P2Pfs {}
4220impl ::core::default::Default for P2Pfs {
4221 #[inline(always)]
4222 fn default() -> P2Pfs {
4223 <crate::RegValueT<P2Pfs_SPEC> as RegisterValue<_>>::new(0)
4224 }
4225}
4226
4227#[doc(hidden)]
4228#[derive(Copy, Clone, Eq, PartialEq)]
4229pub struct P2PfsHa_SPEC;
4230impl crate::sealed::RegSpec for P2PfsHa_SPEC {
4231 type DataType = u16;
4232}
4233
4234#[doc = "P2%s Pin Function Control Register"]
4235pub type P2PfsHa = crate::RegValueT<P2PfsHa_SPEC>;
4236
4237impl NoBitfieldReg<P2PfsHa_SPEC> for P2PfsHa {}
4238impl ::core::default::Default for P2PfsHa {
4239 #[inline(always)]
4240 fn default() -> P2PfsHa {
4241 <crate::RegValueT<P2PfsHa_SPEC> as RegisterValue<_>>::new(0)
4242 }
4243}
4244
4245#[doc(hidden)]
4246#[derive(Copy, Clone, Eq, PartialEq)]
4247pub struct P2PfsBy_SPEC;
4248impl crate::sealed::RegSpec for P2PfsBy_SPEC {
4249 type DataType = u8;
4250}
4251
4252#[doc = "P2%s Pin Function Control Register"]
4253pub type P2PfsBy = crate::RegValueT<P2PfsBy_SPEC>;
4254
4255impl NoBitfieldReg<P2PfsBy_SPEC> for P2PfsBy {}
4256impl ::core::default::Default for P2PfsBy {
4257 #[inline(always)]
4258 fn default() -> P2PfsBy {
4259 <crate::RegValueT<P2PfsBy_SPEC> as RegisterValue<_>>::new(0)
4260 }
4261}
4262
4263#[doc(hidden)]
4264#[derive(Copy, Clone, Eq, PartialEq)]
4265pub struct P300Pfs_SPEC;
4266impl crate::sealed::RegSpec for P300Pfs_SPEC {
4267 type DataType = u32;
4268}
4269
4270#[doc = "P300 Pin Function Control Register"]
4271pub type P300Pfs = crate::RegValueT<P300Pfs_SPEC>;
4272
4273impl NoBitfieldReg<P300Pfs_SPEC> for P300Pfs {}
4274impl ::core::default::Default for P300Pfs {
4275 #[inline(always)]
4276 fn default() -> P300Pfs {
4277 <crate::RegValueT<P300Pfs_SPEC> as RegisterValue<_>>::new(65552)
4278 }
4279}
4280
4281#[doc(hidden)]
4282#[derive(Copy, Clone, Eq, PartialEq)]
4283pub struct P300PfsHa_SPEC;
4284impl crate::sealed::RegSpec for P300PfsHa_SPEC {
4285 type DataType = u16;
4286}
4287
4288#[doc = "P300 Pin Function Control Register"]
4289pub type P300PfsHa = crate::RegValueT<P300PfsHa_SPEC>;
4290
4291impl NoBitfieldReg<P300PfsHa_SPEC> for P300PfsHa {}
4292impl ::core::default::Default for P300PfsHa {
4293 #[inline(always)]
4294 fn default() -> P300PfsHa {
4295 <crate::RegValueT<P300PfsHa_SPEC> as RegisterValue<_>>::new(16)
4296 }
4297}
4298
4299#[doc(hidden)]
4300#[derive(Copy, Clone, Eq, PartialEq)]
4301pub struct P300PfsBy_SPEC;
4302impl crate::sealed::RegSpec for P300PfsBy_SPEC {
4303 type DataType = u8;
4304}
4305
4306#[doc = "P300 Pin Function Control Register"]
4307pub type P300PfsBy = crate::RegValueT<P300PfsBy_SPEC>;
4308
4309impl NoBitfieldReg<P300PfsBy_SPEC> for P300PfsBy {}
4310impl ::core::default::Default for P300PfsBy {
4311 #[inline(always)]
4312 fn default() -> P300PfsBy {
4313 <crate::RegValueT<P300PfsBy_SPEC> as RegisterValue<_>>::new(16)
4314 }
4315}
4316
4317#[doc(hidden)]
4318#[derive(Copy, Clone, Eq, PartialEq)]
4319pub struct P30Pfs_SPEC;
4320impl crate::sealed::RegSpec for P30Pfs_SPEC {
4321 type DataType = u32;
4322}
4323
4324#[doc = "P30%s Pin Function Control Register"]
4325pub type P30Pfs = crate::RegValueT<P30Pfs_SPEC>;
4326
4327impl NoBitfieldReg<P30Pfs_SPEC> for P30Pfs {}
4328impl ::core::default::Default for P30Pfs {
4329 #[inline(always)]
4330 fn default() -> P30Pfs {
4331 <crate::RegValueT<P30Pfs_SPEC> as RegisterValue<_>>::new(0)
4332 }
4333}
4334
4335#[doc(hidden)]
4336#[derive(Copy, Clone, Eq, PartialEq)]
4337pub struct P30PfsHa_SPEC;
4338impl crate::sealed::RegSpec for P30PfsHa_SPEC {
4339 type DataType = u16;
4340}
4341
4342#[doc = "P30%s Pin Function Control Register"]
4343pub type P30PfsHa = crate::RegValueT<P30PfsHa_SPEC>;
4344
4345impl NoBitfieldReg<P30PfsHa_SPEC> for P30PfsHa {}
4346impl ::core::default::Default for P30PfsHa {
4347 #[inline(always)]
4348 fn default() -> P30PfsHa {
4349 <crate::RegValueT<P30PfsHa_SPEC> as RegisterValue<_>>::new(0)
4350 }
4351}
4352
4353#[doc(hidden)]
4354#[derive(Copy, Clone, Eq, PartialEq)]
4355pub struct P30PfsBy_SPEC;
4356impl crate::sealed::RegSpec for P30PfsBy_SPEC {
4357 type DataType = u8;
4358}
4359
4360#[doc = "P30%s Pin Function Control Register"]
4361pub type P30PfsBy = crate::RegValueT<P30PfsBy_SPEC>;
4362
4363impl NoBitfieldReg<P30PfsBy_SPEC> for P30PfsBy {}
4364impl ::core::default::Default for P30PfsBy {
4365 #[inline(always)]
4366 fn default() -> P30PfsBy {
4367 <crate::RegValueT<P30PfsBy_SPEC> as RegisterValue<_>>::new(0)
4368 }
4369}
4370
4371#[doc(hidden)]
4372#[derive(Copy, Clone, Eq, PartialEq)]
4373pub struct P407Pfs_SPEC;
4374impl crate::sealed::RegSpec for P407Pfs_SPEC {
4375 type DataType = u32;
4376}
4377
4378#[doc = "P407 Pin Function Control Register"]
4379pub type P407Pfs = crate::RegValueT<P407Pfs_SPEC>;
4380
4381impl P407Pfs {
4382 #[doc = "Port Function Select\nThese bits select the peripheral function. For individual pin functions, see the MPC table"]
4383 #[inline(always)]
4384 pub fn psel(
4385 self,
4386 ) -> crate::common::RegisterField<24, 0x1f, 1, 0, u8, u8, P407Pfs_SPEC, crate::common::RW> {
4387 crate::common::RegisterField::<24,0x1f,1,0,u8,u8,P407Pfs_SPEC,crate::common::RW>::from_register(self,0)
4388 }
4389
4390 #[doc = "Port Mode Control"]
4391 #[inline(always)]
4392 pub fn pmr(
4393 self,
4394 ) -> crate::common::RegisterField<
4395 16,
4396 0x1,
4397 1,
4398 0,
4399 p407pfs::Pmr,
4400 p407pfs::Pmr,
4401 P407Pfs_SPEC,
4402 crate::common::RW,
4403 > {
4404 crate::common::RegisterField::<
4405 16,
4406 0x1,
4407 1,
4408 0,
4409 p407pfs::Pmr,
4410 p407pfs::Pmr,
4411 P407Pfs_SPEC,
4412 crate::common::RW,
4413 >::from_register(self, 0)
4414 }
4415
4416 #[doc = "Analog Input enable"]
4417 #[inline(always)]
4418 pub fn asel(
4419 self,
4420 ) -> crate::common::RegisterField<
4421 15,
4422 0x1,
4423 1,
4424 0,
4425 p407pfs::Asel,
4426 p407pfs::Asel,
4427 P407Pfs_SPEC,
4428 crate::common::RW,
4429 > {
4430 crate::common::RegisterField::<
4431 15,
4432 0x1,
4433 1,
4434 0,
4435 p407pfs::Asel,
4436 p407pfs::Asel,
4437 P407Pfs_SPEC,
4438 crate::common::RW,
4439 >::from_register(self, 0)
4440 }
4441
4442 #[doc = "IRQ input enable"]
4443 #[inline(always)]
4444 pub fn isel(
4445 self,
4446 ) -> crate::common::RegisterField<
4447 14,
4448 0x1,
4449 1,
4450 0,
4451 p407pfs::Isel,
4452 p407pfs::Isel,
4453 P407Pfs_SPEC,
4454 crate::common::RW,
4455 > {
4456 crate::common::RegisterField::<
4457 14,
4458 0x1,
4459 1,
4460 0,
4461 p407pfs::Isel,
4462 p407pfs::Isel,
4463 P407Pfs_SPEC,
4464 crate::common::RW,
4465 >::from_register(self, 0)
4466 }
4467
4468 #[doc = "Drive Strength Control Register"]
4469 #[inline(always)]
4470 pub fn dscr1(
4471 self,
4472 ) -> crate::common::RegisterField<
4473 11,
4474 0x1,
4475 1,
4476 0,
4477 p407pfs::Dscr1,
4478 p407pfs::Dscr1,
4479 P407Pfs_SPEC,
4480 crate::common::RW,
4481 > {
4482 crate::common::RegisterField::<
4483 11,
4484 0x1,
4485 1,
4486 0,
4487 p407pfs::Dscr1,
4488 p407pfs::Dscr1,
4489 P407Pfs_SPEC,
4490 crate::common::RW,
4491 >::from_register(self, 0)
4492 }
4493
4494 #[inline(always)]
4495 pub fn dscr(
4496 self,
4497 ) -> crate::common::RegisterFieldBool<10, 1, 0, P407Pfs_SPEC, crate::common::RW> {
4498 crate::common::RegisterFieldBool::<10, 1, 0, P407Pfs_SPEC, crate::common::RW>::from_register(
4499 self, 0,
4500 )
4501 }
4502
4503 #[doc = "N-Channel Open Drain Control"]
4504 #[inline(always)]
4505 pub fn ncodr(
4506 self,
4507 ) -> crate::common::RegisterField<
4508 6,
4509 0x1,
4510 1,
4511 0,
4512 p407pfs::Ncodr,
4513 p407pfs::Ncodr,
4514 P407Pfs_SPEC,
4515 crate::common::RW,
4516 > {
4517 crate::common::RegisterField::<
4518 6,
4519 0x1,
4520 1,
4521 0,
4522 p407pfs::Ncodr,
4523 p407pfs::Ncodr,
4524 P407Pfs_SPEC,
4525 crate::common::RW,
4526 >::from_register(self, 0)
4527 }
4528
4529 #[doc = "Pull-up Control"]
4530 #[inline(always)]
4531 pub fn pcr(
4532 self,
4533 ) -> crate::common::RegisterField<
4534 4,
4535 0x1,
4536 1,
4537 0,
4538 p407pfs::Pcr,
4539 p407pfs::Pcr,
4540 P407Pfs_SPEC,
4541 crate::common::RW,
4542 > {
4543 crate::common::RegisterField::<
4544 4,
4545 0x1,
4546 1,
4547 0,
4548 p407pfs::Pcr,
4549 p407pfs::Pcr,
4550 P407Pfs_SPEC,
4551 crate::common::RW,
4552 >::from_register(self, 0)
4553 }
4554
4555 #[doc = "This bit is read as 0. The write value should be 0."]
4556 #[inline(always)]
4557 pub fn reserved(
4558 self,
4559 ) -> crate::common::RegisterFieldBool<3, 1, 0, P407Pfs_SPEC, crate::common::RW> {
4560 crate::common::RegisterFieldBool::<3, 1, 0, P407Pfs_SPEC, crate::common::RW>::from_register(
4561 self, 0,
4562 )
4563 }
4564
4565 #[doc = "Port Direction"]
4566 #[inline(always)]
4567 pub fn pdr(
4568 self,
4569 ) -> crate::common::RegisterField<
4570 2,
4571 0x1,
4572 1,
4573 0,
4574 p407pfs::Pdr,
4575 p407pfs::Pdr,
4576 P407Pfs_SPEC,
4577 crate::common::RW,
4578 > {
4579 crate::common::RegisterField::<
4580 2,
4581 0x1,
4582 1,
4583 0,
4584 p407pfs::Pdr,
4585 p407pfs::Pdr,
4586 P407Pfs_SPEC,
4587 crate::common::RW,
4588 >::from_register(self, 0)
4589 }
4590
4591 #[doc = "Port Input Data"]
4592 #[inline(always)]
4593 pub fn pidr(
4594 self,
4595 ) -> crate::common::RegisterField<
4596 1,
4597 0x1,
4598 1,
4599 0,
4600 p407pfs::Pidr,
4601 p407pfs::Pidr,
4602 P407Pfs_SPEC,
4603 crate::common::R,
4604 > {
4605 crate::common::RegisterField::<
4606 1,
4607 0x1,
4608 1,
4609 0,
4610 p407pfs::Pidr,
4611 p407pfs::Pidr,
4612 P407Pfs_SPEC,
4613 crate::common::R,
4614 >::from_register(self, 0)
4615 }
4616
4617 #[doc = "Port Output Data"]
4618 #[inline(always)]
4619 pub fn podr(
4620 self,
4621 ) -> crate::common::RegisterField<
4622 0,
4623 0x1,
4624 1,
4625 0,
4626 p407pfs::Podr,
4627 p407pfs::Podr,
4628 P407Pfs_SPEC,
4629 crate::common::RW,
4630 > {
4631 crate::common::RegisterField::<
4632 0,
4633 0x1,
4634 1,
4635 0,
4636 p407pfs::Podr,
4637 p407pfs::Podr,
4638 P407Pfs_SPEC,
4639 crate::common::RW,
4640 >::from_register(self, 0)
4641 }
4642}
4643impl ::core::default::Default for P407Pfs {
4644 #[inline(always)]
4645 fn default() -> P407Pfs {
4646 <crate::RegValueT<P407Pfs_SPEC> as RegisterValue<_>>::new(0)
4647 }
4648}
4649pub mod p407pfs {
4650
4651 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4652 pub struct Pmr_SPEC;
4653 pub type Pmr = crate::EnumBitfieldStruct<u8, Pmr_SPEC>;
4654 impl Pmr {
4655 #[doc = "Uses the pin as a general I/O pin."]
4656 pub const _0: Self = Self::new(0);
4657
4658 #[doc = "Uses the pin as an I/O port for peripheral functions."]
4659 pub const _1: Self = Self::new(1);
4660 }
4661 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4662 pub struct Asel_SPEC;
4663 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4664 impl Asel {
4665 #[doc = "Used other than as analog pin"]
4666 pub const _0: Self = Self::new(0);
4667
4668 #[doc = "Used as analog pin"]
4669 pub const _1: Self = Self::new(1);
4670 }
4671 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4672 pub struct Isel_SPEC;
4673 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
4674 impl Isel {
4675 #[doc = "Not used as IRQn input pin"]
4676 pub const _0: Self = Self::new(0);
4677
4678 #[doc = "Used as IRQn input pin"]
4679 pub const _1: Self = Self::new(1);
4680 }
4681 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4682 pub struct Dscr1_SPEC;
4683 pub type Dscr1 = crate::EnumBitfieldStruct<u8, Dscr1_SPEC>;
4684 impl Dscr1 {
4685 #[doc = "Low drive"]
4686 pub const _00: Self = Self::new(0);
4687
4688 #[doc = "Middle drive"]
4689 pub const _01: Self = Self::new(1);
4690
4691 #[doc = "Middle drive for IIC Fast-mode and SPI"]
4692 pub const _10: Self = Self::new(0);
4693
4694 #[doc = "Setting prohibited."]
4695 pub const _11: Self = Self::new(1);
4696 }
4697 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4698 pub struct Ncodr_SPEC;
4699 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
4700 impl Ncodr {
4701 #[doc = "CMOS output"]
4702 pub const _0: Self = Self::new(0);
4703
4704 #[doc = "NMOS open-drain output"]
4705 pub const _1: Self = Self::new(1);
4706 }
4707 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4708 pub struct Pcr_SPEC;
4709 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
4710 impl Pcr {
4711 #[doc = "Disables an input pull-up."]
4712 pub const _0: Self = Self::new(0);
4713
4714 #[doc = "Enables an input pull-up."]
4715 pub const _1: Self = Self::new(1);
4716 }
4717 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4718 pub struct Pdr_SPEC;
4719 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
4720 impl Pdr {
4721 #[doc = "Input (Functions as an input pin.)"]
4722 pub const _0: Self = Self::new(0);
4723
4724 #[doc = "Output (Functions as an output pin.)"]
4725 pub const _1: Self = Self::new(1);
4726 }
4727 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4728 pub struct Pidr_SPEC;
4729 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
4730 impl Pidr {
4731 #[doc = "Low input"]
4732 pub const _0: Self = Self::new(0);
4733
4734 #[doc = "High input"]
4735 pub const _1: Self = Self::new(1);
4736 }
4737 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4738 pub struct Podr_SPEC;
4739 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
4740 impl Podr {
4741 #[doc = "Low output"]
4742 pub const _0: Self = Self::new(0);
4743
4744 #[doc = "High output"]
4745 pub const _1: Self = Self::new(1);
4746 }
4747}
4748#[doc(hidden)]
4749#[derive(Copy, Clone, Eq, PartialEq)]
4750pub struct P407PfsHa_SPEC;
4751impl crate::sealed::RegSpec for P407PfsHa_SPEC {
4752 type DataType = u16;
4753}
4754
4755#[doc = "P407 Pin Function Control Register"]
4756pub type P407PfsHa = crate::RegValueT<P407PfsHa_SPEC>;
4757
4758impl P407PfsHa {
4759 #[doc = "Analog Input enable"]
4760 #[inline(always)]
4761 pub fn asel(
4762 self,
4763 ) -> crate::common::RegisterField<
4764 15,
4765 0x1,
4766 1,
4767 0,
4768 p407pfs_ha::Asel,
4769 p407pfs_ha::Asel,
4770 P407PfsHa_SPEC,
4771 crate::common::RW,
4772 > {
4773 crate::common::RegisterField::<
4774 15,
4775 0x1,
4776 1,
4777 0,
4778 p407pfs_ha::Asel,
4779 p407pfs_ha::Asel,
4780 P407PfsHa_SPEC,
4781 crate::common::RW,
4782 >::from_register(self, 0)
4783 }
4784
4785 #[doc = "IRQ input enable"]
4786 #[inline(always)]
4787 pub fn isel(
4788 self,
4789 ) -> crate::common::RegisterField<
4790 14,
4791 0x1,
4792 1,
4793 0,
4794 p407pfs_ha::Isel,
4795 p407pfs_ha::Isel,
4796 P407PfsHa_SPEC,
4797 crate::common::RW,
4798 > {
4799 crate::common::RegisterField::<
4800 14,
4801 0x1,
4802 1,
4803 0,
4804 p407pfs_ha::Isel,
4805 p407pfs_ha::Isel,
4806 P407PfsHa_SPEC,
4807 crate::common::RW,
4808 >::from_register(self, 0)
4809 }
4810
4811 #[doc = "Drive Strength Control Register"]
4812 #[inline(always)]
4813 pub fn dscr1(
4814 self,
4815 ) -> crate::common::RegisterField<
4816 11,
4817 0x1,
4818 1,
4819 0,
4820 p407pfs_ha::Dscr1,
4821 p407pfs_ha::Dscr1,
4822 P407PfsHa_SPEC,
4823 crate::common::RW,
4824 > {
4825 crate::common::RegisterField::<
4826 11,
4827 0x1,
4828 1,
4829 0,
4830 p407pfs_ha::Dscr1,
4831 p407pfs_ha::Dscr1,
4832 P407PfsHa_SPEC,
4833 crate::common::RW,
4834 >::from_register(self, 0)
4835 }
4836
4837 #[inline(always)]
4838 pub fn dscr(
4839 self,
4840 ) -> crate::common::RegisterFieldBool<10, 1, 0, P407PfsHa_SPEC, crate::common::RW> {
4841 crate::common::RegisterFieldBool::<10,1,0,P407PfsHa_SPEC,crate::common::RW>::from_register(self,0)
4842 }
4843
4844 #[doc = "N-Channel Open Drain Control"]
4845 #[inline(always)]
4846 pub fn ncodr(
4847 self,
4848 ) -> crate::common::RegisterField<
4849 6,
4850 0x1,
4851 1,
4852 0,
4853 p407pfs_ha::Ncodr,
4854 p407pfs_ha::Ncodr,
4855 P407PfsHa_SPEC,
4856 crate::common::RW,
4857 > {
4858 crate::common::RegisterField::<
4859 6,
4860 0x1,
4861 1,
4862 0,
4863 p407pfs_ha::Ncodr,
4864 p407pfs_ha::Ncodr,
4865 P407PfsHa_SPEC,
4866 crate::common::RW,
4867 >::from_register(self, 0)
4868 }
4869
4870 #[doc = "Pull-up Control"]
4871 #[inline(always)]
4872 pub fn pcr(
4873 self,
4874 ) -> crate::common::RegisterField<
4875 4,
4876 0x1,
4877 1,
4878 0,
4879 p407pfs_ha::Pcr,
4880 p407pfs_ha::Pcr,
4881 P407PfsHa_SPEC,
4882 crate::common::RW,
4883 > {
4884 crate::common::RegisterField::<
4885 4,
4886 0x1,
4887 1,
4888 0,
4889 p407pfs_ha::Pcr,
4890 p407pfs_ha::Pcr,
4891 P407PfsHa_SPEC,
4892 crate::common::RW,
4893 >::from_register(self, 0)
4894 }
4895
4896 #[doc = "This bit is read as 0. The write value should be 0."]
4897 #[inline(always)]
4898 pub fn reserved(
4899 self,
4900 ) -> crate::common::RegisterFieldBool<3, 1, 0, P407PfsHa_SPEC, crate::common::RW> {
4901 crate::common::RegisterFieldBool::<3,1,0,P407PfsHa_SPEC,crate::common::RW>::from_register(self,0)
4902 }
4903
4904 #[doc = "Port Direction"]
4905 #[inline(always)]
4906 pub fn pdr(
4907 self,
4908 ) -> crate::common::RegisterField<
4909 2,
4910 0x1,
4911 1,
4912 0,
4913 p407pfs_ha::Pdr,
4914 p407pfs_ha::Pdr,
4915 P407PfsHa_SPEC,
4916 crate::common::RW,
4917 > {
4918 crate::common::RegisterField::<
4919 2,
4920 0x1,
4921 1,
4922 0,
4923 p407pfs_ha::Pdr,
4924 p407pfs_ha::Pdr,
4925 P407PfsHa_SPEC,
4926 crate::common::RW,
4927 >::from_register(self, 0)
4928 }
4929
4930 #[doc = "Port Input Data"]
4931 #[inline(always)]
4932 pub fn pidr(
4933 self,
4934 ) -> crate::common::RegisterField<
4935 1,
4936 0x1,
4937 1,
4938 0,
4939 p407pfs_ha::Pidr,
4940 p407pfs_ha::Pidr,
4941 P407PfsHa_SPEC,
4942 crate::common::R,
4943 > {
4944 crate::common::RegisterField::<
4945 1,
4946 0x1,
4947 1,
4948 0,
4949 p407pfs_ha::Pidr,
4950 p407pfs_ha::Pidr,
4951 P407PfsHa_SPEC,
4952 crate::common::R,
4953 >::from_register(self, 0)
4954 }
4955
4956 #[doc = "Port Output Data"]
4957 #[inline(always)]
4958 pub fn podr(
4959 self,
4960 ) -> crate::common::RegisterField<
4961 0,
4962 0x1,
4963 1,
4964 0,
4965 p407pfs_ha::Podr,
4966 p407pfs_ha::Podr,
4967 P407PfsHa_SPEC,
4968 crate::common::RW,
4969 > {
4970 crate::common::RegisterField::<
4971 0,
4972 0x1,
4973 1,
4974 0,
4975 p407pfs_ha::Podr,
4976 p407pfs_ha::Podr,
4977 P407PfsHa_SPEC,
4978 crate::common::RW,
4979 >::from_register(self, 0)
4980 }
4981}
4982impl ::core::default::Default for P407PfsHa {
4983 #[inline(always)]
4984 fn default() -> P407PfsHa {
4985 <crate::RegValueT<P407PfsHa_SPEC> as RegisterValue<_>>::new(0)
4986 }
4987}
4988pub mod p407pfs_ha {
4989
4990 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4991 pub struct Asel_SPEC;
4992 pub type Asel = crate::EnumBitfieldStruct<u8, Asel_SPEC>;
4993 impl Asel {
4994 #[doc = "Used other than as analog pin"]
4995 pub const _0: Self = Self::new(0);
4996
4997 #[doc = "Used as analog pin"]
4998 pub const _1: Self = Self::new(1);
4999 }
5000 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5001 pub struct Isel_SPEC;
5002 pub type Isel = crate::EnumBitfieldStruct<u8, Isel_SPEC>;
5003 impl Isel {
5004 #[doc = "Not used as IRQn input pin"]
5005 pub const _0: Self = Self::new(0);
5006
5007 #[doc = "Used as IRQn input pin"]
5008 pub const _1: Self = Self::new(1);
5009 }
5010 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5011 pub struct Dscr1_SPEC;
5012 pub type Dscr1 = crate::EnumBitfieldStruct<u8, Dscr1_SPEC>;
5013 impl Dscr1 {
5014 #[doc = "Low drive"]
5015 pub const _00: Self = Self::new(0);
5016
5017 #[doc = "Middle drive"]
5018 pub const _01: Self = Self::new(1);
5019
5020 #[doc = "Middle drive for IIC Fast-mode and SPI"]
5021 pub const _10: Self = Self::new(0);
5022
5023 #[doc = "Setting prohibited."]
5024 pub const _11: Self = Self::new(1);
5025 }
5026 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5027 pub struct Ncodr_SPEC;
5028 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5029 impl Ncodr {
5030 #[doc = "CMOS output"]
5031 pub const _0: Self = Self::new(0);
5032
5033 #[doc = "NMOS open-drain output"]
5034 pub const _1: Self = Self::new(1);
5035 }
5036 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5037 pub struct Pcr_SPEC;
5038 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5039 impl Pcr {
5040 #[doc = "Disables an input pull-up."]
5041 pub const _0: Self = Self::new(0);
5042
5043 #[doc = "Enables an input pull-up."]
5044 pub const _1: Self = Self::new(1);
5045 }
5046 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5047 pub struct Pdr_SPEC;
5048 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5049 impl Pdr {
5050 #[doc = "Input (Functions as an input pin.)"]
5051 pub const _0: Self = Self::new(0);
5052
5053 #[doc = "Output (Functions as an output pin.)"]
5054 pub const _1: Self = Self::new(1);
5055 }
5056 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5057 pub struct Pidr_SPEC;
5058 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5059 impl Pidr {
5060 #[doc = "Low input"]
5061 pub const _0: Self = Self::new(0);
5062
5063 #[doc = "High input"]
5064 pub const _1: Self = Self::new(1);
5065 }
5066 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5067 pub struct Podr_SPEC;
5068 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5069 impl Podr {
5070 #[doc = "Low output"]
5071 pub const _0: Self = Self::new(0);
5072
5073 #[doc = "High output"]
5074 pub const _1: Self = Self::new(1);
5075 }
5076}
5077#[doc(hidden)]
5078#[derive(Copy, Clone, Eq, PartialEq)]
5079pub struct P407PfsBy_SPEC;
5080impl crate::sealed::RegSpec for P407PfsBy_SPEC {
5081 type DataType = u8;
5082}
5083
5084#[doc = "P407 Pin Function Control Register"]
5085pub type P407PfsBy = crate::RegValueT<P407PfsBy_SPEC>;
5086
5087impl P407PfsBy {
5088 #[doc = "N-Channel Open Drain Control"]
5089 #[inline(always)]
5090 pub fn ncodr(
5091 self,
5092 ) -> crate::common::RegisterField<
5093 6,
5094 0x1,
5095 1,
5096 0,
5097 p407pfs_by::Ncodr,
5098 p407pfs_by::Ncodr,
5099 P407PfsBy_SPEC,
5100 crate::common::RW,
5101 > {
5102 crate::common::RegisterField::<
5103 6,
5104 0x1,
5105 1,
5106 0,
5107 p407pfs_by::Ncodr,
5108 p407pfs_by::Ncodr,
5109 P407PfsBy_SPEC,
5110 crate::common::RW,
5111 >::from_register(self, 0)
5112 }
5113
5114 #[doc = "Pull-up Control"]
5115 #[inline(always)]
5116 pub fn pcr(
5117 self,
5118 ) -> crate::common::RegisterField<
5119 4,
5120 0x1,
5121 1,
5122 0,
5123 p407pfs_by::Pcr,
5124 p407pfs_by::Pcr,
5125 P407PfsBy_SPEC,
5126 crate::common::RW,
5127 > {
5128 crate::common::RegisterField::<
5129 4,
5130 0x1,
5131 1,
5132 0,
5133 p407pfs_by::Pcr,
5134 p407pfs_by::Pcr,
5135 P407PfsBy_SPEC,
5136 crate::common::RW,
5137 >::from_register(self, 0)
5138 }
5139
5140 #[doc = "This bit is read as 0. The write value should be 0."]
5141 #[inline(always)]
5142 pub fn reserved(
5143 self,
5144 ) -> crate::common::RegisterFieldBool<3, 1, 0, P407PfsBy_SPEC, crate::common::RW> {
5145 crate::common::RegisterFieldBool::<3,1,0,P407PfsBy_SPEC,crate::common::RW>::from_register(self,0)
5146 }
5147
5148 #[doc = "Port Direction"]
5149 #[inline(always)]
5150 pub fn pdr(
5151 self,
5152 ) -> crate::common::RegisterField<
5153 2,
5154 0x1,
5155 1,
5156 0,
5157 p407pfs_by::Pdr,
5158 p407pfs_by::Pdr,
5159 P407PfsBy_SPEC,
5160 crate::common::RW,
5161 > {
5162 crate::common::RegisterField::<
5163 2,
5164 0x1,
5165 1,
5166 0,
5167 p407pfs_by::Pdr,
5168 p407pfs_by::Pdr,
5169 P407PfsBy_SPEC,
5170 crate::common::RW,
5171 >::from_register(self, 0)
5172 }
5173
5174 #[doc = "Port Input Data"]
5175 #[inline(always)]
5176 pub fn pidr(
5177 self,
5178 ) -> crate::common::RegisterField<
5179 1,
5180 0x1,
5181 1,
5182 0,
5183 p407pfs_by::Pidr,
5184 p407pfs_by::Pidr,
5185 P407PfsBy_SPEC,
5186 crate::common::R,
5187 > {
5188 crate::common::RegisterField::<
5189 1,
5190 0x1,
5191 1,
5192 0,
5193 p407pfs_by::Pidr,
5194 p407pfs_by::Pidr,
5195 P407PfsBy_SPEC,
5196 crate::common::R,
5197 >::from_register(self, 0)
5198 }
5199
5200 #[doc = "Port Output Data"]
5201 #[inline(always)]
5202 pub fn podr(
5203 self,
5204 ) -> crate::common::RegisterField<
5205 0,
5206 0x1,
5207 1,
5208 0,
5209 p407pfs_by::Podr,
5210 p407pfs_by::Podr,
5211 P407PfsBy_SPEC,
5212 crate::common::RW,
5213 > {
5214 crate::common::RegisterField::<
5215 0,
5216 0x1,
5217 1,
5218 0,
5219 p407pfs_by::Podr,
5220 p407pfs_by::Podr,
5221 P407PfsBy_SPEC,
5222 crate::common::RW,
5223 >::from_register(self, 0)
5224 }
5225}
5226impl ::core::default::Default for P407PfsBy {
5227 #[inline(always)]
5228 fn default() -> P407PfsBy {
5229 <crate::RegValueT<P407PfsBy_SPEC> as RegisterValue<_>>::new(0)
5230 }
5231}
5232pub mod p407pfs_by {
5233
5234 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5235 pub struct Ncodr_SPEC;
5236 pub type Ncodr = crate::EnumBitfieldStruct<u8, Ncodr_SPEC>;
5237 impl Ncodr {
5238 #[doc = "CMOS output"]
5239 pub const _0: Self = Self::new(0);
5240
5241 #[doc = "NMOS open-drain output"]
5242 pub const _1: Self = Self::new(1);
5243 }
5244 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5245 pub struct Pcr_SPEC;
5246 pub type Pcr = crate::EnumBitfieldStruct<u8, Pcr_SPEC>;
5247 impl Pcr {
5248 #[doc = "Disables an input pull-up."]
5249 pub const _0: Self = Self::new(0);
5250
5251 #[doc = "Enables an input pull-up."]
5252 pub const _1: Self = Self::new(1);
5253 }
5254 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5255 pub struct Pdr_SPEC;
5256 pub type Pdr = crate::EnumBitfieldStruct<u8, Pdr_SPEC>;
5257 impl Pdr {
5258 #[doc = "Input (Functions as an input pin.)"]
5259 pub const _0: Self = Self::new(0);
5260
5261 #[doc = "Output (Functions as an output pin.)"]
5262 pub const _1: Self = Self::new(1);
5263 }
5264 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5265 pub struct Pidr_SPEC;
5266 pub type Pidr = crate::EnumBitfieldStruct<u8, Pidr_SPEC>;
5267 impl Pidr {
5268 #[doc = "Low input"]
5269 pub const _0: Self = Self::new(0);
5270
5271 #[doc = "High input"]
5272 pub const _1: Self = Self::new(1);
5273 }
5274 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
5275 pub struct Podr_SPEC;
5276 pub type Podr = crate::EnumBitfieldStruct<u8, Podr_SPEC>;
5277 impl Podr {
5278 #[doc = "Low output"]
5279 pub const _0: Self = Self::new(0);
5280
5281 #[doc = "High output"]
5282 pub const _1: Self = Self::new(1);
5283 }
5284}
5285#[doc(hidden)]
5286#[derive(Copy, Clone, Eq, PartialEq)]
5287pub struct P40Pfs_SPEC;
5288impl crate::sealed::RegSpec for P40Pfs_SPEC {
5289 type DataType = u32;
5290}
5291
5292#[doc = "P40%s Pin Function Control Register"]
5293pub type P40Pfs = crate::RegValueT<P40Pfs_SPEC>;
5294
5295impl NoBitfieldReg<P40Pfs_SPEC> for P40Pfs {}
5296impl ::core::default::Default for P40Pfs {
5297 #[inline(always)]
5298 fn default() -> P40Pfs {
5299 <crate::RegValueT<P40Pfs_SPEC> as RegisterValue<_>>::new(0)
5300 }
5301}
5302
5303#[doc(hidden)]
5304#[derive(Copy, Clone, Eq, PartialEq)]
5305pub struct P40PfsHa_SPEC;
5306impl crate::sealed::RegSpec for P40PfsHa_SPEC {
5307 type DataType = u16;
5308}
5309
5310#[doc = "P40%s Pin Function Control Register"]
5311pub type P40PfsHa = crate::RegValueT<P40PfsHa_SPEC>;
5312
5313impl NoBitfieldReg<P40PfsHa_SPEC> for P40PfsHa {}
5314impl ::core::default::Default for P40PfsHa {
5315 #[inline(always)]
5316 fn default() -> P40PfsHa {
5317 <crate::RegValueT<P40PfsHa_SPEC> as RegisterValue<_>>::new(0)
5318 }
5319}
5320
5321#[doc(hidden)]
5322#[derive(Copy, Clone, Eq, PartialEq)]
5323pub struct P40PfsBy_SPEC;
5324impl crate::sealed::RegSpec for P40PfsBy_SPEC {
5325 type DataType = u8;
5326}
5327
5328#[doc = "P40%s Pin Function Control Register"]
5329pub type P40PfsBy = crate::RegValueT<P40PfsBy_SPEC>;
5330
5331impl NoBitfieldReg<P40PfsBy_SPEC> for P40PfsBy {}
5332impl ::core::default::Default for P40PfsBy {
5333 #[inline(always)]
5334 fn default() -> P40PfsBy {
5335 <crate::RegValueT<P40PfsBy_SPEC> as RegisterValue<_>>::new(0)
5336 }
5337}
5338
5339#[doc(hidden)]
5340#[derive(Copy, Clone, Eq, PartialEq)]
5341pub struct P4Pfs_SPEC;
5342impl crate::sealed::RegSpec for P4Pfs_SPEC {
5343 type DataType = u32;
5344}
5345
5346#[doc = "P4%s Pin Function Control Register"]
5347pub type P4Pfs = crate::RegValueT<P4Pfs_SPEC>;
5348
5349impl NoBitfieldReg<P4Pfs_SPEC> for P4Pfs {}
5350impl ::core::default::Default for P4Pfs {
5351 #[inline(always)]
5352 fn default() -> P4Pfs {
5353 <crate::RegValueT<P4Pfs_SPEC> as RegisterValue<_>>::new(0)
5354 }
5355}
5356
5357#[doc(hidden)]
5358#[derive(Copy, Clone, Eq, PartialEq)]
5359pub struct P4PfsHa_SPEC;
5360impl crate::sealed::RegSpec for P4PfsHa_SPEC {
5361 type DataType = u16;
5362}
5363
5364#[doc = "P4%s Pin Function Control Register"]
5365pub type P4PfsHa = crate::RegValueT<P4PfsHa_SPEC>;
5366
5367impl NoBitfieldReg<P4PfsHa_SPEC> for P4PfsHa {}
5368impl ::core::default::Default for P4PfsHa {
5369 #[inline(always)]
5370 fn default() -> P4PfsHa {
5371 <crate::RegValueT<P4PfsHa_SPEC> as RegisterValue<_>>::new(0)
5372 }
5373}
5374
5375#[doc(hidden)]
5376#[derive(Copy, Clone, Eq, PartialEq)]
5377pub struct P4PfsBy_SPEC;
5378impl crate::sealed::RegSpec for P4PfsBy_SPEC {
5379 type DataType = u8;
5380}
5381
5382#[doc = "P4%s Pin Function Control Register"]
5383pub type P4PfsBy = crate::RegValueT<P4PfsBy_SPEC>;
5384
5385impl NoBitfieldReg<P4PfsBy_SPEC> for P4PfsBy {}
5386impl ::core::default::Default for P4PfsBy {
5387 #[inline(always)]
5388 fn default() -> P4PfsBy {
5389 <crate::RegValueT<P4PfsBy_SPEC> as RegisterValue<_>>::new(0)
5390 }
5391}
5392
5393#[doc(hidden)]
5394#[derive(Copy, Clone, Eq, PartialEq)]
5395pub struct P50Pfs_SPEC;
5396impl crate::sealed::RegSpec for P50Pfs_SPEC {
5397 type DataType = u32;
5398}
5399
5400#[doc = "P50%s Pin Function Control Register"]
5401pub type P50Pfs = crate::RegValueT<P50Pfs_SPEC>;
5402
5403impl NoBitfieldReg<P50Pfs_SPEC> for P50Pfs {}
5404impl ::core::default::Default for P50Pfs {
5405 #[inline(always)]
5406 fn default() -> P50Pfs {
5407 <crate::RegValueT<P50Pfs_SPEC> as RegisterValue<_>>::new(0)
5408 }
5409}
5410
5411#[doc(hidden)]
5412#[derive(Copy, Clone, Eq, PartialEq)]
5413pub struct P50PfsHa_SPEC;
5414impl crate::sealed::RegSpec for P50PfsHa_SPEC {
5415 type DataType = u16;
5416}
5417
5418#[doc = "P50%s Pin Function Control Register"]
5419pub type P50PfsHa = crate::RegValueT<P50PfsHa_SPEC>;
5420
5421impl NoBitfieldReg<P50PfsHa_SPEC> for P50PfsHa {}
5422impl ::core::default::Default for P50PfsHa {
5423 #[inline(always)]
5424 fn default() -> P50PfsHa {
5425 <crate::RegValueT<P50PfsHa_SPEC> as RegisterValue<_>>::new(0)
5426 }
5427}
5428
5429#[doc(hidden)]
5430#[derive(Copy, Clone, Eq, PartialEq)]
5431pub struct P50PfsBy_SPEC;
5432impl crate::sealed::RegSpec for P50PfsBy_SPEC {
5433 type DataType = u8;
5434}
5435
5436#[doc = "P50%s Pin Function Control Register"]
5437pub type P50PfsBy = crate::RegValueT<P50PfsBy_SPEC>;
5438
5439impl NoBitfieldReg<P50PfsBy_SPEC> for P50PfsBy {}
5440impl ::core::default::Default for P50PfsBy {
5441 #[inline(always)]
5442 fn default() -> P50PfsBy {
5443 <crate::RegValueT<P50PfsBy_SPEC> as RegisterValue<_>>::new(0)
5444 }
5445}
5446
5447#[doc(hidden)]
5448#[derive(Copy, Clone, Eq, PartialEq)]
5449pub struct P914Pfs_SPEC;
5450impl crate::sealed::RegSpec for P914Pfs_SPEC {
5451 type DataType = u32;
5452}
5453
5454#[doc = "P914 Pin Function Control Register"]
5455pub type P914Pfs = crate::RegValueT<P914Pfs_SPEC>;
5456
5457impl NoBitfieldReg<P914Pfs_SPEC> for P914Pfs {}
5458impl ::core::default::Default for P914Pfs {
5459 #[inline(always)]
5460 fn default() -> P914Pfs {
5461 <crate::RegValueT<P914Pfs_SPEC> as RegisterValue<_>>::new(65536)
5462 }
5463}
5464
5465#[doc(hidden)]
5466#[derive(Copy, Clone, Eq, PartialEq)]
5467pub struct P914PfsHa_SPEC;
5468impl crate::sealed::RegSpec for P914PfsHa_SPEC {
5469 type DataType = u16;
5470}
5471
5472#[doc = "P914 Pin Function Control Register"]
5473pub type P914PfsHa = crate::RegValueT<P914PfsHa_SPEC>;
5474
5475impl NoBitfieldReg<P914PfsHa_SPEC> for P914PfsHa {}
5476impl ::core::default::Default for P914PfsHa {
5477 #[inline(always)]
5478 fn default() -> P914PfsHa {
5479 <crate::RegValueT<P914PfsHa_SPEC> as RegisterValue<_>>::new(0)
5480 }
5481}
5482
5483#[doc(hidden)]
5484#[derive(Copy, Clone, Eq, PartialEq)]
5485pub struct P914PfsBy_SPEC;
5486impl crate::sealed::RegSpec for P914PfsBy_SPEC {
5487 type DataType = u8;
5488}
5489
5490#[doc = "P914 Pin Function Control Register"]
5491pub type P914PfsBy = crate::RegValueT<P914PfsBy_SPEC>;
5492
5493impl NoBitfieldReg<P914PfsBy_SPEC> for P914PfsBy {}
5494impl ::core::default::Default for P914PfsBy {
5495 #[inline(always)]
5496 fn default() -> P914PfsBy {
5497 <crate::RegValueT<P914PfsBy_SPEC> as RegisterValue<_>>::new(0)
5498 }
5499}
5500
5501#[doc(hidden)]
5502#[derive(Copy, Clone, Eq, PartialEq)]
5503pub struct P915Pfs_SPEC;
5504impl crate::sealed::RegSpec for P915Pfs_SPEC {
5505 type DataType = u32;
5506}
5507
5508#[doc = "P915 Pin Function Control Register"]
5509pub type P915Pfs = crate::RegValueT<P915Pfs_SPEC>;
5510
5511impl NoBitfieldReg<P915Pfs_SPEC> for P915Pfs {}
5512impl ::core::default::Default for P915Pfs {
5513 #[inline(always)]
5514 fn default() -> P915Pfs {
5515 <crate::RegValueT<P915Pfs_SPEC> as RegisterValue<_>>::new(65536)
5516 }
5517}
5518
5519#[doc(hidden)]
5520#[derive(Copy, Clone, Eq, PartialEq)]
5521pub struct P915PfsHa_SPEC;
5522impl crate::sealed::RegSpec for P915PfsHa_SPEC {
5523 type DataType = u16;
5524}
5525
5526#[doc = "P915 Pin Function Control Register"]
5527pub type P915PfsHa = crate::RegValueT<P915PfsHa_SPEC>;
5528
5529impl NoBitfieldReg<P915PfsHa_SPEC> for P915PfsHa {}
5530impl ::core::default::Default for P915PfsHa {
5531 #[inline(always)]
5532 fn default() -> P915PfsHa {
5533 <crate::RegValueT<P915PfsHa_SPEC> as RegisterValue<_>>::new(0)
5534 }
5535}
5536
5537#[doc(hidden)]
5538#[derive(Copy, Clone, Eq, PartialEq)]
5539pub struct P915PfsBy_SPEC;
5540impl crate::sealed::RegSpec for P915PfsBy_SPEC {
5541 type DataType = u8;
5542}
5543
5544#[doc = "P915 Pin Function Control Register"]
5545pub type P915PfsBy = crate::RegValueT<P915PfsBy_SPEC>;
5546
5547impl NoBitfieldReg<P915PfsBy_SPEC> for P915PfsBy {}
5548impl ::core::default::Default for P915PfsBy {
5549 #[inline(always)]
5550 fn default() -> P915PfsBy {
5551 <crate::RegValueT<P915PfsBy_SPEC> as RegisterValue<_>>::new(0)
5552 }
5553}