ra2a1_pac/
iic1.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Inter-Integrated Circuit 1"]
28unsafe impl ::core::marker::Send for super::Iic1 {}
29unsafe impl ::core::marker::Sync for super::Iic1 {}
30impl super::Iic1 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "I2C Bus Control Register 1"]
38    #[inline(always)]
39    pub const fn iccr1(&self) -> &'static crate::common::Reg<self::Iccr1_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Iccr1_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "I2C Bus Control Register 2"]
48    #[inline(always)]
49    pub const fn iccr2(&self) -> &'static crate::common::Reg<self::Iccr2_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Iccr2_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "I2C Bus Mode Register 1"]
58    #[inline(always)]
59    pub const fn icmr1(&self) -> &'static crate::common::Reg<self::Icmr1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Icmr1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "I2C Bus Mode Register 2"]
68    #[inline(always)]
69    pub const fn icmr2(&self) -> &'static crate::common::Reg<self::Icmr2_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Icmr2_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(3usize),
73            )
74        }
75    }
76
77    #[doc = "I2C Bus Mode Register 3"]
78    #[inline(always)]
79    pub const fn icmr3(&self) -> &'static crate::common::Reg<self::Icmr3_SPEC, crate::common::RW> {
80        unsafe {
81            crate::common::Reg::<self::Icmr3_SPEC, crate::common::RW>::from_ptr(
82                self._svd2pac_as_ptr().add(4usize),
83            )
84        }
85    }
86
87    #[doc = "I2C Bus Function Enable Register"]
88    #[inline(always)]
89    pub const fn icfer(&self) -> &'static crate::common::Reg<self::Icfer_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Icfer_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(5usize),
93            )
94        }
95    }
96
97    #[doc = "I2C Bus Status Enable Register"]
98    #[inline(always)]
99    pub const fn icser(&self) -> &'static crate::common::Reg<self::Icser_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Icser_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(6usize),
103            )
104        }
105    }
106
107    #[doc = "I2C Bus Interrupt Enable Register"]
108    #[inline(always)]
109    pub const fn icier(&self) -> &'static crate::common::Reg<self::Icier_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Icier_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(7usize),
113            )
114        }
115    }
116
117    #[doc = "I2C Bus Status Register 1"]
118    #[inline(always)]
119    pub const fn icsr1(&self) -> &'static crate::common::Reg<self::Icsr1_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Icsr1_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(8usize),
123            )
124        }
125    }
126
127    #[doc = "I2C Bus Status Register 2"]
128    #[inline(always)]
129    pub const fn icsr2(&self) -> &'static crate::common::Reg<self::Icsr2_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Icsr2_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(9usize),
133            )
134        }
135    }
136
137    #[doc = "Slave Address Register L%s"]
138    #[inline(always)]
139    pub const fn sarl(
140        &self,
141    ) -> &'static crate::common::ClusterRegisterArray<
142        crate::common::Reg<self::Sarl_SPEC, crate::common::RW>,
143        3,
144        0x2,
145    > {
146        unsafe {
147            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xausize))
148        }
149    }
150    #[inline(always)]
151    pub const fn sarl0(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
152        unsafe {
153            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
154                self._svd2pac_as_ptr().add(0xausize),
155            )
156        }
157    }
158    #[inline(always)]
159    pub const fn sarl1(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(0xcusize),
163            )
164        }
165    }
166    #[inline(always)]
167    pub const fn sarl2(&self) -> &'static crate::common::Reg<self::Sarl_SPEC, crate::common::RW> {
168        unsafe {
169            crate::common::Reg::<self::Sarl_SPEC, crate::common::RW>::from_ptr(
170                self._svd2pac_as_ptr().add(0xeusize),
171            )
172        }
173    }
174
175    #[doc = "Slave Address Register U%s"]
176    #[inline(always)]
177    pub const fn saru(
178        &self,
179    ) -> &'static crate::common::ClusterRegisterArray<
180        crate::common::Reg<self::Saru_SPEC, crate::common::RW>,
181        3,
182        0x2,
183    > {
184        unsafe {
185            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0xbusize))
186        }
187    }
188    #[inline(always)]
189    pub const fn saru0(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
190        unsafe {
191            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
192                self._svd2pac_as_ptr().add(0xbusize),
193            )
194        }
195    }
196    #[inline(always)]
197    pub const fn saru1(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
198        unsafe {
199            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
200                self._svd2pac_as_ptr().add(0xdusize),
201            )
202        }
203    }
204    #[inline(always)]
205    pub const fn saru2(&self) -> &'static crate::common::Reg<self::Saru_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Saru_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(0xfusize),
209            )
210        }
211    }
212
213    #[doc = "I2C Bus Bit Rate Low-Level Register"]
214    #[inline(always)]
215    pub const fn icbrl(&self) -> &'static crate::common::Reg<self::Icbrl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Icbrl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(16usize),
219            )
220        }
221    }
222
223    #[doc = "I2C Bus Bit Rate High-Level Register"]
224    #[inline(always)]
225    pub const fn icbrh(&self) -> &'static crate::common::Reg<self::Icbrh_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Icbrh_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(17usize),
229            )
230        }
231    }
232
233    #[doc = "I2C Bus Transmit Data Register"]
234    #[inline(always)]
235    pub const fn icdrt(&self) -> &'static crate::common::Reg<self::Icdrt_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Icdrt_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "I2C Bus Receive Data Register"]
244    #[inline(always)]
245    pub const fn icdrr(&self) -> &'static crate::common::Reg<self::Icdrr_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Icdrr_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252}
253#[doc(hidden)]
254#[derive(Copy, Clone, Eq, PartialEq)]
255pub struct Iccr1_SPEC;
256impl crate::sealed::RegSpec for Iccr1_SPEC {
257    type DataType = u8;
258}
259
260#[doc = "I2C Bus Control Register 1"]
261pub type Iccr1 = crate::RegValueT<Iccr1_SPEC>;
262
263impl Iccr1 {
264    #[doc = "I2C Bus Interface Enable"]
265    #[inline(always)]
266    pub fn ice(
267        self,
268    ) -> crate::common::RegisterField<
269        7,
270        0x1,
271        1,
272        0,
273        iccr1::Ice,
274        iccr1::Ice,
275        Iccr1_SPEC,
276        crate::common::RW,
277    > {
278        crate::common::RegisterField::<
279            7,
280            0x1,
281            1,
282            0,
283            iccr1::Ice,
284            iccr1::Ice,
285            Iccr1_SPEC,
286            crate::common::RW,
287        >::from_register(self, 0)
288    }
289
290    #[doc = "I2C Bus Interface Internal ResetNote:If an internal reset is initiated using the IICRST bit for a bus hang-up occurred during communication with the master device in slave mode, the states may become different between the slave device and the master device (due to the difference in the bit counter information)."]
291    #[inline(always)]
292    pub fn iicrst(
293        self,
294    ) -> crate::common::RegisterField<
295        6,
296        0x1,
297        1,
298        0,
299        iccr1::Iicrst,
300        iccr1::Iicrst,
301        Iccr1_SPEC,
302        crate::common::RW,
303    > {
304        crate::common::RegisterField::<
305            6,
306            0x1,
307            1,
308            0,
309            iccr1::Iicrst,
310            iccr1::Iicrst,
311            Iccr1_SPEC,
312            crate::common::RW,
313        >::from_register(self, 0)
314    }
315
316    #[doc = "Extra SCL Clock Cycle Output"]
317    #[inline(always)]
318    pub fn clo(
319        self,
320    ) -> crate::common::RegisterField<
321        5,
322        0x1,
323        1,
324        0,
325        iccr1::Clo,
326        iccr1::Clo,
327        Iccr1_SPEC,
328        crate::common::RW,
329    > {
330        crate::common::RegisterField::<
331            5,
332            0x1,
333            1,
334            0,
335            iccr1::Clo,
336            iccr1::Clo,
337            Iccr1_SPEC,
338            crate::common::RW,
339        >::from_register(self, 0)
340    }
341
342    #[doc = "SCLO/SDAO Write Protect"]
343    #[inline(always)]
344    pub fn sowp(
345        self,
346    ) -> crate::common::RegisterField<
347        4,
348        0x1,
349        1,
350        0,
351        iccr1::Sowp,
352        iccr1::Sowp,
353        Iccr1_SPEC,
354        crate::common::W,
355    > {
356        crate::common::RegisterField::<
357            4,
358            0x1,
359            1,
360            0,
361            iccr1::Sowp,
362            iccr1::Sowp,
363            Iccr1_SPEC,
364            crate::common::W,
365        >::from_register(self, 0)
366    }
367
368    #[doc = "SCL Output Control/Monitor"]
369    #[inline(always)]
370    pub fn sclo(
371        self,
372    ) -> crate::common::RegisterField<
373        3,
374        0x1,
375        1,
376        0,
377        iccr1::Sclo,
378        iccr1::Sclo,
379        Iccr1_SPEC,
380        crate::common::RW,
381    > {
382        crate::common::RegisterField::<
383            3,
384            0x1,
385            1,
386            0,
387            iccr1::Sclo,
388            iccr1::Sclo,
389            Iccr1_SPEC,
390            crate::common::RW,
391        >::from_register(self, 0)
392    }
393
394    #[doc = "SDA Output Control/Monitor"]
395    #[inline(always)]
396    pub fn sdao(
397        self,
398    ) -> crate::common::RegisterField<
399        2,
400        0x1,
401        1,
402        0,
403        iccr1::Sdao,
404        iccr1::Sdao,
405        Iccr1_SPEC,
406        crate::common::RW,
407    > {
408        crate::common::RegisterField::<
409            2,
410            0x1,
411            1,
412            0,
413            iccr1::Sdao,
414            iccr1::Sdao,
415            Iccr1_SPEC,
416            crate::common::RW,
417        >::from_register(self, 0)
418    }
419
420    #[doc = "SCL Line Monitor"]
421    #[inline(always)]
422    pub fn scli(
423        self,
424    ) -> crate::common::RegisterField<
425        1,
426        0x1,
427        1,
428        0,
429        iccr1::Scli,
430        iccr1::Scli,
431        Iccr1_SPEC,
432        crate::common::R,
433    > {
434        crate::common::RegisterField::<
435            1,
436            0x1,
437            1,
438            0,
439            iccr1::Scli,
440            iccr1::Scli,
441            Iccr1_SPEC,
442            crate::common::R,
443        >::from_register(self, 0)
444    }
445
446    #[doc = "SDA Line Monitor"]
447    #[inline(always)]
448    pub fn sdai(
449        self,
450    ) -> crate::common::RegisterField<
451        0,
452        0x1,
453        1,
454        0,
455        iccr1::Sdai,
456        iccr1::Sdai,
457        Iccr1_SPEC,
458        crate::common::R,
459    > {
460        crate::common::RegisterField::<
461            0,
462            0x1,
463            1,
464            0,
465            iccr1::Sdai,
466            iccr1::Sdai,
467            Iccr1_SPEC,
468            crate::common::R,
469        >::from_register(self, 0)
470    }
471}
472impl ::core::default::Default for Iccr1 {
473    #[inline(always)]
474    fn default() -> Iccr1 {
475        <crate::RegValueT<Iccr1_SPEC> as RegisterValue<_>>::new(31)
476    }
477}
478pub mod iccr1 {
479
480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
481    pub struct Ice_SPEC;
482    pub type Ice = crate::EnumBitfieldStruct<u8, Ice_SPEC>;
483    impl Ice {
484        #[doc = "Disable (SCLn and SDAn pins in inactive state)"]
485        pub const _0: Self = Self::new(0);
486
487        #[doc = "Enable (SCLn and SDAn pins in active state)"]
488        pub const _1: Self = Self::new(1);
489    }
490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
491    pub struct Iicrst_SPEC;
492    pub type Iicrst = crate::EnumBitfieldStruct<u8, Iicrst_SPEC>;
493    impl Iicrst {
494        #[doc = "Releases the RIIC reset or internal reset."]
495        pub const _0: Self = Self::new(0);
496
497        #[doc = "Initiates the RIIC reset or internal reset."]
498        pub const _1: Self = Self::new(1);
499    }
500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
501    pub struct Clo_SPEC;
502    pub type Clo = crate::EnumBitfieldStruct<u8, Clo_SPEC>;
503    impl Clo {
504        #[doc = "Does not output an extra SCL clock cycle."]
505        pub const _0: Self = Self::new(0);
506
507        #[doc = "Outputs an extra SCL clock cycle."]
508        pub const _1: Self = Self::new(1);
509    }
510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
511    pub struct Sowp_SPEC;
512    pub type Sowp = crate::EnumBitfieldStruct<u8, Sowp_SPEC>;
513    impl Sowp {
514        #[doc = "Bits SCLO and SDAO can be written."]
515        pub const _0: Self = Self::new(0);
516
517        #[doc = "Bits SCLO and SDAO are protected."]
518        pub const _1: Self = Self::new(1);
519    }
520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
521    pub struct Sclo_SPEC;
522    pub type Sclo = crate::EnumBitfieldStruct<u8, Sclo_SPEC>;
523    impl Sclo {
524        #[doc = "(Read)The RIIC has driven the SCLn pin low. / (Write)The RIIC drives the SCLn pin low."]
525        pub const _0: Self = Self::new(0);
526
527        #[doc = "(Read)The RIIC has released the SCLn pin. / (Write)The RIIC releases the SCLn pin."]
528        pub const _1: Self = Self::new(1);
529    }
530    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
531    pub struct Sdao_SPEC;
532    pub type Sdao = crate::EnumBitfieldStruct<u8, Sdao_SPEC>;
533    impl Sdao {
534        #[doc = "(Read)The RIIC has driven the SDAn pin low. / (Write)The RIIC drives the SDAn pin low."]
535        pub const _0: Self = Self::new(0);
536
537        #[doc = "(Read)The RIIC has released the SDAn pin./  (Write)The RIIC releases the SDAn pin."]
538        pub const _1: Self = Self::new(1);
539    }
540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
541    pub struct Scli_SPEC;
542    pub type Scli = crate::EnumBitfieldStruct<u8, Scli_SPEC>;
543    impl Scli {
544        #[doc = "SCLn line is low."]
545        pub const _0: Self = Self::new(0);
546
547        #[doc = "SCLn line is high."]
548        pub const _1: Self = Self::new(1);
549    }
550    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
551    pub struct Sdai_SPEC;
552    pub type Sdai = crate::EnumBitfieldStruct<u8, Sdai_SPEC>;
553    impl Sdai {
554        #[doc = "SDAn line is low."]
555        pub const _0: Self = Self::new(0);
556
557        #[doc = "SDAn line is high."]
558        pub const _1: Self = Self::new(1);
559    }
560}
561#[doc(hidden)]
562#[derive(Copy, Clone, Eq, PartialEq)]
563pub struct Iccr2_SPEC;
564impl crate::sealed::RegSpec for Iccr2_SPEC {
565    type DataType = u8;
566}
567
568#[doc = "I2C Bus Control Register 2"]
569pub type Iccr2 = crate::RegValueT<Iccr2_SPEC>;
570
571impl Iccr2 {
572    #[doc = "Bus Busy Detection Flag"]
573    #[inline(always)]
574    pub fn bbsy(
575        self,
576    ) -> crate::common::RegisterField<
577        7,
578        0x1,
579        1,
580        0,
581        iccr2::Bbsy,
582        iccr2::Bbsy,
583        Iccr2_SPEC,
584        crate::common::R,
585    > {
586        crate::common::RegisterField::<
587            7,
588            0x1,
589            1,
590            0,
591            iccr2::Bbsy,
592            iccr2::Bbsy,
593            Iccr2_SPEC,
594            crate::common::R,
595        >::from_register(self, 0)
596    }
597
598    #[doc = "Master/Slave Mode"]
599    #[inline(always)]
600    pub fn mst(
601        self,
602    ) -> crate::common::RegisterField<
603        6,
604        0x1,
605        1,
606        0,
607        iccr2::Mst,
608        iccr2::Mst,
609        Iccr2_SPEC,
610        crate::common::RW,
611    > {
612        crate::common::RegisterField::<
613            6,
614            0x1,
615            1,
616            0,
617            iccr2::Mst,
618            iccr2::Mst,
619            Iccr2_SPEC,
620            crate::common::RW,
621        >::from_register(self, 0)
622    }
623
624    #[doc = "Transmit/Receive Mode"]
625    #[inline(always)]
626    pub fn trs(
627        self,
628    ) -> crate::common::RegisterField<
629        5,
630        0x1,
631        1,
632        0,
633        iccr2::Trs,
634        iccr2::Trs,
635        Iccr2_SPEC,
636        crate::common::RW,
637    > {
638        crate::common::RegisterField::<
639            5,
640            0x1,
641            1,
642            0,
643            iccr2::Trs,
644            iccr2::Trs,
645            Iccr2_SPEC,
646            crate::common::RW,
647        >::from_register(self, 0)
648    }
649
650    #[doc = "Stop Condition Issuance RequestNote: Writing to the SP bit is not possible while the setting of the BBSY flag is 0 (bus free state).Note: Do not set the SP bit to 1 while a restart condition is being issued."]
651    #[inline(always)]
652    pub fn sp(
653        self,
654    ) -> crate::common::RegisterField<
655        3,
656        0x1,
657        1,
658        0,
659        iccr2::Sp,
660        iccr2::Sp,
661        Iccr2_SPEC,
662        crate::common::RW,
663    > {
664        crate::common::RegisterField::<
665            3,
666            0x1,
667            1,
668            0,
669            iccr2::Sp,
670            iccr2::Sp,
671            Iccr2_SPEC,
672            crate::common::RW,
673        >::from_register(self, 0)
674    }
675
676    #[doc = "Restart Condition Issuance RequestNote: Do not set the RS bit to 1 while issuing a stop condition."]
677    #[inline(always)]
678    pub fn rs(
679        self,
680    ) -> crate::common::RegisterField<
681        2,
682        0x1,
683        1,
684        0,
685        iccr2::Rs,
686        iccr2::Rs,
687        Iccr2_SPEC,
688        crate::common::RW,
689    > {
690        crate::common::RegisterField::<
691            2,
692            0x1,
693            1,
694            0,
695            iccr2::Rs,
696            iccr2::Rs,
697            Iccr2_SPEC,
698            crate::common::RW,
699        >::from_register(self, 0)
700    }
701
702    #[doc = "Start Condition Issuance RequestSet the ST bit to 1 (start condition issuance request) when the BBSY flag is set to 0 (bus free state)."]
703    #[inline(always)]
704    pub fn st(
705        self,
706    ) -> crate::common::RegisterField<
707        1,
708        0x1,
709        1,
710        0,
711        iccr2::St,
712        iccr2::St,
713        Iccr2_SPEC,
714        crate::common::RW,
715    > {
716        crate::common::RegisterField::<
717            1,
718            0x1,
719            1,
720            0,
721            iccr2::St,
722            iccr2::St,
723            Iccr2_SPEC,
724            crate::common::RW,
725        >::from_register(self, 0)
726    }
727
728    #[doc = "This bit is read as 0. The write value should be 0."]
729    #[inline(always)]
730    pub fn reserved(
731        self,
732    ) -> crate::common::RegisterFieldBool<0, 1, 0, Iccr2_SPEC, crate::common::RW> {
733        crate::common::RegisterFieldBool::<0, 1, 0, Iccr2_SPEC, crate::common::RW>::from_register(
734            self, 0,
735        )
736    }
737}
738impl ::core::default::Default for Iccr2 {
739    #[inline(always)]
740    fn default() -> Iccr2 {
741        <crate::RegValueT<Iccr2_SPEC> as RegisterValue<_>>::new(0)
742    }
743}
744pub mod iccr2 {
745
746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
747    pub struct Bbsy_SPEC;
748    pub type Bbsy = crate::EnumBitfieldStruct<u8, Bbsy_SPEC>;
749    impl Bbsy {
750        #[doc = "The I2C bus is released (bus free state)."]
751        pub const _0: Self = Self::new(0);
752
753        #[doc = "The I2C bus is occupied (bus busy state)."]
754        pub const _1: Self = Self::new(1);
755    }
756    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
757    pub struct Mst_SPEC;
758    pub type Mst = crate::EnumBitfieldStruct<u8, Mst_SPEC>;
759    impl Mst {
760        #[doc = "Slave mode"]
761        pub const _0: Self = Self::new(0);
762
763        #[doc = "Master mode"]
764        pub const _1: Self = Self::new(1);
765    }
766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
767    pub struct Trs_SPEC;
768    pub type Trs = crate::EnumBitfieldStruct<u8, Trs_SPEC>;
769    impl Trs {
770        #[doc = "Receive mode"]
771        pub const _0: Self = Self::new(0);
772
773        #[doc = "Transmit mode"]
774        pub const _1: Self = Self::new(1);
775    }
776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
777    pub struct Sp_SPEC;
778    pub type Sp = crate::EnumBitfieldStruct<u8, Sp_SPEC>;
779    impl Sp {
780        #[doc = "Does not request to issue a stop condition."]
781        pub const _0: Self = Self::new(0);
782
783        #[doc = "Requests to issue a stop condition."]
784        pub const _1: Self = Self::new(1);
785    }
786    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
787    pub struct Rs_SPEC;
788    pub type Rs = crate::EnumBitfieldStruct<u8, Rs_SPEC>;
789    impl Rs {
790        #[doc = "Does not request to issue a restart condition."]
791        pub const _0: Self = Self::new(0);
792
793        #[doc = "Requests to issue a restart condition."]
794        pub const _1: Self = Self::new(1);
795    }
796    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
797    pub struct St_SPEC;
798    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
799    impl St {
800        #[doc = "Does not request to issue a start condition."]
801        pub const _0: Self = Self::new(0);
802
803        #[doc = "Requests to issue a start condition."]
804        pub const _1: Self = Self::new(1);
805    }
806}
807#[doc(hidden)]
808#[derive(Copy, Clone, Eq, PartialEq)]
809pub struct Icmr1_SPEC;
810impl crate::sealed::RegSpec for Icmr1_SPEC {
811    type DataType = u8;
812}
813
814#[doc = "I2C Bus Mode Register 1"]
815pub type Icmr1 = crate::RegValueT<Icmr1_SPEC>;
816
817impl Icmr1 {
818    #[doc = "MST/TRS Write Protect"]
819    #[inline(always)]
820    pub fn mtwp(
821        self,
822    ) -> crate::common::RegisterField<
823        7,
824        0x1,
825        1,
826        0,
827        icmr1::Mtwp,
828        icmr1::Mtwp,
829        Icmr1_SPEC,
830        crate::common::RW,
831    > {
832        crate::common::RegisterField::<
833            7,
834            0x1,
835            1,
836            0,
837            icmr1::Mtwp,
838            icmr1::Mtwp,
839            Icmr1_SPEC,
840            crate::common::RW,
841        >::from_register(self, 0)
842    }
843
844    #[doc = "Internal Reference Clock (fIIC) Selection ( fIIC = PCLKB / 2^CKS )"]
845    #[inline(always)]
846    pub fn cks(
847        self,
848    ) -> crate::common::RegisterField<
849        4,
850        0x7,
851        1,
852        0,
853        icmr1::Cks,
854        icmr1::Cks,
855        Icmr1_SPEC,
856        crate::common::RW,
857    > {
858        crate::common::RegisterField::<
859            4,
860            0x7,
861            1,
862            0,
863            icmr1::Cks,
864            icmr1::Cks,
865            Icmr1_SPEC,
866            crate::common::RW,
867        >::from_register(self, 0)
868    }
869
870    #[doc = "BC Write Protect(This bit is read as 1.)"]
871    #[inline(always)]
872    pub fn bcwp(
873        self,
874    ) -> crate::common::RegisterField<
875        3,
876        0x1,
877        1,
878        0,
879        icmr1::Bcwp,
880        icmr1::Bcwp,
881        Icmr1_SPEC,
882        crate::common::W,
883    > {
884        crate::common::RegisterField::<
885            3,
886            0x1,
887            1,
888            0,
889            icmr1::Bcwp,
890            icmr1::Bcwp,
891            Icmr1_SPEC,
892            crate::common::W,
893        >::from_register(self, 0)
894    }
895
896    #[doc = "Bit Counter"]
897    #[inline(always)]
898    pub fn bc(
899        self,
900    ) -> crate::common::RegisterField<
901        0,
902        0x7,
903        1,
904        0,
905        icmr1::Bc,
906        icmr1::Bc,
907        Icmr1_SPEC,
908        crate::common::RW,
909    > {
910        crate::common::RegisterField::<
911            0,
912            0x7,
913            1,
914            0,
915            icmr1::Bc,
916            icmr1::Bc,
917            Icmr1_SPEC,
918            crate::common::RW,
919        >::from_register(self, 0)
920    }
921}
922impl ::core::default::Default for Icmr1 {
923    #[inline(always)]
924    fn default() -> Icmr1 {
925        <crate::RegValueT<Icmr1_SPEC> as RegisterValue<_>>::new(8)
926    }
927}
928pub mod icmr1 {
929
930    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
931    pub struct Mtwp_SPEC;
932    pub type Mtwp = crate::EnumBitfieldStruct<u8, Mtwp_SPEC>;
933    impl Mtwp {
934        #[doc = "Disables writing to the MST and TRS bits in ICCR2."]
935        pub const _0: Self = Self::new(0);
936
937        #[doc = "Enables writing to the MST and TRS bits in ICCR2."]
938        pub const _1: Self = Self::new(1);
939    }
940    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
941    pub struct Cks_SPEC;
942    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
943    impl Cks {
944        #[doc = "PCLKB/1 clock"]
945        pub const _000: Self = Self::new(0);
946
947        #[doc = "PCLKB/2 clock"]
948        pub const _001: Self = Self::new(1);
949
950        #[doc = "PCLKB/4 clock"]
951        pub const _010: Self = Self::new(2);
952
953        #[doc = "PCLKB/8 clock"]
954        pub const _011: Self = Self::new(3);
955
956        #[doc = "PCLKB/16 clock"]
957        pub const _100: Self = Self::new(4);
958
959        #[doc = "PCLKB/32 clock"]
960        pub const _101: Self = Self::new(5);
961
962        #[doc = "PCLKB/64 clock"]
963        pub const _110: Self = Self::new(6);
964
965        #[doc = "PCLKB/128 clock"]
966        pub const _111: Self = Self::new(7);
967    }
968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
969    pub struct Bcwp_SPEC;
970    pub type Bcwp = crate::EnumBitfieldStruct<u8, Bcwp_SPEC>;
971    impl Bcwp {
972        #[doc = "Enables a value to be written in the BC\\[2:0\\] bits."]
973        pub const _0: Self = Self::new(0);
974
975        #[doc = "Disables a value to be written in the BC\\[2:0\\] bits."]
976        pub const _1: Self = Self::new(1);
977    }
978    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
979    pub struct Bc_SPEC;
980    pub type Bc = crate::EnumBitfieldStruct<u8, Bc_SPEC>;
981    impl Bc {
982        #[doc = "9 bits"]
983        pub const _000: Self = Self::new(0);
984
985        #[doc = "2 bits"]
986        pub const _001: Self = Self::new(1);
987
988        #[doc = "3 bits"]
989        pub const _010: Self = Self::new(2);
990
991        #[doc = "4 bits"]
992        pub const _011: Self = Self::new(3);
993
994        #[doc = "5 bits"]
995        pub const _100: Self = Self::new(4);
996
997        #[doc = "6 bits"]
998        pub const _101: Self = Self::new(5);
999
1000        #[doc = "7 bits"]
1001        pub const _110: Self = Self::new(6);
1002
1003        #[doc = "8 bits"]
1004        pub const _111: Self = Self::new(7);
1005    }
1006}
1007#[doc(hidden)]
1008#[derive(Copy, Clone, Eq, PartialEq)]
1009pub struct Icmr2_SPEC;
1010impl crate::sealed::RegSpec for Icmr2_SPEC {
1011    type DataType = u8;
1012}
1013
1014#[doc = "I2C Bus Mode Register 2"]
1015pub type Icmr2 = crate::RegValueT<Icmr2_SPEC>;
1016
1017impl Icmr2 {
1018    #[doc = "SDA Output Delay Clock Source Selection"]
1019    #[inline(always)]
1020    pub fn dlcs(
1021        self,
1022    ) -> crate::common::RegisterField<
1023        7,
1024        0x1,
1025        1,
1026        0,
1027        icmr2::Dlcs,
1028        icmr2::Dlcs,
1029        Icmr2_SPEC,
1030        crate::common::RW,
1031    > {
1032        crate::common::RegisterField::<
1033            7,
1034            0x1,
1035            1,
1036            0,
1037            icmr2::Dlcs,
1038            icmr2::Dlcs,
1039            Icmr2_SPEC,
1040            crate::common::RW,
1041        >::from_register(self, 0)
1042    }
1043
1044    #[doc = "SDA Output Delay Counter"]
1045    #[inline(always)]
1046    pub fn sddl(
1047        self,
1048    ) -> crate::common::RegisterField<
1049        4,
1050        0x7,
1051        1,
1052        0,
1053        icmr2::Sddl,
1054        icmr2::Sddl,
1055        Icmr2_SPEC,
1056        crate::common::RW,
1057    > {
1058        crate::common::RegisterField::<
1059            4,
1060            0x7,
1061            1,
1062            0,
1063            icmr2::Sddl,
1064            icmr2::Sddl,
1065            Icmr2_SPEC,
1066            crate::common::RW,
1067        >::from_register(self, 0)
1068    }
1069
1070    #[doc = "This bit is read as 0. The write value should be 0."]
1071    #[inline(always)]
1072    pub fn reserved(
1073        self,
1074    ) -> crate::common::RegisterFieldBool<3, 1, 0, Icmr2_SPEC, crate::common::RW> {
1075        crate::common::RegisterFieldBool::<3, 1, 0, Icmr2_SPEC, crate::common::RW>::from_register(
1076            self, 0,
1077        )
1078    }
1079
1080    #[doc = "Timeout H Count Control"]
1081    #[inline(always)]
1082    pub fn tmoh(
1083        self,
1084    ) -> crate::common::RegisterField<
1085        2,
1086        0x1,
1087        1,
1088        0,
1089        icmr2::Tmoh,
1090        icmr2::Tmoh,
1091        Icmr2_SPEC,
1092        crate::common::RW,
1093    > {
1094        crate::common::RegisterField::<
1095            2,
1096            0x1,
1097            1,
1098            0,
1099            icmr2::Tmoh,
1100            icmr2::Tmoh,
1101            Icmr2_SPEC,
1102            crate::common::RW,
1103        >::from_register(self, 0)
1104    }
1105
1106    #[doc = "Timeout L Count Control"]
1107    #[inline(always)]
1108    pub fn tmol(
1109        self,
1110    ) -> crate::common::RegisterField<
1111        1,
1112        0x1,
1113        1,
1114        0,
1115        icmr2::Tmol,
1116        icmr2::Tmol,
1117        Icmr2_SPEC,
1118        crate::common::RW,
1119    > {
1120        crate::common::RegisterField::<
1121            1,
1122            0x1,
1123            1,
1124            0,
1125            icmr2::Tmol,
1126            icmr2::Tmol,
1127            Icmr2_SPEC,
1128            crate::common::RW,
1129        >::from_register(self, 0)
1130    }
1131
1132    #[doc = "Timeout Detection Time Selection"]
1133    #[inline(always)]
1134    pub fn tmos(
1135        self,
1136    ) -> crate::common::RegisterField<
1137        0,
1138        0x1,
1139        1,
1140        0,
1141        icmr2::Tmos,
1142        icmr2::Tmos,
1143        Icmr2_SPEC,
1144        crate::common::RW,
1145    > {
1146        crate::common::RegisterField::<
1147            0,
1148            0x1,
1149            1,
1150            0,
1151            icmr2::Tmos,
1152            icmr2::Tmos,
1153            Icmr2_SPEC,
1154            crate::common::RW,
1155        >::from_register(self, 0)
1156    }
1157}
1158impl ::core::default::Default for Icmr2 {
1159    #[inline(always)]
1160    fn default() -> Icmr2 {
1161        <crate::RegValueT<Icmr2_SPEC> as RegisterValue<_>>::new(6)
1162    }
1163}
1164pub mod icmr2 {
1165
1166    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1167    pub struct Dlcs_SPEC;
1168    pub type Dlcs = crate::EnumBitfieldStruct<u8, Dlcs_SPEC>;
1169    impl Dlcs {
1170        #[doc = "The internal reference clock (fIIC) is selected as the clock source of the SDA output delay counter."]
1171        pub const _0: Self = Self::new(0);
1172
1173        #[doc = "The internal reference clock divided by 2 (fIIC/2) is selected as the clock source of the SDA output delay counter."]
1174        pub const _1: Self = Self::new(1);
1175    }
1176    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1177    pub struct Sddl_SPEC;
1178    pub type Sddl = crate::EnumBitfieldStruct<u8, Sddl_SPEC>;
1179    impl Sddl {
1180        #[doc = "No output delay"]
1181        pub const _000: Self = Self::new(0);
1182
1183        #[doc = "1 fIIC cycle  (ICMR2.DLCS=0) / 1  or 2 fIIC cycles (ICMR2.DLCS=1)"]
1184        pub const _001: Self = Self::new(1);
1185
1186        #[doc = "2 fIIC cycles (ICMR2.DLCS=0) /  3 or 4 fIIC cycles (ICMR2.DLCS=1)"]
1187        pub const _010: Self = Self::new(2);
1188
1189        #[doc = "3 fIIC cycles (ICMR2.DLCS=0) /  5 or 6 fIIC cycles (ICMR2.DLCS=1)"]
1190        pub const _011: Self = Self::new(3);
1191
1192        #[doc = "4 fIIC cycles (ICMR2.DLCS=0) /  7 or 8 fIIC cycles (ICMR2.DLCS=1)"]
1193        pub const _100: Self = Self::new(4);
1194
1195        #[doc = "5 fIIC cycles (ICMR2.DLCS=0) /  9 or 10 fIIC cycles (ICMR2.DLCS=1)"]
1196        pub const _101: Self = Self::new(5);
1197
1198        #[doc = "6 fIIC cycles (ICMR2.DLCS=0) / 11 or 12 fIIC cycles (ICMR2.DLCS=1)"]
1199        pub const _110: Self = Self::new(6);
1200
1201        #[doc = "7 fIIC cycles (ICMR2.DLCS=0) / 13 or 14 fIIC cycles (ICMR2.DLCS=1)"]
1202        pub const _111: Self = Self::new(7);
1203    }
1204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1205    pub struct Tmoh_SPEC;
1206    pub type Tmoh = crate::EnumBitfieldStruct<u8, Tmoh_SPEC>;
1207    impl Tmoh {
1208        #[doc = "Count is disabled while the SCLn line is at a high level."]
1209        pub const _0: Self = Self::new(0);
1210
1211        #[doc = "Count is enabled while the SCLn line is at a high level."]
1212        pub const _1: Self = Self::new(1);
1213    }
1214    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1215    pub struct Tmol_SPEC;
1216    pub type Tmol = crate::EnumBitfieldStruct<u8, Tmol_SPEC>;
1217    impl Tmol {
1218        #[doc = "Count is disabled while the SCLn line is at a low level."]
1219        pub const _0: Self = Self::new(0);
1220
1221        #[doc = "Count is enabled while the SCLn line is at a low level."]
1222        pub const _1: Self = Self::new(1);
1223    }
1224    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1225    pub struct Tmos_SPEC;
1226    pub type Tmos = crate::EnumBitfieldStruct<u8, Tmos_SPEC>;
1227    impl Tmos {
1228        #[doc = "Long mode is selected."]
1229        pub const _0: Self = Self::new(0);
1230
1231        #[doc = "Short mode is selected."]
1232        pub const _1: Self = Self::new(1);
1233    }
1234}
1235#[doc(hidden)]
1236#[derive(Copy, Clone, Eq, PartialEq)]
1237pub struct Icmr3_SPEC;
1238impl crate::sealed::RegSpec for Icmr3_SPEC {
1239    type DataType = u8;
1240}
1241
1242#[doc = "I2C Bus Mode Register 3"]
1243pub type Icmr3 = crate::RegValueT<Icmr3_SPEC>;
1244
1245impl Icmr3 {
1246    #[doc = "SMBus/I2C Bus Selection"]
1247    #[inline(always)]
1248    pub fn smbe(
1249        self,
1250    ) -> crate::common::RegisterField<
1251        7,
1252        0x1,
1253        1,
1254        0,
1255        icmr3::Smbe,
1256        icmr3::Smbe,
1257        Icmr3_SPEC,
1258        crate::common::RW,
1259    > {
1260        crate::common::RegisterField::<
1261            7,
1262            0x1,
1263            1,
1264            0,
1265            icmr3::Smbe,
1266            icmr3::Smbe,
1267            Icmr3_SPEC,
1268            crate::common::RW,
1269        >::from_register(self, 0)
1270    }
1271
1272    #[doc = "WAITNote: When the value of the WAIT bit is to be read, be sure to read the ICDRR beforehand."]
1273    #[inline(always)]
1274    pub fn wait(
1275        self,
1276    ) -> crate::common::RegisterField<
1277        6,
1278        0x1,
1279        1,
1280        0,
1281        icmr3::Wait,
1282        icmr3::Wait,
1283        Icmr3_SPEC,
1284        crate::common::RW,
1285    > {
1286        crate::common::RegisterField::<
1287            6,
1288            0x1,
1289            1,
1290            0,
1291            icmr3::Wait,
1292            icmr3::Wait,
1293            Icmr3_SPEC,
1294            crate::common::RW,
1295        >::from_register(self, 0)
1296    }
1297
1298    #[doc = "RDRF Flag Set Timing Selection"]
1299    #[inline(always)]
1300    pub fn rdrfs(
1301        self,
1302    ) -> crate::common::RegisterField<
1303        5,
1304        0x1,
1305        1,
1306        0,
1307        icmr3::Rdrfs,
1308        icmr3::Rdrfs,
1309        Icmr3_SPEC,
1310        crate::common::RW,
1311    > {
1312        crate::common::RegisterField::<
1313            5,
1314            0x1,
1315            1,
1316            0,
1317            icmr3::Rdrfs,
1318            icmr3::Rdrfs,
1319            Icmr3_SPEC,
1320            crate::common::RW,
1321        >::from_register(self, 0)
1322    }
1323
1324    #[doc = "ACKBT Write Protect"]
1325    #[inline(always)]
1326    pub fn ackwp(
1327        self,
1328    ) -> crate::common::RegisterField<
1329        4,
1330        0x1,
1331        1,
1332        0,
1333        icmr3::Ackwp,
1334        icmr3::Ackwp,
1335        Icmr3_SPEC,
1336        crate::common::RW,
1337    > {
1338        crate::common::RegisterField::<
1339            4,
1340            0x1,
1341            1,
1342            0,
1343            icmr3::Ackwp,
1344            icmr3::Ackwp,
1345            Icmr3_SPEC,
1346            crate::common::RW,
1347        >::from_register(self, 0)
1348    }
1349
1350    #[doc = "Transmit Acknowledge"]
1351    #[inline(always)]
1352    pub fn ackbt(
1353        self,
1354    ) -> crate::common::RegisterField<
1355        3,
1356        0x1,
1357        1,
1358        0,
1359        icmr3::Ackbt,
1360        icmr3::Ackbt,
1361        Icmr3_SPEC,
1362        crate::common::RW,
1363    > {
1364        crate::common::RegisterField::<
1365            3,
1366            0x1,
1367            1,
1368            0,
1369            icmr3::Ackbt,
1370            icmr3::Ackbt,
1371            Icmr3_SPEC,
1372            crate::common::RW,
1373        >::from_register(self, 0)
1374    }
1375
1376    #[doc = "Receive Acknowledge"]
1377    #[inline(always)]
1378    pub fn ackbr(
1379        self,
1380    ) -> crate::common::RegisterField<
1381        2,
1382        0x1,
1383        1,
1384        0,
1385        icmr3::Ackbr,
1386        icmr3::Ackbr,
1387        Icmr3_SPEC,
1388        crate::common::R,
1389    > {
1390        crate::common::RegisterField::<
1391            2,
1392            0x1,
1393            1,
1394            0,
1395            icmr3::Ackbr,
1396            icmr3::Ackbr,
1397            Icmr3_SPEC,
1398            crate::common::R,
1399        >::from_register(self, 0)
1400    }
1401
1402    #[doc = "Noise Filter Stage Selection"]
1403    #[inline(always)]
1404    pub fn nf(
1405        self,
1406    ) -> crate::common::RegisterField<
1407        0,
1408        0x3,
1409        1,
1410        0,
1411        icmr3::Nf,
1412        icmr3::Nf,
1413        Icmr3_SPEC,
1414        crate::common::RW,
1415    > {
1416        crate::common::RegisterField::<
1417            0,
1418            0x3,
1419            1,
1420            0,
1421            icmr3::Nf,
1422            icmr3::Nf,
1423            Icmr3_SPEC,
1424            crate::common::RW,
1425        >::from_register(self, 0)
1426    }
1427}
1428impl ::core::default::Default for Icmr3 {
1429    #[inline(always)]
1430    fn default() -> Icmr3 {
1431        <crate::RegValueT<Icmr3_SPEC> as RegisterValue<_>>::new(0)
1432    }
1433}
1434pub mod icmr3 {
1435
1436    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1437    pub struct Smbe_SPEC;
1438    pub type Smbe = crate::EnumBitfieldStruct<u8, Smbe_SPEC>;
1439    impl Smbe {
1440        #[doc = "The I2C bus is selected."]
1441        pub const _0: Self = Self::new(0);
1442
1443        #[doc = "The SMBus is selected."]
1444        pub const _1: Self = Self::new(1);
1445    }
1446    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1447    pub struct Wait_SPEC;
1448    pub type Wait = crate::EnumBitfieldStruct<u8, Wait_SPEC>;
1449    impl Wait {
1450        #[doc = "No WAIT (The period between ninth clock cycle and first clock cycle is not held low.)"]
1451        pub const _0: Self = Self::new(0);
1452
1453        #[doc = "WAIT (The period between ninth clock cycle and first clock cycle is held low.)"]
1454        pub const _1: Self = Self::new(1);
1455    }
1456    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1457    pub struct Rdrfs_SPEC;
1458    pub type Rdrfs = crate::EnumBitfieldStruct<u8, Rdrfs_SPEC>;
1459    impl Rdrfs {
1460        #[doc = "The RDRF flag is set at the rising edge of the ninth SCL clock cycle. (The SCLn line is not held low at the falling edge of the eighth clock cycle.)"]
1461        pub const _0: Self = Self::new(0);
1462
1463        #[doc = "The RDRF flag is set at the rising edge of the eighth SCL clock cycle. (The SCLn line is held low at the falling edge of the eighth clock cycle.)"]
1464        pub const _1: Self = Self::new(1);
1465    }
1466    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1467    pub struct Ackwp_SPEC;
1468    pub type Ackwp = crate::EnumBitfieldStruct<u8, Ackwp_SPEC>;
1469    impl Ackwp {
1470        #[doc = "Modification of the ACKBT bit is disabled."]
1471        pub const _0: Self = Self::new(0);
1472
1473        #[doc = "Modification of the ACKBT bit is enabled."]
1474        pub const _1: Self = Self::new(1);
1475    }
1476    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1477    pub struct Ackbt_SPEC;
1478    pub type Ackbt = crate::EnumBitfieldStruct<u8, Ackbt_SPEC>;
1479    impl Ackbt {
1480        #[doc = "A 0 is sent as the acknowledge bit (ACK transmission)."]
1481        pub const _0: Self = Self::new(0);
1482
1483        #[doc = "A 1 is sent as the acknowledge bit (NACK transmission)."]
1484        pub const _1: Self = Self::new(1);
1485    }
1486    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1487    pub struct Ackbr_SPEC;
1488    pub type Ackbr = crate::EnumBitfieldStruct<u8, Ackbr_SPEC>;
1489    impl Ackbr {
1490        #[doc = "A 0 is received as the acknowledge bit (ACK reception)."]
1491        pub const _0: Self = Self::new(0);
1492
1493        #[doc = "A 1 is received as the acknowledge bit (NACK reception)."]
1494        pub const _1: Self = Self::new(1);
1495    }
1496    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1497    pub struct Nf_SPEC;
1498    pub type Nf = crate::EnumBitfieldStruct<u8, Nf_SPEC>;
1499    impl Nf {
1500        #[doc = "Noise of up to one IIC cycle is filtered out (single-stage filter)."]
1501        pub const _00: Self = Self::new(0);
1502
1503        #[doc = "Noise of up to two IIC cycles is filtered out (2-stage filter)."]
1504        pub const _01: Self = Self::new(1);
1505
1506        #[doc = "Noise of up to three IIC cycles is filtered out (3-stage filter)."]
1507        pub const _10: Self = Self::new(2);
1508
1509        #[doc = "Noise of up to four IIC cycles is filtered out (4-stage filter)"]
1510        pub const _11: Self = Self::new(3);
1511    }
1512}
1513#[doc(hidden)]
1514#[derive(Copy, Clone, Eq, PartialEq)]
1515pub struct Icfer_SPEC;
1516impl crate::sealed::RegSpec for Icfer_SPEC {
1517    type DataType = u8;
1518}
1519
1520#[doc = "I2C Bus Function Enable Register"]
1521pub type Icfer = crate::RegValueT<Icfer_SPEC>;
1522
1523impl Icfer {
1524    #[doc = "This bit is read as 0. The write value should be 0."]
1525    #[inline(always)]
1526    pub fn reserved(
1527        self,
1528    ) -> crate::common::RegisterFieldBool<7, 1, 0, Icfer_SPEC, crate::common::RW> {
1529        crate::common::RegisterFieldBool::<7, 1, 0, Icfer_SPEC, crate::common::RW>::from_register(
1530            self, 0,
1531        )
1532    }
1533
1534    #[doc = "SCL Synchronous Circuit Enable"]
1535    #[inline(always)]
1536    pub fn scle(
1537        self,
1538    ) -> crate::common::RegisterField<
1539        6,
1540        0x1,
1541        1,
1542        0,
1543        icfer::Scle,
1544        icfer::Scle,
1545        Icfer_SPEC,
1546        crate::common::RW,
1547    > {
1548        crate::common::RegisterField::<
1549            6,
1550            0x1,
1551            1,
1552            0,
1553            icfer::Scle,
1554            icfer::Scle,
1555            Icfer_SPEC,
1556            crate::common::RW,
1557        >::from_register(self, 0)
1558    }
1559
1560    #[doc = "Digital Noise Filter Circuit Enable"]
1561    #[inline(always)]
1562    pub fn nfe(
1563        self,
1564    ) -> crate::common::RegisterField<
1565        5,
1566        0x1,
1567        1,
1568        0,
1569        icfer::Nfe,
1570        icfer::Nfe,
1571        Icfer_SPEC,
1572        crate::common::RW,
1573    > {
1574        crate::common::RegisterField::<
1575            5,
1576            0x1,
1577            1,
1578            0,
1579            icfer::Nfe,
1580            icfer::Nfe,
1581            Icfer_SPEC,
1582            crate::common::RW,
1583        >::from_register(self, 0)
1584    }
1585
1586    #[doc = "NACK Reception Transfer Suspension Enable"]
1587    #[inline(always)]
1588    pub fn nacke(
1589        self,
1590    ) -> crate::common::RegisterField<
1591        4,
1592        0x1,
1593        1,
1594        0,
1595        icfer::Nacke,
1596        icfer::Nacke,
1597        Icfer_SPEC,
1598        crate::common::RW,
1599    > {
1600        crate::common::RegisterField::<
1601            4,
1602            0x1,
1603            1,
1604            0,
1605            icfer::Nacke,
1606            icfer::Nacke,
1607            Icfer_SPEC,
1608            crate::common::RW,
1609        >::from_register(self, 0)
1610    }
1611
1612    #[doc = "Slave Arbitration-Lost Detection Enable"]
1613    #[inline(always)]
1614    pub fn sale(
1615        self,
1616    ) -> crate::common::RegisterField<
1617        3,
1618        0x1,
1619        1,
1620        0,
1621        icfer::Sale,
1622        icfer::Sale,
1623        Icfer_SPEC,
1624        crate::common::RW,
1625    > {
1626        crate::common::RegisterField::<
1627            3,
1628            0x1,
1629            1,
1630            0,
1631            icfer::Sale,
1632            icfer::Sale,
1633            Icfer_SPEC,
1634            crate::common::RW,
1635        >::from_register(self, 0)
1636    }
1637
1638    #[doc = "NACK Transmission Arbitration-Lost Detection Enable"]
1639    #[inline(always)]
1640    pub fn nale(
1641        self,
1642    ) -> crate::common::RegisterField<
1643        2,
1644        0x1,
1645        1,
1646        0,
1647        icfer::Nale,
1648        icfer::Nale,
1649        Icfer_SPEC,
1650        crate::common::RW,
1651    > {
1652        crate::common::RegisterField::<
1653            2,
1654            0x1,
1655            1,
1656            0,
1657            icfer::Nale,
1658            icfer::Nale,
1659            Icfer_SPEC,
1660            crate::common::RW,
1661        >::from_register(self, 0)
1662    }
1663
1664    #[doc = "Master Arbitration-Lost Detection Enable"]
1665    #[inline(always)]
1666    pub fn male(
1667        self,
1668    ) -> crate::common::RegisterField<
1669        1,
1670        0x1,
1671        1,
1672        0,
1673        icfer::Male,
1674        icfer::Male,
1675        Icfer_SPEC,
1676        crate::common::RW,
1677    > {
1678        crate::common::RegisterField::<
1679            1,
1680            0x1,
1681            1,
1682            0,
1683            icfer::Male,
1684            icfer::Male,
1685            Icfer_SPEC,
1686            crate::common::RW,
1687        >::from_register(self, 0)
1688    }
1689
1690    #[doc = "Timeout Function Enable"]
1691    #[inline(always)]
1692    pub fn tmoe(
1693        self,
1694    ) -> crate::common::RegisterField<
1695        0,
1696        0x1,
1697        1,
1698        0,
1699        icfer::Tmoe,
1700        icfer::Tmoe,
1701        Icfer_SPEC,
1702        crate::common::RW,
1703    > {
1704        crate::common::RegisterField::<
1705            0,
1706            0x1,
1707            1,
1708            0,
1709            icfer::Tmoe,
1710            icfer::Tmoe,
1711            Icfer_SPEC,
1712            crate::common::RW,
1713        >::from_register(self, 0)
1714    }
1715}
1716impl ::core::default::Default for Icfer {
1717    #[inline(always)]
1718    fn default() -> Icfer {
1719        <crate::RegValueT<Icfer_SPEC> as RegisterValue<_>>::new(114)
1720    }
1721}
1722pub mod icfer {
1723
1724    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1725    pub struct Scle_SPEC;
1726    pub type Scle = crate::EnumBitfieldStruct<u8, Scle_SPEC>;
1727    impl Scle {
1728        #[doc = "No SCL synchronous circuit is used."]
1729        pub const _0: Self = Self::new(0);
1730
1731        #[doc = "An SCL synchronous circuit is used."]
1732        pub const _1: Self = Self::new(1);
1733    }
1734    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1735    pub struct Nfe_SPEC;
1736    pub type Nfe = crate::EnumBitfieldStruct<u8, Nfe_SPEC>;
1737    impl Nfe {
1738        #[doc = "No digital noise filter circuit is used."]
1739        pub const _0: Self = Self::new(0);
1740
1741        #[doc = "A digital noise filter circuit is used."]
1742        pub const _1: Self = Self::new(1);
1743    }
1744    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1745    pub struct Nacke_SPEC;
1746    pub type Nacke = crate::EnumBitfieldStruct<u8, Nacke_SPEC>;
1747    impl Nacke {
1748        #[doc = "Transfer operation is not suspended during NACK reception (transfer suspension disabled)."]
1749        pub const _0: Self = Self::new(0);
1750
1751        #[doc = "Transfer operation is suspended during NACK reception (transfer suspension enabled)."]
1752        pub const _1: Self = Self::new(1);
1753    }
1754    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1755    pub struct Sale_SPEC;
1756    pub type Sale = crate::EnumBitfieldStruct<u8, Sale_SPEC>;
1757    impl Sale {
1758        #[doc = "Slave arbitration-lost detection is disabled."]
1759        pub const _0: Self = Self::new(0);
1760
1761        #[doc = "Slave arbitration-lost detection is enabled."]
1762        pub const _1: Self = Self::new(1);
1763    }
1764    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1765    pub struct Nale_SPEC;
1766    pub type Nale = crate::EnumBitfieldStruct<u8, Nale_SPEC>;
1767    impl Nale {
1768        #[doc = "NACK transmission arbitration-lost detection is disabled."]
1769        pub const _0: Self = Self::new(0);
1770
1771        #[doc = "NACK transmission arbitration-lost detection is enabled."]
1772        pub const _1: Self = Self::new(1);
1773    }
1774    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1775    pub struct Male_SPEC;
1776    pub type Male = crate::EnumBitfieldStruct<u8, Male_SPEC>;
1777    impl Male {
1778        #[doc = "Master arbitration-lost detection is disabled."]
1779        pub const _0: Self = Self::new(0);
1780
1781        #[doc = "Master arbitration-lost detection is enabled."]
1782        pub const _1: Self = Self::new(1);
1783    }
1784    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1785    pub struct Tmoe_SPEC;
1786    pub type Tmoe = crate::EnumBitfieldStruct<u8, Tmoe_SPEC>;
1787    impl Tmoe {
1788        #[doc = "The timeout function is disabled."]
1789        pub const _0: Self = Self::new(0);
1790
1791        #[doc = "The timeout function is enabled."]
1792        pub const _1: Self = Self::new(1);
1793    }
1794}
1795#[doc(hidden)]
1796#[derive(Copy, Clone, Eq, PartialEq)]
1797pub struct Icser_SPEC;
1798impl crate::sealed::RegSpec for Icser_SPEC {
1799    type DataType = u8;
1800}
1801
1802#[doc = "I2C Bus Status Enable Register"]
1803pub type Icser = crate::RegValueT<Icser_SPEC>;
1804
1805impl Icser {
1806    #[doc = "Host Address Enable"]
1807    #[inline(always)]
1808    pub fn hoae(
1809        self,
1810    ) -> crate::common::RegisterField<
1811        7,
1812        0x1,
1813        1,
1814        0,
1815        icser::Hoae,
1816        icser::Hoae,
1817        Icser_SPEC,
1818        crate::common::RW,
1819    > {
1820        crate::common::RegisterField::<
1821            7,
1822            0x1,
1823            1,
1824            0,
1825            icser::Hoae,
1826            icser::Hoae,
1827            Icser_SPEC,
1828            crate::common::RW,
1829        >::from_register(self, 0)
1830    }
1831
1832    #[doc = "Device-ID Address Detection Enable"]
1833    #[inline(always)]
1834    pub fn dide(
1835        self,
1836    ) -> crate::common::RegisterField<
1837        5,
1838        0x1,
1839        1,
1840        0,
1841        icser::Dide,
1842        icser::Dide,
1843        Icser_SPEC,
1844        crate::common::RW,
1845    > {
1846        crate::common::RegisterField::<
1847            5,
1848            0x1,
1849            1,
1850            0,
1851            icser::Dide,
1852            icser::Dide,
1853            Icser_SPEC,
1854            crate::common::RW,
1855        >::from_register(self, 0)
1856    }
1857
1858    #[doc = "This bit is read as 0. The write value should be 0."]
1859    #[inline(always)]
1860    pub fn reserved(
1861        self,
1862    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icser_SPEC, crate::common::RW> {
1863        crate::common::RegisterFieldBool::<4, 1, 0, Icser_SPEC, crate::common::RW>::from_register(
1864            self, 0,
1865        )
1866    }
1867
1868    #[doc = "General Call Address Enable"]
1869    #[inline(always)]
1870    pub fn gcae(
1871        self,
1872    ) -> crate::common::RegisterField<
1873        3,
1874        0x1,
1875        1,
1876        0,
1877        icser::Gcae,
1878        icser::Gcae,
1879        Icser_SPEC,
1880        crate::common::RW,
1881    > {
1882        crate::common::RegisterField::<
1883            3,
1884            0x1,
1885            1,
1886            0,
1887            icser::Gcae,
1888            icser::Gcae,
1889            Icser_SPEC,
1890            crate::common::RW,
1891        >::from_register(self, 0)
1892    }
1893
1894    #[doc = "Slave Address Register 2 Enable"]
1895    #[inline(always)]
1896    pub fn sar2e(
1897        self,
1898    ) -> crate::common::RegisterField<
1899        2,
1900        0x1,
1901        1,
1902        0,
1903        icser::Sar2E,
1904        icser::Sar2E,
1905        Icser_SPEC,
1906        crate::common::RW,
1907    > {
1908        crate::common::RegisterField::<
1909            2,
1910            0x1,
1911            1,
1912            0,
1913            icser::Sar2E,
1914            icser::Sar2E,
1915            Icser_SPEC,
1916            crate::common::RW,
1917        >::from_register(self, 0)
1918    }
1919
1920    #[doc = "Slave Address Register 1 Enable"]
1921    #[inline(always)]
1922    pub fn sar1e(
1923        self,
1924    ) -> crate::common::RegisterField<
1925        1,
1926        0x1,
1927        1,
1928        0,
1929        icser::Sar1E,
1930        icser::Sar1E,
1931        Icser_SPEC,
1932        crate::common::RW,
1933    > {
1934        crate::common::RegisterField::<
1935            1,
1936            0x1,
1937            1,
1938            0,
1939            icser::Sar1E,
1940            icser::Sar1E,
1941            Icser_SPEC,
1942            crate::common::RW,
1943        >::from_register(self, 0)
1944    }
1945
1946    #[doc = "Slave Address Register 0 Enable"]
1947    #[inline(always)]
1948    pub fn sar0e(
1949        self,
1950    ) -> crate::common::RegisterField<
1951        0,
1952        0x1,
1953        1,
1954        0,
1955        icser::Sar0E,
1956        icser::Sar0E,
1957        Icser_SPEC,
1958        crate::common::RW,
1959    > {
1960        crate::common::RegisterField::<
1961            0,
1962            0x1,
1963            1,
1964            0,
1965            icser::Sar0E,
1966            icser::Sar0E,
1967            Icser_SPEC,
1968            crate::common::RW,
1969        >::from_register(self, 0)
1970    }
1971}
1972impl ::core::default::Default for Icser {
1973    #[inline(always)]
1974    fn default() -> Icser {
1975        <crate::RegValueT<Icser_SPEC> as RegisterValue<_>>::new(9)
1976    }
1977}
1978pub mod icser {
1979
1980    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1981    pub struct Hoae_SPEC;
1982    pub type Hoae = crate::EnumBitfieldStruct<u8, Hoae_SPEC>;
1983    impl Hoae {
1984        #[doc = "Host address detection is disabled."]
1985        pub const _0: Self = Self::new(0);
1986
1987        #[doc = "Host address detection is enabled."]
1988        pub const _1: Self = Self::new(1);
1989    }
1990    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1991    pub struct Dide_SPEC;
1992    pub type Dide = crate::EnumBitfieldStruct<u8, Dide_SPEC>;
1993    impl Dide {
1994        #[doc = "Device-ID address detection is disabled."]
1995        pub const _0: Self = Self::new(0);
1996
1997        #[doc = "Device-ID address detection is enabled."]
1998        pub const _1: Self = Self::new(1);
1999    }
2000    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2001    pub struct Gcae_SPEC;
2002    pub type Gcae = crate::EnumBitfieldStruct<u8, Gcae_SPEC>;
2003    impl Gcae {
2004        #[doc = "General call address detection is disabled."]
2005        pub const _0: Self = Self::new(0);
2006
2007        #[doc = "General call address detection is enabled."]
2008        pub const _1: Self = Self::new(1);
2009    }
2010    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2011    pub struct Sar2E_SPEC;
2012    pub type Sar2E = crate::EnumBitfieldStruct<u8, Sar2E_SPEC>;
2013    impl Sar2E {
2014        #[doc = "Slave address in SARL2 and SARU2 is disabled."]
2015        pub const _0: Self = Self::new(0);
2016
2017        #[doc = "Slave address in SARL2 and SARU2 is enabled"]
2018        pub const _1: Self = Self::new(1);
2019    }
2020    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2021    pub struct Sar1E_SPEC;
2022    pub type Sar1E = crate::EnumBitfieldStruct<u8, Sar1E_SPEC>;
2023    impl Sar1E {
2024        #[doc = "Slave address in SARL1 and SARU1 is disabled."]
2025        pub const _0: Self = Self::new(0);
2026
2027        #[doc = "Slave address in SARL1 and SARU1 is enabled."]
2028        pub const _1: Self = Self::new(1);
2029    }
2030    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2031    pub struct Sar0E_SPEC;
2032    pub type Sar0E = crate::EnumBitfieldStruct<u8, Sar0E_SPEC>;
2033    impl Sar0E {
2034        #[doc = "Slave address in SARL0 and SARU0 is disabled."]
2035        pub const _0: Self = Self::new(0);
2036
2037        #[doc = "Slave address in SARL0 and SARU0 is enabled."]
2038        pub const _1: Self = Self::new(1);
2039    }
2040}
2041#[doc(hidden)]
2042#[derive(Copy, Clone, Eq, PartialEq)]
2043pub struct Icier_SPEC;
2044impl crate::sealed::RegSpec for Icier_SPEC {
2045    type DataType = u8;
2046}
2047
2048#[doc = "I2C Bus Interrupt Enable Register"]
2049pub type Icier = crate::RegValueT<Icier_SPEC>;
2050
2051impl Icier {
2052    #[doc = "Transmit Data Empty Interrupt Request Enable"]
2053    #[inline(always)]
2054    pub fn tie(
2055        self,
2056    ) -> crate::common::RegisterField<
2057        7,
2058        0x1,
2059        1,
2060        0,
2061        icier::Tie,
2062        icier::Tie,
2063        Icier_SPEC,
2064        crate::common::RW,
2065    > {
2066        crate::common::RegisterField::<
2067            7,
2068            0x1,
2069            1,
2070            0,
2071            icier::Tie,
2072            icier::Tie,
2073            Icier_SPEC,
2074            crate::common::RW,
2075        >::from_register(self, 0)
2076    }
2077
2078    #[doc = "Transmit End Interrupt Request  Enable"]
2079    #[inline(always)]
2080    pub fn teie(
2081        self,
2082    ) -> crate::common::RegisterField<
2083        6,
2084        0x1,
2085        1,
2086        0,
2087        icier::Teie,
2088        icier::Teie,
2089        Icier_SPEC,
2090        crate::common::RW,
2091    > {
2092        crate::common::RegisterField::<
2093            6,
2094            0x1,
2095            1,
2096            0,
2097            icier::Teie,
2098            icier::Teie,
2099            Icier_SPEC,
2100            crate::common::RW,
2101        >::from_register(self, 0)
2102    }
2103
2104    #[doc = "Receive Data Full Interrupt Request Enable"]
2105    #[inline(always)]
2106    pub fn rie(
2107        self,
2108    ) -> crate::common::RegisterField<
2109        5,
2110        0x1,
2111        1,
2112        0,
2113        icier::Rie,
2114        icier::Rie,
2115        Icier_SPEC,
2116        crate::common::RW,
2117    > {
2118        crate::common::RegisterField::<
2119            5,
2120            0x1,
2121            1,
2122            0,
2123            icier::Rie,
2124            icier::Rie,
2125            Icier_SPEC,
2126            crate::common::RW,
2127        >::from_register(self, 0)
2128    }
2129
2130    #[doc = "NACK Reception Interrupt Request Enable"]
2131    #[inline(always)]
2132    pub fn nakie(
2133        self,
2134    ) -> crate::common::RegisterField<
2135        4,
2136        0x1,
2137        1,
2138        0,
2139        icier::Nakie,
2140        icier::Nakie,
2141        Icier_SPEC,
2142        crate::common::RW,
2143    > {
2144        crate::common::RegisterField::<
2145            4,
2146            0x1,
2147            1,
2148            0,
2149            icier::Nakie,
2150            icier::Nakie,
2151            Icier_SPEC,
2152            crate::common::RW,
2153        >::from_register(self, 0)
2154    }
2155
2156    #[doc = "Stop Condition Detection Interrupt Request Enable"]
2157    #[inline(always)]
2158    pub fn spie(
2159        self,
2160    ) -> crate::common::RegisterField<
2161        3,
2162        0x1,
2163        1,
2164        0,
2165        icier::Spie,
2166        icier::Spie,
2167        Icier_SPEC,
2168        crate::common::RW,
2169    > {
2170        crate::common::RegisterField::<
2171            3,
2172            0x1,
2173            1,
2174            0,
2175            icier::Spie,
2176            icier::Spie,
2177            Icier_SPEC,
2178            crate::common::RW,
2179        >::from_register(self, 0)
2180    }
2181
2182    #[doc = "Start Condition Detection Interrupt Request Enable"]
2183    #[inline(always)]
2184    pub fn stie(
2185        self,
2186    ) -> crate::common::RegisterField<
2187        2,
2188        0x1,
2189        1,
2190        0,
2191        icier::Stie,
2192        icier::Stie,
2193        Icier_SPEC,
2194        crate::common::RW,
2195    > {
2196        crate::common::RegisterField::<
2197            2,
2198            0x1,
2199            1,
2200            0,
2201            icier::Stie,
2202            icier::Stie,
2203            Icier_SPEC,
2204            crate::common::RW,
2205        >::from_register(self, 0)
2206    }
2207
2208    #[doc = "Arbitration-Lost Interrupt Request Enable"]
2209    #[inline(always)]
2210    pub fn alie(
2211        self,
2212    ) -> crate::common::RegisterField<
2213        1,
2214        0x1,
2215        1,
2216        0,
2217        icier::Alie,
2218        icier::Alie,
2219        Icier_SPEC,
2220        crate::common::RW,
2221    > {
2222        crate::common::RegisterField::<
2223            1,
2224            0x1,
2225            1,
2226            0,
2227            icier::Alie,
2228            icier::Alie,
2229            Icier_SPEC,
2230            crate::common::RW,
2231        >::from_register(self, 0)
2232    }
2233
2234    #[doc = "Timeout Interrupt Request Enable"]
2235    #[inline(always)]
2236    pub fn tmoie(
2237        self,
2238    ) -> crate::common::RegisterField<
2239        0,
2240        0x1,
2241        1,
2242        0,
2243        icier::Tmoie,
2244        icier::Tmoie,
2245        Icier_SPEC,
2246        crate::common::RW,
2247    > {
2248        crate::common::RegisterField::<
2249            0,
2250            0x1,
2251            1,
2252            0,
2253            icier::Tmoie,
2254            icier::Tmoie,
2255            Icier_SPEC,
2256            crate::common::RW,
2257        >::from_register(self, 0)
2258    }
2259}
2260impl ::core::default::Default for Icier {
2261    #[inline(always)]
2262    fn default() -> Icier {
2263        <crate::RegValueT<Icier_SPEC> as RegisterValue<_>>::new(0)
2264    }
2265}
2266pub mod icier {
2267
2268    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2269    pub struct Tie_SPEC;
2270    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
2271    impl Tie {
2272        #[doc = "Transmit data empty interrupt request (IICn_TXI) is disabled."]
2273        pub const _0: Self = Self::new(0);
2274
2275        #[doc = "Transmit data empty interrupt request (IICn_TXI) is enabled."]
2276        pub const _1: Self = Self::new(1);
2277    }
2278    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2279    pub struct Teie_SPEC;
2280    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
2281    impl Teie {
2282        #[doc = "Transmit end interrupt request (IICn_TEI) is disabled."]
2283        pub const _0: Self = Self::new(0);
2284
2285        #[doc = "Transmit end interrupt request (IICn_TEI) is enabled."]
2286        pub const _1: Self = Self::new(1);
2287    }
2288    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2289    pub struct Rie_SPEC;
2290    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
2291    impl Rie {
2292        #[doc = "Receive data full interrupt request (IICn_RXI) is disabled."]
2293        pub const _0: Self = Self::new(0);
2294
2295        #[doc = "Receive data full interrupt request (IICn_RXI) is enabled."]
2296        pub const _1: Self = Self::new(1);
2297    }
2298    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2299    pub struct Nakie_SPEC;
2300    pub type Nakie = crate::EnumBitfieldStruct<u8, Nakie_SPEC>;
2301    impl Nakie {
2302        #[doc = "NACK reception interrupt request (NAKI) is disabled."]
2303        pub const _0: Self = Self::new(0);
2304
2305        #[doc = "NACK reception interrupt request (NAKI) is enabled."]
2306        pub const _1: Self = Self::new(1);
2307    }
2308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2309    pub struct Spie_SPEC;
2310    pub type Spie = crate::EnumBitfieldStruct<u8, Spie_SPEC>;
2311    impl Spie {
2312        #[doc = "Stop condition detection interrupt request (SPI) is disabled."]
2313        pub const _0: Self = Self::new(0);
2314
2315        #[doc = "Stop condition detection interrupt request (SPI) is enabled."]
2316        pub const _1: Self = Self::new(1);
2317    }
2318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2319    pub struct Stie_SPEC;
2320    pub type Stie = crate::EnumBitfieldStruct<u8, Stie_SPEC>;
2321    impl Stie {
2322        #[doc = "Start condition detection interrupt request (STI) is disabled."]
2323        pub const _0: Self = Self::new(0);
2324
2325        #[doc = "Start condition detection interrupt request (STI) is enabled."]
2326        pub const _1: Self = Self::new(1);
2327    }
2328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2329    pub struct Alie_SPEC;
2330    pub type Alie = crate::EnumBitfieldStruct<u8, Alie_SPEC>;
2331    impl Alie {
2332        #[doc = "Arbitration-lost interrupt request (ALI) is disabled."]
2333        pub const _0: Self = Self::new(0);
2334
2335        #[doc = "Arbitration-lost interrupt request (ALI) is enabled."]
2336        pub const _1: Self = Self::new(1);
2337    }
2338    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2339    pub struct Tmoie_SPEC;
2340    pub type Tmoie = crate::EnumBitfieldStruct<u8, Tmoie_SPEC>;
2341    impl Tmoie {
2342        #[doc = "Timeout interrupt request (TMOI) is disabled."]
2343        pub const _0: Self = Self::new(0);
2344
2345        #[doc = "Timeout interrupt request (TMOI) is enabled."]
2346        pub const _1: Self = Self::new(1);
2347    }
2348}
2349#[doc(hidden)]
2350#[derive(Copy, Clone, Eq, PartialEq)]
2351pub struct Icsr1_SPEC;
2352impl crate::sealed::RegSpec for Icsr1_SPEC {
2353    type DataType = u8;
2354}
2355
2356#[doc = "I2C Bus Status Register 1"]
2357pub type Icsr1 = crate::RegValueT<Icsr1_SPEC>;
2358
2359impl Icsr1 {
2360    #[doc = "Host Address Detection Flag"]
2361    #[inline(always)]
2362    pub fn hoa(
2363        self,
2364    ) -> crate::common::RegisterField<
2365        7,
2366        0x1,
2367        1,
2368        0,
2369        icsr1::Hoa,
2370        icsr1::Hoa,
2371        Icsr1_SPEC,
2372        crate::common::RW,
2373    > {
2374        crate::common::RegisterField::<
2375            7,
2376            0x1,
2377            1,
2378            0,
2379            icsr1::Hoa,
2380            icsr1::Hoa,
2381            Icsr1_SPEC,
2382            crate::common::RW,
2383        >::from_register(self, 0)
2384    }
2385
2386    #[doc = "Device-ID Address Detection Flag"]
2387    #[inline(always)]
2388    pub fn did(
2389        self,
2390    ) -> crate::common::RegisterField<
2391        5,
2392        0x1,
2393        1,
2394        0,
2395        icsr1::Did,
2396        icsr1::Did,
2397        Icsr1_SPEC,
2398        crate::common::RW,
2399    > {
2400        crate::common::RegisterField::<
2401            5,
2402            0x1,
2403            1,
2404            0,
2405            icsr1::Did,
2406            icsr1::Did,
2407            Icsr1_SPEC,
2408            crate::common::RW,
2409        >::from_register(self, 0)
2410    }
2411
2412    #[doc = "This bit is read as 0. The write value should be 0."]
2413    #[inline(always)]
2414    pub fn reserved(
2415        self,
2416    ) -> crate::common::RegisterFieldBool<4, 1, 0, Icsr1_SPEC, crate::common::RW> {
2417        crate::common::RegisterFieldBool::<4, 1, 0, Icsr1_SPEC, crate::common::RW>::from_register(
2418            self, 0,
2419        )
2420    }
2421
2422    #[doc = "General Call Address Detection Flag"]
2423    #[inline(always)]
2424    pub fn gca(
2425        self,
2426    ) -> crate::common::RegisterField<
2427        3,
2428        0x1,
2429        1,
2430        0,
2431        icsr1::Gca,
2432        icsr1::Gca,
2433        Icsr1_SPEC,
2434        crate::common::RW,
2435    > {
2436        crate::common::RegisterField::<
2437            3,
2438            0x1,
2439            1,
2440            0,
2441            icsr1::Gca,
2442            icsr1::Gca,
2443            Icsr1_SPEC,
2444            crate::common::RW,
2445        >::from_register(self, 0)
2446    }
2447
2448    #[doc = "Slave Address 2 Detection Flag"]
2449    #[inline(always)]
2450    pub fn aas2(
2451        self,
2452    ) -> crate::common::RegisterField<
2453        2,
2454        0x1,
2455        1,
2456        0,
2457        icsr1::Aas2,
2458        icsr1::Aas2,
2459        Icsr1_SPEC,
2460        crate::common::RW,
2461    > {
2462        crate::common::RegisterField::<
2463            2,
2464            0x1,
2465            1,
2466            0,
2467            icsr1::Aas2,
2468            icsr1::Aas2,
2469            Icsr1_SPEC,
2470            crate::common::RW,
2471        >::from_register(self, 0)
2472    }
2473
2474    #[doc = "Slave Address 1 Detection Flag"]
2475    #[inline(always)]
2476    pub fn aas1(
2477        self,
2478    ) -> crate::common::RegisterField<
2479        1,
2480        0x1,
2481        1,
2482        0,
2483        icsr1::Aas1,
2484        icsr1::Aas1,
2485        Icsr1_SPEC,
2486        crate::common::RW,
2487    > {
2488        crate::common::RegisterField::<
2489            1,
2490            0x1,
2491            1,
2492            0,
2493            icsr1::Aas1,
2494            icsr1::Aas1,
2495            Icsr1_SPEC,
2496            crate::common::RW,
2497        >::from_register(self, 0)
2498    }
2499
2500    #[doc = "Slave Address 0 Detection Flag"]
2501    #[inline(always)]
2502    pub fn aas0(
2503        self,
2504    ) -> crate::common::RegisterField<
2505        0,
2506        0x1,
2507        1,
2508        0,
2509        icsr1::Aas0,
2510        icsr1::Aas0,
2511        Icsr1_SPEC,
2512        crate::common::RW,
2513    > {
2514        crate::common::RegisterField::<
2515            0,
2516            0x1,
2517            1,
2518            0,
2519            icsr1::Aas0,
2520            icsr1::Aas0,
2521            Icsr1_SPEC,
2522            crate::common::RW,
2523        >::from_register(self, 0)
2524    }
2525}
2526impl ::core::default::Default for Icsr1 {
2527    #[inline(always)]
2528    fn default() -> Icsr1 {
2529        <crate::RegValueT<Icsr1_SPEC> as RegisterValue<_>>::new(0)
2530    }
2531}
2532pub mod icsr1 {
2533
2534    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2535    pub struct Hoa_SPEC;
2536    pub type Hoa = crate::EnumBitfieldStruct<u8, Hoa_SPEC>;
2537    impl Hoa {
2538        #[doc = "Host address is not detected."]
2539        pub const _0: Self = Self::new(0);
2540
2541        #[doc = "Host address is detected."]
2542        pub const _1: Self = Self::new(1);
2543    }
2544    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2545    pub struct Did_SPEC;
2546    pub type Did = crate::EnumBitfieldStruct<u8, Did_SPEC>;
2547    impl Did {
2548        #[doc = "Device-ID command is not detected."]
2549        pub const _0: Self = Self::new(0);
2550
2551        #[doc = "Device-ID command is detected."]
2552        pub const _1: Self = Self::new(1);
2553    }
2554    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2555    pub struct Gca_SPEC;
2556    pub type Gca = crate::EnumBitfieldStruct<u8, Gca_SPEC>;
2557    impl Gca {
2558        #[doc = "General call address is not detected."]
2559        pub const _0: Self = Self::new(0);
2560
2561        #[doc = "General call address is detected."]
2562        pub const _1: Self = Self::new(1);
2563    }
2564    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2565    pub struct Aas2_SPEC;
2566    pub type Aas2 = crate::EnumBitfieldStruct<u8, Aas2_SPEC>;
2567    impl Aas2 {
2568        #[doc = "Slave address 2 is not detected."]
2569        pub const _0: Self = Self::new(0);
2570
2571        #[doc = "Slave address 2 is detected"]
2572        pub const _1: Self = Self::new(1);
2573    }
2574    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2575    pub struct Aas1_SPEC;
2576    pub type Aas1 = crate::EnumBitfieldStruct<u8, Aas1_SPEC>;
2577    impl Aas1 {
2578        #[doc = "Slave address 1 is not detected."]
2579        pub const _0: Self = Self::new(0);
2580
2581        #[doc = "Slave address 1 is detected."]
2582        pub const _1: Self = Self::new(1);
2583    }
2584    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2585    pub struct Aas0_SPEC;
2586    pub type Aas0 = crate::EnumBitfieldStruct<u8, Aas0_SPEC>;
2587    impl Aas0 {
2588        #[doc = "Slave address 0 is not detected."]
2589        pub const _0: Self = Self::new(0);
2590
2591        #[doc = "Slave address 0 is detected."]
2592        pub const _1: Self = Self::new(1);
2593    }
2594}
2595#[doc(hidden)]
2596#[derive(Copy, Clone, Eq, PartialEq)]
2597pub struct Icsr2_SPEC;
2598impl crate::sealed::RegSpec for Icsr2_SPEC {
2599    type DataType = u8;
2600}
2601
2602#[doc = "I2C Bus Status Register 2"]
2603pub type Icsr2 = crate::RegValueT<Icsr2_SPEC>;
2604
2605impl Icsr2 {
2606    #[doc = "Transmit Data Empty Flag"]
2607    #[inline(always)]
2608    pub fn tdre(
2609        self,
2610    ) -> crate::common::RegisterField<
2611        7,
2612        0x1,
2613        1,
2614        0,
2615        icsr2::Tdre,
2616        icsr2::Tdre,
2617        Icsr2_SPEC,
2618        crate::common::R,
2619    > {
2620        crate::common::RegisterField::<
2621            7,
2622            0x1,
2623            1,
2624            0,
2625            icsr2::Tdre,
2626            icsr2::Tdre,
2627            Icsr2_SPEC,
2628            crate::common::R,
2629        >::from_register(self, 0)
2630    }
2631
2632    #[doc = "Transmit End Flag"]
2633    #[inline(always)]
2634    pub fn tend(
2635        self,
2636    ) -> crate::common::RegisterField<
2637        6,
2638        0x1,
2639        1,
2640        0,
2641        icsr2::Tend,
2642        icsr2::Tend,
2643        Icsr2_SPEC,
2644        crate::common::RW,
2645    > {
2646        crate::common::RegisterField::<
2647            6,
2648            0x1,
2649            1,
2650            0,
2651            icsr2::Tend,
2652            icsr2::Tend,
2653            Icsr2_SPEC,
2654            crate::common::RW,
2655        >::from_register(self, 0)
2656    }
2657
2658    #[doc = "Receive Data Full Flag"]
2659    #[inline(always)]
2660    pub fn rdrf(
2661        self,
2662    ) -> crate::common::RegisterField<
2663        5,
2664        0x1,
2665        1,
2666        0,
2667        icsr2::Rdrf,
2668        icsr2::Rdrf,
2669        Icsr2_SPEC,
2670        crate::common::RW,
2671    > {
2672        crate::common::RegisterField::<
2673            5,
2674            0x1,
2675            1,
2676            0,
2677            icsr2::Rdrf,
2678            icsr2::Rdrf,
2679            Icsr2_SPEC,
2680            crate::common::RW,
2681        >::from_register(self, 0)
2682    }
2683
2684    #[doc = "NACK Detection Flag"]
2685    #[inline(always)]
2686    pub fn nackf(
2687        self,
2688    ) -> crate::common::RegisterField<
2689        4,
2690        0x1,
2691        1,
2692        0,
2693        icsr2::Nackf,
2694        icsr2::Nackf,
2695        Icsr2_SPEC,
2696        crate::common::RW,
2697    > {
2698        crate::common::RegisterField::<
2699            4,
2700            0x1,
2701            1,
2702            0,
2703            icsr2::Nackf,
2704            icsr2::Nackf,
2705            Icsr2_SPEC,
2706            crate::common::RW,
2707        >::from_register(self, 0)
2708    }
2709
2710    #[doc = "Stop Condition Detection Flag"]
2711    #[inline(always)]
2712    pub fn stop(
2713        self,
2714    ) -> crate::common::RegisterField<
2715        3,
2716        0x1,
2717        1,
2718        0,
2719        icsr2::Stop,
2720        icsr2::Stop,
2721        Icsr2_SPEC,
2722        crate::common::RW,
2723    > {
2724        crate::common::RegisterField::<
2725            3,
2726            0x1,
2727            1,
2728            0,
2729            icsr2::Stop,
2730            icsr2::Stop,
2731            Icsr2_SPEC,
2732            crate::common::RW,
2733        >::from_register(self, 0)
2734    }
2735
2736    #[doc = "Start Condition Detection Flag"]
2737    #[inline(always)]
2738    pub fn start(
2739        self,
2740    ) -> crate::common::RegisterField<
2741        2,
2742        0x1,
2743        1,
2744        0,
2745        icsr2::Start,
2746        icsr2::Start,
2747        Icsr2_SPEC,
2748        crate::common::RW,
2749    > {
2750        crate::common::RegisterField::<
2751            2,
2752            0x1,
2753            1,
2754            0,
2755            icsr2::Start,
2756            icsr2::Start,
2757            Icsr2_SPEC,
2758            crate::common::RW,
2759        >::from_register(self, 0)
2760    }
2761
2762    #[doc = "Arbitration-Lost Flag"]
2763    #[inline(always)]
2764    pub fn al(
2765        self,
2766    ) -> crate::common::RegisterField<
2767        1,
2768        0x1,
2769        1,
2770        0,
2771        icsr2::Al,
2772        icsr2::Al,
2773        Icsr2_SPEC,
2774        crate::common::RW,
2775    > {
2776        crate::common::RegisterField::<
2777            1,
2778            0x1,
2779            1,
2780            0,
2781            icsr2::Al,
2782            icsr2::Al,
2783            Icsr2_SPEC,
2784            crate::common::RW,
2785        >::from_register(self, 0)
2786    }
2787
2788    #[doc = "Timeout Detection Flag"]
2789    #[inline(always)]
2790    pub fn tmof(
2791        self,
2792    ) -> crate::common::RegisterField<
2793        0,
2794        0x1,
2795        1,
2796        0,
2797        icsr2::Tmof,
2798        icsr2::Tmof,
2799        Icsr2_SPEC,
2800        crate::common::RW,
2801    > {
2802        crate::common::RegisterField::<
2803            0,
2804            0x1,
2805            1,
2806            0,
2807            icsr2::Tmof,
2808            icsr2::Tmof,
2809            Icsr2_SPEC,
2810            crate::common::RW,
2811        >::from_register(self, 0)
2812    }
2813}
2814impl ::core::default::Default for Icsr2 {
2815    #[inline(always)]
2816    fn default() -> Icsr2 {
2817        <crate::RegValueT<Icsr2_SPEC> as RegisterValue<_>>::new(0)
2818    }
2819}
2820pub mod icsr2 {
2821
2822    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2823    pub struct Tdre_SPEC;
2824    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
2825    impl Tdre {
2826        #[doc = "ICDRT contains transmit data."]
2827        pub const _0: Self = Self::new(0);
2828
2829        #[doc = "ICDRT contains no transmit data."]
2830        pub const _1: Self = Self::new(1);
2831    }
2832    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2833    pub struct Tend_SPEC;
2834    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
2835    impl Tend {
2836        #[doc = "Data is being transmitted."]
2837        pub const _0: Self = Self::new(0);
2838
2839        #[doc = "Data has been transmitted."]
2840        pub const _1: Self = Self::new(1);
2841    }
2842    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2843    pub struct Rdrf_SPEC;
2844    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
2845    impl Rdrf {
2846        #[doc = "ICDRR contains no receive data."]
2847        pub const _0: Self = Self::new(0);
2848
2849        #[doc = "ICDRR contains receive data."]
2850        pub const _1: Self = Self::new(1);
2851    }
2852    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2853    pub struct Nackf_SPEC;
2854    pub type Nackf = crate::EnumBitfieldStruct<u8, Nackf_SPEC>;
2855    impl Nackf {
2856        #[doc = "NACK is not detected."]
2857        pub const _0: Self = Self::new(0);
2858
2859        #[doc = "NACK is detected."]
2860        pub const _1: Self = Self::new(1);
2861    }
2862    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2863    pub struct Stop_SPEC;
2864    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
2865    impl Stop {
2866        #[doc = "Stop condition is not detected."]
2867        pub const _0: Self = Self::new(0);
2868
2869        #[doc = "Stop condition is detected."]
2870        pub const _1: Self = Self::new(1);
2871    }
2872    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2873    pub struct Start_SPEC;
2874    pub type Start = crate::EnumBitfieldStruct<u8, Start_SPEC>;
2875    impl Start {
2876        #[doc = "Start condition is not detected."]
2877        pub const _0: Self = Self::new(0);
2878
2879        #[doc = "Start condition is detected."]
2880        pub const _1: Self = Self::new(1);
2881    }
2882    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2883    pub struct Al_SPEC;
2884    pub type Al = crate::EnumBitfieldStruct<u8, Al_SPEC>;
2885    impl Al {
2886        #[doc = "Arbitration is not lost."]
2887        pub const _0: Self = Self::new(0);
2888
2889        #[doc = "Arbitration is lost."]
2890        pub const _1: Self = Self::new(1);
2891    }
2892    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2893    pub struct Tmof_SPEC;
2894    pub type Tmof = crate::EnumBitfieldStruct<u8, Tmof_SPEC>;
2895    impl Tmof {
2896        #[doc = "Timeout is not detected."]
2897        pub const _0: Self = Self::new(0);
2898
2899        #[doc = "Timeout is detected."]
2900        pub const _1: Self = Self::new(1);
2901    }
2902}
2903#[doc(hidden)]
2904#[derive(Copy, Clone, Eq, PartialEq)]
2905pub struct Sarl_SPEC;
2906impl crate::sealed::RegSpec for Sarl_SPEC {
2907    type DataType = u8;
2908}
2909
2910#[doc = "Slave Address Register L%s"]
2911pub type Sarl = crate::RegValueT<Sarl_SPEC>;
2912
2913impl Sarl {
2914    #[doc = "A slave address is set.7-Bit Address = SVA\\[7:1\\] 10-Bit Address = { SVA9,SVA8,SVA\\[7:0\\] }"]
2915    #[inline(always)]
2916    pub fn sva(
2917        self,
2918    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Sarl_SPEC, crate::common::RW> {
2919        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Sarl_SPEC,crate::common::RW>::from_register(self,0)
2920    }
2921}
2922impl ::core::default::Default for Sarl {
2923    #[inline(always)]
2924    fn default() -> Sarl {
2925        <crate::RegValueT<Sarl_SPEC> as RegisterValue<_>>::new(0)
2926    }
2927}
2928
2929#[doc(hidden)]
2930#[derive(Copy, Clone, Eq, PartialEq)]
2931pub struct Saru_SPEC;
2932impl crate::sealed::RegSpec for Saru_SPEC {
2933    type DataType = u8;
2934}
2935
2936#[doc = "Slave Address Register U%s"]
2937pub type Saru = crate::RegValueT<Saru_SPEC>;
2938
2939impl Saru {
2940    #[doc = "These bits are read as 00000. The write value should be 00000."]
2941    #[inline(always)]
2942    pub fn reserved(
2943        self,
2944    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Saru_SPEC, crate::common::RW> {
2945        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Saru_SPEC,crate::common::RW>::from_register(self,0)
2946    }
2947
2948    #[doc = "10-Bit Address(bit9)"]
2949    #[inline(always)]
2950    pub fn sva9(self) -> crate::common::RegisterFieldBool<2, 1, 0, Saru_SPEC, crate::common::RW> {
2951        crate::common::RegisterFieldBool::<2, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2952            self, 0,
2953        )
2954    }
2955
2956    #[doc = "10-Bit Address(bit8)"]
2957    #[inline(always)]
2958    pub fn sva8(self) -> crate::common::RegisterFieldBool<1, 1, 0, Saru_SPEC, crate::common::RW> {
2959        crate::common::RegisterFieldBool::<1, 1, 0, Saru_SPEC, crate::common::RW>::from_register(
2960            self, 0,
2961        )
2962    }
2963
2964    #[doc = "7-Bit/10-Bit Address Format Selection"]
2965    #[inline(always)]
2966    pub fn fs(
2967        self,
2968    ) -> crate::common::RegisterField<0, 0x1, 1, 0, saru::Fs, saru::Fs, Saru_SPEC, crate::common::RW>
2969    {
2970        crate::common::RegisterField::<0,0x1,1,0,saru::Fs,saru::Fs,Saru_SPEC,crate::common::RW>::from_register(self,0)
2971    }
2972}
2973impl ::core::default::Default for Saru {
2974    #[inline(always)]
2975    fn default() -> Saru {
2976        <crate::RegValueT<Saru_SPEC> as RegisterValue<_>>::new(0)
2977    }
2978}
2979pub mod saru {
2980
2981    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2982    pub struct Fs_SPEC;
2983    pub type Fs = crate::EnumBitfieldStruct<u8, Fs_SPEC>;
2984    impl Fs {
2985        #[doc = "The 7-bit address format is selected."]
2986        pub const _0: Self = Self::new(0);
2987
2988        #[doc = "The 10-bit address format is selected."]
2989        pub const _1: Self = Self::new(1);
2990    }
2991}
2992#[doc(hidden)]
2993#[derive(Copy, Clone, Eq, PartialEq)]
2994pub struct Icbrl_SPEC;
2995impl crate::sealed::RegSpec for Icbrl_SPEC {
2996    type DataType = u8;
2997}
2998
2999#[doc = "I2C Bus Bit Rate Low-Level Register"]
3000pub type Icbrl = crate::RegValueT<Icbrl_SPEC>;
3001
3002impl Icbrl {
3003    #[doc = "These bits are read as 111. The write value should be 111."]
3004    #[inline(always)]
3005    pub fn reserved(
3006        self,
3007    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
3008        crate::common::RegisterField::<5,0x7,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
3009    }
3010
3011    #[doc = "Bit Rate Low-Level Period(Low-level period of SCL clock)"]
3012    #[inline(always)]
3013    pub fn brl(
3014        self,
3015    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrl_SPEC, crate::common::RW> {
3016        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrl_SPEC,crate::common::RW>::from_register(self,0)
3017    }
3018}
3019impl ::core::default::Default for Icbrl {
3020    #[inline(always)]
3021    fn default() -> Icbrl {
3022        <crate::RegValueT<Icbrl_SPEC> as RegisterValue<_>>::new(255)
3023    }
3024}
3025
3026#[doc(hidden)]
3027#[derive(Copy, Clone, Eq, PartialEq)]
3028pub struct Icbrh_SPEC;
3029impl crate::sealed::RegSpec for Icbrh_SPEC {
3030    type DataType = u8;
3031}
3032
3033#[doc = "I2C Bus Bit Rate High-Level Register"]
3034pub type Icbrh = crate::RegValueT<Icbrh_SPEC>;
3035
3036impl Icbrh {
3037    #[doc = "These bits are read as 111. The write value should be 111."]
3038    #[inline(always)]
3039    pub fn reserved(
3040        self,
3041    ) -> crate::common::RegisterField<5, 0x7, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3042        crate::common::RegisterField::<5,0x7,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3043    }
3044
3045    #[doc = "Bit Rate High-Level Period(High-level period of SCL clock)"]
3046    #[inline(always)]
3047    pub fn brh(
3048        self,
3049    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Icbrh_SPEC, crate::common::RW> {
3050        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Icbrh_SPEC,crate::common::RW>::from_register(self,0)
3051    }
3052}
3053impl ::core::default::Default for Icbrh {
3054    #[inline(always)]
3055    fn default() -> Icbrh {
3056        <crate::RegValueT<Icbrh_SPEC> as RegisterValue<_>>::new(255)
3057    }
3058}
3059
3060#[doc(hidden)]
3061#[derive(Copy, Clone, Eq, PartialEq)]
3062pub struct Icdrt_SPEC;
3063impl crate::sealed::RegSpec for Icdrt_SPEC {
3064    type DataType = u8;
3065}
3066
3067#[doc = "I2C Bus Transmit Data Register"]
3068pub type Icdrt = crate::RegValueT<Icdrt_SPEC>;
3069
3070impl Icdrt {
3071    #[doc = "8-bit read-write register that stores transmit data."]
3072    #[inline(always)]
3073    pub fn icdrt(
3074        self,
3075    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrt_SPEC, crate::common::RW> {
3076        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrt_SPEC,crate::common::RW>::from_register(self,0)
3077    }
3078}
3079impl ::core::default::Default for Icdrt {
3080    #[inline(always)]
3081    fn default() -> Icdrt {
3082        <crate::RegValueT<Icdrt_SPEC> as RegisterValue<_>>::new(255)
3083    }
3084}
3085
3086#[doc(hidden)]
3087#[derive(Copy, Clone, Eq, PartialEq)]
3088pub struct Icdrr_SPEC;
3089impl crate::sealed::RegSpec for Icdrr_SPEC {
3090    type DataType = u8;
3091}
3092
3093#[doc = "I2C Bus Receive Data Register"]
3094pub type Icdrr = crate::RegValueT<Icdrr_SPEC>;
3095
3096impl Icdrr {
3097    #[doc = "8-bit register that stores the received data"]
3098    #[inline(always)]
3099    pub fn icdrr(
3100        self,
3101    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Icdrr_SPEC, crate::common::R> {
3102        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Icdrr_SPEC,crate::common::R>::from_register(self,0)
3103    }
3104}
3105impl ::core::default::Default for Icdrr {
3106    #[inline(always)]
3107    fn default() -> Icdrr {
3108        <crate::RegValueT<Icdrr_SPEC> as RegisterValue<_>>::new(0)
3109    }
3110}
ra2a1_pac/iic1.rs

ra2a1_pac/
iic1.rs
