ra2a1_pac/
sci1.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Communication Interface 1"]
28unsafe impl ::core::marker::Send for super::Sci1 {}
29unsafe impl ::core::marker::Sync for super::Sci1 {}
30impl super::Sci1 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Serial Mode Register (SCMR.SMIF = 0)"]
38    #[inline(always)]
39    pub const fn smr(&self) -> &'static crate::common::Reg<self::Smr_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Smr_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Serial mode register (SCMR.SMIF = 1)"]
48    #[inline(always)]
49    pub const fn smr_smci(
50        &self,
51    ) -> &'static crate::common::Reg<self::SmrSmci_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::SmrSmci_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0usize),
55            )
56        }
57    }
58
59    #[doc = "Bit Rate Register"]
60    #[inline(always)]
61    pub const fn brr(&self) -> &'static crate::common::Reg<self::Brr_SPEC, crate::common::RW> {
62        unsafe {
63            crate::common::Reg::<self::Brr_SPEC, crate::common::RW>::from_ptr(
64                self._svd2pac_as_ptr().add(1usize),
65            )
66        }
67    }
68
69    #[doc = "Serial Control Register (SCMR.SMIF = 0)"]
70    #[inline(always)]
71    pub const fn scr(&self) -> &'static crate::common::Reg<self::Scr_SPEC, crate::common::RW> {
72        unsafe {
73            crate::common::Reg::<self::Scr_SPEC, crate::common::RW>::from_ptr(
74                self._svd2pac_as_ptr().add(2usize),
75            )
76        }
77    }
78
79    #[doc = "Serial Control Register (SCMR.SMIF =1)"]
80    #[inline(always)]
81    pub const fn scr_smci(
82        &self,
83    ) -> &'static crate::common::Reg<self::ScrSmci_SPEC, crate::common::RW> {
84        unsafe {
85            crate::common::Reg::<self::ScrSmci_SPEC, crate::common::RW>::from_ptr(
86                self._svd2pac_as_ptr().add(2usize),
87            )
88        }
89    }
90
91    #[doc = "Transmit Data Register"]
92    #[inline(always)]
93    pub const fn tdr(&self) -> &'static crate::common::Reg<self::Tdr_SPEC, crate::common::RW> {
94        unsafe {
95            crate::common::Reg::<self::Tdr_SPEC, crate::common::RW>::from_ptr(
96                self._svd2pac_as_ptr().add(3usize),
97            )
98        }
99    }
100
101    #[doc = "Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)"]
102    #[inline(always)]
103    pub const fn ssr(&self) -> &'static crate::common::Reg<self::Ssr_SPEC, crate::common::RW> {
104        unsafe {
105            crate::common::Reg::<self::Ssr_SPEC, crate::common::RW>::from_ptr(
106                self._svd2pac_as_ptr().add(4usize),
107            )
108        }
109    }
110
111    #[doc = "Serial Status Register(SCMR.SMIF = 1)"]
112    #[inline(always)]
113    pub const fn ssr_smci(
114        &self,
115    ) -> &'static crate::common::Reg<self::SsrSmci_SPEC, crate::common::RW> {
116        unsafe {
117            crate::common::Reg::<self::SsrSmci_SPEC, crate::common::RW>::from_ptr(
118                self._svd2pac_as_ptr().add(4usize),
119            )
120        }
121    }
122
123    #[doc = "Receive Data Register"]
124    #[inline(always)]
125    pub const fn rdr(&self) -> &'static crate::common::Reg<self::Rdr_SPEC, crate::common::R> {
126        unsafe {
127            crate::common::Reg::<self::Rdr_SPEC, crate::common::R>::from_ptr(
128                self._svd2pac_as_ptr().add(5usize),
129            )
130        }
131    }
132
133    #[doc = "Smart Card Mode Register"]
134    #[inline(always)]
135    pub const fn scmr(&self) -> &'static crate::common::Reg<self::Scmr_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::Scmr_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(6usize),
139            )
140        }
141    }
142
143    #[doc = "Serial Extended Mode Register"]
144    #[inline(always)]
145    pub const fn semr(&self) -> &'static crate::common::Reg<self::Semr_SPEC, crate::common::RW> {
146        unsafe {
147            crate::common::Reg::<self::Semr_SPEC, crate::common::RW>::from_ptr(
148                self._svd2pac_as_ptr().add(7usize),
149            )
150        }
151    }
152
153    #[doc = "Noise Filter Setting Register"]
154    #[inline(always)]
155    pub const fn snfr(&self) -> &'static crate::common::Reg<self::Snfr_SPEC, crate::common::RW> {
156        unsafe {
157            crate::common::Reg::<self::Snfr_SPEC, crate::common::RW>::from_ptr(
158                self._svd2pac_as_ptr().add(8usize),
159            )
160        }
161    }
162
163    #[doc = "I2C Mode Register 1"]
164    #[inline(always)]
165    pub const fn simr1(&self) -> &'static crate::common::Reg<self::Simr1_SPEC, crate::common::RW> {
166        unsafe {
167            crate::common::Reg::<self::Simr1_SPEC, crate::common::RW>::from_ptr(
168                self._svd2pac_as_ptr().add(9usize),
169            )
170        }
171    }
172
173    #[doc = "I2C Mode Register 2"]
174    #[inline(always)]
175    pub const fn simr2(&self) -> &'static crate::common::Reg<self::Simr2_SPEC, crate::common::RW> {
176        unsafe {
177            crate::common::Reg::<self::Simr2_SPEC, crate::common::RW>::from_ptr(
178                self._svd2pac_as_ptr().add(10usize),
179            )
180        }
181    }
182
183    #[doc = "IIC Mode Register 3"]
184    #[inline(always)]
185    pub const fn simr3(&self) -> &'static crate::common::Reg<self::Simr3_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::Simr3_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(11usize),
189            )
190        }
191    }
192
193    #[doc = "IIC Status Register"]
194    #[inline(always)]
195    pub const fn sisr(&self) -> &'static crate::common::Reg<self::Sisr_SPEC, crate::common::R> {
196        unsafe {
197            crate::common::Reg::<self::Sisr_SPEC, crate::common::R>::from_ptr(
198                self._svd2pac_as_ptr().add(12usize),
199            )
200        }
201    }
202
203    #[doc = "SPI Mode Register"]
204    #[inline(always)]
205    pub const fn spmr(&self) -> &'static crate::common::Reg<self::Spmr_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Spmr_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(13usize),
209            )
210        }
211    }
212
213    #[doc = "Transmit 9-bit Data Register"]
214    #[inline(always)]
215    pub const fn tdrhl(&self) -> &'static crate::common::Reg<self::Tdrhl_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Tdrhl_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(14usize),
219            )
220        }
221    }
222
223    #[doc = "Receive 9-bit Data Register"]
224    #[inline(always)]
225    pub const fn rdrhl(&self) -> &'static crate::common::Reg<self::Rdrhl_SPEC, crate::common::R> {
226        unsafe {
227            crate::common::Reg::<self::Rdrhl_SPEC, crate::common::R>::from_ptr(
228                self._svd2pac_as_ptr().add(16usize),
229            )
230        }
231    }
232
233    #[doc = "Modulation Duty Register"]
234    #[inline(always)]
235    pub const fn mddr(&self) -> &'static crate::common::Reg<self::Mddr_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Mddr_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(18usize),
239            )
240        }
241    }
242
243    #[doc = "Data Compare Match Control Register"]
244    #[inline(always)]
245    pub const fn dccr(&self) -> &'static crate::common::Reg<self::Dccr_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::Dccr_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(19usize),
249            )
250        }
251    }
252
253    #[doc = "Compare Match Data Register"]
254    #[inline(always)]
255    pub const fn cdr(&self) -> &'static crate::common::Reg<self::Cdr_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Cdr_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(26usize),
259            )
260        }
261    }
262
263    #[doc = "Serial Port Register"]
264    #[inline(always)]
265    pub const fn sptr(&self) -> &'static crate::common::Reg<self::Sptr_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::Sptr_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(28usize),
269            )
270        }
271    }
272}
273#[doc(hidden)]
274#[derive(Copy, Clone, Eq, PartialEq)]
275pub struct Smr_SPEC;
276impl crate::sealed::RegSpec for Smr_SPEC {
277    type DataType = u8;
278}
279
280#[doc = "Serial Mode Register (SCMR.SMIF = 0)"]
281pub type Smr = crate::RegValueT<Smr_SPEC>;
282
283impl Smr {
284    #[doc = "Communications Mode"]
285    #[inline(always)]
286    pub fn cm(
287        self,
288    ) -> crate::common::RegisterField<7, 0x1, 1, 0, smr::Cm, smr::Cm, Smr_SPEC, crate::common::RW>
289    {
290        crate::common::RegisterField::<7,0x1,1,0,smr::Cm,smr::Cm,Smr_SPEC,crate::common::RW>::from_register(self,0)
291    }
292
293    #[doc = "Character Length(Valid only in asynchronous mode)"]
294    #[inline(always)]
295    pub fn chr(
296        self,
297    ) -> crate::common::RegisterField<6, 0x1, 1, 0, smr::Chr, smr::Chr, Smr_SPEC, crate::common::RW>
298    {
299        crate::common::RegisterField::<6,0x1,1,0,smr::Chr,smr::Chr,Smr_SPEC,crate::common::RW>::from_register(self,0)
300    }
301
302    #[doc = "Parity Enable(Valid only in asynchronous mode)"]
303    #[inline(always)]
304    pub fn pe(
305        self,
306    ) -> crate::common::RegisterField<5, 0x1, 1, 0, smr::Pe, smr::Pe, Smr_SPEC, crate::common::RW>
307    {
308        crate::common::RegisterField::<5,0x1,1,0,smr::Pe,smr::Pe,Smr_SPEC,crate::common::RW>::from_register(self,0)
309    }
310
311    #[doc = "Parity Mode (Valid only when the PE bit is 1)"]
312    #[inline(always)]
313    pub fn pm(
314        self,
315    ) -> crate::common::RegisterField<4, 0x1, 1, 0, smr::Pm, smr::Pm, Smr_SPEC, crate::common::RW>
316    {
317        crate::common::RegisterField::<4,0x1,1,0,smr::Pm,smr::Pm,Smr_SPEC,crate::common::RW>::from_register(self,0)
318    }
319
320    #[doc = "Stop Bit Length(Valid only in asynchronous mode)"]
321    #[inline(always)]
322    pub fn stop(
323        self,
324    ) -> crate::common::RegisterField<3, 0x1, 1, 0, smr::Stop, smr::Stop, Smr_SPEC, crate::common::RW>
325    {
326        crate::common::RegisterField::<
327            3,
328            0x1,
329            1,
330            0,
331            smr::Stop,
332            smr::Stop,
333            Smr_SPEC,
334            crate::common::RW,
335        >::from_register(self, 0)
336    }
337
338    #[doc = "Multi-Processor Mode(Valid only in asynchronous mode)"]
339    #[inline(always)]
340    pub fn mp(
341        self,
342    ) -> crate::common::RegisterField<2, 0x1, 1, 0, smr::Mp, smr::Mp, Smr_SPEC, crate::common::RW>
343    {
344        crate::common::RegisterField::<2,0x1,1,0,smr::Mp,smr::Mp,Smr_SPEC,crate::common::RW>::from_register(self,0)
345    }
346
347    #[doc = "Clock Select"]
348    #[inline(always)]
349    pub fn cks(
350        self,
351    ) -> crate::common::RegisterField<0, 0x3, 1, 0, smr::Cks, smr::Cks, Smr_SPEC, crate::common::RW>
352    {
353        crate::common::RegisterField::<0,0x3,1,0,smr::Cks,smr::Cks,Smr_SPEC,crate::common::RW>::from_register(self,0)
354    }
355}
356impl ::core::default::Default for Smr {
357    #[inline(always)]
358    fn default() -> Smr {
359        <crate::RegValueT<Smr_SPEC> as RegisterValue<_>>::new(0)
360    }
361}
362pub mod smr {
363
364    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
365    pub struct Cm_SPEC;
366    pub type Cm = crate::EnumBitfieldStruct<u8, Cm_SPEC>;
367    impl Cm {
368        #[doc = "Asynchronous mode or simple I2C mode"]
369        pub const _0: Self = Self::new(0);
370
371        #[doc = "Clock synchronous mode"]
372        pub const _1: Self = Self::new(1);
373    }
374    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
375    pub struct Chr_SPEC;
376    pub type Chr = crate::EnumBitfieldStruct<u8, Chr_SPEC>;
377    impl Chr {
378        #[doc = "Transmit/receive in 9-bit data length(SCMR.CHR1=0) /  in 8bit data length(SCMR.CHR1=1)"]
379        pub const _0: Self = Self::new(0);
380
381        #[doc = "Transmit/receive in 9-bit data length(SCMR.CHR1=0) /  in 7bit data length(SCMR.CHR1=1)"]
382        pub const _1: Self = Self::new(1);
383    }
384    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
385    pub struct Pe_SPEC;
386    pub type Pe = crate::EnumBitfieldStruct<u8, Pe_SPEC>;
387    impl Pe {
388        #[doc = "Parity bit addition is not performed (transmitting) / Parity bit checking is not performed ( receiving )"]
389        pub const _0: Self = Self::new(0);
390
391        #[doc = "The parity bit is added (transmitting) / The parity bit is checked (receiving)"]
392        pub const _1: Self = Self::new(1);
393    }
394    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
395    pub struct Pm_SPEC;
396    pub type Pm = crate::EnumBitfieldStruct<u8, Pm_SPEC>;
397    impl Pm {
398        #[doc = "Selects even parity"]
399        pub const _0: Self = Self::new(0);
400
401        #[doc = "Selects odd parity"]
402        pub const _1: Self = Self::new(1);
403    }
404    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
405    pub struct Stop_SPEC;
406    pub type Stop = crate::EnumBitfieldStruct<u8, Stop_SPEC>;
407    impl Stop {
408        #[doc = "1 stop bit"]
409        pub const _0: Self = Self::new(0);
410
411        #[doc = "2 stop bits"]
412        pub const _1: Self = Self::new(1);
413    }
414    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
415    pub struct Mp_SPEC;
416    pub type Mp = crate::EnumBitfieldStruct<u8, Mp_SPEC>;
417    impl Mp {
418        #[doc = "Multi-processor communications function is disabled"]
419        pub const _0: Self = Self::new(0);
420
421        #[doc = "Multi-processor communications function is enabled"]
422        pub const _1: Self = Self::new(1);
423    }
424    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
425    pub struct Cks_SPEC;
426    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
427    impl Cks {
428        #[doc = "PCLK clock"]
429        pub const _00: Self = Self::new(0);
430
431        #[doc = "PCLK/4 clock"]
432        pub const _01: Self = Self::new(1);
433
434        #[doc = "PCLK/16 clock"]
435        pub const _10: Self = Self::new(2);
436
437        #[doc = "PCLK/64 clock"]
438        pub const _11: Self = Self::new(3);
439    }
440}
441#[doc(hidden)]
442#[derive(Copy, Clone, Eq, PartialEq)]
443pub struct SmrSmci_SPEC;
444impl crate::sealed::RegSpec for SmrSmci_SPEC {
445    type DataType = u8;
446}
447
448#[doc = "Serial mode register (SCMR.SMIF = 1)"]
449pub type SmrSmci = crate::RegValueT<SmrSmci_SPEC>;
450
451impl SmrSmci {
452    #[doc = "GSM Mode"]
453    #[inline(always)]
454    pub fn gm(
455        self,
456    ) -> crate::common::RegisterField<
457        7,
458        0x1,
459        1,
460        0,
461        smr_smci::Gm,
462        smr_smci::Gm,
463        SmrSmci_SPEC,
464        crate::common::RW,
465    > {
466        crate::common::RegisterField::<
467            7,
468            0x1,
469            1,
470            0,
471            smr_smci::Gm,
472            smr_smci::Gm,
473            SmrSmci_SPEC,
474            crate::common::RW,
475        >::from_register(self, 0)
476    }
477
478    #[doc = "Block Transfer Mode"]
479    #[inline(always)]
480    pub fn blk(
481        self,
482    ) -> crate::common::RegisterField<
483        6,
484        0x1,
485        1,
486        0,
487        smr_smci::Blk,
488        smr_smci::Blk,
489        SmrSmci_SPEC,
490        crate::common::RW,
491    > {
492        crate::common::RegisterField::<
493            6,
494            0x1,
495            1,
496            0,
497            smr_smci::Blk,
498            smr_smci::Blk,
499            SmrSmci_SPEC,
500            crate::common::RW,
501        >::from_register(self, 0)
502    }
503
504    #[doc = "Parity Enable(Valid only in asynchronous mode)"]
505    #[inline(always)]
506    pub fn pe(
507        self,
508    ) -> crate::common::RegisterField<
509        5,
510        0x1,
511        1,
512        0,
513        smr_smci::Pe,
514        smr_smci::Pe,
515        SmrSmci_SPEC,
516        crate::common::RW,
517    > {
518        crate::common::RegisterField::<
519            5,
520            0x1,
521            1,
522            0,
523            smr_smci::Pe,
524            smr_smci::Pe,
525            SmrSmci_SPEC,
526            crate::common::RW,
527        >::from_register(self, 0)
528    }
529
530    #[doc = "Parity Mode (Valid only when the PE bit is 1)"]
531    #[inline(always)]
532    pub fn pm(
533        self,
534    ) -> crate::common::RegisterField<
535        4,
536        0x1,
537        1,
538        0,
539        smr_smci::Pm,
540        smr_smci::Pm,
541        SmrSmci_SPEC,
542        crate::common::RW,
543    > {
544        crate::common::RegisterField::<
545            4,
546            0x1,
547            1,
548            0,
549            smr_smci::Pm,
550            smr_smci::Pm,
551            SmrSmci_SPEC,
552            crate::common::RW,
553        >::from_register(self, 0)
554    }
555
556    #[doc = "Base Clock Pulse"]
557    #[inline(always)]
558    pub fn bcp(
559        self,
560    ) -> crate::common::RegisterField<
561        2,
562        0x3,
563        1,
564        0,
565        smr_smci::Bcp,
566        smr_smci::Bcp,
567        SmrSmci_SPEC,
568        crate::common::RW,
569    > {
570        crate::common::RegisterField::<
571            2,
572            0x3,
573            1,
574            0,
575            smr_smci::Bcp,
576            smr_smci::Bcp,
577            SmrSmci_SPEC,
578            crate::common::RW,
579        >::from_register(self, 0)
580    }
581
582    #[doc = "Clock Select"]
583    #[inline(always)]
584    pub fn cks(
585        self,
586    ) -> crate::common::RegisterField<
587        0,
588        0x3,
589        1,
590        0,
591        smr_smci::Cks,
592        smr_smci::Cks,
593        SmrSmci_SPEC,
594        crate::common::RW,
595    > {
596        crate::common::RegisterField::<
597            0,
598            0x3,
599            1,
600            0,
601            smr_smci::Cks,
602            smr_smci::Cks,
603            SmrSmci_SPEC,
604            crate::common::RW,
605        >::from_register(self, 0)
606    }
607}
608impl ::core::default::Default for SmrSmci {
609    #[inline(always)]
610    fn default() -> SmrSmci {
611        <crate::RegValueT<SmrSmci_SPEC> as RegisterValue<_>>::new(0)
612    }
613}
614pub mod smr_smci {
615
616    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
617    pub struct Gm_SPEC;
618    pub type Gm = crate::EnumBitfieldStruct<u8, Gm_SPEC>;
619    impl Gm {
620        #[doc = "Normal mode operation"]
621        pub const _0: Self = Self::new(0);
622
623        #[doc = "GSM mode operation"]
624        pub const _1: Self = Self::new(1);
625    }
626    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
627    pub struct Blk_SPEC;
628    pub type Blk = crate::EnumBitfieldStruct<u8, Blk_SPEC>;
629    impl Blk {
630        #[doc = "Normal mode operation"]
631        pub const _0: Self = Self::new(0);
632
633        #[doc = "Block transfer mode operation"]
634        pub const _1: Self = Self::new(1);
635    }
636    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
637    pub struct Pe_SPEC;
638    pub type Pe = crate::EnumBitfieldStruct<u8, Pe_SPEC>;
639    impl Pe {
640        #[doc = "Setting Prohibited"]
641        pub const _0: Self = Self::new(0);
642
643        #[doc = "Set this bit to 1 in smart card interface mode."]
644        pub const _1: Self = Self::new(1);
645    }
646    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
647    pub struct Pm_SPEC;
648    pub type Pm = crate::EnumBitfieldStruct<u8, Pm_SPEC>;
649    impl Pm {
650        #[doc = "Selects even parity"]
651        pub const _0: Self = Self::new(0);
652
653        #[doc = "Selects odd parity"]
654        pub const _1: Self = Self::new(1);
655    }
656    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
657    pub struct Bcp_SPEC;
658    pub type Bcp = crate::EnumBitfieldStruct<u8, Bcp_SPEC>;
659    impl Bcp {
660        #[doc = "93 clock cycles(S=93) (SCMR.BCP2=0) / 32 clock cycles(S=32)  (SCMR.BCP2=1)"]
661        pub const _00: Self = Self::new(0);
662
663        #[doc = "128 clock cycles(S=128) (SCMR.BCP2=0) / 64 clock cycles(S=64) (SCMR.BCP2=1)"]
664        pub const _01: Self = Self::new(1);
665
666        #[doc = "186 clock cycles(S=186) (SCMR.BCP2=0) / 372 clock cycles(S=372) (SCMR.BCP2=1)"]
667        pub const _10: Self = Self::new(2);
668
669        #[doc = "512 clock cycles(S=512) (SCMR.BCP2=0) / 256 clock cycles(S=256) (SCMR.BCP2=1)"]
670        pub const _11: Self = Self::new(3);
671    }
672    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
673    pub struct Cks_SPEC;
674    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
675    impl Cks {
676        #[doc = "PCLK clock"]
677        pub const _00: Self = Self::new(0);
678
679        #[doc = "PCLK/4 clock"]
680        pub const _01: Self = Self::new(1);
681
682        #[doc = "PCLK/16 clock"]
683        pub const _10: Self = Self::new(2);
684
685        #[doc = "PCLK/64 clock"]
686        pub const _11: Self = Self::new(3);
687    }
688}
689#[doc(hidden)]
690#[derive(Copy, Clone, Eq, PartialEq)]
691pub struct Brr_SPEC;
692impl crate::sealed::RegSpec for Brr_SPEC {
693    type DataType = u8;
694}
695
696#[doc = "Bit Rate Register"]
697pub type Brr = crate::RegValueT<Brr_SPEC>;
698
699impl Brr {
700    #[doc = "BRR is an 8-bit register that adjusts the bit rate."]
701    #[inline(always)]
702    pub fn brr(
703        self,
704    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Brr_SPEC, crate::common::RW> {
705        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Brr_SPEC,crate::common::RW>::from_register(self,0)
706    }
707}
708impl ::core::default::Default for Brr {
709    #[inline(always)]
710    fn default() -> Brr {
711        <crate::RegValueT<Brr_SPEC> as RegisterValue<_>>::new(255)
712    }
713}
714
715#[doc(hidden)]
716#[derive(Copy, Clone, Eq, PartialEq)]
717pub struct Scr_SPEC;
718impl crate::sealed::RegSpec for Scr_SPEC {
719    type DataType = u8;
720}
721
722#[doc = "Serial Control Register (SCMR.SMIF = 0)"]
723pub type Scr = crate::RegValueT<Scr_SPEC>;
724
725impl Scr {
726    #[doc = "Transmit Interrupt Enable"]
727    #[inline(always)]
728    pub fn tie(
729        self,
730    ) -> crate::common::RegisterField<7, 0x1, 1, 0, scr::Tie, scr::Tie, Scr_SPEC, crate::common::RW>
731    {
732        crate::common::RegisterField::<7,0x1,1,0,scr::Tie,scr::Tie,Scr_SPEC,crate::common::RW>::from_register(self,0)
733    }
734
735    #[doc = "Receive Interrupt Enable"]
736    #[inline(always)]
737    pub fn rie(
738        self,
739    ) -> crate::common::RegisterField<6, 0x1, 1, 0, scr::Rie, scr::Rie, Scr_SPEC, crate::common::RW>
740    {
741        crate::common::RegisterField::<6,0x1,1,0,scr::Rie,scr::Rie,Scr_SPEC,crate::common::RW>::from_register(self,0)
742    }
743
744    #[doc = "Transmit Enable"]
745    #[inline(always)]
746    pub fn te(
747        self,
748    ) -> crate::common::RegisterField<5, 0x1, 1, 0, scr::Te, scr::Te, Scr_SPEC, crate::common::RW>
749    {
750        crate::common::RegisterField::<5,0x1,1,0,scr::Te,scr::Te,Scr_SPEC,crate::common::RW>::from_register(self,0)
751    }
752
753    #[doc = "Receive Enable"]
754    #[inline(always)]
755    pub fn re(
756        self,
757    ) -> crate::common::RegisterField<4, 0x1, 1, 0, scr::Re, scr::Re, Scr_SPEC, crate::common::RW>
758    {
759        crate::common::RegisterField::<4,0x1,1,0,scr::Re,scr::Re,Scr_SPEC,crate::common::RW>::from_register(self,0)
760    }
761
762    #[doc = "Multi-Processor Interrupt Enable(Valid in asynchronous mode when SMR.MP = 1)"]
763    #[inline(always)]
764    pub fn mpie(
765        self,
766    ) -> crate::common::RegisterField<3, 0x1, 1, 0, scr::Mpie, scr::Mpie, Scr_SPEC, crate::common::RW>
767    {
768        crate::common::RegisterField::<
769            3,
770            0x1,
771            1,
772            0,
773            scr::Mpie,
774            scr::Mpie,
775            Scr_SPEC,
776            crate::common::RW,
777        >::from_register(self, 0)
778    }
779
780    #[doc = "Transmit End Interrupt Enable"]
781    #[inline(always)]
782    pub fn teie(
783        self,
784    ) -> crate::common::RegisterField<2, 0x1, 1, 0, scr::Teie, scr::Teie, Scr_SPEC, crate::common::RW>
785    {
786        crate::common::RegisterField::<
787            2,
788            0x1,
789            1,
790            0,
791            scr::Teie,
792            scr::Teie,
793            Scr_SPEC,
794            crate::common::RW,
795        >::from_register(self, 0)
796    }
797
798    #[doc = "Clock Enable"]
799    #[inline(always)]
800    pub fn cke(
801        self,
802    ) -> crate::common::RegisterField<0, 0x3, 1, 0, scr::Cke, scr::Cke, Scr_SPEC, crate::common::RW>
803    {
804        crate::common::RegisterField::<0,0x3,1,0,scr::Cke,scr::Cke,Scr_SPEC,crate::common::RW>::from_register(self,0)
805    }
806}
807impl ::core::default::Default for Scr {
808    #[inline(always)]
809    fn default() -> Scr {
810        <crate::RegValueT<Scr_SPEC> as RegisterValue<_>>::new(0)
811    }
812}
813pub mod scr {
814
815    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
816    pub struct Tie_SPEC;
817    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
818    impl Tie {
819        #[doc = "TXI interrupt request is disabled"]
820        pub const _0: Self = Self::new(0);
821
822        #[doc = "TXI interrupt request is enabled"]
823        pub const _1: Self = Self::new(1);
824    }
825    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
826    pub struct Rie_SPEC;
827    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
828    impl Rie {
829        #[doc = "RXI and ERI interrupt requests are disabled"]
830        pub const _0: Self = Self::new(0);
831
832        #[doc = "RXI and ERI interrupt requests are enabled"]
833        pub const _1: Self = Self::new(1);
834    }
835    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
836    pub struct Te_SPEC;
837    pub type Te = crate::EnumBitfieldStruct<u8, Te_SPEC>;
838    impl Te {
839        #[doc = "Serial transmission is disabled"]
840        pub const _0: Self = Self::new(0);
841
842        #[doc = "Serial transmission is enabled"]
843        pub const _1: Self = Self::new(1);
844    }
845    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
846    pub struct Re_SPEC;
847    pub type Re = crate::EnumBitfieldStruct<u8, Re_SPEC>;
848    impl Re {
849        #[doc = "Serial reception is disabled"]
850        pub const _0: Self = Self::new(0);
851
852        #[doc = "Serial reception is enabled"]
853        pub const _1: Self = Self::new(1);
854    }
855    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
856    pub struct Mpie_SPEC;
857    pub type Mpie = crate::EnumBitfieldStruct<u8, Mpie_SPEC>;
858    impl Mpie {
859        #[doc = "Normal reception"]
860        pub const _0: Self = Self::new(0);
861
862        #[doc = "When the data with the multi-processor bit set to 0 is received, the data is not read, and setting the status flags RDRF,ORER and FER in SSR to 1 is disabled. When the data with the multiprocessor bit set to 1 is received, the MPIE bit is automatically cleared to 0, and normal reception is resumed."]
863        pub const _1: Self = Self::new(1);
864    }
865    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
866    pub struct Teie_SPEC;
867    pub type Teie = crate::EnumBitfieldStruct<u8, Teie_SPEC>;
868    impl Teie {
869        #[doc = "TEI interrupt request is disabled"]
870        pub const _0: Self = Self::new(0);
871
872        #[doc = "TEI interrupt request is enabled"]
873        pub const _1: Self = Self::new(1);
874    }
875    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
876    pub struct Cke_SPEC;
877    pub type Cke = crate::EnumBitfieldStruct<u8, Cke_SPEC>;
878    impl Cke {
879        #[doc = "The SCKn pin is available for use as an I/O port in accord with the I/O port settings.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)"]
880        pub const _00: Self = Self::new(0);
881
882        #[doc = "The clock with the same frequency as the bit rate is output from the SCKn pin.(Asynchronous mode) / The SCKn pin functions as the clock output pin(Clock synchronous mode)"]
883        pub const _01: Self = Self::new(1);
884    }
885}
886#[doc(hidden)]
887#[derive(Copy, Clone, Eq, PartialEq)]
888pub struct ScrSmci_SPEC;
889impl crate::sealed::RegSpec for ScrSmci_SPEC {
890    type DataType = u8;
891}
892
893#[doc = "Serial Control Register (SCMR.SMIF =1)"]
894pub type ScrSmci = crate::RegValueT<ScrSmci_SPEC>;
895
896impl ScrSmci {
897    #[doc = "Transmit Interrupt Enable"]
898    #[inline(always)]
899    pub fn tie(
900        self,
901    ) -> crate::common::RegisterField<
902        7,
903        0x1,
904        1,
905        0,
906        scr_smci::Tie,
907        scr_smci::Tie,
908        ScrSmci_SPEC,
909        crate::common::RW,
910    > {
911        crate::common::RegisterField::<
912            7,
913            0x1,
914            1,
915            0,
916            scr_smci::Tie,
917            scr_smci::Tie,
918            ScrSmci_SPEC,
919            crate::common::RW,
920        >::from_register(self, 0)
921    }
922
923    #[doc = "Receive Interrupt Enable"]
924    #[inline(always)]
925    pub fn rie(
926        self,
927    ) -> crate::common::RegisterField<
928        6,
929        0x1,
930        1,
931        0,
932        scr_smci::Rie,
933        scr_smci::Rie,
934        ScrSmci_SPEC,
935        crate::common::RW,
936    > {
937        crate::common::RegisterField::<
938            6,
939            0x1,
940            1,
941            0,
942            scr_smci::Rie,
943            scr_smci::Rie,
944            ScrSmci_SPEC,
945            crate::common::RW,
946        >::from_register(self, 0)
947    }
948
949    #[doc = "Transmit Enable"]
950    #[inline(always)]
951    pub fn te(
952        self,
953    ) -> crate::common::RegisterField<
954        5,
955        0x1,
956        1,
957        0,
958        scr_smci::Te,
959        scr_smci::Te,
960        ScrSmci_SPEC,
961        crate::common::RW,
962    > {
963        crate::common::RegisterField::<
964            5,
965            0x1,
966            1,
967            0,
968            scr_smci::Te,
969            scr_smci::Te,
970            ScrSmci_SPEC,
971            crate::common::RW,
972        >::from_register(self, 0)
973    }
974
975    #[doc = "Receive Enable"]
976    #[inline(always)]
977    pub fn re(
978        self,
979    ) -> crate::common::RegisterField<
980        4,
981        0x1,
982        1,
983        0,
984        scr_smci::Re,
985        scr_smci::Re,
986        ScrSmci_SPEC,
987        crate::common::RW,
988    > {
989        crate::common::RegisterField::<
990            4,
991            0x1,
992            1,
993            0,
994            scr_smci::Re,
995            scr_smci::Re,
996            ScrSmci_SPEC,
997            crate::common::RW,
998        >::from_register(self, 0)
999    }
1000
1001    #[doc = "This bit should be 0 in smart card interface mode."]
1002    #[inline(always)]
1003    pub fn mpie(
1004        self,
1005    ) -> crate::common::RegisterFieldBool<3, 1, 0, ScrSmci_SPEC, crate::common::RW> {
1006        crate::common::RegisterFieldBool::<3, 1, 0, ScrSmci_SPEC, crate::common::RW>::from_register(
1007            self, 0,
1008        )
1009    }
1010
1011    #[doc = "This bit should be 0 in smart card interface mode."]
1012    #[inline(always)]
1013    pub fn teie(
1014        self,
1015    ) -> crate::common::RegisterFieldBool<2, 1, 0, ScrSmci_SPEC, crate::common::RW> {
1016        crate::common::RegisterFieldBool::<2, 1, 0, ScrSmci_SPEC, crate::common::RW>::from_register(
1017            self, 0,
1018        )
1019    }
1020
1021    #[doc = "Clock Enable"]
1022    #[inline(always)]
1023    pub fn cke(
1024        self,
1025    ) -> crate::common::RegisterField<
1026        0,
1027        0x3,
1028        1,
1029        0,
1030        scr_smci::Cke,
1031        scr_smci::Cke,
1032        ScrSmci_SPEC,
1033        crate::common::RW,
1034    > {
1035        crate::common::RegisterField::<
1036            0,
1037            0x3,
1038            1,
1039            0,
1040            scr_smci::Cke,
1041            scr_smci::Cke,
1042            ScrSmci_SPEC,
1043            crate::common::RW,
1044        >::from_register(self, 0)
1045    }
1046}
1047impl ::core::default::Default for ScrSmci {
1048    #[inline(always)]
1049    fn default() -> ScrSmci {
1050        <crate::RegValueT<ScrSmci_SPEC> as RegisterValue<_>>::new(0)
1051    }
1052}
1053pub mod scr_smci {
1054
1055    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1056    pub struct Tie_SPEC;
1057    pub type Tie = crate::EnumBitfieldStruct<u8, Tie_SPEC>;
1058    impl Tie {
1059        #[doc = "A TXI interrupt request is disabled"]
1060        pub const _0: Self = Self::new(0);
1061
1062        #[doc = "A TXI interrupt request is enabled"]
1063        pub const _1: Self = Self::new(1);
1064    }
1065    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1066    pub struct Rie_SPEC;
1067    pub type Rie = crate::EnumBitfieldStruct<u8, Rie_SPEC>;
1068    impl Rie {
1069        #[doc = "RXI and ERI interrupt requests are disabled"]
1070        pub const _0: Self = Self::new(0);
1071
1072        #[doc = "RXI and ERI interrupt requests are enabled"]
1073        pub const _1: Self = Self::new(1);
1074    }
1075    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1076    pub struct Te_SPEC;
1077    pub type Te = crate::EnumBitfieldStruct<u8, Te_SPEC>;
1078    impl Te {
1079        #[doc = "Serial transmission is disabled"]
1080        pub const _0: Self = Self::new(0);
1081
1082        #[doc = "Serial transmission is enabled"]
1083        pub const _1: Self = Self::new(1);
1084    }
1085    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1086    pub struct Re_SPEC;
1087    pub type Re = crate::EnumBitfieldStruct<u8, Re_SPEC>;
1088    impl Re {
1089        #[doc = "Serial reception is disabled"]
1090        pub const _0: Self = Self::new(0);
1091
1092        #[doc = "Serial reception is enabled"]
1093        pub const _1: Self = Self::new(1);
1094    }
1095    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1096    pub struct Cke_SPEC;
1097    pub type Cke = crate::EnumBitfieldStruct<u8, Cke_SPEC>;
1098    impl Cke {
1099        #[doc = "Output disabled(SMR_SMCI.GM=0) / Output fixed low(SMR_SMCI.GM=1)"]
1100        pub const _00: Self = Self::new(0);
1101
1102        #[doc = "Clock Output"]
1103        pub const _01: Self = Self::new(1);
1104
1105        #[doc = "Setting prohibited(SMR_SMCI.GM=0) / Output fixed High(SMR_SMCI.GM=1)"]
1106        pub const _10: Self = Self::new(2);
1107
1108        #[doc = "Setting prohibited(SMR_SMCI.GM=0) / Clock Output(SMR_SMCI.GM=1)"]
1109        pub const _11: Self = Self::new(3);
1110    }
1111}
1112#[doc(hidden)]
1113#[derive(Copy, Clone, Eq, PartialEq)]
1114pub struct Tdr_SPEC;
1115impl crate::sealed::RegSpec for Tdr_SPEC {
1116    type DataType = u8;
1117}
1118
1119#[doc = "Transmit Data Register"]
1120pub type Tdr = crate::RegValueT<Tdr_SPEC>;
1121
1122impl Tdr {
1123    #[doc = "TDR is an 8-bit register that stores transmit data."]
1124    #[inline(always)]
1125    pub fn tdr(
1126        self,
1127    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Tdr_SPEC, crate::common::RW> {
1128        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Tdr_SPEC,crate::common::RW>::from_register(self,0)
1129    }
1130}
1131impl ::core::default::Default for Tdr {
1132    #[inline(always)]
1133    fn default() -> Tdr {
1134        <crate::RegValueT<Tdr_SPEC> as RegisterValue<_>>::new(255)
1135    }
1136}
1137
1138#[doc(hidden)]
1139#[derive(Copy, Clone, Eq, PartialEq)]
1140pub struct Ssr_SPEC;
1141impl crate::sealed::RegSpec for Ssr_SPEC {
1142    type DataType = u8;
1143}
1144
1145#[doc = "Serial Status Register(SCMR.SMIF = 0 and FCR.FM=0)"]
1146pub type Ssr = crate::RegValueT<Ssr_SPEC>;
1147
1148impl Ssr {
1149    #[doc = "Transmit Data Empty Flag"]
1150    #[inline(always)]
1151    pub fn tdre(
1152        self,
1153    ) -> crate::common::RegisterField<7, 0x1, 1, 0, ssr::Tdre, ssr::Tdre, Ssr_SPEC, crate::common::RW>
1154    {
1155        crate::common::RegisterField::<
1156            7,
1157            0x1,
1158            1,
1159            0,
1160            ssr::Tdre,
1161            ssr::Tdre,
1162            Ssr_SPEC,
1163            crate::common::RW,
1164        >::from_register(self, 0)
1165    }
1166
1167    #[doc = "Receive Data Full Flag"]
1168    #[inline(always)]
1169    pub fn rdrf(
1170        self,
1171    ) -> crate::common::RegisterField<6, 0x1, 1, 0, ssr::Rdrf, ssr::Rdrf, Ssr_SPEC, crate::common::RW>
1172    {
1173        crate::common::RegisterField::<
1174            6,
1175            0x1,
1176            1,
1177            0,
1178            ssr::Rdrf,
1179            ssr::Rdrf,
1180            Ssr_SPEC,
1181            crate::common::RW,
1182        >::from_register(self, 0)
1183    }
1184
1185    #[doc = "Overrun Error Flag"]
1186    #[inline(always)]
1187    pub fn orer(
1188        self,
1189    ) -> crate::common::RegisterField<5, 0x1, 1, 0, ssr::Orer, ssr::Orer, Ssr_SPEC, crate::common::RW>
1190    {
1191        crate::common::RegisterField::<
1192            5,
1193            0x1,
1194            1,
1195            0,
1196            ssr::Orer,
1197            ssr::Orer,
1198            Ssr_SPEC,
1199            crate::common::RW,
1200        >::from_register(self, 0)
1201    }
1202
1203    #[doc = "Framing Error Flag"]
1204    #[inline(always)]
1205    pub fn fer(
1206        self,
1207    ) -> crate::common::RegisterField<4, 0x1, 1, 0, ssr::Fer, ssr::Fer, Ssr_SPEC, crate::common::RW>
1208    {
1209        crate::common::RegisterField::<4,0x1,1,0,ssr::Fer,ssr::Fer,Ssr_SPEC,crate::common::RW>::from_register(self,0)
1210    }
1211
1212    #[doc = "Parity Error Flag"]
1213    #[inline(always)]
1214    pub fn per(
1215        self,
1216    ) -> crate::common::RegisterField<3, 0x1, 1, 0, ssr::Per, ssr::Per, Ssr_SPEC, crate::common::RW>
1217    {
1218        crate::common::RegisterField::<3,0x1,1,0,ssr::Per,ssr::Per,Ssr_SPEC,crate::common::RW>::from_register(self,0)
1219    }
1220
1221    #[doc = "Transmit End Flag"]
1222    #[inline(always)]
1223    pub fn tend(
1224        self,
1225    ) -> crate::common::RegisterField<2, 0x1, 1, 0, ssr::Tend, ssr::Tend, Ssr_SPEC, crate::common::R>
1226    {
1227        crate::common::RegisterField::<2,0x1,1,0,ssr::Tend,ssr::Tend,Ssr_SPEC,crate::common::R>::from_register(self,0)
1228    }
1229
1230    #[doc = "Multi-Processor Bit. Value of the multi-processor bit in the reception frame"]
1231    #[inline(always)]
1232    pub fn mpb(
1233        self,
1234    ) -> crate::common::RegisterField<1, 0x1, 1, 0, ssr::Mpb, ssr::Mpb, Ssr_SPEC, crate::common::R>
1235    {
1236        crate::common::RegisterField::<1,0x1,1,0,ssr::Mpb,ssr::Mpb,Ssr_SPEC,crate::common::R>::from_register(self,0)
1237    }
1238
1239    #[doc = "Multi-Processor Bit Transfer. Sets the multi-processor bit for adding to the transmission frame"]
1240    #[inline(always)]
1241    pub fn mpbt(
1242        self,
1243    ) -> crate::common::RegisterField<0, 0x1, 1, 0, ssr::Mpbt, ssr::Mpbt, Ssr_SPEC, crate::common::RW>
1244    {
1245        crate::common::RegisterField::<
1246            0,
1247            0x1,
1248            1,
1249            0,
1250            ssr::Mpbt,
1251            ssr::Mpbt,
1252            Ssr_SPEC,
1253            crate::common::RW,
1254        >::from_register(self, 0)
1255    }
1256}
1257impl ::core::default::Default for Ssr {
1258    #[inline(always)]
1259    fn default() -> Ssr {
1260        <crate::RegValueT<Ssr_SPEC> as RegisterValue<_>>::new(132)
1261    }
1262}
1263pub mod ssr {
1264
1265    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1266    pub struct Tdre_SPEC;
1267    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
1268    impl Tdre {
1269        #[doc = "Transmit data is in TDR register"]
1270        pub const _0: Self = Self::new(0);
1271
1272        #[doc = "No transmit data is in TDR register"]
1273        pub const _1: Self = Self::new(1);
1274    }
1275    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1276    pub struct Rdrf_SPEC;
1277    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
1278    impl Rdrf {
1279        #[doc = "No received data is in RDR register"]
1280        pub const _0: Self = Self::new(0);
1281
1282        #[doc = "Received data is in RDR register"]
1283        pub const _1: Self = Self::new(1);
1284    }
1285    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1286    pub struct Orer_SPEC;
1287    pub type Orer = crate::EnumBitfieldStruct<u8, Orer_SPEC>;
1288    impl Orer {
1289        #[doc = "No overrun error occurred"]
1290        pub const _0: Self = Self::new(0);
1291
1292        #[doc = "An overrun error has occurred"]
1293        pub const _1: Self = Self::new(1);
1294    }
1295    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1296    pub struct Fer_SPEC;
1297    pub type Fer = crate::EnumBitfieldStruct<u8, Fer_SPEC>;
1298    impl Fer {
1299        #[doc = "No framing error occurred"]
1300        pub const _0: Self = Self::new(0);
1301
1302        #[doc = "A framing error has occurred"]
1303        pub const _1: Self = Self::new(1);
1304    }
1305    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1306    pub struct Per_SPEC;
1307    pub type Per = crate::EnumBitfieldStruct<u8, Per_SPEC>;
1308    impl Per {
1309        #[doc = "No parity error occurred"]
1310        pub const _0: Self = Self::new(0);
1311
1312        #[doc = "A parity error has occurred"]
1313        pub const _1: Self = Self::new(1);
1314    }
1315    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1316    pub struct Tend_SPEC;
1317    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
1318    impl Tend {
1319        #[doc = "A character is being transmitted."]
1320        pub const _0: Self = Self::new(0);
1321
1322        #[doc = "Character transfer has been completed."]
1323        pub const _1: Self = Self::new(1);
1324    }
1325    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1326    pub struct Mpb_SPEC;
1327    pub type Mpb = crate::EnumBitfieldStruct<u8, Mpb_SPEC>;
1328    impl Mpb {
1329        #[doc = "Data transmission cycles"]
1330        pub const _0: Self = Self::new(0);
1331
1332        #[doc = "ID transmission cycles"]
1333        pub const _1: Self = Self::new(1);
1334    }
1335    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1336    pub struct Mpbt_SPEC;
1337    pub type Mpbt = crate::EnumBitfieldStruct<u8, Mpbt_SPEC>;
1338    impl Mpbt {
1339        #[doc = "Data transmission cycles"]
1340        pub const _0: Self = Self::new(0);
1341
1342        #[doc = "ID transmission cycles"]
1343        pub const _1: Self = Self::new(1);
1344    }
1345}
1346#[doc(hidden)]
1347#[derive(Copy, Clone, Eq, PartialEq)]
1348pub struct SsrSmci_SPEC;
1349impl crate::sealed::RegSpec for SsrSmci_SPEC {
1350    type DataType = u8;
1351}
1352
1353#[doc = "Serial Status Register(SCMR.SMIF = 1)"]
1354pub type SsrSmci = crate::RegValueT<SsrSmci_SPEC>;
1355
1356impl SsrSmci {
1357    #[doc = "Transmit Data Empty Flag"]
1358    #[inline(always)]
1359    pub fn tdre(
1360        self,
1361    ) -> crate::common::RegisterField<
1362        7,
1363        0x1,
1364        1,
1365        0,
1366        ssr_smci::Tdre,
1367        ssr_smci::Tdre,
1368        SsrSmci_SPEC,
1369        crate::common::RW,
1370    > {
1371        crate::common::RegisterField::<
1372            7,
1373            0x1,
1374            1,
1375            0,
1376            ssr_smci::Tdre,
1377            ssr_smci::Tdre,
1378            SsrSmci_SPEC,
1379            crate::common::RW,
1380        >::from_register(self, 0)
1381    }
1382
1383    #[doc = "Receive Data Full Flag"]
1384    #[inline(always)]
1385    pub fn rdrf(
1386        self,
1387    ) -> crate::common::RegisterField<
1388        6,
1389        0x1,
1390        1,
1391        0,
1392        ssr_smci::Rdrf,
1393        ssr_smci::Rdrf,
1394        SsrSmci_SPEC,
1395        crate::common::RW,
1396    > {
1397        crate::common::RegisterField::<
1398            6,
1399            0x1,
1400            1,
1401            0,
1402            ssr_smci::Rdrf,
1403            ssr_smci::Rdrf,
1404            SsrSmci_SPEC,
1405            crate::common::RW,
1406        >::from_register(self, 0)
1407    }
1408
1409    #[doc = "Overrun Error Flag"]
1410    #[inline(always)]
1411    pub fn orer(
1412        self,
1413    ) -> crate::common::RegisterField<
1414        5,
1415        0x1,
1416        1,
1417        0,
1418        ssr_smci::Orer,
1419        ssr_smci::Orer,
1420        SsrSmci_SPEC,
1421        crate::common::RW,
1422    > {
1423        crate::common::RegisterField::<
1424            5,
1425            0x1,
1426            1,
1427            0,
1428            ssr_smci::Orer,
1429            ssr_smci::Orer,
1430            SsrSmci_SPEC,
1431            crate::common::RW,
1432        >::from_register(self, 0)
1433    }
1434
1435    #[doc = "Error Signal Status Flag"]
1436    #[inline(always)]
1437    pub fn ers(
1438        self,
1439    ) -> crate::common::RegisterField<
1440        4,
1441        0x1,
1442        1,
1443        0,
1444        ssr_smci::Ers,
1445        ssr_smci::Ers,
1446        SsrSmci_SPEC,
1447        crate::common::RW,
1448    > {
1449        crate::common::RegisterField::<
1450            4,
1451            0x1,
1452            1,
1453            0,
1454            ssr_smci::Ers,
1455            ssr_smci::Ers,
1456            SsrSmci_SPEC,
1457            crate::common::RW,
1458        >::from_register(self, 0)
1459    }
1460
1461    #[doc = "Parity Error Flag"]
1462    #[inline(always)]
1463    pub fn per(
1464        self,
1465    ) -> crate::common::RegisterField<
1466        3,
1467        0x1,
1468        1,
1469        0,
1470        ssr_smci::Per,
1471        ssr_smci::Per,
1472        SsrSmci_SPEC,
1473        crate::common::RW,
1474    > {
1475        crate::common::RegisterField::<
1476            3,
1477            0x1,
1478            1,
1479            0,
1480            ssr_smci::Per,
1481            ssr_smci::Per,
1482            SsrSmci_SPEC,
1483            crate::common::RW,
1484        >::from_register(self, 0)
1485    }
1486
1487    #[doc = "Transmit End Flag"]
1488    #[inline(always)]
1489    pub fn tend(
1490        self,
1491    ) -> crate::common::RegisterField<
1492        2,
1493        0x1,
1494        1,
1495        0,
1496        ssr_smci::Tend,
1497        ssr_smci::Tend,
1498        SsrSmci_SPEC,
1499        crate::common::R,
1500    > {
1501        crate::common::RegisterField::<
1502            2,
1503            0x1,
1504            1,
1505            0,
1506            ssr_smci::Tend,
1507            ssr_smci::Tend,
1508            SsrSmci_SPEC,
1509            crate::common::R,
1510        >::from_register(self, 0)
1511    }
1512
1513    #[doc = "Multi-ProcessorThis bit should be 0 in smart card interface mode."]
1514    #[inline(always)]
1515    pub fn mpb(self) -> crate::common::RegisterFieldBool<1, 1, 0, SsrSmci_SPEC, crate::common::R> {
1516        crate::common::RegisterFieldBool::<1, 1, 0, SsrSmci_SPEC, crate::common::R>::from_register(
1517            self, 0,
1518        )
1519    }
1520
1521    #[doc = "Multi-Processor Bit TransferThis bit should be 0 in smart card interface mode."]
1522    #[inline(always)]
1523    pub fn mpbt(
1524        self,
1525    ) -> crate::common::RegisterFieldBool<0, 1, 0, SsrSmci_SPEC, crate::common::RW> {
1526        crate::common::RegisterFieldBool::<0, 1, 0, SsrSmci_SPEC, crate::common::RW>::from_register(
1527            self, 0,
1528        )
1529    }
1530}
1531impl ::core::default::Default for SsrSmci {
1532    #[inline(always)]
1533    fn default() -> SsrSmci {
1534        <crate::RegValueT<SsrSmci_SPEC> as RegisterValue<_>>::new(132)
1535    }
1536}
1537pub mod ssr_smci {
1538
1539    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1540    pub struct Tdre_SPEC;
1541    pub type Tdre = crate::EnumBitfieldStruct<u8, Tdre_SPEC>;
1542    impl Tdre {
1543        #[doc = "Transmit data is in TDR register"]
1544        pub const _0: Self = Self::new(0);
1545
1546        #[doc = "No transmit data is in TDR register"]
1547        pub const _1: Self = Self::new(1);
1548    }
1549    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1550    pub struct Rdrf_SPEC;
1551    pub type Rdrf = crate::EnumBitfieldStruct<u8, Rdrf_SPEC>;
1552    impl Rdrf {
1553        #[doc = "No received data is in RDR register"]
1554        pub const _0: Self = Self::new(0);
1555
1556        #[doc = "Received data is in RDR register"]
1557        pub const _1: Self = Self::new(1);
1558    }
1559    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1560    pub struct Orer_SPEC;
1561    pub type Orer = crate::EnumBitfieldStruct<u8, Orer_SPEC>;
1562    impl Orer {
1563        #[doc = "No overrun error occurred"]
1564        pub const _0: Self = Self::new(0);
1565
1566        #[doc = "An overrun error has occurred"]
1567        pub const _1: Self = Self::new(1);
1568    }
1569    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1570    pub struct Ers_SPEC;
1571    pub type Ers = crate::EnumBitfieldStruct<u8, Ers_SPEC>;
1572    impl Ers {
1573        #[doc = "Low error signal not responded"]
1574        pub const _0: Self = Self::new(0);
1575
1576        #[doc = "Low error signal responded"]
1577        pub const _1: Self = Self::new(1);
1578    }
1579    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1580    pub struct Per_SPEC;
1581    pub type Per = crate::EnumBitfieldStruct<u8, Per_SPEC>;
1582    impl Per {
1583        #[doc = "No parity error occurred"]
1584        pub const _0: Self = Self::new(0);
1585
1586        #[doc = "A parity error has occurred"]
1587        pub const _1: Self = Self::new(1);
1588    }
1589    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1590    pub struct Tend_SPEC;
1591    pub type Tend = crate::EnumBitfieldStruct<u8, Tend_SPEC>;
1592    impl Tend {
1593        #[doc = "A character is being transmitted."]
1594        pub const _0: Self = Self::new(0);
1595
1596        #[doc = "Character transfer has been completed."]
1597        pub const _1: Self = Self::new(1);
1598    }
1599}
1600#[doc(hidden)]
1601#[derive(Copy, Clone, Eq, PartialEq)]
1602pub struct Rdr_SPEC;
1603impl crate::sealed::RegSpec for Rdr_SPEC {
1604    type DataType = u8;
1605}
1606
1607#[doc = "Receive Data Register"]
1608pub type Rdr = crate::RegValueT<Rdr_SPEC>;
1609
1610impl Rdr {
1611    #[doc = "RDR is an 8-bit register that stores receive data."]
1612    #[inline(always)]
1613    pub fn rdr(
1614        self,
1615    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Rdr_SPEC, crate::common::R> {
1616        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Rdr_SPEC,crate::common::R>::from_register(self,0)
1617    }
1618}
1619impl ::core::default::Default for Rdr {
1620    #[inline(always)]
1621    fn default() -> Rdr {
1622        <crate::RegValueT<Rdr_SPEC> as RegisterValue<_>>::new(0)
1623    }
1624}
1625
1626#[doc(hidden)]
1627#[derive(Copy, Clone, Eq, PartialEq)]
1628pub struct Scmr_SPEC;
1629impl crate::sealed::RegSpec for Scmr_SPEC {
1630    type DataType = u8;
1631}
1632
1633#[doc = "Smart Card Mode Register"]
1634pub type Scmr = crate::RegValueT<Scmr_SPEC>;
1635
1636impl Scmr {
1637    #[doc = "Base Clock Pulse 2Selects the number of base clock cycles in combination with the SMR.BCP\\[1:0\\] bits"]
1638    #[inline(always)]
1639    pub fn bcp2(
1640        self,
1641    ) -> crate::common::RegisterField<
1642        7,
1643        0x1,
1644        1,
1645        0,
1646        scmr::Bcp2,
1647        scmr::Bcp2,
1648        Scmr_SPEC,
1649        crate::common::RW,
1650    > {
1651        crate::common::RegisterField::<
1652            7,
1653            0x1,
1654            1,
1655            0,
1656            scmr::Bcp2,
1657            scmr::Bcp2,
1658            Scmr_SPEC,
1659            crate::common::RW,
1660        >::from_register(self, 0)
1661    }
1662
1663    #[doc = "Character Length 1(Only valid in asynchronous mode)"]
1664    #[inline(always)]
1665    pub fn chr1(
1666        self,
1667    ) -> crate::common::RegisterField<
1668        4,
1669        0x1,
1670        1,
1671        0,
1672        scmr::Chr1,
1673        scmr::Chr1,
1674        Scmr_SPEC,
1675        crate::common::RW,
1676    > {
1677        crate::common::RegisterField::<
1678            4,
1679            0x1,
1680            1,
1681            0,
1682            scmr::Chr1,
1683            scmr::Chr1,
1684            Scmr_SPEC,
1685            crate::common::RW,
1686        >::from_register(self, 0)
1687    }
1688
1689    #[doc = "Transmitted/Received Data Transfer DirectionNOTE: The setting is invalid and a fixed data length of 8 bits is used in modes other than asynchronous mode.Set this bit to 1 if operation is to be in simple I2C mode."]
1690    #[inline(always)]
1691    pub fn sdir(
1692        self,
1693    ) -> crate::common::RegisterField<
1694        3,
1695        0x1,
1696        1,
1697        0,
1698        scmr::Sdir,
1699        scmr::Sdir,
1700        Scmr_SPEC,
1701        crate::common::RW,
1702    > {
1703        crate::common::RegisterField::<
1704            3,
1705            0x1,
1706            1,
1707            0,
1708            scmr::Sdir,
1709            scmr::Sdir,
1710            Scmr_SPEC,
1711            crate::common::RW,
1712        >::from_register(self, 0)
1713    }
1714
1715    #[doc = "Transmitted/Received Data InvertSet this bit to 0 if operation is to be in simple I2C mode."]
1716    #[inline(always)]
1717    pub fn sinv(
1718        self,
1719    ) -> crate::common::RegisterField<
1720        2,
1721        0x1,
1722        1,
1723        0,
1724        scmr::Sinv,
1725        scmr::Sinv,
1726        Scmr_SPEC,
1727        crate::common::RW,
1728    > {
1729        crate::common::RegisterField::<
1730            2,
1731            0x1,
1732            1,
1733            0,
1734            scmr::Sinv,
1735            scmr::Sinv,
1736            Scmr_SPEC,
1737            crate::common::RW,
1738        >::from_register(self, 0)
1739    }
1740
1741    #[doc = "This bit is read as 1. The write value should be 1."]
1742    #[inline(always)]
1743    pub fn reserved(
1744        self,
1745    ) -> crate::common::RegisterFieldBool<1, 1, 0, Scmr_SPEC, crate::common::RW> {
1746        crate::common::RegisterFieldBool::<1, 1, 0, Scmr_SPEC, crate::common::RW>::from_register(
1747            self, 0,
1748        )
1749    }
1750
1751    #[doc = "Smart Card Interface Mode Select"]
1752    #[inline(always)]
1753    pub fn smif(
1754        self,
1755    ) -> crate::common::RegisterField<
1756        0,
1757        0x1,
1758        1,
1759        0,
1760        scmr::Smif,
1761        scmr::Smif,
1762        Scmr_SPEC,
1763        crate::common::RW,
1764    > {
1765        crate::common::RegisterField::<
1766            0,
1767            0x1,
1768            1,
1769            0,
1770            scmr::Smif,
1771            scmr::Smif,
1772            Scmr_SPEC,
1773            crate::common::RW,
1774        >::from_register(self, 0)
1775    }
1776}
1777impl ::core::default::Default for Scmr {
1778    #[inline(always)]
1779    fn default() -> Scmr {
1780        <crate::RegValueT<Scmr_SPEC> as RegisterValue<_>>::new(242)
1781    }
1782}
1783pub mod scmr {
1784
1785    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1786    pub struct Bcp2_SPEC;
1787    pub type Bcp2 = crate::EnumBitfieldStruct<u8, Bcp2_SPEC>;
1788    impl Bcp2 {
1789        #[doc = "S=93(SMR.BCP\\[1:0\\]=00), 128(SMR.BCP\\[1:0\\]=01), 186(SMR.BCP\\[1:0\\]=10), 512(SMR.BCP\\[1:0\\]=11)"]
1790        pub const _0: Self = Self::new(0);
1791
1792        #[doc = "S=32(SMR.BCP\\[1:0\\]=00), 64(SMR.BCP\\[1:0\\]=01), 372(SMR.BCP\\[1:0\\]=10), 256(SMR.BCP\\[1:0\\]=11)"]
1793        pub const _1: Self = Self::new(1);
1794    }
1795    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1796    pub struct Chr1_SPEC;
1797    pub type Chr1 = crate::EnumBitfieldStruct<u8, Chr1_SPEC>;
1798    impl Chr1 {
1799        #[doc = "Transmit/receive in 9-bit data length"]
1800        pub const _0: Self = Self::new(0);
1801
1802        #[doc = "Transmit/receive in 8-bit data length(SMR.CHR=0) /  in 7bit data length(SMR.CHR=1)"]
1803        pub const _1: Self = Self::new(1);
1804    }
1805    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1806    pub struct Sdir_SPEC;
1807    pub type Sdir = crate::EnumBitfieldStruct<u8, Sdir_SPEC>;
1808    impl Sdir {
1809        #[doc = "Transfer with LSB first"]
1810        pub const _0: Self = Self::new(0);
1811
1812        #[doc = "Transfer with MSB first"]
1813        pub const _1: Self = Self::new(1);
1814    }
1815    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1816    pub struct Sinv_SPEC;
1817    pub type Sinv = crate::EnumBitfieldStruct<u8, Sinv_SPEC>;
1818    impl Sinv {
1819        #[doc = "TDR contents are transmitted as they are. Receive data is stored as it is in RDR."]
1820        pub const _0: Self = Self::new(0);
1821
1822        #[doc = "TDR contents are inverted before being transmitted. Receive data is stored in inverted form in RDR."]
1823        pub const _1: Self = Self::new(1);
1824    }
1825    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1826    pub struct Smif_SPEC;
1827    pub type Smif = crate::EnumBitfieldStruct<u8, Smif_SPEC>;
1828    impl Smif {
1829        #[doc = "Non-smart card interface mode(Asynchronous mode, clock synchronous mode, simple SPI mode, or simple I2C mode)"]
1830        pub const _0: Self = Self::new(0);
1831
1832        #[doc = "Smart card interface mode"]
1833        pub const _1: Self = Self::new(1);
1834    }
1835}
1836#[doc(hidden)]
1837#[derive(Copy, Clone, Eq, PartialEq)]
1838pub struct Semr_SPEC;
1839impl crate::sealed::RegSpec for Semr_SPEC {
1840    type DataType = u8;
1841}
1842
1843#[doc = "Serial Extended Mode Register"]
1844pub type Semr = crate::RegValueT<Semr_SPEC>;
1845
1846impl Semr {
1847    #[doc = "Asynchronous Start Bit Edge Detection Select(Valid only in asynchronous mode)"]
1848    #[inline(always)]
1849    pub fn rxdesel(
1850        self,
1851    ) -> crate::common::RegisterField<
1852        7,
1853        0x1,
1854        1,
1855        0,
1856        semr::Rxdesel,
1857        semr::Rxdesel,
1858        Semr_SPEC,
1859        crate::common::RW,
1860    > {
1861        crate::common::RegisterField::<
1862            7,
1863            0x1,
1864            1,
1865            0,
1866            semr::Rxdesel,
1867            semr::Rxdesel,
1868            Semr_SPEC,
1869            crate::common::RW,
1870        >::from_register(self, 0)
1871    }
1872
1873    #[doc = "Baud Rate Generator Double-Speed Mode Select(Only valid the CKE\\[1\\] bit in SCR is 0 in asynchronous mode)."]
1874    #[inline(always)]
1875    pub fn bgdm(
1876        self,
1877    ) -> crate::common::RegisterField<
1878        6,
1879        0x1,
1880        1,
1881        0,
1882        semr::Bgdm,
1883        semr::Bgdm,
1884        Semr_SPEC,
1885        crate::common::RW,
1886    > {
1887        crate::common::RegisterField::<
1888            6,
1889            0x1,
1890            1,
1891            0,
1892            semr::Bgdm,
1893            semr::Bgdm,
1894            Semr_SPEC,
1895            crate::common::RW,
1896        >::from_register(self, 0)
1897    }
1898
1899    #[doc = "Digital Noise Filter Function Enable(The NFEN bit should be 0 without simple I2C mode and asynchronous mode.)In asynchronous mode, for RXDn input only. In simple I2C mode, for RXDn/TxDn input."]
1900    #[inline(always)]
1901    pub fn nfen(
1902        self,
1903    ) -> crate::common::RegisterField<
1904        5,
1905        0x1,
1906        1,
1907        0,
1908        semr::Nfen,
1909        semr::Nfen,
1910        Semr_SPEC,
1911        crate::common::RW,
1912    > {
1913        crate::common::RegisterField::<
1914            5,
1915            0x1,
1916            1,
1917            0,
1918            semr::Nfen,
1919            semr::Nfen,
1920            Semr_SPEC,
1921            crate::common::RW,
1922        >::from_register(self, 0)
1923    }
1924
1925    #[doc = "Asynchronous Mode Base Clock Select(Valid only in asynchronous mode)"]
1926    #[inline(always)]
1927    pub fn abcs(
1928        self,
1929    ) -> crate::common::RegisterField<
1930        4,
1931        0x1,
1932        1,
1933        0,
1934        semr::Abcs,
1935        semr::Abcs,
1936        Semr_SPEC,
1937        crate::common::RW,
1938    > {
1939        crate::common::RegisterField::<
1940            4,
1941            0x1,
1942            1,
1943            0,
1944            semr::Abcs,
1945            semr::Abcs,
1946            Semr_SPEC,
1947            crate::common::RW,
1948        >::from_register(self, 0)
1949    }
1950
1951    #[doc = "Asynchronous Mode Extended Base Clock Select1(Valid only in asynchronous mode and SCR.CKE\\[1\\]=0)"]
1952    #[inline(always)]
1953    pub fn abcse(
1954        self,
1955    ) -> crate::common::RegisterField<
1956        3,
1957        0x1,
1958        1,
1959        0,
1960        semr::Abcse,
1961        semr::Abcse,
1962        Semr_SPEC,
1963        crate::common::RW,
1964    > {
1965        crate::common::RegisterField::<
1966            3,
1967            0x1,
1968            1,
1969            0,
1970            semr::Abcse,
1971            semr::Abcse,
1972            Semr_SPEC,
1973            crate::common::RW,
1974        >::from_register(self, 0)
1975    }
1976
1977    #[doc = "Bit Rate Modulation Enable"]
1978    #[inline(always)]
1979    pub fn brme(
1980        self,
1981    ) -> crate::common::RegisterField<
1982        2,
1983        0x1,
1984        1,
1985        0,
1986        semr::Brme,
1987        semr::Brme,
1988        Semr_SPEC,
1989        crate::common::RW,
1990    > {
1991        crate::common::RegisterField::<
1992            2,
1993            0x1,
1994            1,
1995            0,
1996            semr::Brme,
1997            semr::Brme,
1998            Semr_SPEC,
1999            crate::common::RW,
2000        >::from_register(self, 0)
2001    }
2002
2003    #[doc = "These bits are read as 00. The write value should be 00."]
2004    #[inline(always)]
2005    pub fn reserved(
2006        self,
2007    ) -> crate::common::RegisterField<0, 0x3, 1, 0, u8, u8, Semr_SPEC, crate::common::RW> {
2008        crate::common::RegisterField::<0,0x3,1,0,u8,u8,Semr_SPEC,crate::common::RW>::from_register(self,0)
2009    }
2010}
2011impl ::core::default::Default for Semr {
2012    #[inline(always)]
2013    fn default() -> Semr {
2014        <crate::RegValueT<Semr_SPEC> as RegisterValue<_>>::new(0)
2015    }
2016}
2017pub mod semr {
2018
2019    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2020    pub struct Rxdesel_SPEC;
2021    pub type Rxdesel = crate::EnumBitfieldStruct<u8, Rxdesel_SPEC>;
2022    impl Rxdesel {
2023        #[doc = "The low level on the RXDn pin is detected as the start bit."]
2024        pub const _0: Self = Self::new(0);
2025
2026        #[doc = "A falling edge on the RXDn pin is detected as the start bit."]
2027        pub const _1: Self = Self::new(1);
2028    }
2029    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2030    pub struct Bgdm_SPEC;
2031    pub type Bgdm = crate::EnumBitfieldStruct<u8, Bgdm_SPEC>;
2032    impl Bgdm {
2033        #[doc = "Baud rate generator outputs the clock with normal frequency."]
2034        pub const _0: Self = Self::new(0);
2035
2036        #[doc = "Baud rate generator outputs the clock with doubled frequency."]
2037        pub const _1: Self = Self::new(1);
2038    }
2039    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2040    pub struct Nfen_SPEC;
2041    pub type Nfen = crate::EnumBitfieldStruct<u8, Nfen_SPEC>;
2042    impl Nfen {
2043        #[doc = "Noise cancellation function for the RXDn/TXDn input signal is disabled."]
2044        pub const _0: Self = Self::new(0);
2045
2046        #[doc = "Noise cancellation function for the RXDn/TXDn input signal is enabled."]
2047        pub const _1: Self = Self::new(1);
2048    }
2049    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2050    pub struct Abcs_SPEC;
2051    pub type Abcs = crate::EnumBitfieldStruct<u8, Abcs_SPEC>;
2052    impl Abcs {
2053        #[doc = "Selects 16 base clock cycles for 1-bit period."]
2054        pub const _0: Self = Self::new(0);
2055
2056        #[doc = "Selects 8 base clock cycles for 1-bit period."]
2057        pub const _1: Self = Self::new(1);
2058    }
2059    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2060    pub struct Abcse_SPEC;
2061    pub type Abcse = crate::EnumBitfieldStruct<u8, Abcse_SPEC>;
2062    impl Abcse {
2063        #[doc = "Clock cycles for 1-bit period is decided with combination between BGDM and ABCS in SEMR."]
2064        pub const _0: Self = Self::new(0);
2065
2066        #[doc = "Baud rate is 6 base clock cycles for 1-bit period and the clock of a double frequency is output from the baud rate generator."]
2067        pub const _1: Self = Self::new(1);
2068    }
2069    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2070    pub struct Brme_SPEC;
2071    pub type Brme = crate::EnumBitfieldStruct<u8, Brme_SPEC>;
2072    impl Brme {
2073        #[doc = "Bit rate modulation function is disabled."]
2074        pub const _0: Self = Self::new(0);
2075
2076        #[doc = "Bit rate modulation function is enabled."]
2077        pub const _1: Self = Self::new(1);
2078    }
2079}
2080#[doc(hidden)]
2081#[derive(Copy, Clone, Eq, PartialEq)]
2082pub struct Snfr_SPEC;
2083impl crate::sealed::RegSpec for Snfr_SPEC {
2084    type DataType = u8;
2085}
2086
2087#[doc = "Noise Filter Setting Register"]
2088pub type Snfr = crate::RegValueT<Snfr_SPEC>;
2089
2090impl Snfr {
2091    #[doc = "These bits are read as 00000. The write value should be 00000."]
2092    #[inline(always)]
2093    pub fn reserved(
2094        self,
2095    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Snfr_SPEC, crate::common::RW> {
2096        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Snfr_SPEC,crate::common::RW>::from_register(self,0)
2097    }
2098
2099    #[doc = "Noise Filter Clock Select"]
2100    #[inline(always)]
2101    pub fn nfcs(
2102        self,
2103    ) -> crate::common::RegisterField<
2104        0,
2105        0x7,
2106        1,
2107        0,
2108        snfr::Nfcs,
2109        snfr::Nfcs,
2110        Snfr_SPEC,
2111        crate::common::RW,
2112    > {
2113        crate::common::RegisterField::<
2114            0,
2115            0x7,
2116            1,
2117            0,
2118            snfr::Nfcs,
2119            snfr::Nfcs,
2120            Snfr_SPEC,
2121            crate::common::RW,
2122        >::from_register(self, 0)
2123    }
2124}
2125impl ::core::default::Default for Snfr {
2126    #[inline(always)]
2127    fn default() -> Snfr {
2128        <crate::RegValueT<Snfr_SPEC> as RegisterValue<_>>::new(0)
2129    }
2130}
2131pub mod snfr {
2132
2133    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2134    pub struct Nfcs_SPEC;
2135    pub type Nfcs = crate::EnumBitfieldStruct<u8, Nfcs_SPEC>;
2136    impl Nfcs {
2137        #[doc = "The clock signal divided by 1 is used with the noise filter.(In asynchronous mode)"]
2138        pub const _000: Self = Self::new(0);
2139
2140        #[doc = "The clock signal divided by 1 is used with the noise filter.(In simple I2C mode)"]
2141        pub const _001: Self = Self::new(1);
2142
2143        #[doc = "The clock signal divided by 2 is used with the noise filter.(In simple I2C mode)"]
2144        pub const _010: Self = Self::new(2);
2145
2146        #[doc = "The clock signal divided by 4 is used with the noise filter.(In simple I2C mode)"]
2147        pub const _011: Self = Self::new(3);
2148
2149        #[doc = "The clock signal divided by 8 is used with the noise filter.(In simple I2C mode)"]
2150        pub const _100: Self = Self::new(4);
2151    }
2152}
2153#[doc(hidden)]
2154#[derive(Copy, Clone, Eq, PartialEq)]
2155pub struct Simr1_SPEC;
2156impl crate::sealed::RegSpec for Simr1_SPEC {
2157    type DataType = u8;
2158}
2159
2160#[doc = "I2C Mode Register 1"]
2161pub type Simr1 = crate::RegValueT<Simr1_SPEC>;
2162
2163impl Simr1 {
2164    #[doc = "SSDA Delay Output SelectCycles below are of the clock signal from the on-chip baud rate generator."]
2165    #[inline(always)]
2166    pub fn iicdl(
2167        self,
2168    ) -> crate::common::RegisterField<
2169        3,
2170        0x1f,
2171        1,
2172        0,
2173        simr1::Iicdl,
2174        simr1::Iicdl,
2175        Simr1_SPEC,
2176        crate::common::RW,
2177    > {
2178        crate::common::RegisterField::<
2179            3,
2180            0x1f,
2181            1,
2182            0,
2183            simr1::Iicdl,
2184            simr1::Iicdl,
2185            Simr1_SPEC,
2186            crate::common::RW,
2187        >::from_register(self, 0)
2188    }
2189
2190    #[doc = "These bits are read as 00. The write value should be 00."]
2191    #[inline(always)]
2192    pub fn reserved(
2193        self,
2194    ) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, Simr1_SPEC, crate::common::RW> {
2195        crate::common::RegisterField::<1,0x3,1,0,u8,u8,Simr1_SPEC,crate::common::RW>::from_register(self,0)
2196    }
2197
2198    #[doc = "Simple I2C Mode Select"]
2199    #[inline(always)]
2200    pub fn iicm(
2201        self,
2202    ) -> crate::common::RegisterField<
2203        0,
2204        0x1,
2205        1,
2206        0,
2207        simr1::Iicm,
2208        simr1::Iicm,
2209        Simr1_SPEC,
2210        crate::common::RW,
2211    > {
2212        crate::common::RegisterField::<
2213            0,
2214            0x1,
2215            1,
2216            0,
2217            simr1::Iicm,
2218            simr1::Iicm,
2219            Simr1_SPEC,
2220            crate::common::RW,
2221        >::from_register(self, 0)
2222    }
2223}
2224impl ::core::default::Default for Simr1 {
2225    #[inline(always)]
2226    fn default() -> Simr1 {
2227        <crate::RegValueT<Simr1_SPEC> as RegisterValue<_>>::new(0)
2228    }
2229}
2230pub mod simr1 {
2231
2232    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2233    pub struct Iicdl_SPEC;
2234    pub type Iicdl = crate::EnumBitfieldStruct<u8, Iicdl_SPEC>;
2235    impl Iicdl {
2236        #[doc = "No output delay"]
2237        pub const _00000: Self = Self::new(0);
2238    }
2239    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2240    pub struct Iicm_SPEC;
2241    pub type Iicm = crate::EnumBitfieldStruct<u8, Iicm_SPEC>;
2242    impl Iicm {
2243        #[doc = "Asynchronous mode, Multi-processor mode, Clock synchronous mode(SCMR.SMIF=0) /Smart card interface mode(SCMR.SMIF=1)"]
2244        pub const _0: Self = Self::new(0);
2245
2246        #[doc = "Simple I2C mode(SCMR.SMIF=0) / Setting prohibited.(SCMR.SMIF=1)"]
2247        pub const _1: Self = Self::new(1);
2248    }
2249}
2250#[doc(hidden)]
2251#[derive(Copy, Clone, Eq, PartialEq)]
2252pub struct Simr2_SPEC;
2253impl crate::sealed::RegSpec for Simr2_SPEC {
2254    type DataType = u8;
2255}
2256
2257#[doc = "I2C Mode Register 2"]
2258pub type Simr2 = crate::RegValueT<Simr2_SPEC>;
2259
2260impl Simr2 {
2261    #[doc = "ACK Transmission Data"]
2262    #[inline(always)]
2263    pub fn iicackt(
2264        self,
2265    ) -> crate::common::RegisterField<
2266        5,
2267        0x1,
2268        1,
2269        0,
2270        simr2::Iicackt,
2271        simr2::Iicackt,
2272        Simr2_SPEC,
2273        crate::common::RW,
2274    > {
2275        crate::common::RegisterField::<
2276            5,
2277            0x1,
2278            1,
2279            0,
2280            simr2::Iicackt,
2281            simr2::Iicackt,
2282            Simr2_SPEC,
2283            crate::common::RW,
2284        >::from_register(self, 0)
2285    }
2286
2287    #[doc = "These bits are read as 000. The write value should be 000."]
2288    #[inline(always)]
2289    pub fn reserved(
2290        self,
2291    ) -> crate::common::RegisterField<2, 0x7, 1, 0, u8, u8, Simr2_SPEC, crate::common::RW> {
2292        crate::common::RegisterField::<2,0x7,1,0,u8,u8,Simr2_SPEC,crate::common::RW>::from_register(self,0)
2293    }
2294
2295    #[doc = "Clock Synchronization"]
2296    #[inline(always)]
2297    pub fn iiccsc(
2298        self,
2299    ) -> crate::common::RegisterField<
2300        1,
2301        0x1,
2302        1,
2303        0,
2304        simr2::Iiccsc,
2305        simr2::Iiccsc,
2306        Simr2_SPEC,
2307        crate::common::RW,
2308    > {
2309        crate::common::RegisterField::<
2310            1,
2311            0x1,
2312            1,
2313            0,
2314            simr2::Iiccsc,
2315            simr2::Iiccsc,
2316            Simr2_SPEC,
2317            crate::common::RW,
2318        >::from_register(self, 0)
2319    }
2320
2321    #[doc = "I2C Interrupt Mode Select"]
2322    #[inline(always)]
2323    pub fn iicintm(
2324        self,
2325    ) -> crate::common::RegisterField<
2326        0,
2327        0x1,
2328        1,
2329        0,
2330        simr2::Iicintm,
2331        simr2::Iicintm,
2332        Simr2_SPEC,
2333        crate::common::RW,
2334    > {
2335        crate::common::RegisterField::<
2336            0,
2337            0x1,
2338            1,
2339            0,
2340            simr2::Iicintm,
2341            simr2::Iicintm,
2342            Simr2_SPEC,
2343            crate::common::RW,
2344        >::from_register(self, 0)
2345    }
2346}
2347impl ::core::default::Default for Simr2 {
2348    #[inline(always)]
2349    fn default() -> Simr2 {
2350        <crate::RegValueT<Simr2_SPEC> as RegisterValue<_>>::new(0)
2351    }
2352}
2353pub mod simr2 {
2354
2355    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2356    pub struct Iicackt_SPEC;
2357    pub type Iicackt = crate::EnumBitfieldStruct<u8, Iicackt_SPEC>;
2358    impl Iicackt {
2359        #[doc = "ACK transmission"]
2360        pub const _0: Self = Self::new(0);
2361
2362        #[doc = "NACK transmission and reception of ACK/NACK"]
2363        pub const _1: Self = Self::new(1);
2364    }
2365    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2366    pub struct Iiccsc_SPEC;
2367    pub type Iiccsc = crate::EnumBitfieldStruct<u8, Iiccsc_SPEC>;
2368    impl Iiccsc {
2369        #[doc = "No synchronization with the clock signal"]
2370        pub const _0: Self = Self::new(0);
2371
2372        #[doc = "Synchronization with the clock signal"]
2373        pub const _1: Self = Self::new(1);
2374    }
2375    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2376    pub struct Iicintm_SPEC;
2377    pub type Iicintm = crate::EnumBitfieldStruct<u8, Iicintm_SPEC>;
2378    impl Iicintm {
2379        #[doc = "Use ACK/NACK interrupts."]
2380        pub const _0: Self = Self::new(0);
2381
2382        #[doc = "Use reception and transmission interrupts"]
2383        pub const _1: Self = Self::new(1);
2384    }
2385}
2386#[doc(hidden)]
2387#[derive(Copy, Clone, Eq, PartialEq)]
2388pub struct Simr3_SPEC;
2389impl crate::sealed::RegSpec for Simr3_SPEC {
2390    type DataType = u8;
2391}
2392
2393#[doc = "IIC Mode Register 3"]
2394pub type Simr3 = crate::RegValueT<Simr3_SPEC>;
2395
2396impl Simr3 {
2397    #[doc = "SCL Output Select"]
2398    #[inline(always)]
2399    pub fn iicscls(
2400        self,
2401    ) -> crate::common::RegisterField<
2402        6,
2403        0x3,
2404        1,
2405        0,
2406        simr3::Iicscls,
2407        simr3::Iicscls,
2408        Simr3_SPEC,
2409        crate::common::RW,
2410    > {
2411        crate::common::RegisterField::<
2412            6,
2413            0x3,
2414            1,
2415            0,
2416            simr3::Iicscls,
2417            simr3::Iicscls,
2418            Simr3_SPEC,
2419            crate::common::RW,
2420        >::from_register(self, 0)
2421    }
2422
2423    #[doc = "SDA Output Select"]
2424    #[inline(always)]
2425    pub fn iicsdas(
2426        self,
2427    ) -> crate::common::RegisterField<
2428        4,
2429        0x3,
2430        1,
2431        0,
2432        simr3::Iicsdas,
2433        simr3::Iicsdas,
2434        Simr3_SPEC,
2435        crate::common::RW,
2436    > {
2437        crate::common::RegisterField::<
2438            4,
2439            0x3,
2440            1,
2441            0,
2442            simr3::Iicsdas,
2443            simr3::Iicsdas,
2444            Simr3_SPEC,
2445            crate::common::RW,
2446        >::from_register(self, 0)
2447    }
2448
2449    #[doc = "Issuing of Start, Restart, or Stop Condition Completed Flag(When 0 is written to IICSTIF, it is cleared to 0.)"]
2450    #[inline(always)]
2451    pub fn iicstif(
2452        self,
2453    ) -> crate::common::RegisterField<
2454        3,
2455        0x1,
2456        1,
2457        0,
2458        simr3::Iicstif,
2459        simr3::Iicstif,
2460        Simr3_SPEC,
2461        crate::common::RW,
2462    > {
2463        crate::common::RegisterField::<
2464            3,
2465            0x1,
2466            1,
2467            0,
2468            simr3::Iicstif,
2469            simr3::Iicstif,
2470            Simr3_SPEC,
2471            crate::common::RW,
2472        >::from_register(self, 0)
2473    }
2474
2475    #[doc = "Stop Condition Generation"]
2476    #[inline(always)]
2477    pub fn iicstpreq(
2478        self,
2479    ) -> crate::common::RegisterField<
2480        2,
2481        0x1,
2482        1,
2483        0,
2484        simr3::Iicstpreq,
2485        simr3::Iicstpreq,
2486        Simr3_SPEC,
2487        crate::common::RW,
2488    > {
2489        crate::common::RegisterField::<
2490            2,
2491            0x1,
2492            1,
2493            0,
2494            simr3::Iicstpreq,
2495            simr3::Iicstpreq,
2496            Simr3_SPEC,
2497            crate::common::RW,
2498        >::from_register(self, 0)
2499    }
2500
2501    #[doc = "Restart Condition Generation"]
2502    #[inline(always)]
2503    pub fn iicrstareq(
2504        self,
2505    ) -> crate::common::RegisterField<
2506        1,
2507        0x1,
2508        1,
2509        0,
2510        simr3::Iicrstareq,
2511        simr3::Iicrstareq,
2512        Simr3_SPEC,
2513        crate::common::RW,
2514    > {
2515        crate::common::RegisterField::<
2516            1,
2517            0x1,
2518            1,
2519            0,
2520            simr3::Iicrstareq,
2521            simr3::Iicrstareq,
2522            Simr3_SPEC,
2523            crate::common::RW,
2524        >::from_register(self, 0)
2525    }
2526
2527    #[doc = "Start Condition Generation"]
2528    #[inline(always)]
2529    pub fn iicstareq(
2530        self,
2531    ) -> crate::common::RegisterField<
2532        0,
2533        0x1,
2534        1,
2535        0,
2536        simr3::Iicstareq,
2537        simr3::Iicstareq,
2538        Simr3_SPEC,
2539        crate::common::RW,
2540    > {
2541        crate::common::RegisterField::<
2542            0,
2543            0x1,
2544            1,
2545            0,
2546            simr3::Iicstareq,
2547            simr3::Iicstareq,
2548            Simr3_SPEC,
2549            crate::common::RW,
2550        >::from_register(self, 0)
2551    }
2552}
2553impl ::core::default::Default for Simr3 {
2554    #[inline(always)]
2555    fn default() -> Simr3 {
2556        <crate::RegValueT<Simr3_SPEC> as RegisterValue<_>>::new(0)
2557    }
2558}
2559pub mod simr3 {
2560
2561    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2562    pub struct Iicscls_SPEC;
2563    pub type Iicscls = crate::EnumBitfieldStruct<u8, Iicscls_SPEC>;
2564    impl Iicscls {
2565        #[doc = "Serial clock output"]
2566        pub const _00: Self = Self::new(0);
2567
2568        #[doc = "Generate a start, restart, or stop condition."]
2569        pub const _01: Self = Self::new(1);
2570
2571        #[doc = "Output the low level on the SSCLn pin."]
2572        pub const _10: Self = Self::new(2);
2573
2574        #[doc = "Place the SSCLn pin in the high-impedance state."]
2575        pub const _11: Self = Self::new(3);
2576    }
2577    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2578    pub struct Iicsdas_SPEC;
2579    pub type Iicsdas = crate::EnumBitfieldStruct<u8, Iicsdas_SPEC>;
2580    impl Iicsdas {
2581        #[doc = "Serial data output"]
2582        pub const _00: Self = Self::new(0);
2583
2584        #[doc = "Generate a start, restart, or stop condition."]
2585        pub const _01: Self = Self::new(1);
2586
2587        #[doc = "Output the low level on the SSDAn pin."]
2588        pub const _10: Self = Self::new(2);
2589
2590        #[doc = "Place the SSDAn pin in the high-impedance state."]
2591        pub const _11: Self = Self::new(3);
2592    }
2593    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2594    pub struct Iicstif_SPEC;
2595    pub type Iicstif = crate::EnumBitfieldStruct<u8, Iicstif_SPEC>;
2596    impl Iicstif {
2597        #[doc = "There are no requests for generating conditions or a condition is being generated."]
2598        pub const _0: Self = Self::new(0);
2599
2600        #[doc = "A start, restart, or stop condition is completely generated."]
2601        pub const _1: Self = Self::new(1);
2602    }
2603    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2604    pub struct Iicstpreq_SPEC;
2605    pub type Iicstpreq = crate::EnumBitfieldStruct<u8, Iicstpreq_SPEC>;
2606    impl Iicstpreq {
2607        #[doc = "A stop condition is not generated."]
2608        pub const _0: Self = Self::new(0);
2609
2610        #[doc = "A stop condition is generated."]
2611        pub const _1: Self = Self::new(1);
2612    }
2613    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2614    pub struct Iicrstareq_SPEC;
2615    pub type Iicrstareq = crate::EnumBitfieldStruct<u8, Iicrstareq_SPEC>;
2616    impl Iicrstareq {
2617        #[doc = "A restart condition is not generated."]
2618        pub const _0: Self = Self::new(0);
2619
2620        #[doc = "A restart condition is generated."]
2621        pub const _1: Self = Self::new(1);
2622    }
2623    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2624    pub struct Iicstareq_SPEC;
2625    pub type Iicstareq = crate::EnumBitfieldStruct<u8, Iicstareq_SPEC>;
2626    impl Iicstareq {
2627        #[doc = "A start condition is not generated."]
2628        pub const _0: Self = Self::new(0);
2629
2630        #[doc = "A start condition is generated."]
2631        pub const _1: Self = Self::new(1);
2632    }
2633}
2634#[doc(hidden)]
2635#[derive(Copy, Clone, Eq, PartialEq)]
2636pub struct Sisr_SPEC;
2637impl crate::sealed::RegSpec for Sisr_SPEC {
2638    type DataType = u8;
2639}
2640
2641#[doc = "IIC Status Register"]
2642pub type Sisr = crate::RegValueT<Sisr_SPEC>;
2643
2644impl Sisr {
2645    #[doc = "This bit is read as 0."]
2646    #[inline(always)]
2647    pub fn reserved(
2648        self,
2649    ) -> crate::common::RegisterFieldBool<1, 1, 0, Sisr_SPEC, crate::common::R> {
2650        crate::common::RegisterFieldBool::<1, 1, 0, Sisr_SPEC, crate::common::R>::from_register(
2651            self, 0,
2652        )
2653    }
2654
2655    #[doc = "ACK Reception Data Flag"]
2656    #[inline(always)]
2657    pub fn iicackr(
2658        self,
2659    ) -> crate::common::RegisterField<
2660        0,
2661        0x1,
2662        1,
2663        0,
2664        sisr::Iicackr,
2665        sisr::Iicackr,
2666        Sisr_SPEC,
2667        crate::common::R,
2668    > {
2669        crate::common::RegisterField::<
2670            0,
2671            0x1,
2672            1,
2673            0,
2674            sisr::Iicackr,
2675            sisr::Iicackr,
2676            Sisr_SPEC,
2677            crate::common::R,
2678        >::from_register(self, 0)
2679    }
2680}
2681impl ::core::default::Default for Sisr {
2682    #[inline(always)]
2683    fn default() -> Sisr {
2684        <crate::RegValueT<Sisr_SPEC> as RegisterValue<_>>::new(0)
2685    }
2686}
2687pub mod sisr {
2688
2689    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2690    pub struct Iicackr_SPEC;
2691    pub type Iicackr = crate::EnumBitfieldStruct<u8, Iicackr_SPEC>;
2692    impl Iicackr {
2693        #[doc = "ACK received"]
2694        pub const _0: Self = Self::new(0);
2695
2696        #[doc = "NACK received"]
2697        pub const _1: Self = Self::new(1);
2698    }
2699}
2700#[doc(hidden)]
2701#[derive(Copy, Clone, Eq, PartialEq)]
2702pub struct Spmr_SPEC;
2703impl crate::sealed::RegSpec for Spmr_SPEC {
2704    type DataType = u8;
2705}
2706
2707#[doc = "SPI Mode Register"]
2708pub type Spmr = crate::RegValueT<Spmr_SPEC>;
2709
2710impl Spmr {
2711    #[doc = "Clock Phase Select"]
2712    #[inline(always)]
2713    pub fn ckph(
2714        self,
2715    ) -> crate::common::RegisterField<
2716        7,
2717        0x1,
2718        1,
2719        0,
2720        spmr::Ckph,
2721        spmr::Ckph,
2722        Spmr_SPEC,
2723        crate::common::RW,
2724    > {
2725        crate::common::RegisterField::<
2726            7,
2727            0x1,
2728            1,
2729            0,
2730            spmr::Ckph,
2731            spmr::Ckph,
2732            Spmr_SPEC,
2733            crate::common::RW,
2734        >::from_register(self, 0)
2735    }
2736
2737    #[doc = "Clock Polarity Select"]
2738    #[inline(always)]
2739    pub fn ckpol(
2740        self,
2741    ) -> crate::common::RegisterField<
2742        6,
2743        0x1,
2744        1,
2745        0,
2746        spmr::Ckpol,
2747        spmr::Ckpol,
2748        Spmr_SPEC,
2749        crate::common::RW,
2750    > {
2751        crate::common::RegisterField::<
2752            6,
2753            0x1,
2754            1,
2755            0,
2756            spmr::Ckpol,
2757            spmr::Ckpol,
2758            Spmr_SPEC,
2759            crate::common::RW,
2760        >::from_register(self, 0)
2761    }
2762
2763    #[doc = "Mode Fault Flag"]
2764    #[inline(always)]
2765    pub fn mff(
2766        self,
2767    ) -> crate::common::RegisterField<
2768        4,
2769        0x1,
2770        1,
2771        0,
2772        spmr::Mff,
2773        spmr::Mff,
2774        Spmr_SPEC,
2775        crate::common::RW,
2776    > {
2777        crate::common::RegisterField::<
2778            4,
2779            0x1,
2780            1,
2781            0,
2782            spmr::Mff,
2783            spmr::Mff,
2784            Spmr_SPEC,
2785            crate::common::RW,
2786        >::from_register(self, 0)
2787    }
2788
2789    #[doc = "This bit is read as 0. The write value should be 0."]
2790    #[inline(always)]
2791    pub fn reserved(
2792        self,
2793    ) -> crate::common::RegisterFieldBool<3, 1, 0, Spmr_SPEC, crate::common::RW> {
2794        crate::common::RegisterFieldBool::<3, 1, 0, Spmr_SPEC, crate::common::RW>::from_register(
2795            self, 0,
2796        )
2797    }
2798
2799    #[doc = "Master Slave Select"]
2800    #[inline(always)]
2801    pub fn mss(
2802        self,
2803    ) -> crate::common::RegisterField<
2804        2,
2805        0x1,
2806        1,
2807        0,
2808        spmr::Mss,
2809        spmr::Mss,
2810        Spmr_SPEC,
2811        crate::common::RW,
2812    > {
2813        crate::common::RegisterField::<
2814            2,
2815            0x1,
2816            1,
2817            0,
2818            spmr::Mss,
2819            spmr::Mss,
2820            Spmr_SPEC,
2821            crate::common::RW,
2822        >::from_register(self, 0)
2823    }
2824
2825    #[doc = "CTS Enable"]
2826    #[inline(always)]
2827    pub fn ctse(
2828        self,
2829    ) -> crate::common::RegisterField<
2830        1,
2831        0x1,
2832        1,
2833        0,
2834        spmr::Ctse,
2835        spmr::Ctse,
2836        Spmr_SPEC,
2837        crate::common::RW,
2838    > {
2839        crate::common::RegisterField::<
2840            1,
2841            0x1,
2842            1,
2843            0,
2844            spmr::Ctse,
2845            spmr::Ctse,
2846            Spmr_SPEC,
2847            crate::common::RW,
2848        >::from_register(self, 0)
2849    }
2850
2851    #[doc = "SSn# Pin Function Enable"]
2852    #[inline(always)]
2853    pub fn sse(
2854        self,
2855    ) -> crate::common::RegisterField<
2856        0,
2857        0x1,
2858        1,
2859        0,
2860        spmr::Sse,
2861        spmr::Sse,
2862        Spmr_SPEC,
2863        crate::common::RW,
2864    > {
2865        crate::common::RegisterField::<
2866            0,
2867            0x1,
2868            1,
2869            0,
2870            spmr::Sse,
2871            spmr::Sse,
2872            Spmr_SPEC,
2873            crate::common::RW,
2874        >::from_register(self, 0)
2875    }
2876}
2877impl ::core::default::Default for Spmr {
2878    #[inline(always)]
2879    fn default() -> Spmr {
2880        <crate::RegValueT<Spmr_SPEC> as RegisterValue<_>>::new(0)
2881    }
2882}
2883pub mod spmr {
2884
2885    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2886    pub struct Ckph_SPEC;
2887    pub type Ckph = crate::EnumBitfieldStruct<u8, Ckph_SPEC>;
2888    impl Ckph {
2889        #[doc = "Clock is not delayed."]
2890        pub const _0: Self = Self::new(0);
2891
2892        #[doc = "Clock is delayed."]
2893        pub const _1: Self = Self::new(1);
2894    }
2895    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2896    pub struct Ckpol_SPEC;
2897    pub type Ckpol = crate::EnumBitfieldStruct<u8, Ckpol_SPEC>;
2898    impl Ckpol {
2899        #[doc = "Clock polarity is not inverted."]
2900        pub const _0: Self = Self::new(0);
2901
2902        #[doc = "Clock polarity is inverted"]
2903        pub const _1: Self = Self::new(1);
2904    }
2905    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2906    pub struct Mff_SPEC;
2907    pub type Mff = crate::EnumBitfieldStruct<u8, Mff_SPEC>;
2908    impl Mff {
2909        #[doc = "No mode fault error"]
2910        pub const _0: Self = Self::new(0);
2911
2912        #[doc = "Mode fault error"]
2913        pub const _1: Self = Self::new(1);
2914    }
2915    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2916    pub struct Mss_SPEC;
2917    pub type Mss = crate::EnumBitfieldStruct<u8, Mss_SPEC>;
2918    impl Mss {
2919        #[doc = "Transmission is through the TXDn pin and reception is through the RXDn pin (master mode)."]
2920        pub const _0: Self = Self::new(0);
2921
2922        #[doc = "Reception is through the TXDn pin and transmission is through the RXDn pin (slave mode)."]
2923        pub const _1: Self = Self::new(1);
2924    }
2925    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2926    pub struct Ctse_SPEC;
2927    pub type Ctse = crate::EnumBitfieldStruct<u8, Ctse_SPEC>;
2928    impl Ctse {
2929        #[doc = "CTS function is disabled (RTS output function is enabled)."]
2930        pub const _0: Self = Self::new(0);
2931
2932        #[doc = "CTS function is enabled."]
2933        pub const _1: Self = Self::new(1);
2934    }
2935    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2936    pub struct Sse_SPEC;
2937    pub type Sse = crate::EnumBitfieldStruct<u8, Sse_SPEC>;
2938    impl Sse {
2939        #[doc = "SSn# pin function is disabled."]
2940        pub const _0: Self = Self::new(0);
2941
2942        #[doc = "SSn# pin function is enabled."]
2943        pub const _1: Self = Self::new(1);
2944    }
2945}
2946#[doc(hidden)]
2947#[derive(Copy, Clone, Eq, PartialEq)]
2948pub struct Tdrhl_SPEC;
2949impl crate::sealed::RegSpec for Tdrhl_SPEC {
2950    type DataType = u16;
2951}
2952
2953#[doc = "Transmit 9-bit Data Register"]
2954pub type Tdrhl = crate::RegValueT<Tdrhl_SPEC>;
2955
2956impl Tdrhl {
2957    #[doc = "TDRHL is a 16-bit register that stores transmit data."]
2958    #[inline(always)]
2959    pub fn tdrhl(
2960        self,
2961    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Tdrhl_SPEC, crate::common::RW>
2962    {
2963        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Tdrhl_SPEC,crate::common::RW>::from_register(self,0)
2964    }
2965}
2966impl ::core::default::Default for Tdrhl {
2967    #[inline(always)]
2968    fn default() -> Tdrhl {
2969        <crate::RegValueT<Tdrhl_SPEC> as RegisterValue<_>>::new(65535)
2970    }
2971}
2972
2973#[doc(hidden)]
2974#[derive(Copy, Clone, Eq, PartialEq)]
2975pub struct Rdrhl_SPEC;
2976impl crate::sealed::RegSpec for Rdrhl_SPEC {
2977    type DataType = u16;
2978}
2979
2980#[doc = "Receive 9-bit Data Register"]
2981pub type Rdrhl = crate::RegValueT<Rdrhl_SPEC>;
2982
2983impl Rdrhl {
2984    #[doc = "RDRHL is an 16-bit register that stores receive data."]
2985    #[inline(always)]
2986    pub fn rdrhl(
2987        self,
2988    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Rdrhl_SPEC, crate::common::R> {
2989        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Rdrhl_SPEC,crate::common::R>::from_register(self,0)
2990    }
2991}
2992impl ::core::default::Default for Rdrhl {
2993    #[inline(always)]
2994    fn default() -> Rdrhl {
2995        <crate::RegValueT<Rdrhl_SPEC> as RegisterValue<_>>::new(0)
2996    }
2997}
2998
2999#[doc(hidden)]
3000#[derive(Copy, Clone, Eq, PartialEq)]
3001pub struct Mddr_SPEC;
3002impl crate::sealed::RegSpec for Mddr_SPEC {
3003    type DataType = u8;
3004}
3005
3006#[doc = "Modulation Duty Register"]
3007pub type Mddr = crate::RegValueT<Mddr_SPEC>;
3008
3009impl Mddr {
3010    #[doc = "MDDR corrects the bit rate adjusted by the BRR register."]
3011    #[inline(always)]
3012    pub fn mddr(
3013        self,
3014    ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, Mddr_SPEC, crate::common::RW> {
3015        crate::common::RegisterField::<0,0xff,1,0,u8,u8,Mddr_SPEC,crate::common::RW>::from_register(self,0)
3016    }
3017}
3018impl ::core::default::Default for Mddr {
3019    #[inline(always)]
3020    fn default() -> Mddr {
3021        <crate::RegValueT<Mddr_SPEC> as RegisterValue<_>>::new(255)
3022    }
3023}
3024
3025#[doc(hidden)]
3026#[derive(Copy, Clone, Eq, PartialEq)]
3027pub struct Dccr_SPEC;
3028impl crate::sealed::RegSpec for Dccr_SPEC {
3029    type DataType = u8;
3030}
3031
3032#[doc = "Data Compare Match Control Register"]
3033pub type Dccr = crate::RegValueT<Dccr_SPEC>;
3034
3035impl Dccr {
3036    #[doc = "Data Compare Match Enable(Valid only in asynchronous mode(including multi-processor)"]
3037    #[inline(always)]
3038    pub fn dcme(
3039        self,
3040    ) -> crate::common::RegisterField<
3041        7,
3042        0x1,
3043        1,
3044        0,
3045        dccr::Dcme,
3046        dccr::Dcme,
3047        Dccr_SPEC,
3048        crate::common::RW,
3049    > {
3050        crate::common::RegisterField::<
3051            7,
3052            0x1,
3053            1,
3054            0,
3055            dccr::Dcme,
3056            dccr::Dcme,
3057            Dccr_SPEC,
3058            crate::common::RW,
3059        >::from_register(self, 0)
3060    }
3061
3062    #[doc = "ID frame select Bit(Valid only in asynchronous mode(including multi-processor)"]
3063    #[inline(always)]
3064    pub fn idsel(
3065        self,
3066    ) -> crate::common::RegisterField<
3067        6,
3068        0x1,
3069        1,
3070        0,
3071        dccr::Idsel,
3072        dccr::Idsel,
3073        Dccr_SPEC,
3074        crate::common::RW,
3075    > {
3076        crate::common::RegisterField::<
3077            6,
3078            0x1,
3079            1,
3080            0,
3081            dccr::Idsel,
3082            dccr::Idsel,
3083            Dccr_SPEC,
3084            crate::common::RW,
3085        >::from_register(self, 0)
3086    }
3087
3088    #[doc = "Data Compare Match Framing Error Flag"]
3089    #[inline(always)]
3090    pub fn dfer(
3091        self,
3092    ) -> crate::common::RegisterField<
3093        4,
3094        0x1,
3095        1,
3096        0,
3097        dccr::Dfer,
3098        dccr::Dfer,
3099        Dccr_SPEC,
3100        crate::common::RW,
3101    > {
3102        crate::common::RegisterField::<
3103            4,
3104            0x1,
3105            1,
3106            0,
3107            dccr::Dfer,
3108            dccr::Dfer,
3109            Dccr_SPEC,
3110            crate::common::RW,
3111        >::from_register(self, 0)
3112    }
3113
3114    #[doc = "Data Compare Match Parity Error Flag"]
3115    #[inline(always)]
3116    pub fn dper(
3117        self,
3118    ) -> crate::common::RegisterField<
3119        3,
3120        0x1,
3121        1,
3122        0,
3123        dccr::Dper,
3124        dccr::Dper,
3125        Dccr_SPEC,
3126        crate::common::RW,
3127    > {
3128        crate::common::RegisterField::<
3129            3,
3130            0x1,
3131            1,
3132            0,
3133            dccr::Dper,
3134            dccr::Dper,
3135            Dccr_SPEC,
3136            crate::common::RW,
3137        >::from_register(self, 0)
3138    }
3139
3140    #[doc = "These bits are read as 00. The write value should be 00."]
3141    #[inline(always)]
3142    pub fn reserved(
3143        self,
3144    ) -> crate::common::RegisterField<1, 0x3, 1, 0, u8, u8, Dccr_SPEC, crate::common::RW> {
3145        crate::common::RegisterField::<1,0x3,1,0,u8,u8,Dccr_SPEC,crate::common::RW>::from_register(self,0)
3146    }
3147
3148    #[doc = "Data Compare Match Flag"]
3149    #[inline(always)]
3150    pub fn dcmf(
3151        self,
3152    ) -> crate::common::RegisterField<
3153        0,
3154        0x1,
3155        1,
3156        0,
3157        dccr::Dcmf,
3158        dccr::Dcmf,
3159        Dccr_SPEC,
3160        crate::common::RW,
3161    > {
3162        crate::common::RegisterField::<
3163            0,
3164            0x1,
3165            1,
3166            0,
3167            dccr::Dcmf,
3168            dccr::Dcmf,
3169            Dccr_SPEC,
3170            crate::common::RW,
3171        >::from_register(self, 0)
3172    }
3173}
3174impl ::core::default::Default for Dccr {
3175    #[inline(always)]
3176    fn default() -> Dccr {
3177        <crate::RegValueT<Dccr_SPEC> as RegisterValue<_>>::new(64)
3178    }
3179}
3180pub mod dccr {
3181
3182    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3183    pub struct Dcme_SPEC;
3184    pub type Dcme = crate::EnumBitfieldStruct<u8, Dcme_SPEC>;
3185    impl Dcme {
3186        #[doc = "Address match function is disabled."]
3187        pub const _0: Self = Self::new(0);
3188
3189        #[doc = "Address match function is enabled"]
3190        pub const _1: Self = Self::new(1);
3191    }
3192    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3193    pub struct Idsel_SPEC;
3194    pub type Idsel = crate::EnumBitfieldStruct<u8, Idsel_SPEC>;
3195    impl Idsel {
3196        #[doc = "Always compare data regardless of the value of the MPB bit."]
3197        pub const _0: Self = Self::new(0);
3198
3199        #[doc = "Compare data when the MPB bit is 1 (ID frame) only."]
3200        pub const _1: Self = Self::new(1);
3201    }
3202    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3203    pub struct Dfer_SPEC;
3204    pub type Dfer = crate::EnumBitfieldStruct<u8, Dfer_SPEC>;
3205    impl Dfer {
3206        #[doc = "No framing error occurred"]
3207        pub const _0: Self = Self::new(0);
3208
3209        #[doc = "A framing error has occurred"]
3210        pub const _1: Self = Self::new(1);
3211    }
3212    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3213    pub struct Dper_SPEC;
3214    pub type Dper = crate::EnumBitfieldStruct<u8, Dper_SPEC>;
3215    impl Dper {
3216        #[doc = "No parity error occurred"]
3217        pub const _0: Self = Self::new(0);
3218
3219        #[doc = "A parity error has occurred"]
3220        pub const _1: Self = Self::new(1);
3221    }
3222    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3223    pub struct Dcmf_SPEC;
3224    pub type Dcmf = crate::EnumBitfieldStruct<u8, Dcmf_SPEC>;
3225    impl Dcmf {
3226        #[doc = "No matched"]
3227        pub const _0: Self = Self::new(0);
3228
3229        #[doc = "Matched"]
3230        pub const _1: Self = Self::new(1);
3231    }
3232}
3233#[doc(hidden)]
3234#[derive(Copy, Clone, Eq, PartialEq)]
3235pub struct Cdr_SPEC;
3236impl crate::sealed::RegSpec for Cdr_SPEC {
3237    type DataType = u16;
3238}
3239
3240#[doc = "Compare Match Data Register"]
3241pub type Cdr = crate::RegValueT<Cdr_SPEC>;
3242
3243impl Cdr {
3244    #[doc = "These bits are read as 0000000. The write value should be 0000000."]
3245    #[inline(always)]
3246    pub fn reserved(
3247        self,
3248    ) -> crate::common::RegisterField<9, 0x7f, 1, 0, u8, u8, Cdr_SPEC, crate::common::RW> {
3249        crate::common::RegisterField::<9,0x7f,1,0,u8,u8,Cdr_SPEC,crate::common::RW>::from_register(self,0)
3250    }
3251
3252    #[doc = "Compare Match DataCompare data pattern for address match wake-up function"]
3253    #[inline(always)]
3254    pub fn cmpd(
3255        self,
3256    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Cdr_SPEC, crate::common::RW> {
3257        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Cdr_SPEC,crate::common::RW>::from_register(self,0)
3258    }
3259}
3260impl ::core::default::Default for Cdr {
3261    #[inline(always)]
3262    fn default() -> Cdr {
3263        <crate::RegValueT<Cdr_SPEC> as RegisterValue<_>>::new(0)
3264    }
3265}
3266
3267#[doc(hidden)]
3268#[derive(Copy, Clone, Eq, PartialEq)]
3269pub struct Sptr_SPEC;
3270impl crate::sealed::RegSpec for Sptr_SPEC {
3271    type DataType = u8;
3272}
3273
3274#[doc = "Serial Port Register"]
3275pub type Sptr = crate::RegValueT<Sptr_SPEC>;
3276
3277impl Sptr {
3278    #[doc = "These bits are read as 00000. The write value should be 00000."]
3279    #[inline(always)]
3280    pub fn reserved(
3281        self,
3282    ) -> crate::common::RegisterField<3, 0x1f, 1, 0, u8, u8, Sptr_SPEC, crate::common::RW> {
3283        crate::common::RegisterField::<3,0x1f,1,0,u8,u8,Sptr_SPEC,crate::common::RW>::from_register(self,0)
3284    }
3285
3286    #[doc = "Serial port break I/O bit(It\'s selected whether the value of SPB2DT is output to TxD terminal.)"]
3287    #[inline(always)]
3288    pub fn spb2io(
3289        self,
3290    ) -> crate::common::RegisterField<
3291        2,
3292        0x1,
3293        1,
3294        0,
3295        sptr::Spb2Io,
3296        sptr::Spb2Io,
3297        Sptr_SPEC,
3298        crate::common::RW,
3299    > {
3300        crate::common::RegisterField::<
3301            2,
3302            0x1,
3303            1,
3304            0,
3305            sptr::Spb2Io,
3306            sptr::Spb2Io,
3307            Sptr_SPEC,
3308            crate::common::RW,
3309        >::from_register(self, 0)
3310    }
3311
3312    #[doc = "Serial port break data select bit(The output level of TxD terminal is selected when SCR.TE = 0.)"]
3313    #[inline(always)]
3314    pub fn spb2dt(
3315        self,
3316    ) -> crate::common::RegisterField<
3317        1,
3318        0x1,
3319        1,
3320        0,
3321        sptr::Spb2Dt,
3322        sptr::Spb2Dt,
3323        Sptr_SPEC,
3324        crate::common::RW,
3325    > {
3326        crate::common::RegisterField::<
3327            1,
3328            0x1,
3329            1,
3330            0,
3331            sptr::Spb2Dt,
3332            sptr::Spb2Dt,
3333            Sptr_SPEC,
3334            crate::common::RW,
3335        >::from_register(self, 0)
3336    }
3337
3338    #[doc = "Serial input data monitor bit(The state of the RXD terminal is shown.)"]
3339    #[inline(always)]
3340    pub fn rxdmon(
3341        self,
3342    ) -> crate::common::RegisterField<
3343        0,
3344        0x1,
3345        1,
3346        0,
3347        sptr::Rxdmon,
3348        sptr::Rxdmon,
3349        Sptr_SPEC,
3350        crate::common::R,
3351    > {
3352        crate::common::RegisterField::<
3353            0,
3354            0x1,
3355            1,
3356            0,
3357            sptr::Rxdmon,
3358            sptr::Rxdmon,
3359            Sptr_SPEC,
3360            crate::common::R,
3361        >::from_register(self, 0)
3362    }
3363}
3364impl ::core::default::Default for Sptr {
3365    #[inline(always)]
3366    fn default() -> Sptr {
3367        <crate::RegValueT<Sptr_SPEC> as RegisterValue<_>>::new(3)
3368    }
3369}
3370pub mod sptr {
3371
3372    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3373    pub struct Spb2Io_SPEC;
3374    pub type Spb2Io = crate::EnumBitfieldStruct<u8, Spb2Io_SPEC>;
3375    impl Spb2Io {
3376        #[doc = "The value of SPB2DT bit isn\'t output in TxD terminal."]
3377        pub const _0: Self = Self::new(0);
3378
3379        #[doc = "The value of SPB2DT bit is output in TxD terminal."]
3380        pub const _1: Self = Self::new(1);
3381    }
3382    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3383    pub struct Spb2Dt_SPEC;
3384    pub type Spb2Dt = crate::EnumBitfieldStruct<u8, Spb2Dt_SPEC>;
3385    impl Spb2Dt {
3386        #[doc = "Low level is output in TxD terminal."]
3387        pub const _0: Self = Self::new(0);
3388
3389        #[doc = "High level is output in TxD terminal."]
3390        pub const _1: Self = Self::new(1);
3391    }
3392    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3393    pub struct Rxdmon_SPEC;
3394    pub type Rxdmon = crate::EnumBitfieldStruct<u8, Rxdmon_SPEC>;
3395    impl Rxdmon {
3396        #[doc = "RXD terminal is the Low level."]
3397        pub const _0: Self = Self::new(0);
3398
3399        #[doc = "RXD terminal is the High level."]
3400        pub const _1: Self = Self::new(1);
3401    }
3402}
ra2a1_pac/sci1.rs

ra2a1_pac/
sci1.rs
