1#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"CRC Calculator"]
28unsafe impl ::core::marker::Send for super::Crc {}
29unsafe impl ::core::marker::Sync for super::Crc {}
30impl super::Crc {
31 #[allow(unused)]
32 #[inline(always)]
33 pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34 self.ptr
35 }
36
37 #[doc = "CRC Control Register0"]
38 #[inline(always)]
39 pub const fn crccr0(
40 &self,
41 ) -> &'static crate::common::Reg<self::Crccr0_SPEC, crate::common::RW> {
42 unsafe {
43 crate::common::Reg::<self::Crccr0_SPEC, crate::common::RW>::from_ptr(
44 self._svd2pac_as_ptr().add(0usize),
45 )
46 }
47 }
48
49 #[doc = "CRC Control Register1"]
50 #[inline(always)]
51 pub const fn crccr1(
52 &self,
53 ) -> &'static crate::common::Reg<self::Crccr1_SPEC, crate::common::RW> {
54 unsafe {
55 crate::common::Reg::<self::Crccr1_SPEC, crate::common::RW>::from_ptr(
56 self._svd2pac_as_ptr().add(1usize),
57 )
58 }
59 }
60
61 #[doc = "CRC Data Input Register"]
62 #[inline(always)]
63 pub const fn crcdir(
64 &self,
65 ) -> &'static crate::common::Reg<self::Crcdir_SPEC, crate::common::RW> {
66 unsafe {
67 crate::common::Reg::<self::Crcdir_SPEC, crate::common::RW>::from_ptr(
68 self._svd2pac_as_ptr().add(4usize),
69 )
70 }
71 }
72
73 #[doc = "CRC Data Input Register (byte access)"]
74 #[inline(always)]
75 pub const fn crcdir_by(
76 &self,
77 ) -> &'static crate::common::Reg<self::CrcdirBy_SPEC, crate::common::RW> {
78 unsafe {
79 crate::common::Reg::<self::CrcdirBy_SPEC, crate::common::RW>::from_ptr(
80 self._svd2pac_as_ptr().add(4usize),
81 )
82 }
83 }
84
85 #[doc = "CRC Data Output Register"]
86 #[inline(always)]
87 pub const fn crcdor(
88 &self,
89 ) -> &'static crate::common::Reg<self::Crcdor_SPEC, crate::common::RW> {
90 unsafe {
91 crate::common::Reg::<self::Crcdor_SPEC, crate::common::RW>::from_ptr(
92 self._svd2pac_as_ptr().add(8usize),
93 )
94 }
95 }
96
97 #[doc = "CRC Data Output Register (halfword access)"]
98 #[inline(always)]
99 pub const fn crcdor_ha(
100 &self,
101 ) -> &'static crate::common::Reg<self::CrcdorHa_SPEC, crate::common::RW> {
102 unsafe {
103 crate::common::Reg::<self::CrcdorHa_SPEC, crate::common::RW>::from_ptr(
104 self._svd2pac_as_ptr().add(8usize),
105 )
106 }
107 }
108
109 #[doc = "CRC Data Output Register(byte access)"]
110 #[inline(always)]
111 pub const fn crcdor_by(
112 &self,
113 ) -> &'static crate::common::Reg<self::CrcdorBy_SPEC, crate::common::RW> {
114 unsafe {
115 crate::common::Reg::<self::CrcdorBy_SPEC, crate::common::RW>::from_ptr(
116 self._svd2pac_as_ptr().add(8usize),
117 )
118 }
119 }
120
121 #[doc = "Snoop Address Register"]
122 #[inline(always)]
123 pub const fn crcsar(
124 &self,
125 ) -> &'static crate::common::Reg<self::Crcsar_SPEC, crate::common::RW> {
126 unsafe {
127 crate::common::Reg::<self::Crcsar_SPEC, crate::common::RW>::from_ptr(
128 self._svd2pac_as_ptr().add(12usize),
129 )
130 }
131 }
132}
133#[doc(hidden)]
134#[derive(Copy, Clone, Eq, PartialEq)]
135pub struct Crccr0_SPEC;
136impl crate::sealed::RegSpec for Crccr0_SPEC {
137 type DataType = u8;
138}
139
140#[doc = "CRC Control Register0"]
141pub type Crccr0 = crate::RegValueT<Crccr0_SPEC>;
142
143impl Crccr0 {
144 #[doc = "CRCDOR Register Clear"]
145 #[inline(always)]
146 pub fn dorclr(
147 self,
148 ) -> crate::common::RegisterField<
149 7,
150 0x1,
151 1,
152 0,
153 crccr0::Dorclr,
154 crccr0::Dorclr,
155 Crccr0_SPEC,
156 crate::common::W,
157 > {
158 crate::common::RegisterField::<
159 7,
160 0x1,
161 1,
162 0,
163 crccr0::Dorclr,
164 crccr0::Dorclr,
165 Crccr0_SPEC,
166 crate::common::W,
167 >::from_register(self, 0)
168 }
169
170 #[doc = "CRC Calculation Switching"]
171 #[inline(always)]
172 pub fn lms(
173 self,
174 ) -> crate::common::RegisterField<
175 6,
176 0x1,
177 1,
178 0,
179 crccr0::Lms,
180 crccr0::Lms,
181 Crccr0_SPEC,
182 crate::common::RW,
183 > {
184 crate::common::RegisterField::<
185 6,
186 0x1,
187 1,
188 0,
189 crccr0::Lms,
190 crccr0::Lms,
191 Crccr0_SPEC,
192 crate::common::RW,
193 >::from_register(self, 0)
194 }
195
196 #[doc = "These bits are read as 000. The write value should be 000."]
197 #[inline(always)]
198 pub fn reserved(
199 self,
200 ) -> crate::common::RegisterField<3, 0x7, 1, 0, u8, u8, Crccr0_SPEC, crate::common::RW> {
201 crate::common::RegisterField::<3,0x7,1,0,u8,u8,Crccr0_SPEC,crate::common::RW>::from_register(self,0)
202 }
203
204 #[doc = "CRC Generating Polynomial Switching"]
205 #[inline(always)]
206 pub fn gps(
207 self,
208 ) -> crate::common::RegisterField<
209 0,
210 0x7,
211 1,
212 0,
213 crccr0::Gps,
214 crccr0::Gps,
215 Crccr0_SPEC,
216 crate::common::RW,
217 > {
218 crate::common::RegisterField::<
219 0,
220 0x7,
221 1,
222 0,
223 crccr0::Gps,
224 crccr0::Gps,
225 Crccr0_SPEC,
226 crate::common::RW,
227 >::from_register(self, 0)
228 }
229}
230impl ::core::default::Default for Crccr0 {
231 #[inline(always)]
232 fn default() -> Crccr0 {
233 <crate::RegValueT<Crccr0_SPEC> as RegisterValue<_>>::new(0)
234 }
235}
236pub mod crccr0 {
237
238 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
239 pub struct Dorclr_SPEC;
240 pub type Dorclr = crate::EnumBitfieldStruct<u8, Dorclr_SPEC>;
241 impl Dorclr {
242 #[doc = "No effect."]
243 pub const _0: Self = Self::new(0);
244
245 #[doc = "Clears the CRCDOR register."]
246 pub const _1: Self = Self::new(1);
247 }
248 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
249 pub struct Lms_SPEC;
250 pub type Lms = crate::EnumBitfieldStruct<u8, Lms_SPEC>;
251 impl Lms {
252 #[doc = "Generates CRC for LSB first communication."]
253 pub const _0: Self = Self::new(0);
254
255 #[doc = "Generates CRC for MSB first communication."]
256 pub const _1: Self = Self::new(1);
257 }
258 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
259 pub struct Gps_SPEC;
260 pub type Gps = crate::EnumBitfieldStruct<u8, Gps_SPEC>;
261 impl Gps {
262 #[doc = "No calculation is executed."]
263 pub const _000: Self = Self::new(0);
264
265 #[doc = "8-bit CRC-8 (X8 + X2 + X + 1)"]
266 pub const _001: Self = Self::new(1);
267
268 #[doc = "16-bit CRC-16 (X16 + X15 + X2 + 1)"]
269 pub const _010: Self = Self::new(2);
270
271 #[doc = "16-bit CRC-CCITT (X16 + X12 + X5 + 1)"]
272 pub const _011: Self = Self::new(3);
273
274 #[doc = "32-bit CRC-32(X32+X26+X23+X22+X16+X12+X11+X10+X8+X7+X5+X4+X2+X+1)"]
275 pub const _100: Self = Self::new(4);
276
277 #[doc = "32-bit CRC-32C (X32+X28+X27+X26+X25+X23+X22+X20+X19+X18+X14+X13+X11+X10+X9+X8+X6+1)"]
278 pub const _101: Self = Self::new(5);
279 }
280}
281#[doc(hidden)]
282#[derive(Copy, Clone, Eq, PartialEq)]
283pub struct Crccr1_SPEC;
284impl crate::sealed::RegSpec for Crccr1_SPEC {
285 type DataType = u8;
286}
287
288#[doc = "CRC Control Register1"]
289pub type Crccr1 = crate::RegValueT<Crccr1_SPEC>;
290
291impl Crccr1 {
292 #[doc = "Snoop enable bit"]
293 #[inline(always)]
294 pub fn crcsen(
295 self,
296 ) -> crate::common::RegisterField<
297 7,
298 0x1,
299 1,
300 0,
301 crccr1::Crcsen,
302 crccr1::Crcsen,
303 Crccr1_SPEC,
304 crate::common::RW,
305 > {
306 crate::common::RegisterField::<
307 7,
308 0x1,
309 1,
310 0,
311 crccr1::Crcsen,
312 crccr1::Crcsen,
313 Crccr1_SPEC,
314 crate::common::RW,
315 >::from_register(self, 0)
316 }
317
318 #[doc = "Snoop-on-write/read switch bit"]
319 #[inline(always)]
320 pub fn crcswr(
321 self,
322 ) -> crate::common::RegisterField<
323 6,
324 0x1,
325 1,
326 0,
327 crccr1::Crcswr,
328 crccr1::Crcswr,
329 Crccr1_SPEC,
330 crate::common::RW,
331 > {
332 crate::common::RegisterField::<
333 6,
334 0x1,
335 1,
336 0,
337 crccr1::Crcswr,
338 crccr1::Crcswr,
339 Crccr1_SPEC,
340 crate::common::RW,
341 >::from_register(self, 0)
342 }
343
344 #[doc = "These bits are read as 000000. The write value should be 000000."]
345 #[inline(always)]
346 pub fn reserved(
347 self,
348 ) -> crate::common::RegisterField<0, 0x3f, 1, 0, u8, u8, Crccr1_SPEC, crate::common::RW> {
349 crate::common::RegisterField::<0,0x3f,1,0,u8,u8,Crccr1_SPEC,crate::common::RW>::from_register(self,0)
350 }
351}
352impl ::core::default::Default for Crccr1 {
353 #[inline(always)]
354 fn default() -> Crccr1 {
355 <crate::RegValueT<Crccr1_SPEC> as RegisterValue<_>>::new(0)
356 }
357}
358pub mod crccr1 {
359
360 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
361 pub struct Crcsen_SPEC;
362 pub type Crcsen = crate::EnumBitfieldStruct<u8, Crcsen_SPEC>;
363 impl Crcsen {
364 #[doc = "Disabled"]
365 pub const _0: Self = Self::new(0);
366
367 #[doc = "Enabled"]
368 pub const _1: Self = Self::new(1);
369 }
370 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
371 pub struct Crcswr_SPEC;
372 pub type Crcswr = crate::EnumBitfieldStruct<u8, Crcswr_SPEC>;
373 impl Crcswr {
374 #[doc = "Snoop-on-read"]
375 pub const _0: Self = Self::new(0);
376
377 #[doc = "Snoop-on-write"]
378 pub const _1: Self = Self::new(1);
379 }
380}
381#[doc(hidden)]
382#[derive(Copy, Clone, Eq, PartialEq)]
383pub struct Crcdir_SPEC;
384impl crate::sealed::RegSpec for Crcdir_SPEC {
385 type DataType = u32;
386}
387
388#[doc = "CRC Data Input Register"]
389pub type Crcdir = crate::RegValueT<Crcdir_SPEC>;
390
391impl Crcdir {
392 #[doc = "Calculation input Data (Case of CRC-32, CRC-32C )"]
393 #[inline(always)]
394 pub fn crcdir(
395 self,
396 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Crcdir_SPEC, crate::common::RW>
397 {
398 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Crcdir_SPEC,crate::common::RW>::from_register(self,0)
399 }
400}
401impl ::core::default::Default for Crcdir {
402 #[inline(always)]
403 fn default() -> Crcdir {
404 <crate::RegValueT<Crcdir_SPEC> as RegisterValue<_>>::new(0)
405 }
406}
407
408#[doc(hidden)]
409#[derive(Copy, Clone, Eq, PartialEq)]
410pub struct CrcdirBy_SPEC;
411impl crate::sealed::RegSpec for CrcdirBy_SPEC {
412 type DataType = u8;
413}
414
415#[doc = "CRC Data Input Register (byte access)"]
416pub type CrcdirBy = crate::RegValueT<CrcdirBy_SPEC>;
417
418impl CrcdirBy {
419 #[doc = "Calculation input Data ( Case of CRC-8, CRC-16 or CRC-CCITT )"]
420 #[inline(always)]
421 pub fn crcdir_by(
422 self,
423 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, CrcdirBy_SPEC, crate::common::RW> {
424 crate::common::RegisterField::<0,0xff,1,0,u8,u8,CrcdirBy_SPEC,crate::common::RW>::from_register(self,0)
425 }
426}
427impl ::core::default::Default for CrcdirBy {
428 #[inline(always)]
429 fn default() -> CrcdirBy {
430 <crate::RegValueT<CrcdirBy_SPEC> as RegisterValue<_>>::new(0)
431 }
432}
433
434#[doc(hidden)]
435#[derive(Copy, Clone, Eq, PartialEq)]
436pub struct Crcdor_SPEC;
437impl crate::sealed::RegSpec for Crcdor_SPEC {
438 type DataType = u32;
439}
440
441#[doc = "CRC Data Output Register"]
442pub type Crcdor = crate::RegValueT<Crcdor_SPEC>;
443
444impl Crcdor {
445 #[doc = "Calculation output Data (Case of CRC-32, CRC-32C )"]
446 #[inline(always)]
447 pub fn crcdor(
448 self,
449 ) -> crate::common::RegisterField<0, 0xffffffff, 1, 0, u32, u32, Crcdor_SPEC, crate::common::RW>
450 {
451 crate::common::RegisterField::<0,0xffffffff,1,0,u32,u32,Crcdor_SPEC,crate::common::RW>::from_register(self,0)
452 }
453}
454impl ::core::default::Default for Crcdor {
455 #[inline(always)]
456 fn default() -> Crcdor {
457 <crate::RegValueT<Crcdor_SPEC> as RegisterValue<_>>::new(0)
458 }
459}
460
461#[doc(hidden)]
462#[derive(Copy, Clone, Eq, PartialEq)]
463pub struct CrcdorHa_SPEC;
464impl crate::sealed::RegSpec for CrcdorHa_SPEC {
465 type DataType = u16;
466}
467
468#[doc = "CRC Data Output Register (halfword access)"]
469pub type CrcdorHa = crate::RegValueT<CrcdorHa_SPEC>;
470
471impl CrcdorHa {
472 #[doc = "Calculation output Data (Case of CRC-16 or CRC-CCITT )"]
473 #[inline(always)]
474 pub fn crcdor_ha(
475 self,
476 ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, CrcdorHa_SPEC, crate::common::RW>
477 {
478 crate::common::RegisterField::<0,0xffff,1,0,u16,u16,CrcdorHa_SPEC,crate::common::RW>::from_register(self,0)
479 }
480}
481impl ::core::default::Default for CrcdorHa {
482 #[inline(always)]
483 fn default() -> CrcdorHa {
484 <crate::RegValueT<CrcdorHa_SPEC> as RegisterValue<_>>::new(0)
485 }
486}
487
488#[doc(hidden)]
489#[derive(Copy, Clone, Eq, PartialEq)]
490pub struct CrcdorBy_SPEC;
491impl crate::sealed::RegSpec for CrcdorBy_SPEC {
492 type DataType = u8;
493}
494
495#[doc = "CRC Data Output Register(byte access)"]
496pub type CrcdorBy = crate::RegValueT<CrcdorBy_SPEC>;
497
498impl CrcdorBy {
499 #[doc = "Calculation output Data (Case of CRC-8 )"]
500 #[inline(always)]
501 pub fn crcdor_by(
502 self,
503 ) -> crate::common::RegisterField<0, 0xff, 1, 0, u8, u8, CrcdorBy_SPEC, crate::common::RW> {
504 crate::common::RegisterField::<0,0xff,1,0,u8,u8,CrcdorBy_SPEC,crate::common::RW>::from_register(self,0)
505 }
506}
507impl ::core::default::Default for CrcdorBy {
508 #[inline(always)]
509 fn default() -> CrcdorBy {
510 <crate::RegValueT<CrcdorBy_SPEC> as RegisterValue<_>>::new(0)
511 }
512}
513
514#[doc(hidden)]
515#[derive(Copy, Clone, Eq, PartialEq)]
516pub struct Crcsar_SPEC;
517impl crate::sealed::RegSpec for Crcsar_SPEC {
518 type DataType = u16;
519}
520
521#[doc = "Snoop Address Register"]
522pub type Crcsar = crate::RegValueT<Crcsar_SPEC>;
523
524impl Crcsar {
525 #[doc = "These bits are read as 00. The write value should be 00."]
526 #[inline(always)]
527 pub fn reserved(
528 self,
529 ) -> crate::common::RegisterField<14, 0x3, 1, 0, u8, u8, Crcsar_SPEC, crate::common::RW> {
530 crate::common::RegisterField::<14,0x3,1,0,u8,u8,Crcsar_SPEC,crate::common::RW>::from_register(self,0)
531 }
532
533 #[doc = "snoop address bitSet the I/O register address to snoop"]
534 #[inline(always)]
535 pub fn crcsa(
536 self,
537 ) -> crate::common::RegisterField<
538 0,
539 0x3fff,
540 1,
541 0,
542 crcsar::Crcsa,
543 crcsar::Crcsa,
544 Crcsar_SPEC,
545 crate::common::RW,
546 > {
547 crate::common::RegisterField::<
548 0,
549 0x3fff,
550 1,
551 0,
552 crcsar::Crcsa,
553 crcsar::Crcsa,
554 Crcsar_SPEC,
555 crate::common::RW,
556 >::from_register(self, 0)
557 }
558}
559impl ::core::default::Default for Crcsar {
560 #[inline(always)]
561 fn default() -> Crcsar {
562 <crate::RegValueT<Crcsar_SPEC> as RegisterValue<_>>::new(0)
563 }
564}
565pub mod crcsar {
566
567 #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
568 pub struct Crcsa_SPEC;
569 pub type Crcsa = crate::EnumBitfieldStruct<u16, Crcsa_SPEC>;
570 impl Crcsa {
571 #[doc = "SCI0.TDR"]
572 pub const _0_X_0003: Self = Self::new(3);
573
574 #[doc = "SCI0.RDR"]
575 pub const _0_X_0005: Self = Self::new(5);
576
577 #[doc = "SCI1.TDR"]
578 pub const _0_X_0023: Self = Self::new(35);
579
580 #[doc = "SCI1.RDR"]
581 pub const _0_X_0025: Self = Self::new(37);
582
583 #[doc = "SCI9.TDR"]
584 pub const _0_X_0123: Self = Self::new(291);
585
586 #[doc = "SCI9.RDR"]
587 pub const _0_X_0125: Self = Self::new(293);
588 }
589}