ra2a1_pac/
cac.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.1, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:31 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Clock Frequency Accuracy Measurement Circuit"]
28unsafe impl ::core::marker::Send for super::Cac {}
29unsafe impl ::core::marker::Sync for super::Cac {}
30impl super::Cac {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "CAC Control Register 0"]
38    #[inline(always)]
39    pub const fn cacr0(&self) -> &'static crate::common::Reg<self::Cacr0_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Cacr0_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "CAC Control Register 1"]
48    #[inline(always)]
49    pub const fn cacr1(&self) -> &'static crate::common::Reg<self::Cacr1_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Cacr1_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "CAC Control Register 2"]
58    #[inline(always)]
59    pub const fn cacr2(&self) -> &'static crate::common::Reg<self::Cacr2_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Cacr2_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "CAC Interrupt Control Register"]
68    #[inline(always)]
69    pub const fn caicr(&self) -> &'static crate::common::Reg<self::Caicr_SPEC, crate::common::RW> {
70        unsafe {
71            crate::common::Reg::<self::Caicr_SPEC, crate::common::RW>::from_ptr(
72                self._svd2pac_as_ptr().add(3usize),
73            )
74        }
75    }
76
77    #[doc = "CAC Status Register"]
78    #[inline(always)]
79    pub const fn castr(&self) -> &'static crate::common::Reg<self::Castr_SPEC, crate::common::R> {
80        unsafe {
81            crate::common::Reg::<self::Castr_SPEC, crate::common::R>::from_ptr(
82                self._svd2pac_as_ptr().add(4usize),
83            )
84        }
85    }
86
87    #[doc = "CAC Upper-Limit Value Setting Register"]
88    #[inline(always)]
89    pub const fn caulvr(
90        &self,
91    ) -> &'static crate::common::Reg<self::Caulvr_SPEC, crate::common::RW> {
92        unsafe {
93            crate::common::Reg::<self::Caulvr_SPEC, crate::common::RW>::from_ptr(
94                self._svd2pac_as_ptr().add(6usize),
95            )
96        }
97    }
98
99    #[doc = "CAC Lower-Limit Value Setting Register"]
100    #[inline(always)]
101    pub const fn callvr(
102        &self,
103    ) -> &'static crate::common::Reg<self::Callvr_SPEC, crate::common::RW> {
104        unsafe {
105            crate::common::Reg::<self::Callvr_SPEC, crate::common::RW>::from_ptr(
106                self._svd2pac_as_ptr().add(8usize),
107            )
108        }
109    }
110
111    #[doc = "CAC Counter Buffer Register"]
112    #[inline(always)]
113    pub const fn cacntbr(
114        &self,
115    ) -> &'static crate::common::Reg<self::Cacntbr_SPEC, crate::common::R> {
116        unsafe {
117            crate::common::Reg::<self::Cacntbr_SPEC, crate::common::R>::from_ptr(
118                self._svd2pac_as_ptr().add(10usize),
119            )
120        }
121    }
122}
123#[doc(hidden)]
124#[derive(Copy, Clone, Eq, PartialEq)]
125pub struct Cacr0_SPEC;
126impl crate::sealed::RegSpec for Cacr0_SPEC {
127    type DataType = u8;
128}
129
130#[doc = "CAC Control Register 0"]
131pub type Cacr0 = crate::RegValueT<Cacr0_SPEC>;
132
133impl Cacr0 {
134    #[doc = "These bits are read as 0000000. The write value should be 0000000."]
135    #[inline(always)]
136    pub fn reserved(
137        self,
138    ) -> crate::common::RegisterField<1, 0x7f, 1, 0, u8, u8, Cacr0_SPEC, crate::common::RW> {
139        crate::common::RegisterField::<1,0x7f,1,0,u8,u8,Cacr0_SPEC,crate::common::RW>::from_register(self,0)
140    }
141
142    #[doc = "Clock Frequency Measurement Enable."]
143    #[inline(always)]
144    pub fn cfme(
145        self,
146    ) -> crate::common::RegisterField<
147        0,
148        0x1,
149        1,
150        0,
151        cacr0::Cfme,
152        cacr0::Cfme,
153        Cacr0_SPEC,
154        crate::common::RW,
155    > {
156        crate::common::RegisterField::<
157            0,
158            0x1,
159            1,
160            0,
161            cacr0::Cfme,
162            cacr0::Cfme,
163            Cacr0_SPEC,
164            crate::common::RW,
165        >::from_register(self, 0)
166    }
167}
168impl ::core::default::Default for Cacr0 {
169    #[inline(always)]
170    fn default() -> Cacr0 {
171        <crate::RegValueT<Cacr0_SPEC> as RegisterValue<_>>::new(0)
172    }
173}
174pub mod cacr0 {
175
176    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
177    pub struct Cfme_SPEC;
178    pub type Cfme = crate::EnumBitfieldStruct<u8, Cfme_SPEC>;
179    impl Cfme {
180        #[doc = "Disable"]
181        pub const _0: Self = Self::new(0);
182
183        #[doc = "Enable"]
184        pub const _1: Self = Self::new(1);
185    }
186}
187#[doc(hidden)]
188#[derive(Copy, Clone, Eq, PartialEq)]
189pub struct Cacr1_SPEC;
190impl crate::sealed::RegSpec for Cacr1_SPEC {
191    type DataType = u8;
192}
193
194#[doc = "CAC Control Register 1"]
195pub type Cacr1 = crate::RegValueT<Cacr1_SPEC>;
196
197impl Cacr1 {
198    #[doc = "Valid Edge Select"]
199    #[inline(always)]
200    pub fn edges(
201        self,
202    ) -> crate::common::RegisterField<
203        6,
204        0x3,
205        1,
206        0,
207        cacr1::Edges,
208        cacr1::Edges,
209        Cacr1_SPEC,
210        crate::common::RW,
211    > {
212        crate::common::RegisterField::<
213            6,
214            0x3,
215            1,
216            0,
217            cacr1::Edges,
218            cacr1::Edges,
219            Cacr1_SPEC,
220            crate::common::RW,
221        >::from_register(self, 0)
222    }
223
224    #[doc = "Measurement Target Clock Frequency Division Ratio Select"]
225    #[inline(always)]
226    pub fn tcss(
227        self,
228    ) -> crate::common::RegisterField<
229        4,
230        0x3,
231        1,
232        0,
233        cacr1::Tcss,
234        cacr1::Tcss,
235        Cacr1_SPEC,
236        crate::common::RW,
237    > {
238        crate::common::RegisterField::<
239            4,
240            0x3,
241            1,
242            0,
243            cacr1::Tcss,
244            cacr1::Tcss,
245            Cacr1_SPEC,
246            crate::common::RW,
247        >::from_register(self, 0)
248    }
249
250    #[doc = "Measurement Target Clock Select"]
251    #[inline(always)]
252    pub fn fmcs(
253        self,
254    ) -> crate::common::RegisterField<
255        1,
256        0x7,
257        1,
258        0,
259        cacr1::Fmcs,
260        cacr1::Fmcs,
261        Cacr1_SPEC,
262        crate::common::RW,
263    > {
264        crate::common::RegisterField::<
265            1,
266            0x7,
267            1,
268            0,
269            cacr1::Fmcs,
270            cacr1::Fmcs,
271            Cacr1_SPEC,
272            crate::common::RW,
273        >::from_register(self, 0)
274    }
275
276    #[doc = "CACREF Pin Input Enable"]
277    #[inline(always)]
278    pub fn cacrefe(
279        self,
280    ) -> crate::common::RegisterField<
281        0,
282        0x1,
283        1,
284        0,
285        cacr1::Cacrefe,
286        cacr1::Cacrefe,
287        Cacr1_SPEC,
288        crate::common::RW,
289    > {
290        crate::common::RegisterField::<
291            0,
292            0x1,
293            1,
294            0,
295            cacr1::Cacrefe,
296            cacr1::Cacrefe,
297            Cacr1_SPEC,
298            crate::common::RW,
299        >::from_register(self, 0)
300    }
301}
302impl ::core::default::Default for Cacr1 {
303    #[inline(always)]
304    fn default() -> Cacr1 {
305        <crate::RegValueT<Cacr1_SPEC> as RegisterValue<_>>::new(0)
306    }
307}
308pub mod cacr1 {
309
310    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
311    pub struct Edges_SPEC;
312    pub type Edges = crate::EnumBitfieldStruct<u8, Edges_SPEC>;
313    impl Edges {
314        #[doc = "Rising edge"]
315        pub const _00: Self = Self::new(0);
316
317        #[doc = "Falling edge"]
318        pub const _01: Self = Self::new(1);
319
320        #[doc = "Both rising and falling edges"]
321        pub const _10: Self = Self::new(2);
322
323        #[doc = "Setting prohibited"]
324        pub const _11: Self = Self::new(3);
325    }
326    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
327    pub struct Tcss_SPEC;
328    pub type Tcss = crate::EnumBitfieldStruct<u8, Tcss_SPEC>;
329    impl Tcss {
330        #[doc = "No division"]
331        pub const _00: Self = Self::new(0);
332
333        #[doc = "x 1/4 clock"]
334        pub const _01: Self = Self::new(1);
335
336        #[doc = "x 1/8 clock"]
337        pub const _10: Self = Self::new(2);
338
339        #[doc = "x 1/32 clock"]
340        pub const _11: Self = Self::new(3);
341    }
342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
343    pub struct Fmcs_SPEC;
344    pub type Fmcs = crate::EnumBitfieldStruct<u8, Fmcs_SPEC>;
345    impl Fmcs {
346        #[doc = "Main clock"]
347        pub const _000: Self = Self::new(0);
348
349        #[doc = "Sub-clock"]
350        pub const _001: Self = Self::new(1);
351
352        #[doc = "HOCO clock"]
353        pub const _010: Self = Self::new(2);
354
355        #[doc = "MOCO clock"]
356        pub const _011: Self = Self::new(3);
357
358        #[doc = "LOCO clock"]
359        pub const _100: Self = Self::new(4);
360
361        #[doc = "Peripheral module clock(PCLKB)"]
362        pub const _101: Self = Self::new(5);
363
364        #[doc = "IWDTCLK clock"]
365        pub const _110: Self = Self::new(6);
366
367        #[doc = "Setting prohibited"]
368        pub const _111: Self = Self::new(7);
369    }
370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
371    pub struct Cacrefe_SPEC;
372    pub type Cacrefe = crate::EnumBitfieldStruct<u8, Cacrefe_SPEC>;
373    impl Cacrefe {
374        #[doc = "Disable"]
375        pub const _0: Self = Self::new(0);
376
377        #[doc = "Enable"]
378        pub const _1: Self = Self::new(1);
379    }
380}
381#[doc(hidden)]
382#[derive(Copy, Clone, Eq, PartialEq)]
383pub struct Cacr2_SPEC;
384impl crate::sealed::RegSpec for Cacr2_SPEC {
385    type DataType = u8;
386}
387
388#[doc = "CAC Control Register 2"]
389pub type Cacr2 = crate::RegValueT<Cacr2_SPEC>;
390
391impl Cacr2 {
392    #[doc = "Digital Filter Selection"]
393    #[inline(always)]
394    pub fn dfs(
395        self,
396    ) -> crate::common::RegisterField<
397        6,
398        0x3,
399        1,
400        0,
401        cacr2::Dfs,
402        cacr2::Dfs,
403        Cacr2_SPEC,
404        crate::common::RW,
405    > {
406        crate::common::RegisterField::<
407            6,
408            0x3,
409            1,
410            0,
411            cacr2::Dfs,
412            cacr2::Dfs,
413            Cacr2_SPEC,
414            crate::common::RW,
415        >::from_register(self, 0)
416    }
417
418    #[doc = "Measurement Reference Clock Frequency Division Ratio Select"]
419    #[inline(always)]
420    pub fn rcds(
421        self,
422    ) -> crate::common::RegisterField<
423        4,
424        0x3,
425        1,
426        0,
427        cacr2::Rcds,
428        cacr2::Rcds,
429        Cacr2_SPEC,
430        crate::common::RW,
431    > {
432        crate::common::RegisterField::<
433            4,
434            0x3,
435            1,
436            0,
437            cacr2::Rcds,
438            cacr2::Rcds,
439            Cacr2_SPEC,
440            crate::common::RW,
441        >::from_register(self, 0)
442    }
443
444    #[doc = "Measurement Reference Clock Select"]
445    #[inline(always)]
446    pub fn rscs(
447        self,
448    ) -> crate::common::RegisterField<
449        1,
450        0x7,
451        1,
452        0,
453        cacr2::Rscs,
454        cacr2::Rscs,
455        Cacr2_SPEC,
456        crate::common::RW,
457    > {
458        crate::common::RegisterField::<
459            1,
460            0x7,
461            1,
462            0,
463            cacr2::Rscs,
464            cacr2::Rscs,
465            Cacr2_SPEC,
466            crate::common::RW,
467        >::from_register(self, 0)
468    }
469
470    #[doc = "Reference Signal Select"]
471    #[inline(always)]
472    pub fn rps(
473        self,
474    ) -> crate::common::RegisterField<
475        0,
476        0x1,
477        1,
478        0,
479        cacr2::Rps,
480        cacr2::Rps,
481        Cacr2_SPEC,
482        crate::common::RW,
483    > {
484        crate::common::RegisterField::<
485            0,
486            0x1,
487            1,
488            0,
489            cacr2::Rps,
490            cacr2::Rps,
491            Cacr2_SPEC,
492            crate::common::RW,
493        >::from_register(self, 0)
494    }
495}
496impl ::core::default::Default for Cacr2 {
497    #[inline(always)]
498    fn default() -> Cacr2 {
499        <crate::RegValueT<Cacr2_SPEC> as RegisterValue<_>>::new(0)
500    }
501}
502pub mod cacr2 {
503
504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
505    pub struct Dfs_SPEC;
506    pub type Dfs = crate::EnumBitfieldStruct<u8, Dfs_SPEC>;
507    impl Dfs {
508        #[doc = "Digital filtering is disabled."]
509        pub const _00: Self = Self::new(0);
510
511        #[doc = "The sampling clock for the digital filter is the frequency measuring clock."]
512        pub const _01: Self = Self::new(1);
513
514        #[doc = "The sampling clock for the digital filter is the frequency measuring clock divided by 4."]
515        pub const _10: Self = Self::new(2);
516
517        #[doc = "The sampling clock for the digital filter is the frequency measuring clock divided by 16."]
518        pub const _11: Self = Self::new(3);
519    }
520    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
521    pub struct Rcds_SPEC;
522    pub type Rcds = crate::EnumBitfieldStruct<u8, Rcds_SPEC>;
523    impl Rcds {
524        #[doc = "1/32 clock"]
525        pub const _00: Self = Self::new(0);
526
527        #[doc = "1/128 clock"]
528        pub const _01: Self = Self::new(1);
529
530        #[doc = "1/1024 clock"]
531        pub const _10: Self = Self::new(2);
532
533        #[doc = "1/8192 clock"]
534        pub const _11: Self = Self::new(3);
535    }
536    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
537    pub struct Rscs_SPEC;
538    pub type Rscs = crate::EnumBitfieldStruct<u8, Rscs_SPEC>;
539    impl Rscs {
540        #[doc = "Main clock"]
541        pub const _000: Self = Self::new(0);
542
543        #[doc = "Sub-clock"]
544        pub const _001: Self = Self::new(1);
545
546        #[doc = "HOCO clock"]
547        pub const _010: Self = Self::new(2);
548
549        #[doc = "MOCO clock"]
550        pub const _011: Self = Self::new(3);
551
552        #[doc = "LOCO clock"]
553        pub const _100: Self = Self::new(4);
554
555        #[doc = "Peripheral module clock(PCLKB)"]
556        pub const _101: Self = Self::new(5);
557
558        #[doc = "IWDTCLK clock"]
559        pub const _110: Self = Self::new(6);
560
561        #[doc = "Setting prohibited"]
562        pub const _111: Self = Self::new(7);
563    }
564    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
565    pub struct Rps_SPEC;
566    pub type Rps = crate::EnumBitfieldStruct<u8, Rps_SPEC>;
567    impl Rps {
568        #[doc = "CACREF pin input"]
569        pub const _0: Self = Self::new(0);
570
571        #[doc = "Internal clock (internally generated signal)"]
572        pub const _1: Self = Self::new(1);
573    }
574}
575#[doc(hidden)]
576#[derive(Copy, Clone, Eq, PartialEq)]
577pub struct Caicr_SPEC;
578impl crate::sealed::RegSpec for Caicr_SPEC {
579    type DataType = u8;
580}
581
582#[doc = "CAC Interrupt Control Register"]
583pub type Caicr = crate::RegValueT<Caicr_SPEC>;
584
585impl Caicr {
586    #[doc = "OVFF Clear"]
587    #[inline(always)]
588    pub fn ovffcl(
589        self,
590    ) -> crate::common::RegisterField<
591        6,
592        0x1,
593        1,
594        0,
595        caicr::Ovffcl,
596        caicr::Ovffcl,
597        Caicr_SPEC,
598        crate::common::W,
599    > {
600        crate::common::RegisterField::<
601            6,
602            0x1,
603            1,
604            0,
605            caicr::Ovffcl,
606            caicr::Ovffcl,
607            Caicr_SPEC,
608            crate::common::W,
609        >::from_register(self, 0)
610    }
611
612    #[doc = "MENDF Clear"]
613    #[inline(always)]
614    pub fn mendfcl(
615        self,
616    ) -> crate::common::RegisterField<
617        5,
618        0x1,
619        1,
620        0,
621        caicr::Mendfcl,
622        caicr::Mendfcl,
623        Caicr_SPEC,
624        crate::common::W,
625    > {
626        crate::common::RegisterField::<
627            5,
628            0x1,
629            1,
630            0,
631            caicr::Mendfcl,
632            caicr::Mendfcl,
633            Caicr_SPEC,
634            crate::common::W,
635        >::from_register(self, 0)
636    }
637
638    #[doc = "FERRF Clear"]
639    #[inline(always)]
640    pub fn ferrfcl(
641        self,
642    ) -> crate::common::RegisterField<
643        4,
644        0x1,
645        1,
646        0,
647        caicr::Ferrfcl,
648        caicr::Ferrfcl,
649        Caicr_SPEC,
650        crate::common::W,
651    > {
652        crate::common::RegisterField::<
653            4,
654            0x1,
655            1,
656            0,
657            caicr::Ferrfcl,
658            caicr::Ferrfcl,
659            Caicr_SPEC,
660            crate::common::W,
661        >::from_register(self, 0)
662    }
663
664    #[doc = "This bit is read as 0. The write value should be 0."]
665    #[inline(always)]
666    pub fn reserved(
667        self,
668    ) -> crate::common::RegisterFieldBool<3, 1, 0, Caicr_SPEC, crate::common::RW> {
669        crate::common::RegisterFieldBool::<3, 1, 0, Caicr_SPEC, crate::common::RW>::from_register(
670            self, 0,
671        )
672    }
673
674    #[doc = "Overflow Interrupt Request  Enable"]
675    #[inline(always)]
676    pub fn ovfie(
677        self,
678    ) -> crate::common::RegisterField<
679        2,
680        0x1,
681        1,
682        0,
683        caicr::Ovfie,
684        caicr::Ovfie,
685        Caicr_SPEC,
686        crate::common::RW,
687    > {
688        crate::common::RegisterField::<
689            2,
690            0x1,
691            1,
692            0,
693            caicr::Ovfie,
694            caicr::Ovfie,
695            Caicr_SPEC,
696            crate::common::RW,
697        >::from_register(self, 0)
698    }
699
700    #[doc = "Measurement End Interrupt Request Enable"]
701    #[inline(always)]
702    pub fn mendie(
703        self,
704    ) -> crate::common::RegisterField<
705        1,
706        0x1,
707        1,
708        0,
709        caicr::Mendie,
710        caicr::Mendie,
711        Caicr_SPEC,
712        crate::common::RW,
713    > {
714        crate::common::RegisterField::<
715            1,
716            0x1,
717            1,
718            0,
719            caicr::Mendie,
720            caicr::Mendie,
721            Caicr_SPEC,
722            crate::common::RW,
723        >::from_register(self, 0)
724    }
725
726    #[doc = "Frequency Error Interrupt Request Enable"]
727    #[inline(always)]
728    pub fn ferrie(
729        self,
730    ) -> crate::common::RegisterField<
731        0,
732        0x1,
733        1,
734        0,
735        caicr::Ferrie,
736        caicr::Ferrie,
737        Caicr_SPEC,
738        crate::common::RW,
739    > {
740        crate::common::RegisterField::<
741            0,
742            0x1,
743            1,
744            0,
745            caicr::Ferrie,
746            caicr::Ferrie,
747            Caicr_SPEC,
748            crate::common::RW,
749        >::from_register(self, 0)
750    }
751}
752impl ::core::default::Default for Caicr {
753    #[inline(always)]
754    fn default() -> Caicr {
755        <crate::RegValueT<Caicr_SPEC> as RegisterValue<_>>::new(0)
756    }
757}
758pub mod caicr {
759
760    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
761    pub struct Ovffcl_SPEC;
762    pub type Ovffcl = crate::EnumBitfieldStruct<u8, Ovffcl_SPEC>;
763    impl Ovffcl {
764        #[doc = "No effect on operations"]
765        pub const _0: Self = Self::new(0);
766
767        #[doc = "Clears the OVFF flag"]
768        pub const _1: Self = Self::new(1);
769    }
770    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
771    pub struct Mendfcl_SPEC;
772    pub type Mendfcl = crate::EnumBitfieldStruct<u8, Mendfcl_SPEC>;
773    impl Mendfcl {
774        #[doc = "No effect on operations"]
775        pub const _0: Self = Self::new(0);
776
777        #[doc = "Clears the MENDF flag"]
778        pub const _1: Self = Self::new(1);
779    }
780    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
781    pub struct Ferrfcl_SPEC;
782    pub type Ferrfcl = crate::EnumBitfieldStruct<u8, Ferrfcl_SPEC>;
783    impl Ferrfcl {
784        #[doc = "No effect on operations"]
785        pub const _0: Self = Self::new(0);
786
787        #[doc = "Clears the FERRF flag"]
788        pub const _1: Self = Self::new(1);
789    }
790    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
791    pub struct Ovfie_SPEC;
792    pub type Ovfie = crate::EnumBitfieldStruct<u8, Ovfie_SPEC>;
793    impl Ovfie {
794        #[doc = "Disable"]
795        pub const _0: Self = Self::new(0);
796
797        #[doc = "Enable"]
798        pub const _1: Self = Self::new(1);
799    }
800    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
801    pub struct Mendie_SPEC;
802    pub type Mendie = crate::EnumBitfieldStruct<u8, Mendie_SPEC>;
803    impl Mendie {
804        #[doc = "Disable"]
805        pub const _0: Self = Self::new(0);
806
807        #[doc = "Enable"]
808        pub const _1: Self = Self::new(1);
809    }
810    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
811    pub struct Ferrie_SPEC;
812    pub type Ferrie = crate::EnumBitfieldStruct<u8, Ferrie_SPEC>;
813    impl Ferrie {
814        #[doc = "Disable"]
815        pub const _0: Self = Self::new(0);
816
817        #[doc = "Enable"]
818        pub const _1: Self = Self::new(1);
819    }
820}
821#[doc(hidden)]
822#[derive(Copy, Clone, Eq, PartialEq)]
823pub struct Castr_SPEC;
824impl crate::sealed::RegSpec for Castr_SPEC {
825    type DataType = u8;
826}
827
828#[doc = "CAC Status Register"]
829pub type Castr = crate::RegValueT<Castr_SPEC>;
830
831impl Castr {
832    #[doc = "Counter Overflow Flag"]
833    #[inline(always)]
834    pub fn ovff(
835        self,
836    ) -> crate::common::RegisterField<
837        2,
838        0x1,
839        1,
840        0,
841        castr::Ovff,
842        castr::Ovff,
843        Castr_SPEC,
844        crate::common::R,
845    > {
846        crate::common::RegisterField::<
847            2,
848            0x1,
849            1,
850            0,
851            castr::Ovff,
852            castr::Ovff,
853            Castr_SPEC,
854            crate::common::R,
855        >::from_register(self, 0)
856    }
857
858    #[doc = "Measurement End Flag"]
859    #[inline(always)]
860    pub fn mendf(
861        self,
862    ) -> crate::common::RegisterField<
863        1,
864        0x1,
865        1,
866        0,
867        castr::Mendf,
868        castr::Mendf,
869        Castr_SPEC,
870        crate::common::R,
871    > {
872        crate::common::RegisterField::<
873            1,
874            0x1,
875            1,
876            0,
877            castr::Mendf,
878            castr::Mendf,
879            Castr_SPEC,
880            crate::common::R,
881        >::from_register(self, 0)
882    }
883
884    #[doc = "Frequency Error Flag"]
885    #[inline(always)]
886    pub fn ferrf(
887        self,
888    ) -> crate::common::RegisterField<
889        0,
890        0x1,
891        1,
892        0,
893        castr::Ferrf,
894        castr::Ferrf,
895        Castr_SPEC,
896        crate::common::R,
897    > {
898        crate::common::RegisterField::<
899            0,
900            0x1,
901            1,
902            0,
903            castr::Ferrf,
904            castr::Ferrf,
905            Castr_SPEC,
906            crate::common::R,
907        >::from_register(self, 0)
908    }
909}
910impl ::core::default::Default for Castr {
911    #[inline(always)]
912    fn default() -> Castr {
913        <crate::RegValueT<Castr_SPEC> as RegisterValue<_>>::new(0)
914    }
915}
916pub mod castr {
917
918    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
919    pub struct Ovff_SPEC;
920    pub type Ovff = crate::EnumBitfieldStruct<u8, Ovff_SPEC>;
921    impl Ovff {
922        #[doc = "The counter has not overflowed."]
923        pub const _0: Self = Self::new(0);
924
925        #[doc = "The counter has overflowed."]
926        pub const _1: Self = Self::new(1);
927    }
928    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
929    pub struct Mendf_SPEC;
930    pub type Mendf = crate::EnumBitfieldStruct<u8, Mendf_SPEC>;
931    impl Mendf {
932        #[doc = "Measurement is in progress."]
933        pub const _0: Self = Self::new(0);
934
935        #[doc = "Measurement has ended."]
936        pub const _1: Self = Self::new(1);
937    }
938    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
939    pub struct Ferrf_SPEC;
940    pub type Ferrf = crate::EnumBitfieldStruct<u8, Ferrf_SPEC>;
941    impl Ferrf {
942        #[doc = "The clock frequency is within the range corresponding to the settings."]
943        pub const _0: Self = Self::new(0);
944
945        #[doc = "The clock frequency has deviated beyond the range corresponding to the settings (frequency error)."]
946        pub const _1: Self = Self::new(1);
947    }
948}
949#[doc(hidden)]
950#[derive(Copy, Clone, Eq, PartialEq)]
951pub struct Caulvr_SPEC;
952impl crate::sealed::RegSpec for Caulvr_SPEC {
953    type DataType = u16;
954}
955
956#[doc = "CAC Upper-Limit Value Setting Register"]
957pub type Caulvr = crate::RegValueT<Caulvr_SPEC>;
958
959impl Caulvr {
960    #[doc = "CAULVR is a 16-bit readable/writable register that stores the upper-limit value of the frequency."]
961    #[inline(always)]
962    pub fn caulvr(
963        self,
964    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Caulvr_SPEC, crate::common::RW>
965    {
966        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Caulvr_SPEC,crate::common::RW>::from_register(self,0)
967    }
968}
969impl ::core::default::Default for Caulvr {
970    #[inline(always)]
971    fn default() -> Caulvr {
972        <crate::RegValueT<Caulvr_SPEC> as RegisterValue<_>>::new(0)
973    }
974}
975
976#[doc(hidden)]
977#[derive(Copy, Clone, Eq, PartialEq)]
978pub struct Callvr_SPEC;
979impl crate::sealed::RegSpec for Callvr_SPEC {
980    type DataType = u16;
981}
982
983#[doc = "CAC Lower-Limit Value Setting Register"]
984pub type Callvr = crate::RegValueT<Callvr_SPEC>;
985
986impl Callvr {
987    #[doc = "CALLVR is a 16-bit readable/writable register that stores the lower-limit value of the frequency."]
988    #[inline(always)]
989    pub fn callvr(
990        self,
991    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Callvr_SPEC, crate::common::RW>
992    {
993        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Callvr_SPEC,crate::common::RW>::from_register(self,0)
994    }
995}
996impl ::core::default::Default for Callvr {
997    #[inline(always)]
998    fn default() -> Callvr {
999        <crate::RegValueT<Callvr_SPEC> as RegisterValue<_>>::new(0)
1000    }
1001}
1002
1003#[doc(hidden)]
1004#[derive(Copy, Clone, Eq, PartialEq)]
1005pub struct Cacntbr_SPEC;
1006impl crate::sealed::RegSpec for Cacntbr_SPEC {
1007    type DataType = u16;
1008}
1009
1010#[doc = "CAC Counter Buffer Register"]
1011pub type Cacntbr = crate::RegValueT<Cacntbr_SPEC>;
1012
1013impl Cacntbr {
1014    #[doc = "CACNTBR is a 16-bit read-only register that retains the counter value at the time a valid reference signal edge is input"]
1015    #[inline(always)]
1016    pub fn cacntbr(
1017        self,
1018    ) -> crate::common::RegisterField<0, 0xffff, 1, 0, u16, u16, Cacntbr_SPEC, crate::common::R>
1019    {
1020        crate::common::RegisterField::<0,0xffff,1,0,u16,u16,Cacntbr_SPEC,crate::common::R>::from_register(self,0)
1021    }
1022}
1023impl ::core::default::Default for Cacntbr {
1024    #[inline(always)]
1025    fn default() -> Cacntbr {
1026        <crate::RegValueT<Cacntbr_SPEC> as RegisterValue<_>>::new(0)
1027    }
1028}
ra2a1_pac/cac.rs

ra2a1_pac/
cac.rs
