ra0e1_pac/
sau1.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Array Unit 1"]
28unsafe impl ::core::marker::Send for super::Sau1 {}
29unsafe impl ::core::marker::Sync for super::Sau1 {}
30impl super::Sau1 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Serial Data Register 1%s"]
38    #[inline(always)]
39    pub const fn sdr1(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::Sdr1_SPEC, crate::common::RW>,
43        2,
44        0x2,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn sdr10(&self) -> &'static crate::common::Reg<self::Sdr1_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Sdr1_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0x0usize),
55            )
56        }
57    }
58    #[inline(always)]
59    pub const fn sdr11(&self) -> &'static crate::common::Reg<self::Sdr1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Sdr1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(0x2usize),
63            )
64        }
65    }
66
67    #[doc = "Serial Status Register 10"]
68    #[inline(always)]
69    pub const fn ssr10(&self) -> &'static crate::common::Reg<self::Ssr10_SPEC, crate::common::R> {
70        unsafe {
71            crate::common::Reg::<self::Ssr10_SPEC, crate::common::R>::from_ptr(
72                self._svd2pac_as_ptr().add(256usize),
73            )
74        }
75    }
76
77    #[doc = "Serial Status Register 11"]
78    #[inline(always)]
79    pub const fn ssr11(&self) -> &'static crate::common::Reg<self::Ssr11_SPEC, crate::common::R> {
80        unsafe {
81            crate::common::Reg::<self::Ssr11_SPEC, crate::common::R>::from_ptr(
82                self._svd2pac_as_ptr().add(258usize),
83            )
84        }
85    }
86
87    #[doc = "Serial Flag Clear Trigger Register 10"]
88    #[inline(always)]
89    pub const fn sir10(&self) -> &'static crate::common::Reg<self::Sir10_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Sir10_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(264usize),
93            )
94        }
95    }
96
97    #[doc = "Serial Flag Clear Trigger Register 11"]
98    #[inline(always)]
99    pub const fn sir11(&self) -> &'static crate::common::Reg<self::Sir11_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Sir11_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(266usize),
103            )
104        }
105    }
106
107    #[doc = "Serial Mode Register 10"]
108    #[inline(always)]
109    pub const fn smr10(&self) -> &'static crate::common::Reg<self::Smr10_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Smr10_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(272usize),
113            )
114        }
115    }
116
117    #[doc = "Serial Mode Register 11"]
118    #[inline(always)]
119    pub const fn smr11(&self) -> &'static crate::common::Reg<self::Smr11_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Smr11_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(274usize),
123            )
124        }
125    }
126
127    #[doc = "Serial Communication Operation Setting Register 10"]
128    #[inline(always)]
129    pub const fn scr10(&self) -> &'static crate::common::Reg<self::Scr10_SPEC, crate::common::RW> {
130        unsafe {
131            crate::common::Reg::<self::Scr10_SPEC, crate::common::RW>::from_ptr(
132                self._svd2pac_as_ptr().add(280usize),
133            )
134        }
135    }
136
137    #[doc = "Serial Communication Operation Setting Register 11"]
138    #[inline(always)]
139    pub const fn scr11(&self) -> &'static crate::common::Reg<self::Scr11_SPEC, crate::common::RW> {
140        unsafe {
141            crate::common::Reg::<self::Scr11_SPEC, crate::common::RW>::from_ptr(
142                self._svd2pac_as_ptr().add(282usize),
143            )
144        }
145    }
146
147    #[doc = "Serial Channel Enable Status Register 1"]
148    #[inline(always)]
149    pub const fn se1(&self) -> &'static crate::common::Reg<self::Se1_SPEC, crate::common::R> {
150        unsafe {
151            crate::common::Reg::<self::Se1_SPEC, crate::common::R>::from_ptr(
152                self._svd2pac_as_ptr().add(288usize),
153            )
154        }
155    }
156
157    #[doc = "Serial Channel Start Register 1"]
158    #[inline(always)]
159    pub const fn ss1(&self) -> &'static crate::common::Reg<self::Ss1_SPEC, crate::common::RW> {
160        unsafe {
161            crate::common::Reg::<self::Ss1_SPEC, crate::common::RW>::from_ptr(
162                self._svd2pac_as_ptr().add(290usize),
163            )
164        }
165    }
166
167    #[doc = "Serial Channel Stop Register 1"]
168    #[inline(always)]
169    pub const fn st1(&self) -> &'static crate::common::Reg<self::St1_SPEC, crate::common::RW> {
170        unsafe {
171            crate::common::Reg::<self::St1_SPEC, crate::common::RW>::from_ptr(
172                self._svd2pac_as_ptr().add(292usize),
173            )
174        }
175    }
176
177    #[doc = "Serial Clock Select Register 1"]
178    #[inline(always)]
179    pub const fn sps1(&self) -> &'static crate::common::Reg<self::Sps1_SPEC, crate::common::RW> {
180        unsafe {
181            crate::common::Reg::<self::Sps1_SPEC, crate::common::RW>::from_ptr(
182                self._svd2pac_as_ptr().add(294usize),
183            )
184        }
185    }
186
187    #[doc = "Serial Output Register 1"]
188    #[inline(always)]
189    pub const fn so1(&self) -> &'static crate::common::Reg<self::So1_SPEC, crate::common::RW> {
190        unsafe {
191            crate::common::Reg::<self::So1_SPEC, crate::common::RW>::from_ptr(
192                self._svd2pac_as_ptr().add(296usize),
193            )
194        }
195    }
196
197    #[doc = "Serial Output Enable Register 1"]
198    #[inline(always)]
199    pub const fn soe1(&self) -> &'static crate::common::Reg<self::Soe1_SPEC, crate::common::RW> {
200        unsafe {
201            crate::common::Reg::<self::Soe1_SPEC, crate::common::RW>::from_ptr(
202                self._svd2pac_as_ptr().add(298usize),
203            )
204        }
205    }
206
207    #[doc = "Serial Output Level Register 1"]
208    #[inline(always)]
209    pub const fn sol1(&self) -> &'static crate::common::Reg<self::Sol1_SPEC, crate::common::RW> {
210        unsafe {
211            crate::common::Reg::<self::Sol1_SPEC, crate::common::RW>::from_ptr(
212                self._svd2pac_as_ptr().add(308usize),
213            )
214        }
215    }
216}
217#[doc(hidden)]
218#[derive(Copy, Clone, Eq, PartialEq)]
219pub struct Sdr1_SPEC;
220impl crate::sealed::RegSpec for Sdr1_SPEC {
221    type DataType = u16;
222}
223
224#[doc = "Serial Data Register 1%s"]
225pub type Sdr1 = crate::RegValueT<Sdr1_SPEC>;
226
227impl Sdr1 {
228    #[doc = "Data Buffer for Transmit and Receive"]
229    #[inline(always)]
230    pub fn dat(
231        self,
232    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Sdr1_SPEC, crate::common::RW> {
233        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Sdr1_SPEC,crate::common::RW>::from_register(self,0)
234    }
235
236    #[doc = "Transfer Clock Setting by Dividing the Operation Clock"]
237    #[inline(always)]
238    pub fn stclk(
239        self,
240    ) -> crate::common::RegisterField<9, 0x7f, 1, 0, u8, u8, Sdr1_SPEC, crate::common::RW> {
241        crate::common::RegisterField::<9,0x7f,1,0,u8,u8,Sdr1_SPEC,crate::common::RW>::from_register(self,0)
242    }
243}
244impl ::core::default::Default for Sdr1 {
245    #[inline(always)]
246    fn default() -> Sdr1 {
247        <crate::RegValueT<Sdr1_SPEC> as RegisterValue<_>>::new(0)
248    }
249}
250
251#[doc(hidden)]
252#[derive(Copy, Clone, Eq, PartialEq)]
253pub struct Ssr10_SPEC;
254impl crate::sealed::RegSpec for Ssr10_SPEC {
255    type DataType = u16;
256}
257
258#[doc = "Serial Status Register 10"]
259pub type Ssr10 = crate::RegValueT<Ssr10_SPEC>;
260
261impl Ssr10 {
262    #[doc = "Overrun Error Detection Flag of Channel n"]
263    #[inline(always)]
264    pub fn ovf(
265        self,
266    ) -> crate::common::RegisterField<
267        0,
268        0x1,
269        1,
270        0,
271        ssr10::Ovf,
272        ssr10::Ovf,
273        Ssr10_SPEC,
274        crate::common::R,
275    > {
276        crate::common::RegisterField::<
277            0,
278            0x1,
279            1,
280            0,
281            ssr10::Ovf,
282            ssr10::Ovf,
283            Ssr10_SPEC,
284            crate::common::R,
285        >::from_register(self, 0)
286    }
287
288    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
289    #[inline(always)]
290    pub fn pef(
291        self,
292    ) -> crate::common::RegisterField<
293        1,
294        0x1,
295        1,
296        0,
297        ssr10::Pef,
298        ssr10::Pef,
299        Ssr10_SPEC,
300        crate::common::R,
301    > {
302        crate::common::RegisterField::<
303            1,
304            0x1,
305            1,
306            0,
307            ssr10::Pef,
308            ssr10::Pef,
309            Ssr10_SPEC,
310            crate::common::R,
311        >::from_register(self, 0)
312    }
313
314    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
315    #[inline(always)]
316    pub fn bff(
317        self,
318    ) -> crate::common::RegisterField<
319        5,
320        0x1,
321        1,
322        0,
323        ssr10::Bff,
324        ssr10::Bff,
325        Ssr10_SPEC,
326        crate::common::R,
327    > {
328        crate::common::RegisterField::<
329            5,
330            0x1,
331            1,
332            0,
333            ssr10::Bff,
334            ssr10::Bff,
335            Ssr10_SPEC,
336            crate::common::R,
337        >::from_register(self, 0)
338    }
339
340    #[doc = "Flag Indicating the State of Communications for Channel n"]
341    #[inline(always)]
342    pub fn tsf(
343        self,
344    ) -> crate::common::RegisterField<
345        6,
346        0x1,
347        1,
348        0,
349        ssr10::Tsf,
350        ssr10::Tsf,
351        Ssr10_SPEC,
352        crate::common::R,
353    > {
354        crate::common::RegisterField::<
355            6,
356            0x1,
357            1,
358            0,
359            ssr10::Tsf,
360            ssr10::Tsf,
361            Ssr10_SPEC,
362            crate::common::R,
363        >::from_register(self, 0)
364    }
365}
366impl ::core::default::Default for Ssr10 {
367    #[inline(always)]
368    fn default() -> Ssr10 {
369        <crate::RegValueT<Ssr10_SPEC> as RegisterValue<_>>::new(0)
370    }
371}
372pub mod ssr10 {
373
374    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
375    pub struct Ovf_SPEC;
376    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
377    impl Ovf {
378        #[doc = "No error occurs"]
379        pub const _0: Self = Self::new(0);
380
381        #[doc = "An error occurs"]
382        pub const _1: Self = Self::new(1);
383    }
384    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
385    pub struct Pef_SPEC;
386    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
387    impl Pef {
388        #[doc = "No error occurs"]
389        pub const _0: Self = Self::new(0);
390
391        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
392        pub const _1: Self = Self::new(1);
393    }
394    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
395    pub struct Bff_SPEC;
396    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
397    impl Bff {
398        #[doc = "Valid data is not stored in the SDRmn register"]
399        pub const _0: Self = Self::new(0);
400
401        #[doc = "Valid data is stored in the SDRmn register"]
402        pub const _1: Self = Self::new(1);
403    }
404    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
405    pub struct Tsf_SPEC;
406    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
407    impl Tsf {
408        #[doc = "Communication is stopped or suspended"]
409        pub const _0: Self = Self::new(0);
410
411        #[doc = "Communication is in progress"]
412        pub const _1: Self = Self::new(1);
413    }
414}
415#[doc(hidden)]
416#[derive(Copy, Clone, Eq, PartialEq)]
417pub struct Ssr11_SPEC;
418impl crate::sealed::RegSpec for Ssr11_SPEC {
419    type DataType = u16;
420}
421
422#[doc = "Serial Status Register 11"]
423pub type Ssr11 = crate::RegValueT<Ssr11_SPEC>;
424
425impl Ssr11 {
426    #[doc = "Overrun Error Detection Flag of Channel n"]
427    #[inline(always)]
428    pub fn ovf(
429        self,
430    ) -> crate::common::RegisterField<
431        0,
432        0x1,
433        1,
434        0,
435        ssr11::Ovf,
436        ssr11::Ovf,
437        Ssr11_SPEC,
438        crate::common::R,
439    > {
440        crate::common::RegisterField::<
441            0,
442            0x1,
443            1,
444            0,
445            ssr11::Ovf,
446            ssr11::Ovf,
447            Ssr11_SPEC,
448            crate::common::R,
449        >::from_register(self, 0)
450    }
451
452    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
453    #[inline(always)]
454    pub fn pef(
455        self,
456    ) -> crate::common::RegisterField<
457        1,
458        0x1,
459        1,
460        0,
461        ssr11::Pef,
462        ssr11::Pef,
463        Ssr11_SPEC,
464        crate::common::R,
465    > {
466        crate::common::RegisterField::<
467            1,
468            0x1,
469            1,
470            0,
471            ssr11::Pef,
472            ssr11::Pef,
473            Ssr11_SPEC,
474            crate::common::R,
475        >::from_register(self, 0)
476    }
477
478    #[doc = "Framing Error Detection Flag of Channel n"]
479    #[inline(always)]
480    pub fn fef(
481        self,
482    ) -> crate::common::RegisterField<
483        2,
484        0x1,
485        1,
486        0,
487        ssr11::Fef,
488        ssr11::Fef,
489        Ssr11_SPEC,
490        crate::common::R,
491    > {
492        crate::common::RegisterField::<
493            2,
494            0x1,
495            1,
496            0,
497            ssr11::Fef,
498            ssr11::Fef,
499            Ssr11_SPEC,
500            crate::common::R,
501        >::from_register(self, 0)
502    }
503
504    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
505    #[inline(always)]
506    pub fn bff(
507        self,
508    ) -> crate::common::RegisterField<
509        5,
510        0x1,
511        1,
512        0,
513        ssr11::Bff,
514        ssr11::Bff,
515        Ssr11_SPEC,
516        crate::common::R,
517    > {
518        crate::common::RegisterField::<
519            5,
520            0x1,
521            1,
522            0,
523            ssr11::Bff,
524            ssr11::Bff,
525            Ssr11_SPEC,
526            crate::common::R,
527        >::from_register(self, 0)
528    }
529
530    #[doc = "Flag Indicating the State of Communications for Channel n"]
531    #[inline(always)]
532    pub fn tsf(
533        self,
534    ) -> crate::common::RegisterField<
535        6,
536        0x1,
537        1,
538        0,
539        ssr11::Tsf,
540        ssr11::Tsf,
541        Ssr11_SPEC,
542        crate::common::R,
543    > {
544        crate::common::RegisterField::<
545            6,
546            0x1,
547            1,
548            0,
549            ssr11::Tsf,
550            ssr11::Tsf,
551            Ssr11_SPEC,
552            crate::common::R,
553        >::from_register(self, 0)
554    }
555}
556impl ::core::default::Default for Ssr11 {
557    #[inline(always)]
558    fn default() -> Ssr11 {
559        <crate::RegValueT<Ssr11_SPEC> as RegisterValue<_>>::new(0)
560    }
561}
562pub mod ssr11 {
563
564    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
565    pub struct Ovf_SPEC;
566    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
567    impl Ovf {
568        #[doc = "No error occurs"]
569        pub const _0: Self = Self::new(0);
570
571        #[doc = "An error occurs"]
572        pub const _1: Self = Self::new(1);
573    }
574    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
575    pub struct Pef_SPEC;
576    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
577    impl Pef {
578        #[doc = "No error occurs"]
579        pub const _0: Self = Self::new(0);
580
581        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
582        pub const _1: Self = Self::new(1);
583    }
584    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
585    pub struct Fef_SPEC;
586    pub type Fef = crate::EnumBitfieldStruct<u8, Fef_SPEC>;
587    impl Fef {
588        #[doc = "No error occurs"]
589        pub const _0: Self = Self::new(0);
590
591        #[doc = "An error occurs (during UART reception)"]
592        pub const _1: Self = Self::new(1);
593    }
594    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
595    pub struct Bff_SPEC;
596    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
597    impl Bff {
598        #[doc = "Valid data is not stored in the SDRmn register"]
599        pub const _0: Self = Self::new(0);
600
601        #[doc = "Valid data is stored in the SDRmn register"]
602        pub const _1: Self = Self::new(1);
603    }
604    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
605    pub struct Tsf_SPEC;
606    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
607    impl Tsf {
608        #[doc = "Communication is stopped or suspended"]
609        pub const _0: Self = Self::new(0);
610
611        #[doc = "Communication is in progress"]
612        pub const _1: Self = Self::new(1);
613    }
614}
615#[doc(hidden)]
616#[derive(Copy, Clone, Eq, PartialEq)]
617pub struct Sir10_SPEC;
618impl crate::sealed::RegSpec for Sir10_SPEC {
619    type DataType = u16;
620}
621
622#[doc = "Serial Flag Clear Trigger Register 10"]
623pub type Sir10 = crate::RegValueT<Sir10_SPEC>;
624
625impl Sir10 {
626    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
627    #[inline(always)]
628    pub fn ovct(
629        self,
630    ) -> crate::common::RegisterField<
631        0,
632        0x1,
633        1,
634        0,
635        sir10::Ovct,
636        sir10::Ovct,
637        Sir10_SPEC,
638        crate::common::RW,
639    > {
640        crate::common::RegisterField::<
641            0,
642            0x1,
643            1,
644            0,
645            sir10::Ovct,
646            sir10::Ovct,
647            Sir10_SPEC,
648            crate::common::RW,
649        >::from_register(self, 0)
650    }
651
652    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
653    #[inline(always)]
654    pub fn pect(
655        self,
656    ) -> crate::common::RegisterField<
657        1,
658        0x1,
659        1,
660        0,
661        sir10::Pect,
662        sir10::Pect,
663        Sir10_SPEC,
664        crate::common::RW,
665    > {
666        crate::common::RegisterField::<
667            1,
668            0x1,
669            1,
670            0,
671            sir10::Pect,
672            sir10::Pect,
673            Sir10_SPEC,
674            crate::common::RW,
675        >::from_register(self, 0)
676    }
677}
678impl ::core::default::Default for Sir10 {
679    #[inline(always)]
680    fn default() -> Sir10 {
681        <crate::RegValueT<Sir10_SPEC> as RegisterValue<_>>::new(0)
682    }
683}
684pub mod sir10 {
685
686    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
687    pub struct Ovct_SPEC;
688    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
689    impl Ovct {
690        #[doc = "Not cleared"]
691        pub const _0: Self = Self::new(0);
692
693        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
694        pub const _1: Self = Self::new(1);
695    }
696    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
697    pub struct Pect_SPEC;
698    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
699    impl Pect {
700        #[doc = "Not cleared"]
701        pub const _0: Self = Self::new(0);
702
703        #[doc = "Clears the PEF bit of the SSRmn register to 0."]
704        pub const _1: Self = Self::new(1);
705    }
706}
707#[doc(hidden)]
708#[derive(Copy, Clone, Eq, PartialEq)]
709pub struct Sir11_SPEC;
710impl crate::sealed::RegSpec for Sir11_SPEC {
711    type DataType = u16;
712}
713
714#[doc = "Serial Flag Clear Trigger Register 11"]
715pub type Sir11 = crate::RegValueT<Sir11_SPEC>;
716
717impl Sir11 {
718    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
719    #[inline(always)]
720    pub fn ovct(
721        self,
722    ) -> crate::common::RegisterField<
723        0,
724        0x1,
725        1,
726        0,
727        sir11::Ovct,
728        sir11::Ovct,
729        Sir11_SPEC,
730        crate::common::RW,
731    > {
732        crate::common::RegisterField::<
733            0,
734            0x1,
735            1,
736            0,
737            sir11::Ovct,
738            sir11::Ovct,
739            Sir11_SPEC,
740            crate::common::RW,
741        >::from_register(self, 0)
742    }
743
744    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
745    #[inline(always)]
746    pub fn pect(
747        self,
748    ) -> crate::common::RegisterField<
749        1,
750        0x1,
751        1,
752        0,
753        sir11::Pect,
754        sir11::Pect,
755        Sir11_SPEC,
756        crate::common::RW,
757    > {
758        crate::common::RegisterField::<
759            1,
760            0x1,
761            1,
762            0,
763            sir11::Pect,
764            sir11::Pect,
765            Sir11_SPEC,
766            crate::common::RW,
767        >::from_register(self, 0)
768    }
769
770    #[doc = "Clear Trigger of Framing Error Flag of Channel n"]
771    #[inline(always)]
772    pub fn fect(
773        self,
774    ) -> crate::common::RegisterField<
775        2,
776        0x1,
777        1,
778        0,
779        sir11::Fect,
780        sir11::Fect,
781        Sir11_SPEC,
782        crate::common::RW,
783    > {
784        crate::common::RegisterField::<
785            2,
786            0x1,
787            1,
788            0,
789            sir11::Fect,
790            sir11::Fect,
791            Sir11_SPEC,
792            crate::common::RW,
793        >::from_register(self, 0)
794    }
795}
796impl ::core::default::Default for Sir11 {
797    #[inline(always)]
798    fn default() -> Sir11 {
799        <crate::RegValueT<Sir11_SPEC> as RegisterValue<_>>::new(0)
800    }
801}
802pub mod sir11 {
803
804    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
805    pub struct Ovct_SPEC;
806    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
807    impl Ovct {
808        #[doc = "Not cleared"]
809        pub const _0: Self = Self::new(0);
810
811        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
812        pub const _1: Self = Self::new(1);
813    }
814    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
815    pub struct Pect_SPEC;
816    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
817    impl Pect {
818        #[doc = "Not cleared"]
819        pub const _0: Self = Self::new(0);
820
821        #[doc = "Clears the PEF bit of the SSRmn register to 0"]
822        pub const _1: Self = Self::new(1);
823    }
824    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
825    pub struct Fect_SPEC;
826    pub type Fect = crate::EnumBitfieldStruct<u8, Fect_SPEC>;
827    impl Fect {
828        #[doc = "Not cleared"]
829        pub const _0: Self = Self::new(0);
830
831        #[doc = "Clears the FEF bit of the SSRmn register to 0"]
832        pub const _1: Self = Self::new(1);
833    }
834}
835#[doc(hidden)]
836#[derive(Copy, Clone, Eq, PartialEq)]
837pub struct Smr10_SPEC;
838impl crate::sealed::RegSpec for Smr10_SPEC {
839    type DataType = u16;
840}
841
842#[doc = "Serial Mode Register 10"]
843pub type Smr10 = crate::RegValueT<Smr10_SPEC>;
844
845impl Smr10 {
846    #[doc = "Selection of Channel n Interrupt Source"]
847    #[inline(always)]
848    pub fn md0(
849        self,
850    ) -> crate::common::RegisterField<
851        0,
852        0x1,
853        1,
854        0,
855        smr10::Md0,
856        smr10::Md0,
857        Smr10_SPEC,
858        crate::common::RW,
859    > {
860        crate::common::RegisterField::<
861            0,
862            0x1,
863            1,
864            0,
865            smr10::Md0,
866            smr10::Md0,
867            Smr10_SPEC,
868            crate::common::RW,
869        >::from_register(self, 0)
870    }
871
872    #[doc = "Setting of Channel n Operation Mode"]
873    #[inline(always)]
874    pub fn md1(
875        self,
876    ) -> crate::common::RegisterField<
877        1,
878        0x3,
879        1,
880        0,
881        smr10::Md1,
882        smr10::Md1,
883        Smr10_SPEC,
884        crate::common::RW,
885    > {
886        crate::common::RegisterField::<
887            1,
888            0x3,
889            1,
890            0,
891            smr10::Md1,
892            smr10::Md1,
893            Smr10_SPEC,
894            crate::common::RW,
895        >::from_register(self, 0)
896    }
897
898    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
899    #[inline(always)]
900    pub fn ccs(
901        self,
902    ) -> crate::common::RegisterField<
903        14,
904        0x1,
905        1,
906        0,
907        smr10::Ccs,
908        smr10::Ccs,
909        Smr10_SPEC,
910        crate::common::RW,
911    > {
912        crate::common::RegisterField::<
913            14,
914            0x1,
915            1,
916            0,
917            smr10::Ccs,
918            smr10::Ccs,
919            Smr10_SPEC,
920            crate::common::RW,
921        >::from_register(self, 0)
922    }
923
924    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
925    #[inline(always)]
926    pub fn cks(
927        self,
928    ) -> crate::common::RegisterField<
929        15,
930        0x1,
931        1,
932        0,
933        smr10::Cks,
934        smr10::Cks,
935        Smr10_SPEC,
936        crate::common::RW,
937    > {
938        crate::common::RegisterField::<
939            15,
940            0x1,
941            1,
942            0,
943            smr10::Cks,
944            smr10::Cks,
945            Smr10_SPEC,
946            crate::common::RW,
947        >::from_register(self, 0)
948    }
949}
950impl ::core::default::Default for Smr10 {
951    #[inline(always)]
952    fn default() -> Smr10 {
953        <crate::RegValueT<Smr10_SPEC> as RegisterValue<_>>::new(32)
954    }
955}
956pub mod smr10 {
957
958    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
959    pub struct Md0_SPEC;
960    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
961    impl Md0 {
962        #[doc = "Transfer end interrupt"]
963        pub const _0: Self = Self::new(0);
964
965        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
966        pub const _1: Self = Self::new(1);
967    }
968    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
969    pub struct Md1_SPEC;
970    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
971    impl Md1 {
972        #[doc = "Simplified SPI mode"]
973        pub const _00: Self = Self::new(0);
974
975        #[doc = "UART mode"]
976        pub const _01: Self = Self::new(1);
977
978        #[doc = "Simplified I2C mode"]
979        pub const _10: Self = Self::new(2);
980
981        #[doc = "Setting prohibited"]
982        pub const _11: Self = Self::new(3);
983    }
984    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
985    pub struct Ccs_SPEC;
986    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
987    impl Ccs {
988        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
989        pub const _0: Self = Self::new(0);
990
991        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
992        pub const _1: Self = Self::new(1);
993    }
994    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
995    pub struct Cks_SPEC;
996    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
997    impl Cks {
998        #[doc = "Operation clock CKm0 set by the SPSm register"]
999        pub const _0: Self = Self::new(0);
1000
1001        #[doc = "Operation clock CKm1 set by the SPSm register"]
1002        pub const _1: Self = Self::new(1);
1003    }
1004}
1005#[doc(hidden)]
1006#[derive(Copy, Clone, Eq, PartialEq)]
1007pub struct Smr11_SPEC;
1008impl crate::sealed::RegSpec for Smr11_SPEC {
1009    type DataType = u16;
1010}
1011
1012#[doc = "Serial Mode Register 11"]
1013pub type Smr11 = crate::RegValueT<Smr11_SPEC>;
1014
1015impl Smr11 {
1016    #[doc = "Selection of Channel n Interrupt Source"]
1017    #[inline(always)]
1018    pub fn md0(
1019        self,
1020    ) -> crate::common::RegisterField<
1021        0,
1022        0x1,
1023        1,
1024        0,
1025        smr11::Md0,
1026        smr11::Md0,
1027        Smr11_SPEC,
1028        crate::common::RW,
1029    > {
1030        crate::common::RegisterField::<
1031            0,
1032            0x1,
1033            1,
1034            0,
1035            smr11::Md0,
1036            smr11::Md0,
1037            Smr11_SPEC,
1038            crate::common::RW,
1039        >::from_register(self, 0)
1040    }
1041
1042    #[doc = "Setting of Channel n Operation Mode"]
1043    #[inline(always)]
1044    pub fn md1(
1045        self,
1046    ) -> crate::common::RegisterField<
1047        1,
1048        0x3,
1049        1,
1050        0,
1051        smr11::Md1,
1052        smr11::Md1,
1053        Smr11_SPEC,
1054        crate::common::RW,
1055    > {
1056        crate::common::RegisterField::<
1057            1,
1058            0x3,
1059            1,
1060            0,
1061            smr11::Md1,
1062            smr11::Md1,
1063            Smr11_SPEC,
1064            crate::common::RW,
1065        >::from_register(self, 0)
1066    }
1067
1068    #[doc = "Controls Inversion of Level of Channel n Receive Data in UART Mode"]
1069    #[inline(always)]
1070    pub fn sis0(
1071        self,
1072    ) -> crate::common::RegisterField<
1073        6,
1074        0x1,
1075        1,
1076        0,
1077        smr11::Sis0,
1078        smr11::Sis0,
1079        Smr11_SPEC,
1080        crate::common::RW,
1081    > {
1082        crate::common::RegisterField::<
1083            6,
1084            0x1,
1085            1,
1086            0,
1087            smr11::Sis0,
1088            smr11::Sis0,
1089            Smr11_SPEC,
1090            crate::common::RW,
1091        >::from_register(self, 0)
1092    }
1093
1094    #[doc = "Selection of Start Trigger Source"]
1095    #[inline(always)]
1096    pub fn sts(
1097        self,
1098    ) -> crate::common::RegisterField<
1099        8,
1100        0x1,
1101        1,
1102        0,
1103        smr11::Sts,
1104        smr11::Sts,
1105        Smr11_SPEC,
1106        crate::common::RW,
1107    > {
1108        crate::common::RegisterField::<
1109            8,
1110            0x1,
1111            1,
1112            0,
1113            smr11::Sts,
1114            smr11::Sts,
1115            Smr11_SPEC,
1116            crate::common::RW,
1117        >::from_register(self, 0)
1118    }
1119
1120    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
1121    #[inline(always)]
1122    pub fn ccs(
1123        self,
1124    ) -> crate::common::RegisterField<
1125        14,
1126        0x1,
1127        1,
1128        0,
1129        smr11::Ccs,
1130        smr11::Ccs,
1131        Smr11_SPEC,
1132        crate::common::RW,
1133    > {
1134        crate::common::RegisterField::<
1135            14,
1136            0x1,
1137            1,
1138            0,
1139            smr11::Ccs,
1140            smr11::Ccs,
1141            Smr11_SPEC,
1142            crate::common::RW,
1143        >::from_register(self, 0)
1144    }
1145
1146    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1147    #[inline(always)]
1148    pub fn cks(
1149        self,
1150    ) -> crate::common::RegisterField<
1151        15,
1152        0x1,
1153        1,
1154        0,
1155        smr11::Cks,
1156        smr11::Cks,
1157        Smr11_SPEC,
1158        crate::common::RW,
1159    > {
1160        crate::common::RegisterField::<
1161            15,
1162            0x1,
1163            1,
1164            0,
1165            smr11::Cks,
1166            smr11::Cks,
1167            Smr11_SPEC,
1168            crate::common::RW,
1169        >::from_register(self, 0)
1170    }
1171}
1172impl ::core::default::Default for Smr11 {
1173    #[inline(always)]
1174    fn default() -> Smr11 {
1175        <crate::RegValueT<Smr11_SPEC> as RegisterValue<_>>::new(32)
1176    }
1177}
1178pub mod smr11 {
1179
1180    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1181    pub struct Md0_SPEC;
1182    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
1183    impl Md0 {
1184        #[doc = "Transfer end interrupt"]
1185        pub const _0: Self = Self::new(0);
1186
1187        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
1188        pub const _1: Self = Self::new(1);
1189    }
1190    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1191    pub struct Md1_SPEC;
1192    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
1193    impl Md1 {
1194        #[doc = "Simplified SPI mode"]
1195        pub const _00: Self = Self::new(0);
1196
1197        #[doc = "UART mode"]
1198        pub const _01: Self = Self::new(1);
1199
1200        #[doc = "Simplified I2C mode"]
1201        pub const _10: Self = Self::new(2);
1202
1203        #[doc = "Setting prohibited"]
1204        pub const _11: Self = Self::new(3);
1205    }
1206    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1207    pub struct Sis0_SPEC;
1208    pub type Sis0 = crate::EnumBitfieldStruct<u8, Sis0_SPEC>;
1209    impl Sis0 {
1210        #[doc = "Falling edge is detected as the start bit. The input communication data is captured as is."]
1211        pub const _0: Self = Self::new(0);
1212
1213        #[doc = "Rising edge is detected as the start bit. The input communication data is inverted and captured."]
1214        pub const _1: Self = Self::new(1);
1215    }
1216    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1217    pub struct Sts_SPEC;
1218    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1219    impl Sts {
1220        #[doc = "Only software trigger is valid (selected for simplified SPI, UART transmission, and simplified I2C)"]
1221        pub const _0: Self = Self::new(0);
1222
1223        #[doc = "Valid edge of the RXDq pin (selected for UART reception)"]
1224        pub const _1: Self = Self::new(1);
1225    }
1226    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1227    pub struct Ccs_SPEC;
1228    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1229    impl Ccs {
1230        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
1231        pub const _0: Self = Self::new(0);
1232
1233        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
1234        pub const _1: Self = Self::new(1);
1235    }
1236    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1237    pub struct Cks_SPEC;
1238    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1239    impl Cks {
1240        #[doc = "Operation clock CKm0 set by the SPSm register"]
1241        pub const _0: Self = Self::new(0);
1242
1243        #[doc = "Operation clock CKm1 set by the SPSm register"]
1244        pub const _1: Self = Self::new(1);
1245    }
1246}
1247#[doc(hidden)]
1248#[derive(Copy, Clone, Eq, PartialEq)]
1249pub struct Scr10_SPEC;
1250impl crate::sealed::RegSpec for Scr10_SPEC {
1251    type DataType = u16;
1252}
1253
1254#[doc = "Serial Communication Operation Setting Register 10"]
1255pub type Scr10 = crate::RegValueT<Scr10_SPEC>;
1256
1257impl Scr10 {
1258    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
1259    #[inline(always)]
1260    pub fn dls(
1261        self,
1262    ) -> crate::common::RegisterField<
1263        0,
1264        0x3,
1265        1,
1266        0,
1267        scr10::Dls,
1268        scr10::Dls,
1269        Scr10_SPEC,
1270        crate::common::RW,
1271    > {
1272        crate::common::RegisterField::<
1273            0,
1274            0x3,
1275            1,
1276            0,
1277            scr10::Dls,
1278            scr10::Dls,
1279            Scr10_SPEC,
1280            crate::common::RW,
1281        >::from_register(self, 0)
1282    }
1283
1284    #[doc = "Setting of Stop Bit in UART Mode"]
1285    #[inline(always)]
1286    pub fn slc(
1287        self,
1288    ) -> crate::common::RegisterField<
1289        4,
1290        0x3,
1291        1,
1292        0,
1293        scr10::Slc,
1294        scr10::Slc,
1295        Scr10_SPEC,
1296        crate::common::RW,
1297    > {
1298        crate::common::RegisterField::<
1299            4,
1300            0x3,
1301            1,
1302            0,
1303            scr10::Slc,
1304            scr10::Slc,
1305            Scr10_SPEC,
1306            crate::common::RW,
1307        >::from_register(self, 0)
1308    }
1309
1310    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
1311    #[inline(always)]
1312    pub fn dir(
1313        self,
1314    ) -> crate::common::RegisterField<
1315        7,
1316        0x1,
1317        1,
1318        0,
1319        scr10::Dir,
1320        scr10::Dir,
1321        Scr10_SPEC,
1322        crate::common::RW,
1323    > {
1324        crate::common::RegisterField::<
1325            7,
1326            0x1,
1327            1,
1328            0,
1329            scr10::Dir,
1330            scr10::Dir,
1331            Scr10_SPEC,
1332            crate::common::RW,
1333        >::from_register(self, 0)
1334    }
1335
1336    #[doc = "Setting of Parity Bit in UART Mode"]
1337    #[inline(always)]
1338    pub fn ptc(
1339        self,
1340    ) -> crate::common::RegisterField<
1341        8,
1342        0x3,
1343        1,
1344        0,
1345        scr10::Ptc,
1346        scr10::Ptc,
1347        Scr10_SPEC,
1348        crate::common::RW,
1349    > {
1350        crate::common::RegisterField::<
1351            8,
1352            0x3,
1353            1,
1354            0,
1355            scr10::Ptc,
1356            scr10::Ptc,
1357            Scr10_SPEC,
1358            crate::common::RW,
1359        >::from_register(self, 0)
1360    }
1361
1362    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
1363    #[inline(always)]
1364    pub fn dcp(
1365        self,
1366    ) -> crate::common::RegisterField<
1367        12,
1368        0x3,
1369        1,
1370        0,
1371        scr10::Dcp,
1372        scr10::Dcp,
1373        Scr10_SPEC,
1374        crate::common::RW,
1375    > {
1376        crate::common::RegisterField::<
1377            12,
1378            0x3,
1379            1,
1380            0,
1381            scr10::Dcp,
1382            scr10::Dcp,
1383            Scr10_SPEC,
1384            crate::common::RW,
1385        >::from_register(self, 0)
1386    }
1387
1388    #[doc = "Setting of Channel 0 Operation Mode"]
1389    #[inline(always)]
1390    pub fn trxe(
1391        self,
1392    ) -> crate::common::RegisterField<
1393        14,
1394        0x3,
1395        1,
1396        0,
1397        scr10::Trxe,
1398        scr10::Trxe,
1399        Scr10_SPEC,
1400        crate::common::RW,
1401    > {
1402        crate::common::RegisterField::<
1403            14,
1404            0x3,
1405            1,
1406            0,
1407            scr10::Trxe,
1408            scr10::Trxe,
1409            Scr10_SPEC,
1410            crate::common::RW,
1411        >::from_register(self, 0)
1412    }
1413}
1414impl ::core::default::Default for Scr10 {
1415    #[inline(always)]
1416    fn default() -> Scr10 {
1417        <crate::RegValueT<Scr10_SPEC> as RegisterValue<_>>::new(135)
1418    }
1419}
1420pub mod scr10 {
1421
1422    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1423    pub struct Dls_SPEC;
1424    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
1425    impl Dls {
1426        #[doc = "Setting prohibited"]
1427        pub const _00: Self = Self::new(0);
1428
1429        #[doc = "9-bit data length (stored in bits 0 to 8 of the SDRm0 register) (settable in UART mode only)"]
1430        pub const _01: Self = Self::new(1);
1431
1432        #[doc = "7-bit data length (stored in bits 0 to 6 of the SDRm0 register)"]
1433        pub const _10: Self = Self::new(2);
1434
1435        #[doc = "8-bit data length (stored in bits 0 to 7 of the SDRm0 register)"]
1436        pub const _11: Self = Self::new(3);
1437    }
1438    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1439    pub struct Slc_SPEC;
1440    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
1441    impl Slc {
1442        #[doc = "No stop bit"]
1443        pub const _00: Self = Self::new(0);
1444
1445        #[doc = "Stop bit length = 1 bit"]
1446        pub const _01: Self = Self::new(1);
1447
1448        #[doc = "Stop bit length = 2 bits"]
1449        pub const _10: Self = Self::new(2);
1450
1451        #[doc = "Setting prohibited"]
1452        pub const _11: Self = Self::new(3);
1453    }
1454    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1455    pub struct Dir_SPEC;
1456    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
1457    impl Dir {
1458        #[doc = "Inputs or outputs data with MSB first"]
1459        pub const _0: Self = Self::new(0);
1460
1461        #[doc = "Inputs or outputs data with LSB first"]
1462        pub const _1: Self = Self::new(1);
1463    }
1464    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1465    pub struct Ptc_SPEC;
1466    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
1467    impl Ptc {
1468        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
1469        pub const _00: Self = Self::new(0);
1470
1471        #[doc = "Transmission: Outputs 0 parity Reception: No parity determination"]
1472        pub const _01: Self = Self::new(1);
1473
1474        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
1475        pub const _10: Self = Self::new(2);
1476
1477        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
1478        pub const _11: Self = Self::new(3);
1479    }
1480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1481    pub struct Dcp_SPEC;
1482    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
1483    impl Dcp {
1484        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
1485        pub const _00: Self = Self::new(0);
1486
1487        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
1488        pub const _01: Self = Self::new(1);
1489
1490        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
1491        pub const _10: Self = Self::new(2);
1492
1493        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
1494        pub const _11: Self = Self::new(3);
1495    }
1496    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1497    pub struct Trxe_SPEC;
1498    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
1499    impl Trxe {
1500        #[doc = "Disable communication"]
1501        pub const _00: Self = Self::new(0);
1502
1503        #[doc = "Reception only"]
1504        pub const _01: Self = Self::new(1);
1505
1506        #[doc = "Transmission only"]
1507        pub const _10: Self = Self::new(2);
1508
1509        #[doc = "Transmission and reception"]
1510        pub const _11: Self = Self::new(3);
1511    }
1512}
1513#[doc(hidden)]
1514#[derive(Copy, Clone, Eq, PartialEq)]
1515pub struct Scr11_SPEC;
1516impl crate::sealed::RegSpec for Scr11_SPEC {
1517    type DataType = u16;
1518}
1519
1520#[doc = "Serial Communication Operation Setting Register 11"]
1521pub type Scr11 = crate::RegValueT<Scr11_SPEC>;
1522
1523impl Scr11 {
1524    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
1525    #[inline(always)]
1526    pub fn dls(
1527        self,
1528    ) -> crate::common::RegisterField<
1529        0,
1530        0x3,
1531        1,
1532        0,
1533        scr11::Dls,
1534        scr11::Dls,
1535        Scr11_SPEC,
1536        crate::common::RW,
1537    > {
1538        crate::common::RegisterField::<
1539            0,
1540            0x3,
1541            1,
1542            0,
1543            scr11::Dls,
1544            scr11::Dls,
1545            Scr11_SPEC,
1546            crate::common::RW,
1547        >::from_register(self, 0)
1548    }
1549
1550    #[doc = "Setting of Stop Bit in UART Mode"]
1551    #[inline(always)]
1552    pub fn slc(
1553        self,
1554    ) -> crate::common::RegisterField<
1555        4,
1556        0x1,
1557        1,
1558        0,
1559        scr11::Slc,
1560        scr11::Slc,
1561        Scr11_SPEC,
1562        crate::common::RW,
1563    > {
1564        crate::common::RegisterField::<
1565            4,
1566            0x1,
1567            1,
1568            0,
1569            scr11::Slc,
1570            scr11::Slc,
1571            Scr11_SPEC,
1572            crate::common::RW,
1573        >::from_register(self, 0)
1574    }
1575
1576    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
1577    #[inline(always)]
1578    pub fn dir(
1579        self,
1580    ) -> crate::common::RegisterField<
1581        7,
1582        0x1,
1583        1,
1584        0,
1585        scr11::Dir,
1586        scr11::Dir,
1587        Scr11_SPEC,
1588        crate::common::RW,
1589    > {
1590        crate::common::RegisterField::<
1591            7,
1592            0x1,
1593            1,
1594            0,
1595            scr11::Dir,
1596            scr11::Dir,
1597            Scr11_SPEC,
1598            crate::common::RW,
1599        >::from_register(self, 0)
1600    }
1601
1602    #[doc = "Setting of Parity Bit in UART Mode"]
1603    #[inline(always)]
1604    pub fn ptc(
1605        self,
1606    ) -> crate::common::RegisterField<
1607        8,
1608        0x3,
1609        1,
1610        0,
1611        scr11::Ptc,
1612        scr11::Ptc,
1613        Scr11_SPEC,
1614        crate::common::RW,
1615    > {
1616        crate::common::RegisterField::<
1617            8,
1618            0x3,
1619            1,
1620            0,
1621            scr11::Ptc,
1622            scr11::Ptc,
1623            Scr11_SPEC,
1624            crate::common::RW,
1625        >::from_register(self, 0)
1626    }
1627
1628    #[doc = "Mask Control of Error Interrupt Signal SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1)"]
1629    #[inline(always)]
1630    pub fn eoc(
1631        self,
1632    ) -> crate::common::RegisterField<
1633        10,
1634        0x1,
1635        1,
1636        0,
1637        scr11::Eoc,
1638        scr11::Eoc,
1639        Scr11_SPEC,
1640        crate::common::RW,
1641    > {
1642        crate::common::RegisterField::<
1643            10,
1644            0x1,
1645            1,
1646            0,
1647            scr11::Eoc,
1648            scr11::Eoc,
1649            Scr11_SPEC,
1650            crate::common::RW,
1651        >::from_register(self, 0)
1652    }
1653
1654    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
1655    #[inline(always)]
1656    pub fn dcp(
1657        self,
1658    ) -> crate::common::RegisterField<
1659        12,
1660        0x3,
1661        1,
1662        0,
1663        scr11::Dcp,
1664        scr11::Dcp,
1665        Scr11_SPEC,
1666        crate::common::RW,
1667    > {
1668        crate::common::RegisterField::<
1669            12,
1670            0x3,
1671            1,
1672            0,
1673            scr11::Dcp,
1674            scr11::Dcp,
1675            Scr11_SPEC,
1676            crate::common::RW,
1677        >::from_register(self, 0)
1678    }
1679
1680    #[doc = "Setting of Channel 1 Operation Mode"]
1681    #[inline(always)]
1682    pub fn trxe(
1683        self,
1684    ) -> crate::common::RegisterField<
1685        14,
1686        0x3,
1687        1,
1688        0,
1689        scr11::Trxe,
1690        scr11::Trxe,
1691        Scr11_SPEC,
1692        crate::common::RW,
1693    > {
1694        crate::common::RegisterField::<
1695            14,
1696            0x3,
1697            1,
1698            0,
1699            scr11::Trxe,
1700            scr11::Trxe,
1701            Scr11_SPEC,
1702            crate::common::RW,
1703        >::from_register(self, 0)
1704    }
1705}
1706impl ::core::default::Default for Scr11 {
1707    #[inline(always)]
1708    fn default() -> Scr11 {
1709        <crate::RegValueT<Scr11_SPEC> as RegisterValue<_>>::new(135)
1710    }
1711}
1712pub mod scr11 {
1713
1714    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1715    pub struct Dls_SPEC;
1716    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
1717    impl Dls {
1718        #[doc = "Setting prohibited"]
1719        pub const _00: Self = Self::new(0);
1720
1721        #[doc = "9-bit data length (stored in the DAT\\[8:0\\] bits of the SDRm1 register) (settable in UART mode only)"]
1722        pub const _01: Self = Self::new(1);
1723
1724        #[doc = "7-bit data length (stored in the DAT\\[6:0\\] bits of the SDRm1 register)"]
1725        pub const _10: Self = Self::new(2);
1726
1727        #[doc = "8-bit data length (stored in the DAT\\[7:0\\] bits of the SDRm1 register)"]
1728        pub const _11: Self = Self::new(3);
1729    }
1730    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1731    pub struct Slc_SPEC;
1732    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
1733    impl Slc {
1734        #[doc = "No stop bit"]
1735        pub const _0: Self = Self::new(0);
1736
1737        #[doc = "Stop bit length = 1 bit"]
1738        pub const _1: Self = Self::new(1);
1739    }
1740    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1741    pub struct Dir_SPEC;
1742    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
1743    impl Dir {
1744        #[doc = "Inputs or outputs data with MSB first"]
1745        pub const _0: Self = Self::new(0);
1746
1747        #[doc = "Inputs or outputs data with LSB first"]
1748        pub const _1: Self = Self::new(1);
1749    }
1750    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1751    pub struct Ptc_SPEC;
1752    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
1753    impl Ptc {
1754        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
1755        pub const _00: Self = Self::new(0);
1756
1757        #[doc = "Transmission: Outputs 0 parity Reception: No parity judgment"]
1758        pub const _01: Self = Self::new(1);
1759
1760        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
1761        pub const _10: Self = Self::new(2);
1762
1763        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
1764        pub const _11: Self = Self::new(3);
1765    }
1766    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1767    pub struct Eoc_SPEC;
1768    pub type Eoc = crate::EnumBitfieldStruct<u8, Eoc_SPEC>;
1769    impl Eoc {
1770        #[doc = "Disables generation of error interrupt SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) (SAUm_UART_RXIq is generated)"]
1771        pub const _0: Self = Self::new(0);
1772
1773        #[doc = "Enables generation of error interrupt SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) (SAUm_UART_RXIq is not generated if an error occurs)"]
1774        pub const _1: Self = Self::new(1);
1775    }
1776    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1777    pub struct Dcp_SPEC;
1778    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
1779    impl Dcp {
1780        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
1781        pub const _00: Self = Self::new(0);
1782
1783        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
1784        pub const _01: Self = Self::new(1);
1785
1786        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
1787        pub const _10: Self = Self::new(2);
1788
1789        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
1790        pub const _11: Self = Self::new(3);
1791    }
1792    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1793    pub struct Trxe_SPEC;
1794    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
1795    impl Trxe {
1796        #[doc = "Disable communication"]
1797        pub const _00: Self = Self::new(0);
1798
1799        #[doc = "Reception only"]
1800        pub const _01: Self = Self::new(1);
1801
1802        #[doc = "Transmission only"]
1803        pub const _10: Self = Self::new(2);
1804
1805        #[doc = "Transmission and reception"]
1806        pub const _11: Self = Self::new(3);
1807    }
1808}
1809#[doc(hidden)]
1810#[derive(Copy, Clone, Eq, PartialEq)]
1811pub struct Se1_SPEC;
1812impl crate::sealed::RegSpec for Se1_SPEC {
1813    type DataType = u16;
1814}
1815
1816#[doc = "Serial Channel Enable Status Register 1"]
1817pub type Se1 = crate::RegValueT<Se1_SPEC>;
1818
1819impl Se1 {
1820    #[doc = "Indication of whether Operation of Channel n is Enabled or Stopped."]
1821    #[inline(always)]
1822    pub fn se(
1823        self,
1824    ) -> crate::common::RegisterField<0, 0x3, 1, 0, se1::Se, se1::Se, Se1_SPEC, crate::common::R>
1825    {
1826        crate::common::RegisterField::<0,0x3,1,0,se1::Se,se1::Se,Se1_SPEC,crate::common::R>::from_register(self,0)
1827    }
1828}
1829impl ::core::default::Default for Se1 {
1830    #[inline(always)]
1831    fn default() -> Se1 {
1832        <crate::RegValueT<Se1_SPEC> as RegisterValue<_>>::new(0)
1833    }
1834}
1835pub mod se1 {
1836
1837    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1838    pub struct Se_SPEC;
1839    pub type Se = crate::EnumBitfieldStruct<u8, Se_SPEC>;
1840    impl Se {
1841        #[doc = "Operation stops"]
1842        pub const _0: Self = Self::new(0);
1843
1844        #[doc = "Operation is enabled"]
1845        pub const _1: Self = Self::new(1);
1846    }
1847}
1848#[doc(hidden)]
1849#[derive(Copy, Clone, Eq, PartialEq)]
1850pub struct Ss1_SPEC;
1851impl crate::sealed::RegSpec for Ss1_SPEC {
1852    type DataType = u16;
1853}
1854
1855#[doc = "Serial Channel Start Register 1"]
1856pub type Ss1 = crate::RegValueT<Ss1_SPEC>;
1857
1858impl Ss1 {
1859    #[doc = "Operation Start Trigger of Channel n"]
1860    #[inline(always)]
1861    pub fn ss(
1862        self,
1863    ) -> crate::common::RegisterField<0, 0x3, 1, 0, ss1::Ss, ss1::Ss, Ss1_SPEC, crate::common::RW>
1864    {
1865        crate::common::RegisterField::<0,0x3,1,0,ss1::Ss,ss1::Ss,Ss1_SPEC,crate::common::RW>::from_register(self,0)
1866    }
1867}
1868impl ::core::default::Default for Ss1 {
1869    #[inline(always)]
1870    fn default() -> Ss1 {
1871        <crate::RegValueT<Ss1_SPEC> as RegisterValue<_>>::new(0)
1872    }
1873}
1874pub mod ss1 {
1875
1876    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1877    pub struct Ss_SPEC;
1878    pub type Ss = crate::EnumBitfieldStruct<u8, Ss_SPEC>;
1879    impl Ss {
1880        #[doc = "No trigger operation"]
1881        pub const _0: Self = Self::new(0);
1882
1883        #[doc = "Set the SE1.SE\\[n\\] bit to 1 to place the channel in communications waiting state"]
1884        pub const _1: Self = Self::new(1);
1885    }
1886}
1887#[doc(hidden)]
1888#[derive(Copy, Clone, Eq, PartialEq)]
1889pub struct St1_SPEC;
1890impl crate::sealed::RegSpec for St1_SPEC {
1891    type DataType = u16;
1892}
1893
1894#[doc = "Serial Channel Stop Register 1"]
1895pub type St1 = crate::RegValueT<St1_SPEC>;
1896
1897impl St1 {
1898    #[doc = "Operation Stop Trigger of Channel n"]
1899    #[inline(always)]
1900    pub fn st(
1901        self,
1902    ) -> crate::common::RegisterField<0, 0x3, 1, 0, st1::St, st1::St, St1_SPEC, crate::common::RW>
1903    {
1904        crate::common::RegisterField::<0,0x3,1,0,st1::St,st1::St,St1_SPEC,crate::common::RW>::from_register(self,0)
1905    }
1906}
1907impl ::core::default::Default for St1 {
1908    #[inline(always)]
1909    fn default() -> St1 {
1910        <crate::RegValueT<St1_SPEC> as RegisterValue<_>>::new(0)
1911    }
1912}
1913pub mod st1 {
1914
1915    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1916    pub struct St_SPEC;
1917    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
1918    impl St {
1919        #[doc = "No trigger operation"]
1920        pub const _0: Self = Self::new(0);
1921
1922        #[doc = "Clears the SE1.SE\\[n\\] bit to 0 and stops the communication operation"]
1923        pub const _1: Self = Self::new(1);
1924    }
1925}
1926#[doc(hidden)]
1927#[derive(Copy, Clone, Eq, PartialEq)]
1928pub struct Sps1_SPEC;
1929impl crate::sealed::RegSpec for Sps1_SPEC {
1930    type DataType = u16;
1931}
1932
1933#[doc = "Serial Clock Select Register 1"]
1934pub type Sps1 = crate::RegValueT<Sps1_SPEC>;
1935
1936impl Sps1 {
1937    #[doc = "Selection of Operation Clock (CKm0)"]
1938    #[inline(always)]
1939    pub fn prs0(
1940        self,
1941    ) -> crate::common::RegisterField<
1942        0,
1943        0xf,
1944        1,
1945        0,
1946        sps1::Prs0,
1947        sps1::Prs0,
1948        Sps1_SPEC,
1949        crate::common::RW,
1950    > {
1951        crate::common::RegisterField::<
1952            0,
1953            0xf,
1954            1,
1955            0,
1956            sps1::Prs0,
1957            sps1::Prs0,
1958            Sps1_SPEC,
1959            crate::common::RW,
1960        >::from_register(self, 0)
1961    }
1962
1963    #[doc = "Selection of Operation Clock (CKm1)"]
1964    #[inline(always)]
1965    pub fn prs1(
1966        self,
1967    ) -> crate::common::RegisterField<
1968        4,
1969        0xf,
1970        1,
1971        0,
1972        sps1::Prs1,
1973        sps1::Prs1,
1974        Sps1_SPEC,
1975        crate::common::RW,
1976    > {
1977        crate::common::RegisterField::<
1978            4,
1979            0xf,
1980            1,
1981            0,
1982            sps1::Prs1,
1983            sps1::Prs1,
1984            Sps1_SPEC,
1985            crate::common::RW,
1986        >::from_register(self, 0)
1987    }
1988}
1989impl ::core::default::Default for Sps1 {
1990    #[inline(always)]
1991    fn default() -> Sps1 {
1992        <crate::RegValueT<Sps1_SPEC> as RegisterValue<_>>::new(0)
1993    }
1994}
1995pub mod sps1 {
1996
1997    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1998    pub struct Prs0_SPEC;
1999    pub type Prs0 = crate::EnumBitfieldStruct<u8, Prs0_SPEC>;
2000    impl Prs0 {
2001        #[doc = "PCLKB"]
2002        pub const _0_X_0: Self = Self::new(0);
2003
2004        #[doc = "PCLKB/2"]
2005        pub const _0_X_1: Self = Self::new(1);
2006
2007        #[doc = "PCLKB/22"]
2008        pub const _0_X_2: Self = Self::new(2);
2009
2010        #[doc = "PCLKB/23"]
2011        pub const _0_X_3: Self = Self::new(3);
2012
2013        #[doc = "PCLKB/24"]
2014        pub const _0_X_4: Self = Self::new(4);
2015
2016        #[doc = "PCLKB/25"]
2017        pub const _0_X_5: Self = Self::new(5);
2018
2019        #[doc = "PCLKB/26"]
2020        pub const _0_X_6: Self = Self::new(6);
2021
2022        #[doc = "PCLKB/27"]
2023        pub const _0_X_7: Self = Self::new(7);
2024
2025        #[doc = "PCLKB/28"]
2026        pub const _0_X_8: Self = Self::new(8);
2027
2028        #[doc = "PCLKB/29"]
2029        pub const _0_X_9: Self = Self::new(9);
2030
2031        #[doc = "PCLKB/210"]
2032        pub const _0_X_A: Self = Self::new(10);
2033
2034        #[doc = "PCLKB/211"]
2035        pub const _0_X_B: Self = Self::new(11);
2036
2037        #[doc = "PCLKB/212"]
2038        pub const _0_X_C: Self = Self::new(12);
2039
2040        #[doc = "PCLKB/213"]
2041        pub const _0_X_D: Self = Self::new(13);
2042
2043        #[doc = "PCLKB/214"]
2044        pub const _0_X_E: Self = Self::new(14);
2045
2046        #[doc = "PCLKB/215"]
2047        pub const _0_X_F: Self = Self::new(15);
2048    }
2049    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2050    pub struct Prs1_SPEC;
2051    pub type Prs1 = crate::EnumBitfieldStruct<u8, Prs1_SPEC>;
2052    impl Prs1 {
2053        #[doc = "PCLKB"]
2054        pub const _0_X_0: Self = Self::new(0);
2055
2056        #[doc = "PCLKB/2"]
2057        pub const _0_X_1: Self = Self::new(1);
2058
2059        #[doc = "PCLKB/22"]
2060        pub const _0_X_2: Self = Self::new(2);
2061
2062        #[doc = "PCLKB/23"]
2063        pub const _0_X_3: Self = Self::new(3);
2064
2065        #[doc = "PCLKB/24"]
2066        pub const _0_X_4: Self = Self::new(4);
2067
2068        #[doc = "PCLKB/25"]
2069        pub const _0_X_5: Self = Self::new(5);
2070
2071        #[doc = "PCLKB/26"]
2072        pub const _0_X_6: Self = Self::new(6);
2073
2074        #[doc = "PCLKB/27"]
2075        pub const _0_X_7: Self = Self::new(7);
2076
2077        #[doc = "PCLKB/28"]
2078        pub const _0_X_8: Self = Self::new(8);
2079
2080        #[doc = "PCLKB/29"]
2081        pub const _0_X_9: Self = Self::new(9);
2082
2083        #[doc = "PCLKB/210"]
2084        pub const _0_X_A: Self = Self::new(10);
2085
2086        #[doc = "PCLKB/211"]
2087        pub const _0_X_B: Self = Self::new(11);
2088
2089        #[doc = "PCLKB/212"]
2090        pub const _0_X_C: Self = Self::new(12);
2091
2092        #[doc = "PCLKB/213"]
2093        pub const _0_X_D: Self = Self::new(13);
2094
2095        #[doc = "PCLKB/214"]
2096        pub const _0_X_E: Self = Self::new(14);
2097
2098        #[doc = "PCLKB/215"]
2099        pub const _0_X_F: Self = Self::new(15);
2100    }
2101}
2102#[doc(hidden)]
2103#[derive(Copy, Clone, Eq, PartialEq)]
2104pub struct So1_SPEC;
2105impl crate::sealed::RegSpec for So1_SPEC {
2106    type DataType = u16;
2107}
2108
2109#[doc = "Serial Output Register 1"]
2110pub type So1 = crate::RegValueT<So1_SPEC>;
2111
2112impl So1 {
2113    #[doc = "Serial Data Output of Channel n"]
2114    #[inline(always)]
2115    pub fn so(
2116        self,
2117    ) -> crate::common::RegisterField<0, 0x3, 1, 0, so1::So, so1::So, So1_SPEC, crate::common::RW>
2118    {
2119        crate::common::RegisterField::<0,0x3,1,0,so1::So,so1::So,So1_SPEC,crate::common::RW>::from_register(self,0)
2120    }
2121
2122    #[doc = "Serial Clock Output of Channel n"]
2123    #[inline(always)]
2124    pub fn cko(
2125        self,
2126    ) -> crate::common::RegisterField<8, 0x3, 1, 0, so1::Cko, so1::Cko, So1_SPEC, crate::common::RW>
2127    {
2128        crate::common::RegisterField::<8,0x3,1,0,so1::Cko,so1::Cko,So1_SPEC,crate::common::RW>::from_register(self,0)
2129    }
2130}
2131impl ::core::default::Default for So1 {
2132    #[inline(always)]
2133    fn default() -> So1 {
2134        <crate::RegValueT<So1_SPEC> as RegisterValue<_>>::new(771)
2135    }
2136}
2137pub mod so1 {
2138
2139    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2140    pub struct So_SPEC;
2141    pub type So = crate::EnumBitfieldStruct<u8, So_SPEC>;
2142    impl So {
2143        #[doc = "Serial data output value is 0"]
2144        pub const _0: Self = Self::new(0);
2145
2146        #[doc = "Serial data output value is 1"]
2147        pub const _1: Self = Self::new(1);
2148    }
2149    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2150    pub struct Cko_SPEC;
2151    pub type Cko = crate::EnumBitfieldStruct<u8, Cko_SPEC>;
2152    impl Cko {
2153        #[doc = "Serial clock output value is 0"]
2154        pub const _0: Self = Self::new(0);
2155
2156        #[doc = "Serial clock output value is 1"]
2157        pub const _1: Self = Self::new(1);
2158    }
2159}
2160#[doc(hidden)]
2161#[derive(Copy, Clone, Eq, PartialEq)]
2162pub struct Soe1_SPEC;
2163impl crate::sealed::RegSpec for Soe1_SPEC {
2164    type DataType = u16;
2165}
2166
2167#[doc = "Serial Output Enable Register 1"]
2168pub type Soe1 = crate::RegValueT<Soe1_SPEC>;
2169
2170impl Soe1 {
2171    #[doc = "Serial Output Enable or Stop of Channel n"]
2172    #[inline(always)]
2173    pub fn soe(
2174        self,
2175    ) -> crate::common::RegisterField<
2176        0,
2177        0x3,
2178        1,
2179        0,
2180        soe1::Soe,
2181        soe1::Soe,
2182        Soe1_SPEC,
2183        crate::common::RW,
2184    > {
2185        crate::common::RegisterField::<
2186            0,
2187            0x3,
2188            1,
2189            0,
2190            soe1::Soe,
2191            soe1::Soe,
2192            Soe1_SPEC,
2193            crate::common::RW,
2194        >::from_register(self, 0)
2195    }
2196}
2197impl ::core::default::Default for Soe1 {
2198    #[inline(always)]
2199    fn default() -> Soe1 {
2200        <crate::RegValueT<Soe1_SPEC> as RegisterValue<_>>::new(0)
2201    }
2202}
2203pub mod soe1 {
2204
2205    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2206    pub struct Soe_SPEC;
2207    pub type Soe = crate::EnumBitfieldStruct<u8, Soe_SPEC>;
2208    impl Soe {
2209        #[doc = "Stops output by serial communication operation"]
2210        pub const _0: Self = Self::new(0);
2211
2212        #[doc = "Enables output by serial communication operation"]
2213        pub const _1: Self = Self::new(1);
2214    }
2215}
2216#[doc(hidden)]
2217#[derive(Copy, Clone, Eq, PartialEq)]
2218pub struct Sol1_SPEC;
2219impl crate::sealed::RegSpec for Sol1_SPEC {
2220    type DataType = u16;
2221}
2222
2223#[doc = "Serial Output Level Register 1"]
2224pub type Sol1 = crate::RegValueT<Sol1_SPEC>;
2225
2226impl Sol1 {
2227    #[doc = "Selects Inversion of the Level of the Transmit Data of Channel 0 in UART Mode"]
2228    #[inline(always)]
2229    pub fn sol0(
2230        self,
2231    ) -> crate::common::RegisterField<
2232        0,
2233        0x1,
2234        1,
2235        0,
2236        sol1::Sol0,
2237        sol1::Sol0,
2238        Sol1_SPEC,
2239        crate::common::RW,
2240    > {
2241        crate::common::RegisterField::<
2242            0,
2243            0x1,
2244            1,
2245            0,
2246            sol1::Sol0,
2247            sol1::Sol0,
2248            Sol1_SPEC,
2249            crate::common::RW,
2250        >::from_register(self, 0)
2251    }
2252}
2253impl ::core::default::Default for Sol1 {
2254    #[inline(always)]
2255    fn default() -> Sol1 {
2256        <crate::RegValueT<Sol1_SPEC> as RegisterValue<_>>::new(0)
2257    }
2258}
2259pub mod sol1 {
2260
2261    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2262    pub struct Sol0_SPEC;
2263    pub type Sol0 = crate::EnumBitfieldStruct<u8, Sol0_SPEC>;
2264    impl Sol0 {
2265        #[doc = "Communication data is output as is"]
2266        pub const _0: Self = Self::new(0);
2267
2268        #[doc = "Communication data is inverted and output"]
2269        pub const _1: Self = Self::new(1);
2270    }
2271}
ra0e1_pac/sau1.rs

ra0e1_pac/
sau1.rs
