ra0e1_pac/
dbg.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Debug Function"]
28unsafe impl ::core::marker::Send for super::Dbg {}
29unsafe impl ::core::marker::Sync for super::Dbg {}
30impl super::Dbg {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Debug Status Register"]
38    #[inline(always)]
39    pub const fn dbgstr(&self) -> &'static crate::common::Reg<self::Dbgstr_SPEC, crate::common::R> {
40        unsafe {
41            crate::common::Reg::<self::Dbgstr_SPEC, crate::common::R>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Debug Stop Control Register"]
48    #[inline(always)]
49    pub const fn dbgstopcr(
50        &self,
51    ) -> &'static crate::common::Reg<self::Dbgstopcr_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Dbgstopcr_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(16usize),
55            )
56        }
57    }
58}
59#[doc(hidden)]
60#[derive(Copy, Clone, Eq, PartialEq)]
61pub struct Dbgstr_SPEC;
62impl crate::sealed::RegSpec for Dbgstr_SPEC {
63    type DataType = u32;
64}
65
66#[doc = "Debug Status Register"]
67pub type Dbgstr = crate::RegValueT<Dbgstr_SPEC>;
68
69impl Dbgstr {
70    #[doc = "Debug Power-up Request"]
71    #[inline(always)]
72    pub fn cdbgpwrupreq(
73        self,
74    ) -> crate::common::RegisterField<
75        28,
76        0x1,
77        1,
78        0,
79        dbgstr::Cdbgpwrupreq,
80        dbgstr::Cdbgpwrupreq,
81        Dbgstr_SPEC,
82        crate::common::R,
83    > {
84        crate::common::RegisterField::<
85            28,
86            0x1,
87            1,
88            0,
89            dbgstr::Cdbgpwrupreq,
90            dbgstr::Cdbgpwrupreq,
91            Dbgstr_SPEC,
92            crate::common::R,
93        >::from_register(self, 0)
94    }
95
96    #[doc = "Debug Power-up Acknowledge"]
97    #[inline(always)]
98    pub fn cdbgpwrupack(
99        self,
100    ) -> crate::common::RegisterField<
101        29,
102        0x1,
103        1,
104        0,
105        dbgstr::Cdbgpwrupack,
106        dbgstr::Cdbgpwrupack,
107        Dbgstr_SPEC,
108        crate::common::R,
109    > {
110        crate::common::RegisterField::<
111            29,
112            0x1,
113            1,
114            0,
115            dbgstr::Cdbgpwrupack,
116            dbgstr::Cdbgpwrupack,
117            Dbgstr_SPEC,
118            crate::common::R,
119        >::from_register(self, 0)
120    }
121}
122impl ::core::default::Default for Dbgstr {
123    #[inline(always)]
124    fn default() -> Dbgstr {
125        <crate::RegValueT<Dbgstr_SPEC> as RegisterValue<_>>::new(0)
126    }
127}
128pub mod dbgstr {
129
130    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
131    pub struct Cdbgpwrupreq_SPEC;
132    pub type Cdbgpwrupreq = crate::EnumBitfieldStruct<u8, Cdbgpwrupreq_SPEC>;
133    impl Cdbgpwrupreq {
134        #[doc = "OCD emulator is not requesting debug power up"]
135        pub const _0: Self = Self::new(0);
136
137        #[doc = "OCD emulator is requesting debug power up"]
138        pub const _1: Self = Self::new(1);
139    }
140    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
141    pub struct Cdbgpwrupack_SPEC;
142    pub type Cdbgpwrupack = crate::EnumBitfieldStruct<u8, Cdbgpwrupack_SPEC>;
143    impl Cdbgpwrupack {
144        #[doc = "Debug power-up request is not acknowledged"]
145        pub const _0: Self = Self::new(0);
146
147        #[doc = "Debug power-up request is acknowledged"]
148        pub const _1: Self = Self::new(1);
149    }
150}
151#[doc(hidden)]
152#[derive(Copy, Clone, Eq, PartialEq)]
153pub struct Dbgstopcr_SPEC;
154impl crate::sealed::RegSpec for Dbgstopcr_SPEC {
155    type DataType = u32;
156}
157
158#[doc = "Debug Stop Control Register"]
159pub type Dbgstopcr = crate::RegValueT<Dbgstopcr_SPEC>;
160
161impl Dbgstopcr {
162    #[doc = "Mask Bit for IWDT Reset/Interrupt in the OCD Run Mode"]
163    #[inline(always)]
164    pub fn dbgstop_iwdt(
165        self,
166    ) -> crate::common::RegisterField<
167        0,
168        0x1,
169        1,
170        0,
171        dbgstopcr::DbgstopIwdt,
172        dbgstopcr::DbgstopIwdt,
173        Dbgstopcr_SPEC,
174        crate::common::RW,
175    > {
176        crate::common::RegisterField::<
177            0,
178            0x1,
179            1,
180            0,
181            dbgstopcr::DbgstopIwdt,
182            dbgstopcr::DbgstopIwdt,
183            Dbgstopcr_SPEC,
184            crate::common::RW,
185        >::from_register(self, 0)
186    }
187
188    #[inline(always)]
189    pub fn dbgstop_tim(
190        self,
191    ) -> crate::common::RegisterField<
192        14,
193        0x1,
194        1,
195        0,
196        dbgstopcr::DbgstopTim,
197        dbgstopcr::DbgstopTim,
198        Dbgstopcr_SPEC,
199        crate::common::RW,
200    > {
201        crate::common::RegisterField::<
202            14,
203            0x1,
204            1,
205            0,
206            dbgstopcr::DbgstopTim,
207            dbgstopcr::DbgstopTim,
208            Dbgstopcr_SPEC,
209            crate::common::RW,
210        >::from_register(self, 0)
211    }
212
213    #[doc = "Mask Bit for SAU, IICA, UARTA, PORT_IRQ0-5 Reset/Interrupt in the OCD brake mode. In the OCD break mode, the reset/interrupt is masked and each operation is stopped."]
214    #[inline(always)]
215    pub fn dbgstop_sir(
216        self,
217    ) -> crate::common::RegisterField<
218        15,
219        0x1,
220        1,
221        0,
222        dbgstopcr::DbgstopSir,
223        dbgstopcr::DbgstopSir,
224        Dbgstopcr_SPEC,
225        crate::common::RW,
226    > {
227        crate::common::RegisterField::<
228            15,
229            0x1,
230            1,
231            0,
232            dbgstopcr::DbgstopSir,
233            dbgstopcr::DbgstopSir,
234            Dbgstopcr_SPEC,
235            crate::common::RW,
236        >::from_register(self, 0)
237    }
238
239    #[doc = "Mask Bit for LVD0 Reset"]
240    #[inline(always)]
241    pub fn dbgstop_lvd0(
242        self,
243    ) -> crate::common::RegisterField<
244        16,
245        0x1,
246        1,
247        0,
248        dbgstopcr::DbgstopLvd0,
249        dbgstopcr::DbgstopLvd0,
250        Dbgstopcr_SPEC,
251        crate::common::RW,
252    > {
253        crate::common::RegisterField::<
254            16,
255            0x1,
256            1,
257            0,
258            dbgstopcr::DbgstopLvd0,
259            dbgstopcr::DbgstopLvd0,
260            Dbgstopcr_SPEC,
261            crate::common::RW,
262        >::from_register(self, 0)
263    }
264
265    #[doc = "Mask Bit for LVD1 Reset/Interrupt"]
266    #[inline(always)]
267    pub fn dbgstop_lvd1(
268        self,
269    ) -> crate::common::RegisterField<
270        17,
271        0x1,
272        1,
273        0,
274        dbgstopcr::DbgstopLvd1,
275        dbgstopcr::DbgstopLvd1,
276        Dbgstopcr_SPEC,
277        crate::common::RW,
278    > {
279        crate::common::RegisterField::<
280            17,
281            0x1,
282            1,
283            0,
284            dbgstopcr::DbgstopLvd1,
285            dbgstopcr::DbgstopLvd1,
286            Dbgstopcr_SPEC,
287            crate::common::RW,
288        >::from_register(self, 0)
289    }
290
291    #[doc = "Mask Bit for SRAM Parity Error Reset/Interrupt"]
292    #[inline(always)]
293    pub fn dbgstop_rper(
294        self,
295    ) -> crate::common::RegisterField<
296        24,
297        0x1,
298        1,
299        0,
300        dbgstopcr::DbgstopRper,
301        dbgstopcr::DbgstopRper,
302        Dbgstopcr_SPEC,
303        crate::common::RW,
304    > {
305        crate::common::RegisterField::<
306            24,
307            0x1,
308            1,
309            0,
310            dbgstopcr::DbgstopRper,
311            dbgstopcr::DbgstopRper,
312            Dbgstopcr_SPEC,
313            crate::common::RW,
314        >::from_register(self, 0)
315    }
316}
317impl ::core::default::Default for Dbgstopcr {
318    #[inline(always)]
319    fn default() -> Dbgstopcr {
320        <crate::RegValueT<Dbgstopcr_SPEC> as RegisterValue<_>>::new(3)
321    }
322}
323pub mod dbgstopcr {
324
325    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
326    pub struct DbgstopIwdt_SPEC;
327    pub type DbgstopIwdt = crate::EnumBitfieldStruct<u8, DbgstopIwdt_SPEC>;
328    impl DbgstopIwdt {
329        #[doc = "Enable IWDT reset/interrupt"]
330        pub const _0: Self = Self::new(0);
331
332        #[doc = "Mask IWDT reset/interrupt and stop IWDT counter"]
333        pub const _1: Self = Self::new(1);
334    }
335    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
336    pub struct DbgstopTim_SPEC;
337    pub type DbgstopTim = crate::EnumBitfieldStruct<u8, DbgstopTim_SPEC>;
338    impl DbgstopTim {
339        #[doc = "Enable RTC, TAU, TML32 reset/interrupt"]
340        pub const _0: Self = Self::new(0);
341
342        #[doc = "Mask RTC, TAU, TML32 reset/interrupt"]
343        pub const _1: Self = Self::new(1);
344    }
345    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
346    pub struct DbgstopSir_SPEC;
347    pub type DbgstopSir = crate::EnumBitfieldStruct<u8, DbgstopSir_SPEC>;
348    impl DbgstopSir {
349        #[doc = "Enable SAU, IICA, UARTA, PORT_IRQ0 to 5 reset/interrupt"]
350        pub const _0: Self = Self::new(0);
351
352        #[doc = "Mask SAU, IICA, UARTA, PORT_IRQ0 to 5 reset/interrupt"]
353        pub const _1: Self = Self::new(1);
354    }
355    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
356    pub struct DbgstopLvd0_SPEC;
357    pub type DbgstopLvd0 = crate::EnumBitfieldStruct<u8, DbgstopLvd0_SPEC>;
358    impl DbgstopLvd0 {
359        #[doc = "Enable LVD0 reset"]
360        pub const _0: Self = Self::new(0);
361
362        #[doc = "Mask LVD0 reset"]
363        pub const _1: Self = Self::new(1);
364    }
365    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
366    pub struct DbgstopLvd1_SPEC;
367    pub type DbgstopLvd1 = crate::EnumBitfieldStruct<u8, DbgstopLvd1_SPEC>;
368    impl DbgstopLvd1 {
369        #[doc = "Enable LVD1 reset/interrupt"]
370        pub const _0: Self = Self::new(0);
371
372        #[doc = "Mask LVD1 reset/interrupt"]
373        pub const _1: Self = Self::new(1);
374    }
375    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
376    pub struct DbgstopRper_SPEC;
377    pub type DbgstopRper = crate::EnumBitfieldStruct<u8, DbgstopRper_SPEC>;
378    impl DbgstopRper {
379        #[doc = "Enable SRAM parity error reset/interrupt"]
380        pub const _0: Self = Self::new(0);
381
382        #[doc = "Mask SRAM parity error reset/interrupt"]
383        pub const _1: Self = Self::new(1);
384    }
385}
ra0e1_pac/dbg.rs

ra0e1_pac/
dbg.rs
