ra0e1_pac/
adc_d.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"A/D Converter"]
28unsafe impl ::core::marker::Send for super::AdcD {}
29unsafe impl ::core::marker::Sync for super::AdcD {}
30impl super::AdcD {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "A/D Converter Mode Register 0"]
38    #[inline(always)]
39    pub const fn adm0(&self) -> &'static crate::common::Reg<self::Adm0_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Adm0_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Analog Input Channel Specification Register"]
48    #[inline(always)]
49    pub const fn ads(&self) -> &'static crate::common::Reg<self::Ads_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Ads_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "A/D Converter Mode Register 1"]
58    #[inline(always)]
59    pub const fn adm1(&self) -> &'static crate::common::Reg<self::Adm1_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Adm1_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(2usize),
63            )
64        }
65    }
66
67    #[doc = "12-bit or 10-bit A/D Conversion Result Register"]
68    #[inline(always)]
69    pub const fn adcr(&self) -> &'static crate::common::Reg<self::Adcr_SPEC, crate::common::R> {
70        unsafe {
71            crate::common::Reg::<self::Adcr_SPEC, crate::common::R>::from_ptr(
72                self._svd2pac_as_ptr().add(6usize),
73            )
74        }
75    }
76
77    #[doc = "8-bit A/D Conversion Result Register"]
78    #[inline(always)]
79    pub const fn adcrh(&self) -> &'static crate::common::Reg<self::Adcrh_SPEC, crate::common::R> {
80        unsafe {
81            crate::common::Reg::<self::Adcrh_SPEC, crate::common::R>::from_ptr(
82                self._svd2pac_as_ptr().add(7usize),
83            )
84        }
85    }
86
87    #[doc = "A/D Converter Mode Register 2"]
88    #[inline(always)]
89    pub const fn adm2(&self) -> &'static crate::common::Reg<self::Adm2_SPEC, crate::common::RW> {
90        unsafe {
91            crate::common::Reg::<self::Adm2_SPEC, crate::common::RW>::from_ptr(
92                self._svd2pac_as_ptr().add(272usize),
93            )
94        }
95    }
96
97    #[doc = "Conversion Result Comparison Upper Limit Setting Register"]
98    #[inline(always)]
99    pub const fn adul(&self) -> &'static crate::common::Reg<self::Adul_SPEC, crate::common::RW> {
100        unsafe {
101            crate::common::Reg::<self::Adul_SPEC, crate::common::RW>::from_ptr(
102                self._svd2pac_as_ptr().add(273usize),
103            )
104        }
105    }
106
107    #[doc = "Conversion Result Comparison Lower Limit Setting Register"]
108    #[inline(always)]
109    pub const fn adll(&self) -> &'static crate::common::Reg<self::Adll_SPEC, crate::common::RW> {
110        unsafe {
111            crate::common::Reg::<self::Adll_SPEC, crate::common::RW>::from_ptr(
112                self._svd2pac_as_ptr().add(274usize),
113            )
114        }
115    }
116
117    #[doc = "A/D Test Register"]
118    #[inline(always)]
119    pub const fn adtes(&self) -> &'static crate::common::Reg<self::Adtes_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Adtes_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(275usize),
123            )
124        }
125    }
126
127    #[doc = "12-bit or 10-bit A/D Conversion Result Register 0"]
128    #[inline(always)]
129    pub const fn adcr0(&self) -> &'static crate::common::Reg<self::Adcr0_SPEC, crate::common::R> {
130        unsafe {
131            crate::common::Reg::<self::Adcr0_SPEC, crate::common::R>::from_ptr(
132                self._svd2pac_as_ptr().add(288usize),
133            )
134        }
135    }
136
137    #[doc = "8-bit A/D Conversion Result Register 0"]
138    #[inline(always)]
139    pub const fn adcr0h(&self) -> &'static crate::common::Reg<self::Adcr0H_SPEC, crate::common::R> {
140        unsafe {
141            crate::common::Reg::<self::Adcr0H_SPEC, crate::common::R>::from_ptr(
142                self._svd2pac_as_ptr().add(289usize),
143            )
144        }
145    }
146
147    #[doc = "12-bit or 10-bit A/D Conversion Result Register 1"]
148    #[inline(always)]
149    pub const fn adcr1(&self) -> &'static crate::common::Reg<self::Adcr1_SPEC, crate::common::R> {
150        unsafe {
151            crate::common::Reg::<self::Adcr1_SPEC, crate::common::R>::from_ptr(
152                self._svd2pac_as_ptr().add(290usize),
153            )
154        }
155    }
156
157    #[doc = "8-bit A/D Conversion Result Register 1"]
158    #[inline(always)]
159    pub const fn adcr1h(&self) -> &'static crate::common::Reg<self::Adcr1H_SPEC, crate::common::R> {
160        unsafe {
161            crate::common::Reg::<self::Adcr1H_SPEC, crate::common::R>::from_ptr(
162                self._svd2pac_as_ptr().add(291usize),
163            )
164        }
165    }
166
167    #[doc = "12-bit or 10-bit A/D Conversion Result Register 2"]
168    #[inline(always)]
169    pub const fn adcr2(&self) -> &'static crate::common::Reg<self::Adcr2_SPEC, crate::common::R> {
170        unsafe {
171            crate::common::Reg::<self::Adcr2_SPEC, crate::common::R>::from_ptr(
172                self._svd2pac_as_ptr().add(292usize),
173            )
174        }
175    }
176
177    #[doc = "8-bit A/D Conversion Result Register 2"]
178    #[inline(always)]
179    pub const fn adcr2h(&self) -> &'static crate::common::Reg<self::Adcr2H_SPEC, crate::common::R> {
180        unsafe {
181            crate::common::Reg::<self::Adcr2H_SPEC, crate::common::R>::from_ptr(
182                self._svd2pac_as_ptr().add(293usize),
183            )
184        }
185    }
186
187    #[doc = "12-bit or 10-bit A/D Conversion Result Register 3"]
188    #[inline(always)]
189    pub const fn adcr3(&self) -> &'static crate::common::Reg<self::Adcr3_SPEC, crate::common::R> {
190        unsafe {
191            crate::common::Reg::<self::Adcr3_SPEC, crate::common::R>::from_ptr(
192                self._svd2pac_as_ptr().add(294usize),
193            )
194        }
195    }
196
197    #[doc = "8-bit A/D Conversion Result Register 3"]
198    #[inline(always)]
199    pub const fn adcr3h(&self) -> &'static crate::common::Reg<self::Adcr3H_SPEC, crate::common::R> {
200        unsafe {
201            crate::common::Reg::<self::Adcr3H_SPEC, crate::common::R>::from_ptr(
202                self._svd2pac_as_ptr().add(295usize),
203            )
204        }
205    }
206}
207#[doc(hidden)]
208#[derive(Copy, Clone, Eq, PartialEq)]
209pub struct Adm0_SPEC;
210impl crate::sealed::RegSpec for Adm0_SPEC {
211    type DataType = u8;
212}
213
214#[doc = "A/D Converter Mode Register 0"]
215pub type Adm0 = crate::RegValueT<Adm0_SPEC>;
216
217impl Adm0 {
218    #[doc = "A/D voltage comparator operation control"]
219    #[inline(always)]
220    pub fn adce(
221        self,
222    ) -> crate::common::RegisterField<
223        0,
224        0x1,
225        1,
226        0,
227        adm0::Adce,
228        adm0::Adce,
229        Adm0_SPEC,
230        crate::common::RW,
231    > {
232        crate::common::RegisterField::<
233            0,
234            0x1,
235            1,
236            0,
237            adm0::Adce,
238            adm0::Adce,
239            Adm0_SPEC,
240            crate::common::RW,
241        >::from_register(self, 0)
242    }
243
244    #[doc = "Select Operation voltage mode"]
245    #[inline(always)]
246    pub fn lv(
247        self,
248    ) -> crate::common::RegisterField<1, 0x3, 1, 0, adm0::Lv, adm0::Lv, Adm0_SPEC, crate::common::RW>
249    {
250        crate::common::RegisterField::<1,0x3,1,0,adm0::Lv,adm0::Lv,Adm0_SPEC,crate::common::RW>::from_register(self,0)
251    }
252
253    #[doc = "Select Conversion Clock (fAD)"]
254    #[inline(always)]
255    pub fn fr(
256        self,
257    ) -> crate::common::RegisterField<3, 0x7, 1, 0, adm0::Fr, adm0::Fr, Adm0_SPEC, crate::common::RW>
258    {
259        crate::common::RegisterField::<3,0x7,1,0,adm0::Fr,adm0::Fr,Adm0_SPEC,crate::common::RW>::from_register(self,0)
260    }
261
262    #[doc = "Specification of the A/D conversion channel selection mode"]
263    #[inline(always)]
264    pub fn admd(
265        self,
266    ) -> crate::common::RegisterField<
267        6,
268        0x1,
269        1,
270        0,
271        adm0::Admd,
272        adm0::Admd,
273        Adm0_SPEC,
274        crate::common::RW,
275    > {
276        crate::common::RegisterField::<
277            6,
278            0x1,
279            1,
280            0,
281            adm0::Admd,
282            adm0::Admd,
283            Adm0_SPEC,
284            crate::common::RW,
285        >::from_register(self, 0)
286    }
287
288    #[doc = "A/D conversion operation control"]
289    #[inline(always)]
290    pub fn adcs(
291        self,
292    ) -> crate::common::RegisterField<
293        7,
294        0x1,
295        1,
296        0,
297        adm0::Adcs,
298        adm0::Adcs,
299        Adm0_SPEC,
300        crate::common::RW,
301    > {
302        crate::common::RegisterField::<
303            7,
304            0x1,
305            1,
306            0,
307            adm0::Adcs,
308            adm0::Adcs,
309            Adm0_SPEC,
310            crate::common::RW,
311        >::from_register(self, 0)
312    }
313}
314impl ::core::default::Default for Adm0 {
315    #[inline(always)]
316    fn default() -> Adm0 {
317        <crate::RegValueT<Adm0_SPEC> as RegisterValue<_>>::new(0)
318    }
319}
320pub mod adm0 {
321
322    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
323    pub struct Adce_SPEC;
324    pub type Adce = crate::EnumBitfieldStruct<u8, Adce_SPEC>;
325    impl Adce {
326        #[doc = "Stops A/D voltage comparator operation"]
327        pub const _0: Self = Self::new(0);
328
329        #[doc = "Enables A/D voltage comparator operation"]
330        pub const _1: Self = Self::new(1);
331    }
332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
333    pub struct Lv_SPEC;
334    pub type Lv = crate::EnumBitfieldStruct<u8, Lv_SPEC>;
335    impl Lv {
336        #[doc = "Normal mode 1"]
337        pub const _00: Self = Self::new(0);
338
339        #[doc = "Normal mode 2"]
340        pub const _01: Self = Self::new(1);
341
342        #[doc = "Low voltage mode 1"]
343        pub const _10: Self = Self::new(2);
344
345        #[doc = "Low voltage mode 2"]
346        pub const _11: Self = Self::new(3);
347    }
348    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
349    pub struct Fr_SPEC;
350    pub type Fr = crate::EnumBitfieldStruct<u8, Fr_SPEC>;
351    impl Fr {
352        #[doc = "PCLKB/32"]
353        pub const _000: Self = Self::new(0);
354
355        #[doc = "PCLKB/16"]
356        pub const _001: Self = Self::new(1);
357
358        #[doc = "PCLKB/8"]
359        pub const _010: Self = Self::new(2);
360
361        #[doc = "PCLKB/4"]
362        pub const _011: Self = Self::new(3);
363
364        #[doc = "PCLKB/2"]
365        pub const _100: Self = Self::new(4);
366
367        #[doc = "PCLKB"]
368        pub const _101: Self = Self::new(5);
369    }
370    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
371    pub struct Admd_SPEC;
372    pub type Admd = crate::EnumBitfieldStruct<u8, Admd_SPEC>;
373    impl Admd {
374        #[doc = "Select mode"]
375        pub const _0: Self = Self::new(0);
376
377        #[doc = "Scan mode"]
378        pub const _1: Self = Self::new(1);
379    }
380    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
381    pub struct Adcs_SPEC;
382    pub type Adcs = crate::EnumBitfieldStruct<u8, Adcs_SPEC>;
383    impl Adcs {
384        #[doc = "Stops conversion operation \\[When read\\] Conversion is stopped or in standby"]
385        pub const _0: Self = Self::new(0);
386
387        #[doc = "Enables conversion operation \\[When read\\] While in the no wait mode (both software and hardware trigger mode):Conversion is enabledWhile in the wait mode (both software and hardware trigger mode):A/D power supply stabilization wait time + conversion"]
388        pub const _1: Self = Self::new(1);
389    }
390}
391#[doc(hidden)]
392#[derive(Copy, Clone, Eq, PartialEq)]
393pub struct Ads_SPEC;
394impl crate::sealed::RegSpec for Ads_SPEC {
395    type DataType = u8;
396}
397
398#[doc = "Analog Input Channel Specification Register"]
399pub type Ads = crate::RegValueT<Ads_SPEC>;
400
401impl Ads {
402    #[doc = "Selection of the Analog Input Channel (See to )"]
403    #[inline(always)]
404    pub fn ads(
405        self,
406    ) -> crate::common::RegisterField<0, 0x1f, 1, 0, u8, u8, Ads_SPEC, crate::common::RW> {
407        crate::common::RegisterField::<0,0x1f,1,0,u8,u8,Ads_SPEC,crate::common::RW>::from_register(self,0)
408    }
409
410    #[doc = "Select Internal or External of Analog Input (See to )"]
411    #[inline(always)]
412    pub fn adiss(
413        self,
414    ) -> crate::common::RegisterField<
415        7,
416        0x1,
417        1,
418        0,
419        ads::Adiss,
420        ads::Adiss,
421        Ads_SPEC,
422        crate::common::RW,
423    > {
424        crate::common::RegisterField::<
425            7,
426            0x1,
427            1,
428            0,
429            ads::Adiss,
430            ads::Adiss,
431            Ads_SPEC,
432            crate::common::RW,
433        >::from_register(self, 0)
434    }
435}
436impl ::core::default::Default for Ads {
437    #[inline(always)]
438    fn default() -> Ads {
439        <crate::RegValueT<Ads_SPEC> as RegisterValue<_>>::new(0)
440    }
441}
442pub mod ads {
443
444    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
445    pub struct Adiss_SPEC;
446    pub type Adiss = crate::EnumBitfieldStruct<u8, Adiss_SPEC>;
447    impl Adiss {
448        #[doc = "External input"]
449        pub const _0: Self = Self::new(0);
450
451        #[doc = "Internal circuit input"]
452        pub const _1: Self = Self::new(1);
453    }
454}
455#[doc(hidden)]
456#[derive(Copy, Clone, Eq, PartialEq)]
457pub struct Adm1_SPEC;
458impl crate::sealed::RegSpec for Adm1_SPEC {
459    type DataType = u8;
460}
461
462#[doc = "A/D Converter Mode Register 1"]
463pub type Adm1 = crate::RegValueT<Adm1_SPEC>;
464
465impl Adm1 {
466    #[doc = "Selection of the Hardware Trigger Signal"]
467    #[inline(always)]
468    pub fn adtrs(
469        self,
470    ) -> crate::common::RegisterField<
471        0,
472        0x7,
473        1,
474        0,
475        adm1::Adtrs,
476        adm1::Adtrs,
477        Adm1_SPEC,
478        crate::common::RW,
479    > {
480        crate::common::RegisterField::<
481            0,
482            0x7,
483            1,
484            0,
485            adm1::Adtrs,
486            adm1::Adtrs,
487            Adm1_SPEC,
488            crate::common::RW,
489        >::from_register(self, 0)
490    }
491
492    #[doc = "PCLKB Input Frequency Setting"]
493    #[inline(always)]
494    pub fn adlsp(
495        self,
496    ) -> crate::common::RegisterField<
497        3,
498        0x1,
499        1,
500        0,
501        adm1::Adlsp,
502        adm1::Adlsp,
503        Adm1_SPEC,
504        crate::common::RW,
505    > {
506        crate::common::RegisterField::<
507            3,
508            0x1,
509            1,
510            0,
511            adm1::Adlsp,
512            adm1::Adlsp,
513            Adm1_SPEC,
514            crate::common::RW,
515        >::from_register(self, 0)
516    }
517
518    #[doc = "Specification of the A/D Conversion Mode"]
519    #[inline(always)]
520    pub fn adscm(
521        self,
522    ) -> crate::common::RegisterField<
523        5,
524        0x1,
525        1,
526        0,
527        adm1::Adscm,
528        adm1::Adscm,
529        Adm1_SPEC,
530        crate::common::RW,
531    > {
532        crate::common::RegisterField::<
533            5,
534            0x1,
535            1,
536            0,
537            adm1::Adscm,
538            adm1::Adscm,
539            Adm1_SPEC,
540            crate::common::RW,
541        >::from_register(self, 0)
542    }
543
544    #[doc = "Selection of the A/D Conversion Trigger Mode"]
545    #[inline(always)]
546    pub fn adtmd(
547        self,
548    ) -> crate::common::RegisterField<
549        6,
550        0x3,
551        1,
552        0,
553        adm1::Adtmd,
554        adm1::Adtmd,
555        Adm1_SPEC,
556        crate::common::RW,
557    > {
558        crate::common::RegisterField::<
559            6,
560            0x3,
561            1,
562            0,
563            adm1::Adtmd,
564            adm1::Adtmd,
565            Adm1_SPEC,
566            crate::common::RW,
567        >::from_register(self, 0)
568    }
569}
570impl ::core::default::Default for Adm1 {
571    #[inline(always)]
572    fn default() -> Adm1 {
573        <crate::RegValueT<Adm1_SPEC> as RegisterValue<_>>::new(0)
574    }
575}
576pub mod adm1 {
577
578    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
579    pub struct Adtrs_SPEC;
580    pub type Adtrs = crate::EnumBitfieldStruct<u8, Adtrs_SPEC>;
581    impl Adtrs {
582        #[doc = "Timer Array Unit channel 1 count or capture end interrupt signal (TAU0_TMI01)"]
583        pub const _000: Self = Self::new(0);
584
585        #[doc = "Realtime clock interrupt signal (RTC_ALM_OR_PRD)"]
586        pub const _010: Self = Self::new(2);
587
588        #[doc = "32-bit interval timer event signal (ADITL0 (= TML32_ITL0))"]
589        pub const _011: Self = Self::new(3);
590
591        #[doc = "Event input signal (ELC_AD)"]
592        pub const _100: Self = Self::new(4);
593    }
594    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
595    pub struct Adlsp_SPEC;
596    pub type Adlsp = crate::EnumBitfieldStruct<u8, Adlsp_SPEC>;
597    impl Adlsp {
598        #[doc = "4 MHz < PCLKB ≤ 32 MHz"]
599        pub const _0: Self = Self::new(0);
600
601        #[doc = "1 MHz ≤ PCLKB ≤ 4 MHz"]
602        pub const _1: Self = Self::new(1);
603    }
604    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
605    pub struct Adscm_SPEC;
606    pub type Adscm = crate::EnumBitfieldStruct<u8, Adscm_SPEC>;
607    impl Adscm {
608        #[doc = "Sequential conversion mode"]
609        pub const _0: Self = Self::new(0);
610
611        #[doc = "One-shot conversion mode"]
612        pub const _1: Self = Self::new(1);
613    }
614    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
615    pub struct Adtmd_SPEC;
616    pub type Adtmd = crate::EnumBitfieldStruct<u8, Adtmd_SPEC>;
617    impl Adtmd {
618        #[doc = "Hardware trigger no-wait mode"]
619        pub const _10: Self = Self::new(2);
620
621        #[doc = "Hardware trigger wait mode"]
622        pub const _11: Self = Self::new(3);
623    }
624}
625#[doc(hidden)]
626#[derive(Copy, Clone, Eq, PartialEq)]
627pub struct Adcr_SPEC;
628impl crate::sealed::RegSpec for Adcr_SPEC {
629    type DataType = u16;
630}
631
632#[doc = "12-bit or 10-bit A/D Conversion Result Register"]
633pub type Adcr = crate::RegValueT<Adcr_SPEC>;
634
635impl NoBitfieldReg<Adcr_SPEC> for Adcr {}
636impl ::core::default::Default for Adcr {
637    #[inline(always)]
638    fn default() -> Adcr {
639        <crate::RegValueT<Adcr_SPEC> as RegisterValue<_>>::new(0)
640    }
641}
642
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Adcrh_SPEC;
646impl crate::sealed::RegSpec for Adcrh_SPEC {
647    type DataType = u8;
648}
649
650#[doc = "8-bit A/D Conversion Result Register"]
651pub type Adcrh = crate::RegValueT<Adcrh_SPEC>;
652
653impl NoBitfieldReg<Adcrh_SPEC> for Adcrh {}
654impl ::core::default::Default for Adcrh {
655    #[inline(always)]
656    fn default() -> Adcrh {
657        <crate::RegValueT<Adcrh_SPEC> as RegisterValue<_>>::new(0)
658    }
659}
660
661#[doc(hidden)]
662#[derive(Copy, Clone, Eq, PartialEq)]
663pub struct Adm2_SPEC;
664impl crate::sealed::RegSpec for Adm2_SPEC {
665    type DataType = u8;
666}
667
668#[doc = "A/D Converter Mode Register 2"]
669pub type Adm2 = crate::RegValueT<Adm2_SPEC>;
670
671impl Adm2 {
672    #[inline(always)]
673    pub fn adtyp(
674        self,
675    ) -> crate::common::RegisterField<
676        0,
677        0x3,
678        1,
679        0,
680        adm2::Adtyp,
681        adm2::Adtyp,
682        Adm2_SPEC,
683        crate::common::RW,
684    > {
685        crate::common::RegisterField::<
686            0,
687            0x3,
688            1,
689            0,
690            adm2::Adtyp,
691            adm2::Adtyp,
692            Adm2_SPEC,
693            crate::common::RW,
694        >::from_register(self, 0)
695    }
696
697    #[inline(always)]
698    pub fn awc(
699        self,
700    ) -> crate::common::RegisterField<
701        2,
702        0x1,
703        1,
704        0,
705        adm2::Awc,
706        adm2::Awc,
707        Adm2_SPEC,
708        crate::common::RW,
709    > {
710        crate::common::RegisterField::<
711            2,
712            0x1,
713            1,
714            0,
715            adm2::Awc,
716            adm2::Awc,
717            Adm2_SPEC,
718            crate::common::RW,
719        >::from_register(self, 0)
720    }
721
722    #[inline(always)]
723    pub fn adrck(
724        self,
725    ) -> crate::common::RegisterField<
726        3,
727        0x1,
728        1,
729        0,
730        adm2::Adrck,
731        adm2::Adrck,
732        Adm2_SPEC,
733        crate::common::RW,
734    > {
735        crate::common::RegisterField::<
736            3,
737            0x1,
738            1,
739            0,
740            adm2::Adrck,
741            adm2::Adrck,
742            Adm2_SPEC,
743            crate::common::RW,
744        >::from_register(self, 0)
745    }
746
747    #[inline(always)]
748    pub fn adrefm(
749        self,
750    ) -> crate::common::RegisterField<
751        5,
752        0x1,
753        1,
754        0,
755        adm2::Adrefm,
756        adm2::Adrefm,
757        Adm2_SPEC,
758        crate::common::RW,
759    > {
760        crate::common::RegisterField::<
761            5,
762            0x1,
763            1,
764            0,
765            adm2::Adrefm,
766            adm2::Adrefm,
767            Adm2_SPEC,
768            crate::common::RW,
769        >::from_register(self, 0)
770    }
771
772    #[inline(always)]
773    pub fn adrefp(
774        self,
775    ) -> crate::common::RegisterField<
776        6,
777        0x3,
778        1,
779        0,
780        adm2::Adrefp,
781        adm2::Adrefp,
782        Adm2_SPEC,
783        crate::common::RW,
784    > {
785        crate::common::RegisterField::<
786            6,
787            0x3,
788            1,
789            0,
790            adm2::Adrefp,
791            adm2::Adrefp,
792            Adm2_SPEC,
793            crate::common::RW,
794        >::from_register(self, 0)
795    }
796}
797impl ::core::default::Default for Adm2 {
798    #[inline(always)]
799    fn default() -> Adm2 {
800        <crate::RegValueT<Adm2_SPEC> as RegisterValue<_>>::new(0)
801    }
802}
803pub mod adm2 {
804
805    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
806    pub struct Adtyp_SPEC;
807    pub type Adtyp = crate::EnumBitfieldStruct<u8, Adtyp_SPEC>;
808    impl Adtyp {
809        #[doc = "10-bit resolution"]
810        pub const _00: Self = Self::new(0);
811
812        #[doc = "8-bit resolution"]
813        pub const _01: Self = Self::new(1);
814
815        #[doc = "12-bit resolution"]
816        pub const _10: Self = Self::new(2);
817    }
818    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
819    pub struct Awc_SPEC;
820    pub type Awc = crate::EnumBitfieldStruct<u8, Awc_SPEC>;
821    impl Awc {
822        #[doc = "Do not use the Snooze mode function."]
823        pub const _0: Self = Self::new(0);
824
825        #[doc = "Use the Snooze mode function."]
826        pub const _1: Self = Self::new(1);
827    }
828    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
829    pub struct Adrck_SPEC;
830    pub type Adrck = crate::EnumBitfieldStruct<u8, Adrck_SPEC>;
831    impl Adrck {
832        #[doc = "The interrupt signal (ADC12_ADI) is output when the ADLL register ≤ the ADCRn register ≤ the ADUL register (AREA 1)."]
833        pub const _0: Self = Self::new(0);
834
835        #[doc = "The interrupt signal (ADC12_ADI) is output when the ADCRn register < the ADLL register (AREA 2) or the ADUL register < the ADCRn register (AREA 3)."]
836        pub const _1: Self = Self::new(1);
837    }
838    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
839    pub struct Adrefm_SPEC;
840    pub type Adrefm = crate::EnumBitfieldStruct<u8, Adrefm_SPEC>;
841    impl Adrefm {
842        #[doc = "Supplied from VSS"]
843        pub const _0: Self = Self::new(0);
844
845        #[doc = "Supplied from VREFL0/AN001"]
846        pub const _1: Self = Self::new(1);
847    }
848    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
849    pub struct Adrefp_SPEC;
850    pub type Adrefp = crate::EnumBitfieldStruct<u8, Adrefp_SPEC>;
851    impl Adrefp {
852        #[doc = "Supplied from VCC"]
853        pub const _00: Self = Self::new(0);
854
855        #[doc = "Supplied from VREFH0/AN000"]
856        pub const _01: Self = Self::new(1);
857
858        #[doc = "Supplied from the internal reference voltage"]
859        pub const _10: Self = Self::new(2);
860
861        #[doc = "Discharge the internal circuitry"]
862        pub const _11: Self = Self::new(3);
863    }
864}
865#[doc(hidden)]
866#[derive(Copy, Clone, Eq, PartialEq)]
867pub struct Adul_SPEC;
868impl crate::sealed::RegSpec for Adul_SPEC {
869    type DataType = u8;
870}
871
872#[doc = "Conversion Result Comparison Upper Limit Setting Register"]
873pub type Adul = crate::RegValueT<Adul_SPEC>;
874
875impl NoBitfieldReg<Adul_SPEC> for Adul {}
876impl ::core::default::Default for Adul {
877    #[inline(always)]
878    fn default() -> Adul {
879        <crate::RegValueT<Adul_SPEC> as RegisterValue<_>>::new(255)
880    }
881}
882
883#[doc(hidden)]
884#[derive(Copy, Clone, Eq, PartialEq)]
885pub struct Adll_SPEC;
886impl crate::sealed::RegSpec for Adll_SPEC {
887    type DataType = u8;
888}
889
890#[doc = "Conversion Result Comparison Lower Limit Setting Register"]
891pub type Adll = crate::RegValueT<Adll_SPEC>;
892
893impl NoBitfieldReg<Adll_SPEC> for Adll {}
894impl ::core::default::Default for Adll {
895    #[inline(always)]
896    fn default() -> Adll {
897        <crate::RegValueT<Adll_SPEC> as RegisterValue<_>>::new(0)
898    }
899}
900
901#[doc(hidden)]
902#[derive(Copy, Clone, Eq, PartialEq)]
903pub struct Adtes_SPEC;
904impl crate::sealed::RegSpec for Adtes_SPEC {
905    type DataType = u8;
906}
907
908#[doc = "A/D Test Register"]
909pub type Adtes = crate::RegValueT<Adtes_SPEC>;
910
911impl Adtes {
912    #[doc = "Selection of A/D Conversion Target for Testing"]
913    #[inline(always)]
914    pub fn adtes(
915        self,
916    ) -> crate::common::RegisterField<
917        0,
918        0x3,
919        1,
920        0,
921        adtes::Adtes,
922        adtes::Adtes,
923        Adtes_SPEC,
924        crate::common::RW,
925    > {
926        crate::common::RegisterField::<
927            0,
928            0x3,
929            1,
930            0,
931            adtes::Adtes,
932            adtes::Adtes,
933            Adtes_SPEC,
934            crate::common::RW,
935        >::from_register(self, 0)
936    }
937}
938impl ::core::default::Default for Adtes {
939    #[inline(always)]
940    fn default() -> Adtes {
941        <crate::RegValueT<Adtes_SPEC> as RegisterValue<_>>::new(0)
942    }
943}
944pub mod adtes {
945
946    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
947    pub struct Adtes_SPEC;
948    pub type Adtes = crate::EnumBitfieldStruct<u8, Adtes_SPEC>;
949    impl Adtes {
950        #[doc = "ANxxx, temperature sensor output voltage or internal reference voltage (Set by analog input channel specification register (ADS))"]
951        pub const _00: Self = Self::new(0);
952
953        #[doc = "The ‘-’ side reference voltage (selected by the ADREFM bit of the ADM2 register)"]
954        pub const _10: Self = Self::new(2);
955
956        #[doc = "The ‘+’ side reference voltage (selected by the ADREFP\\[1:0\\] bits of the ADM2 register)"]
957        pub const _11: Self = Self::new(3);
958    }
959}
960#[doc(hidden)]
961#[derive(Copy, Clone, Eq, PartialEq)]
962pub struct Adcr0_SPEC;
963impl crate::sealed::RegSpec for Adcr0_SPEC {
964    type DataType = u16;
965}
966
967#[doc = "12-bit or 10-bit A/D Conversion Result Register 0"]
968pub type Adcr0 = crate::RegValueT<Adcr0_SPEC>;
969
970impl NoBitfieldReg<Adcr0_SPEC> for Adcr0 {}
971impl ::core::default::Default for Adcr0 {
972    #[inline(always)]
973    fn default() -> Adcr0 {
974        <crate::RegValueT<Adcr0_SPEC> as RegisterValue<_>>::new(0)
975    }
976}
977
978#[doc(hidden)]
979#[derive(Copy, Clone, Eq, PartialEq)]
980pub struct Adcr0H_SPEC;
981impl crate::sealed::RegSpec for Adcr0H_SPEC {
982    type DataType = u8;
983}
984
985#[doc = "8-bit A/D Conversion Result Register 0"]
986pub type Adcr0H = crate::RegValueT<Adcr0H_SPEC>;
987
988impl NoBitfieldReg<Adcr0H_SPEC> for Adcr0H {}
989impl ::core::default::Default for Adcr0H {
990    #[inline(always)]
991    fn default() -> Adcr0H {
992        <crate::RegValueT<Adcr0H_SPEC> as RegisterValue<_>>::new(0)
993    }
994}
995
996#[doc(hidden)]
997#[derive(Copy, Clone, Eq, PartialEq)]
998pub struct Adcr1_SPEC;
999impl crate::sealed::RegSpec for Adcr1_SPEC {
1000    type DataType = u16;
1001}
1002
1003#[doc = "12-bit or 10-bit A/D Conversion Result Register 1"]
1004pub type Adcr1 = crate::RegValueT<Adcr1_SPEC>;
1005
1006impl NoBitfieldReg<Adcr1_SPEC> for Adcr1 {}
1007impl ::core::default::Default for Adcr1 {
1008    #[inline(always)]
1009    fn default() -> Adcr1 {
1010        <crate::RegValueT<Adcr1_SPEC> as RegisterValue<_>>::new(0)
1011    }
1012}
1013
1014#[doc(hidden)]
1015#[derive(Copy, Clone, Eq, PartialEq)]
1016pub struct Adcr1H_SPEC;
1017impl crate::sealed::RegSpec for Adcr1H_SPEC {
1018    type DataType = u8;
1019}
1020
1021#[doc = "8-bit A/D Conversion Result Register 1"]
1022pub type Adcr1H = crate::RegValueT<Adcr1H_SPEC>;
1023
1024impl NoBitfieldReg<Adcr1H_SPEC> for Adcr1H {}
1025impl ::core::default::Default for Adcr1H {
1026    #[inline(always)]
1027    fn default() -> Adcr1H {
1028        <crate::RegValueT<Adcr1H_SPEC> as RegisterValue<_>>::new(0)
1029    }
1030}
1031
1032#[doc(hidden)]
1033#[derive(Copy, Clone, Eq, PartialEq)]
1034pub struct Adcr2_SPEC;
1035impl crate::sealed::RegSpec for Adcr2_SPEC {
1036    type DataType = u16;
1037}
1038
1039#[doc = "12-bit or 10-bit A/D Conversion Result Register 2"]
1040pub type Adcr2 = crate::RegValueT<Adcr2_SPEC>;
1041
1042impl NoBitfieldReg<Adcr2_SPEC> for Adcr2 {}
1043impl ::core::default::Default for Adcr2 {
1044    #[inline(always)]
1045    fn default() -> Adcr2 {
1046        <crate::RegValueT<Adcr2_SPEC> as RegisterValue<_>>::new(0)
1047    }
1048}
1049
1050#[doc(hidden)]
1051#[derive(Copy, Clone, Eq, PartialEq)]
1052pub struct Adcr2H_SPEC;
1053impl crate::sealed::RegSpec for Adcr2H_SPEC {
1054    type DataType = u8;
1055}
1056
1057#[doc = "8-bit A/D Conversion Result Register 2"]
1058pub type Adcr2H = crate::RegValueT<Adcr2H_SPEC>;
1059
1060impl NoBitfieldReg<Adcr2H_SPEC> for Adcr2H {}
1061impl ::core::default::Default for Adcr2H {
1062    #[inline(always)]
1063    fn default() -> Adcr2H {
1064        <crate::RegValueT<Adcr2H_SPEC> as RegisterValue<_>>::new(0)
1065    }
1066}
1067
1068#[doc(hidden)]
1069#[derive(Copy, Clone, Eq, PartialEq)]
1070pub struct Adcr3_SPEC;
1071impl crate::sealed::RegSpec for Adcr3_SPEC {
1072    type DataType = u16;
1073}
1074
1075#[doc = "12-bit or 10-bit A/D Conversion Result Register 3"]
1076pub type Adcr3 = crate::RegValueT<Adcr3_SPEC>;
1077
1078impl NoBitfieldReg<Adcr3_SPEC> for Adcr3 {}
1079impl ::core::default::Default for Adcr3 {
1080    #[inline(always)]
1081    fn default() -> Adcr3 {
1082        <crate::RegValueT<Adcr3_SPEC> as RegisterValue<_>>::new(0)
1083    }
1084}
1085
1086#[doc(hidden)]
1087#[derive(Copy, Clone, Eq, PartialEq)]
1088pub struct Adcr3H_SPEC;
1089impl crate::sealed::RegSpec for Adcr3H_SPEC {
1090    type DataType = u8;
1091}
1092
1093#[doc = "8-bit A/D Conversion Result Register 3"]
1094pub type Adcr3H = crate::RegValueT<Adcr3H_SPEC>;
1095
1096impl NoBitfieldReg<Adcr3H_SPEC> for Adcr3H {}
1097impl ::core::default::Default for Adcr3H {
1098    #[inline(always)]
1099    fn default() -> Adcr3H {
1100        <crate::RegValueT<Adcr3H_SPEC> as RegisterValue<_>>::new(0)
1101    }
1102}
ra0e1_pac/adc_d.rs

ra0e1_pac/
adc_d.rs
