ra0e1_pac/
uarta.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Interface UARTA"]
28unsafe impl ::core::marker::Send for super::Uarta {}
29unsafe impl ::core::marker::Sync for super::Uarta {}
30impl super::Uarta {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Transmit Buffer Register 0"]
38    #[inline(always)]
39    pub const fn txba0(&self) -> &'static crate::common::Reg<self::Txba0_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Txba0_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Receive Buffer Register 0"]
48    #[inline(always)]
49    pub const fn rxba0(&self) -> &'static crate::common::Reg<self::Rxba0_SPEC, crate::common::R> {
50        unsafe {
51            crate::common::Reg::<self::Rxba0_SPEC, crate::common::R>::from_ptr(
52                self._svd2pac_as_ptr().add(1usize),
53            )
54        }
55    }
56
57    #[doc = "Operation Mode Setting Register 00"]
58    #[inline(always)]
59    pub const fn asima00(
60        &self,
61    ) -> &'static crate::common::Reg<self::Asima00_SPEC, crate::common::RW> {
62        unsafe {
63            crate::common::Reg::<self::Asima00_SPEC, crate::common::RW>::from_ptr(
64                self._svd2pac_as_ptr().add(2usize),
65            )
66        }
67    }
68
69    #[doc = "Operation Mode Setting Register 01"]
70    #[inline(always)]
71    pub const fn asima01(
72        &self,
73    ) -> &'static crate::common::Reg<self::Asima01_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::Asima01_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(3usize),
77            )
78        }
79    }
80
81    #[doc = "Baud Rate Generator Control Register 0"]
82    #[inline(always)]
83    pub const fn brgca0(
84        &self,
85    ) -> &'static crate::common::Reg<self::Brgca0_SPEC, crate::common::RW> {
86        unsafe {
87            crate::common::Reg::<self::Brgca0_SPEC, crate::common::RW>::from_ptr(
88                self._svd2pac_as_ptr().add(4usize),
89            )
90        }
91    }
92
93    #[doc = "Status Register 0"]
94    #[inline(always)]
95    pub const fn asisa0(&self) -> &'static crate::common::Reg<self::Asisa0_SPEC, crate::common::R> {
96        unsafe {
97            crate::common::Reg::<self::Asisa0_SPEC, crate::common::R>::from_ptr(
98                self._svd2pac_as_ptr().add(5usize),
99            )
100        }
101    }
102
103    #[doc = "Status Clear Trigger Register 0"]
104    #[inline(always)]
105    pub const fn ascta0(
106        &self,
107    ) -> &'static crate::common::Reg<self::Ascta0_SPEC, crate::common::RW> {
108        unsafe {
109            crate::common::Reg::<self::Ascta0_SPEC, crate::common::RW>::from_ptr(
110                self._svd2pac_as_ptr().add(6usize),
111            )
112        }
113    }
114
115    #[doc = "UARTA Clock Select Register 0"]
116    #[inline(always)]
117    pub const fn uta0ck(
118        &self,
119    ) -> &'static crate::common::Reg<self::Uta0Ck_SPEC, crate::common::RW> {
120        unsafe {
121            crate::common::Reg::<self::Uta0Ck_SPEC, crate::common::RW>::from_ptr(
122                self._svd2pac_as_ptr().add(256usize),
123            )
124        }
125    }
126}
127#[doc(hidden)]
128#[derive(Copy, Clone, Eq, PartialEq)]
129pub struct Txba0_SPEC;
130impl crate::sealed::RegSpec for Txba0_SPEC {
131    type DataType = u8;
132}
133
134#[doc = "Transmit Buffer Register 0"]
135pub type Txba0 = crate::RegValueT<Txba0_SPEC>;
136
137impl NoBitfieldReg<Txba0_SPEC> for Txba0 {}
138impl ::core::default::Default for Txba0 {
139    #[inline(always)]
140    fn default() -> Txba0 {
141        <crate::RegValueT<Txba0_SPEC> as RegisterValue<_>>::new(255)
142    }
143}
144
145#[doc(hidden)]
146#[derive(Copy, Clone, Eq, PartialEq)]
147pub struct Rxba0_SPEC;
148impl crate::sealed::RegSpec for Rxba0_SPEC {
149    type DataType = u8;
150}
151
152#[doc = "Receive Buffer Register 0"]
153pub type Rxba0 = crate::RegValueT<Rxba0_SPEC>;
154
155impl NoBitfieldReg<Rxba0_SPEC> for Rxba0 {}
156impl ::core::default::Default for Rxba0 {
157    #[inline(always)]
158    fn default() -> Rxba0 {
159        <crate::RegValueT<Rxba0_SPEC> as RegisterValue<_>>::new(255)
160    }
161}
162
163#[doc(hidden)]
164#[derive(Copy, Clone, Eq, PartialEq)]
165pub struct Asima00_SPEC;
166impl crate::sealed::RegSpec for Asima00_SPEC {
167    type DataType = u8;
168}
169
170#[doc = "Operation Mode Setting Register 00"]
171pub type Asima00 = crate::RegValueT<Asima00_SPEC>;
172
173impl Asima00 {
174    #[doc = "Receive Interrupt Mode Select"]
175    #[inline(always)]
176    pub fn isrma(
177        self,
178    ) -> crate::common::RegisterField<
179        0,
180        0x1,
181        1,
182        0,
183        asima00::Isrma,
184        asima00::Isrma,
185        Asima00_SPEC,
186        crate::common::RW,
187    > {
188        crate::common::RegisterField::<
189            0,
190            0x1,
191            1,
192            0,
193            asima00::Isrma,
194            asima00::Isrma,
195            Asima00_SPEC,
196            crate::common::RW,
197        >::from_register(self, 0)
198    }
199
200    #[doc = "Transmit Interrupt Mode Select"]
201    #[inline(always)]
202    pub fn issma(
203        self,
204    ) -> crate::common::RegisterField<
205        1,
206        0x1,
207        1,
208        0,
209        asima00::Issma,
210        asima00::Issma,
211        Asima00_SPEC,
212        crate::common::RW,
213    > {
214        crate::common::RegisterField::<
215            1,
216            0x1,
217            1,
218            0,
219            asima00::Issma,
220            asima00::Issma,
221            Asima00_SPEC,
222            crate::common::RW,
223        >::from_register(self, 0)
224    }
225
226    #[doc = "Reception Enable"]
227    #[inline(always)]
228    pub fn rxea(
229        self,
230    ) -> crate::common::RegisterField<
231        5,
232        0x1,
233        1,
234        0,
235        asima00::Rxea,
236        asima00::Rxea,
237        Asima00_SPEC,
238        crate::common::RW,
239    > {
240        crate::common::RegisterField::<
241            5,
242            0x1,
243            1,
244            0,
245            asima00::Rxea,
246            asima00::Rxea,
247            Asima00_SPEC,
248            crate::common::RW,
249        >::from_register(self, 0)
250    }
251
252    #[doc = "Transmission Enable"]
253    #[inline(always)]
254    pub fn txea(
255        self,
256    ) -> crate::common::RegisterField<
257        6,
258        0x1,
259        1,
260        0,
261        asima00::Txea,
262        asima00::Txea,
263        Asima00_SPEC,
264        crate::common::RW,
265    > {
266        crate::common::RegisterField::<
267            6,
268            0x1,
269            1,
270            0,
271            asima00::Txea,
272            asima00::Txea,
273            Asima00_SPEC,
274            crate::common::RW,
275        >::from_register(self, 0)
276    }
277
278    #[doc = "UART Operation Enable"]
279    #[inline(always)]
280    pub fn en(
281        self,
282    ) -> crate::common::RegisterField<
283        7,
284        0x1,
285        1,
286        0,
287        asima00::En,
288        asima00::En,
289        Asima00_SPEC,
290        crate::common::RW,
291    > {
292        crate::common::RegisterField::<
293            7,
294            0x1,
295            1,
296            0,
297            asima00::En,
298            asima00::En,
299            Asima00_SPEC,
300            crate::common::RW,
301        >::from_register(self, 0)
302    }
303}
304impl ::core::default::Default for Asima00 {
305    #[inline(always)]
306    fn default() -> Asima00 {
307        <crate::RegValueT<Asima00_SPEC> as RegisterValue<_>>::new(1)
308    }
309}
310pub mod asima00 {
311
312    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
313    pub struct Isrma_SPEC;
314    pub type Isrma = crate::EnumBitfieldStruct<u8, Isrma_SPEC>;
315    impl Isrma {
316        #[doc = "The UARTA0_ERRI interrupt is generated when a reception error occurs (UARTA0_RXI is not generated)"]
317        pub const _0: Self = Self::new(0);
318
319        #[doc = "The UARTA0_RXI interrupt is generated when a reception error occurs (UARTA0_ERRI is not generated)"]
320        pub const _1: Self = Self::new(1);
321    }
322    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
323    pub struct Issma_SPEC;
324    pub type Issma = crate::EnumBitfieldStruct<u8, Issma_SPEC>;
325    impl Issma {
326        #[doc = "The UARTA0_TXI interrupt is generated on completion of transmission"]
327        pub const _0: Self = Self::new(0);
328
329        #[doc = "The UARTA0_TXI interrupt is generated when the transmit buffer becomes empty (for continuous transmission)"]
330        pub const _1: Self = Self::new(1);
331    }
332    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
333    pub struct Rxea_SPEC;
334    pub type Rxea = crate::EnumBitfieldStruct<u8, Rxea_SPEC>;
335    impl Rxea {
336        #[doc = "Disables reception (reset the reception circuit)"]
337        pub const _0: Self = Self::new(0);
338
339        #[doc = "Enables reception"]
340        pub const _1: Self = Self::new(1);
341    }
342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
343    pub struct Txea_SPEC;
344    pub type Txea = crate::EnumBitfieldStruct<u8, Txea_SPEC>;
345    impl Txea {
346        #[doc = "Disables transmission (resets the transmission circuit)"]
347        pub const _0: Self = Self::new(0);
348
349        #[doc = "Enables transmission"]
350        pub const _1: Self = Self::new(1);
351    }
352    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
353    pub struct En_SPEC;
354    pub type En = crate::EnumBitfieldStruct<u8, En_SPEC>;
355    impl En {
356        #[doc = "Disables the UART operation clock (resets the internal circuits)"]
357        pub const _0: Self = Self::new(0);
358
359        #[doc = "Enables the UART operation clock"]
360        pub const _1: Self = Self::new(1);
361    }
362}
363#[doc(hidden)]
364#[derive(Copy, Clone, Eq, PartialEq)]
365pub struct Asima01_SPEC;
366impl crate::sealed::RegSpec for Asima01_SPEC {
367    type DataType = u8;
368}
369
370#[doc = "Operation Mode Setting Register 01"]
371pub type Asima01 = crate::RegValueT<Asima01_SPEC>;
372
373impl Asima01 {
374    #[doc = "Transmission and Reception Level Setting"]
375    #[inline(always)]
376    pub fn alv(
377        self,
378    ) -> crate::common::RegisterField<
379        0,
380        0x1,
381        1,
382        0,
383        asima01::Alv,
384        asima01::Alv,
385        Asima01_SPEC,
386        crate::common::RW,
387    > {
388        crate::common::RegisterField::<
389            0,
390            0x1,
391            1,
392            0,
393            asima01::Alv,
394            asima01::Alv,
395            Asima01_SPEC,
396            crate::common::RW,
397        >::from_register(self, 0)
398    }
399
400    #[doc = "Transmission and Reception Order Setting"]
401    #[inline(always)]
402    pub fn dir(
403        self,
404    ) -> crate::common::RegisterField<
405        1,
406        0x1,
407        1,
408        0,
409        asima01::Dir,
410        asima01::Dir,
411        Asima01_SPEC,
412        crate::common::RW,
413    > {
414        crate::common::RegisterField::<
415            1,
416            0x1,
417            1,
418            0,
419            asima01::Dir,
420            asima01::Dir,
421            Asima01_SPEC,
422            crate::common::RW,
423        >::from_register(self, 0)
424    }
425
426    #[doc = "Transmission Stop Bit Length Setting"]
427    #[inline(always)]
428    pub fn sl(
429        self,
430    ) -> crate::common::RegisterField<
431        2,
432        0x1,
433        1,
434        0,
435        asima01::Sl,
436        asima01::Sl,
437        Asima01_SPEC,
438        crate::common::RW,
439    > {
440        crate::common::RegisterField::<
441            2,
442            0x1,
443            1,
444            0,
445            asima01::Sl,
446            asima01::Sl,
447            Asima01_SPEC,
448            crate::common::RW,
449        >::from_register(self, 0)
450    }
451
452    #[doc = "Transmission and Reception Character Length Setting"]
453    #[inline(always)]
454    pub fn cl(
455        self,
456    ) -> crate::common::RegisterField<
457        3,
458        0x3,
459        1,
460        0,
461        asima01::Cl,
462        asima01::Cl,
463        Asima01_SPEC,
464        crate::common::RW,
465    > {
466        crate::common::RegisterField::<
467            3,
468            0x3,
469            1,
470            0,
471            asima01::Cl,
472            asima01::Cl,
473            Asima01_SPEC,
474            crate::common::RW,
475        >::from_register(self, 0)
476    }
477
478    #[doc = "Transmission and Reception Parity Bit Setting"]
479    #[inline(always)]
480    pub fn ps(
481        self,
482    ) -> crate::common::RegisterField<
483        5,
484        0x3,
485        1,
486        0,
487        asima01::Ps,
488        asima01::Ps,
489        Asima01_SPEC,
490        crate::common::RW,
491    > {
492        crate::common::RegisterField::<
493            5,
494            0x3,
495            1,
496            0,
497            asima01::Ps,
498            asima01::Ps,
499            Asima01_SPEC,
500            crate::common::RW,
501        >::from_register(self, 0)
502    }
503}
504impl ::core::default::Default for Asima01 {
505    #[inline(always)]
506    fn default() -> Asima01 {
507        <crate::RegValueT<Asima01_SPEC> as RegisterValue<_>>::new(26)
508    }
509}
510pub mod asima01 {
511
512    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
513    pub struct Alv_SPEC;
514    pub type Alv = crate::EnumBitfieldStruct<u8, Alv_SPEC>;
515    impl Alv {
516        #[doc = "Positive logic (wait state = high level, start bit = low level, stop bit = high level)"]
517        pub const _0: Self = Self::new(0);
518
519        #[doc = "Negative logic (wait state = low level, start bit = high level, stop bit = low level)"]
520        pub const _1: Self = Self::new(1);
521    }
522    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
523    pub struct Dir_SPEC;
524    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
525    impl Dir {
526        #[doc = "MSB first"]
527        pub const _0: Self = Self::new(0);
528
529        #[doc = "LSB first"]
530        pub const _1: Self = Self::new(1);
531    }
532    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
533    pub struct Sl_SPEC;
534    pub type Sl = crate::EnumBitfieldStruct<u8, Sl_SPEC>;
535    impl Sl {
536        #[doc = "Stop bit length = 1 bit"]
537        pub const _0: Self = Self::new(0);
538
539        #[doc = "Stop bit length = 2 bits"]
540        pub const _1: Self = Self::new(1);
541    }
542    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
543    pub struct Cl_SPEC;
544    pub type Cl = crate::EnumBitfieldStruct<u8, Cl_SPEC>;
545    impl Cl {
546        #[doc = "Character length of data = 5 bits"]
547        pub const _00: Self = Self::new(0);
548
549        #[doc = "Setting prohibited"]
550        pub const _01: Self = Self::new(1);
551
552        #[doc = "Character length of data = 7 bits"]
553        pub const _10: Self = Self::new(2);
554
555        #[doc = "Character length of data = 8 bits"]
556        pub const _11: Self = Self::new(3);
557    }
558    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
559    pub struct Ps_SPEC;
560    pub type Ps = crate::EnumBitfieldStruct<u8, Ps_SPEC>;
561    impl Ps {
562        #[doc = "Transmission: No parity bit is output. Reception: Data is received without parity."]
563        pub const _00: Self = Self::new(0);
564
565        #[doc = "Transmission: 0 parity is output. Reception: Data is received with 0 parity."]
566        pub const _01: Self = Self::new(1);
567
568        #[doc = "Transmission: Odd parity is output. Reception: Check is made for odd parity."]
569        pub const _10: Self = Self::new(2);
570
571        #[doc = "Transmission: Even parity is output. Reception: Check is made for even parity."]
572        pub const _11: Self = Self::new(3);
573    }
574}
575#[doc(hidden)]
576#[derive(Copy, Clone, Eq, PartialEq)]
577pub struct Brgca0_SPEC;
578impl crate::sealed::RegSpec for Brgca0_SPEC {
579    type DataType = u8;
580}
581
582#[doc = "Baud Rate Generator Control Register 0"]
583pub type Brgca0 = crate::RegValueT<Brgca0_SPEC>;
584
585impl NoBitfieldReg<Brgca0_SPEC> for Brgca0 {}
586impl ::core::default::Default for Brgca0 {
587    #[inline(always)]
588    fn default() -> Brgca0 {
589        <crate::RegValueT<Brgca0_SPEC> as RegisterValue<_>>::new(255)
590    }
591}
592
593#[doc(hidden)]
594#[derive(Copy, Clone, Eq, PartialEq)]
595pub struct Asisa0_SPEC;
596impl crate::sealed::RegSpec for Asisa0_SPEC {
597    type DataType = u8;
598}
599
600#[doc = "Status Register 0"]
601pub type Asisa0 = crate::RegValueT<Asisa0_SPEC>;
602
603impl Asisa0 {
604    #[doc = "Overrun Error Flag"]
605    #[inline(always)]
606    pub fn ovea(
607        self,
608    ) -> crate::common::RegisterField<
609        0,
610        0x1,
611        1,
612        0,
613        asisa0::Ovea,
614        asisa0::Ovea,
615        Asisa0_SPEC,
616        crate::common::R,
617    > {
618        crate::common::RegisterField::<
619            0,
620            0x1,
621            1,
622            0,
623            asisa0::Ovea,
624            asisa0::Ovea,
625            Asisa0_SPEC,
626            crate::common::R,
627        >::from_register(self, 0)
628    }
629
630    #[doc = "Framing Error Flag"]
631    #[inline(always)]
632    pub fn fea(
633        self,
634    ) -> crate::common::RegisterField<
635        1,
636        0x1,
637        1,
638        0,
639        asisa0::Fea,
640        asisa0::Fea,
641        Asisa0_SPEC,
642        crate::common::R,
643    > {
644        crate::common::RegisterField::<
645            1,
646            0x1,
647            1,
648            0,
649            asisa0::Fea,
650            asisa0::Fea,
651            Asisa0_SPEC,
652            crate::common::R,
653        >::from_register(self, 0)
654    }
655
656    #[doc = "Parity Error Flag"]
657    #[inline(always)]
658    pub fn pea(
659        self,
660    ) -> crate::common::RegisterField<
661        2,
662        0x1,
663        1,
664        0,
665        asisa0::Pea,
666        asisa0::Pea,
667        Asisa0_SPEC,
668        crate::common::R,
669    > {
670        crate::common::RegisterField::<
671            2,
672            0x1,
673            1,
674            0,
675            asisa0::Pea,
676            asisa0::Pea,
677            Asisa0_SPEC,
678            crate::common::R,
679        >::from_register(self, 0)
680    }
681
682    #[doc = "Transmit Shift Register Data Flag"]
683    #[inline(always)]
684    pub fn txsfa(
685        self,
686    ) -> crate::common::RegisterField<
687        4,
688        0x1,
689        1,
690        0,
691        asisa0::Txsfa,
692        asisa0::Txsfa,
693        Asisa0_SPEC,
694        crate::common::R,
695    > {
696        crate::common::RegisterField::<
697            4,
698            0x1,
699            1,
700            0,
701            asisa0::Txsfa,
702            asisa0::Txsfa,
703            Asisa0_SPEC,
704            crate::common::R,
705        >::from_register(self, 0)
706    }
707
708    #[doc = "Transmit Buffer Data Flag"]
709    #[inline(always)]
710    pub fn txbfa(
711        self,
712    ) -> crate::common::RegisterField<
713        5,
714        0x1,
715        1,
716        0,
717        asisa0::Txbfa,
718        asisa0::Txbfa,
719        Asisa0_SPEC,
720        crate::common::R,
721    > {
722        crate::common::RegisterField::<
723            5,
724            0x1,
725            1,
726            0,
727            asisa0::Txbfa,
728            asisa0::Txbfa,
729            Asisa0_SPEC,
730            crate::common::R,
731        >::from_register(self, 0)
732    }
733}
734impl ::core::default::Default for Asisa0 {
735    #[inline(always)]
736    fn default() -> Asisa0 {
737        <crate::RegValueT<Asisa0_SPEC> as RegisterValue<_>>::new(0)
738    }
739}
740pub mod asisa0 {
741
742    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
743    pub struct Ovea_SPEC;
744    pub type Ovea = crate::EnumBitfieldStruct<u8, Ovea_SPEC>;
745    impl Ovea {
746        #[doc = "No error has occurred"]
747        pub const _0: Self = Self::new(0);
748
749        #[doc = "An error has occurred"]
750        pub const _1: Self = Self::new(1);
751    }
752    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
753    pub struct Fea_SPEC;
754    pub type Fea = crate::EnumBitfieldStruct<u8, Fea_SPEC>;
755    impl Fea {
756        #[doc = "No error has occurred"]
757        pub const _0: Self = Self::new(0);
758
759        #[doc = "An error has occurred"]
760        pub const _1: Self = Self::new(1);
761    }
762    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
763    pub struct Pea_SPEC;
764    pub type Pea = crate::EnumBitfieldStruct<u8, Pea_SPEC>;
765    impl Pea {
766        #[doc = "No error has occurred"]
767        pub const _0: Self = Self::new(0);
768
769        #[doc = "An error has occurred"]
770        pub const _1: Self = Self::new(1);
771    }
772    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
773    pub struct Txsfa_SPEC;
774    pub type Txsfa = crate::EnumBitfieldStruct<u8, Txsfa_SPEC>;
775    impl Txsfa {
776        #[doc = "Data is not being transmitted"]
777        pub const _0: Self = Self::new(0);
778
779        #[doc = "Data is being transmitted"]
780        pub const _1: Self = Self::new(1);
781    }
782    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
783    pub struct Txbfa_SPEC;
784    pub type Txbfa = crate::EnumBitfieldStruct<u8, Txbfa_SPEC>;
785    impl Txbfa {
786        #[doc = "No valid data exists in the TXBA0 register"]
787        pub const _0: Self = Self::new(0);
788
789        #[doc = "Valid data exists in the TXBA0 register"]
790        pub const _1: Self = Self::new(1);
791    }
792}
793#[doc(hidden)]
794#[derive(Copy, Clone, Eq, PartialEq)]
795pub struct Ascta0_SPEC;
796impl crate::sealed::RegSpec for Ascta0_SPEC {
797    type DataType = u8;
798}
799
800#[doc = "Status Clear Trigger Register 0"]
801pub type Ascta0 = crate::RegValueT<Ascta0_SPEC>;
802
803impl Ascta0 {
804    #[doc = "Overrun Error Flag Clear Trigger"]
805    #[inline(always)]
806    pub fn ovecta(
807        self,
808    ) -> crate::common::RegisterField<
809        0,
810        0x1,
811        1,
812        0,
813        ascta0::Ovecta,
814        ascta0::Ovecta,
815        Ascta0_SPEC,
816        crate::common::RW,
817    > {
818        crate::common::RegisterField::<
819            0,
820            0x1,
821            1,
822            0,
823            ascta0::Ovecta,
824            ascta0::Ovecta,
825            Ascta0_SPEC,
826            crate::common::RW,
827        >::from_register(self, 0)
828    }
829
830    #[doc = "Framing Error Flag Clear Trigger"]
831    #[inline(always)]
832    pub fn fecta(
833        self,
834    ) -> crate::common::RegisterField<
835        1,
836        0x1,
837        1,
838        0,
839        ascta0::Fecta,
840        ascta0::Fecta,
841        Ascta0_SPEC,
842        crate::common::RW,
843    > {
844        crate::common::RegisterField::<
845            1,
846            0x1,
847            1,
848            0,
849            ascta0::Fecta,
850            ascta0::Fecta,
851            Ascta0_SPEC,
852            crate::common::RW,
853        >::from_register(self, 0)
854    }
855
856    #[doc = "Parity Error Flag Clear Trigger"]
857    #[inline(always)]
858    pub fn pecta(
859        self,
860    ) -> crate::common::RegisterField<
861        2,
862        0x1,
863        1,
864        0,
865        ascta0::Pecta,
866        ascta0::Pecta,
867        Ascta0_SPEC,
868        crate::common::RW,
869    > {
870        crate::common::RegisterField::<
871            2,
872            0x1,
873            1,
874            0,
875            ascta0::Pecta,
876            ascta0::Pecta,
877            Ascta0_SPEC,
878            crate::common::RW,
879        >::from_register(self, 0)
880    }
881}
882impl ::core::default::Default for Ascta0 {
883    #[inline(always)]
884    fn default() -> Ascta0 {
885        <crate::RegValueT<Ascta0_SPEC> as RegisterValue<_>>::new(0)
886    }
887}
888pub mod ascta0 {
889
890    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
891    pub struct Ovecta_SPEC;
892    pub type Ovecta = crate::EnumBitfieldStruct<u8, Ovecta_SPEC>;
893    impl Ovecta {
894        #[doc = "Does not clear the ASISA0.OVEA flag (the flag is retained)"]
895        pub const _0: Self = Self::new(0);
896
897        #[doc = "Clears the ASISA0.OVEA flag"]
898        pub const _1: Self = Self::new(1);
899    }
900    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
901    pub struct Fecta_SPEC;
902    pub type Fecta = crate::EnumBitfieldStruct<u8, Fecta_SPEC>;
903    impl Fecta {
904        #[doc = "Does not clear the ASISA0.FEA flag (the flag is retained)"]
905        pub const _0: Self = Self::new(0);
906
907        #[doc = "Clears the ASISA0.FEA flag"]
908        pub const _1: Self = Self::new(1);
909    }
910    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
911    pub struct Pecta_SPEC;
912    pub type Pecta = crate::EnumBitfieldStruct<u8, Pecta_SPEC>;
913    impl Pecta {
914        #[doc = "Does not clear the ASISA0.PEA flag (the flag is retained)"]
915        pub const _0: Self = Self::new(0);
916
917        #[doc = "Clears the ASISA0.PEA flag"]
918        pub const _1: Self = Self::new(1);
919    }
920}
921#[doc(hidden)]
922#[derive(Copy, Clone, Eq, PartialEq)]
923pub struct Uta0Ck_SPEC;
924impl crate::sealed::RegSpec for Uta0Ck_SPEC {
925    type DataType = u8;
926}
927
928#[doc = "UARTA Clock Select Register 0"]
929pub type Uta0Ck = crate::RegValueT<Uta0Ck_SPEC>;
930
931impl Uta0Ck {
932    #[doc = "UARTA0 Operation Clock Select (fUTA0)"]
933    #[inline(always)]
934    pub fn ck(
935        self,
936    ) -> crate::common::RegisterField<
937        0,
938        0xf,
939        1,
940        0,
941        uta0ck::Ck,
942        uta0ck::Ck,
943        Uta0Ck_SPEC,
944        crate::common::RW,
945    > {
946        crate::common::RegisterField::<
947            0,
948            0xf,
949            1,
950            0,
951            uta0ck::Ck,
952            uta0ck::Ck,
953            Uta0Ck_SPEC,
954            crate::common::RW,
955        >::from_register(self, 0)
956    }
957
958    #[doc = "fSEL Clock Select"]
959    #[inline(always)]
960    pub fn sel(
961        self,
962    ) -> crate::common::RegisterField<
963        4,
964        0x3,
965        1,
966        0,
967        uta0ck::Sel,
968        uta0ck::Sel,
969        Uta0Ck_SPEC,
970        crate::common::RW,
971    > {
972        crate::common::RegisterField::<
973            4,
974            0x3,
975            1,
976            0,
977            uta0ck::Sel,
978            uta0ck::Sel,
979            Uta0Ck_SPEC,
980            crate::common::RW,
981        >::from_register(self, 0)
982    }
983}
984impl ::core::default::Default for Uta0Ck {
985    #[inline(always)]
986    fn default() -> Uta0Ck {
987        <crate::RegValueT<Uta0Ck_SPEC> as RegisterValue<_>>::new(0)
988    }
989}
990pub mod uta0ck {
991
992    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
993    pub struct Ck_SPEC;
994    pub type Ck = crate::EnumBitfieldStruct<u8, Ck_SPEC>;
995    impl Ck {
996        #[doc = "fSEL"]
997        pub const _0_X_0: Self = Self::new(0);
998
999        #[doc = "fSEL/2"]
1000        pub const _0_X_1: Self = Self::new(1);
1001
1002        #[doc = "fSEL/4"]
1003        pub const _0_X_2: Self = Self::new(2);
1004
1005        #[doc = "fSEL/8"]
1006        pub const _0_X_3: Self = Self::new(3);
1007
1008        #[doc = "fSEL/16"]
1009        pub const _0_X_4: Self = Self::new(4);
1010
1011        #[doc = "fSEL/32"]
1012        pub const _0_X_5: Self = Self::new(5);
1013
1014        #[doc = "fSEL/64"]
1015        pub const _0_X_6: Self = Self::new(6);
1016
1017        #[doc = "FSXP"]
1018        pub const _0_X_8: Self = Self::new(8);
1019    }
1020    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1021    pub struct Sel_SPEC;
1022    pub type Sel = crate::EnumBitfieldStruct<u8, Sel_SPEC>;
1023    impl Sel {
1024        #[doc = "Stop"]
1025        pub const _00: Self = Self::new(0);
1026
1027        #[doc = "MOSC"]
1028        pub const _01: Self = Self::new(1);
1029
1030        #[doc = "HOCO"]
1031        pub const _10: Self = Self::new(2);
1032
1033        #[doc = "MOCO"]
1034        pub const _11: Self = Self::new(3);
1035    }
1036}
ra0e1_pac/uarta.rs

ra0e1_pac/
uarta.rs
