ra0e1_pac/
tau.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Timer Array Unit"]
28unsafe impl ::core::marker::Send for super::Tau {}
29unsafe impl ::core::marker::Sync for super::Tau {}
30impl super::Tau {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Timer Data Register 00"]
38    #[inline(always)]
39    pub const fn tdr00(&self) -> &'static crate::common::Reg<self::Tdr00_SPEC, crate::common::RW> {
40        unsafe {
41            crate::common::Reg::<self::Tdr00_SPEC, crate::common::RW>::from_ptr(
42                self._svd2pac_as_ptr().add(0usize),
43            )
44        }
45    }
46
47    #[doc = "Timer Data Register 01"]
48    #[inline(always)]
49    pub const fn tdr01(&self) -> &'static crate::common::Reg<self::Tdr01_SPEC, crate::common::RW> {
50        unsafe {
51            crate::common::Reg::<self::Tdr01_SPEC, crate::common::RW>::from_ptr(
52                self._svd2pac_as_ptr().add(2usize),
53            )
54        }
55    }
56
57    #[doc = "Timer Data Register 01"]
58    #[inline(always)]
59    pub const fn tdr01l(
60        &self,
61    ) -> &'static crate::common::Reg<self::Tdr01L_SPEC, crate::common::RW> {
62        unsafe {
63            crate::common::Reg::<self::Tdr01L_SPEC, crate::common::RW>::from_ptr(
64                self._svd2pac_as_ptr().add(2usize),
65            )
66        }
67    }
68
69    #[doc = "Timer Data Register 01"]
70    #[inline(always)]
71    pub const fn tdr01h(
72        &self,
73    ) -> &'static crate::common::Reg<self::Tdr01H_SPEC, crate::common::RW> {
74        unsafe {
75            crate::common::Reg::<self::Tdr01H_SPEC, crate::common::RW>::from_ptr(
76                self._svd2pac_as_ptr().add(3usize),
77            )
78        }
79    }
80
81    #[doc = "Timer Data Register 02"]
82    #[inline(always)]
83    pub const fn tdr02(&self) -> &'static crate::common::Reg<self::Tdr02_SPEC, crate::common::RW> {
84        unsafe {
85            crate::common::Reg::<self::Tdr02_SPEC, crate::common::RW>::from_ptr(
86                self._svd2pac_as_ptr().add(4usize),
87            )
88        }
89    }
90
91    #[doc = "Timer Data Register 03"]
92    #[inline(always)]
93    pub const fn tdr03(&self) -> &'static crate::common::Reg<self::Tdr03_SPEC, crate::common::RW> {
94        unsafe {
95            crate::common::Reg::<self::Tdr03_SPEC, crate::common::RW>::from_ptr(
96                self._svd2pac_as_ptr().add(6usize),
97            )
98        }
99    }
100
101    #[doc = "Timer Data Register 03"]
102    #[inline(always)]
103    pub const fn tdr03l(
104        &self,
105    ) -> &'static crate::common::Reg<self::Tdr03L_SPEC, crate::common::RW> {
106        unsafe {
107            crate::common::Reg::<self::Tdr03L_SPEC, crate::common::RW>::from_ptr(
108                self._svd2pac_as_ptr().add(6usize),
109            )
110        }
111    }
112
113    #[doc = "Timer Data Register 03"]
114    #[inline(always)]
115    pub const fn tdr03h(
116        &self,
117    ) -> &'static crate::common::Reg<self::Tdr03H_SPEC, crate::common::RW> {
118        unsafe {
119            crate::common::Reg::<self::Tdr03H_SPEC, crate::common::RW>::from_ptr(
120                self._svd2pac_as_ptr().add(7usize),
121            )
122        }
123    }
124
125    #[doc = "Timer Data Register 04"]
126    #[inline(always)]
127    pub const fn tdr04(&self) -> &'static crate::common::Reg<self::Tdr04_SPEC, crate::common::RW> {
128        unsafe {
129            crate::common::Reg::<self::Tdr04_SPEC, crate::common::RW>::from_ptr(
130                self._svd2pac_as_ptr().add(8usize),
131            )
132        }
133    }
134
135    #[doc = "Timer Data Register 05"]
136    #[inline(always)]
137    pub const fn tdr05(&self) -> &'static crate::common::Reg<self::Tdr05_SPEC, crate::common::RW> {
138        unsafe {
139            crate::common::Reg::<self::Tdr05_SPEC, crate::common::RW>::from_ptr(
140                self._svd2pac_as_ptr().add(10usize),
141            )
142        }
143    }
144
145    #[doc = "Timer Data Register 06"]
146    #[inline(always)]
147    pub const fn tdr06(&self) -> &'static crate::common::Reg<self::Tdr06_SPEC, crate::common::RW> {
148        unsafe {
149            crate::common::Reg::<self::Tdr06_SPEC, crate::common::RW>::from_ptr(
150                self._svd2pac_as_ptr().add(12usize),
151            )
152        }
153    }
154
155    #[doc = "Timer Data Register 07"]
156    #[inline(always)]
157    pub const fn tdr07(&self) -> &'static crate::common::Reg<self::Tdr07_SPEC, crate::common::RW> {
158        unsafe {
159            crate::common::Reg::<self::Tdr07_SPEC, crate::common::RW>::from_ptr(
160                self._svd2pac_as_ptr().add(14usize),
161            )
162        }
163    }
164
165    #[doc = "Timer Counter Register 0%s"]
166    #[inline(always)]
167    pub const fn tcr0(
168        &self,
169    ) -> &'static crate::common::ClusterRegisterArray<
170        crate::common::Reg<self::Tcr0_SPEC, crate::common::R>,
171        8,
172        0x2,
173    > {
174        unsafe {
175            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x100usize))
176        }
177    }
178    #[inline(always)]
179    pub const fn tcr00(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
180        unsafe {
181            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
182                self._svd2pac_as_ptr().add(0x100usize),
183            )
184        }
185    }
186    #[inline(always)]
187    pub const fn tcr01(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
188        unsafe {
189            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
190                self._svd2pac_as_ptr().add(0x102usize),
191            )
192        }
193    }
194    #[inline(always)]
195    pub const fn tcr02(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
196        unsafe {
197            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
198                self._svd2pac_as_ptr().add(0x104usize),
199            )
200        }
201    }
202    #[inline(always)]
203    pub const fn tcr03(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
204        unsafe {
205            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
206                self._svd2pac_as_ptr().add(0x106usize),
207            )
208        }
209    }
210    #[inline(always)]
211    pub const fn tcr04(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
212        unsafe {
213            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
214                self._svd2pac_as_ptr().add(0x108usize),
215            )
216        }
217    }
218    #[inline(always)]
219    pub const fn tcr05(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
220        unsafe {
221            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
222                self._svd2pac_as_ptr().add(0x10ausize),
223            )
224        }
225    }
226    #[inline(always)]
227    pub const fn tcr06(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
228        unsafe {
229            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
230                self._svd2pac_as_ptr().add(0x10cusize),
231            )
232        }
233    }
234    #[inline(always)]
235    pub const fn tcr07(&self) -> &'static crate::common::Reg<self::Tcr0_SPEC, crate::common::R> {
236        unsafe {
237            crate::common::Reg::<self::Tcr0_SPEC, crate::common::R>::from_ptr(
238                self._svd2pac_as_ptr().add(0x10eusize),
239            )
240        }
241    }
242
243    #[doc = "Timer Mode Register 00"]
244    #[inline(always)]
245    pub const fn tmr00(&self) -> &'static crate::common::Reg<self::Tmr00_SPEC, crate::common::RW> {
246        unsafe {
247            crate::common::Reg::<self::Tmr00_SPEC, crate::common::RW>::from_ptr(
248                self._svd2pac_as_ptr().add(272usize),
249            )
250        }
251    }
252
253    #[doc = "Timer Mode Register 01"]
254    #[inline(always)]
255    pub const fn tmr01(&self) -> &'static crate::common::Reg<self::Tmr01_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Tmr01_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(274usize),
259            )
260        }
261    }
262
263    #[doc = "Timer Mode Register 02"]
264    #[inline(always)]
265    pub const fn tmr02(&self) -> &'static crate::common::Reg<self::Tmr02_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::Tmr02_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(276usize),
269            )
270        }
271    }
272
273    #[doc = "Timer Mode Register 03"]
274    #[inline(always)]
275    pub const fn tmr03(&self) -> &'static crate::common::Reg<self::Tmr03_SPEC, crate::common::RW> {
276        unsafe {
277            crate::common::Reg::<self::Tmr03_SPEC, crate::common::RW>::from_ptr(
278                self._svd2pac_as_ptr().add(278usize),
279            )
280        }
281    }
282
283    #[doc = "Timer Mode Register 04"]
284    #[inline(always)]
285    pub const fn tmr04(&self) -> &'static crate::common::Reg<self::Tmr04_SPEC, crate::common::RW> {
286        unsafe {
287            crate::common::Reg::<self::Tmr04_SPEC, crate::common::RW>::from_ptr(
288                self._svd2pac_as_ptr().add(280usize),
289            )
290        }
291    }
292
293    #[doc = "Timer Mode Register 05"]
294    #[inline(always)]
295    pub const fn tmr05(&self) -> &'static crate::common::Reg<self::Tmr05_SPEC, crate::common::RW> {
296        unsafe {
297            crate::common::Reg::<self::Tmr05_SPEC, crate::common::RW>::from_ptr(
298                self._svd2pac_as_ptr().add(282usize),
299            )
300        }
301    }
302
303    #[doc = "Timer Mode Register 06"]
304    #[inline(always)]
305    pub const fn tmr06(&self) -> &'static crate::common::Reg<self::Tmr06_SPEC, crate::common::RW> {
306        unsafe {
307            crate::common::Reg::<self::Tmr06_SPEC, crate::common::RW>::from_ptr(
308                self._svd2pac_as_ptr().add(284usize),
309            )
310        }
311    }
312
313    #[doc = "Timer Mode Register 07"]
314    #[inline(always)]
315    pub const fn tmr07(&self) -> &'static crate::common::Reg<self::Tmr07_SPEC, crate::common::RW> {
316        unsafe {
317            crate::common::Reg::<self::Tmr07_SPEC, crate::common::RW>::from_ptr(
318                self._svd2pac_as_ptr().add(286usize),
319            )
320        }
321    }
322
323    #[doc = "Timer Status Register 0%s"]
324    #[inline(always)]
325    pub const fn tsr0(
326        &self,
327    ) -> &'static crate::common::ClusterRegisterArray<
328        crate::common::Reg<self::Tsr0_SPEC, crate::common::R>,
329        8,
330        0x2,
331    > {
332        unsafe {
333            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x120usize))
334        }
335    }
336    #[inline(always)]
337    pub const fn tsr00(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
338        unsafe {
339            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
340                self._svd2pac_as_ptr().add(0x120usize),
341            )
342        }
343    }
344    #[inline(always)]
345    pub const fn tsr01(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
346        unsafe {
347            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
348                self._svd2pac_as_ptr().add(0x122usize),
349            )
350        }
351    }
352    #[inline(always)]
353    pub const fn tsr02(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
354        unsafe {
355            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
356                self._svd2pac_as_ptr().add(0x124usize),
357            )
358        }
359    }
360    #[inline(always)]
361    pub const fn tsr03(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
362        unsafe {
363            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
364                self._svd2pac_as_ptr().add(0x126usize),
365            )
366        }
367    }
368    #[inline(always)]
369    pub const fn tsr04(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
370        unsafe {
371            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
372                self._svd2pac_as_ptr().add(0x128usize),
373            )
374        }
375    }
376    #[inline(always)]
377    pub const fn tsr05(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
378        unsafe {
379            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
380                self._svd2pac_as_ptr().add(0x12ausize),
381            )
382        }
383    }
384    #[inline(always)]
385    pub const fn tsr06(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
386        unsafe {
387            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
388                self._svd2pac_as_ptr().add(0x12cusize),
389            )
390        }
391    }
392    #[inline(always)]
393    pub const fn tsr07(&self) -> &'static crate::common::Reg<self::Tsr0_SPEC, crate::common::R> {
394        unsafe {
395            crate::common::Reg::<self::Tsr0_SPEC, crate::common::R>::from_ptr(
396                self._svd2pac_as_ptr().add(0x12eusize),
397            )
398        }
399    }
400
401    #[doc = "Timer Channel Enable Status Register 0"]
402    #[inline(always)]
403    pub const fn te0(&self) -> &'static crate::common::Reg<self::Te0_SPEC, crate::common::R> {
404        unsafe {
405            crate::common::Reg::<self::Te0_SPEC, crate::common::R>::from_ptr(
406                self._svd2pac_as_ptr().add(304usize),
407            )
408        }
409    }
410
411    #[doc = "Timer Channel Start Register 0"]
412    #[inline(always)]
413    pub const fn ts0(&self) -> &'static crate::common::Reg<self::Ts0_SPEC, crate::common::RW> {
414        unsafe {
415            crate::common::Reg::<self::Ts0_SPEC, crate::common::RW>::from_ptr(
416                self._svd2pac_as_ptr().add(306usize),
417            )
418        }
419    }
420
421    #[doc = "Timer Channel Stop Register 0"]
422    #[inline(always)]
423    pub const fn tt0(&self) -> &'static crate::common::Reg<self::Tt0_SPEC, crate::common::RW> {
424        unsafe {
425            crate::common::Reg::<self::Tt0_SPEC, crate::common::RW>::from_ptr(
426                self._svd2pac_as_ptr().add(308usize),
427            )
428        }
429    }
430
431    #[doc = "Timer Clock Select Register 0"]
432    #[inline(always)]
433    pub const fn tps0(&self) -> &'static crate::common::Reg<self::Tps0_SPEC, crate::common::RW> {
434        unsafe {
435            crate::common::Reg::<self::Tps0_SPEC, crate::common::RW>::from_ptr(
436                self._svd2pac_as_ptr().add(310usize),
437            )
438        }
439    }
440
441    #[doc = "Timer Output Register 0"]
442    #[inline(always)]
443    pub const fn to0(&self) -> &'static crate::common::Reg<self::To0_SPEC, crate::common::RW> {
444        unsafe {
445            crate::common::Reg::<self::To0_SPEC, crate::common::RW>::from_ptr(
446                self._svd2pac_as_ptr().add(312usize),
447            )
448        }
449    }
450
451    #[doc = "Timer Output Enable Register 0"]
452    #[inline(always)]
453    pub const fn toe0(&self) -> &'static crate::common::Reg<self::Toe0_SPEC, crate::common::RW> {
454        unsafe {
455            crate::common::Reg::<self::Toe0_SPEC, crate::common::RW>::from_ptr(
456                self._svd2pac_as_ptr().add(314usize),
457            )
458        }
459    }
460
461    #[doc = "Timer Output Level Register 0"]
462    #[inline(always)]
463    pub const fn tol0(&self) -> &'static crate::common::Reg<self::Tol0_SPEC, crate::common::RW> {
464        unsafe {
465            crate::common::Reg::<self::Tol0_SPEC, crate::common::RW>::from_ptr(
466                self._svd2pac_as_ptr().add(316usize),
467            )
468        }
469    }
470
471    #[doc = "Timer Output Mode Register 0"]
472    #[inline(always)]
473    pub const fn tom0(&self) -> &'static crate::common::Reg<self::Tom0_SPEC, crate::common::RW> {
474        unsafe {
475            crate::common::Reg::<self::Tom0_SPEC, crate::common::RW>::from_ptr(
476                self._svd2pac_as_ptr().add(318usize),
477            )
478        }
479    }
480}
481#[doc(hidden)]
482#[derive(Copy, Clone, Eq, PartialEq)]
483pub struct Tdr00_SPEC;
484impl crate::sealed::RegSpec for Tdr00_SPEC {
485    type DataType = u16;
486}
487
488#[doc = "Timer Data Register 00"]
489pub type Tdr00 = crate::RegValueT<Tdr00_SPEC>;
490
491impl NoBitfieldReg<Tdr00_SPEC> for Tdr00 {}
492impl ::core::default::Default for Tdr00 {
493    #[inline(always)]
494    fn default() -> Tdr00 {
495        <crate::RegValueT<Tdr00_SPEC> as RegisterValue<_>>::new(0)
496    }
497}
498
499#[doc(hidden)]
500#[derive(Copy, Clone, Eq, PartialEq)]
501pub struct Tdr01_SPEC;
502impl crate::sealed::RegSpec for Tdr01_SPEC {
503    type DataType = u16;
504}
505
506#[doc = "Timer Data Register 01"]
507pub type Tdr01 = crate::RegValueT<Tdr01_SPEC>;
508
509impl NoBitfieldReg<Tdr01_SPEC> for Tdr01 {}
510impl ::core::default::Default for Tdr01 {
511    #[inline(always)]
512    fn default() -> Tdr01 {
513        <crate::RegValueT<Tdr01_SPEC> as RegisterValue<_>>::new(0)
514    }
515}
516
517#[doc(hidden)]
518#[derive(Copy, Clone, Eq, PartialEq)]
519pub struct Tdr01L_SPEC;
520impl crate::sealed::RegSpec for Tdr01L_SPEC {
521    type DataType = u8;
522}
523
524#[doc = "Timer Data Register 01"]
525pub type Tdr01L = crate::RegValueT<Tdr01L_SPEC>;
526
527impl NoBitfieldReg<Tdr01L_SPEC> for Tdr01L {}
528impl ::core::default::Default for Tdr01L {
529    #[inline(always)]
530    fn default() -> Tdr01L {
531        <crate::RegValueT<Tdr01L_SPEC> as RegisterValue<_>>::new(0)
532    }
533}
534
535#[doc(hidden)]
536#[derive(Copy, Clone, Eq, PartialEq)]
537pub struct Tdr01H_SPEC;
538impl crate::sealed::RegSpec for Tdr01H_SPEC {
539    type DataType = u8;
540}
541
542#[doc = "Timer Data Register 01"]
543pub type Tdr01H = crate::RegValueT<Tdr01H_SPEC>;
544
545impl NoBitfieldReg<Tdr01H_SPEC> for Tdr01H {}
546impl ::core::default::Default for Tdr01H {
547    #[inline(always)]
548    fn default() -> Tdr01H {
549        <crate::RegValueT<Tdr01H_SPEC> as RegisterValue<_>>::new(0)
550    }
551}
552
553#[doc(hidden)]
554#[derive(Copy, Clone, Eq, PartialEq)]
555pub struct Tdr02_SPEC;
556impl crate::sealed::RegSpec for Tdr02_SPEC {
557    type DataType = u16;
558}
559
560#[doc = "Timer Data Register 02"]
561pub type Tdr02 = crate::RegValueT<Tdr02_SPEC>;
562
563impl NoBitfieldReg<Tdr02_SPEC> for Tdr02 {}
564impl ::core::default::Default for Tdr02 {
565    #[inline(always)]
566    fn default() -> Tdr02 {
567        <crate::RegValueT<Tdr02_SPEC> as RegisterValue<_>>::new(0)
568    }
569}
570
571#[doc(hidden)]
572#[derive(Copy, Clone, Eq, PartialEq)]
573pub struct Tdr03_SPEC;
574impl crate::sealed::RegSpec for Tdr03_SPEC {
575    type DataType = u16;
576}
577
578#[doc = "Timer Data Register 03"]
579pub type Tdr03 = crate::RegValueT<Tdr03_SPEC>;
580
581impl NoBitfieldReg<Tdr03_SPEC> for Tdr03 {}
582impl ::core::default::Default for Tdr03 {
583    #[inline(always)]
584    fn default() -> Tdr03 {
585        <crate::RegValueT<Tdr03_SPEC> as RegisterValue<_>>::new(0)
586    }
587}
588
589#[doc(hidden)]
590#[derive(Copy, Clone, Eq, PartialEq)]
591pub struct Tdr03L_SPEC;
592impl crate::sealed::RegSpec for Tdr03L_SPEC {
593    type DataType = u8;
594}
595
596#[doc = "Timer Data Register 03"]
597pub type Tdr03L = crate::RegValueT<Tdr03L_SPEC>;
598
599impl NoBitfieldReg<Tdr03L_SPEC> for Tdr03L {}
600impl ::core::default::Default for Tdr03L {
601    #[inline(always)]
602    fn default() -> Tdr03L {
603        <crate::RegValueT<Tdr03L_SPEC> as RegisterValue<_>>::new(0)
604    }
605}
606
607#[doc(hidden)]
608#[derive(Copy, Clone, Eq, PartialEq)]
609pub struct Tdr03H_SPEC;
610impl crate::sealed::RegSpec for Tdr03H_SPEC {
611    type DataType = u8;
612}
613
614#[doc = "Timer Data Register 03"]
615pub type Tdr03H = crate::RegValueT<Tdr03H_SPEC>;
616
617impl NoBitfieldReg<Tdr03H_SPEC> for Tdr03H {}
618impl ::core::default::Default for Tdr03H {
619    #[inline(always)]
620    fn default() -> Tdr03H {
621        <crate::RegValueT<Tdr03H_SPEC> as RegisterValue<_>>::new(0)
622    }
623}
624
625#[doc(hidden)]
626#[derive(Copy, Clone, Eq, PartialEq)]
627pub struct Tdr04_SPEC;
628impl crate::sealed::RegSpec for Tdr04_SPEC {
629    type DataType = u16;
630}
631
632#[doc = "Timer Data Register 04"]
633pub type Tdr04 = crate::RegValueT<Tdr04_SPEC>;
634
635impl NoBitfieldReg<Tdr04_SPEC> for Tdr04 {}
636impl ::core::default::Default for Tdr04 {
637    #[inline(always)]
638    fn default() -> Tdr04 {
639        <crate::RegValueT<Tdr04_SPEC> as RegisterValue<_>>::new(0)
640    }
641}
642
643#[doc(hidden)]
644#[derive(Copy, Clone, Eq, PartialEq)]
645pub struct Tdr05_SPEC;
646impl crate::sealed::RegSpec for Tdr05_SPEC {
647    type DataType = u16;
648}
649
650#[doc = "Timer Data Register 05"]
651pub type Tdr05 = crate::RegValueT<Tdr05_SPEC>;
652
653impl NoBitfieldReg<Tdr05_SPEC> for Tdr05 {}
654impl ::core::default::Default for Tdr05 {
655    #[inline(always)]
656    fn default() -> Tdr05 {
657        <crate::RegValueT<Tdr05_SPEC> as RegisterValue<_>>::new(0)
658    }
659}
660
661#[doc(hidden)]
662#[derive(Copy, Clone, Eq, PartialEq)]
663pub struct Tdr06_SPEC;
664impl crate::sealed::RegSpec for Tdr06_SPEC {
665    type DataType = u16;
666}
667
668#[doc = "Timer Data Register 06"]
669pub type Tdr06 = crate::RegValueT<Tdr06_SPEC>;
670
671impl NoBitfieldReg<Tdr06_SPEC> for Tdr06 {}
672impl ::core::default::Default for Tdr06 {
673    #[inline(always)]
674    fn default() -> Tdr06 {
675        <crate::RegValueT<Tdr06_SPEC> as RegisterValue<_>>::new(0)
676    }
677}
678
679#[doc(hidden)]
680#[derive(Copy, Clone, Eq, PartialEq)]
681pub struct Tdr07_SPEC;
682impl crate::sealed::RegSpec for Tdr07_SPEC {
683    type DataType = u16;
684}
685
686#[doc = "Timer Data Register 07"]
687pub type Tdr07 = crate::RegValueT<Tdr07_SPEC>;
688
689impl NoBitfieldReg<Tdr07_SPEC> for Tdr07 {}
690impl ::core::default::Default for Tdr07 {
691    #[inline(always)]
692    fn default() -> Tdr07 {
693        <crate::RegValueT<Tdr07_SPEC> as RegisterValue<_>>::new(0)
694    }
695}
696
697#[doc(hidden)]
698#[derive(Copy, Clone, Eq, PartialEq)]
699pub struct Tcr0_SPEC;
700impl crate::sealed::RegSpec for Tcr0_SPEC {
701    type DataType = u16;
702}
703
704#[doc = "Timer Counter Register 0%s"]
705pub type Tcr0 = crate::RegValueT<Tcr0_SPEC>;
706
707impl NoBitfieldReg<Tcr0_SPEC> for Tcr0 {}
708impl ::core::default::Default for Tcr0 {
709    #[inline(always)]
710    fn default() -> Tcr0 {
711        <crate::RegValueT<Tcr0_SPEC> as RegisterValue<_>>::new(65535)
712    }
713}
714
715#[doc(hidden)]
716#[derive(Copy, Clone, Eq, PartialEq)]
717pub struct Tmr00_SPEC;
718impl crate::sealed::RegSpec for Tmr00_SPEC {
719    type DataType = u16;
720}
721
722#[doc = "Timer Mode Register 00"]
723pub type Tmr00 = crate::RegValueT<Tmr00_SPEC>;
724
725impl Tmr00 {
726    #[doc = "Setting of Starting Count and Interrupt"]
727    #[inline(always)]
728    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr00_SPEC, crate::common::RW> {
729        crate::common::RegisterFieldBool::<0, 1, 0, Tmr00_SPEC, crate::common::RW>::from_register(
730            self, 0,
731        )
732    }
733
734    #[doc = "Selection of Operation Mode at Channel n"]
735    #[inline(always)]
736    pub fn md(
737        self,
738    ) -> crate::common::RegisterField<
739        1,
740        0x7,
741        1,
742        0,
743        tmr00::Md,
744        tmr00::Md,
745        Tmr00_SPEC,
746        crate::common::RW,
747    > {
748        crate::common::RegisterField::<
749            1,
750            0x7,
751            1,
752            0,
753            tmr00::Md,
754            tmr00::Md,
755            Tmr00_SPEC,
756            crate::common::RW,
757        >::from_register(self, 0)
758    }
759
760    #[doc = "Selection of TI0n Pin Input Valid Edge"]
761    #[inline(always)]
762    pub fn cis(
763        self,
764    ) -> crate::common::RegisterField<
765        6,
766        0x3,
767        1,
768        0,
769        tmr00::Cis,
770        tmr00::Cis,
771        Tmr00_SPEC,
772        crate::common::RW,
773    > {
774        crate::common::RegisterField::<
775            6,
776            0x3,
777            1,
778            0,
779            tmr00::Cis,
780            tmr00::Cis,
781            Tmr00_SPEC,
782            crate::common::RW,
783        >::from_register(self, 0)
784    }
785
786    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
787    #[inline(always)]
788    pub fn sts(
789        self,
790    ) -> crate::common::RegisterField<
791        8,
792        0x7,
793        1,
794        0,
795        tmr00::Sts,
796        tmr00::Sts,
797        Tmr00_SPEC,
798        crate::common::RW,
799    > {
800        crate::common::RegisterField::<
801            8,
802            0x7,
803            1,
804            0,
805            tmr00::Sts,
806            tmr00::Sts,
807            Tmr00_SPEC,
808            crate::common::RW,
809        >::from_register(self, 0)
810    }
811
812    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
813    #[inline(always)]
814    pub fn ccs(
815        self,
816    ) -> crate::common::RegisterField<
817        12,
818        0x1,
819        1,
820        0,
821        tmr00::Ccs,
822        tmr00::Ccs,
823        Tmr00_SPEC,
824        crate::common::RW,
825    > {
826        crate::common::RegisterField::<
827            12,
828            0x1,
829            1,
830            0,
831            tmr00::Ccs,
832            tmr00::Ccs,
833            Tmr00_SPEC,
834            crate::common::RW,
835        >::from_register(self, 0)
836    }
837
838    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
839    #[inline(always)]
840    pub fn cks(
841        self,
842    ) -> crate::common::RegisterField<
843        14,
844        0x3,
845        1,
846        0,
847        tmr00::Cks,
848        tmr00::Cks,
849        Tmr00_SPEC,
850        crate::common::RW,
851    > {
852        crate::common::RegisterField::<
853            14,
854            0x3,
855            1,
856            0,
857            tmr00::Cks,
858            tmr00::Cks,
859            Tmr00_SPEC,
860            crate::common::RW,
861        >::from_register(self, 0)
862    }
863}
864impl ::core::default::Default for Tmr00 {
865    #[inline(always)]
866    fn default() -> Tmr00 {
867        <crate::RegValueT<Tmr00_SPEC> as RegisterValue<_>>::new(0)
868    }
869}
870pub mod tmr00 {
871
872    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
873    pub struct Md_SPEC;
874    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
875    impl Md {
876        #[doc = "Interval timer mode"]
877        pub const _000: Self = Self::new(0);
878
879        #[doc = "Capture mode"]
880        pub const _010: Self = Self::new(2);
881
882        #[doc = "Event counter mode"]
883        pub const _011: Self = Self::new(3);
884
885        #[doc = "One-count mode"]
886        pub const _100: Self = Self::new(4);
887
888        #[doc = "Capture and one-count mode"]
889        pub const _110: Self = Self::new(6);
890    }
891    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
892    pub struct Cis_SPEC;
893    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
894    impl Cis {
895        #[doc = "Falling edge"]
896        pub const _00: Self = Self::new(0);
897
898        #[doc = "Rising edge"]
899        pub const _01: Self = Self::new(1);
900
901        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
902        pub const _10: Self = Self::new(2);
903
904        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
905        pub const _11: Self = Self::new(3);
906    }
907    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
908    pub struct Sts_SPEC;
909    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
910    impl Sts {
911        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
912        pub const _000: Self = Self::new(0);
913
914        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
915        pub const _001: Self = Self::new(1);
916
917        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
918        pub const _010: Self = Self::new(2);
919
920        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
921        pub const _100: Self = Self::new(4);
922    }
923    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
924    pub struct Ccs_SPEC;
925    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
926    impl Ccs {
927        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
928        pub const _0: Self = Self::new(0);
929
930        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
931        pub const _1: Self = Self::new(1);
932    }
933    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
934    pub struct Cks_SPEC;
935    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
936    impl Cks {
937        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
938        pub const _00: Self = Self::new(0);
939
940        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
941        pub const _01: Self = Self::new(1);
942
943        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
944        pub const _10: Self = Self::new(2);
945
946        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
947        pub const _11: Self = Self::new(3);
948    }
949}
950#[doc(hidden)]
951#[derive(Copy, Clone, Eq, PartialEq)]
952pub struct Tmr01_SPEC;
953impl crate::sealed::RegSpec for Tmr01_SPEC {
954    type DataType = u16;
955}
956
957#[doc = "Timer Mode Register 01"]
958pub type Tmr01 = crate::RegValueT<Tmr01_SPEC>;
959
960impl Tmr01 {
961    #[doc = "Setting of Starting Count and Interrupt"]
962    #[inline(always)]
963    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr01_SPEC, crate::common::RW> {
964        crate::common::RegisterFieldBool::<0, 1, 0, Tmr01_SPEC, crate::common::RW>::from_register(
965            self, 0,
966        )
967    }
968
969    #[doc = "Selection of Operation Mode at Channel n"]
970    #[inline(always)]
971    pub fn md(
972        self,
973    ) -> crate::common::RegisterField<
974        1,
975        0x7,
976        1,
977        0,
978        tmr01::Md,
979        tmr01::Md,
980        Tmr01_SPEC,
981        crate::common::RW,
982    > {
983        crate::common::RegisterField::<
984            1,
985            0x7,
986            1,
987            0,
988            tmr01::Md,
989            tmr01::Md,
990            Tmr01_SPEC,
991            crate::common::RW,
992        >::from_register(self, 0)
993    }
994
995    #[doc = "Selection of TI0n Pin Input Valid Edge"]
996    #[inline(always)]
997    pub fn cis(
998        self,
999    ) -> crate::common::RegisterField<
1000        6,
1001        0x3,
1002        1,
1003        0,
1004        tmr01::Cis,
1005        tmr01::Cis,
1006        Tmr01_SPEC,
1007        crate::common::RW,
1008    > {
1009        crate::common::RegisterField::<
1010            6,
1011            0x3,
1012            1,
1013            0,
1014            tmr01::Cis,
1015            tmr01::Cis,
1016            Tmr01_SPEC,
1017            crate::common::RW,
1018        >::from_register(self, 0)
1019    }
1020
1021    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
1022    #[inline(always)]
1023    pub fn sts(
1024        self,
1025    ) -> crate::common::RegisterField<
1026        8,
1027        0x7,
1028        1,
1029        0,
1030        tmr01::Sts,
1031        tmr01::Sts,
1032        Tmr01_SPEC,
1033        crate::common::RW,
1034    > {
1035        crate::common::RegisterField::<
1036            8,
1037            0x7,
1038            1,
1039            0,
1040            tmr01::Sts,
1041            tmr01::Sts,
1042            Tmr01_SPEC,
1043            crate::common::RW,
1044        >::from_register(self, 0)
1045    }
1046
1047    #[doc = "Selection of 8 or 16-bit Timer Operation for Channels 1 and 3"]
1048    #[inline(always)]
1049    pub fn split(
1050        self,
1051    ) -> crate::common::RegisterField<
1052        11,
1053        0x1,
1054        1,
1055        0,
1056        tmr01::Split,
1057        tmr01::Split,
1058        Tmr01_SPEC,
1059        crate::common::RW,
1060    > {
1061        crate::common::RegisterField::<
1062            11,
1063            0x1,
1064            1,
1065            0,
1066            tmr01::Split,
1067            tmr01::Split,
1068            Tmr01_SPEC,
1069            crate::common::RW,
1070        >::from_register(self, 0)
1071    }
1072
1073    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
1074    #[inline(always)]
1075    pub fn ccs(
1076        self,
1077    ) -> crate::common::RegisterField<
1078        12,
1079        0x1,
1080        1,
1081        0,
1082        tmr01::Ccs,
1083        tmr01::Ccs,
1084        Tmr01_SPEC,
1085        crate::common::RW,
1086    > {
1087        crate::common::RegisterField::<
1088            12,
1089            0x1,
1090            1,
1091            0,
1092            tmr01::Ccs,
1093            tmr01::Ccs,
1094            Tmr01_SPEC,
1095            crate::common::RW,
1096        >::from_register(self, 0)
1097    }
1098
1099    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1100    #[inline(always)]
1101    pub fn cks(
1102        self,
1103    ) -> crate::common::RegisterField<
1104        14,
1105        0x3,
1106        1,
1107        0,
1108        tmr01::Cks,
1109        tmr01::Cks,
1110        Tmr01_SPEC,
1111        crate::common::RW,
1112    > {
1113        crate::common::RegisterField::<
1114            14,
1115            0x3,
1116            1,
1117            0,
1118            tmr01::Cks,
1119            tmr01::Cks,
1120            Tmr01_SPEC,
1121            crate::common::RW,
1122        >::from_register(self, 0)
1123    }
1124}
1125impl ::core::default::Default for Tmr01 {
1126    #[inline(always)]
1127    fn default() -> Tmr01 {
1128        <crate::RegValueT<Tmr01_SPEC> as RegisterValue<_>>::new(0)
1129    }
1130}
1131pub mod tmr01 {
1132
1133    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1134    pub struct Md_SPEC;
1135    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
1136    impl Md {
1137        #[doc = "Interval timer mode"]
1138        pub const _000: Self = Self::new(0);
1139
1140        #[doc = "Capture mode"]
1141        pub const _010: Self = Self::new(2);
1142
1143        #[doc = "Event counter mode"]
1144        pub const _011: Self = Self::new(3);
1145
1146        #[doc = "One-count mode"]
1147        pub const _100: Self = Self::new(4);
1148
1149        #[doc = "Capture & one-count mode"]
1150        pub const _110: Self = Self::new(6);
1151    }
1152    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1153    pub struct Cis_SPEC;
1154    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
1155    impl Cis {
1156        #[doc = "Falling edge"]
1157        pub const _00: Self = Self::new(0);
1158
1159        #[doc = "Rising edge"]
1160        pub const _01: Self = Self::new(1);
1161
1162        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
1163        pub const _10: Self = Self::new(2);
1164
1165        #[doc = "Both edges (when high-level width is measured) Start trigger: Rising edge, Capture trigger: Falling edge"]
1166        pub const _11: Self = Self::new(3);
1167    }
1168    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1169    pub struct Sts_SPEC;
1170    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1171    impl Sts {
1172        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
1173        pub const _000: Self = Self::new(0);
1174
1175        #[doc = "Valid edge of the Ti0n pin input is used as both the start trigger and capture trigger."]
1176        pub const _001: Self = Self::new(1);
1177
1178        #[doc = "Both the edges of the Ti0n pin input are used as a start trigger and a capture trigger."]
1179        pub const _010: Self = Self::new(2);
1180
1181        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
1182        pub const _100: Self = Self::new(4);
1183    }
1184    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1185    pub struct Split_SPEC;
1186    pub type Split = crate::EnumBitfieldStruct<u8, Split_SPEC>;
1187    impl Split {
1188        #[doc = "Operates as 16-bit timer (Operates in independent channel operation function or as slave channel in simultaneous channel operation function.)"]
1189        pub const _0: Self = Self::new(0);
1190
1191        #[doc = "Operates as 8-bit timer"]
1192        pub const _1: Self = Self::new(1);
1193    }
1194    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1195    pub struct Ccs_SPEC;
1196    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1197    impl Ccs {
1198        #[doc = "Operating clock (fMCK) specified by the CKS\\[1:0\\] bits"]
1199        pub const _0: Self = Self::new(0);
1200
1201        #[doc = "Valid edge of input signal input from the Ti0n pin In the case of unit 0: In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
1202        pub const _1: Self = Self::new(1);
1203    }
1204    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1205    pub struct Cks_SPEC;
1206    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1207    impl Cks {
1208        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
1209        pub const _00: Self = Self::new(0);
1210
1211        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
1212        pub const _01: Self = Self::new(1);
1213
1214        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
1215        pub const _10: Self = Self::new(2);
1216
1217        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
1218        pub const _11: Self = Self::new(3);
1219    }
1220}
1221#[doc(hidden)]
1222#[derive(Copy, Clone, Eq, PartialEq)]
1223pub struct Tmr02_SPEC;
1224impl crate::sealed::RegSpec for Tmr02_SPEC {
1225    type DataType = u16;
1226}
1227
1228#[doc = "Timer Mode Register 02"]
1229pub type Tmr02 = crate::RegValueT<Tmr02_SPEC>;
1230
1231impl Tmr02 {
1232    #[doc = "Setting of Starting Count and Interrupt"]
1233    #[inline(always)]
1234    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr02_SPEC, crate::common::RW> {
1235        crate::common::RegisterFieldBool::<0, 1, 0, Tmr02_SPEC, crate::common::RW>::from_register(
1236            self, 0,
1237        )
1238    }
1239
1240    #[doc = "Selection of Operation Mode at Channel n"]
1241    #[inline(always)]
1242    pub fn md(
1243        self,
1244    ) -> crate::common::RegisterField<
1245        1,
1246        0x7,
1247        1,
1248        0,
1249        tmr02::Md,
1250        tmr02::Md,
1251        Tmr02_SPEC,
1252        crate::common::RW,
1253    > {
1254        crate::common::RegisterField::<
1255            1,
1256            0x7,
1257            1,
1258            0,
1259            tmr02::Md,
1260            tmr02::Md,
1261            Tmr02_SPEC,
1262            crate::common::RW,
1263        >::from_register(self, 0)
1264    }
1265
1266    #[doc = "Selection of TI0n Pin Input Valid Edge"]
1267    #[inline(always)]
1268    pub fn cis(
1269        self,
1270    ) -> crate::common::RegisterField<
1271        6,
1272        0x3,
1273        1,
1274        0,
1275        tmr02::Cis,
1276        tmr02::Cis,
1277        Tmr02_SPEC,
1278        crate::common::RW,
1279    > {
1280        crate::common::RegisterField::<
1281            6,
1282            0x3,
1283            1,
1284            0,
1285            tmr02::Cis,
1286            tmr02::Cis,
1287            Tmr02_SPEC,
1288            crate::common::RW,
1289        >::from_register(self, 0)
1290    }
1291
1292    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
1293    #[inline(always)]
1294    pub fn sts(
1295        self,
1296    ) -> crate::common::RegisterField<
1297        8,
1298        0x7,
1299        1,
1300        0,
1301        tmr02::Sts,
1302        tmr02::Sts,
1303        Tmr02_SPEC,
1304        crate::common::RW,
1305    > {
1306        crate::common::RegisterField::<
1307            8,
1308            0x7,
1309            1,
1310            0,
1311            tmr02::Sts,
1312            tmr02::Sts,
1313            Tmr02_SPEC,
1314            crate::common::RW,
1315        >::from_register(self, 0)
1316    }
1317
1318    #[doc = "Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)"]
1319    #[inline(always)]
1320    pub fn master(
1321        self,
1322    ) -> crate::common::RegisterField<
1323        11,
1324        0x1,
1325        1,
1326        0,
1327        tmr02::Master,
1328        tmr02::Master,
1329        Tmr02_SPEC,
1330        crate::common::RW,
1331    > {
1332        crate::common::RegisterField::<
1333            11,
1334            0x1,
1335            1,
1336            0,
1337            tmr02::Master,
1338            tmr02::Master,
1339            Tmr02_SPEC,
1340            crate::common::RW,
1341        >::from_register(self, 0)
1342    }
1343
1344    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
1345    #[inline(always)]
1346    pub fn ccs(
1347        self,
1348    ) -> crate::common::RegisterField<
1349        12,
1350        0x1,
1351        1,
1352        0,
1353        tmr02::Ccs,
1354        tmr02::Ccs,
1355        Tmr02_SPEC,
1356        crate::common::RW,
1357    > {
1358        crate::common::RegisterField::<
1359            12,
1360            0x1,
1361            1,
1362            0,
1363            tmr02::Ccs,
1364            tmr02::Ccs,
1365            Tmr02_SPEC,
1366            crate::common::RW,
1367        >::from_register(self, 0)
1368    }
1369
1370    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1371    #[inline(always)]
1372    pub fn cks(
1373        self,
1374    ) -> crate::common::RegisterField<
1375        14,
1376        0x3,
1377        1,
1378        0,
1379        tmr02::Cks,
1380        tmr02::Cks,
1381        Tmr02_SPEC,
1382        crate::common::RW,
1383    > {
1384        crate::common::RegisterField::<
1385            14,
1386            0x3,
1387            1,
1388            0,
1389            tmr02::Cks,
1390            tmr02::Cks,
1391            Tmr02_SPEC,
1392            crate::common::RW,
1393        >::from_register(self, 0)
1394    }
1395}
1396impl ::core::default::Default for Tmr02 {
1397    #[inline(always)]
1398    fn default() -> Tmr02 {
1399        <crate::RegValueT<Tmr02_SPEC> as RegisterValue<_>>::new(0)
1400    }
1401}
1402pub mod tmr02 {
1403
1404    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1405    pub struct Md_SPEC;
1406    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
1407    impl Md {
1408        #[doc = "Interval timer mode"]
1409        pub const _000: Self = Self::new(0);
1410
1411        #[doc = "Capture mode"]
1412        pub const _010: Self = Self::new(2);
1413
1414        #[doc = "Event counter mode"]
1415        pub const _011: Self = Self::new(3);
1416
1417        #[doc = "One-count mode"]
1418        pub const _100: Self = Self::new(4);
1419
1420        #[doc = "Capture and one-count mode"]
1421        pub const _110: Self = Self::new(6);
1422    }
1423    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1424    pub struct Cis_SPEC;
1425    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
1426    impl Cis {
1427        #[doc = "Falling edge"]
1428        pub const _00: Self = Self::new(0);
1429
1430        #[doc = "Rising edge"]
1431        pub const _01: Self = Self::new(1);
1432
1433        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
1434        pub const _10: Self = Self::new(2);
1435
1436        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
1437        pub const _11: Self = Self::new(3);
1438    }
1439    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1440    pub struct Sts_SPEC;
1441    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1442    impl Sts {
1443        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
1444        pub const _000: Self = Self::new(0);
1445
1446        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
1447        pub const _001: Self = Self::new(1);
1448
1449        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
1450        pub const _010: Self = Self::new(2);
1451
1452        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
1453        pub const _100: Self = Self::new(4);
1454    }
1455    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1456    pub struct Master_SPEC;
1457    pub type Master = crate::EnumBitfieldStruct<u8, Master_SPEC>;
1458    impl Master {
1459        #[doc = "Operates in independent channel operation function or as slave channel in simultaneous channel operation function."]
1460        pub const _0: Self = Self::new(0);
1461
1462        #[doc = "Operates as master channel in simultaneous channel operation function."]
1463        pub const _1: Self = Self::new(1);
1464    }
1465    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1466    pub struct Ccs_SPEC;
1467    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1468    impl Ccs {
1469        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
1470        pub const _0: Self = Self::new(0);
1471
1472        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
1473        pub const _1: Self = Self::new(1);
1474    }
1475    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1476    pub struct Cks_SPEC;
1477    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1478    impl Cks {
1479        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
1480        pub const _00: Self = Self::new(0);
1481
1482        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
1483        pub const _01: Self = Self::new(1);
1484
1485        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
1486        pub const _10: Self = Self::new(2);
1487
1488        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
1489        pub const _11: Self = Self::new(3);
1490    }
1491}
1492#[doc(hidden)]
1493#[derive(Copy, Clone, Eq, PartialEq)]
1494pub struct Tmr03_SPEC;
1495impl crate::sealed::RegSpec for Tmr03_SPEC {
1496    type DataType = u16;
1497}
1498
1499#[doc = "Timer Mode Register 03"]
1500pub type Tmr03 = crate::RegValueT<Tmr03_SPEC>;
1501
1502impl Tmr03 {
1503    #[doc = "Setting of Starting Count and Interrupt"]
1504    #[inline(always)]
1505    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr03_SPEC, crate::common::RW> {
1506        crate::common::RegisterFieldBool::<0, 1, 0, Tmr03_SPEC, crate::common::RW>::from_register(
1507            self, 0,
1508        )
1509    }
1510
1511    #[doc = "Selection of Operation Mode at Channel n"]
1512    #[inline(always)]
1513    pub fn md(
1514        self,
1515    ) -> crate::common::RegisterField<
1516        1,
1517        0x7,
1518        1,
1519        0,
1520        tmr03::Md,
1521        tmr03::Md,
1522        Tmr03_SPEC,
1523        crate::common::RW,
1524    > {
1525        crate::common::RegisterField::<
1526            1,
1527            0x7,
1528            1,
1529            0,
1530            tmr03::Md,
1531            tmr03::Md,
1532            Tmr03_SPEC,
1533            crate::common::RW,
1534        >::from_register(self, 0)
1535    }
1536
1537    #[doc = "Selection of TI0n Pin Input Valid Edge"]
1538    #[inline(always)]
1539    pub fn cis(
1540        self,
1541    ) -> crate::common::RegisterField<
1542        6,
1543        0x3,
1544        1,
1545        0,
1546        tmr03::Cis,
1547        tmr03::Cis,
1548        Tmr03_SPEC,
1549        crate::common::RW,
1550    > {
1551        crate::common::RegisterField::<
1552            6,
1553            0x3,
1554            1,
1555            0,
1556            tmr03::Cis,
1557            tmr03::Cis,
1558            Tmr03_SPEC,
1559            crate::common::RW,
1560        >::from_register(self, 0)
1561    }
1562
1563    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
1564    #[inline(always)]
1565    pub fn sts(
1566        self,
1567    ) -> crate::common::RegisterField<
1568        8,
1569        0x7,
1570        1,
1571        0,
1572        tmr03::Sts,
1573        tmr03::Sts,
1574        Tmr03_SPEC,
1575        crate::common::RW,
1576    > {
1577        crate::common::RegisterField::<
1578            8,
1579            0x7,
1580            1,
1581            0,
1582            tmr03::Sts,
1583            tmr03::Sts,
1584            Tmr03_SPEC,
1585            crate::common::RW,
1586        >::from_register(self, 0)
1587    }
1588
1589    #[doc = "Selection of 8 or 16-bit Timer Operation for Channels 1 and 3"]
1590    #[inline(always)]
1591    pub fn split(
1592        self,
1593    ) -> crate::common::RegisterField<
1594        11,
1595        0x1,
1596        1,
1597        0,
1598        tmr03::Split,
1599        tmr03::Split,
1600        Tmr03_SPEC,
1601        crate::common::RW,
1602    > {
1603        crate::common::RegisterField::<
1604            11,
1605            0x1,
1606            1,
1607            0,
1608            tmr03::Split,
1609            tmr03::Split,
1610            Tmr03_SPEC,
1611            crate::common::RW,
1612        >::from_register(self, 0)
1613    }
1614
1615    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
1616    #[inline(always)]
1617    pub fn ccs(
1618        self,
1619    ) -> crate::common::RegisterField<
1620        12,
1621        0x1,
1622        1,
1623        0,
1624        tmr03::Ccs,
1625        tmr03::Ccs,
1626        Tmr03_SPEC,
1627        crate::common::RW,
1628    > {
1629        crate::common::RegisterField::<
1630            12,
1631            0x1,
1632            1,
1633            0,
1634            tmr03::Ccs,
1635            tmr03::Ccs,
1636            Tmr03_SPEC,
1637            crate::common::RW,
1638        >::from_register(self, 0)
1639    }
1640
1641    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1642    #[inline(always)]
1643    pub fn cks(
1644        self,
1645    ) -> crate::common::RegisterField<
1646        14,
1647        0x3,
1648        1,
1649        0,
1650        tmr03::Cks,
1651        tmr03::Cks,
1652        Tmr03_SPEC,
1653        crate::common::RW,
1654    > {
1655        crate::common::RegisterField::<
1656            14,
1657            0x3,
1658            1,
1659            0,
1660            tmr03::Cks,
1661            tmr03::Cks,
1662            Tmr03_SPEC,
1663            crate::common::RW,
1664        >::from_register(self, 0)
1665    }
1666}
1667impl ::core::default::Default for Tmr03 {
1668    #[inline(always)]
1669    fn default() -> Tmr03 {
1670        <crate::RegValueT<Tmr03_SPEC> as RegisterValue<_>>::new(0)
1671    }
1672}
1673pub mod tmr03 {
1674
1675    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1676    pub struct Md_SPEC;
1677    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
1678    impl Md {
1679        #[doc = "Interval timer mode"]
1680        pub const _000: Self = Self::new(0);
1681
1682        #[doc = "Capture mode"]
1683        pub const _010: Self = Self::new(2);
1684
1685        #[doc = "Event counter mode"]
1686        pub const _011: Self = Self::new(3);
1687
1688        #[doc = "One-count mode"]
1689        pub const _100: Self = Self::new(4);
1690
1691        #[doc = "Capture & one-count mode"]
1692        pub const _110: Self = Self::new(6);
1693    }
1694    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1695    pub struct Cis_SPEC;
1696    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
1697    impl Cis {
1698        #[doc = "Falling edge"]
1699        pub const _00: Self = Self::new(0);
1700
1701        #[doc = "Rising edge"]
1702        pub const _01: Self = Self::new(1);
1703
1704        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
1705        pub const _10: Self = Self::new(2);
1706
1707        #[doc = "Both edges (when high-level width is measured) Start trigger: Rising edge, Capture trigger: Falling edge"]
1708        pub const _11: Self = Self::new(3);
1709    }
1710    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1711    pub struct Sts_SPEC;
1712    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1713    impl Sts {
1714        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
1715        pub const _000: Self = Self::new(0);
1716
1717        #[doc = "Valid edge of the Ti0n pin input is used as both the start trigger and capture trigger."]
1718        pub const _001: Self = Self::new(1);
1719
1720        #[doc = "Both the edges of the Ti0n pin input are used as a start trigger and a capture trigger."]
1721        pub const _010: Self = Self::new(2);
1722
1723        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
1724        pub const _100: Self = Self::new(4);
1725    }
1726    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1727    pub struct Split_SPEC;
1728    pub type Split = crate::EnumBitfieldStruct<u8, Split_SPEC>;
1729    impl Split {
1730        #[doc = "Operates as 16-bit timer (Operates in independent channel operation function or as slave channel in simultaneous channel operation function.)"]
1731        pub const _0: Self = Self::new(0);
1732
1733        #[doc = "Operates as 8-bit timer"]
1734        pub const _1: Self = Self::new(1);
1735    }
1736    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1737    pub struct Ccs_SPEC;
1738    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1739    impl Ccs {
1740        #[doc = "Operating clock (fMCK) specified by the CKS\\[1:0\\] bits"]
1741        pub const _0: Self = Self::new(0);
1742
1743        #[doc = "Valid edge of input signal input from the Ti0n pin In the case of unit 0: In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
1744        pub const _1: Self = Self::new(1);
1745    }
1746    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1747    pub struct Cks_SPEC;
1748    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1749    impl Cks {
1750        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
1751        pub const _00: Self = Self::new(0);
1752
1753        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
1754        pub const _01: Self = Self::new(1);
1755
1756        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
1757        pub const _10: Self = Self::new(2);
1758
1759        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
1760        pub const _11: Self = Self::new(3);
1761    }
1762}
1763#[doc(hidden)]
1764#[derive(Copy, Clone, Eq, PartialEq)]
1765pub struct Tmr04_SPEC;
1766impl crate::sealed::RegSpec for Tmr04_SPEC {
1767    type DataType = u16;
1768}
1769
1770#[doc = "Timer Mode Register 04"]
1771pub type Tmr04 = crate::RegValueT<Tmr04_SPEC>;
1772
1773impl Tmr04 {
1774    #[doc = "Setting of Starting Count and Interrupt"]
1775    #[inline(always)]
1776    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr04_SPEC, crate::common::RW> {
1777        crate::common::RegisterFieldBool::<0, 1, 0, Tmr04_SPEC, crate::common::RW>::from_register(
1778            self, 0,
1779        )
1780    }
1781
1782    #[doc = "Selection of Operation Mode at Channel n"]
1783    #[inline(always)]
1784    pub fn md(
1785        self,
1786    ) -> crate::common::RegisterField<
1787        1,
1788        0x7,
1789        1,
1790        0,
1791        tmr04::Md,
1792        tmr04::Md,
1793        Tmr04_SPEC,
1794        crate::common::RW,
1795    > {
1796        crate::common::RegisterField::<
1797            1,
1798            0x7,
1799            1,
1800            0,
1801            tmr04::Md,
1802            tmr04::Md,
1803            Tmr04_SPEC,
1804            crate::common::RW,
1805        >::from_register(self, 0)
1806    }
1807
1808    #[doc = "Selection of TI0n Pin Input Valid Edge"]
1809    #[inline(always)]
1810    pub fn cis(
1811        self,
1812    ) -> crate::common::RegisterField<
1813        6,
1814        0x3,
1815        1,
1816        0,
1817        tmr04::Cis,
1818        tmr04::Cis,
1819        Tmr04_SPEC,
1820        crate::common::RW,
1821    > {
1822        crate::common::RegisterField::<
1823            6,
1824            0x3,
1825            1,
1826            0,
1827            tmr04::Cis,
1828            tmr04::Cis,
1829            Tmr04_SPEC,
1830            crate::common::RW,
1831        >::from_register(self, 0)
1832    }
1833
1834    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
1835    #[inline(always)]
1836    pub fn sts(
1837        self,
1838    ) -> crate::common::RegisterField<
1839        8,
1840        0x7,
1841        1,
1842        0,
1843        tmr04::Sts,
1844        tmr04::Sts,
1845        Tmr04_SPEC,
1846        crate::common::RW,
1847    > {
1848        crate::common::RegisterField::<
1849            8,
1850            0x7,
1851            1,
1852            0,
1853            tmr04::Sts,
1854            tmr04::Sts,
1855            Tmr04_SPEC,
1856            crate::common::RW,
1857        >::from_register(self, 0)
1858    }
1859
1860    #[doc = "Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)"]
1861    #[inline(always)]
1862    pub fn master(
1863        self,
1864    ) -> crate::common::RegisterField<
1865        11,
1866        0x1,
1867        1,
1868        0,
1869        tmr04::Master,
1870        tmr04::Master,
1871        Tmr04_SPEC,
1872        crate::common::RW,
1873    > {
1874        crate::common::RegisterField::<
1875            11,
1876            0x1,
1877            1,
1878            0,
1879            tmr04::Master,
1880            tmr04::Master,
1881            Tmr04_SPEC,
1882            crate::common::RW,
1883        >::from_register(self, 0)
1884    }
1885
1886    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
1887    #[inline(always)]
1888    pub fn ccs(
1889        self,
1890    ) -> crate::common::RegisterField<
1891        12,
1892        0x1,
1893        1,
1894        0,
1895        tmr04::Ccs,
1896        tmr04::Ccs,
1897        Tmr04_SPEC,
1898        crate::common::RW,
1899    > {
1900        crate::common::RegisterField::<
1901            12,
1902            0x1,
1903            1,
1904            0,
1905            tmr04::Ccs,
1906            tmr04::Ccs,
1907            Tmr04_SPEC,
1908            crate::common::RW,
1909        >::from_register(self, 0)
1910    }
1911
1912    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1913    #[inline(always)]
1914    pub fn cks(
1915        self,
1916    ) -> crate::common::RegisterField<
1917        14,
1918        0x3,
1919        1,
1920        0,
1921        tmr04::Cks,
1922        tmr04::Cks,
1923        Tmr04_SPEC,
1924        crate::common::RW,
1925    > {
1926        crate::common::RegisterField::<
1927            14,
1928            0x3,
1929            1,
1930            0,
1931            tmr04::Cks,
1932            tmr04::Cks,
1933            Tmr04_SPEC,
1934            crate::common::RW,
1935        >::from_register(self, 0)
1936    }
1937}
1938impl ::core::default::Default for Tmr04 {
1939    #[inline(always)]
1940    fn default() -> Tmr04 {
1941        <crate::RegValueT<Tmr04_SPEC> as RegisterValue<_>>::new(0)
1942    }
1943}
1944pub mod tmr04 {
1945
1946    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1947    pub struct Md_SPEC;
1948    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
1949    impl Md {
1950        #[doc = "Interval timer mode"]
1951        pub const _000: Self = Self::new(0);
1952
1953        #[doc = "Capture mode"]
1954        pub const _010: Self = Self::new(2);
1955
1956        #[doc = "Event counter mode"]
1957        pub const _011: Self = Self::new(3);
1958
1959        #[doc = "One-count mode"]
1960        pub const _100: Self = Self::new(4);
1961
1962        #[doc = "Capture and one-count mode"]
1963        pub const _110: Self = Self::new(6);
1964    }
1965    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1966    pub struct Cis_SPEC;
1967    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
1968    impl Cis {
1969        #[doc = "Falling edge"]
1970        pub const _00: Self = Self::new(0);
1971
1972        #[doc = "Rising edge"]
1973        pub const _01: Self = Self::new(1);
1974
1975        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
1976        pub const _10: Self = Self::new(2);
1977
1978        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
1979        pub const _11: Self = Self::new(3);
1980    }
1981    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1982    pub struct Sts_SPEC;
1983    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1984    impl Sts {
1985        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
1986        pub const _000: Self = Self::new(0);
1987
1988        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
1989        pub const _001: Self = Self::new(1);
1990
1991        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
1992        pub const _010: Self = Self::new(2);
1993
1994        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
1995        pub const _100: Self = Self::new(4);
1996    }
1997    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1998    pub struct Master_SPEC;
1999    pub type Master = crate::EnumBitfieldStruct<u8, Master_SPEC>;
2000    impl Master {
2001        #[doc = "Operates in independent channel operation function or as slave channel in simultaneous channel operation function."]
2002        pub const _0: Self = Self::new(0);
2003
2004        #[doc = "Operates as master channel in simultaneous channel operation function."]
2005        pub const _1: Self = Self::new(1);
2006    }
2007    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2008    pub struct Ccs_SPEC;
2009    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2010    impl Ccs {
2011        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
2012        pub const _0: Self = Self::new(0);
2013
2014        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
2015        pub const _1: Self = Self::new(1);
2016    }
2017    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2018    pub struct Cks_SPEC;
2019    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2020    impl Cks {
2021        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
2022        pub const _00: Self = Self::new(0);
2023
2024        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
2025        pub const _01: Self = Self::new(1);
2026
2027        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
2028        pub const _10: Self = Self::new(2);
2029
2030        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
2031        pub const _11: Self = Self::new(3);
2032    }
2033}
2034#[doc(hidden)]
2035#[derive(Copy, Clone, Eq, PartialEq)]
2036pub struct Tmr05_SPEC;
2037impl crate::sealed::RegSpec for Tmr05_SPEC {
2038    type DataType = u16;
2039}
2040
2041#[doc = "Timer Mode Register 05"]
2042pub type Tmr05 = crate::RegValueT<Tmr05_SPEC>;
2043
2044impl Tmr05 {
2045    #[doc = "Setting of Starting Count and Interrupt"]
2046    #[inline(always)]
2047    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr05_SPEC, crate::common::RW> {
2048        crate::common::RegisterFieldBool::<0, 1, 0, Tmr05_SPEC, crate::common::RW>::from_register(
2049            self, 0,
2050        )
2051    }
2052
2053    #[doc = "Selection of Operation Mode at Channel n"]
2054    #[inline(always)]
2055    pub fn md(
2056        self,
2057    ) -> crate::common::RegisterField<
2058        1,
2059        0x7,
2060        1,
2061        0,
2062        tmr05::Md,
2063        tmr05::Md,
2064        Tmr05_SPEC,
2065        crate::common::RW,
2066    > {
2067        crate::common::RegisterField::<
2068            1,
2069            0x7,
2070            1,
2071            0,
2072            tmr05::Md,
2073            tmr05::Md,
2074            Tmr05_SPEC,
2075            crate::common::RW,
2076        >::from_register(self, 0)
2077    }
2078
2079    #[doc = "Selection of TI0n Pin Input Valid Edge"]
2080    #[inline(always)]
2081    pub fn cis(
2082        self,
2083    ) -> crate::common::RegisterField<
2084        6,
2085        0x3,
2086        1,
2087        0,
2088        tmr05::Cis,
2089        tmr05::Cis,
2090        Tmr05_SPEC,
2091        crate::common::RW,
2092    > {
2093        crate::common::RegisterField::<
2094            6,
2095            0x3,
2096            1,
2097            0,
2098            tmr05::Cis,
2099            tmr05::Cis,
2100            Tmr05_SPEC,
2101            crate::common::RW,
2102        >::from_register(self, 0)
2103    }
2104
2105    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
2106    #[inline(always)]
2107    pub fn sts(
2108        self,
2109    ) -> crate::common::RegisterField<
2110        8,
2111        0x7,
2112        1,
2113        0,
2114        tmr05::Sts,
2115        tmr05::Sts,
2116        Tmr05_SPEC,
2117        crate::common::RW,
2118    > {
2119        crate::common::RegisterField::<
2120            8,
2121            0x7,
2122            1,
2123            0,
2124            tmr05::Sts,
2125            tmr05::Sts,
2126            Tmr05_SPEC,
2127            crate::common::RW,
2128        >::from_register(self, 0)
2129    }
2130
2131    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
2132    #[inline(always)]
2133    pub fn ccs(
2134        self,
2135    ) -> crate::common::RegisterField<
2136        12,
2137        0x1,
2138        1,
2139        0,
2140        tmr05::Ccs,
2141        tmr05::Ccs,
2142        Tmr05_SPEC,
2143        crate::common::RW,
2144    > {
2145        crate::common::RegisterField::<
2146            12,
2147            0x1,
2148            1,
2149            0,
2150            tmr05::Ccs,
2151            tmr05::Ccs,
2152            Tmr05_SPEC,
2153            crate::common::RW,
2154        >::from_register(self, 0)
2155    }
2156
2157    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
2158    #[inline(always)]
2159    pub fn cks(
2160        self,
2161    ) -> crate::common::RegisterField<
2162        14,
2163        0x3,
2164        1,
2165        0,
2166        tmr05::Cks,
2167        tmr05::Cks,
2168        Tmr05_SPEC,
2169        crate::common::RW,
2170    > {
2171        crate::common::RegisterField::<
2172            14,
2173            0x3,
2174            1,
2175            0,
2176            tmr05::Cks,
2177            tmr05::Cks,
2178            Tmr05_SPEC,
2179            crate::common::RW,
2180        >::from_register(self, 0)
2181    }
2182}
2183impl ::core::default::Default for Tmr05 {
2184    #[inline(always)]
2185    fn default() -> Tmr05 {
2186        <crate::RegValueT<Tmr05_SPEC> as RegisterValue<_>>::new(0)
2187    }
2188}
2189pub mod tmr05 {
2190
2191    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2192    pub struct Md_SPEC;
2193    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
2194    impl Md {
2195        #[doc = "Interval timer mode"]
2196        pub const _000: Self = Self::new(0);
2197
2198        #[doc = "Capture mode"]
2199        pub const _010: Self = Self::new(2);
2200
2201        #[doc = "Event counter mode"]
2202        pub const _011: Self = Self::new(3);
2203
2204        #[doc = "One-count mode"]
2205        pub const _100: Self = Self::new(4);
2206
2207        #[doc = "Capture and one-count mode"]
2208        pub const _110: Self = Self::new(6);
2209    }
2210    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2211    pub struct Cis_SPEC;
2212    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
2213    impl Cis {
2214        #[doc = "Falling edge"]
2215        pub const _00: Self = Self::new(0);
2216
2217        #[doc = "Rising edge"]
2218        pub const _01: Self = Self::new(1);
2219
2220        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
2221        pub const _10: Self = Self::new(2);
2222
2223        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
2224        pub const _11: Self = Self::new(3);
2225    }
2226    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2227    pub struct Sts_SPEC;
2228    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
2229    impl Sts {
2230        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
2231        pub const _000: Self = Self::new(0);
2232
2233        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
2234        pub const _001: Self = Self::new(1);
2235
2236        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
2237        pub const _010: Self = Self::new(2);
2238
2239        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
2240        pub const _100: Self = Self::new(4);
2241    }
2242    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2243    pub struct Ccs_SPEC;
2244    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2245    impl Ccs {
2246        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
2247        pub const _0: Self = Self::new(0);
2248
2249        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
2250        pub const _1: Self = Self::new(1);
2251    }
2252    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2253    pub struct Cks_SPEC;
2254    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2255    impl Cks {
2256        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
2257        pub const _00: Self = Self::new(0);
2258
2259        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
2260        pub const _01: Self = Self::new(1);
2261
2262        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
2263        pub const _10: Self = Self::new(2);
2264
2265        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
2266        pub const _11: Self = Self::new(3);
2267    }
2268}
2269#[doc(hidden)]
2270#[derive(Copy, Clone, Eq, PartialEq)]
2271pub struct Tmr06_SPEC;
2272impl crate::sealed::RegSpec for Tmr06_SPEC {
2273    type DataType = u16;
2274}
2275
2276#[doc = "Timer Mode Register 06"]
2277pub type Tmr06 = crate::RegValueT<Tmr06_SPEC>;
2278
2279impl Tmr06 {
2280    #[doc = "Setting of Starting Count and Interrupt"]
2281    #[inline(always)]
2282    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr06_SPEC, crate::common::RW> {
2283        crate::common::RegisterFieldBool::<0, 1, 0, Tmr06_SPEC, crate::common::RW>::from_register(
2284            self, 0,
2285        )
2286    }
2287
2288    #[doc = "Selection of Operation Mode at Channel n"]
2289    #[inline(always)]
2290    pub fn md(
2291        self,
2292    ) -> crate::common::RegisterField<
2293        1,
2294        0x7,
2295        1,
2296        0,
2297        tmr06::Md,
2298        tmr06::Md,
2299        Tmr06_SPEC,
2300        crate::common::RW,
2301    > {
2302        crate::common::RegisterField::<
2303            1,
2304            0x7,
2305            1,
2306            0,
2307            tmr06::Md,
2308            tmr06::Md,
2309            Tmr06_SPEC,
2310            crate::common::RW,
2311        >::from_register(self, 0)
2312    }
2313
2314    #[doc = "Selection of TI0n Pin Input Valid Edge"]
2315    #[inline(always)]
2316    pub fn cis(
2317        self,
2318    ) -> crate::common::RegisterField<
2319        6,
2320        0x3,
2321        1,
2322        0,
2323        tmr06::Cis,
2324        tmr06::Cis,
2325        Tmr06_SPEC,
2326        crate::common::RW,
2327    > {
2328        crate::common::RegisterField::<
2329            6,
2330            0x3,
2331            1,
2332            0,
2333            tmr06::Cis,
2334            tmr06::Cis,
2335            Tmr06_SPEC,
2336            crate::common::RW,
2337        >::from_register(self, 0)
2338    }
2339
2340    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
2341    #[inline(always)]
2342    pub fn sts(
2343        self,
2344    ) -> crate::common::RegisterField<
2345        8,
2346        0x7,
2347        1,
2348        0,
2349        tmr06::Sts,
2350        tmr06::Sts,
2351        Tmr06_SPEC,
2352        crate::common::RW,
2353    > {
2354        crate::common::RegisterField::<
2355            8,
2356            0x7,
2357            1,
2358            0,
2359            tmr06::Sts,
2360            tmr06::Sts,
2361            Tmr06_SPEC,
2362            crate::common::RW,
2363        >::from_register(self, 0)
2364    }
2365
2366    #[doc = "Selection Between Using Channel n Independently or Simultaneously with Another Channel (as a Slave or Master)"]
2367    #[inline(always)]
2368    pub fn master(
2369        self,
2370    ) -> crate::common::RegisterField<
2371        11,
2372        0x1,
2373        1,
2374        0,
2375        tmr06::Master,
2376        tmr06::Master,
2377        Tmr06_SPEC,
2378        crate::common::RW,
2379    > {
2380        crate::common::RegisterField::<
2381            11,
2382            0x1,
2383            1,
2384            0,
2385            tmr06::Master,
2386            tmr06::Master,
2387            Tmr06_SPEC,
2388            crate::common::RW,
2389        >::from_register(self, 0)
2390    }
2391
2392    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
2393    #[inline(always)]
2394    pub fn ccs(
2395        self,
2396    ) -> crate::common::RegisterField<
2397        12,
2398        0x1,
2399        1,
2400        0,
2401        tmr06::Ccs,
2402        tmr06::Ccs,
2403        Tmr06_SPEC,
2404        crate::common::RW,
2405    > {
2406        crate::common::RegisterField::<
2407            12,
2408            0x1,
2409            1,
2410            0,
2411            tmr06::Ccs,
2412            tmr06::Ccs,
2413            Tmr06_SPEC,
2414            crate::common::RW,
2415        >::from_register(self, 0)
2416    }
2417
2418    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
2419    #[inline(always)]
2420    pub fn cks(
2421        self,
2422    ) -> crate::common::RegisterField<
2423        14,
2424        0x3,
2425        1,
2426        0,
2427        tmr06::Cks,
2428        tmr06::Cks,
2429        Tmr06_SPEC,
2430        crate::common::RW,
2431    > {
2432        crate::common::RegisterField::<
2433            14,
2434            0x3,
2435            1,
2436            0,
2437            tmr06::Cks,
2438            tmr06::Cks,
2439            Tmr06_SPEC,
2440            crate::common::RW,
2441        >::from_register(self, 0)
2442    }
2443}
2444impl ::core::default::Default for Tmr06 {
2445    #[inline(always)]
2446    fn default() -> Tmr06 {
2447        <crate::RegValueT<Tmr06_SPEC> as RegisterValue<_>>::new(0)
2448    }
2449}
2450pub mod tmr06 {
2451
2452    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2453    pub struct Md_SPEC;
2454    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
2455    impl Md {
2456        #[doc = "Interval timer mode"]
2457        pub const _000: Self = Self::new(0);
2458
2459        #[doc = "Capture mode"]
2460        pub const _010: Self = Self::new(2);
2461
2462        #[doc = "Event counter mode"]
2463        pub const _011: Self = Self::new(3);
2464
2465        #[doc = "One-count mode"]
2466        pub const _100: Self = Self::new(4);
2467
2468        #[doc = "Capture and one-count mode"]
2469        pub const _110: Self = Self::new(6);
2470    }
2471    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2472    pub struct Cis_SPEC;
2473    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
2474    impl Cis {
2475        #[doc = "Falling edge"]
2476        pub const _00: Self = Self::new(0);
2477
2478        #[doc = "Rising edge"]
2479        pub const _01: Self = Self::new(1);
2480
2481        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
2482        pub const _10: Self = Self::new(2);
2483
2484        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
2485        pub const _11: Self = Self::new(3);
2486    }
2487    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2488    pub struct Sts_SPEC;
2489    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
2490    impl Sts {
2491        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
2492        pub const _000: Self = Self::new(0);
2493
2494        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
2495        pub const _001: Self = Self::new(1);
2496
2497        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
2498        pub const _010: Self = Self::new(2);
2499
2500        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
2501        pub const _100: Self = Self::new(4);
2502    }
2503    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2504    pub struct Master_SPEC;
2505    pub type Master = crate::EnumBitfieldStruct<u8, Master_SPEC>;
2506    impl Master {
2507        #[doc = "Operates in independent channel operation function or as slave channel in simultaneous channel operation function."]
2508        pub const _0: Self = Self::new(0);
2509
2510        #[doc = "Operates as master channel in simultaneous channel operation function."]
2511        pub const _1: Self = Self::new(1);
2512    }
2513    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2514    pub struct Ccs_SPEC;
2515    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2516    impl Ccs {
2517        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
2518        pub const _0: Self = Self::new(0);
2519
2520        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
2521        pub const _1: Self = Self::new(1);
2522    }
2523    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2524    pub struct Cks_SPEC;
2525    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2526    impl Cks {
2527        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
2528        pub const _00: Self = Self::new(0);
2529
2530        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
2531        pub const _01: Self = Self::new(1);
2532
2533        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
2534        pub const _10: Self = Self::new(2);
2535
2536        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
2537        pub const _11: Self = Self::new(3);
2538    }
2539}
2540#[doc(hidden)]
2541#[derive(Copy, Clone, Eq, PartialEq)]
2542pub struct Tmr07_SPEC;
2543impl crate::sealed::RegSpec for Tmr07_SPEC {
2544    type DataType = u16;
2545}
2546
2547#[doc = "Timer Mode Register 07"]
2548pub type Tmr07 = crate::RegValueT<Tmr07_SPEC>;
2549
2550impl Tmr07 {
2551    #[doc = "Setting of Starting Count and Interrupt"]
2552    #[inline(always)]
2553    pub fn opirq(self) -> crate::common::RegisterFieldBool<0, 1, 0, Tmr07_SPEC, crate::common::RW> {
2554        crate::common::RegisterFieldBool::<0, 1, 0, Tmr07_SPEC, crate::common::RW>::from_register(
2555            self, 0,
2556        )
2557    }
2558
2559    #[doc = "Selection of Operation Mode at Channel n"]
2560    #[inline(always)]
2561    pub fn md(
2562        self,
2563    ) -> crate::common::RegisterField<
2564        1,
2565        0x7,
2566        1,
2567        0,
2568        tmr07::Md,
2569        tmr07::Md,
2570        Tmr07_SPEC,
2571        crate::common::RW,
2572    > {
2573        crate::common::RegisterField::<
2574            1,
2575            0x7,
2576            1,
2577            0,
2578            tmr07::Md,
2579            tmr07::Md,
2580            Tmr07_SPEC,
2581            crate::common::RW,
2582        >::from_register(self, 0)
2583    }
2584
2585    #[doc = "Selection of TI0n Pin Input Valid Edge"]
2586    #[inline(always)]
2587    pub fn cis(
2588        self,
2589    ) -> crate::common::RegisterField<
2590        6,
2591        0x3,
2592        1,
2593        0,
2594        tmr07::Cis,
2595        tmr07::Cis,
2596        Tmr07_SPEC,
2597        crate::common::RW,
2598    > {
2599        crate::common::RegisterField::<
2600            6,
2601            0x3,
2602            1,
2603            0,
2604            tmr07::Cis,
2605            tmr07::Cis,
2606            Tmr07_SPEC,
2607            crate::common::RW,
2608        >::from_register(self, 0)
2609    }
2610
2611    #[doc = "Setting of Start Trigger or Capture Trigger of Channel n"]
2612    #[inline(always)]
2613    pub fn sts(
2614        self,
2615    ) -> crate::common::RegisterField<
2616        8,
2617        0x7,
2618        1,
2619        0,
2620        tmr07::Sts,
2621        tmr07::Sts,
2622        Tmr07_SPEC,
2623        crate::common::RW,
2624    > {
2625        crate::common::RegisterField::<
2626            8,
2627            0x7,
2628            1,
2629            0,
2630            tmr07::Sts,
2631            tmr07::Sts,
2632            Tmr07_SPEC,
2633            crate::common::RW,
2634        >::from_register(self, 0)
2635    }
2636
2637    #[doc = "Selection of Counter Clock (fTCLK) of Channel n"]
2638    #[inline(always)]
2639    pub fn ccs(
2640        self,
2641    ) -> crate::common::RegisterField<
2642        12,
2643        0x1,
2644        1,
2645        0,
2646        tmr07::Ccs,
2647        tmr07::Ccs,
2648        Tmr07_SPEC,
2649        crate::common::RW,
2650    > {
2651        crate::common::RegisterField::<
2652            12,
2653            0x1,
2654            1,
2655            0,
2656            tmr07::Ccs,
2657            tmr07::Ccs,
2658            Tmr07_SPEC,
2659            crate::common::RW,
2660        >::from_register(self, 0)
2661    }
2662
2663    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
2664    #[inline(always)]
2665    pub fn cks(
2666        self,
2667    ) -> crate::common::RegisterField<
2668        14,
2669        0x3,
2670        1,
2671        0,
2672        tmr07::Cks,
2673        tmr07::Cks,
2674        Tmr07_SPEC,
2675        crate::common::RW,
2676    > {
2677        crate::common::RegisterField::<
2678            14,
2679            0x3,
2680            1,
2681            0,
2682            tmr07::Cks,
2683            tmr07::Cks,
2684            Tmr07_SPEC,
2685            crate::common::RW,
2686        >::from_register(self, 0)
2687    }
2688}
2689impl ::core::default::Default for Tmr07 {
2690    #[inline(always)]
2691    fn default() -> Tmr07 {
2692        <crate::RegValueT<Tmr07_SPEC> as RegisterValue<_>>::new(0)
2693    }
2694}
2695pub mod tmr07 {
2696
2697    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2698    pub struct Md_SPEC;
2699    pub type Md = crate::EnumBitfieldStruct<u8, Md_SPEC>;
2700    impl Md {
2701        #[doc = "Interval timer mode"]
2702        pub const _000: Self = Self::new(0);
2703
2704        #[doc = "Capture mode"]
2705        pub const _010: Self = Self::new(2);
2706
2707        #[doc = "Event counter mode"]
2708        pub const _011: Self = Self::new(3);
2709
2710        #[doc = "One-count mode"]
2711        pub const _100: Self = Self::new(4);
2712
2713        #[doc = "Capture and one-count mode"]
2714        pub const _110: Self = Self::new(6);
2715    }
2716    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2717    pub struct Cis_SPEC;
2718    pub type Cis = crate::EnumBitfieldStruct<u8, Cis_SPEC>;
2719    impl Cis {
2720        #[doc = "Falling edge"]
2721        pub const _00: Self = Self::new(0);
2722
2723        #[doc = "Rising edge"]
2724        pub const _01: Self = Self::new(1);
2725
2726        #[doc = "Both edges (when low-level width is measured) Start trigger: Falling edge, Capture trigger: Rising edge"]
2727        pub const _10: Self = Self::new(2);
2728
2729        #[doc = "Both edges (when high-level width is measured)  Start trigger: Rising edge, Capture trigger: Falling edge"]
2730        pub const _11: Self = Self::new(3);
2731    }
2732    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2733    pub struct Sts_SPEC;
2734    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
2735    impl Sts {
2736        #[doc = "Only software trigger start is valid (other trigger sources are unselected)."]
2737        pub const _000: Self = Self::new(0);
2738
2739        #[doc = "Valid edge of the TI0n pin input is used as both the start trigger and capture trigger."]
2740        pub const _001: Self = Self::new(1);
2741
2742        #[doc = "Both the edges of the TI0n pin input are used as a start trigger and a capture trigger."]
2743        pub const _010: Self = Self::new(2);
2744
2745        #[doc = "Interrupt signal of the master channel is used (when the channel is used as a slave channel with the simultaneous channel operation function)."]
2746        pub const _100: Self = Self::new(4);
2747    }
2748    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2749    pub struct Ccs_SPEC;
2750    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2751    impl Ccs {
2752        #[doc = "Operating clock (fMCK)specified by the CKS\\[1:0\\] bits"]
2753        pub const _0: Self = Self::new(0);
2754
2755        #[doc = "Valid edge of input signal input from the TI0n pin. In channel 5, valid edge of input signal selected by the TIS0 registerIn channel 7, valid edge of input signal selected by the ISC register"]
2756        pub const _1: Self = Self::new(1);
2757    }
2758    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2759    pub struct Cks_SPEC;
2760    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2761    impl Cks {
2762        #[doc = "Operation clock CK00 set by timer clock select register 0 (TPS0)"]
2763        pub const _00: Self = Self::new(0);
2764
2765        #[doc = "Operation clock CK02 set by timer clock select register 0 (TPS0)"]
2766        pub const _01: Self = Self::new(1);
2767
2768        #[doc = "Operation clock CK01 set by timer clock select register 0 (TPS0)"]
2769        pub const _10: Self = Self::new(2);
2770
2771        #[doc = "Operation clock CK03 set by timer clock select register 0 (TPS0)"]
2772        pub const _11: Self = Self::new(3);
2773    }
2774}
2775#[doc(hidden)]
2776#[derive(Copy, Clone, Eq, PartialEq)]
2777pub struct Tsr0_SPEC;
2778impl crate::sealed::RegSpec for Tsr0_SPEC {
2779    type DataType = u16;
2780}
2781
2782#[doc = "Timer Status Register 0%s"]
2783pub type Tsr0 = crate::RegValueT<Tsr0_SPEC>;
2784
2785impl Tsr0 {
2786    #[doc = "Counter Overflow State of Channel n"]
2787    #[inline(always)]
2788    pub fn ovf(
2789        self,
2790    ) -> crate::common::RegisterField<0, 0x1, 1, 0, tsr0::Ovf, tsr0::Ovf, Tsr0_SPEC, crate::common::R>
2791    {
2792        crate::common::RegisterField::<
2793            0,
2794            0x1,
2795            1,
2796            0,
2797            tsr0::Ovf,
2798            tsr0::Ovf,
2799            Tsr0_SPEC,
2800            crate::common::R,
2801        >::from_register(self, 0)
2802    }
2803}
2804impl ::core::default::Default for Tsr0 {
2805    #[inline(always)]
2806    fn default() -> Tsr0 {
2807        <crate::RegValueT<Tsr0_SPEC> as RegisterValue<_>>::new(0)
2808    }
2809}
2810pub mod tsr0 {
2811
2812    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2813    pub struct Ovf_SPEC;
2814    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
2815    impl Ovf {
2816        #[doc = "Overflow does not occur"]
2817        pub const _0: Self = Self::new(0);
2818
2819        #[doc = "Overflow occurs"]
2820        pub const _1: Self = Self::new(1);
2821    }
2822}
2823#[doc(hidden)]
2824#[derive(Copy, Clone, Eq, PartialEq)]
2825pub struct Te0_SPEC;
2826impl crate::sealed::RegSpec for Te0_SPEC {
2827    type DataType = u16;
2828}
2829
2830#[doc = "Timer Channel Enable Status Register 0"]
2831pub type Te0 = crate::RegValueT<Te0_SPEC>;
2832
2833impl Te0 {
2834    #[doc = "Indication of Operation Enabled or Stopped State of Channel n"]
2835    #[inline(always)]
2836    pub fn te(
2837        self,
2838    ) -> crate::common::RegisterField<0, 0xff, 1, 0, te0::Te, te0::Te, Te0_SPEC, crate::common::R>
2839    {
2840        crate::common::RegisterField::<0,0xff,1,0,te0::Te,te0::Te,Te0_SPEC,crate::common::R>::from_register(self,0)
2841    }
2842
2843    #[doc = "Indication of whether Operation of the Higher 8-bit Timer is Enabled or Stopped when Channel 1 is in the 8-bit Timer Mode"]
2844    #[inline(always)]
2845    pub fn teh1(
2846        self,
2847    ) -> crate::common::RegisterField<9, 0x1, 1, 0, te0::Teh1, te0::Teh1, Te0_SPEC, crate::common::R>
2848    {
2849        crate::common::RegisterField::<9,0x1,1,0,te0::Teh1,te0::Teh1,Te0_SPEC,crate::common::R>::from_register(self,0)
2850    }
2851
2852    #[doc = "Indication of whether Operation of the Higher 8-bit Timer is Enabled or Stopped when Channel 3 is in the 8-bit Timer Mode"]
2853    #[inline(always)]
2854    pub fn teh3(
2855        self,
2856    ) -> crate::common::RegisterField<11, 0x1, 1, 0, te0::Teh3, te0::Teh3, Te0_SPEC, crate::common::R>
2857    {
2858        crate::common::RegisterField::<
2859            11,
2860            0x1,
2861            1,
2862            0,
2863            te0::Teh3,
2864            te0::Teh3,
2865            Te0_SPEC,
2866            crate::common::R,
2867        >::from_register(self, 0)
2868    }
2869}
2870impl ::core::default::Default for Te0 {
2871    #[inline(always)]
2872    fn default() -> Te0 {
2873        <crate::RegValueT<Te0_SPEC> as RegisterValue<_>>::new(0)
2874    }
2875}
2876pub mod te0 {
2877
2878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2879    pub struct Te_SPEC;
2880    pub type Te = crate::EnumBitfieldStruct<u8, Te_SPEC>;
2881    impl Te {
2882        #[doc = "Operation is stopped"]
2883        pub const _0: Self = Self::new(0);
2884
2885        #[doc = "Operation is enabled"]
2886        pub const _1: Self = Self::new(1);
2887    }
2888    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2889    pub struct Teh1_SPEC;
2890    pub type Teh1 = crate::EnumBitfieldStruct<u8, Teh1_SPEC>;
2891    impl Teh1 {
2892        #[doc = "Operation is stopped"]
2893        pub const _0: Self = Self::new(0);
2894
2895        #[doc = "Operation is enabled"]
2896        pub const _1: Self = Self::new(1);
2897    }
2898    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2899    pub struct Teh3_SPEC;
2900    pub type Teh3 = crate::EnumBitfieldStruct<u8, Teh3_SPEC>;
2901    impl Teh3 {
2902        #[doc = "Operation is stopped"]
2903        pub const _0: Self = Self::new(0);
2904
2905        #[doc = "Operation is enabled"]
2906        pub const _1: Self = Self::new(1);
2907    }
2908}
2909#[doc(hidden)]
2910#[derive(Copy, Clone, Eq, PartialEq)]
2911pub struct Ts0_SPEC;
2912impl crate::sealed::RegSpec for Ts0_SPEC {
2913    type DataType = u16;
2914}
2915
2916#[doc = "Timer Channel Start Register 0"]
2917pub type Ts0 = crate::RegValueT<Ts0_SPEC>;
2918
2919impl Ts0 {
2920    #[doc = "Operation Enable (Start) Trigger of Channel n"]
2921    #[inline(always)]
2922    pub fn ts(
2923        self,
2924    ) -> crate::common::RegisterField<0, 0xff, 1, 0, ts0::Ts, ts0::Ts, Ts0_SPEC, crate::common::RW>
2925    {
2926        crate::common::RegisterField::<0,0xff,1,0,ts0::Ts,ts0::Ts,Ts0_SPEC,crate::common::RW>::from_register(self,0)
2927    }
2928
2929    #[doc = "Trigger to Enable Operation (Start Operation) of the Higher 8-bit Timer when Channel 1 is in the 8-bit Timer Mode"]
2930    #[inline(always)]
2931    pub fn tsh1(
2932        self,
2933    ) -> crate::common::RegisterField<9, 0x1, 1, 0, ts0::Tsh1, ts0::Tsh1, Ts0_SPEC, crate::common::RW>
2934    {
2935        crate::common::RegisterField::<
2936            9,
2937            0x1,
2938            1,
2939            0,
2940            ts0::Tsh1,
2941            ts0::Tsh1,
2942            Ts0_SPEC,
2943            crate::common::RW,
2944        >::from_register(self, 0)
2945    }
2946
2947    #[doc = "Trigger to Enable Operation (Start Operation) of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode"]
2948    #[inline(always)]
2949    pub fn tsh3(
2950        self,
2951    ) -> crate::common::RegisterField<
2952        11,
2953        0x1,
2954        1,
2955        0,
2956        ts0::Tsh3,
2957        ts0::Tsh3,
2958        Ts0_SPEC,
2959        crate::common::RW,
2960    > {
2961        crate::common::RegisterField::<
2962            11,
2963            0x1,
2964            1,
2965            0,
2966            ts0::Tsh3,
2967            ts0::Tsh3,
2968            Ts0_SPEC,
2969            crate::common::RW,
2970        >::from_register(self, 0)
2971    }
2972}
2973impl ::core::default::Default for Ts0 {
2974    #[inline(always)]
2975    fn default() -> Ts0 {
2976        <crate::RegValueT<Ts0_SPEC> as RegisterValue<_>>::new(0)
2977    }
2978}
2979pub mod ts0 {
2980
2981    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2982    pub struct Ts_SPEC;
2983    pub type Ts = crate::EnumBitfieldStruct<u8, Ts_SPEC>;
2984    impl Ts {
2985        #[doc = "No trigger operation"]
2986        pub const _0: Self = Self::new(0);
2987
2988        #[doc = "The TE0.TE\\[n\\] bit is set to 1 and the count operation becomes enabled"]
2989        pub const _1: Self = Self::new(1);
2990    }
2991    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2992    pub struct Tsh1_SPEC;
2993    pub type Tsh1 = crate::EnumBitfieldStruct<u8, Tsh1_SPEC>;
2994    impl Tsh1 {
2995        #[doc = "No trigger operation"]
2996        pub const _0: Self = Self::new(0);
2997
2998        #[doc = "The TE0.TEH1 bit is set to 1 and the count operation becomes enabled"]
2999        pub const _1: Self = Self::new(1);
3000    }
3001    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3002    pub struct Tsh3_SPEC;
3003    pub type Tsh3 = crate::EnumBitfieldStruct<u8, Tsh3_SPEC>;
3004    impl Tsh3 {
3005        #[doc = "No trigger operation"]
3006        pub const _0: Self = Self::new(0);
3007
3008        #[doc = "The TE0.TEH3 bit is set to 1 and the count operation becomes enabled"]
3009        pub const _1: Self = Self::new(1);
3010    }
3011}
3012#[doc(hidden)]
3013#[derive(Copy, Clone, Eq, PartialEq)]
3014pub struct Tt0_SPEC;
3015impl crate::sealed::RegSpec for Tt0_SPEC {
3016    type DataType = u16;
3017}
3018
3019#[doc = "Timer Channel Stop Register 0"]
3020pub type Tt0 = crate::RegValueT<Tt0_SPEC>;
3021
3022impl Tt0 {
3023    #[doc = "Operation Stop Trigger of Channel n"]
3024    #[inline(always)]
3025    pub fn tt(
3026        self,
3027    ) -> crate::common::RegisterField<0, 0xff, 1, 0, tt0::Tt, tt0::Tt, Tt0_SPEC, crate::common::RW>
3028    {
3029        crate::common::RegisterField::<0,0xff,1,0,tt0::Tt,tt0::Tt,Tt0_SPEC,crate::common::RW>::from_register(self,0)
3030    }
3031
3032    #[doc = "Trigger to Stop Operation of the Higher 8-bit Timer when Channel 1 is in the 8-bit Timer Mode"]
3033    #[inline(always)]
3034    pub fn tth1(
3035        self,
3036    ) -> crate::common::RegisterField<9, 0x1, 1, 0, tt0::Tth1, tt0::Tth1, Tt0_SPEC, crate::common::RW>
3037    {
3038        crate::common::RegisterField::<
3039            9,
3040            0x1,
3041            1,
3042            0,
3043            tt0::Tth1,
3044            tt0::Tth1,
3045            Tt0_SPEC,
3046            crate::common::RW,
3047        >::from_register(self, 0)
3048    }
3049
3050    #[doc = "Trigger to Stop Operation of the Higher 8-bit Timer when Channel 3 is in the 8-bit Timer Mode"]
3051    #[inline(always)]
3052    pub fn tth3(
3053        self,
3054    ) -> crate::common::RegisterField<
3055        11,
3056        0x1,
3057        1,
3058        0,
3059        tt0::Tth3,
3060        tt0::Tth3,
3061        Tt0_SPEC,
3062        crate::common::RW,
3063    > {
3064        crate::common::RegisterField::<
3065            11,
3066            0x1,
3067            1,
3068            0,
3069            tt0::Tth3,
3070            tt0::Tth3,
3071            Tt0_SPEC,
3072            crate::common::RW,
3073        >::from_register(self, 0)
3074    }
3075}
3076impl ::core::default::Default for Tt0 {
3077    #[inline(always)]
3078    fn default() -> Tt0 {
3079        <crate::RegValueT<Tt0_SPEC> as RegisterValue<_>>::new(0)
3080    }
3081}
3082pub mod tt0 {
3083
3084    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3085    pub struct Tt_SPEC;
3086    pub type Tt = crate::EnumBitfieldStruct<u8, Tt_SPEC>;
3087    impl Tt {
3088        #[doc = "No trigger operation"]
3089        pub const _0: Self = Self::new(0);
3090
3091        #[doc = "The TE0.TE\\[n\\] bit is cleared to 0 and the count operation is stopped"]
3092        pub const _1: Self = Self::new(1);
3093    }
3094    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3095    pub struct Tth1_SPEC;
3096    pub type Tth1 = crate::EnumBitfieldStruct<u8, Tth1_SPEC>;
3097    impl Tth1 {
3098        #[doc = "No trigger operation"]
3099        pub const _0: Self = Self::new(0);
3100
3101        #[doc = "The TE0.TEH1 bit is cleared to 0 and the count operation is stopped"]
3102        pub const _1: Self = Self::new(1);
3103    }
3104    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3105    pub struct Tth3_SPEC;
3106    pub type Tth3 = crate::EnumBitfieldStruct<u8, Tth3_SPEC>;
3107    impl Tth3 {
3108        #[doc = "No trigger operation"]
3109        pub const _0: Self = Self::new(0);
3110
3111        #[doc = "The TE0.TEH3 bit is cleared to 0 and the count operation is stopped"]
3112        pub const _1: Self = Self::new(1);
3113    }
3114}
3115#[doc(hidden)]
3116#[derive(Copy, Clone, Eq, PartialEq)]
3117pub struct Tps0_SPEC;
3118impl crate::sealed::RegSpec for Tps0_SPEC {
3119    type DataType = u16;
3120}
3121
3122#[doc = "Timer Clock Select Register 0"]
3123pub type Tps0 = crate::RegValueT<Tps0_SPEC>;
3124
3125impl Tps0 {
3126    #[doc = "Selection of Operation Clock (CK00)"]
3127    #[inline(always)]
3128    pub fn prs0(
3129        self,
3130    ) -> crate::common::RegisterField<
3131        0,
3132        0xf,
3133        1,
3134        0,
3135        tps0::Prs0,
3136        tps0::Prs0,
3137        Tps0_SPEC,
3138        crate::common::RW,
3139    > {
3140        crate::common::RegisterField::<
3141            0,
3142            0xf,
3143            1,
3144            0,
3145            tps0::Prs0,
3146            tps0::Prs0,
3147            Tps0_SPEC,
3148            crate::common::RW,
3149        >::from_register(self, 0)
3150    }
3151
3152    #[doc = "Selection of Operation Clock (CK01)"]
3153    #[inline(always)]
3154    pub fn prs1(
3155        self,
3156    ) -> crate::common::RegisterField<
3157        4,
3158        0xf,
3159        1,
3160        0,
3161        tps0::Prs1,
3162        tps0::Prs1,
3163        Tps0_SPEC,
3164        crate::common::RW,
3165    > {
3166        crate::common::RegisterField::<
3167            4,
3168            0xf,
3169            1,
3170            0,
3171            tps0::Prs1,
3172            tps0::Prs1,
3173            Tps0_SPEC,
3174            crate::common::RW,
3175        >::from_register(self, 0)
3176    }
3177
3178    #[doc = "Selection of Operation Clock (CK02)"]
3179    #[inline(always)]
3180    pub fn prs2(
3181        self,
3182    ) -> crate::common::RegisterField<
3183        8,
3184        0x3,
3185        1,
3186        0,
3187        tps0::Prs2,
3188        tps0::Prs2,
3189        Tps0_SPEC,
3190        crate::common::RW,
3191    > {
3192        crate::common::RegisterField::<
3193            8,
3194            0x3,
3195            1,
3196            0,
3197            tps0::Prs2,
3198            tps0::Prs2,
3199            Tps0_SPEC,
3200            crate::common::RW,
3201        >::from_register(self, 0)
3202    }
3203
3204    #[doc = "Selection of Operation Clock (CK03)"]
3205    #[inline(always)]
3206    pub fn prs3(
3207        self,
3208    ) -> crate::common::RegisterField<
3209        12,
3210        0x3,
3211        1,
3212        0,
3213        tps0::Prs3,
3214        tps0::Prs3,
3215        Tps0_SPEC,
3216        crate::common::RW,
3217    > {
3218        crate::common::RegisterField::<
3219            12,
3220            0x3,
3221            1,
3222            0,
3223            tps0::Prs3,
3224            tps0::Prs3,
3225            Tps0_SPEC,
3226            crate::common::RW,
3227        >::from_register(self, 0)
3228    }
3229}
3230impl ::core::default::Default for Tps0 {
3231    #[inline(always)]
3232    fn default() -> Tps0 {
3233        <crate::RegValueT<Tps0_SPEC> as RegisterValue<_>>::new(0)
3234    }
3235}
3236pub mod tps0 {
3237
3238    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3239    pub struct Prs0_SPEC;
3240    pub type Prs0 = crate::EnumBitfieldStruct<u8, Prs0_SPEC>;
3241    impl Prs0 {
3242        #[doc = "PCLKB"]
3243        pub const _0_X_0: Self = Self::new(0);
3244
3245        #[doc = "PCLKB/2"]
3246        pub const _0_X_1: Self = Self::new(1);
3247
3248        #[doc = "PCLKB/22"]
3249        pub const _0_X_2: Self = Self::new(2);
3250
3251        #[doc = "PCLKB/23"]
3252        pub const _0_X_3: Self = Self::new(3);
3253
3254        #[doc = "PCLKB/24"]
3255        pub const _0_X_4: Self = Self::new(4);
3256
3257        #[doc = "PCLKB/25"]
3258        pub const _0_X_5: Self = Self::new(5);
3259
3260        #[doc = "PCLKB/26"]
3261        pub const _0_X_6: Self = Self::new(6);
3262
3263        #[doc = "PCLKB/27"]
3264        pub const _0_X_7: Self = Self::new(7);
3265
3266        #[doc = "PCLKB/28"]
3267        pub const _0_X_8: Self = Self::new(8);
3268
3269        #[doc = "PCLKB/29"]
3270        pub const _0_X_9: Self = Self::new(9);
3271
3272        #[doc = "PCLKB/210"]
3273        pub const _0_X_A: Self = Self::new(10);
3274
3275        #[doc = "PCLKB/211"]
3276        pub const _0_X_B: Self = Self::new(11);
3277
3278        #[doc = "PCLKB/212"]
3279        pub const _0_X_C: Self = Self::new(12);
3280
3281        #[doc = "PCLKB/213"]
3282        pub const _0_X_D: Self = Self::new(13);
3283
3284        #[doc = "PCLKB/214"]
3285        pub const _0_X_E: Self = Self::new(14);
3286
3287        #[doc = "PCLKB/215"]
3288        pub const _0_X_F: Self = Self::new(15);
3289    }
3290    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3291    pub struct Prs1_SPEC;
3292    pub type Prs1 = crate::EnumBitfieldStruct<u8, Prs1_SPEC>;
3293    impl Prs1 {
3294        #[doc = "PCLKB"]
3295        pub const _0_X_0: Self = Self::new(0);
3296
3297        #[doc = "PCLKB/2"]
3298        pub const _0_X_1: Self = Self::new(1);
3299
3300        #[doc = "PCLKB/22"]
3301        pub const _0_X_2: Self = Self::new(2);
3302
3303        #[doc = "PCLKB/23"]
3304        pub const _0_X_3: Self = Self::new(3);
3305
3306        #[doc = "PCLKB/24"]
3307        pub const _0_X_4: Self = Self::new(4);
3308
3309        #[doc = "PCLKB/25"]
3310        pub const _0_X_5: Self = Self::new(5);
3311
3312        #[doc = "PCLKB/26"]
3313        pub const _0_X_6: Self = Self::new(6);
3314
3315        #[doc = "PCLKB/27"]
3316        pub const _0_X_7: Self = Self::new(7);
3317
3318        #[doc = "PCLKB/28"]
3319        pub const _0_X_8: Self = Self::new(8);
3320
3321        #[doc = "PCLKB/29"]
3322        pub const _0_X_9: Self = Self::new(9);
3323
3324        #[doc = "PCLKB/210"]
3325        pub const _0_X_A: Self = Self::new(10);
3326
3327        #[doc = "PCLKB/211"]
3328        pub const _0_X_B: Self = Self::new(11);
3329
3330        #[doc = "PCLKB/212"]
3331        pub const _0_X_C: Self = Self::new(12);
3332
3333        #[doc = "PCLKB/213"]
3334        pub const _0_X_D: Self = Self::new(13);
3335
3336        #[doc = "PCLKB/214"]
3337        pub const _0_X_E: Self = Self::new(14);
3338
3339        #[doc = "PCLKB/215"]
3340        pub const _0_X_F: Self = Self::new(15);
3341    }
3342    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3343    pub struct Prs2_SPEC;
3344    pub type Prs2 = crate::EnumBitfieldStruct<u8, Prs2_SPEC>;
3345    impl Prs2 {
3346        #[doc = "PCLKB/2"]
3347        pub const _0_X_0: Self = Self::new(0);
3348
3349        #[doc = "PCLKB/22"]
3350        pub const _0_X_1: Self = Self::new(1);
3351
3352        #[doc = "PCLKB/24"]
3353        pub const _0_X_2: Self = Self::new(2);
3354
3355        #[doc = "PCLKB/26"]
3356        pub const _0_X_3: Self = Self::new(3);
3357    }
3358    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3359    pub struct Prs3_SPEC;
3360    pub type Prs3 = crate::EnumBitfieldStruct<u8, Prs3_SPEC>;
3361    impl Prs3 {
3362        #[doc = "PCLKB/28"]
3363        pub const _0_X_0: Self = Self::new(0);
3364
3365        #[doc = "PCLKB/210"]
3366        pub const _0_X_1: Self = Self::new(1);
3367
3368        #[doc = "PCLKB/212"]
3369        pub const _0_X_2: Self = Self::new(2);
3370
3371        #[doc = "PCLKB/214"]
3372        pub const _0_X_3: Self = Self::new(3);
3373    }
3374}
3375#[doc(hidden)]
3376#[derive(Copy, Clone, Eq, PartialEq)]
3377pub struct To0_SPEC;
3378impl crate::sealed::RegSpec for To0_SPEC {
3379    type DataType = u16;
3380}
3381
3382#[doc = "Timer Output Register 0"]
3383pub type To0 = crate::RegValueT<To0_SPEC>;
3384
3385impl To0 {
3386    #[doc = "Timer Output of Channel n"]
3387    #[inline(always)]
3388    pub fn to(
3389        self,
3390    ) -> crate::common::RegisterField<0, 0xff, 1, 0, to0::To, to0::To, To0_SPEC, crate::common::RW>
3391    {
3392        crate::common::RegisterField::<0,0xff,1,0,to0::To,to0::To,To0_SPEC,crate::common::RW>::from_register(self,0)
3393    }
3394}
3395impl ::core::default::Default for To0 {
3396    #[inline(always)]
3397    fn default() -> To0 {
3398        <crate::RegValueT<To0_SPEC> as RegisterValue<_>>::new(0)
3399    }
3400}
3401pub mod to0 {
3402
3403    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3404    pub struct To_SPEC;
3405    pub type To = crate::EnumBitfieldStruct<u8, To_SPEC>;
3406    impl To {
3407        #[doc = "Timer output value is 0"]
3408        pub const _0: Self = Self::new(0);
3409
3410        #[doc = "Timer output value is 1"]
3411        pub const _1: Self = Self::new(1);
3412    }
3413}
3414#[doc(hidden)]
3415#[derive(Copy, Clone, Eq, PartialEq)]
3416pub struct Toe0_SPEC;
3417impl crate::sealed::RegSpec for Toe0_SPEC {
3418    type DataType = u16;
3419}
3420
3421#[doc = "Timer Output Enable Register 0"]
3422pub type Toe0 = crate::RegValueT<Toe0_SPEC>;
3423
3424impl Toe0 {
3425    #[doc = "Enabling or Disabling Timer Output for Channel n"]
3426    #[inline(always)]
3427    pub fn toe(
3428        self,
3429    ) -> crate::common::RegisterField<
3430        0,
3431        0xff,
3432        1,
3433        0,
3434        toe0::Toe,
3435        toe0::Toe,
3436        Toe0_SPEC,
3437        crate::common::RW,
3438    > {
3439        crate::common::RegisterField::<
3440            0,
3441            0xff,
3442            1,
3443            0,
3444            toe0::Toe,
3445            toe0::Toe,
3446            Toe0_SPEC,
3447            crate::common::RW,
3448        >::from_register(self, 0)
3449    }
3450}
3451impl ::core::default::Default for Toe0 {
3452    #[inline(always)]
3453    fn default() -> Toe0 {
3454        <crate::RegValueT<Toe0_SPEC> as RegisterValue<_>>::new(0)
3455    }
3456}
3457pub mod toe0 {
3458
3459    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3460    pub struct Toe_SPEC;
3461    pub type Toe = crate::EnumBitfieldStruct<u8, Toe_SPEC>;
3462    impl Toe {
3463        #[doc = "Disables timer output."]
3464        pub const _0: Self = Self::new(0);
3465
3466        #[doc = "Enables timer output."]
3467        pub const _1: Self = Self::new(1);
3468    }
3469}
3470#[doc(hidden)]
3471#[derive(Copy, Clone, Eq, PartialEq)]
3472pub struct Tol0_SPEC;
3473impl crate::sealed::RegSpec for Tol0_SPEC {
3474    type DataType = u16;
3475}
3476
3477#[doc = "Timer Output Level Register 0"]
3478pub type Tol0 = crate::RegValueT<Tol0_SPEC>;
3479
3480impl Tol0 {
3481    #[doc = "Control of Timer Output of Channel n"]
3482    #[inline(always)]
3483    pub fn tol(
3484        self,
3485    ) -> crate::common::RegisterField<
3486        1,
3487        0x7f,
3488        1,
3489        0,
3490        tol0::Tol,
3491        tol0::Tol,
3492        Tol0_SPEC,
3493        crate::common::RW,
3494    > {
3495        crate::common::RegisterField::<
3496            1,
3497            0x7f,
3498            1,
3499            0,
3500            tol0::Tol,
3501            tol0::Tol,
3502            Tol0_SPEC,
3503            crate::common::RW,
3504        >::from_register(self, 0)
3505    }
3506}
3507impl ::core::default::Default for Tol0 {
3508    #[inline(always)]
3509    fn default() -> Tol0 {
3510        <crate::RegValueT<Tol0_SPEC> as RegisterValue<_>>::new(0)
3511    }
3512}
3513pub mod tol0 {
3514
3515    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3516    pub struct Tol_SPEC;
3517    pub type Tol = crate::EnumBitfieldStruct<u8, Tol_SPEC>;
3518    impl Tol {
3519        #[doc = "Positive logic output (active-high)"]
3520        pub const _0: Self = Self::new(0);
3521
3522        #[doc = "Negative logic output (active-low)"]
3523        pub const _1: Self = Self::new(1);
3524    }
3525}
3526#[doc(hidden)]
3527#[derive(Copy, Clone, Eq, PartialEq)]
3528pub struct Tom0_SPEC;
3529impl crate::sealed::RegSpec for Tom0_SPEC {
3530    type DataType = u16;
3531}
3532
3533#[doc = "Timer Output Mode Register 0"]
3534pub type Tom0 = crate::RegValueT<Tom0_SPEC>;
3535
3536impl Tom0 {
3537    #[doc = "Control of Timer Output Mode of Channel n"]
3538    #[inline(always)]
3539    pub fn tom(
3540        self,
3541    ) -> crate::common::RegisterField<
3542        1,
3543        0x7f,
3544        1,
3545        0,
3546        tom0::Tom,
3547        tom0::Tom,
3548        Tom0_SPEC,
3549        crate::common::RW,
3550    > {
3551        crate::common::RegisterField::<
3552            1,
3553            0x7f,
3554            1,
3555            0,
3556            tom0::Tom,
3557            tom0::Tom,
3558            Tom0_SPEC,
3559            crate::common::RW,
3560        >::from_register(self, 0)
3561    }
3562}
3563impl ::core::default::Default for Tom0 {
3564    #[inline(always)]
3565    fn default() -> Tom0 {
3566        <crate::RegValueT<Tom0_SPEC> as RegisterValue<_>>::new(0)
3567    }
3568}
3569pub mod tom0 {
3570
3571    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3572    pub struct Tom_SPEC;
3573    pub type Tom = crate::EnumBitfieldStruct<u8, Tom_SPEC>;
3574    impl Tom {
3575        #[doc = "Master channel output mode (to produce toggled output by timer interrupt request signal (TAU0_TMI0n))"]
3576        pub const _0: Self = Self::new(0);
3577
3578        #[doc = "Slave channel output mode (output is set by the timer interrupt request signal (TAU0_TMI0n) of the master channel, and reset by the timer interrupt request signal (TAU0_TMI0p) of the slave channel)"]
3579        pub const _1: Self = Self::new(1);
3580    }
3581}
ra0e1_pac/tau.rs

ra0e1_pac/
tau.rs
