ra0e1_pac/
sau0.rs

1/*
2DISCLAIMER
3This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products.
4No other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all
5applicable laws, including copyright laws.
6THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED
7OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
8NON-INFRINGEMENT.  ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY
9LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT,
10INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR
11ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
12Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability
13of this software. By using this software, you agree to the additional terms and conditions found by accessing the
14following link:
15http://www.renesas.com/disclaimer
16
17*/
18// Generated from SVD 1.10.00, with svd2pac 0.6.1 on Sun, 15 Mar 2026 07:00:13 +0000
19
20#![allow(clippy::identity_op)]
21#![allow(clippy::module_inception)]
22#![allow(clippy::derivable_impls)]
23#[allow(unused_imports)]
24use crate::common::sealed;
25#[allow(unused_imports)]
26use crate::common::*;
27#[doc = r"Serial Array Unit 0"]
28unsafe impl ::core::marker::Send for super::Sau0 {}
29unsafe impl ::core::marker::Sync for super::Sau0 {}
30impl super::Sau0 {
31    #[allow(unused)]
32    #[inline(always)]
33    pub(crate) const fn _svd2pac_as_ptr(&self) -> *mut u8 {
34        self.ptr
35    }
36
37    #[doc = "Serial Data Register 0%s"]
38    #[inline(always)]
39    pub const fn sdr0(
40        &self,
41    ) -> &'static crate::common::ClusterRegisterArray<
42        crate::common::Reg<self::Sdr0_SPEC, crate::common::RW>,
43        4,
44        0x2,
45    > {
46        unsafe {
47            crate::common::ClusterRegisterArray::from_ptr(self._svd2pac_as_ptr().add(0x0usize))
48        }
49    }
50    #[inline(always)]
51    pub const fn sdr00(&self) -> &'static crate::common::Reg<self::Sdr0_SPEC, crate::common::RW> {
52        unsafe {
53            crate::common::Reg::<self::Sdr0_SPEC, crate::common::RW>::from_ptr(
54                self._svd2pac_as_ptr().add(0x0usize),
55            )
56        }
57    }
58    #[inline(always)]
59    pub const fn sdr01(&self) -> &'static crate::common::Reg<self::Sdr0_SPEC, crate::common::RW> {
60        unsafe {
61            crate::common::Reg::<self::Sdr0_SPEC, crate::common::RW>::from_ptr(
62                self._svd2pac_as_ptr().add(0x2usize),
63            )
64        }
65    }
66    #[inline(always)]
67    pub const fn sdr02(&self) -> &'static crate::common::Reg<self::Sdr0_SPEC, crate::common::RW> {
68        unsafe {
69            crate::common::Reg::<self::Sdr0_SPEC, crate::common::RW>::from_ptr(
70                self._svd2pac_as_ptr().add(0x4usize),
71            )
72        }
73    }
74    #[inline(always)]
75    pub const fn sdr03(&self) -> &'static crate::common::Reg<self::Sdr0_SPEC, crate::common::RW> {
76        unsafe {
77            crate::common::Reg::<self::Sdr0_SPEC, crate::common::RW>::from_ptr(
78                self._svd2pac_as_ptr().add(0x6usize),
79            )
80        }
81    }
82
83    #[doc = "Serial Status Register 00"]
84    #[inline(always)]
85    pub const fn ssr00(&self) -> &'static crate::common::Reg<self::Ssr00_SPEC, crate::common::R> {
86        unsafe {
87            crate::common::Reg::<self::Ssr00_SPEC, crate::common::R>::from_ptr(
88                self._svd2pac_as_ptr().add(256usize),
89            )
90        }
91    }
92
93    #[doc = "Serial Status Register 01"]
94    #[inline(always)]
95    pub const fn ssr01(&self) -> &'static crate::common::Reg<self::Ssr01_SPEC, crate::common::R> {
96        unsafe {
97            crate::common::Reg::<self::Ssr01_SPEC, crate::common::R>::from_ptr(
98                self._svd2pac_as_ptr().add(258usize),
99            )
100        }
101    }
102
103    #[doc = "Serial Status Register 02"]
104    #[inline(always)]
105    pub const fn ssr02(&self) -> &'static crate::common::Reg<self::Ssr02_SPEC, crate::common::R> {
106        unsafe {
107            crate::common::Reg::<self::Ssr02_SPEC, crate::common::R>::from_ptr(
108                self._svd2pac_as_ptr().add(260usize),
109            )
110        }
111    }
112
113    #[doc = "Serial Status Register 03"]
114    #[inline(always)]
115    pub const fn ssr03(&self) -> &'static crate::common::Reg<self::Ssr03_SPEC, crate::common::R> {
116        unsafe {
117            crate::common::Reg::<self::Ssr03_SPEC, crate::common::R>::from_ptr(
118                self._svd2pac_as_ptr().add(262usize),
119            )
120        }
121    }
122
123    #[doc = "Serial Flag Clear Trigger Register 00"]
124    #[inline(always)]
125    pub const fn sir00(&self) -> &'static crate::common::Reg<self::Sir00_SPEC, crate::common::RW> {
126        unsafe {
127            crate::common::Reg::<self::Sir00_SPEC, crate::common::RW>::from_ptr(
128                self._svd2pac_as_ptr().add(264usize),
129            )
130        }
131    }
132
133    #[doc = "Serial Flag Clear Trigger Register 01"]
134    #[inline(always)]
135    pub const fn sir01(&self) -> &'static crate::common::Reg<self::Sir01_SPEC, crate::common::RW> {
136        unsafe {
137            crate::common::Reg::<self::Sir01_SPEC, crate::common::RW>::from_ptr(
138                self._svd2pac_as_ptr().add(266usize),
139            )
140        }
141    }
142
143    #[doc = "Serial Flag Clear Trigger Register 02"]
144    #[inline(always)]
145    pub const fn sir02(&self) -> &'static crate::common::Reg<self::Sir02_SPEC, crate::common::RW> {
146        unsafe {
147            crate::common::Reg::<self::Sir02_SPEC, crate::common::RW>::from_ptr(
148                self._svd2pac_as_ptr().add(268usize),
149            )
150        }
151    }
152
153    #[doc = "Serial Flag Clear Trigger Register 03"]
154    #[inline(always)]
155    pub const fn sir03(&self) -> &'static crate::common::Reg<self::Sir03_SPEC, crate::common::RW> {
156        unsafe {
157            crate::common::Reg::<self::Sir03_SPEC, crate::common::RW>::from_ptr(
158                self._svd2pac_as_ptr().add(270usize),
159            )
160        }
161    }
162
163    #[doc = "Serial Mode Register 00"]
164    #[inline(always)]
165    pub const fn smr00(&self) -> &'static crate::common::Reg<self::Smr00_SPEC, crate::common::RW> {
166        unsafe {
167            crate::common::Reg::<self::Smr00_SPEC, crate::common::RW>::from_ptr(
168                self._svd2pac_as_ptr().add(272usize),
169            )
170        }
171    }
172
173    #[doc = "Serial Mode Register 01"]
174    #[inline(always)]
175    pub const fn smr01(&self) -> &'static crate::common::Reg<self::Smr01_SPEC, crate::common::RW> {
176        unsafe {
177            crate::common::Reg::<self::Smr01_SPEC, crate::common::RW>::from_ptr(
178                self._svd2pac_as_ptr().add(274usize),
179            )
180        }
181    }
182
183    #[doc = "Serial Mode Register 02"]
184    #[inline(always)]
185    pub const fn smr02(&self) -> &'static crate::common::Reg<self::Smr02_SPEC, crate::common::RW> {
186        unsafe {
187            crate::common::Reg::<self::Smr02_SPEC, crate::common::RW>::from_ptr(
188                self._svd2pac_as_ptr().add(276usize),
189            )
190        }
191    }
192
193    #[doc = "Serial Mode Register 03"]
194    #[inline(always)]
195    pub const fn smr03(&self) -> &'static crate::common::Reg<self::Smr03_SPEC, crate::common::RW> {
196        unsafe {
197            crate::common::Reg::<self::Smr03_SPEC, crate::common::RW>::from_ptr(
198                self._svd2pac_as_ptr().add(278usize),
199            )
200        }
201    }
202
203    #[doc = "Serial Communication Operation Setting Register 00"]
204    #[inline(always)]
205    pub const fn scr00(&self) -> &'static crate::common::Reg<self::Scr00_SPEC, crate::common::RW> {
206        unsafe {
207            crate::common::Reg::<self::Scr00_SPEC, crate::common::RW>::from_ptr(
208                self._svd2pac_as_ptr().add(280usize),
209            )
210        }
211    }
212
213    #[doc = "Serial Communication Operation Setting Register 01"]
214    #[inline(always)]
215    pub const fn scr01(&self) -> &'static crate::common::Reg<self::Scr01_SPEC, crate::common::RW> {
216        unsafe {
217            crate::common::Reg::<self::Scr01_SPEC, crate::common::RW>::from_ptr(
218                self._svd2pac_as_ptr().add(282usize),
219            )
220        }
221    }
222
223    #[doc = "Serial Communication Operation Setting Register 02"]
224    #[inline(always)]
225    pub const fn scr02(&self) -> &'static crate::common::Reg<self::Scr02_SPEC, crate::common::RW> {
226        unsafe {
227            crate::common::Reg::<self::Scr02_SPEC, crate::common::RW>::from_ptr(
228                self._svd2pac_as_ptr().add(284usize),
229            )
230        }
231    }
232
233    #[doc = "Serial Communication Operation Setting Register 03"]
234    #[inline(always)]
235    pub const fn scr03(&self) -> &'static crate::common::Reg<self::Scr03_SPEC, crate::common::RW> {
236        unsafe {
237            crate::common::Reg::<self::Scr03_SPEC, crate::common::RW>::from_ptr(
238                self._svd2pac_as_ptr().add(286usize),
239            )
240        }
241    }
242
243    #[doc = "Serial Channel Enable Status Register 0"]
244    #[inline(always)]
245    pub const fn se0(&self) -> &'static crate::common::Reg<self::Se0_SPEC, crate::common::R> {
246        unsafe {
247            crate::common::Reg::<self::Se0_SPEC, crate::common::R>::from_ptr(
248                self._svd2pac_as_ptr().add(288usize),
249            )
250        }
251    }
252
253    #[doc = "Serial Channel Start Register 0"]
254    #[inline(always)]
255    pub const fn ss0(&self) -> &'static crate::common::Reg<self::Ss0_SPEC, crate::common::RW> {
256        unsafe {
257            crate::common::Reg::<self::Ss0_SPEC, crate::common::RW>::from_ptr(
258                self._svd2pac_as_ptr().add(290usize),
259            )
260        }
261    }
262
263    #[doc = "Serial Channel Stop Register 0"]
264    #[inline(always)]
265    pub const fn st0(&self) -> &'static crate::common::Reg<self::St0_SPEC, crate::common::RW> {
266        unsafe {
267            crate::common::Reg::<self::St0_SPEC, crate::common::RW>::from_ptr(
268                self._svd2pac_as_ptr().add(292usize),
269            )
270        }
271    }
272
273    #[doc = "Serial Clock Select Register 0"]
274    #[inline(always)]
275    pub const fn sps0(&self) -> &'static crate::common::Reg<self::Sps0_SPEC, crate::common::RW> {
276        unsafe {
277            crate::common::Reg::<self::Sps0_SPEC, crate::common::RW>::from_ptr(
278                self._svd2pac_as_ptr().add(294usize),
279            )
280        }
281    }
282
283    #[doc = "Serial Output Register 0"]
284    #[inline(always)]
285    pub const fn so0(&self) -> &'static crate::common::Reg<self::So0_SPEC, crate::common::RW> {
286        unsafe {
287            crate::common::Reg::<self::So0_SPEC, crate::common::RW>::from_ptr(
288                self._svd2pac_as_ptr().add(296usize),
289            )
290        }
291    }
292
293    #[doc = "Serial Output Enable Register 0"]
294    #[inline(always)]
295    pub const fn soe0(&self) -> &'static crate::common::Reg<self::Soe0_SPEC, crate::common::RW> {
296        unsafe {
297            crate::common::Reg::<self::Soe0_SPEC, crate::common::RW>::from_ptr(
298                self._svd2pac_as_ptr().add(298usize),
299            )
300        }
301    }
302
303    #[doc = "Serial Output Level Register 0"]
304    #[inline(always)]
305    pub const fn sol0(&self) -> &'static crate::common::Reg<self::Sol0_SPEC, crate::common::RW> {
306        unsafe {
307            crate::common::Reg::<self::Sol0_SPEC, crate::common::RW>::from_ptr(
308                self._svd2pac_as_ptr().add(308usize),
309            )
310        }
311    }
312
313    #[doc = "Serial Standby Control Register 0"]
314    #[inline(always)]
315    pub const fn ssc0(&self) -> &'static crate::common::Reg<self::Ssc0_SPEC, crate::common::RW> {
316        unsafe {
317            crate::common::Reg::<self::Ssc0_SPEC, crate::common::RW>::from_ptr(
318                self._svd2pac_as_ptr().add(312usize),
319            )
320        }
321    }
322}
323#[doc(hidden)]
324#[derive(Copy, Clone, Eq, PartialEq)]
325pub struct Sdr0_SPEC;
326impl crate::sealed::RegSpec for Sdr0_SPEC {
327    type DataType = u16;
328}
329
330#[doc = "Serial Data Register 0%s"]
331pub type Sdr0 = crate::RegValueT<Sdr0_SPEC>;
332
333impl Sdr0 {
334    #[doc = "Data Buffer for Transmit and Receive"]
335    #[inline(always)]
336    pub fn dat(
337        self,
338    ) -> crate::common::RegisterField<0, 0x1ff, 1, 0, u16, u16, Sdr0_SPEC, crate::common::RW> {
339        crate::common::RegisterField::<0,0x1ff,1,0,u16,u16,Sdr0_SPEC,crate::common::RW>::from_register(self,0)
340    }
341
342    #[doc = "Transfer Clock Setting by Dividing the Operation Clock"]
343    #[inline(always)]
344    pub fn stclk(
345        self,
346    ) -> crate::common::RegisterField<9, 0x7f, 1, 0, u8, u8, Sdr0_SPEC, crate::common::RW> {
347        crate::common::RegisterField::<9,0x7f,1,0,u8,u8,Sdr0_SPEC,crate::common::RW>::from_register(self,0)
348    }
349}
350impl ::core::default::Default for Sdr0 {
351    #[inline(always)]
352    fn default() -> Sdr0 {
353        <crate::RegValueT<Sdr0_SPEC> as RegisterValue<_>>::new(0)
354    }
355}
356
357#[doc(hidden)]
358#[derive(Copy, Clone, Eq, PartialEq)]
359pub struct Ssr00_SPEC;
360impl crate::sealed::RegSpec for Ssr00_SPEC {
361    type DataType = u16;
362}
363
364#[doc = "Serial Status Register 00"]
365pub type Ssr00 = crate::RegValueT<Ssr00_SPEC>;
366
367impl Ssr00 {
368    #[doc = "Overrun Error Detection Flag of Channel n"]
369    #[inline(always)]
370    pub fn ovf(
371        self,
372    ) -> crate::common::RegisterField<
373        0,
374        0x1,
375        1,
376        0,
377        ssr00::Ovf,
378        ssr00::Ovf,
379        Ssr00_SPEC,
380        crate::common::R,
381    > {
382        crate::common::RegisterField::<
383            0,
384            0x1,
385            1,
386            0,
387            ssr00::Ovf,
388            ssr00::Ovf,
389            Ssr00_SPEC,
390            crate::common::R,
391        >::from_register(self, 0)
392    }
393
394    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
395    #[inline(always)]
396    pub fn pef(
397        self,
398    ) -> crate::common::RegisterField<
399        1,
400        0x1,
401        1,
402        0,
403        ssr00::Pef,
404        ssr00::Pef,
405        Ssr00_SPEC,
406        crate::common::R,
407    > {
408        crate::common::RegisterField::<
409            1,
410            0x1,
411            1,
412            0,
413            ssr00::Pef,
414            ssr00::Pef,
415            Ssr00_SPEC,
416            crate::common::R,
417        >::from_register(self, 0)
418    }
419
420    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
421    #[inline(always)]
422    pub fn bff(
423        self,
424    ) -> crate::common::RegisterField<
425        5,
426        0x1,
427        1,
428        0,
429        ssr00::Bff,
430        ssr00::Bff,
431        Ssr00_SPEC,
432        crate::common::R,
433    > {
434        crate::common::RegisterField::<
435            5,
436            0x1,
437            1,
438            0,
439            ssr00::Bff,
440            ssr00::Bff,
441            Ssr00_SPEC,
442            crate::common::R,
443        >::from_register(self, 0)
444    }
445
446    #[doc = "Flag Indicating the State of Communications for Channel n"]
447    #[inline(always)]
448    pub fn tsf(
449        self,
450    ) -> crate::common::RegisterField<
451        6,
452        0x1,
453        1,
454        0,
455        ssr00::Tsf,
456        ssr00::Tsf,
457        Ssr00_SPEC,
458        crate::common::R,
459    > {
460        crate::common::RegisterField::<
461            6,
462            0x1,
463            1,
464            0,
465            ssr00::Tsf,
466            ssr00::Tsf,
467            Ssr00_SPEC,
468            crate::common::R,
469        >::from_register(self, 0)
470    }
471}
472impl ::core::default::Default for Ssr00 {
473    #[inline(always)]
474    fn default() -> Ssr00 {
475        <crate::RegValueT<Ssr00_SPEC> as RegisterValue<_>>::new(0)
476    }
477}
478pub mod ssr00 {
479
480    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
481    pub struct Ovf_SPEC;
482    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
483    impl Ovf {
484        #[doc = "No error occurs"]
485        pub const _0: Self = Self::new(0);
486
487        #[doc = "An error occurs"]
488        pub const _1: Self = Self::new(1);
489    }
490    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
491    pub struct Pef_SPEC;
492    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
493    impl Pef {
494        #[doc = "No error occurs"]
495        pub const _0: Self = Self::new(0);
496
497        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
498        pub const _1: Self = Self::new(1);
499    }
500    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
501    pub struct Bff_SPEC;
502    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
503    impl Bff {
504        #[doc = "Valid data is not stored in the SDRmn register"]
505        pub const _0: Self = Self::new(0);
506
507        #[doc = "Valid data is stored in the SDRmn register"]
508        pub const _1: Self = Self::new(1);
509    }
510    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
511    pub struct Tsf_SPEC;
512    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
513    impl Tsf {
514        #[doc = "Communication is stopped or suspended"]
515        pub const _0: Self = Self::new(0);
516
517        #[doc = "Communication is in progress"]
518        pub const _1: Self = Self::new(1);
519    }
520}
521#[doc(hidden)]
522#[derive(Copy, Clone, Eq, PartialEq)]
523pub struct Ssr01_SPEC;
524impl crate::sealed::RegSpec for Ssr01_SPEC {
525    type DataType = u16;
526}
527
528#[doc = "Serial Status Register 01"]
529pub type Ssr01 = crate::RegValueT<Ssr01_SPEC>;
530
531impl Ssr01 {
532    #[doc = "Overrun Error Detection Flag of Channel n"]
533    #[inline(always)]
534    pub fn ovf(
535        self,
536    ) -> crate::common::RegisterField<
537        0,
538        0x1,
539        1,
540        0,
541        ssr01::Ovf,
542        ssr01::Ovf,
543        Ssr01_SPEC,
544        crate::common::R,
545    > {
546        crate::common::RegisterField::<
547            0,
548            0x1,
549            1,
550            0,
551            ssr01::Ovf,
552            ssr01::Ovf,
553            Ssr01_SPEC,
554            crate::common::R,
555        >::from_register(self, 0)
556    }
557
558    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
559    #[inline(always)]
560    pub fn pef(
561        self,
562    ) -> crate::common::RegisterField<
563        1,
564        0x1,
565        1,
566        0,
567        ssr01::Pef,
568        ssr01::Pef,
569        Ssr01_SPEC,
570        crate::common::R,
571    > {
572        crate::common::RegisterField::<
573            1,
574            0x1,
575            1,
576            0,
577            ssr01::Pef,
578            ssr01::Pef,
579            Ssr01_SPEC,
580            crate::common::R,
581        >::from_register(self, 0)
582    }
583
584    #[doc = "Framing Error Detection Flag of Channel n"]
585    #[inline(always)]
586    pub fn fef(
587        self,
588    ) -> crate::common::RegisterField<
589        2,
590        0x1,
591        1,
592        0,
593        ssr01::Fef,
594        ssr01::Fef,
595        Ssr01_SPEC,
596        crate::common::R,
597    > {
598        crate::common::RegisterField::<
599            2,
600            0x1,
601            1,
602            0,
603            ssr01::Fef,
604            ssr01::Fef,
605            Ssr01_SPEC,
606            crate::common::R,
607        >::from_register(self, 0)
608    }
609
610    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
611    #[inline(always)]
612    pub fn bff(
613        self,
614    ) -> crate::common::RegisterField<
615        5,
616        0x1,
617        1,
618        0,
619        ssr01::Bff,
620        ssr01::Bff,
621        Ssr01_SPEC,
622        crate::common::R,
623    > {
624        crate::common::RegisterField::<
625            5,
626            0x1,
627            1,
628            0,
629            ssr01::Bff,
630            ssr01::Bff,
631            Ssr01_SPEC,
632            crate::common::R,
633        >::from_register(self, 0)
634    }
635
636    #[doc = "Flag Indicating the State of Communications for Channel n"]
637    #[inline(always)]
638    pub fn tsf(
639        self,
640    ) -> crate::common::RegisterField<
641        6,
642        0x1,
643        1,
644        0,
645        ssr01::Tsf,
646        ssr01::Tsf,
647        Ssr01_SPEC,
648        crate::common::R,
649    > {
650        crate::common::RegisterField::<
651            6,
652            0x1,
653            1,
654            0,
655            ssr01::Tsf,
656            ssr01::Tsf,
657            Ssr01_SPEC,
658            crate::common::R,
659        >::from_register(self, 0)
660    }
661}
662impl ::core::default::Default for Ssr01 {
663    #[inline(always)]
664    fn default() -> Ssr01 {
665        <crate::RegValueT<Ssr01_SPEC> as RegisterValue<_>>::new(0)
666    }
667}
668pub mod ssr01 {
669
670    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
671    pub struct Ovf_SPEC;
672    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
673    impl Ovf {
674        #[doc = "No error occurs"]
675        pub const _0: Self = Self::new(0);
676
677        #[doc = "An error occurs"]
678        pub const _1: Self = Self::new(1);
679    }
680    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
681    pub struct Pef_SPEC;
682    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
683    impl Pef {
684        #[doc = "No error occurs"]
685        pub const _0: Self = Self::new(0);
686
687        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
688        pub const _1: Self = Self::new(1);
689    }
690    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
691    pub struct Fef_SPEC;
692    pub type Fef = crate::EnumBitfieldStruct<u8, Fef_SPEC>;
693    impl Fef {
694        #[doc = "No error occurs"]
695        pub const _0: Self = Self::new(0);
696
697        #[doc = "An error occurs (during UART reception)"]
698        pub const _1: Self = Self::new(1);
699    }
700    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
701    pub struct Bff_SPEC;
702    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
703    impl Bff {
704        #[doc = "Valid data is not stored in the SDRmn register"]
705        pub const _0: Self = Self::new(0);
706
707        #[doc = "Valid data is stored in the SDRmn register"]
708        pub const _1: Self = Self::new(1);
709    }
710    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
711    pub struct Tsf_SPEC;
712    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
713    impl Tsf {
714        #[doc = "Communication is stopped or suspended"]
715        pub const _0: Self = Self::new(0);
716
717        #[doc = "Communication is in progress"]
718        pub const _1: Self = Self::new(1);
719    }
720}
721#[doc(hidden)]
722#[derive(Copy, Clone, Eq, PartialEq)]
723pub struct Ssr02_SPEC;
724impl crate::sealed::RegSpec for Ssr02_SPEC {
725    type DataType = u16;
726}
727
728#[doc = "Serial Status Register 02"]
729pub type Ssr02 = crate::RegValueT<Ssr02_SPEC>;
730
731impl Ssr02 {
732    #[doc = "Overrun Error Detection Flag of Channel n"]
733    #[inline(always)]
734    pub fn ovf(
735        self,
736    ) -> crate::common::RegisterField<
737        0,
738        0x1,
739        1,
740        0,
741        ssr02::Ovf,
742        ssr02::Ovf,
743        Ssr02_SPEC,
744        crate::common::R,
745    > {
746        crate::common::RegisterField::<
747            0,
748            0x1,
749            1,
750            0,
751            ssr02::Ovf,
752            ssr02::Ovf,
753            Ssr02_SPEC,
754            crate::common::R,
755        >::from_register(self, 0)
756    }
757
758    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
759    #[inline(always)]
760    pub fn pef(
761        self,
762    ) -> crate::common::RegisterField<
763        1,
764        0x1,
765        1,
766        0,
767        ssr02::Pef,
768        ssr02::Pef,
769        Ssr02_SPEC,
770        crate::common::R,
771    > {
772        crate::common::RegisterField::<
773            1,
774            0x1,
775            1,
776            0,
777            ssr02::Pef,
778            ssr02::Pef,
779            Ssr02_SPEC,
780            crate::common::R,
781        >::from_register(self, 0)
782    }
783
784    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
785    #[inline(always)]
786    pub fn bff(
787        self,
788    ) -> crate::common::RegisterField<
789        5,
790        0x1,
791        1,
792        0,
793        ssr02::Bff,
794        ssr02::Bff,
795        Ssr02_SPEC,
796        crate::common::R,
797    > {
798        crate::common::RegisterField::<
799            5,
800            0x1,
801            1,
802            0,
803            ssr02::Bff,
804            ssr02::Bff,
805            Ssr02_SPEC,
806            crate::common::R,
807        >::from_register(self, 0)
808    }
809
810    #[doc = "Flag Indicating the State of Communications for Channel n"]
811    #[inline(always)]
812    pub fn tsf(
813        self,
814    ) -> crate::common::RegisterField<
815        6,
816        0x1,
817        1,
818        0,
819        ssr02::Tsf,
820        ssr02::Tsf,
821        Ssr02_SPEC,
822        crate::common::R,
823    > {
824        crate::common::RegisterField::<
825            6,
826            0x1,
827            1,
828            0,
829            ssr02::Tsf,
830            ssr02::Tsf,
831            Ssr02_SPEC,
832            crate::common::R,
833        >::from_register(self, 0)
834    }
835}
836impl ::core::default::Default for Ssr02 {
837    #[inline(always)]
838    fn default() -> Ssr02 {
839        <crate::RegValueT<Ssr02_SPEC> as RegisterValue<_>>::new(0)
840    }
841}
842pub mod ssr02 {
843
844    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
845    pub struct Ovf_SPEC;
846    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
847    impl Ovf {
848        #[doc = "No error occurs"]
849        pub const _0: Self = Self::new(0);
850
851        #[doc = "An error occurs"]
852        pub const _1: Self = Self::new(1);
853    }
854    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
855    pub struct Pef_SPEC;
856    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
857    impl Pef {
858        #[doc = "No error occurs"]
859        pub const _0: Self = Self::new(0);
860
861        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
862        pub const _1: Self = Self::new(1);
863    }
864    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
865    pub struct Bff_SPEC;
866    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
867    impl Bff {
868        #[doc = "Valid data is not stored in the SDRmn register"]
869        pub const _0: Self = Self::new(0);
870
871        #[doc = "Valid data is stored in the SDRmn register"]
872        pub const _1: Self = Self::new(1);
873    }
874    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
875    pub struct Tsf_SPEC;
876    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
877    impl Tsf {
878        #[doc = "Communication is stopped or suspended"]
879        pub const _0: Self = Self::new(0);
880
881        #[doc = "Communication is in progress"]
882        pub const _1: Self = Self::new(1);
883    }
884}
885#[doc(hidden)]
886#[derive(Copy, Clone, Eq, PartialEq)]
887pub struct Ssr03_SPEC;
888impl crate::sealed::RegSpec for Ssr03_SPEC {
889    type DataType = u16;
890}
891
892#[doc = "Serial Status Register 03"]
893pub type Ssr03 = crate::RegValueT<Ssr03_SPEC>;
894
895impl Ssr03 {
896    #[doc = "Overrun Error Detection Flag of Channel n"]
897    #[inline(always)]
898    pub fn ovf(
899        self,
900    ) -> crate::common::RegisterField<
901        0,
902        0x1,
903        1,
904        0,
905        ssr03::Ovf,
906        ssr03::Ovf,
907        Ssr03_SPEC,
908        crate::common::R,
909    > {
910        crate::common::RegisterField::<
911            0,
912            0x1,
913            1,
914            0,
915            ssr03::Ovf,
916            ssr03::Ovf,
917            Ssr03_SPEC,
918            crate::common::R,
919        >::from_register(self, 0)
920    }
921
922    #[doc = "Parity or ACK Error Detection Flag of Channel n"]
923    #[inline(always)]
924    pub fn pef(
925        self,
926    ) -> crate::common::RegisterField<
927        1,
928        0x1,
929        1,
930        0,
931        ssr03::Pef,
932        ssr03::Pef,
933        Ssr03_SPEC,
934        crate::common::R,
935    > {
936        crate::common::RegisterField::<
937            1,
938            0x1,
939            1,
940            0,
941            ssr03::Pef,
942            ssr03::Pef,
943            Ssr03_SPEC,
944            crate::common::R,
945        >::from_register(self, 0)
946    }
947
948    #[doc = "Framing Error Detection Flag of Channel n"]
949    #[inline(always)]
950    pub fn fef(
951        self,
952    ) -> crate::common::RegisterField<
953        2,
954        0x1,
955        1,
956        0,
957        ssr03::Fef,
958        ssr03::Fef,
959        Ssr03_SPEC,
960        crate::common::R,
961    > {
962        crate::common::RegisterField::<
963            2,
964            0x1,
965            1,
966            0,
967            ssr03::Fef,
968            ssr03::Fef,
969            Ssr03_SPEC,
970            crate::common::R,
971        >::from_register(self, 0)
972    }
973
974    #[doc = "Flag Indicating the State of the Buffer Register for Channel n"]
975    #[inline(always)]
976    pub fn bff(
977        self,
978    ) -> crate::common::RegisterField<
979        5,
980        0x1,
981        1,
982        0,
983        ssr03::Bff,
984        ssr03::Bff,
985        Ssr03_SPEC,
986        crate::common::R,
987    > {
988        crate::common::RegisterField::<
989            5,
990            0x1,
991            1,
992            0,
993            ssr03::Bff,
994            ssr03::Bff,
995            Ssr03_SPEC,
996            crate::common::R,
997        >::from_register(self, 0)
998    }
999
1000    #[doc = "Flag Indicating the State of Communications for Channel n"]
1001    #[inline(always)]
1002    pub fn tsf(
1003        self,
1004    ) -> crate::common::RegisterField<
1005        6,
1006        0x1,
1007        1,
1008        0,
1009        ssr03::Tsf,
1010        ssr03::Tsf,
1011        Ssr03_SPEC,
1012        crate::common::R,
1013    > {
1014        crate::common::RegisterField::<
1015            6,
1016            0x1,
1017            1,
1018            0,
1019            ssr03::Tsf,
1020            ssr03::Tsf,
1021            Ssr03_SPEC,
1022            crate::common::R,
1023        >::from_register(self, 0)
1024    }
1025}
1026impl ::core::default::Default for Ssr03 {
1027    #[inline(always)]
1028    fn default() -> Ssr03 {
1029        <crate::RegValueT<Ssr03_SPEC> as RegisterValue<_>>::new(0)
1030    }
1031}
1032pub mod ssr03 {
1033
1034    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1035    pub struct Ovf_SPEC;
1036    pub type Ovf = crate::EnumBitfieldStruct<u8, Ovf_SPEC>;
1037    impl Ovf {
1038        #[doc = "No error occurs"]
1039        pub const _0: Self = Self::new(0);
1040
1041        #[doc = "An error occurs"]
1042        pub const _1: Self = Self::new(1);
1043    }
1044    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1045    pub struct Pef_SPEC;
1046    pub type Pef = crate::EnumBitfieldStruct<u8, Pef_SPEC>;
1047    impl Pef {
1048        #[doc = "No error occurs"]
1049        pub const _0: Self = Self::new(0);
1050
1051        #[doc = "Parity error occurs (during UART reception) or ACK is not detected (during I2C transmission)"]
1052        pub const _1: Self = Self::new(1);
1053    }
1054    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1055    pub struct Fef_SPEC;
1056    pub type Fef = crate::EnumBitfieldStruct<u8, Fef_SPEC>;
1057    impl Fef {
1058        #[doc = "No error occurs"]
1059        pub const _0: Self = Self::new(0);
1060
1061        #[doc = "An error occurs (during UART reception)"]
1062        pub const _1: Self = Self::new(1);
1063    }
1064    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1065    pub struct Bff_SPEC;
1066    pub type Bff = crate::EnumBitfieldStruct<u8, Bff_SPEC>;
1067    impl Bff {
1068        #[doc = "Valid data is not stored in the SDRmn register"]
1069        pub const _0: Self = Self::new(0);
1070
1071        #[doc = "Valid data is stored in the SDRmn register"]
1072        pub const _1: Self = Self::new(1);
1073    }
1074    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1075    pub struct Tsf_SPEC;
1076    pub type Tsf = crate::EnumBitfieldStruct<u8, Tsf_SPEC>;
1077    impl Tsf {
1078        #[doc = "Communication is stopped or suspended"]
1079        pub const _0: Self = Self::new(0);
1080
1081        #[doc = "Communication is in progress"]
1082        pub const _1: Self = Self::new(1);
1083    }
1084}
1085#[doc(hidden)]
1086#[derive(Copy, Clone, Eq, PartialEq)]
1087pub struct Sir00_SPEC;
1088impl crate::sealed::RegSpec for Sir00_SPEC {
1089    type DataType = u16;
1090}
1091
1092#[doc = "Serial Flag Clear Trigger Register 00"]
1093pub type Sir00 = crate::RegValueT<Sir00_SPEC>;
1094
1095impl Sir00 {
1096    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
1097    #[inline(always)]
1098    pub fn ovct(
1099        self,
1100    ) -> crate::common::RegisterField<
1101        0,
1102        0x1,
1103        1,
1104        0,
1105        sir00::Ovct,
1106        sir00::Ovct,
1107        Sir00_SPEC,
1108        crate::common::RW,
1109    > {
1110        crate::common::RegisterField::<
1111            0,
1112            0x1,
1113            1,
1114            0,
1115            sir00::Ovct,
1116            sir00::Ovct,
1117            Sir00_SPEC,
1118            crate::common::RW,
1119        >::from_register(self, 0)
1120    }
1121
1122    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
1123    #[inline(always)]
1124    pub fn pect(
1125        self,
1126    ) -> crate::common::RegisterField<
1127        1,
1128        0x1,
1129        1,
1130        0,
1131        sir00::Pect,
1132        sir00::Pect,
1133        Sir00_SPEC,
1134        crate::common::RW,
1135    > {
1136        crate::common::RegisterField::<
1137            1,
1138            0x1,
1139            1,
1140            0,
1141            sir00::Pect,
1142            sir00::Pect,
1143            Sir00_SPEC,
1144            crate::common::RW,
1145        >::from_register(self, 0)
1146    }
1147}
1148impl ::core::default::Default for Sir00 {
1149    #[inline(always)]
1150    fn default() -> Sir00 {
1151        <crate::RegValueT<Sir00_SPEC> as RegisterValue<_>>::new(0)
1152    }
1153}
1154pub mod sir00 {
1155
1156    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1157    pub struct Ovct_SPEC;
1158    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
1159    impl Ovct {
1160        #[doc = "Not cleared"]
1161        pub const _0: Self = Self::new(0);
1162
1163        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
1164        pub const _1: Self = Self::new(1);
1165    }
1166    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1167    pub struct Pect_SPEC;
1168    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
1169    impl Pect {
1170        #[doc = "Not cleared"]
1171        pub const _0: Self = Self::new(0);
1172
1173        #[doc = "Clears the PEF bit of the SSRmn register to 0."]
1174        pub const _1: Self = Self::new(1);
1175    }
1176}
1177#[doc(hidden)]
1178#[derive(Copy, Clone, Eq, PartialEq)]
1179pub struct Sir01_SPEC;
1180impl crate::sealed::RegSpec for Sir01_SPEC {
1181    type DataType = u16;
1182}
1183
1184#[doc = "Serial Flag Clear Trigger Register 01"]
1185pub type Sir01 = crate::RegValueT<Sir01_SPEC>;
1186
1187impl Sir01 {
1188    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
1189    #[inline(always)]
1190    pub fn ovct(
1191        self,
1192    ) -> crate::common::RegisterField<
1193        0,
1194        0x1,
1195        1,
1196        0,
1197        sir01::Ovct,
1198        sir01::Ovct,
1199        Sir01_SPEC,
1200        crate::common::RW,
1201    > {
1202        crate::common::RegisterField::<
1203            0,
1204            0x1,
1205            1,
1206            0,
1207            sir01::Ovct,
1208            sir01::Ovct,
1209            Sir01_SPEC,
1210            crate::common::RW,
1211        >::from_register(self, 0)
1212    }
1213
1214    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
1215    #[inline(always)]
1216    pub fn pect(
1217        self,
1218    ) -> crate::common::RegisterField<
1219        1,
1220        0x1,
1221        1,
1222        0,
1223        sir01::Pect,
1224        sir01::Pect,
1225        Sir01_SPEC,
1226        crate::common::RW,
1227    > {
1228        crate::common::RegisterField::<
1229            1,
1230            0x1,
1231            1,
1232            0,
1233            sir01::Pect,
1234            sir01::Pect,
1235            Sir01_SPEC,
1236            crate::common::RW,
1237        >::from_register(self, 0)
1238    }
1239
1240    #[doc = "Clear Trigger of Framing Error Flag of Channel n"]
1241    #[inline(always)]
1242    pub fn fect(
1243        self,
1244    ) -> crate::common::RegisterField<
1245        2,
1246        0x1,
1247        1,
1248        0,
1249        sir01::Fect,
1250        sir01::Fect,
1251        Sir01_SPEC,
1252        crate::common::RW,
1253    > {
1254        crate::common::RegisterField::<
1255            2,
1256            0x1,
1257            1,
1258            0,
1259            sir01::Fect,
1260            sir01::Fect,
1261            Sir01_SPEC,
1262            crate::common::RW,
1263        >::from_register(self, 0)
1264    }
1265}
1266impl ::core::default::Default for Sir01 {
1267    #[inline(always)]
1268    fn default() -> Sir01 {
1269        <crate::RegValueT<Sir01_SPEC> as RegisterValue<_>>::new(0)
1270    }
1271}
1272pub mod sir01 {
1273
1274    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1275    pub struct Ovct_SPEC;
1276    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
1277    impl Ovct {
1278        #[doc = "Not cleared"]
1279        pub const _0: Self = Self::new(0);
1280
1281        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
1282        pub const _1: Self = Self::new(1);
1283    }
1284    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1285    pub struct Pect_SPEC;
1286    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
1287    impl Pect {
1288        #[doc = "Not cleared"]
1289        pub const _0: Self = Self::new(0);
1290
1291        #[doc = "Clears the PEF bit of the SSRmn register to 0"]
1292        pub const _1: Self = Self::new(1);
1293    }
1294    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1295    pub struct Fect_SPEC;
1296    pub type Fect = crate::EnumBitfieldStruct<u8, Fect_SPEC>;
1297    impl Fect {
1298        #[doc = "Not cleared"]
1299        pub const _0: Self = Self::new(0);
1300
1301        #[doc = "Clears the FEF bit of the SSRmn register to 0"]
1302        pub const _1: Self = Self::new(1);
1303    }
1304}
1305#[doc(hidden)]
1306#[derive(Copy, Clone, Eq, PartialEq)]
1307pub struct Sir02_SPEC;
1308impl crate::sealed::RegSpec for Sir02_SPEC {
1309    type DataType = u16;
1310}
1311
1312#[doc = "Serial Flag Clear Trigger Register 02"]
1313pub type Sir02 = crate::RegValueT<Sir02_SPEC>;
1314
1315impl Sir02 {
1316    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
1317    #[inline(always)]
1318    pub fn ovct(
1319        self,
1320    ) -> crate::common::RegisterField<
1321        0,
1322        0x1,
1323        1,
1324        0,
1325        sir02::Ovct,
1326        sir02::Ovct,
1327        Sir02_SPEC,
1328        crate::common::RW,
1329    > {
1330        crate::common::RegisterField::<
1331            0,
1332            0x1,
1333            1,
1334            0,
1335            sir02::Ovct,
1336            sir02::Ovct,
1337            Sir02_SPEC,
1338            crate::common::RW,
1339        >::from_register(self, 0)
1340    }
1341
1342    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
1343    #[inline(always)]
1344    pub fn pect(
1345        self,
1346    ) -> crate::common::RegisterField<
1347        1,
1348        0x1,
1349        1,
1350        0,
1351        sir02::Pect,
1352        sir02::Pect,
1353        Sir02_SPEC,
1354        crate::common::RW,
1355    > {
1356        crate::common::RegisterField::<
1357            1,
1358            0x1,
1359            1,
1360            0,
1361            sir02::Pect,
1362            sir02::Pect,
1363            Sir02_SPEC,
1364            crate::common::RW,
1365        >::from_register(self, 0)
1366    }
1367}
1368impl ::core::default::Default for Sir02 {
1369    #[inline(always)]
1370    fn default() -> Sir02 {
1371        <crate::RegValueT<Sir02_SPEC> as RegisterValue<_>>::new(0)
1372    }
1373}
1374pub mod sir02 {
1375
1376    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1377    pub struct Ovct_SPEC;
1378    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
1379    impl Ovct {
1380        #[doc = "Not cleared"]
1381        pub const _0: Self = Self::new(0);
1382
1383        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
1384        pub const _1: Self = Self::new(1);
1385    }
1386    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1387    pub struct Pect_SPEC;
1388    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
1389    impl Pect {
1390        #[doc = "Not cleared"]
1391        pub const _0: Self = Self::new(0);
1392
1393        #[doc = "Clears the PEF bit of the SSRmn register to 0."]
1394        pub const _1: Self = Self::new(1);
1395    }
1396}
1397#[doc(hidden)]
1398#[derive(Copy, Clone, Eq, PartialEq)]
1399pub struct Sir03_SPEC;
1400impl crate::sealed::RegSpec for Sir03_SPEC {
1401    type DataType = u16;
1402}
1403
1404#[doc = "Serial Flag Clear Trigger Register 03"]
1405pub type Sir03 = crate::RegValueT<Sir03_SPEC>;
1406
1407impl Sir03 {
1408    #[doc = "Clear Trigger of Overrun Error Flag of Channel n"]
1409    #[inline(always)]
1410    pub fn ovct(
1411        self,
1412    ) -> crate::common::RegisterField<
1413        0,
1414        0x1,
1415        1,
1416        0,
1417        sir03::Ovct,
1418        sir03::Ovct,
1419        Sir03_SPEC,
1420        crate::common::RW,
1421    > {
1422        crate::common::RegisterField::<
1423            0,
1424            0x1,
1425            1,
1426            0,
1427            sir03::Ovct,
1428            sir03::Ovct,
1429            Sir03_SPEC,
1430            crate::common::RW,
1431        >::from_register(self, 0)
1432    }
1433
1434    #[doc = "Clear Trigger of Parity Error Flag of Channel n"]
1435    #[inline(always)]
1436    pub fn pect(
1437        self,
1438    ) -> crate::common::RegisterField<
1439        1,
1440        0x1,
1441        1,
1442        0,
1443        sir03::Pect,
1444        sir03::Pect,
1445        Sir03_SPEC,
1446        crate::common::RW,
1447    > {
1448        crate::common::RegisterField::<
1449            1,
1450            0x1,
1451            1,
1452            0,
1453            sir03::Pect,
1454            sir03::Pect,
1455            Sir03_SPEC,
1456            crate::common::RW,
1457        >::from_register(self, 0)
1458    }
1459
1460    #[doc = "Clear Trigger of Framing Error Flag of Channel n"]
1461    #[inline(always)]
1462    pub fn fect(
1463        self,
1464    ) -> crate::common::RegisterField<
1465        2,
1466        0x1,
1467        1,
1468        0,
1469        sir03::Fect,
1470        sir03::Fect,
1471        Sir03_SPEC,
1472        crate::common::RW,
1473    > {
1474        crate::common::RegisterField::<
1475            2,
1476            0x1,
1477            1,
1478            0,
1479            sir03::Fect,
1480            sir03::Fect,
1481            Sir03_SPEC,
1482            crate::common::RW,
1483        >::from_register(self, 0)
1484    }
1485}
1486impl ::core::default::Default for Sir03 {
1487    #[inline(always)]
1488    fn default() -> Sir03 {
1489        <crate::RegValueT<Sir03_SPEC> as RegisterValue<_>>::new(0)
1490    }
1491}
1492pub mod sir03 {
1493
1494    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1495    pub struct Ovct_SPEC;
1496    pub type Ovct = crate::EnumBitfieldStruct<u8, Ovct_SPEC>;
1497    impl Ovct {
1498        #[doc = "Not cleared"]
1499        pub const _0: Self = Self::new(0);
1500
1501        #[doc = "Clears the OVF bit of the SSRmn register to 0"]
1502        pub const _1: Self = Self::new(1);
1503    }
1504    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1505    pub struct Pect_SPEC;
1506    pub type Pect = crate::EnumBitfieldStruct<u8, Pect_SPEC>;
1507    impl Pect {
1508        #[doc = "Not cleared"]
1509        pub const _0: Self = Self::new(0);
1510
1511        #[doc = "Clears the PEF bit of the SSRmn register to 0"]
1512        pub const _1: Self = Self::new(1);
1513    }
1514    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1515    pub struct Fect_SPEC;
1516    pub type Fect = crate::EnumBitfieldStruct<u8, Fect_SPEC>;
1517    impl Fect {
1518        #[doc = "Not cleared"]
1519        pub const _0: Self = Self::new(0);
1520
1521        #[doc = "Clears the FEF bit of the SSRmn register to 0"]
1522        pub const _1: Self = Self::new(1);
1523    }
1524}
1525#[doc(hidden)]
1526#[derive(Copy, Clone, Eq, PartialEq)]
1527pub struct Smr00_SPEC;
1528impl crate::sealed::RegSpec for Smr00_SPEC {
1529    type DataType = u16;
1530}
1531
1532#[doc = "Serial Mode Register 00"]
1533pub type Smr00 = crate::RegValueT<Smr00_SPEC>;
1534
1535impl Smr00 {
1536    #[doc = "Selection of Channel n Interrupt Source"]
1537    #[inline(always)]
1538    pub fn md0(
1539        self,
1540    ) -> crate::common::RegisterField<
1541        0,
1542        0x1,
1543        1,
1544        0,
1545        smr00::Md0,
1546        smr00::Md0,
1547        Smr00_SPEC,
1548        crate::common::RW,
1549    > {
1550        crate::common::RegisterField::<
1551            0,
1552            0x1,
1553            1,
1554            0,
1555            smr00::Md0,
1556            smr00::Md0,
1557            Smr00_SPEC,
1558            crate::common::RW,
1559        >::from_register(self, 0)
1560    }
1561
1562    #[doc = "Setting of Channel n Operation Mode"]
1563    #[inline(always)]
1564    pub fn md1(
1565        self,
1566    ) -> crate::common::RegisterField<
1567        1,
1568        0x3,
1569        1,
1570        0,
1571        smr00::Md1,
1572        smr00::Md1,
1573        Smr00_SPEC,
1574        crate::common::RW,
1575    > {
1576        crate::common::RegisterField::<
1577            1,
1578            0x3,
1579            1,
1580            0,
1581            smr00::Md1,
1582            smr00::Md1,
1583            Smr00_SPEC,
1584            crate::common::RW,
1585        >::from_register(self, 0)
1586    }
1587
1588    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
1589    #[inline(always)]
1590    pub fn ccs(
1591        self,
1592    ) -> crate::common::RegisterField<
1593        14,
1594        0x1,
1595        1,
1596        0,
1597        smr00::Ccs,
1598        smr00::Ccs,
1599        Smr00_SPEC,
1600        crate::common::RW,
1601    > {
1602        crate::common::RegisterField::<
1603            14,
1604            0x1,
1605            1,
1606            0,
1607            smr00::Ccs,
1608            smr00::Ccs,
1609            Smr00_SPEC,
1610            crate::common::RW,
1611        >::from_register(self, 0)
1612    }
1613
1614    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1615    #[inline(always)]
1616    pub fn cks(
1617        self,
1618    ) -> crate::common::RegisterField<
1619        15,
1620        0x1,
1621        1,
1622        0,
1623        smr00::Cks,
1624        smr00::Cks,
1625        Smr00_SPEC,
1626        crate::common::RW,
1627    > {
1628        crate::common::RegisterField::<
1629            15,
1630            0x1,
1631            1,
1632            0,
1633            smr00::Cks,
1634            smr00::Cks,
1635            Smr00_SPEC,
1636            crate::common::RW,
1637        >::from_register(self, 0)
1638    }
1639}
1640impl ::core::default::Default for Smr00 {
1641    #[inline(always)]
1642    fn default() -> Smr00 {
1643        <crate::RegValueT<Smr00_SPEC> as RegisterValue<_>>::new(32)
1644    }
1645}
1646pub mod smr00 {
1647
1648    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1649    pub struct Md0_SPEC;
1650    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
1651    impl Md0 {
1652        #[doc = "Transfer end interrupt"]
1653        pub const _0: Self = Self::new(0);
1654
1655        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
1656        pub const _1: Self = Self::new(1);
1657    }
1658    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1659    pub struct Md1_SPEC;
1660    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
1661    impl Md1 {
1662        #[doc = "Simplified SPI mode"]
1663        pub const _00: Self = Self::new(0);
1664
1665        #[doc = "UART mode"]
1666        pub const _01: Self = Self::new(1);
1667
1668        #[doc = "Simplified I2C mode"]
1669        pub const _10: Self = Self::new(2);
1670
1671        #[doc = "Setting prohibited"]
1672        pub const _11: Self = Self::new(3);
1673    }
1674    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1675    pub struct Ccs_SPEC;
1676    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1677    impl Ccs {
1678        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
1679        pub const _0: Self = Self::new(0);
1680
1681        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
1682        pub const _1: Self = Self::new(1);
1683    }
1684    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1685    pub struct Cks_SPEC;
1686    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1687    impl Cks {
1688        #[doc = "Operation clock CKm0 set by the SPSm register"]
1689        pub const _0: Self = Self::new(0);
1690
1691        #[doc = "Operation clock CKm1 set by the SPSm register"]
1692        pub const _1: Self = Self::new(1);
1693    }
1694}
1695#[doc(hidden)]
1696#[derive(Copy, Clone, Eq, PartialEq)]
1697pub struct Smr01_SPEC;
1698impl crate::sealed::RegSpec for Smr01_SPEC {
1699    type DataType = u16;
1700}
1701
1702#[doc = "Serial Mode Register 01"]
1703pub type Smr01 = crate::RegValueT<Smr01_SPEC>;
1704
1705impl Smr01 {
1706    #[doc = "Selection of Channel n Interrupt Source"]
1707    #[inline(always)]
1708    pub fn md0(
1709        self,
1710    ) -> crate::common::RegisterField<
1711        0,
1712        0x1,
1713        1,
1714        0,
1715        smr01::Md0,
1716        smr01::Md0,
1717        Smr01_SPEC,
1718        crate::common::RW,
1719    > {
1720        crate::common::RegisterField::<
1721            0,
1722            0x1,
1723            1,
1724            0,
1725            smr01::Md0,
1726            smr01::Md0,
1727            Smr01_SPEC,
1728            crate::common::RW,
1729        >::from_register(self, 0)
1730    }
1731
1732    #[doc = "Setting of Channel n Operation Mode"]
1733    #[inline(always)]
1734    pub fn md1(
1735        self,
1736    ) -> crate::common::RegisterField<
1737        1,
1738        0x3,
1739        1,
1740        0,
1741        smr01::Md1,
1742        smr01::Md1,
1743        Smr01_SPEC,
1744        crate::common::RW,
1745    > {
1746        crate::common::RegisterField::<
1747            1,
1748            0x3,
1749            1,
1750            0,
1751            smr01::Md1,
1752            smr01::Md1,
1753            Smr01_SPEC,
1754            crate::common::RW,
1755        >::from_register(self, 0)
1756    }
1757
1758    #[doc = "Controls Inversion of Level of Channel n Receive Data in UART Mode"]
1759    #[inline(always)]
1760    pub fn sis0(
1761        self,
1762    ) -> crate::common::RegisterField<
1763        6,
1764        0x1,
1765        1,
1766        0,
1767        smr01::Sis0,
1768        smr01::Sis0,
1769        Smr01_SPEC,
1770        crate::common::RW,
1771    > {
1772        crate::common::RegisterField::<
1773            6,
1774            0x1,
1775            1,
1776            0,
1777            smr01::Sis0,
1778            smr01::Sis0,
1779            Smr01_SPEC,
1780            crate::common::RW,
1781        >::from_register(self, 0)
1782    }
1783
1784    #[doc = "Selection of Start Trigger Source"]
1785    #[inline(always)]
1786    pub fn sts(
1787        self,
1788    ) -> crate::common::RegisterField<
1789        8,
1790        0x1,
1791        1,
1792        0,
1793        smr01::Sts,
1794        smr01::Sts,
1795        Smr01_SPEC,
1796        crate::common::RW,
1797    > {
1798        crate::common::RegisterField::<
1799            8,
1800            0x1,
1801            1,
1802            0,
1803            smr01::Sts,
1804            smr01::Sts,
1805            Smr01_SPEC,
1806            crate::common::RW,
1807        >::from_register(self, 0)
1808    }
1809
1810    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
1811    #[inline(always)]
1812    pub fn ccs(
1813        self,
1814    ) -> crate::common::RegisterField<
1815        14,
1816        0x1,
1817        1,
1818        0,
1819        smr01::Ccs,
1820        smr01::Ccs,
1821        Smr01_SPEC,
1822        crate::common::RW,
1823    > {
1824        crate::common::RegisterField::<
1825            14,
1826            0x1,
1827            1,
1828            0,
1829            smr01::Ccs,
1830            smr01::Ccs,
1831            Smr01_SPEC,
1832            crate::common::RW,
1833        >::from_register(self, 0)
1834    }
1835
1836    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
1837    #[inline(always)]
1838    pub fn cks(
1839        self,
1840    ) -> crate::common::RegisterField<
1841        15,
1842        0x1,
1843        1,
1844        0,
1845        smr01::Cks,
1846        smr01::Cks,
1847        Smr01_SPEC,
1848        crate::common::RW,
1849    > {
1850        crate::common::RegisterField::<
1851            15,
1852            0x1,
1853            1,
1854            0,
1855            smr01::Cks,
1856            smr01::Cks,
1857            Smr01_SPEC,
1858            crate::common::RW,
1859        >::from_register(self, 0)
1860    }
1861}
1862impl ::core::default::Default for Smr01 {
1863    #[inline(always)]
1864    fn default() -> Smr01 {
1865        <crate::RegValueT<Smr01_SPEC> as RegisterValue<_>>::new(32)
1866    }
1867}
1868pub mod smr01 {
1869
1870    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1871    pub struct Md0_SPEC;
1872    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
1873    impl Md0 {
1874        #[doc = "Transfer end interrupt"]
1875        pub const _0: Self = Self::new(0);
1876
1877        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
1878        pub const _1: Self = Self::new(1);
1879    }
1880    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1881    pub struct Md1_SPEC;
1882    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
1883    impl Md1 {
1884        #[doc = "Simplified SPI mode"]
1885        pub const _00: Self = Self::new(0);
1886
1887        #[doc = "UART mode"]
1888        pub const _01: Self = Self::new(1);
1889
1890        #[doc = "Simplified I2C mode"]
1891        pub const _10: Self = Self::new(2);
1892
1893        #[doc = "Setting prohibited"]
1894        pub const _11: Self = Self::new(3);
1895    }
1896    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1897    pub struct Sis0_SPEC;
1898    pub type Sis0 = crate::EnumBitfieldStruct<u8, Sis0_SPEC>;
1899    impl Sis0 {
1900        #[doc = "Falling edge is detected as the start bit. The input communication data is captured as is."]
1901        pub const _0: Self = Self::new(0);
1902
1903        #[doc = "Rising edge is detected as the start bit. The input communication data is inverted and captured."]
1904        pub const _1: Self = Self::new(1);
1905    }
1906    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1907    pub struct Sts_SPEC;
1908    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
1909    impl Sts {
1910        #[doc = "Only software trigger is valid (selected for simplified SPI, UART transmission, and simplified I2C)"]
1911        pub const _0: Self = Self::new(0);
1912
1913        #[doc = "Valid edge of the RXDq pin (selected for UART reception)"]
1914        pub const _1: Self = Self::new(1);
1915    }
1916    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1917    pub struct Ccs_SPEC;
1918    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
1919    impl Ccs {
1920        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
1921        pub const _0: Self = Self::new(0);
1922
1923        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
1924        pub const _1: Self = Self::new(1);
1925    }
1926    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
1927    pub struct Cks_SPEC;
1928    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
1929    impl Cks {
1930        #[doc = "Operation clock CKm0 set by the SPSm register"]
1931        pub const _0: Self = Self::new(0);
1932
1933        #[doc = "Operation clock CKm1 set by the SPSm register"]
1934        pub const _1: Self = Self::new(1);
1935    }
1936}
1937#[doc(hidden)]
1938#[derive(Copy, Clone, Eq, PartialEq)]
1939pub struct Smr02_SPEC;
1940impl crate::sealed::RegSpec for Smr02_SPEC {
1941    type DataType = u16;
1942}
1943
1944#[doc = "Serial Mode Register 02"]
1945pub type Smr02 = crate::RegValueT<Smr02_SPEC>;
1946
1947impl Smr02 {
1948    #[doc = "Selection of Channel n Interrupt Source"]
1949    #[inline(always)]
1950    pub fn md0(
1951        self,
1952    ) -> crate::common::RegisterField<
1953        0,
1954        0x1,
1955        1,
1956        0,
1957        smr02::Md0,
1958        smr02::Md0,
1959        Smr02_SPEC,
1960        crate::common::RW,
1961    > {
1962        crate::common::RegisterField::<
1963            0,
1964            0x1,
1965            1,
1966            0,
1967            smr02::Md0,
1968            smr02::Md0,
1969            Smr02_SPEC,
1970            crate::common::RW,
1971        >::from_register(self, 0)
1972    }
1973
1974    #[doc = "Setting of Channel n Operation Mode"]
1975    #[inline(always)]
1976    pub fn md1(
1977        self,
1978    ) -> crate::common::RegisterField<
1979        1,
1980        0x3,
1981        1,
1982        0,
1983        smr02::Md1,
1984        smr02::Md1,
1985        Smr02_SPEC,
1986        crate::common::RW,
1987    > {
1988        crate::common::RegisterField::<
1989            1,
1990            0x3,
1991            1,
1992            0,
1993            smr02::Md1,
1994            smr02::Md1,
1995            Smr02_SPEC,
1996            crate::common::RW,
1997        >::from_register(self, 0)
1998    }
1999
2000    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
2001    #[inline(always)]
2002    pub fn ccs(
2003        self,
2004    ) -> crate::common::RegisterField<
2005        14,
2006        0x1,
2007        1,
2008        0,
2009        smr02::Ccs,
2010        smr02::Ccs,
2011        Smr02_SPEC,
2012        crate::common::RW,
2013    > {
2014        crate::common::RegisterField::<
2015            14,
2016            0x1,
2017            1,
2018            0,
2019            smr02::Ccs,
2020            smr02::Ccs,
2021            Smr02_SPEC,
2022            crate::common::RW,
2023        >::from_register(self, 0)
2024    }
2025
2026    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
2027    #[inline(always)]
2028    pub fn cks(
2029        self,
2030    ) -> crate::common::RegisterField<
2031        15,
2032        0x1,
2033        1,
2034        0,
2035        smr02::Cks,
2036        smr02::Cks,
2037        Smr02_SPEC,
2038        crate::common::RW,
2039    > {
2040        crate::common::RegisterField::<
2041            15,
2042            0x1,
2043            1,
2044            0,
2045            smr02::Cks,
2046            smr02::Cks,
2047            Smr02_SPEC,
2048            crate::common::RW,
2049        >::from_register(self, 0)
2050    }
2051}
2052impl ::core::default::Default for Smr02 {
2053    #[inline(always)]
2054    fn default() -> Smr02 {
2055        <crate::RegValueT<Smr02_SPEC> as RegisterValue<_>>::new(32)
2056    }
2057}
2058pub mod smr02 {
2059
2060    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2061    pub struct Md0_SPEC;
2062    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
2063    impl Md0 {
2064        #[doc = "Transfer end interrupt"]
2065        pub const _0: Self = Self::new(0);
2066
2067        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
2068        pub const _1: Self = Self::new(1);
2069    }
2070    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2071    pub struct Md1_SPEC;
2072    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
2073    impl Md1 {
2074        #[doc = "Simplified SPI mode"]
2075        pub const _00: Self = Self::new(0);
2076
2077        #[doc = "UART mode"]
2078        pub const _01: Self = Self::new(1);
2079
2080        #[doc = "Simplified I2C mode"]
2081        pub const _10: Self = Self::new(2);
2082
2083        #[doc = "Setting prohibited"]
2084        pub const _11: Self = Self::new(3);
2085    }
2086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2087    pub struct Ccs_SPEC;
2088    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2089    impl Ccs {
2090        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
2091        pub const _0: Self = Self::new(0);
2092
2093        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
2094        pub const _1: Self = Self::new(1);
2095    }
2096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2097    pub struct Cks_SPEC;
2098    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2099    impl Cks {
2100        #[doc = "Operation clock CKm0 set by the SPSm register"]
2101        pub const _0: Self = Self::new(0);
2102
2103        #[doc = "Operation clock CKm1 set by the SPSm register"]
2104        pub const _1: Self = Self::new(1);
2105    }
2106}
2107#[doc(hidden)]
2108#[derive(Copy, Clone, Eq, PartialEq)]
2109pub struct Smr03_SPEC;
2110impl crate::sealed::RegSpec for Smr03_SPEC {
2111    type DataType = u16;
2112}
2113
2114#[doc = "Serial Mode Register 03"]
2115pub type Smr03 = crate::RegValueT<Smr03_SPEC>;
2116
2117impl Smr03 {
2118    #[doc = "Selection of Channel n Interrupt Source"]
2119    #[inline(always)]
2120    pub fn md0(
2121        self,
2122    ) -> crate::common::RegisterField<
2123        0,
2124        0x1,
2125        1,
2126        0,
2127        smr03::Md0,
2128        smr03::Md0,
2129        Smr03_SPEC,
2130        crate::common::RW,
2131    > {
2132        crate::common::RegisterField::<
2133            0,
2134            0x1,
2135            1,
2136            0,
2137            smr03::Md0,
2138            smr03::Md0,
2139            Smr03_SPEC,
2140            crate::common::RW,
2141        >::from_register(self, 0)
2142    }
2143
2144    #[doc = "Setting of Channel n Operation Mode"]
2145    #[inline(always)]
2146    pub fn md1(
2147        self,
2148    ) -> crate::common::RegisterField<
2149        1,
2150        0x3,
2151        1,
2152        0,
2153        smr03::Md1,
2154        smr03::Md1,
2155        Smr03_SPEC,
2156        crate::common::RW,
2157    > {
2158        crate::common::RegisterField::<
2159            1,
2160            0x3,
2161            1,
2162            0,
2163            smr03::Md1,
2164            smr03::Md1,
2165            Smr03_SPEC,
2166            crate::common::RW,
2167        >::from_register(self, 0)
2168    }
2169
2170    #[doc = "Controls Inversion of Level of Channel n Receive Data in UART Mode"]
2171    #[inline(always)]
2172    pub fn sis0(
2173        self,
2174    ) -> crate::common::RegisterField<
2175        6,
2176        0x1,
2177        1,
2178        0,
2179        smr03::Sis0,
2180        smr03::Sis0,
2181        Smr03_SPEC,
2182        crate::common::RW,
2183    > {
2184        crate::common::RegisterField::<
2185            6,
2186            0x1,
2187            1,
2188            0,
2189            smr03::Sis0,
2190            smr03::Sis0,
2191            Smr03_SPEC,
2192            crate::common::RW,
2193        >::from_register(self, 0)
2194    }
2195
2196    #[doc = "Selection of Start Trigger Source"]
2197    #[inline(always)]
2198    pub fn sts(
2199        self,
2200    ) -> crate::common::RegisterField<
2201        8,
2202        0x1,
2203        1,
2204        0,
2205        smr03::Sts,
2206        smr03::Sts,
2207        Smr03_SPEC,
2208        crate::common::RW,
2209    > {
2210        crate::common::RegisterField::<
2211            8,
2212            0x1,
2213            1,
2214            0,
2215            smr03::Sts,
2216            smr03::Sts,
2217            Smr03_SPEC,
2218            crate::common::RW,
2219        >::from_register(self, 0)
2220    }
2221
2222    #[doc = "Selection of Transfer Clock (fTCLK) of Channel n"]
2223    #[inline(always)]
2224    pub fn ccs(
2225        self,
2226    ) -> crate::common::RegisterField<
2227        14,
2228        0x1,
2229        1,
2230        0,
2231        smr03::Ccs,
2232        smr03::Ccs,
2233        Smr03_SPEC,
2234        crate::common::RW,
2235    > {
2236        crate::common::RegisterField::<
2237            14,
2238            0x1,
2239            1,
2240            0,
2241            smr03::Ccs,
2242            smr03::Ccs,
2243            Smr03_SPEC,
2244            crate::common::RW,
2245        >::from_register(self, 0)
2246    }
2247
2248    #[doc = "Selection of Operation Clock (fMCK) of Channel n"]
2249    #[inline(always)]
2250    pub fn cks(
2251        self,
2252    ) -> crate::common::RegisterField<
2253        15,
2254        0x1,
2255        1,
2256        0,
2257        smr03::Cks,
2258        smr03::Cks,
2259        Smr03_SPEC,
2260        crate::common::RW,
2261    > {
2262        crate::common::RegisterField::<
2263            15,
2264            0x1,
2265            1,
2266            0,
2267            smr03::Cks,
2268            smr03::Cks,
2269            Smr03_SPEC,
2270            crate::common::RW,
2271        >::from_register(self, 0)
2272    }
2273}
2274impl ::core::default::Default for Smr03 {
2275    #[inline(always)]
2276    fn default() -> Smr03 {
2277        <crate::RegValueT<Smr03_SPEC> as RegisterValue<_>>::new(32)
2278    }
2279}
2280pub mod smr03 {
2281
2282    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2283    pub struct Md0_SPEC;
2284    pub type Md0 = crate::EnumBitfieldStruct<u8, Md0_SPEC>;
2285    impl Md0 {
2286        #[doc = "Transfer end interrupt"]
2287        pub const _0: Self = Self::new(0);
2288
2289        #[doc = "Buffer empty interrupt (Occurs when data is transferred from the SDRmn register to the shift register.)"]
2290        pub const _1: Self = Self::new(1);
2291    }
2292    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2293    pub struct Md1_SPEC;
2294    pub type Md1 = crate::EnumBitfieldStruct<u8, Md1_SPEC>;
2295    impl Md1 {
2296        #[doc = "Simplified SPI mode"]
2297        pub const _00: Self = Self::new(0);
2298
2299        #[doc = "UART mode"]
2300        pub const _01: Self = Self::new(1);
2301
2302        #[doc = "Simplified I2C mode"]
2303        pub const _10: Self = Self::new(2);
2304
2305        #[doc = "Setting prohibited"]
2306        pub const _11: Self = Self::new(3);
2307    }
2308    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2309    pub struct Sis0_SPEC;
2310    pub type Sis0 = crate::EnumBitfieldStruct<u8, Sis0_SPEC>;
2311    impl Sis0 {
2312        #[doc = "Falling edge is detected as the start bit. The input communication data is captured as is."]
2313        pub const _0: Self = Self::new(0);
2314
2315        #[doc = "Rising edge is detected as the start bit. The input communication data is inverted and captured."]
2316        pub const _1: Self = Self::new(1);
2317    }
2318    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2319    pub struct Sts_SPEC;
2320    pub type Sts = crate::EnumBitfieldStruct<u8, Sts_SPEC>;
2321    impl Sts {
2322        #[doc = "Only software trigger is valid (selected for simplified SPI, UART transmission, and simplified I2C)"]
2323        pub const _0: Self = Self::new(0);
2324
2325        #[doc = "Valid edge of the RXDq pin (selected for UART reception)"]
2326        pub const _1: Self = Self::new(1);
2327    }
2328    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2329    pub struct Ccs_SPEC;
2330    pub type Ccs = crate::EnumBitfieldStruct<u8, Ccs_SPEC>;
2331    impl Ccs {
2332        #[doc = "Divided operation clock fMCK specified by the CKS bit"]
2333        pub const _0: Self = Self::new(0);
2334
2335        #[doc = "Clock input fSCK from the SCKp pin (slave transfer in simplified SPI mode)"]
2336        pub const _1: Self = Self::new(1);
2337    }
2338    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2339    pub struct Cks_SPEC;
2340    pub type Cks = crate::EnumBitfieldStruct<u8, Cks_SPEC>;
2341    impl Cks {
2342        #[doc = "Operation clock CKm0 set by the SPSm register"]
2343        pub const _0: Self = Self::new(0);
2344
2345        #[doc = "Operation clock CKm1 set by the SPSm register"]
2346        pub const _1: Self = Self::new(1);
2347    }
2348}
2349#[doc(hidden)]
2350#[derive(Copy, Clone, Eq, PartialEq)]
2351pub struct Scr00_SPEC;
2352impl crate::sealed::RegSpec for Scr00_SPEC {
2353    type DataType = u16;
2354}
2355
2356#[doc = "Serial Communication Operation Setting Register 00"]
2357pub type Scr00 = crate::RegValueT<Scr00_SPEC>;
2358
2359impl Scr00 {
2360    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
2361    #[inline(always)]
2362    pub fn dls(
2363        self,
2364    ) -> crate::common::RegisterField<
2365        0,
2366        0x3,
2367        1,
2368        0,
2369        scr00::Dls,
2370        scr00::Dls,
2371        Scr00_SPEC,
2372        crate::common::RW,
2373    > {
2374        crate::common::RegisterField::<
2375            0,
2376            0x3,
2377            1,
2378            0,
2379            scr00::Dls,
2380            scr00::Dls,
2381            Scr00_SPEC,
2382            crate::common::RW,
2383        >::from_register(self, 0)
2384    }
2385
2386    #[doc = "Setting of Stop Bit in UART Mode"]
2387    #[inline(always)]
2388    pub fn slc(
2389        self,
2390    ) -> crate::common::RegisterField<
2391        4,
2392        0x3,
2393        1,
2394        0,
2395        scr00::Slc,
2396        scr00::Slc,
2397        Scr00_SPEC,
2398        crate::common::RW,
2399    > {
2400        crate::common::RegisterField::<
2401            4,
2402            0x3,
2403            1,
2404            0,
2405            scr00::Slc,
2406            scr00::Slc,
2407            Scr00_SPEC,
2408            crate::common::RW,
2409        >::from_register(self, 0)
2410    }
2411
2412    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
2413    #[inline(always)]
2414    pub fn dir(
2415        self,
2416    ) -> crate::common::RegisterField<
2417        7,
2418        0x1,
2419        1,
2420        0,
2421        scr00::Dir,
2422        scr00::Dir,
2423        Scr00_SPEC,
2424        crate::common::RW,
2425    > {
2426        crate::common::RegisterField::<
2427            7,
2428            0x1,
2429            1,
2430            0,
2431            scr00::Dir,
2432            scr00::Dir,
2433            Scr00_SPEC,
2434            crate::common::RW,
2435        >::from_register(self, 0)
2436    }
2437
2438    #[doc = "Setting of Parity Bit in UART Mode"]
2439    #[inline(always)]
2440    pub fn ptc(
2441        self,
2442    ) -> crate::common::RegisterField<
2443        8,
2444        0x3,
2445        1,
2446        0,
2447        scr00::Ptc,
2448        scr00::Ptc,
2449        Scr00_SPEC,
2450        crate::common::RW,
2451    > {
2452        crate::common::RegisterField::<
2453            8,
2454            0x3,
2455            1,
2456            0,
2457            scr00::Ptc,
2458            scr00::Ptc,
2459            Scr00_SPEC,
2460            crate::common::RW,
2461        >::from_register(self, 0)
2462    }
2463
2464    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
2465    #[inline(always)]
2466    pub fn dcp(
2467        self,
2468    ) -> crate::common::RegisterField<
2469        12,
2470        0x3,
2471        1,
2472        0,
2473        scr00::Dcp,
2474        scr00::Dcp,
2475        Scr00_SPEC,
2476        crate::common::RW,
2477    > {
2478        crate::common::RegisterField::<
2479            12,
2480            0x3,
2481            1,
2482            0,
2483            scr00::Dcp,
2484            scr00::Dcp,
2485            Scr00_SPEC,
2486            crate::common::RW,
2487        >::from_register(self, 0)
2488    }
2489
2490    #[doc = "Setting of Channel 0 Operation Mode"]
2491    #[inline(always)]
2492    pub fn trxe(
2493        self,
2494    ) -> crate::common::RegisterField<
2495        14,
2496        0x3,
2497        1,
2498        0,
2499        scr00::Trxe,
2500        scr00::Trxe,
2501        Scr00_SPEC,
2502        crate::common::RW,
2503    > {
2504        crate::common::RegisterField::<
2505            14,
2506            0x3,
2507            1,
2508            0,
2509            scr00::Trxe,
2510            scr00::Trxe,
2511            Scr00_SPEC,
2512            crate::common::RW,
2513        >::from_register(self, 0)
2514    }
2515}
2516impl ::core::default::Default for Scr00 {
2517    #[inline(always)]
2518    fn default() -> Scr00 {
2519        <crate::RegValueT<Scr00_SPEC> as RegisterValue<_>>::new(135)
2520    }
2521}
2522pub mod scr00 {
2523
2524    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2525    pub struct Dls_SPEC;
2526    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
2527    impl Dls {
2528        #[doc = "Setting prohibited"]
2529        pub const _00: Self = Self::new(0);
2530
2531        #[doc = "9-bit data length (stored in bits 0 to 8 of the SDRm0 register) (settable in UART mode only)"]
2532        pub const _01: Self = Self::new(1);
2533
2534        #[doc = "7-bit data length (stored in bits 0 to 6 of the SDRm0 register)"]
2535        pub const _10: Self = Self::new(2);
2536
2537        #[doc = "8-bit data length (stored in bits 0 to 7 of the SDRm0 register)"]
2538        pub const _11: Self = Self::new(3);
2539    }
2540    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2541    pub struct Slc_SPEC;
2542    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
2543    impl Slc {
2544        #[doc = "No stop bit"]
2545        pub const _00: Self = Self::new(0);
2546
2547        #[doc = "Stop bit length = 1 bit"]
2548        pub const _01: Self = Self::new(1);
2549
2550        #[doc = "Stop bit length = 2 bits"]
2551        pub const _10: Self = Self::new(2);
2552
2553        #[doc = "Setting prohibited"]
2554        pub const _11: Self = Self::new(3);
2555    }
2556    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2557    pub struct Dir_SPEC;
2558    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
2559    impl Dir {
2560        #[doc = "Inputs or outputs data with MSB first"]
2561        pub const _0: Self = Self::new(0);
2562
2563        #[doc = "Inputs or outputs data with LSB first"]
2564        pub const _1: Self = Self::new(1);
2565    }
2566    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2567    pub struct Ptc_SPEC;
2568    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
2569    impl Ptc {
2570        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
2571        pub const _00: Self = Self::new(0);
2572
2573        #[doc = "Transmission: Outputs 0 parity Reception: No parity determination"]
2574        pub const _01: Self = Self::new(1);
2575
2576        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
2577        pub const _10: Self = Self::new(2);
2578
2579        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
2580        pub const _11: Self = Self::new(3);
2581    }
2582    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2583    pub struct Dcp_SPEC;
2584    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
2585    impl Dcp {
2586        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
2587        pub const _00: Self = Self::new(0);
2588
2589        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
2590        pub const _01: Self = Self::new(1);
2591
2592        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
2593        pub const _10: Self = Self::new(2);
2594
2595        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
2596        pub const _11: Self = Self::new(3);
2597    }
2598    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2599    pub struct Trxe_SPEC;
2600    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
2601    impl Trxe {
2602        #[doc = "Disable communication"]
2603        pub const _00: Self = Self::new(0);
2604
2605        #[doc = "Reception only"]
2606        pub const _01: Self = Self::new(1);
2607
2608        #[doc = "Transmission only"]
2609        pub const _10: Self = Self::new(2);
2610
2611        #[doc = "Transmission and reception"]
2612        pub const _11: Self = Self::new(3);
2613    }
2614}
2615#[doc(hidden)]
2616#[derive(Copy, Clone, Eq, PartialEq)]
2617pub struct Scr01_SPEC;
2618impl crate::sealed::RegSpec for Scr01_SPEC {
2619    type DataType = u16;
2620}
2621
2622#[doc = "Serial Communication Operation Setting Register 01"]
2623pub type Scr01 = crate::RegValueT<Scr01_SPEC>;
2624
2625impl Scr01 {
2626    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
2627    #[inline(always)]
2628    pub fn dls(
2629        self,
2630    ) -> crate::common::RegisterField<
2631        0,
2632        0x3,
2633        1,
2634        0,
2635        scr01::Dls,
2636        scr01::Dls,
2637        Scr01_SPEC,
2638        crate::common::RW,
2639    > {
2640        crate::common::RegisterField::<
2641            0,
2642            0x3,
2643            1,
2644            0,
2645            scr01::Dls,
2646            scr01::Dls,
2647            Scr01_SPEC,
2648            crate::common::RW,
2649        >::from_register(self, 0)
2650    }
2651
2652    #[doc = "Setting of Stop Bit in UART Mode"]
2653    #[inline(always)]
2654    pub fn slc(
2655        self,
2656    ) -> crate::common::RegisterField<
2657        4,
2658        0x1,
2659        1,
2660        0,
2661        scr01::Slc,
2662        scr01::Slc,
2663        Scr01_SPEC,
2664        crate::common::RW,
2665    > {
2666        crate::common::RegisterField::<
2667            4,
2668            0x1,
2669            1,
2670            0,
2671            scr01::Slc,
2672            scr01::Slc,
2673            Scr01_SPEC,
2674            crate::common::RW,
2675        >::from_register(self, 0)
2676    }
2677
2678    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
2679    #[inline(always)]
2680    pub fn dir(
2681        self,
2682    ) -> crate::common::RegisterField<
2683        7,
2684        0x1,
2685        1,
2686        0,
2687        scr01::Dir,
2688        scr01::Dir,
2689        Scr01_SPEC,
2690        crate::common::RW,
2691    > {
2692        crate::common::RegisterField::<
2693            7,
2694            0x1,
2695            1,
2696            0,
2697            scr01::Dir,
2698            scr01::Dir,
2699            Scr01_SPEC,
2700            crate::common::RW,
2701        >::from_register(self, 0)
2702    }
2703
2704    #[doc = "Setting of Parity Bit in UART Mode"]
2705    #[inline(always)]
2706    pub fn ptc(
2707        self,
2708    ) -> crate::common::RegisterField<
2709        8,
2710        0x3,
2711        1,
2712        0,
2713        scr01::Ptc,
2714        scr01::Ptc,
2715        Scr01_SPEC,
2716        crate::common::RW,
2717    > {
2718        crate::common::RegisterField::<
2719            8,
2720            0x3,
2721            1,
2722            0,
2723            scr01::Ptc,
2724            scr01::Ptc,
2725            Scr01_SPEC,
2726            crate::common::RW,
2727        >::from_register(self, 0)
2728    }
2729
2730    #[doc = "Mask Control of Error Interrupt Signal SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1)"]
2731    #[inline(always)]
2732    pub fn eoc(
2733        self,
2734    ) -> crate::common::RegisterField<
2735        10,
2736        0x1,
2737        1,
2738        0,
2739        scr01::Eoc,
2740        scr01::Eoc,
2741        Scr01_SPEC,
2742        crate::common::RW,
2743    > {
2744        crate::common::RegisterField::<
2745            10,
2746            0x1,
2747            1,
2748            0,
2749            scr01::Eoc,
2750            scr01::Eoc,
2751            Scr01_SPEC,
2752            crate::common::RW,
2753        >::from_register(self, 0)
2754    }
2755
2756    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
2757    #[inline(always)]
2758    pub fn dcp(
2759        self,
2760    ) -> crate::common::RegisterField<
2761        12,
2762        0x3,
2763        1,
2764        0,
2765        scr01::Dcp,
2766        scr01::Dcp,
2767        Scr01_SPEC,
2768        crate::common::RW,
2769    > {
2770        crate::common::RegisterField::<
2771            12,
2772            0x3,
2773            1,
2774            0,
2775            scr01::Dcp,
2776            scr01::Dcp,
2777            Scr01_SPEC,
2778            crate::common::RW,
2779        >::from_register(self, 0)
2780    }
2781
2782    #[doc = "Setting of Channel 1 Operation Mode"]
2783    #[inline(always)]
2784    pub fn trxe(
2785        self,
2786    ) -> crate::common::RegisterField<
2787        14,
2788        0x3,
2789        1,
2790        0,
2791        scr01::Trxe,
2792        scr01::Trxe,
2793        Scr01_SPEC,
2794        crate::common::RW,
2795    > {
2796        crate::common::RegisterField::<
2797            14,
2798            0x3,
2799            1,
2800            0,
2801            scr01::Trxe,
2802            scr01::Trxe,
2803            Scr01_SPEC,
2804            crate::common::RW,
2805        >::from_register(self, 0)
2806    }
2807}
2808impl ::core::default::Default for Scr01 {
2809    #[inline(always)]
2810    fn default() -> Scr01 {
2811        <crate::RegValueT<Scr01_SPEC> as RegisterValue<_>>::new(135)
2812    }
2813}
2814pub mod scr01 {
2815
2816    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2817    pub struct Dls_SPEC;
2818    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
2819    impl Dls {
2820        #[doc = "Setting prohibited"]
2821        pub const _00: Self = Self::new(0);
2822
2823        #[doc = "9-bit data length (stored in the DAT\\[8:0\\] bits of the SDRm1 register) (settable in UART mode only)"]
2824        pub const _01: Self = Self::new(1);
2825
2826        #[doc = "7-bit data length (stored in the DAT\\[6:0\\] bits of the SDRm1 register)"]
2827        pub const _10: Self = Self::new(2);
2828
2829        #[doc = "8-bit data length (stored in the DAT\\[7:0\\] bits of the SDRm1 register)"]
2830        pub const _11: Self = Self::new(3);
2831    }
2832    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2833    pub struct Slc_SPEC;
2834    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
2835    impl Slc {
2836        #[doc = "No stop bit"]
2837        pub const _0: Self = Self::new(0);
2838
2839        #[doc = "Stop bit length = 1 bit"]
2840        pub const _1: Self = Self::new(1);
2841    }
2842    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2843    pub struct Dir_SPEC;
2844    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
2845    impl Dir {
2846        #[doc = "Inputs or outputs data with MSB first"]
2847        pub const _0: Self = Self::new(0);
2848
2849        #[doc = "Inputs or outputs data with LSB first"]
2850        pub const _1: Self = Self::new(1);
2851    }
2852    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2853    pub struct Ptc_SPEC;
2854    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
2855    impl Ptc {
2856        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
2857        pub const _00: Self = Self::new(0);
2858
2859        #[doc = "Transmission: Outputs 0 parity Reception: No parity judgment"]
2860        pub const _01: Self = Self::new(1);
2861
2862        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
2863        pub const _10: Self = Self::new(2);
2864
2865        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
2866        pub const _11: Self = Self::new(3);
2867    }
2868    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2869    pub struct Eoc_SPEC;
2870    pub type Eoc = crate::EnumBitfieldStruct<u8, Eoc_SPEC>;
2871    impl Eoc {
2872        #[doc = "Disables generation of error interrupt SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) (SAUm_UART_RXIq is generated)"]
2873        pub const _0: Self = Self::new(0);
2874
2875        #[doc = "Enables generation of error interrupt SAU0_UART_ERRI0 (m = 0), SAU1_UART_ERRI2 (m = 1) (SAUm_UART_RXIq is not generated if an error occurs)"]
2876        pub const _1: Self = Self::new(1);
2877    }
2878    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2879    pub struct Dcp_SPEC;
2880    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
2881    impl Dcp {
2882        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
2883        pub const _00: Self = Self::new(0);
2884
2885        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
2886        pub const _01: Self = Self::new(1);
2887
2888        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
2889        pub const _10: Self = Self::new(2);
2890
2891        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
2892        pub const _11: Self = Self::new(3);
2893    }
2894    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
2895    pub struct Trxe_SPEC;
2896    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
2897    impl Trxe {
2898        #[doc = "Disable communication"]
2899        pub const _00: Self = Self::new(0);
2900
2901        #[doc = "Reception only"]
2902        pub const _01: Self = Self::new(1);
2903
2904        #[doc = "Transmission only"]
2905        pub const _10: Self = Self::new(2);
2906
2907        #[doc = "Transmission and reception"]
2908        pub const _11: Self = Self::new(3);
2909    }
2910}
2911#[doc(hidden)]
2912#[derive(Copy, Clone, Eq, PartialEq)]
2913pub struct Scr02_SPEC;
2914impl crate::sealed::RegSpec for Scr02_SPEC {
2915    type DataType = u16;
2916}
2917
2918#[doc = "Serial Communication Operation Setting Register 02"]
2919pub type Scr02 = crate::RegValueT<Scr02_SPEC>;
2920
2921impl Scr02 {
2922    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
2923    #[inline(always)]
2924    pub fn dls(
2925        self,
2926    ) -> crate::common::RegisterField<
2927        0,
2928        0x1,
2929        1,
2930        0,
2931        scr02::Dls,
2932        scr02::Dls,
2933        Scr02_SPEC,
2934        crate::common::RW,
2935    > {
2936        crate::common::RegisterField::<
2937            0,
2938            0x1,
2939            1,
2940            0,
2941            scr02::Dls,
2942            scr02::Dls,
2943            Scr02_SPEC,
2944            crate::common::RW,
2945        >::from_register(self, 0)
2946    }
2947
2948    #[doc = "Setting of Stop Bit in UART Mode"]
2949    #[inline(always)]
2950    pub fn slc(
2951        self,
2952    ) -> crate::common::RegisterField<
2953        4,
2954        0x3,
2955        1,
2956        0,
2957        scr02::Slc,
2958        scr02::Slc,
2959        Scr02_SPEC,
2960        crate::common::RW,
2961    > {
2962        crate::common::RegisterField::<
2963            4,
2964            0x3,
2965            1,
2966            0,
2967            scr02::Slc,
2968            scr02::Slc,
2969            Scr02_SPEC,
2970            crate::common::RW,
2971        >::from_register(self, 0)
2972    }
2973
2974    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
2975    #[inline(always)]
2976    pub fn dir(
2977        self,
2978    ) -> crate::common::RegisterField<
2979        7,
2980        0x1,
2981        1,
2982        0,
2983        scr02::Dir,
2984        scr02::Dir,
2985        Scr02_SPEC,
2986        crate::common::RW,
2987    > {
2988        crate::common::RegisterField::<
2989            7,
2990            0x1,
2991            1,
2992            0,
2993            scr02::Dir,
2994            scr02::Dir,
2995            Scr02_SPEC,
2996            crate::common::RW,
2997        >::from_register(self, 0)
2998    }
2999
3000    #[doc = "Setting of Parity Bit in UART Mode"]
3001    #[inline(always)]
3002    pub fn ptc(
3003        self,
3004    ) -> crate::common::RegisterField<
3005        8,
3006        0x3,
3007        1,
3008        0,
3009        scr02::Ptc,
3010        scr02::Ptc,
3011        Scr02_SPEC,
3012        crate::common::RW,
3013    > {
3014        crate::common::RegisterField::<
3015            8,
3016            0x3,
3017            1,
3018            0,
3019            scr02::Ptc,
3020            scr02::Ptc,
3021            Scr02_SPEC,
3022            crate::common::RW,
3023        >::from_register(self, 0)
3024    }
3025
3026    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
3027    #[inline(always)]
3028    pub fn dcp(
3029        self,
3030    ) -> crate::common::RegisterField<
3031        12,
3032        0x3,
3033        1,
3034        0,
3035        scr02::Dcp,
3036        scr02::Dcp,
3037        Scr02_SPEC,
3038        crate::common::RW,
3039    > {
3040        crate::common::RegisterField::<
3041            12,
3042            0x3,
3043            1,
3044            0,
3045            scr02::Dcp,
3046            scr02::Dcp,
3047            Scr02_SPEC,
3048            crate::common::RW,
3049        >::from_register(self, 0)
3050    }
3051
3052    #[doc = "Setting of Channel 2 Operation Mode"]
3053    #[inline(always)]
3054    pub fn trxe(
3055        self,
3056    ) -> crate::common::RegisterField<
3057        14,
3058        0x3,
3059        1,
3060        0,
3061        scr02::Trxe,
3062        scr02::Trxe,
3063        Scr02_SPEC,
3064        crate::common::RW,
3065    > {
3066        crate::common::RegisterField::<
3067            14,
3068            0x3,
3069            1,
3070            0,
3071            scr02::Trxe,
3072            scr02::Trxe,
3073            Scr02_SPEC,
3074            crate::common::RW,
3075        >::from_register(self, 0)
3076    }
3077}
3078impl ::core::default::Default for Scr02 {
3079    #[inline(always)]
3080    fn default() -> Scr02 {
3081        <crate::RegValueT<Scr02_SPEC> as RegisterValue<_>>::new(135)
3082    }
3083}
3084pub mod scr02 {
3085
3086    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3087    pub struct Dls_SPEC;
3088    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
3089    impl Dls {
3090        #[doc = "7-bit data length (stored in the DAT\\[6:0\\] bits of the SDR02 register)"]
3091        pub const _0: Self = Self::new(0);
3092
3093        #[doc = "8-bit data length (stored in the DAT\\[7:0\\] bits of the SDR02 register)"]
3094        pub const _1: Self = Self::new(1);
3095    }
3096    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3097    pub struct Slc_SPEC;
3098    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
3099    impl Slc {
3100        #[doc = "No stop bit"]
3101        pub const _00: Self = Self::new(0);
3102
3103        #[doc = "Stop bit length = 1 bit"]
3104        pub const _01: Self = Self::new(1);
3105
3106        #[doc = "Stop bit length = 2 bits"]
3107        pub const _10: Self = Self::new(2);
3108
3109        #[doc = "Setting prohibited"]
3110        pub const _11: Self = Self::new(3);
3111    }
3112    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3113    pub struct Dir_SPEC;
3114    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
3115    impl Dir {
3116        #[doc = "Inputs or outputs data with MSB first"]
3117        pub const _0: Self = Self::new(0);
3118
3119        #[doc = "Inputs or outputs data with LSB first"]
3120        pub const _1: Self = Self::new(1);
3121    }
3122    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3123    pub struct Ptc_SPEC;
3124    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
3125    impl Ptc {
3126        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
3127        pub const _00: Self = Self::new(0);
3128
3129        #[doc = "Transmission: Outputs 0 parity Reception: No parity judgment"]
3130        pub const _01: Self = Self::new(1);
3131
3132        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
3133        pub const _10: Self = Self::new(2);
3134
3135        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
3136        pub const _11: Self = Self::new(3);
3137    }
3138    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3139    pub struct Dcp_SPEC;
3140    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
3141    impl Dcp {
3142        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
3143        pub const _00: Self = Self::new(0);
3144
3145        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
3146        pub const _01: Self = Self::new(1);
3147
3148        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
3149        pub const _10: Self = Self::new(2);
3150
3151        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
3152        pub const _11: Self = Self::new(3);
3153    }
3154    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3155    pub struct Trxe_SPEC;
3156    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
3157    impl Trxe {
3158        #[doc = "Disables communication"]
3159        pub const _00: Self = Self::new(0);
3160
3161        #[doc = "Reception only"]
3162        pub const _01: Self = Self::new(1);
3163
3164        #[doc = "Transmission only"]
3165        pub const _10: Self = Self::new(2);
3166
3167        #[doc = "Transmission and reception"]
3168        pub const _11: Self = Self::new(3);
3169    }
3170}
3171#[doc(hidden)]
3172#[derive(Copy, Clone, Eq, PartialEq)]
3173pub struct Scr03_SPEC;
3174impl crate::sealed::RegSpec for Scr03_SPEC {
3175    type DataType = u16;
3176}
3177
3178#[doc = "Serial Communication Operation Setting Register 03"]
3179pub type Scr03 = crate::RegValueT<Scr03_SPEC>;
3180
3181impl Scr03 {
3182    #[doc = "Setting of Data Length in Simplified SPI and UART Modes"]
3183    #[inline(always)]
3184    pub fn dls(
3185        self,
3186    ) -> crate::common::RegisterField<
3187        0,
3188        0x1,
3189        1,
3190        0,
3191        scr03::Dls,
3192        scr03::Dls,
3193        Scr03_SPEC,
3194        crate::common::RW,
3195    > {
3196        crate::common::RegisterField::<
3197            0,
3198            0x1,
3199            1,
3200            0,
3201            scr03::Dls,
3202            scr03::Dls,
3203            Scr03_SPEC,
3204            crate::common::RW,
3205        >::from_register(self, 0)
3206    }
3207
3208    #[doc = "Setting of Stop Bit in UART Mode"]
3209    #[inline(always)]
3210    pub fn slc(
3211        self,
3212    ) -> crate::common::RegisterField<
3213        4,
3214        0x1,
3215        1,
3216        0,
3217        scr03::Slc,
3218        scr03::Slc,
3219        Scr03_SPEC,
3220        crate::common::RW,
3221    > {
3222        crate::common::RegisterField::<
3223            4,
3224            0x1,
3225            1,
3226            0,
3227            scr03::Slc,
3228            scr03::Slc,
3229            Scr03_SPEC,
3230            crate::common::RW,
3231        >::from_register(self, 0)
3232    }
3233
3234    #[doc = "Selection of Data Transfer Sequence in Simplified SPI and UART Modes"]
3235    #[inline(always)]
3236    pub fn dir(
3237        self,
3238    ) -> crate::common::RegisterField<
3239        7,
3240        0x1,
3241        1,
3242        0,
3243        scr03::Dir,
3244        scr03::Dir,
3245        Scr03_SPEC,
3246        crate::common::RW,
3247    > {
3248        crate::common::RegisterField::<
3249            7,
3250            0x1,
3251            1,
3252            0,
3253            scr03::Dir,
3254            scr03::Dir,
3255            Scr03_SPEC,
3256            crate::common::RW,
3257        >::from_register(self, 0)
3258    }
3259
3260    #[doc = "Setting of Parity Bit in UART Mode"]
3261    #[inline(always)]
3262    pub fn ptc(
3263        self,
3264    ) -> crate::common::RegisterField<
3265        8,
3266        0x3,
3267        1,
3268        0,
3269        scr03::Ptc,
3270        scr03::Ptc,
3271        Scr03_SPEC,
3272        crate::common::RW,
3273    > {
3274        crate::common::RegisterField::<
3275            8,
3276            0x3,
3277            1,
3278            0,
3279            scr03::Ptc,
3280            scr03::Ptc,
3281            Scr03_SPEC,
3282            crate::common::RW,
3283        >::from_register(self, 0)
3284    }
3285
3286    #[doc = "Mask Control of Error Interrupt Signal SAU0_UART_ERRI1"]
3287    #[inline(always)]
3288    pub fn eoc(
3289        self,
3290    ) -> crate::common::RegisterField<
3291        10,
3292        0x1,
3293        1,
3294        0,
3295        scr03::Eoc,
3296        scr03::Eoc,
3297        Scr03_SPEC,
3298        crate::common::RW,
3299    > {
3300        crate::common::RegisterField::<
3301            10,
3302            0x1,
3303            1,
3304            0,
3305            scr03::Eoc,
3306            scr03::Eoc,
3307            Scr03_SPEC,
3308            crate::common::RW,
3309        >::from_register(self, 0)
3310    }
3311
3312    #[doc = "Selection of Data and Clock Phase in Simplified SPI Mode"]
3313    #[inline(always)]
3314    pub fn dcp(
3315        self,
3316    ) -> crate::common::RegisterField<
3317        12,
3318        0x3,
3319        1,
3320        0,
3321        scr03::Dcp,
3322        scr03::Dcp,
3323        Scr03_SPEC,
3324        crate::common::RW,
3325    > {
3326        crate::common::RegisterField::<
3327            12,
3328            0x3,
3329            1,
3330            0,
3331            scr03::Dcp,
3332            scr03::Dcp,
3333            Scr03_SPEC,
3334            crate::common::RW,
3335        >::from_register(self, 0)
3336    }
3337
3338    #[doc = "Setting of Operation Mode of Channel 3"]
3339    #[inline(always)]
3340    pub fn trxe(
3341        self,
3342    ) -> crate::common::RegisterField<
3343        14,
3344        0x3,
3345        1,
3346        0,
3347        scr03::Trxe,
3348        scr03::Trxe,
3349        Scr03_SPEC,
3350        crate::common::RW,
3351    > {
3352        crate::common::RegisterField::<
3353            14,
3354            0x3,
3355            1,
3356            0,
3357            scr03::Trxe,
3358            scr03::Trxe,
3359            Scr03_SPEC,
3360            crate::common::RW,
3361        >::from_register(self, 0)
3362    }
3363}
3364impl ::core::default::Default for Scr03 {
3365    #[inline(always)]
3366    fn default() -> Scr03 {
3367        <crate::RegValueT<Scr03_SPEC> as RegisterValue<_>>::new(135)
3368    }
3369}
3370pub mod scr03 {
3371
3372    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3373    pub struct Dls_SPEC;
3374    pub type Dls = crate::EnumBitfieldStruct<u8, Dls_SPEC>;
3375    impl Dls {
3376        #[doc = "7-bit data length (stored in the DAT\\[6:0\\] bits of the SDR03 register)"]
3377        pub const _0: Self = Self::new(0);
3378
3379        #[doc = "8-bit data length (stored in the DAT\\[7:0\\] bits of the SDR03 register)"]
3380        pub const _1: Self = Self::new(1);
3381    }
3382    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3383    pub struct Slc_SPEC;
3384    pub type Slc = crate::EnumBitfieldStruct<u8, Slc_SPEC>;
3385    impl Slc {
3386        #[doc = "No stop bit"]
3387        pub const _0: Self = Self::new(0);
3388
3389        #[doc = "Stop bit length = 1 bit"]
3390        pub const _1: Self = Self::new(1);
3391    }
3392    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3393    pub struct Dir_SPEC;
3394    pub type Dir = crate::EnumBitfieldStruct<u8, Dir_SPEC>;
3395    impl Dir {
3396        #[doc = "Inputs or outputs data with MSB first"]
3397        pub const _0: Self = Self::new(0);
3398
3399        #[doc = "Inputs or outputs data with LSB first"]
3400        pub const _1: Self = Self::new(1);
3401    }
3402    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3403    pub struct Ptc_SPEC;
3404    pub type Ptc = crate::EnumBitfieldStruct<u8, Ptc_SPEC>;
3405    impl Ptc {
3406        #[doc = "Transmission: Does not output the parity bit Reception: Receives without parity"]
3407        pub const _00: Self = Self::new(0);
3408
3409        #[doc = "Transmission: Outputs 0 parity Reception: No parity determination"]
3410        pub const _01: Self = Self::new(1);
3411
3412        #[doc = "Transmission: Outputs even parity Reception: Determines as even parity"]
3413        pub const _10: Self = Self::new(2);
3414
3415        #[doc = "Transmission: Outputs odd parity Reception: Determines as odd parity"]
3416        pub const _11: Self = Self::new(3);
3417    }
3418    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3419    pub struct Eoc_SPEC;
3420    pub type Eoc = crate::EnumBitfieldStruct<u8, Eoc_SPEC>;
3421    impl Eoc {
3422        #[doc = "Disables generation of error interrupt SAU0_UART_ERRI1 (SAU0_UART_RXI1 is generated)"]
3423        pub const _0: Self = Self::new(0);
3424
3425        #[doc = "Enables generation of error interrupt SAU0_UART_ERRI1 (SAU0_UART_RXI1 is not generated if an error occurs)"]
3426        pub const _1: Self = Self::new(1);
3427    }
3428    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3429    pub struct Dcp_SPEC;
3430    pub type Dcp = crate::EnumBitfieldStruct<u8, Dcp_SPEC>;
3431    impl Dcp {
3432        #[doc = "Type1 (SCK: inverted, Input timing: rising edge)"]
3433        pub const _00: Self = Self::new(0);
3434
3435        #[doc = "Type2 (SCK: non-inverted, Input timing: falling edge)"]
3436        pub const _01: Self = Self::new(1);
3437
3438        #[doc = "Type3 (SCK: inverted, Input timing: falling edge)"]
3439        pub const _10: Self = Self::new(2);
3440
3441        #[doc = "Type4 (SCK: non-inverted, Input timing: rising edge)"]
3442        pub const _11: Self = Self::new(3);
3443    }
3444    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3445    pub struct Trxe_SPEC;
3446    pub type Trxe = crate::EnumBitfieldStruct<u8, Trxe_SPEC>;
3447    impl Trxe {
3448        #[doc = "Disable communication"]
3449        pub const _00: Self = Self::new(0);
3450
3451        #[doc = "Reception only"]
3452        pub const _01: Self = Self::new(1);
3453
3454        #[doc = "Transmission only"]
3455        pub const _10: Self = Self::new(2);
3456
3457        #[doc = "Transmission and reception"]
3458        pub const _11: Self = Self::new(3);
3459    }
3460}
3461#[doc(hidden)]
3462#[derive(Copy, Clone, Eq, PartialEq)]
3463pub struct Se0_SPEC;
3464impl crate::sealed::RegSpec for Se0_SPEC {
3465    type DataType = u16;
3466}
3467
3468#[doc = "Serial Channel Enable Status Register 0"]
3469pub type Se0 = crate::RegValueT<Se0_SPEC>;
3470
3471impl Se0 {
3472    #[doc = "Indication of whether Operation of Channel n is Enabled or Stopped."]
3473    #[inline(always)]
3474    pub fn se(
3475        self,
3476    ) -> crate::common::RegisterField<0, 0xf, 1, 0, se0::Se, se0::Se, Se0_SPEC, crate::common::R>
3477    {
3478        crate::common::RegisterField::<0,0xf,1,0,se0::Se,se0::Se,Se0_SPEC,crate::common::R>::from_register(self,0)
3479    }
3480}
3481impl ::core::default::Default for Se0 {
3482    #[inline(always)]
3483    fn default() -> Se0 {
3484        <crate::RegValueT<Se0_SPEC> as RegisterValue<_>>::new(0)
3485    }
3486}
3487pub mod se0 {
3488
3489    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3490    pub struct Se_SPEC;
3491    pub type Se = crate::EnumBitfieldStruct<u8, Se_SPEC>;
3492    impl Se {
3493        #[doc = "Operation stops"]
3494        pub const _0: Self = Self::new(0);
3495
3496        #[doc = "Operation is enabled"]
3497        pub const _1: Self = Self::new(1);
3498    }
3499}
3500#[doc(hidden)]
3501#[derive(Copy, Clone, Eq, PartialEq)]
3502pub struct Ss0_SPEC;
3503impl crate::sealed::RegSpec for Ss0_SPEC {
3504    type DataType = u16;
3505}
3506
3507#[doc = "Serial Channel Start Register 0"]
3508pub type Ss0 = crate::RegValueT<Ss0_SPEC>;
3509
3510impl Ss0 {
3511    #[doc = "Operation Start Trigger of Channel n"]
3512    #[inline(always)]
3513    pub fn ss(
3514        self,
3515    ) -> crate::common::RegisterField<0, 0xf, 1, 0, ss0::Ss, ss0::Ss, Ss0_SPEC, crate::common::RW>
3516    {
3517        crate::common::RegisterField::<0,0xf,1,0,ss0::Ss,ss0::Ss,Ss0_SPEC,crate::common::RW>::from_register(self,0)
3518    }
3519}
3520impl ::core::default::Default for Ss0 {
3521    #[inline(always)]
3522    fn default() -> Ss0 {
3523        <crate::RegValueT<Ss0_SPEC> as RegisterValue<_>>::new(0)
3524    }
3525}
3526pub mod ss0 {
3527
3528    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3529    pub struct Ss_SPEC;
3530    pub type Ss = crate::EnumBitfieldStruct<u8, Ss_SPEC>;
3531    impl Ss {
3532        #[doc = "No trigger operation"]
3533        pub const _0: Self = Self::new(0);
3534
3535        #[doc = "Set the SE0.SE\\[n\\] bit to 1 to place the channel in communications waiting state"]
3536        pub const _1: Self = Self::new(1);
3537    }
3538}
3539#[doc(hidden)]
3540#[derive(Copy, Clone, Eq, PartialEq)]
3541pub struct St0_SPEC;
3542impl crate::sealed::RegSpec for St0_SPEC {
3543    type DataType = u16;
3544}
3545
3546#[doc = "Serial Channel Stop Register 0"]
3547pub type St0 = crate::RegValueT<St0_SPEC>;
3548
3549impl St0 {
3550    #[doc = "Operation Stop Trigger of Channel n"]
3551    #[inline(always)]
3552    pub fn st(
3553        self,
3554    ) -> crate::common::RegisterField<0, 0xf, 1, 0, st0::St, st0::St, St0_SPEC, crate::common::RW>
3555    {
3556        crate::common::RegisterField::<0,0xf,1,0,st0::St,st0::St,St0_SPEC,crate::common::RW>::from_register(self,0)
3557    }
3558}
3559impl ::core::default::Default for St0 {
3560    #[inline(always)]
3561    fn default() -> St0 {
3562        <crate::RegValueT<St0_SPEC> as RegisterValue<_>>::new(0)
3563    }
3564}
3565pub mod st0 {
3566
3567    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3568    pub struct St_SPEC;
3569    pub type St = crate::EnumBitfieldStruct<u8, St_SPEC>;
3570    impl St {
3571        #[doc = "No trigger operation"]
3572        pub const _0: Self = Self::new(0);
3573
3574        #[doc = "Clears the SE0.SE\\[n\\] bit to 0 and stops the communication operation"]
3575        pub const _1: Self = Self::new(1);
3576    }
3577}
3578#[doc(hidden)]
3579#[derive(Copy, Clone, Eq, PartialEq)]
3580pub struct Sps0_SPEC;
3581impl crate::sealed::RegSpec for Sps0_SPEC {
3582    type DataType = u16;
3583}
3584
3585#[doc = "Serial Clock Select Register 0"]
3586pub type Sps0 = crate::RegValueT<Sps0_SPEC>;
3587
3588impl Sps0 {
3589    #[doc = "Selection of Operation Clock (CKm0)"]
3590    #[inline(always)]
3591    pub fn prs0(
3592        self,
3593    ) -> crate::common::RegisterField<
3594        0,
3595        0xf,
3596        1,
3597        0,
3598        sps0::Prs0,
3599        sps0::Prs0,
3600        Sps0_SPEC,
3601        crate::common::RW,
3602    > {
3603        crate::common::RegisterField::<
3604            0,
3605            0xf,
3606            1,
3607            0,
3608            sps0::Prs0,
3609            sps0::Prs0,
3610            Sps0_SPEC,
3611            crate::common::RW,
3612        >::from_register(self, 0)
3613    }
3614
3615    #[doc = "Selection of Operation Clock (CKm1)"]
3616    #[inline(always)]
3617    pub fn prs1(
3618        self,
3619    ) -> crate::common::RegisterField<
3620        4,
3621        0xf,
3622        1,
3623        0,
3624        sps0::Prs1,
3625        sps0::Prs1,
3626        Sps0_SPEC,
3627        crate::common::RW,
3628    > {
3629        crate::common::RegisterField::<
3630            4,
3631            0xf,
3632            1,
3633            0,
3634            sps0::Prs1,
3635            sps0::Prs1,
3636            Sps0_SPEC,
3637            crate::common::RW,
3638        >::from_register(self, 0)
3639    }
3640}
3641impl ::core::default::Default for Sps0 {
3642    #[inline(always)]
3643    fn default() -> Sps0 {
3644        <crate::RegValueT<Sps0_SPEC> as RegisterValue<_>>::new(0)
3645    }
3646}
3647pub mod sps0 {
3648
3649    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3650    pub struct Prs0_SPEC;
3651    pub type Prs0 = crate::EnumBitfieldStruct<u8, Prs0_SPEC>;
3652    impl Prs0 {
3653        #[doc = "PCLKB"]
3654        pub const _0_X_0: Self = Self::new(0);
3655
3656        #[doc = "PCLKB/2"]
3657        pub const _0_X_1: Self = Self::new(1);
3658
3659        #[doc = "PCLKB/22"]
3660        pub const _0_X_2: Self = Self::new(2);
3661
3662        #[doc = "PCLKB/23"]
3663        pub const _0_X_3: Self = Self::new(3);
3664
3665        #[doc = "PCLKB/24"]
3666        pub const _0_X_4: Self = Self::new(4);
3667
3668        #[doc = "PCLKB/25"]
3669        pub const _0_X_5: Self = Self::new(5);
3670
3671        #[doc = "PCLKB/26"]
3672        pub const _0_X_6: Self = Self::new(6);
3673
3674        #[doc = "PCLKB/27"]
3675        pub const _0_X_7: Self = Self::new(7);
3676
3677        #[doc = "PCLKB/28"]
3678        pub const _0_X_8: Self = Self::new(8);
3679
3680        #[doc = "PCLKB/29"]
3681        pub const _0_X_9: Self = Self::new(9);
3682
3683        #[doc = "PCLKB/210"]
3684        pub const _0_X_A: Self = Self::new(10);
3685
3686        #[doc = "PCLKB/211"]
3687        pub const _0_X_B: Self = Self::new(11);
3688
3689        #[doc = "PCLKB/212"]
3690        pub const _0_X_C: Self = Self::new(12);
3691
3692        #[doc = "PCLKB/213"]
3693        pub const _0_X_D: Self = Self::new(13);
3694
3695        #[doc = "PCLKB/214"]
3696        pub const _0_X_E: Self = Self::new(14);
3697
3698        #[doc = "PCLKB/215"]
3699        pub const _0_X_F: Self = Self::new(15);
3700    }
3701    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3702    pub struct Prs1_SPEC;
3703    pub type Prs1 = crate::EnumBitfieldStruct<u8, Prs1_SPEC>;
3704    impl Prs1 {
3705        #[doc = "PCLKB"]
3706        pub const _0_X_0: Self = Self::new(0);
3707
3708        #[doc = "PCLKB/2"]
3709        pub const _0_X_1: Self = Self::new(1);
3710
3711        #[doc = "PCLKB/22"]
3712        pub const _0_X_2: Self = Self::new(2);
3713
3714        #[doc = "PCLKB/23"]
3715        pub const _0_X_3: Self = Self::new(3);
3716
3717        #[doc = "PCLKB/24"]
3718        pub const _0_X_4: Self = Self::new(4);
3719
3720        #[doc = "PCLKB/25"]
3721        pub const _0_X_5: Self = Self::new(5);
3722
3723        #[doc = "PCLKB/26"]
3724        pub const _0_X_6: Self = Self::new(6);
3725
3726        #[doc = "PCLKB/27"]
3727        pub const _0_X_7: Self = Self::new(7);
3728
3729        #[doc = "PCLKB/28"]
3730        pub const _0_X_8: Self = Self::new(8);
3731
3732        #[doc = "PCLKB/29"]
3733        pub const _0_X_9: Self = Self::new(9);
3734
3735        #[doc = "PCLKB/210"]
3736        pub const _0_X_A: Self = Self::new(10);
3737
3738        #[doc = "PCLKB/211"]
3739        pub const _0_X_B: Self = Self::new(11);
3740
3741        #[doc = "PCLKB/212"]
3742        pub const _0_X_C: Self = Self::new(12);
3743
3744        #[doc = "PCLKB/213"]
3745        pub const _0_X_D: Self = Self::new(13);
3746
3747        #[doc = "PCLKB/214"]
3748        pub const _0_X_E: Self = Self::new(14);
3749
3750        #[doc = "PCLKB/215"]
3751        pub const _0_X_F: Self = Self::new(15);
3752    }
3753}
3754#[doc(hidden)]
3755#[derive(Copy, Clone, Eq, PartialEq)]
3756pub struct So0_SPEC;
3757impl crate::sealed::RegSpec for So0_SPEC {
3758    type DataType = u16;
3759}
3760
3761#[doc = "Serial Output Register 0"]
3762pub type So0 = crate::RegValueT<So0_SPEC>;
3763
3764impl So0 {
3765    #[doc = "Serial Data Output of Channel n"]
3766    #[inline(always)]
3767    pub fn so(
3768        self,
3769    ) -> crate::common::RegisterField<0, 0xf, 1, 0, so0::So, so0::So, So0_SPEC, crate::common::RW>
3770    {
3771        crate::common::RegisterField::<0,0xf,1,0,so0::So,so0::So,So0_SPEC,crate::common::RW>::from_register(self,0)
3772    }
3773
3774    #[doc = "Serial Clock Output of Channel n"]
3775    #[inline(always)]
3776    pub fn cko(
3777        self,
3778    ) -> crate::common::RegisterField<8, 0xf, 1, 0, so0::Cko, so0::Cko, So0_SPEC, crate::common::RW>
3779    {
3780        crate::common::RegisterField::<8,0xf,1,0,so0::Cko,so0::Cko,So0_SPEC,crate::common::RW>::from_register(self,0)
3781    }
3782}
3783impl ::core::default::Default for So0 {
3784    #[inline(always)]
3785    fn default() -> So0 {
3786        <crate::RegValueT<So0_SPEC> as RegisterValue<_>>::new(3855)
3787    }
3788}
3789pub mod so0 {
3790
3791    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3792    pub struct So_SPEC;
3793    pub type So = crate::EnumBitfieldStruct<u8, So_SPEC>;
3794    impl So {
3795        #[doc = "Serial data output value is 0"]
3796        pub const _0: Self = Self::new(0);
3797
3798        #[doc = "Serial data output value is 1"]
3799        pub const _1: Self = Self::new(1);
3800    }
3801    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3802    pub struct Cko_SPEC;
3803    pub type Cko = crate::EnumBitfieldStruct<u8, Cko_SPEC>;
3804    impl Cko {
3805        #[doc = "Serial clock output value is 0"]
3806        pub const _0: Self = Self::new(0);
3807
3808        #[doc = "Serial clock output value is 1"]
3809        pub const _1: Self = Self::new(1);
3810    }
3811}
3812#[doc(hidden)]
3813#[derive(Copy, Clone, Eq, PartialEq)]
3814pub struct Soe0_SPEC;
3815impl crate::sealed::RegSpec for Soe0_SPEC {
3816    type DataType = u16;
3817}
3818
3819#[doc = "Serial Output Enable Register 0"]
3820pub type Soe0 = crate::RegValueT<Soe0_SPEC>;
3821
3822impl Soe0 {
3823    #[doc = "Serial Output Enable or Stop of Channel n"]
3824    #[inline(always)]
3825    pub fn soe(
3826        self,
3827    ) -> crate::common::RegisterField<
3828        0,
3829        0xf,
3830        1,
3831        0,
3832        soe0::Soe,
3833        soe0::Soe,
3834        Soe0_SPEC,
3835        crate::common::RW,
3836    > {
3837        crate::common::RegisterField::<
3838            0,
3839            0xf,
3840            1,
3841            0,
3842            soe0::Soe,
3843            soe0::Soe,
3844            Soe0_SPEC,
3845            crate::common::RW,
3846        >::from_register(self, 0)
3847    }
3848}
3849impl ::core::default::Default for Soe0 {
3850    #[inline(always)]
3851    fn default() -> Soe0 {
3852        <crate::RegValueT<Soe0_SPEC> as RegisterValue<_>>::new(0)
3853    }
3854}
3855pub mod soe0 {
3856
3857    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3858    pub struct Soe_SPEC;
3859    pub type Soe = crate::EnumBitfieldStruct<u8, Soe_SPEC>;
3860    impl Soe {
3861        #[doc = "Stops output by serial communication operation"]
3862        pub const _0: Self = Self::new(0);
3863
3864        #[doc = "Enables output by serial communication operation"]
3865        pub const _1: Self = Self::new(1);
3866    }
3867}
3868#[doc(hidden)]
3869#[derive(Copy, Clone, Eq, PartialEq)]
3870pub struct Sol0_SPEC;
3871impl crate::sealed::RegSpec for Sol0_SPEC {
3872    type DataType = u16;
3873}
3874
3875#[doc = "Serial Output Level Register 0"]
3876pub type Sol0 = crate::RegValueT<Sol0_SPEC>;
3877
3878impl Sol0 {
3879    #[doc = "Selects Inversion of the Level of the Transmit Data of Channel 0 in UART Mode"]
3880    #[inline(always)]
3881    pub fn sol0(
3882        self,
3883    ) -> crate::common::RegisterField<
3884        0,
3885        0x1,
3886        1,
3887        0,
3888        sol0::Sol0,
3889        sol0::Sol0,
3890        Sol0_SPEC,
3891        crate::common::RW,
3892    > {
3893        crate::common::RegisterField::<
3894            0,
3895            0x1,
3896            1,
3897            0,
3898            sol0::Sol0,
3899            sol0::Sol0,
3900            Sol0_SPEC,
3901            crate::common::RW,
3902        >::from_register(self, 0)
3903    }
3904
3905    #[doc = "Selects Inversion of the Level of the Transmit Data of Channel 2 in UART Mode"]
3906    #[inline(always)]
3907    pub fn sol2(
3908        self,
3909    ) -> crate::common::RegisterField<
3910        2,
3911        0x1,
3912        1,
3913        0,
3914        sol0::Sol2,
3915        sol0::Sol2,
3916        Sol0_SPEC,
3917        crate::common::RW,
3918    > {
3919        crate::common::RegisterField::<
3920            2,
3921            0x1,
3922            1,
3923            0,
3924            sol0::Sol2,
3925            sol0::Sol2,
3926            Sol0_SPEC,
3927            crate::common::RW,
3928        >::from_register(self, 0)
3929    }
3930}
3931impl ::core::default::Default for Sol0 {
3932    #[inline(always)]
3933    fn default() -> Sol0 {
3934        <crate::RegValueT<Sol0_SPEC> as RegisterValue<_>>::new(0)
3935    }
3936}
3937pub mod sol0 {
3938
3939    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3940    pub struct Sol0_SPEC;
3941    pub type Sol0 = crate::EnumBitfieldStruct<u8, Sol0_SPEC>;
3942    impl Sol0 {
3943        #[doc = "Communication data is output as is"]
3944        pub const _0: Self = Self::new(0);
3945
3946        #[doc = "Communication data is inverted and output"]
3947        pub const _1: Self = Self::new(1);
3948    }
3949    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
3950    pub struct Sol2_SPEC;
3951    pub type Sol2 = crate::EnumBitfieldStruct<u8, Sol2_SPEC>;
3952    impl Sol2 {
3953        #[doc = "Communication data is output as is"]
3954        pub const _0: Self = Self::new(0);
3955
3956        #[doc = "Communication data is inverted and output"]
3957        pub const _1: Self = Self::new(1);
3958    }
3959}
3960#[doc(hidden)]
3961#[derive(Copy, Clone, Eq, PartialEq)]
3962pub struct Ssc0_SPEC;
3963impl crate::sealed::RegSpec for Ssc0_SPEC {
3964    type DataType = u16;
3965}
3966
3967#[doc = "Serial Standby Control Register 0"]
3968pub type Ssc0 = crate::RegValueT<Ssc0_SPEC>;
3969
3970impl Ssc0 {
3971    #[doc = "Setting of the Snooze Mode"]
3972    #[inline(always)]
3973    pub fn swc(
3974        self,
3975    ) -> crate::common::RegisterField<
3976        0,
3977        0x1,
3978        1,
3979        0,
3980        ssc0::Swc,
3981        ssc0::Swc,
3982        Ssc0_SPEC,
3983        crate::common::RW,
3984    > {
3985        crate::common::RegisterField::<
3986            0,
3987            0x1,
3988            1,
3989            0,
3990            ssc0::Swc,
3991            ssc0::Swc,
3992            Ssc0_SPEC,
3993            crate::common::RW,
3994        >::from_register(self, 0)
3995    }
3996
3997    #[doc = "Selection of whether to Enable or Disable the Generation of Communication Error Interrupts in the Snooze Mode"]
3998    #[inline(always)]
3999    pub fn ssec(
4000        self,
4001    ) -> crate::common::RegisterField<
4002        1,
4003        0x1,
4004        1,
4005        0,
4006        ssc0::Ssec,
4007        ssc0::Ssec,
4008        Ssc0_SPEC,
4009        crate::common::RW,
4010    > {
4011        crate::common::RegisterField::<
4012            1,
4013            0x1,
4014            1,
4015            0,
4016            ssc0::Ssec,
4017            ssc0::Ssec,
4018            Ssc0_SPEC,
4019            crate::common::RW,
4020        >::from_register(self, 0)
4021    }
4022}
4023impl ::core::default::Default for Ssc0 {
4024    #[inline(always)]
4025    fn default() -> Ssc0 {
4026        <crate::RegValueT<Ssc0_SPEC> as RegisterValue<_>>::new(0)
4027    }
4028}
4029pub mod ssc0 {
4030
4031    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4032    pub struct Swc_SPEC;
4033    pub type Swc = crate::EnumBitfieldStruct<u8, Swc_SPEC>;
4034    impl Swc {
4035        #[doc = "Do not use the Snooze mode function"]
4036        pub const _0: Self = Self::new(0);
4037
4038        #[doc = "Use the Snooze mode function"]
4039        pub const _1: Self = Self::new(1);
4040    }
4041    #[derive(Clone, Copy, Eq, PartialEq, Ord, PartialOrd)]
4042    pub struct Ssec_SPEC;
4043    pub type Ssec = crate::EnumBitfieldStruct<u8, Ssec_SPEC>;
4044    impl Ssec {
4045        #[doc = "Enable the generation of error interrupts SAU0_UART_ERRI0"]
4046        pub const _0: Self = Self::new(0);
4047
4048        #[doc = "Disable the generation of error interrupts SAU0_UART_ERRI0"]
4049        pub const _1: Self = Self::new(1);
4050    }
4051}
ra0e1_pac/sau0.rs

ra0e1_pac/
sau0.rs
